diff options
author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233 | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233')
138 files changed, 41995 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-apbh.h b/firmware/target/arm/imx233/regs/imx233/regs-apbh.h new file mode 100644 index 0000000000..bef0b82d78 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-apbh.h | |||
@@ -0,0 +1,355 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__APBH__H__ | ||
24 | #define __HEADERGEN__IMX233__APBH__H__ | ||
25 | |||
26 | #define REGS_APBH_BASE (0x80004000) | ||
27 | |||
28 | #define REGS_APBH_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_APBH_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_APBH_CTRL0 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0)) | ||
36 | #define HW_APBH_CTRL0_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4)) | ||
37 | #define HW_APBH_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8)) | ||
38 | #define HW_APBH_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc)) | ||
39 | #define BP_APBH_CTRL0_SFTRST 31 | ||
40 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_APBH_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_APBH_CTRL0_CLKGATE 30 | ||
43 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_APBH_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_APBH_CTRL0_AHB_BURST8_EN 29 | ||
46 | #define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 | ||
47 | #define BF_APBH_CTRL0_AHB_BURST8_EN(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_APBH_CTRL0_APB_BURST4_EN 28 | ||
49 | #define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000 | ||
50 | #define BF_APBH_CTRL0_APB_BURST4_EN(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_APBH_CTRL0_RSVD0 24 | ||
52 | #define BM_APBH_CTRL0_RSVD0 0xf000000 | ||
53 | #define BF_APBH_CTRL0_RSVD0(v) (((v) << 24) & 0xf000000) | ||
54 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
55 | #define BM_APBH_CTRL0_RESET_CHANNEL 0xff0000 | ||
56 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP1 0x2 | ||
57 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP2 0x4 | ||
58 | #define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 | ||
59 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 | ||
60 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 | ||
61 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x40 | ||
62 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x80 | ||
63 | #define BF_APBH_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
64 | #define BF_APBH_CTRL0_RESET_CHANNEL_V(v) ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
65 | #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 | ||
66 | #define BM_APBH_CTRL0_CLKGATE_CHANNEL 0xff00 | ||
67 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x2 | ||
68 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x4 | ||
69 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 | ||
70 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 | ||
71 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 | ||
72 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x40 | ||
73 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x80 | ||
74 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) << 8) & 0xff00) | ||
75 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v) ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00) | ||
76 | #define BP_APBH_CTRL0_FREEZE_CHANNEL 0 | ||
77 | #define BM_APBH_CTRL0_FREEZE_CHANNEL 0xff | ||
78 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1 0x2 | ||
79 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2 0x4 | ||
80 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 | ||
81 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 | ||
82 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 | ||
83 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x40 | ||
84 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x80 | ||
85 | #define BF_APBH_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
86 | #define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
87 | |||
88 | /** | ||
89 | * Register: HW_APBH_CTRL1 | ||
90 | * Address: 0x10 | ||
91 | * SCT: yes | ||
92 | */ | ||
93 | #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0)) | ||
94 | #define HW_APBH_CTRL1_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4)) | ||
95 | #define HW_APBH_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8)) | ||
96 | #define HW_APBH_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc)) | ||
97 | #define BP_APBH_CTRL1_RSVD1 24 | ||
98 | #define BM_APBH_CTRL1_RSVD1 0xff000000 | ||
99 | #define BF_APBH_CTRL1_RSVD1(v) (((v) << 24) & 0xff000000) | ||
100 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 16 | ||
101 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff0000 | ||
102 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000) | ||
103 | #define BP_APBH_CTRL1_RSVD0 8 | ||
104 | #define BM_APBH_CTRL1_RSVD0 0xff00 | ||
105 | #define BF_APBH_CTRL1_RSVD0(v) (((v) << 8) & 0xff00) | ||
106 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
107 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
108 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
109 | |||
110 | /** | ||
111 | * Register: HW_APBH_CTRL2 | ||
112 | * Address: 0x20 | ||
113 | * SCT: yes | ||
114 | */ | ||
115 | #define HW_APBH_CTRL2 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x0)) | ||
116 | #define HW_APBH_CTRL2_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x4)) | ||
117 | #define HW_APBH_CTRL2_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x8)) | ||
118 | #define HW_APBH_CTRL2_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0xc)) | ||
119 | #define BP_APBH_CTRL2_RSVD1 24 | ||
120 | #define BM_APBH_CTRL2_RSVD1 0xff000000 | ||
121 | #define BF_APBH_CTRL2_RSVD1(v) (((v) << 24) & 0xff000000) | ||
122 | #define BP_APBH_CTRL2_CH_ERROR_STATUS 16 | ||
123 | #define BM_APBH_CTRL2_CH_ERROR_STATUS 0xff0000 | ||
124 | #define BF_APBH_CTRL2_CH_ERROR_STATUS(v) (((v) << 16) & 0xff0000) | ||
125 | #define BP_APBH_CTRL2_RSVD0 8 | ||
126 | #define BM_APBH_CTRL2_RSVD0 0xff00 | ||
127 | #define BF_APBH_CTRL2_RSVD0(v) (((v) << 8) & 0xff00) | ||
128 | #define BP_APBH_CTRL2_CH_ERROR_IRQ 0 | ||
129 | #define BM_APBH_CTRL2_CH_ERROR_IRQ 0xff | ||
130 | #define BF_APBH_CTRL2_CH_ERROR_IRQ(v) (((v) << 0) & 0xff) | ||
131 | |||
132 | /** | ||
133 | * Register: HW_APBH_DEVSEL | ||
134 | * Address: 0x30 | ||
135 | * SCT: no | ||
136 | */ | ||
137 | #define HW_APBH_DEVSEL (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30)) | ||
138 | #define BP_APBH_DEVSEL_CH7 28 | ||
139 | #define BM_APBH_DEVSEL_CH7 0xf0000000 | ||
140 | #define BF_APBH_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
141 | #define BP_APBH_DEVSEL_CH6 24 | ||
142 | #define BM_APBH_DEVSEL_CH6 0xf000000 | ||
143 | #define BF_APBH_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
144 | #define BP_APBH_DEVSEL_CH5 20 | ||
145 | #define BM_APBH_DEVSEL_CH5 0xf00000 | ||
146 | #define BF_APBH_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
147 | #define BP_APBH_DEVSEL_CH4 16 | ||
148 | #define BM_APBH_DEVSEL_CH4 0xf0000 | ||
149 | #define BF_APBH_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
150 | #define BP_APBH_DEVSEL_CH3 12 | ||
151 | #define BM_APBH_DEVSEL_CH3 0xf000 | ||
152 | #define BF_APBH_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
153 | #define BP_APBH_DEVSEL_CH2 8 | ||
154 | #define BM_APBH_DEVSEL_CH2 0xf00 | ||
155 | #define BF_APBH_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
156 | #define BP_APBH_DEVSEL_CH1 4 | ||
157 | #define BM_APBH_DEVSEL_CH1 0xf0 | ||
158 | #define BF_APBH_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
159 | #define BP_APBH_DEVSEL_CH0 0 | ||
160 | #define BM_APBH_DEVSEL_CH0 0xf | ||
161 | #define BF_APBH_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
162 | |||
163 | /** | ||
164 | * Register: HW_APBH_CHn_CURCMDAR | ||
165 | * Address: 0x40+n*0x70 | ||
166 | * SCT: no | ||
167 | */ | ||
168 | #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70)) | ||
169 | #define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 | ||
170 | #define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
171 | #define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
172 | |||
173 | /** | ||
174 | * Register: HW_APBH_CHn_NXTCMDAR | ||
175 | * Address: 0x50+n*0x70 | ||
176 | * SCT: no | ||
177 | */ | ||
178 | #define HW_APBH_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70)) | ||
179 | #define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 | ||
180 | #define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
181 | #define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_APBH_CHn_CMD | ||
185 | * Address: 0x60+n*0x70 | ||
186 | * SCT: no | ||
187 | */ | ||
188 | #define HW_APBH_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70)) | ||
189 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
190 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xffff0000 | ||
191 | #define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
192 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
193 | #define BM_APBH_CHn_CMD_CMDWORDS 0xf000 | ||
194 | #define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
195 | #define BP_APBH_CHn_CMD_RSVD1 9 | ||
196 | #define BM_APBH_CHn_CMD_RSVD1 0xe00 | ||
197 | #define BF_APBH_CHn_CMD_RSVD1(v) (((v) << 9) & 0xe00) | ||
198 | #define BP_APBH_CHn_CMD_HALTONTERMINATE 8 | ||
199 | #define BM_APBH_CHn_CMD_HALTONTERMINATE 0x100 | ||
200 | #define BF_APBH_CHn_CMD_HALTONTERMINATE(v) (((v) << 8) & 0x100) | ||
201 | #define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 | ||
202 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x80 | ||
203 | #define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
204 | #define BP_APBH_CHn_CMD_SEMAPHORE 6 | ||
205 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x40 | ||
206 | #define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
207 | #define BP_APBH_CHn_CMD_NANDWAIT4READY 5 | ||
208 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x20 | ||
209 | #define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & 0x20) | ||
210 | #define BP_APBH_CHn_CMD_NANDLOCK 4 | ||
211 | #define BM_APBH_CHn_CMD_NANDLOCK 0x10 | ||
212 | #define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & 0x10) | ||
213 | #define BP_APBH_CHn_CMD_IRQONCMPLT 3 | ||
214 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x8 | ||
215 | #define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
216 | #define BP_APBH_CHn_CMD_CHAIN 2 | ||
217 | #define BM_APBH_CHn_CMD_CHAIN 0x4 | ||
218 | #define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
219 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
220 | #define BM_APBH_CHn_CMD_COMMAND 0x3 | ||
221 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
222 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
223 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
224 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 | ||
225 | #define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
226 | #define BF_APBH_CHn_CMD_COMMAND_V(v) ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
227 | |||
228 | /** | ||
229 | * Register: HW_APBH_CHn_BAR | ||
230 | * Address: 0x70+n*0x70 | ||
231 | * SCT: no | ||
232 | */ | ||
233 | #define HW_APBH_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70)) | ||
234 | #define BP_APBH_CHn_BAR_ADDRESS 0 | ||
235 | #define BM_APBH_CHn_BAR_ADDRESS 0xffffffff | ||
236 | #define BF_APBH_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
237 | |||
238 | /** | ||
239 | * Register: HW_APBH_CHn_SEMA | ||
240 | * Address: 0x80+n*0x70 | ||
241 | * SCT: no | ||
242 | */ | ||
243 | #define HW_APBH_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70)) | ||
244 | #define BP_APBH_CHn_SEMA_RSVD2 24 | ||
245 | #define BM_APBH_CHn_SEMA_RSVD2 0xff000000 | ||
246 | #define BF_APBH_CHn_SEMA_RSVD2(v) (((v) << 24) & 0xff000000) | ||
247 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
248 | #define BM_APBH_CHn_SEMA_PHORE 0xff0000 | ||
249 | #define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
250 | #define BP_APBH_CHn_SEMA_RSVD1 8 | ||
251 | #define BM_APBH_CHn_SEMA_RSVD1 0xff00 | ||
252 | #define BF_APBH_CHn_SEMA_RSVD1(v) (((v) << 8) & 0xff00) | ||
253 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
254 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0xff | ||
255 | #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
256 | |||
257 | /** | ||
258 | * Register: HW_APBH_CHn_DEBUG1 | ||
259 | * Address: 0x90+n*0x70 | ||
260 | * SCT: no | ||
261 | */ | ||
262 | #define HW_APBH_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70)) | ||
263 | #define BP_APBH_CHn_DEBUG1_REQ 31 | ||
264 | #define BM_APBH_CHn_DEBUG1_REQ 0x80000000 | ||
265 | #define BF_APBH_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
266 | #define BP_APBH_CHn_DEBUG1_BURST 30 | ||
267 | #define BM_APBH_CHn_DEBUG1_BURST 0x40000000 | ||
268 | #define BF_APBH_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
269 | #define BP_APBH_CHn_DEBUG1_KICK 29 | ||
270 | #define BM_APBH_CHn_DEBUG1_KICK 0x20000000 | ||
271 | #define BF_APBH_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
272 | #define BP_APBH_CHn_DEBUG1_END 28 | ||
273 | #define BM_APBH_CHn_DEBUG1_END 0x10000000 | ||
274 | #define BF_APBH_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
275 | #define BP_APBH_CHn_DEBUG1_SENSE 27 | ||
276 | #define BM_APBH_CHn_DEBUG1_SENSE 0x8000000 | ||
277 | #define BF_APBH_CHn_DEBUG1_SENSE(v) (((v) << 27) & 0x8000000) | ||
278 | #define BP_APBH_CHn_DEBUG1_READY 26 | ||
279 | #define BM_APBH_CHn_DEBUG1_READY 0x4000000 | ||
280 | #define BF_APBH_CHn_DEBUG1_READY(v) (((v) << 26) & 0x4000000) | ||
281 | #define BP_APBH_CHn_DEBUG1_LOCK 25 | ||
282 | #define BM_APBH_CHn_DEBUG1_LOCK 0x2000000 | ||
283 | #define BF_APBH_CHn_DEBUG1_LOCK(v) (((v) << 25) & 0x2000000) | ||
284 | #define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
285 | #define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
286 | #define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
287 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
288 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
289 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
290 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
291 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
292 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
293 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
294 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
295 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
296 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
297 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
298 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
299 | #define BP_APBH_CHn_DEBUG1_RSVD1 5 | ||
300 | #define BM_APBH_CHn_DEBUG1_RSVD1 0xfffe0 | ||
301 | #define BF_APBH_CHn_DEBUG1_RSVD1(v) (((v) << 5) & 0xfffe0) | ||
302 | #define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 | ||
303 | #define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x1f | ||
304 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
305 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
306 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
307 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
308 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
309 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
310 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
311 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
312 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
313 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
314 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
315 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
316 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
317 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
318 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 | ||
319 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
320 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
321 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1d | ||
322 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
323 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
324 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
325 | |||
326 | /** | ||
327 | * Register: HW_APBH_CHn_DEBUG2 | ||
328 | * Address: 0xa0+n*0x70 | ||
329 | * SCT: no | ||
330 | */ | ||
331 | #define HW_APBH_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0xa0+(n)*0x70)) | ||
332 | #define BP_APBH_CHn_DEBUG2_APB_BYTES 16 | ||
333 | #define BM_APBH_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
334 | #define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
335 | #define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 | ||
336 | #define BM_APBH_CHn_DEBUG2_AHB_BYTES 0xffff | ||
337 | #define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
338 | |||
339 | /** | ||
340 | * Register: HW_APBH_VERSION | ||
341 | * Address: 0x3f0 | ||
342 | * SCT: no | ||
343 | */ | ||
344 | #define HW_APBH_VERSION (*(volatile unsigned long *)(REGS_APBH_BASE + 0x3f0)) | ||
345 | #define BP_APBH_VERSION_MAJOR 24 | ||
346 | #define BM_APBH_VERSION_MAJOR 0xff000000 | ||
347 | #define BF_APBH_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
348 | #define BP_APBH_VERSION_MINOR 16 | ||
349 | #define BM_APBH_VERSION_MINOR 0xff0000 | ||
350 | #define BF_APBH_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
351 | #define BP_APBH_VERSION_STEP 0 | ||
352 | #define BM_APBH_VERSION_STEP 0xffff | ||
353 | #define BF_APBH_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
354 | |||
355 | #endif /* __HEADERGEN__IMX233__APBH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-apbx.h b/firmware/target/arm/imx233/regs/imx233/regs-apbx.h new file mode 100644 index 0000000000..990ae26d24 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-apbx.h | |||
@@ -0,0 +1,366 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.1 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__APBX__H__ | ||
24 | #define __HEADERGEN__IMX233__APBX__H__ | ||
25 | |||
26 | #define REGS_APBX_BASE (0x80024000) | ||
27 | |||
28 | #define REGS_APBX_VERSION "3.2.1" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_APBX_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_APBX_CTRL0 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0)) | ||
36 | #define HW_APBX_CTRL0_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4)) | ||
37 | #define HW_APBX_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8)) | ||
38 | #define HW_APBX_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc)) | ||
39 | #define BP_APBX_CTRL0_SFTRST 31 | ||
40 | #define BM_APBX_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_APBX_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_APBX_CTRL0_CLKGATE 30 | ||
43 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_APBX_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_APBX_CTRL0_RSVD0 0 | ||
46 | #define BM_APBX_CTRL0_RSVD0 0x3fffffff | ||
47 | #define BF_APBX_CTRL0_RSVD0(v) (((v) << 0) & 0x3fffffff) | ||
48 | |||
49 | /** | ||
50 | * Register: HW_APBX_CTRL1 | ||
51 | * Address: 0x10 | ||
52 | * SCT: yes | ||
53 | */ | ||
54 | #define HW_APBX_CTRL1 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0)) | ||
55 | #define HW_APBX_CTRL1_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4)) | ||
56 | #define HW_APBX_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8)) | ||
57 | #define HW_APBX_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc)) | ||
58 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 16 | ||
59 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 0xffff0000 | ||
60 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xffff0000) | ||
61 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
62 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ 0xffff | ||
63 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xffff) | ||
64 | |||
65 | /** | ||
66 | * Register: HW_APBX_CTRL2 | ||
67 | * Address: 0x20 | ||
68 | * SCT: yes | ||
69 | */ | ||
70 | #define HW_APBX_CTRL2 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x0)) | ||
71 | #define HW_APBX_CTRL2_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x4)) | ||
72 | #define HW_APBX_CTRL2_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x8)) | ||
73 | #define HW_APBX_CTRL2_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0xc)) | ||
74 | #define BP_APBX_CTRL2_CH_ERROR_STATUS 16 | ||
75 | #define BM_APBX_CTRL2_CH_ERROR_STATUS 0xffff0000 | ||
76 | #define BF_APBX_CTRL2_CH_ERROR_STATUS(v) (((v) << 16) & 0xffff0000) | ||
77 | #define BP_APBX_CTRL2_CH_ERROR_IRQ 0 | ||
78 | #define BM_APBX_CTRL2_CH_ERROR_IRQ 0xffff | ||
79 | #define BF_APBX_CTRL2_CH_ERROR_IRQ(v) (((v) << 0) & 0xffff) | ||
80 | |||
81 | /** | ||
82 | * Register: HW_APBX_CHANNEL_CTRL | ||
83 | * Address: 0x30 | ||
84 | * SCT: yes | ||
85 | */ | ||
86 | #define HW_APBX_CHANNEL_CTRL (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x0)) | ||
87 | #define HW_APBX_CHANNEL_CTRL_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x4)) | ||
88 | #define HW_APBX_CHANNEL_CTRL_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x8)) | ||
89 | #define HW_APBX_CHANNEL_CTRL_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0xc)) | ||
90 | #define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 | ||
91 | #define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xffff0000 | ||
92 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOIN 0x1 | ||
93 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOOUT 0x2 | ||
94 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX 0x4 | ||
95 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C 0x8 | ||
96 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1 0x10 | ||
97 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__DRI 0x20 | ||
98 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_RX 0x40 | ||
99 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX 0x40 | ||
100 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_TX 0x80 | ||
101 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX 0x80 | ||
102 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX 0x100 | ||
103 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX 0x200 | ||
104 | #define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF2 0x400 | ||
105 | #define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) (((v) << 16) & 0xffff0000) | ||
106 | #define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL_V(v) ((BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__##v << 16) & 0xffff0000) | ||
107 | #define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0 | ||
108 | #define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0xffff | ||
109 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOIN 0x1 | ||
110 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOOUT 0x2 | ||
111 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX 0x4 | ||
112 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C 0x8 | ||
113 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1 0x10 | ||
114 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__DRI 0x20 | ||
115 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_RX 0x40 | ||
116 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX 0x40 | ||
117 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_TX 0x80 | ||
118 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX 0x80 | ||
119 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX 0x100 | ||
120 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX 0x200 | ||
121 | #define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF2 0x400 | ||
122 | #define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v) (((v) << 0) & 0xffff) | ||
123 | #define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL_V(v) ((BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__##v << 0) & 0xffff) | ||
124 | |||
125 | /** | ||
126 | * Register: HW_APBX_DEVSEL | ||
127 | * Address: 0x40 | ||
128 | * SCT: no | ||
129 | */ | ||
130 | #define HW_APBX_DEVSEL (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40)) | ||
131 | #define BP_APBX_DEVSEL_CH15 30 | ||
132 | #define BM_APBX_DEVSEL_CH15 0xc0000000 | ||
133 | #define BF_APBX_DEVSEL_CH15(v) (((v) << 30) & 0xc0000000) | ||
134 | #define BP_APBX_DEVSEL_CH14 28 | ||
135 | #define BM_APBX_DEVSEL_CH14 0x30000000 | ||
136 | #define BF_APBX_DEVSEL_CH14(v) (((v) << 28) & 0x30000000) | ||
137 | #define BP_APBX_DEVSEL_CH13 26 | ||
138 | #define BM_APBX_DEVSEL_CH13 0xc000000 | ||
139 | #define BF_APBX_DEVSEL_CH13(v) (((v) << 26) & 0xc000000) | ||
140 | #define BP_APBX_DEVSEL_CH12 24 | ||
141 | #define BM_APBX_DEVSEL_CH12 0x3000000 | ||
142 | #define BF_APBX_DEVSEL_CH12(v) (((v) << 24) & 0x3000000) | ||
143 | #define BP_APBX_DEVSEL_CH11 22 | ||
144 | #define BM_APBX_DEVSEL_CH11 0xc00000 | ||
145 | #define BF_APBX_DEVSEL_CH11(v) (((v) << 22) & 0xc00000) | ||
146 | #define BP_APBX_DEVSEL_CH10 20 | ||
147 | #define BM_APBX_DEVSEL_CH10 0x300000 | ||
148 | #define BF_APBX_DEVSEL_CH10(v) (((v) << 20) & 0x300000) | ||
149 | #define BP_APBX_DEVSEL_CH9 18 | ||
150 | #define BM_APBX_DEVSEL_CH9 0xc0000 | ||
151 | #define BF_APBX_DEVSEL_CH9(v) (((v) << 18) & 0xc0000) | ||
152 | #define BP_APBX_DEVSEL_CH8 16 | ||
153 | #define BM_APBX_DEVSEL_CH8 0x30000 | ||
154 | #define BF_APBX_DEVSEL_CH8(v) (((v) << 16) & 0x30000) | ||
155 | #define BP_APBX_DEVSEL_CH7 14 | ||
156 | #define BM_APBX_DEVSEL_CH7 0xc000 | ||
157 | #define BV_APBX_DEVSEL_CH7__USE_I2C1 0x0 | ||
158 | #define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 | ||
159 | #define BF_APBX_DEVSEL_CH7(v) (((v) << 14) & 0xc000) | ||
160 | #define BF_APBX_DEVSEL_CH7_V(v) ((BV_APBX_DEVSEL_CH7__##v << 14) & 0xc000) | ||
161 | #define BP_APBX_DEVSEL_CH6 12 | ||
162 | #define BM_APBX_DEVSEL_CH6 0x3000 | ||
163 | #define BV_APBX_DEVSEL_CH6__USE_SAIF1 0x0 | ||
164 | #define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 | ||
165 | #define BF_APBX_DEVSEL_CH6(v) (((v) << 12) & 0x3000) | ||
166 | #define BF_APBX_DEVSEL_CH6_V(v) ((BV_APBX_DEVSEL_CH6__##v << 12) & 0x3000) | ||
167 | #define BP_APBX_DEVSEL_CH5 10 | ||
168 | #define BM_APBX_DEVSEL_CH5 0xc00 | ||
169 | #define BF_APBX_DEVSEL_CH5(v) (((v) << 10) & 0xc00) | ||
170 | #define BP_APBX_DEVSEL_CH4 8 | ||
171 | #define BM_APBX_DEVSEL_CH4 0x300 | ||
172 | #define BF_APBX_DEVSEL_CH4(v) (((v) << 8) & 0x300) | ||
173 | #define BP_APBX_DEVSEL_CH3 6 | ||
174 | #define BM_APBX_DEVSEL_CH3 0xc0 | ||
175 | #define BF_APBX_DEVSEL_CH3(v) (((v) << 6) & 0xc0) | ||
176 | #define BP_APBX_DEVSEL_CH2 4 | ||
177 | #define BM_APBX_DEVSEL_CH2 0x30 | ||
178 | #define BF_APBX_DEVSEL_CH2(v) (((v) << 4) & 0x30) | ||
179 | #define BP_APBX_DEVSEL_CH1 2 | ||
180 | #define BM_APBX_DEVSEL_CH1 0xc | ||
181 | #define BF_APBX_DEVSEL_CH1(v) (((v) << 2) & 0xc) | ||
182 | #define BP_APBX_DEVSEL_CH0 0 | ||
183 | #define BM_APBX_DEVSEL_CH0 0x3 | ||
184 | #define BF_APBX_DEVSEL_CH0(v) (((v) << 0) & 0x3) | ||
185 | |||
186 | /** | ||
187 | * Register: HW_APBX_CHn_CURCMDAR | ||
188 | * Address: 0x100+n*0x70 | ||
189 | * SCT: no | ||
190 | */ | ||
191 | #define HW_APBX_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x100+(n)*0x70)) | ||
192 | #define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 | ||
193 | #define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
194 | #define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
195 | |||
196 | /** | ||
197 | * Register: HW_APBX_CHn_NXTCMDAR | ||
198 | * Address: 0x110+n*0x70 | ||
199 | * SCT: no | ||
200 | */ | ||
201 | #define HW_APBX_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x110+(n)*0x70)) | ||
202 | #define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 | ||
203 | #define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
204 | #define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
205 | |||
206 | /** | ||
207 | * Register: HW_APBX_CHn_CMD | ||
208 | * Address: 0x120+n*0x70 | ||
209 | * SCT: no | ||
210 | */ | ||
211 | #define HW_APBX_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x120+(n)*0x70)) | ||
212 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 | ||
213 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xffff0000 | ||
214 | #define BF_APBX_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
215 | #define BP_APBX_CHn_CMD_CMDWORDS 12 | ||
216 | #define BM_APBX_CHn_CMD_CMDWORDS 0xf000 | ||
217 | #define BF_APBX_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
218 | #define BP_APBX_CHn_CMD_RSVD1 9 | ||
219 | #define BM_APBX_CHn_CMD_RSVD1 0xe00 | ||
220 | #define BF_APBX_CHn_CMD_RSVD1(v) (((v) << 9) & 0xe00) | ||
221 | #define BP_APBX_CHn_CMD_HALTONTERMINATE 8 | ||
222 | #define BM_APBX_CHn_CMD_HALTONTERMINATE 0x100 | ||
223 | #define BF_APBX_CHn_CMD_HALTONTERMINATE(v) (((v) << 8) & 0x100) | ||
224 | #define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 | ||
225 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x80 | ||
226 | #define BF_APBX_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
227 | #define BP_APBX_CHn_CMD_SEMAPHORE 6 | ||
228 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x40 | ||
229 | #define BF_APBX_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
230 | #define BP_APBX_CHn_CMD_RSVD0 4 | ||
231 | #define BM_APBX_CHn_CMD_RSVD0 0x30 | ||
232 | #define BF_APBX_CHn_CMD_RSVD0(v) (((v) << 4) & 0x30) | ||
233 | #define BP_APBX_CHn_CMD_IRQONCMPLT 3 | ||
234 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x8 | ||
235 | #define BF_APBX_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
236 | #define BP_APBX_CHn_CMD_CHAIN 2 | ||
237 | #define BM_APBX_CHn_CMD_CHAIN 0x4 | ||
238 | #define BF_APBX_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
239 | #define BP_APBX_CHn_CMD_COMMAND 0 | ||
240 | #define BM_APBX_CHn_CMD_COMMAND 0x3 | ||
241 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
242 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
243 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
244 | #define BF_APBX_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
245 | #define BF_APBX_CHn_CMD_COMMAND_V(v) ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_APBX_CHn_BAR | ||
249 | * Address: 0x130+n*0x70 | ||
250 | * SCT: no | ||
251 | */ | ||
252 | #define HW_APBX_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x130+(n)*0x70)) | ||
253 | #define BP_APBX_CHn_BAR_ADDRESS 0 | ||
254 | #define BM_APBX_CHn_BAR_ADDRESS 0xffffffff | ||
255 | #define BF_APBX_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
256 | |||
257 | /** | ||
258 | * Register: HW_APBX_CHn_SEMA | ||
259 | * Address: 0x140+n*0x70 | ||
260 | * SCT: no | ||
261 | */ | ||
262 | #define HW_APBX_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x140+(n)*0x70)) | ||
263 | #define BP_APBX_CHn_SEMA_RSVD2 24 | ||
264 | #define BM_APBX_CHn_SEMA_RSVD2 0xff000000 | ||
265 | #define BF_APBX_CHn_SEMA_RSVD2(v) (((v) << 24) & 0xff000000) | ||
266 | #define BP_APBX_CHn_SEMA_PHORE 16 | ||
267 | #define BM_APBX_CHn_SEMA_PHORE 0xff0000 | ||
268 | #define BF_APBX_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
269 | #define BP_APBX_CHn_SEMA_RSVD1 8 | ||
270 | #define BM_APBX_CHn_SEMA_RSVD1 0xff00 | ||
271 | #define BF_APBX_CHn_SEMA_RSVD1(v) (((v) << 8) & 0xff00) | ||
272 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 | ||
273 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0xff | ||
274 | #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
275 | |||
276 | /** | ||
277 | * Register: HW_APBX_CHn_DEBUG1 | ||
278 | * Address: 0x150+n*0x70 | ||
279 | * SCT: no | ||
280 | */ | ||
281 | #define HW_APBX_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x150+(n)*0x70)) | ||
282 | #define BP_APBX_CHn_DEBUG1_REQ 31 | ||
283 | #define BM_APBX_CHn_DEBUG1_REQ 0x80000000 | ||
284 | #define BF_APBX_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
285 | #define BP_APBX_CHn_DEBUG1_BURST 30 | ||
286 | #define BM_APBX_CHn_DEBUG1_BURST 0x40000000 | ||
287 | #define BF_APBX_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
288 | #define BP_APBX_CHn_DEBUG1_KICK 29 | ||
289 | #define BM_APBX_CHn_DEBUG1_KICK 0x20000000 | ||
290 | #define BF_APBX_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
291 | #define BP_APBX_CHn_DEBUG1_END 28 | ||
292 | #define BM_APBX_CHn_DEBUG1_END 0x10000000 | ||
293 | #define BF_APBX_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
294 | #define BP_APBX_CHn_DEBUG1_RSVD2 25 | ||
295 | #define BM_APBX_CHn_DEBUG1_RSVD2 0xe000000 | ||
296 | #define BF_APBX_CHn_DEBUG1_RSVD2(v) (((v) << 25) & 0xe000000) | ||
297 | #define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
298 | #define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
299 | #define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
300 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
301 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
302 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
303 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
304 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
305 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
306 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
307 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
308 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
309 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
310 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
311 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
312 | #define BP_APBX_CHn_DEBUG1_RSVD1 5 | ||
313 | #define BM_APBX_CHn_DEBUG1_RSVD1 0xfffe0 | ||
314 | #define BF_APBX_CHn_DEBUG1_RSVD1(v) (((v) << 5) & 0xfffe0) | ||
315 | #define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 | ||
316 | #define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x1f | ||
317 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
318 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
319 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
320 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
321 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
322 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
323 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
324 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
325 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
326 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
327 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
328 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
329 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
330 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
331 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
332 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
333 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
334 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
335 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
336 | |||
337 | /** | ||
338 | * Register: HW_APBX_CHn_DEBUG2 | ||
339 | * Address: 0x160+n*0x70 | ||
340 | * SCT: no | ||
341 | */ | ||
342 | #define HW_APBX_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x160+(n)*0x70)) | ||
343 | #define BP_APBX_CHn_DEBUG2_APB_BYTES 16 | ||
344 | #define BM_APBX_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
345 | #define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
346 | #define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 | ||
347 | #define BM_APBX_CHn_DEBUG2_AHB_BYTES 0xffff | ||
348 | #define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
349 | |||
350 | /** | ||
351 | * Register: HW_APBX_VERSION | ||
352 | * Address: 0x800 | ||
353 | * SCT: no | ||
354 | */ | ||
355 | #define HW_APBX_VERSION (*(volatile unsigned long *)(REGS_APBX_BASE + 0x800)) | ||
356 | #define BP_APBX_VERSION_MAJOR 24 | ||
357 | #define BM_APBX_VERSION_MAJOR 0xff000000 | ||
358 | #define BF_APBX_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
359 | #define BP_APBX_VERSION_MINOR 16 | ||
360 | #define BM_APBX_VERSION_MINOR 0xff0000 | ||
361 | #define BF_APBX_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
362 | #define BP_APBX_VERSION_STEP 0 | ||
363 | #define BM_APBX_VERSION_STEP 0xffff | ||
364 | #define BF_APBX_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
365 | |||
366 | #endif /* __HEADERGEN__IMX233__APBX__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-audioin.h b/firmware/target/arm/imx233/regs/imx233/regs-audioin.h new file mode 100644 index 0000000000..f2dd252f3a --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-audioin.h | |||
@@ -0,0 +1,368 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__AUDIOIN__H__ | ||
24 | #define __HEADERGEN__IMX233__AUDIOIN__H__ | ||
25 | |||
26 | #define REGS_AUDIOIN_BASE (0x8004c000) | ||
27 | |||
28 | #define REGS_AUDIOIN_VERSION "3.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_AUDIOIN_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_AUDIOIN_CTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0)) | ||
36 | #define HW_AUDIOIN_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4)) | ||
37 | #define HW_AUDIOIN_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8)) | ||
38 | #define HW_AUDIOIN_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc)) | ||
39 | #define BP_AUDIOIN_CTRL_SFTRST 31 | ||
40 | #define BM_AUDIOIN_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_AUDIOIN_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_AUDIOIN_CTRL_CLKGATE 30 | ||
43 | #define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_AUDIOIN_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_AUDIOIN_CTRL_RSRVD3 21 | ||
46 | #define BM_AUDIOIN_CTRL_RSRVD3 0x3fe00000 | ||
47 | #define BF_AUDIOIN_CTRL_RSRVD3(v) (((v) << 21) & 0x3fe00000) | ||
48 | #define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 | ||
49 | #define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
50 | #define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
51 | #define BP_AUDIOIN_CTRL_RSRVD1 11 | ||
52 | #define BM_AUDIOIN_CTRL_RSRVD1 0xf800 | ||
53 | #define BF_AUDIOIN_CTRL_RSRVD1(v) (((v) << 11) & 0xf800) | ||
54 | #define BP_AUDIOIN_CTRL_LR_SWAP 10 | ||
55 | #define BM_AUDIOIN_CTRL_LR_SWAP 0x400 | ||
56 | #define BF_AUDIOIN_CTRL_LR_SWAP(v) (((v) << 10) & 0x400) | ||
57 | #define BP_AUDIOIN_CTRL_EDGE_SYNC 9 | ||
58 | #define BM_AUDIOIN_CTRL_EDGE_SYNC 0x200 | ||
59 | #define BF_AUDIOIN_CTRL_EDGE_SYNC(v) (((v) << 9) & 0x200) | ||
60 | #define BP_AUDIOIN_CTRL_INVERT_1BIT 8 | ||
61 | #define BM_AUDIOIN_CTRL_INVERT_1BIT 0x100 | ||
62 | #define BF_AUDIOIN_CTRL_INVERT_1BIT(v) (((v) << 8) & 0x100) | ||
63 | #define BP_AUDIOIN_CTRL_OFFSET_ENABLE 7 | ||
64 | #define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x80 | ||
65 | #define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v) (((v) << 7) & 0x80) | ||
66 | #define BP_AUDIOIN_CTRL_HPF_ENABLE 6 | ||
67 | #define BM_AUDIOIN_CTRL_HPF_ENABLE 0x40 | ||
68 | #define BF_AUDIOIN_CTRL_HPF_ENABLE(v) (((v) << 6) & 0x40) | ||
69 | #define BP_AUDIOIN_CTRL_WORD_LENGTH 5 | ||
70 | #define BM_AUDIOIN_CTRL_WORD_LENGTH 0x20 | ||
71 | #define BF_AUDIOIN_CTRL_WORD_LENGTH(v) (((v) << 5) & 0x20) | ||
72 | #define BP_AUDIOIN_CTRL_LOOPBACK 4 | ||
73 | #define BM_AUDIOIN_CTRL_LOOPBACK 0x10 | ||
74 | #define BF_AUDIOIN_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
75 | #define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
76 | #define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
77 | #define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
78 | #define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
79 | #define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
80 | #define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
81 | #define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
82 | #define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
83 | #define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
84 | #define BP_AUDIOIN_CTRL_RUN 0 | ||
85 | #define BM_AUDIOIN_CTRL_RUN 0x1 | ||
86 | #define BF_AUDIOIN_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
87 | |||
88 | /** | ||
89 | * Register: HW_AUDIOIN_STAT | ||
90 | * Address: 0x10 | ||
91 | * SCT: yes | ||
92 | */ | ||
93 | #define HW_AUDIOIN_STAT (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x0)) | ||
94 | #define HW_AUDIOIN_STAT_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x4)) | ||
95 | #define HW_AUDIOIN_STAT_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x8)) | ||
96 | #define HW_AUDIOIN_STAT_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0xc)) | ||
97 | #define BP_AUDIOIN_STAT_ADC_PRESENT 31 | ||
98 | #define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 | ||
99 | #define BF_AUDIOIN_STAT_ADC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
100 | #define BP_AUDIOIN_STAT_RSRVD3 0 | ||
101 | #define BM_AUDIOIN_STAT_RSRVD3 0x7fffffff | ||
102 | #define BF_AUDIOIN_STAT_RSRVD3(v) (((v) << 0) & 0x7fffffff) | ||
103 | |||
104 | /** | ||
105 | * Register: HW_AUDIOIN_ADCSRR | ||
106 | * Address: 0x20 | ||
107 | * SCT: yes | ||
108 | */ | ||
109 | #define HW_AUDIOIN_ADCSRR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0)) | ||
110 | #define HW_AUDIOIN_ADCSRR_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4)) | ||
111 | #define HW_AUDIOIN_ADCSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8)) | ||
112 | #define HW_AUDIOIN_ADCSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc)) | ||
113 | #define BP_AUDIOIN_ADCSRR_OSR 31 | ||
114 | #define BM_AUDIOIN_ADCSRR_OSR 0x80000000 | ||
115 | #define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 | ||
116 | #define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 | ||
117 | #define BF_AUDIOIN_ADCSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
118 | #define BF_AUDIOIN_ADCSRR_OSR_V(v) ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000) | ||
119 | #define BP_AUDIOIN_ADCSRR_BASEMULT 28 | ||
120 | #define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 | ||
121 | #define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 | ||
122 | #define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
123 | #define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 | ||
124 | #define BF_AUDIOIN_ADCSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
125 | #define BF_AUDIOIN_ADCSRR_BASEMULT_V(v) ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000) | ||
126 | #define BP_AUDIOIN_ADCSRR_RSRVD2 27 | ||
127 | #define BM_AUDIOIN_ADCSRR_RSRVD2 0x8000000 | ||
128 | #define BF_AUDIOIN_ADCSRR_RSRVD2(v) (((v) << 27) & 0x8000000) | ||
129 | #define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 | ||
130 | #define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x7000000 | ||
131 | #define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
132 | #define BP_AUDIOIN_ADCSRR_RSRVD1 21 | ||
133 | #define BM_AUDIOIN_ADCSRR_RSRVD1 0xe00000 | ||
134 | #define BF_AUDIOIN_ADCSRR_RSRVD1(v) (((v) << 21) & 0xe00000) | ||
135 | #define BP_AUDIOIN_ADCSRR_SRC_INT 16 | ||
136 | #define BM_AUDIOIN_ADCSRR_SRC_INT 0x1f0000 | ||
137 | #define BF_AUDIOIN_ADCSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
138 | #define BP_AUDIOIN_ADCSRR_RSRVD0 13 | ||
139 | #define BM_AUDIOIN_ADCSRR_RSRVD0 0xe000 | ||
140 | #define BF_AUDIOIN_ADCSRR_RSRVD0(v) (((v) << 13) & 0xe000) | ||
141 | #define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 | ||
142 | #define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x1fff | ||
143 | #define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
144 | |||
145 | /** | ||
146 | * Register: HW_AUDIOIN_ADCVOLUME | ||
147 | * Address: 0x30 | ||
148 | * SCT: yes | ||
149 | */ | ||
150 | #define HW_AUDIOIN_ADCVOLUME (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0)) | ||
151 | #define HW_AUDIOIN_ADCVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4)) | ||
152 | #define HW_AUDIOIN_ADCVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8)) | ||
153 | #define HW_AUDIOIN_ADCVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc)) | ||
154 | #define BP_AUDIOIN_ADCVOLUME_RSRVD5 29 | ||
155 | #define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xe0000000 | ||
156 | #define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) (((v) << 29) & 0xe0000000) | ||
157 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 28 | ||
158 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
159 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
160 | #define BP_AUDIOIN_ADCVOLUME_RSRVD4 26 | ||
161 | #define BM_AUDIOIN_ADCVOLUME_RSRVD4 0xc000000 | ||
162 | #define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) (((v) << 26) & 0xc000000) | ||
163 | #define BP_AUDIOIN_ADCVOLUME_EN_ZCD 25 | ||
164 | #define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x2000000 | ||
165 | #define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
166 | #define BP_AUDIOIN_ADCVOLUME_RSRVD3 24 | ||
167 | #define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x1000000 | ||
168 | #define BF_AUDIOIN_ADCVOLUME_RSRVD3(v) (((v) << 24) & 0x1000000) | ||
169 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 | ||
170 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0xff0000 | ||
171 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
172 | #define BP_AUDIOIN_ADCVOLUME_RSRVD2 13 | ||
173 | #define BM_AUDIOIN_ADCVOLUME_RSRVD2 0xe000 | ||
174 | #define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) (((v) << 13) & 0xe000) | ||
175 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
176 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
177 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
178 | #define BP_AUDIOIN_ADCVOLUME_RSRVD1 8 | ||
179 | #define BM_AUDIOIN_ADCVOLUME_RSRVD1 0xf00 | ||
180 | #define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) (((v) << 8) & 0xf00) | ||
181 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 | ||
182 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0xff | ||
183 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
184 | |||
185 | /** | ||
186 | * Register: HW_AUDIOIN_ADCDEBUG | ||
187 | * Address: 0x40 | ||
188 | * SCT: yes | ||
189 | */ | ||
190 | #define HW_AUDIOIN_ADCDEBUG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0)) | ||
191 | #define HW_AUDIOIN_ADCDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4)) | ||
192 | #define HW_AUDIOIN_ADCDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8)) | ||
193 | #define HW_AUDIOIN_ADCDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc)) | ||
194 | #define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 31 | ||
195 | #define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 | ||
196 | #define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v) (((v) << 31) & 0x80000000) | ||
197 | #define BP_AUDIOIN_ADCDEBUG_RSRVD1 4 | ||
198 | #define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7ffffff0 | ||
199 | #define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) (((v) << 4) & 0x7ffffff0) | ||
200 | #define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 3 | ||
201 | #define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x8 | ||
202 | #define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8) | ||
203 | #define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 2 | ||
204 | #define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x4 | ||
205 | #define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
206 | #define BP_AUDIOIN_ADCDEBUG_DMA_PREQ 1 | ||
207 | #define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x2 | ||
208 | #define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
209 | #define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS 0 | ||
210 | #define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x1 | ||
211 | #define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
212 | |||
213 | /** | ||
214 | * Register: HW_AUDIOIN_ADCVOL | ||
215 | * Address: 0x50 | ||
216 | * SCT: yes | ||
217 | */ | ||
218 | #define HW_AUDIOIN_ADCVOL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0)) | ||
219 | #define HW_AUDIOIN_ADCVOL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4)) | ||
220 | #define HW_AUDIOIN_ADCVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8)) | ||
221 | #define HW_AUDIOIN_ADCVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc)) | ||
222 | #define BP_AUDIOIN_ADCVOL_RSRVD4 29 | ||
223 | #define BM_AUDIOIN_ADCVOL_RSRVD4 0xe0000000 | ||
224 | #define BF_AUDIOIN_ADCVOL_RSRVD4(v) (((v) << 29) & 0xe0000000) | ||
225 | #define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 28 | ||
226 | #define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000 | ||
227 | #define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
228 | #define BP_AUDIOIN_ADCVOL_RSRVD3 26 | ||
229 | #define BM_AUDIOIN_ADCVOL_RSRVD3 0xc000000 | ||
230 | #define BF_AUDIOIN_ADCVOL_RSRVD3(v) (((v) << 26) & 0xc000000) | ||
231 | #define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD 25 | ||
232 | #define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x2000000 | ||
233 | #define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v) (((v) << 25) & 0x2000000) | ||
234 | #define BP_AUDIOIN_ADCVOL_MUTE 24 | ||
235 | #define BM_AUDIOIN_ADCVOL_MUTE 0x1000000 | ||
236 | #define BF_AUDIOIN_ADCVOL_MUTE(v) (((v) << 24) & 0x1000000) | ||
237 | #define BP_AUDIOIN_ADCVOL_RSRVD2 14 | ||
238 | #define BM_AUDIOIN_ADCVOL_RSRVD2 0xffc000 | ||
239 | #define BF_AUDIOIN_ADCVOL_RSRVD2(v) (((v) << 14) & 0xffc000) | ||
240 | #define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 | ||
241 | #define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x3000 | ||
242 | #define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) (((v) << 12) & 0x3000) | ||
243 | #define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 | ||
244 | #define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0xf00 | ||
245 | #define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) (((v) << 8) & 0xf00) | ||
246 | #define BP_AUDIOIN_ADCVOL_RSRVD1 6 | ||
247 | #define BM_AUDIOIN_ADCVOL_RSRVD1 0xc0 | ||
248 | #define BF_AUDIOIN_ADCVOL_RSRVD1(v) (((v) << 6) & 0xc0) | ||
249 | #define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 | ||
250 | #define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x30 | ||
251 | #define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) (((v) << 4) & 0x30) | ||
252 | #define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 | ||
253 | #define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0xf | ||
254 | #define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) (((v) << 0) & 0xf) | ||
255 | |||
256 | /** | ||
257 | * Register: HW_AUDIOIN_MICLINE | ||
258 | * Address: 0x60 | ||
259 | * SCT: yes | ||
260 | */ | ||
261 | #define HW_AUDIOIN_MICLINE (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0)) | ||
262 | #define HW_AUDIOIN_MICLINE_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4)) | ||
263 | #define HW_AUDIOIN_MICLINE_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8)) | ||
264 | #define HW_AUDIOIN_MICLINE_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc)) | ||
265 | #define BP_AUDIOIN_MICLINE_RSRVD6 30 | ||
266 | #define BM_AUDIOIN_MICLINE_RSRVD6 0xc0000000 | ||
267 | #define BF_AUDIOIN_MICLINE_RSRVD6(v) (((v) << 30) & 0xc0000000) | ||
268 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE1 29 | ||
269 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 | ||
270 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v) (((v) << 29) & 0x20000000) | ||
271 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE2 28 | ||
272 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 | ||
273 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v) (((v) << 28) & 0x10000000) | ||
274 | #define BP_AUDIOIN_MICLINE_RSRVD5 25 | ||
275 | #define BM_AUDIOIN_MICLINE_RSRVD5 0xe000000 | ||
276 | #define BF_AUDIOIN_MICLINE_RSRVD5(v) (((v) << 25) & 0xe000000) | ||
277 | #define BP_AUDIOIN_MICLINE_MIC_SELECT 24 | ||
278 | #define BM_AUDIOIN_MICLINE_MIC_SELECT 0x1000000 | ||
279 | #define BF_AUDIOIN_MICLINE_MIC_SELECT(v) (((v) << 24) & 0x1000000) | ||
280 | #define BP_AUDIOIN_MICLINE_RSRVD4 22 | ||
281 | #define BM_AUDIOIN_MICLINE_RSRVD4 0xc00000 | ||
282 | #define BF_AUDIOIN_MICLINE_RSRVD4(v) (((v) << 22) & 0xc00000) | ||
283 | #define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 | ||
284 | #define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x300000 | ||
285 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off 0x0 | ||
286 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm 0x1 | ||
287 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm 0x2 | ||
288 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm 0x3 | ||
289 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) (((v) << 20) & 0x300000) | ||
290 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v) ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000) | ||
291 | #define BP_AUDIOIN_MICLINE_RSRVD3 19 | ||
292 | #define BM_AUDIOIN_MICLINE_RSRVD3 0x80000 | ||
293 | #define BF_AUDIOIN_MICLINE_RSRVD3(v) (((v) << 19) & 0x80000) | ||
294 | #define BP_AUDIOIN_MICLINE_MIC_BIAS 16 | ||
295 | #define BM_AUDIOIN_MICLINE_MIC_BIAS 0x70000 | ||
296 | #define BF_AUDIOIN_MICLINE_MIC_BIAS(v) (((v) << 16) & 0x70000) | ||
297 | #define BP_AUDIOIN_MICLINE_RSRVD2 6 | ||
298 | #define BM_AUDIOIN_MICLINE_RSRVD2 0xffc0 | ||
299 | #define BF_AUDIOIN_MICLINE_RSRVD2(v) (((v) << 6) & 0xffc0) | ||
300 | #define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4 | ||
301 | #define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x30 | ||
302 | #define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) (((v) << 4) & 0x30) | ||
303 | #define BP_AUDIOIN_MICLINE_RSRVD1 2 | ||
304 | #define BM_AUDIOIN_MICLINE_RSRVD1 0xc | ||
305 | #define BF_AUDIOIN_MICLINE_RSRVD1(v) (((v) << 2) & 0xc) | ||
306 | #define BP_AUDIOIN_MICLINE_MIC_GAIN 0 | ||
307 | #define BM_AUDIOIN_MICLINE_MIC_GAIN 0x3 | ||
308 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB 0x0 | ||
309 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB 0x1 | ||
310 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB 0x2 | ||
311 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB 0x3 | ||
312 | #define BF_AUDIOIN_MICLINE_MIC_GAIN(v) (((v) << 0) & 0x3) | ||
313 | #define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v) ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3) | ||
314 | |||
315 | /** | ||
316 | * Register: HW_AUDIOIN_ANACLKCTRL | ||
317 | * Address: 0x70 | ||
318 | * SCT: yes | ||
319 | */ | ||
320 | #define HW_AUDIOIN_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0)) | ||
321 | #define HW_AUDIOIN_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4)) | ||
322 | #define HW_AUDIOIN_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8)) | ||
323 | #define HW_AUDIOIN_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc)) | ||
324 | #define BP_AUDIOIN_ANACLKCTRL_CLKGATE 31 | ||
325 | #define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 | ||
326 | #define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
327 | #define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11 | ||
328 | #define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7ffff800 | ||
329 | #define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) (((v) << 11) & 0x7ffff800) | ||
330 | #define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF 10 | ||
331 | #define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x400 | ||
332 | #define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v) (((v) << 10) & 0x400) | ||
333 | #define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER 9 | ||
334 | #define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x200 | ||
335 | #define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v) (((v) << 9) & 0x200) | ||
336 | #define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 8 | ||
337 | #define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x100 | ||
338 | #define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v) (((v) << 8) & 0x100) | ||
339 | #define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6 | ||
340 | #define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0xc0 | ||
341 | #define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) (((v) << 6) & 0xc0) | ||
342 | #define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4 | ||
343 | #define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x30 | ||
344 | #define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) (((v) << 4) & 0x30) | ||
345 | #define BP_AUDIOIN_ANACLKCTRL_RSRVD2 3 | ||
346 | #define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x8 | ||
347 | #define BF_AUDIOIN_ANACLKCTRL_RSRVD2(v) (((v) << 3) & 0x8) | ||
348 | #define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 | ||
349 | #define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x7 | ||
350 | #define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) (((v) << 0) & 0x7) | ||
351 | |||
352 | /** | ||
353 | * Register: HW_AUDIOIN_DATA | ||
354 | * Address: 0x80 | ||
355 | * SCT: yes | ||
356 | */ | ||
357 | #define HW_AUDIOIN_DATA (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x0)) | ||
358 | #define HW_AUDIOIN_DATA_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x4)) | ||
359 | #define HW_AUDIOIN_DATA_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x8)) | ||
360 | #define HW_AUDIOIN_DATA_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0xc)) | ||
361 | #define BP_AUDIOIN_DATA_HIGH 16 | ||
362 | #define BM_AUDIOIN_DATA_HIGH 0xffff0000 | ||
363 | #define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
364 | #define BP_AUDIOIN_DATA_LOW 0 | ||
365 | #define BM_AUDIOIN_DATA_LOW 0xffff | ||
366 | #define BF_AUDIOIN_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
367 | |||
368 | #endif /* __HEADERGEN__IMX233__AUDIOIN__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-audioout.h b/firmware/target/arm/imx233/regs/imx233/regs-audioout.h new file mode 100644 index 0000000000..2b9f62ae74 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-audioout.h | |||
@@ -0,0 +1,673 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__AUDIOOUT__H__ | ||
24 | #define __HEADERGEN__IMX233__AUDIOOUT__H__ | ||
25 | |||
26 | #define REGS_AUDIOOUT_BASE (0x80048000) | ||
27 | |||
28 | #define REGS_AUDIOOUT_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_AUDIOOUT_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_AUDIOOUT_CTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0)) | ||
36 | #define HW_AUDIOOUT_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4)) | ||
37 | #define HW_AUDIOOUT_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8)) | ||
38 | #define HW_AUDIOOUT_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc)) | ||
39 | #define BP_AUDIOOUT_CTRL_SFTRST 31 | ||
40 | #define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_AUDIOOUT_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_AUDIOOUT_CTRL_CLKGATE 30 | ||
43 | #define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_AUDIOOUT_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_AUDIOOUT_CTRL_RSRVD4 21 | ||
46 | #define BM_AUDIOOUT_CTRL_RSRVD4 0x3fe00000 | ||
47 | #define BF_AUDIOOUT_CTRL_RSRVD4(v) (((v) << 21) & 0x3fe00000) | ||
48 | #define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 | ||
49 | #define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
50 | #define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
51 | #define BP_AUDIOOUT_CTRL_RSRVD3 15 | ||
52 | #define BM_AUDIOOUT_CTRL_RSRVD3 0x8000 | ||
53 | #define BF_AUDIOOUT_CTRL_RSRVD3(v) (((v) << 15) & 0x8000) | ||
54 | #define BP_AUDIOOUT_CTRL_LR_SWAP 14 | ||
55 | #define BM_AUDIOOUT_CTRL_LR_SWAP 0x4000 | ||
56 | #define BF_AUDIOOUT_CTRL_LR_SWAP(v) (((v) << 14) & 0x4000) | ||
57 | #define BP_AUDIOOUT_CTRL_EDGE_SYNC 13 | ||
58 | #define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x2000 | ||
59 | #define BF_AUDIOOUT_CTRL_EDGE_SYNC(v) (((v) << 13) & 0x2000) | ||
60 | #define BP_AUDIOOUT_CTRL_INVERT_1BIT 12 | ||
61 | #define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x1000 | ||
62 | #define BF_AUDIOOUT_CTRL_INVERT_1BIT(v) (((v) << 12) & 0x1000) | ||
63 | #define BP_AUDIOOUT_CTRL_RSRVD2 10 | ||
64 | #define BM_AUDIOOUT_CTRL_RSRVD2 0xc00 | ||
65 | #define BF_AUDIOOUT_CTRL_RSRVD2(v) (((v) << 10) & 0xc00) | ||
66 | #define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 | ||
67 | #define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x300 | ||
68 | #define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) (((v) << 8) & 0x300) | ||
69 | #define BP_AUDIOOUT_CTRL_RSRVD1 7 | ||
70 | #define BM_AUDIOOUT_CTRL_RSRVD1 0x80 | ||
71 | #define BF_AUDIOOUT_CTRL_RSRVD1(v) (((v) << 7) & 0x80) | ||
72 | #define BP_AUDIOOUT_CTRL_WORD_LENGTH 6 | ||
73 | #define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x40 | ||
74 | #define BF_AUDIOOUT_CTRL_WORD_LENGTH(v) (((v) << 6) & 0x40) | ||
75 | #define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 5 | ||
76 | #define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x20 | ||
77 | #define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v) (((v) << 5) & 0x20) | ||
78 | #define BP_AUDIOOUT_CTRL_LOOPBACK 4 | ||
79 | #define BM_AUDIOOUT_CTRL_LOOPBACK 0x10 | ||
80 | #define BF_AUDIOOUT_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
81 | #define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
82 | #define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
83 | #define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
84 | #define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
85 | #define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
86 | #define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
87 | #define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
88 | #define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
89 | #define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
90 | #define BP_AUDIOOUT_CTRL_RUN 0 | ||
91 | #define BM_AUDIOOUT_CTRL_RUN 0x1 | ||
92 | #define BF_AUDIOOUT_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
93 | |||
94 | /** | ||
95 | * Register: HW_AUDIOOUT_STAT | ||
96 | * Address: 0x10 | ||
97 | * SCT: yes | ||
98 | */ | ||
99 | #define HW_AUDIOOUT_STAT (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x0)) | ||
100 | #define HW_AUDIOOUT_STAT_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x4)) | ||
101 | #define HW_AUDIOOUT_STAT_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x8)) | ||
102 | #define HW_AUDIOOUT_STAT_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0xc)) | ||
103 | #define BP_AUDIOOUT_STAT_DAC_PRESENT 31 | ||
104 | #define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 | ||
105 | #define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
106 | #define BP_AUDIOOUT_STAT_RSRVD1 0 | ||
107 | #define BM_AUDIOOUT_STAT_RSRVD1 0x7fffffff | ||
108 | #define BF_AUDIOOUT_STAT_RSRVD1(v) (((v) << 0) & 0x7fffffff) | ||
109 | |||
110 | /** | ||
111 | * Register: HW_AUDIOOUT_DACSRR | ||
112 | * Address: 0x20 | ||
113 | * SCT: yes | ||
114 | */ | ||
115 | #define HW_AUDIOOUT_DACSRR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0)) | ||
116 | #define HW_AUDIOOUT_DACSRR_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4)) | ||
117 | #define HW_AUDIOOUT_DACSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8)) | ||
118 | #define HW_AUDIOOUT_DACSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc)) | ||
119 | #define BP_AUDIOOUT_DACSRR_OSR 31 | ||
120 | #define BM_AUDIOOUT_DACSRR_OSR 0x80000000 | ||
121 | #define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 | ||
122 | #define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 | ||
123 | #define BF_AUDIOOUT_DACSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
124 | #define BF_AUDIOOUT_DACSRR_OSR_V(v) ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000) | ||
125 | #define BP_AUDIOOUT_DACSRR_BASEMULT 28 | ||
126 | #define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 | ||
127 | #define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 | ||
128 | #define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
129 | #define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 | ||
130 | #define BF_AUDIOOUT_DACSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
131 | #define BF_AUDIOOUT_DACSRR_BASEMULT_V(v) ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000) | ||
132 | #define BP_AUDIOOUT_DACSRR_RSRVD2 27 | ||
133 | #define BM_AUDIOOUT_DACSRR_RSRVD2 0x8000000 | ||
134 | #define BF_AUDIOOUT_DACSRR_RSRVD2(v) (((v) << 27) & 0x8000000) | ||
135 | #define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 | ||
136 | #define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x7000000 | ||
137 | #define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
138 | #define BP_AUDIOOUT_DACSRR_RSRVD1 21 | ||
139 | #define BM_AUDIOOUT_DACSRR_RSRVD1 0xe00000 | ||
140 | #define BF_AUDIOOUT_DACSRR_RSRVD1(v) (((v) << 21) & 0xe00000) | ||
141 | #define BP_AUDIOOUT_DACSRR_SRC_INT 16 | ||
142 | #define BM_AUDIOOUT_DACSRR_SRC_INT 0x1f0000 | ||
143 | #define BF_AUDIOOUT_DACSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
144 | #define BP_AUDIOOUT_DACSRR_RSRVD0 13 | ||
145 | #define BM_AUDIOOUT_DACSRR_RSRVD0 0xe000 | ||
146 | #define BF_AUDIOOUT_DACSRR_RSRVD0(v) (((v) << 13) & 0xe000) | ||
147 | #define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 | ||
148 | #define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x1fff | ||
149 | #define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
150 | |||
151 | /** | ||
152 | * Register: HW_AUDIOOUT_DACVOLUME | ||
153 | * Address: 0x30 | ||
154 | * SCT: yes | ||
155 | */ | ||
156 | #define HW_AUDIOOUT_DACVOLUME (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0)) | ||
157 | #define HW_AUDIOOUT_DACVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4)) | ||
158 | #define HW_AUDIOOUT_DACVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8)) | ||
159 | #define HW_AUDIOOUT_DACVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc)) | ||
160 | #define BP_AUDIOOUT_DACVOLUME_RSRVD4 29 | ||
161 | #define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xe0000000 | ||
162 | #define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) (((v) << 29) & 0xe0000000) | ||
163 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 28 | ||
164 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
165 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
166 | #define BP_AUDIOOUT_DACVOLUME_RSRVD3 26 | ||
167 | #define BM_AUDIOOUT_DACVOLUME_RSRVD3 0xc000000 | ||
168 | #define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) (((v) << 26) & 0xc000000) | ||
169 | #define BP_AUDIOOUT_DACVOLUME_EN_ZCD 25 | ||
170 | #define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x2000000 | ||
171 | #define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
172 | #define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT 24 | ||
173 | #define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x1000000 | ||
174 | #define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v) (((v) << 24) & 0x1000000) | ||
175 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 | ||
176 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0xff0000 | ||
177 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
178 | #define BP_AUDIOOUT_DACVOLUME_RSRVD2 13 | ||
179 | #define BM_AUDIOOUT_DACVOLUME_RSRVD2 0xe000 | ||
180 | #define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) (((v) << 13) & 0xe000) | ||
181 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
182 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
183 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
184 | #define BP_AUDIOOUT_DACVOLUME_RSRVD1 9 | ||
185 | #define BM_AUDIOOUT_DACVOLUME_RSRVD1 0xe00 | ||
186 | #define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) (((v) << 9) & 0xe00) | ||
187 | #define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT 8 | ||
188 | #define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x100 | ||
189 | #define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v) (((v) << 8) & 0x100) | ||
190 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 | ||
191 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0xff | ||
192 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
193 | |||
194 | /** | ||
195 | * Register: HW_AUDIOOUT_DACDEBUG | ||
196 | * Address: 0x40 | ||
197 | * SCT: yes | ||
198 | */ | ||
199 | #define HW_AUDIOOUT_DACDEBUG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0)) | ||
200 | #define HW_AUDIOOUT_DACDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4)) | ||
201 | #define HW_AUDIOOUT_DACDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8)) | ||
202 | #define HW_AUDIOOUT_DACDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc)) | ||
203 | #define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 31 | ||
204 | #define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 | ||
205 | #define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v) (((v) << 31) & 0x80000000) | ||
206 | #define BP_AUDIOOUT_DACDEBUG_RSRVD2 12 | ||
207 | #define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7ffff000 | ||
208 | #define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) (((v) << 12) & 0x7ffff000) | ||
209 | #define BP_AUDIOOUT_DACDEBUG_RAM_SS 8 | ||
210 | #define BM_AUDIOOUT_DACDEBUG_RAM_SS 0xf00 | ||
211 | #define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) (((v) << 8) & 0xf00) | ||
212 | #define BP_AUDIOOUT_DACDEBUG_RSRVD1 6 | ||
213 | #define BM_AUDIOOUT_DACDEBUG_RSRVD1 0xc0 | ||
214 | #define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) (((v) << 6) & 0xc0) | ||
215 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 5 | ||
216 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x20 | ||
217 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v) (((v) << 5) & 0x20) | ||
218 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 4 | ||
219 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x10 | ||
220 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v) (((v) << 4) & 0x10) | ||
221 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 3 | ||
222 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x8 | ||
223 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v) (((v) << 3) & 0x8) | ||
224 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 2 | ||
225 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x4 | ||
226 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
227 | #define BP_AUDIOOUT_DACDEBUG_DMA_PREQ 1 | ||
228 | #define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x2 | ||
229 | #define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
230 | #define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS 0 | ||
231 | #define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x1 | ||
232 | #define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
233 | |||
234 | /** | ||
235 | * Register: HW_AUDIOOUT_HPVOL | ||
236 | * Address: 0x50 | ||
237 | * SCT: yes | ||
238 | */ | ||
239 | #define HW_AUDIOOUT_HPVOL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0)) | ||
240 | #define HW_AUDIOOUT_HPVOL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4)) | ||
241 | #define HW_AUDIOOUT_HPVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8)) | ||
242 | #define HW_AUDIOOUT_HPVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc)) | ||
243 | #define BP_AUDIOOUT_HPVOL_RSRVD5 29 | ||
244 | #define BM_AUDIOOUT_HPVOL_RSRVD5 0xe0000000 | ||
245 | #define BF_AUDIOOUT_HPVOL_RSRVD5(v) (((v) << 29) & 0xe0000000) | ||
246 | #define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 28 | ||
247 | #define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000 | ||
248 | #define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
249 | #define BP_AUDIOOUT_HPVOL_RSRVD4 26 | ||
250 | #define BM_AUDIOOUT_HPVOL_RSRVD4 0xc000000 | ||
251 | #define BF_AUDIOOUT_HPVOL_RSRVD4(v) (((v) << 26) & 0xc000000) | ||
252 | #define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD 25 | ||
253 | #define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x2000000 | ||
254 | #define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v) (((v) << 25) & 0x2000000) | ||
255 | #define BP_AUDIOOUT_HPVOL_MUTE 24 | ||
256 | #define BM_AUDIOOUT_HPVOL_MUTE 0x1000000 | ||
257 | #define BF_AUDIOOUT_HPVOL_MUTE(v) (((v) << 24) & 0x1000000) | ||
258 | #define BP_AUDIOOUT_HPVOL_RSRVD3 17 | ||
259 | #define BM_AUDIOOUT_HPVOL_RSRVD3 0xfe0000 | ||
260 | #define BF_AUDIOOUT_HPVOL_RSRVD3(v) (((v) << 17) & 0xfe0000) | ||
261 | #define BP_AUDIOOUT_HPVOL_SELECT 16 | ||
262 | #define BM_AUDIOOUT_HPVOL_SELECT 0x10000 | ||
263 | #define BF_AUDIOOUT_HPVOL_SELECT(v) (((v) << 16) & 0x10000) | ||
264 | #define BP_AUDIOOUT_HPVOL_RSRVD2 15 | ||
265 | #define BM_AUDIOOUT_HPVOL_RSRVD2 0x8000 | ||
266 | #define BF_AUDIOOUT_HPVOL_RSRVD2(v) (((v) << 15) & 0x8000) | ||
267 | #define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 | ||
268 | #define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x7f00 | ||
269 | #define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) (((v) << 8) & 0x7f00) | ||
270 | #define BP_AUDIOOUT_HPVOL_RSRVD1 7 | ||
271 | #define BM_AUDIOOUT_HPVOL_RSRVD1 0x80 | ||
272 | #define BF_AUDIOOUT_HPVOL_RSRVD1(v) (((v) << 7) & 0x80) | ||
273 | #define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 | ||
274 | #define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x7f | ||
275 | #define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) (((v) << 0) & 0x7f) | ||
276 | |||
277 | /** | ||
278 | * Register: HW_AUDIOOUT_RESERVED | ||
279 | * Address: 0x60 | ||
280 | * SCT: yes | ||
281 | */ | ||
282 | #define HW_AUDIOOUT_RESERVED (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x0)) | ||
283 | #define HW_AUDIOOUT_RESERVED_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x4)) | ||
284 | #define HW_AUDIOOUT_RESERVED_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x8)) | ||
285 | #define HW_AUDIOOUT_RESERVED_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0xc)) | ||
286 | #define BP_AUDIOOUT_RESERVED_RSRVD1 0 | ||
287 | #define BM_AUDIOOUT_RESERVED_RSRVD1 0xffffffff | ||
288 | #define BF_AUDIOOUT_RESERVED_RSRVD1(v) (((v) << 0) & 0xffffffff) | ||
289 | |||
290 | /** | ||
291 | * Register: HW_AUDIOOUT_PWRDN | ||
292 | * Address: 0x70 | ||
293 | * SCT: yes | ||
294 | */ | ||
295 | #define HW_AUDIOOUT_PWRDN (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0)) | ||
296 | #define HW_AUDIOOUT_PWRDN_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4)) | ||
297 | #define HW_AUDIOOUT_PWRDN_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8)) | ||
298 | #define HW_AUDIOOUT_PWRDN_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc)) | ||
299 | #define BP_AUDIOOUT_PWRDN_RSRVD7 25 | ||
300 | #define BM_AUDIOOUT_PWRDN_RSRVD7 0xfe000000 | ||
301 | #define BF_AUDIOOUT_PWRDN_RSRVD7(v) (((v) << 25) & 0xfe000000) | ||
302 | #define BP_AUDIOOUT_PWRDN_SPEAKER 24 | ||
303 | #define BM_AUDIOOUT_PWRDN_SPEAKER 0x1000000 | ||
304 | #define BF_AUDIOOUT_PWRDN_SPEAKER(v) (((v) << 24) & 0x1000000) | ||
305 | #define BP_AUDIOOUT_PWRDN_RSRVD6 21 | ||
306 | #define BM_AUDIOOUT_PWRDN_RSRVD6 0xe00000 | ||
307 | #define BF_AUDIOOUT_PWRDN_RSRVD6(v) (((v) << 21) & 0xe00000) | ||
308 | #define BP_AUDIOOUT_PWRDN_SELFBIAS 20 | ||
309 | #define BM_AUDIOOUT_PWRDN_SELFBIAS 0x100000 | ||
310 | #define BF_AUDIOOUT_PWRDN_SELFBIAS(v) (((v) << 20) & 0x100000) | ||
311 | #define BP_AUDIOOUT_PWRDN_RSRVD5 17 | ||
312 | #define BM_AUDIOOUT_PWRDN_RSRVD5 0xe0000 | ||
313 | #define BF_AUDIOOUT_PWRDN_RSRVD5(v) (((v) << 17) & 0xe0000) | ||
314 | #define BP_AUDIOOUT_PWRDN_RIGHT_ADC 16 | ||
315 | #define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x10000 | ||
316 | #define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v) (((v) << 16) & 0x10000) | ||
317 | #define BP_AUDIOOUT_PWRDN_RSRVD4 13 | ||
318 | #define BM_AUDIOOUT_PWRDN_RSRVD4 0xe000 | ||
319 | #define BF_AUDIOOUT_PWRDN_RSRVD4(v) (((v) << 13) & 0xe000) | ||
320 | #define BP_AUDIOOUT_PWRDN_DAC 12 | ||
321 | #define BM_AUDIOOUT_PWRDN_DAC 0x1000 | ||
322 | #define BF_AUDIOOUT_PWRDN_DAC(v) (((v) << 12) & 0x1000) | ||
323 | #define BP_AUDIOOUT_PWRDN_RSRVD3 9 | ||
324 | #define BM_AUDIOOUT_PWRDN_RSRVD3 0xe00 | ||
325 | #define BF_AUDIOOUT_PWRDN_RSRVD3(v) (((v) << 9) & 0xe00) | ||
326 | #define BP_AUDIOOUT_PWRDN_ADC 8 | ||
327 | #define BM_AUDIOOUT_PWRDN_ADC 0x100 | ||
328 | #define BF_AUDIOOUT_PWRDN_ADC(v) (((v) << 8) & 0x100) | ||
329 | #define BP_AUDIOOUT_PWRDN_RSRVD2 5 | ||
330 | #define BM_AUDIOOUT_PWRDN_RSRVD2 0xe0 | ||
331 | #define BF_AUDIOOUT_PWRDN_RSRVD2(v) (((v) << 5) & 0xe0) | ||
332 | #define BP_AUDIOOUT_PWRDN_CAPLESS 4 | ||
333 | #define BM_AUDIOOUT_PWRDN_CAPLESS 0x10 | ||
334 | #define BF_AUDIOOUT_PWRDN_CAPLESS(v) (((v) << 4) & 0x10) | ||
335 | #define BP_AUDIOOUT_PWRDN_RSRVD1 1 | ||
336 | #define BM_AUDIOOUT_PWRDN_RSRVD1 0xe | ||
337 | #define BF_AUDIOOUT_PWRDN_RSRVD1(v) (((v) << 1) & 0xe) | ||
338 | #define BP_AUDIOOUT_PWRDN_HEADPHONE 0 | ||
339 | #define BM_AUDIOOUT_PWRDN_HEADPHONE 0x1 | ||
340 | #define BF_AUDIOOUT_PWRDN_HEADPHONE(v) (((v) << 0) & 0x1) | ||
341 | |||
342 | /** | ||
343 | * Register: HW_AUDIOOUT_REFCTRL | ||
344 | * Address: 0x80 | ||
345 | * SCT: yes | ||
346 | */ | ||
347 | #define HW_AUDIOOUT_REFCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0)) | ||
348 | #define HW_AUDIOOUT_REFCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4)) | ||
349 | #define HW_AUDIOOUT_REFCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8)) | ||
350 | #define HW_AUDIOOUT_REFCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc)) | ||
351 | #define BP_AUDIOOUT_REFCTRL_RSRVD4 27 | ||
352 | #define BM_AUDIOOUT_REFCTRL_RSRVD4 0xf8000000 | ||
353 | #define BF_AUDIOOUT_REFCTRL_RSRVD4(v) (((v) << 27) & 0xf8000000) | ||
354 | #define BP_AUDIOOUT_REFCTRL_FASTSETTLING 26 | ||
355 | #define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x4000000 | ||
356 | #define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v) (((v) << 26) & 0x4000000) | ||
357 | #define BP_AUDIOOUT_REFCTRL_RAISE_REF 25 | ||
358 | #define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x2000000 | ||
359 | #define BF_AUDIOOUT_REFCTRL_RAISE_REF(v) (((v) << 25) & 0x2000000) | ||
360 | #define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 24 | ||
361 | #define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x1000000 | ||
362 | #define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v) (((v) << 24) & 0x1000000) | ||
363 | #define BP_AUDIOOUT_REFCTRL_RSRVD3 23 | ||
364 | #define BM_AUDIOOUT_REFCTRL_RSRVD3 0x800000 | ||
365 | #define BF_AUDIOOUT_REFCTRL_RSRVD3(v) (((v) << 23) & 0x800000) | ||
366 | #define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 | ||
367 | #define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x700000 | ||
368 | #define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) (((v) << 20) & 0x700000) | ||
369 | #define BP_AUDIOOUT_REFCTRL_LOW_PWR 19 | ||
370 | #define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x80000 | ||
371 | #define BF_AUDIOOUT_REFCTRL_LOW_PWR(v) (((v) << 19) & 0x80000) | ||
372 | #define BP_AUDIOOUT_REFCTRL_LW_REF 18 | ||
373 | #define BM_AUDIOOUT_REFCTRL_LW_REF 0x40000 | ||
374 | #define BF_AUDIOOUT_REFCTRL_LW_REF(v) (((v) << 18) & 0x40000) | ||
375 | #define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 | ||
376 | #define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x30000 | ||
377 | #define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) (((v) << 16) & 0x30000) | ||
378 | #define BP_AUDIOOUT_REFCTRL_RSRVD2 15 | ||
379 | #define BM_AUDIOOUT_REFCTRL_RSRVD2 0x8000 | ||
380 | #define BF_AUDIOOUT_REFCTRL_RSRVD2(v) (((v) << 15) & 0x8000) | ||
381 | #define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 14 | ||
382 | #define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x4000 | ||
383 | #define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v) (((v) << 14) & 0x4000) | ||
384 | #define BP_AUDIOOUT_REFCTRL_ADJ_ADC 13 | ||
385 | #define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x2000 | ||
386 | #define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v) (((v) << 13) & 0x2000) | ||
387 | #define BP_AUDIOOUT_REFCTRL_ADJ_VAG 12 | ||
388 | #define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x1000 | ||
389 | #define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v) (((v) << 12) & 0x1000) | ||
390 | #define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 | ||
391 | #define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0xf00 | ||
392 | #define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) (((v) << 8) & 0xf00) | ||
393 | #define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 | ||
394 | #define BM_AUDIOOUT_REFCTRL_VAG_VAL 0xf0 | ||
395 | #define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) (((v) << 4) & 0xf0) | ||
396 | #define BP_AUDIOOUT_REFCTRL_RSRVD1 3 | ||
397 | #define BM_AUDIOOUT_REFCTRL_RSRVD1 0x8 | ||
398 | #define BF_AUDIOOUT_REFCTRL_RSRVD1(v) (((v) << 3) & 0x8) | ||
399 | #define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 | ||
400 | #define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x7 | ||
401 | #define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) (((v) << 0) & 0x7) | ||
402 | |||
403 | /** | ||
404 | * Register: HW_AUDIOOUT_ANACTRL | ||
405 | * Address: 0x90 | ||
406 | * SCT: yes | ||
407 | */ | ||
408 | #define HW_AUDIOOUT_ANACTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0)) | ||
409 | #define HW_AUDIOOUT_ANACTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4)) | ||
410 | #define HW_AUDIOOUT_ANACTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8)) | ||
411 | #define HW_AUDIOOUT_ANACTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc)) | ||
412 | #define BP_AUDIOOUT_ANACTRL_RSRVD8 29 | ||
413 | #define BM_AUDIOOUT_ANACTRL_RSRVD8 0xe0000000 | ||
414 | #define BF_AUDIOOUT_ANACTRL_RSRVD8(v) (((v) << 29) & 0xe0000000) | ||
415 | #define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS 28 | ||
416 | #define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 | ||
417 | #define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v) (((v) << 28) & 0x10000000) | ||
418 | #define BP_AUDIOOUT_ANACTRL_RSRVD7 25 | ||
419 | #define BM_AUDIOOUT_ANACTRL_RSRVD7 0xe000000 | ||
420 | #define BF_AUDIOOUT_ANACTRL_RSRVD7(v) (((v) << 25) & 0xe000000) | ||
421 | #define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS 24 | ||
422 | #define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x1000000 | ||
423 | #define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v) (((v) << 24) & 0x1000000) | ||
424 | #define BP_AUDIOOUT_ANACTRL_RSRVD6 22 | ||
425 | #define BM_AUDIOOUT_ANACTRL_RSRVD6 0xc00000 | ||
426 | #define BF_AUDIOOUT_ANACTRL_RSRVD6(v) (((v) << 22) & 0xc00000) | ||
427 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 | ||
428 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x300000 | ||
429 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) (((v) << 20) & 0x300000) | ||
430 | #define BP_AUDIOOUT_ANACTRL_RSRVD5 19 | ||
431 | #define BM_AUDIOOUT_ANACTRL_RSRVD5 0x80000 | ||
432 | #define BF_AUDIOOUT_ANACTRL_RSRVD5(v) (((v) << 19) & 0x80000) | ||
433 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 | ||
434 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x60000 | ||
435 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) (((v) << 17) & 0x60000) | ||
436 | #define BP_AUDIOOUT_ANACTRL_RSRVD4 15 | ||
437 | #define BM_AUDIOOUT_ANACTRL_RSRVD4 0x18000 | ||
438 | #define BF_AUDIOOUT_ANACTRL_RSRVD4(v) (((v) << 15) & 0x18000) | ||
439 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 | ||
440 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x7000 | ||
441 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) (((v) << 12) & 0x7000) | ||
442 | #define BP_AUDIOOUT_ANACTRL_RSRVD3 11 | ||
443 | #define BM_AUDIOOUT_ANACTRL_RSRVD3 0x800 | ||
444 | #define BF_AUDIOOUT_ANACTRL_RSRVD3(v) (((v) << 11) & 0x800) | ||
445 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 | ||
446 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x700 | ||
447 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) (((v) << 8) & 0x700) | ||
448 | #define BP_AUDIOOUT_ANACTRL_RSRVD2 6 | ||
449 | #define BM_AUDIOOUT_ANACTRL_RSRVD2 0xc0 | ||
450 | #define BF_AUDIOOUT_ANACTRL_RSRVD2(v) (((v) << 6) & 0xc0) | ||
451 | #define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND 5 | ||
452 | #define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x20 | ||
453 | #define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v) (((v) << 5) & 0x20) | ||
454 | #define BP_AUDIOOUT_ANACTRL_HP_CLASSAB 4 | ||
455 | #define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x10 | ||
456 | #define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v) (((v) << 4) & 0x10) | ||
457 | #define BP_AUDIOOUT_ANACTRL_RSRVD1 0 | ||
458 | #define BM_AUDIOOUT_ANACTRL_RSRVD1 0xf | ||
459 | #define BF_AUDIOOUT_ANACTRL_RSRVD1(v) (((v) << 0) & 0xf) | ||
460 | |||
461 | /** | ||
462 | * Register: HW_AUDIOOUT_TEST | ||
463 | * Address: 0xa0 | ||
464 | * SCT: yes | ||
465 | */ | ||
466 | #define HW_AUDIOOUT_TEST (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0)) | ||
467 | #define HW_AUDIOOUT_TEST_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4)) | ||
468 | #define HW_AUDIOOUT_TEST_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8)) | ||
469 | #define HW_AUDIOOUT_TEST_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc)) | ||
470 | #define BP_AUDIOOUT_TEST_RSRVD4 31 | ||
471 | #define BM_AUDIOOUT_TEST_RSRVD4 0x80000000 | ||
472 | #define BF_AUDIOOUT_TEST_RSRVD4(v) (((v) << 31) & 0x80000000) | ||
473 | #define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 | ||
474 | #define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 | ||
475 | #define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) (((v) << 28) & 0x70000000) | ||
476 | #define BP_AUDIOOUT_TEST_RSRVD3 27 | ||
477 | #define BM_AUDIOOUT_TEST_RSRVD3 0x8000000 | ||
478 | #define BF_AUDIOOUT_TEST_RSRVD3(v) (((v) << 27) & 0x8000000) | ||
479 | #define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP 26 | ||
480 | #define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x4000000 | ||
481 | #define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v) (((v) << 26) & 0x4000000) | ||
482 | #define BP_AUDIOOUT_TEST_TM_LOOP 25 | ||
483 | #define BM_AUDIOOUT_TEST_TM_LOOP 0x2000000 | ||
484 | #define BF_AUDIOOUT_TEST_TM_LOOP(v) (((v) << 25) & 0x2000000) | ||
485 | #define BP_AUDIOOUT_TEST_TM_HPCOMMON 24 | ||
486 | #define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x1000000 | ||
487 | #define BF_AUDIOOUT_TEST_TM_HPCOMMON(v) (((v) << 24) & 0x1000000) | ||
488 | #define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 | ||
489 | #define BM_AUDIOOUT_TEST_HP_I1_ADJ 0xc00000 | ||
490 | #define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) (((v) << 22) & 0xc00000) | ||
491 | #define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 | ||
492 | #define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x300000 | ||
493 | #define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) (((v) << 20) & 0x300000) | ||
494 | #define BP_AUDIOOUT_TEST_RSRVD2 14 | ||
495 | #define BM_AUDIOOUT_TEST_RSRVD2 0xfc000 | ||
496 | #define BF_AUDIOOUT_TEST_RSRVD2(v) (((v) << 14) & 0xfc000) | ||
497 | #define BP_AUDIOOUT_TEST_VAG_CLASSA 13 | ||
498 | #define BM_AUDIOOUT_TEST_VAG_CLASSA 0x2000 | ||
499 | #define BF_AUDIOOUT_TEST_VAG_CLASSA(v) (((v) << 13) & 0x2000) | ||
500 | #define BP_AUDIOOUT_TEST_VAG_DOUBLE_I 12 | ||
501 | #define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x1000 | ||
502 | #define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v) (((v) << 12) & 0x1000) | ||
503 | #define BP_AUDIOOUT_TEST_RSRVD1 4 | ||
504 | #define BM_AUDIOOUT_TEST_RSRVD1 0xff0 | ||
505 | #define BF_AUDIOOUT_TEST_RSRVD1(v) (((v) << 4) & 0xff0) | ||
506 | #define BP_AUDIOOUT_TEST_ADCTODAC_LOOP 3 | ||
507 | #define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x8 | ||
508 | #define BF_AUDIOOUT_TEST_ADCTODAC_LOOP(v) (((v) << 3) & 0x8) | ||
509 | #define BP_AUDIOOUT_TEST_DAC_CLASSA 2 | ||
510 | #define BM_AUDIOOUT_TEST_DAC_CLASSA 0x4 | ||
511 | #define BF_AUDIOOUT_TEST_DAC_CLASSA(v) (((v) << 2) & 0x4) | ||
512 | #define BP_AUDIOOUT_TEST_DAC_DOUBLE_I 1 | ||
513 | #define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x2 | ||
514 | #define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v) (((v) << 1) & 0x2) | ||
515 | #define BP_AUDIOOUT_TEST_DAC_DIS_RTZ 0 | ||
516 | #define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x1 | ||
517 | #define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v) (((v) << 0) & 0x1) | ||
518 | |||
519 | /** | ||
520 | * Register: HW_AUDIOOUT_BISTCTRL | ||
521 | * Address: 0xb0 | ||
522 | * SCT: yes | ||
523 | */ | ||
524 | #define HW_AUDIOOUT_BISTCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0)) | ||
525 | #define HW_AUDIOOUT_BISTCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4)) | ||
526 | #define HW_AUDIOOUT_BISTCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8)) | ||
527 | #define HW_AUDIOOUT_BISTCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc)) | ||
528 | #define BP_AUDIOOUT_BISTCTRL_RSVD0 4 | ||
529 | #define BM_AUDIOOUT_BISTCTRL_RSVD0 0xfffffff0 | ||
530 | #define BF_AUDIOOUT_BISTCTRL_RSVD0(v) (((v) << 4) & 0xfffffff0) | ||
531 | #define BP_AUDIOOUT_BISTCTRL_FAIL 3 | ||
532 | #define BM_AUDIOOUT_BISTCTRL_FAIL 0x8 | ||
533 | #define BF_AUDIOOUT_BISTCTRL_FAIL(v) (((v) << 3) & 0x8) | ||
534 | #define BP_AUDIOOUT_BISTCTRL_PASS 2 | ||
535 | #define BM_AUDIOOUT_BISTCTRL_PASS 0x4 | ||
536 | #define BF_AUDIOOUT_BISTCTRL_PASS(v) (((v) << 2) & 0x4) | ||
537 | #define BP_AUDIOOUT_BISTCTRL_DONE 1 | ||
538 | #define BM_AUDIOOUT_BISTCTRL_DONE 0x2 | ||
539 | #define BF_AUDIOOUT_BISTCTRL_DONE(v) (((v) << 1) & 0x2) | ||
540 | #define BP_AUDIOOUT_BISTCTRL_START 0 | ||
541 | #define BM_AUDIOOUT_BISTCTRL_START 0x1 | ||
542 | #define BF_AUDIOOUT_BISTCTRL_START(v) (((v) << 0) & 0x1) | ||
543 | |||
544 | /** | ||
545 | * Register: HW_AUDIOOUT_BISTSTAT0 | ||
546 | * Address: 0xc0 | ||
547 | * SCT: yes | ||
548 | */ | ||
549 | #define HW_AUDIOOUT_BISTSTAT0 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x0)) | ||
550 | #define HW_AUDIOOUT_BISTSTAT0_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x4)) | ||
551 | #define HW_AUDIOOUT_BISTSTAT0_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x8)) | ||
552 | #define HW_AUDIOOUT_BISTSTAT0_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0xc)) | ||
553 | #define BP_AUDIOOUT_BISTSTAT0_RSVD0 24 | ||
554 | #define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xff000000 | ||
555 | #define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) (((v) << 24) & 0xff000000) | ||
556 | #define BP_AUDIOOUT_BISTSTAT0_DATA 0 | ||
557 | #define BM_AUDIOOUT_BISTSTAT0_DATA 0xffffff | ||
558 | #define BF_AUDIOOUT_BISTSTAT0_DATA(v) (((v) << 0) & 0xffffff) | ||
559 | |||
560 | /** | ||
561 | * Register: HW_AUDIOOUT_BISTSTAT1 | ||
562 | * Address: 0xd0 | ||
563 | * SCT: yes | ||
564 | */ | ||
565 | #define HW_AUDIOOUT_BISTSTAT1 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x0)) | ||
566 | #define HW_AUDIOOUT_BISTSTAT1_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x4)) | ||
567 | #define HW_AUDIOOUT_BISTSTAT1_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x8)) | ||
568 | #define HW_AUDIOOUT_BISTSTAT1_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0xc)) | ||
569 | #define BP_AUDIOOUT_BISTSTAT1_RSVD1 29 | ||
570 | #define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xe0000000 | ||
571 | #define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) (((v) << 29) & 0xe0000000) | ||
572 | #define BP_AUDIOOUT_BISTSTAT1_STATE 24 | ||
573 | #define BM_AUDIOOUT_BISTSTAT1_STATE 0x1f000000 | ||
574 | #define BF_AUDIOOUT_BISTSTAT1_STATE(v) (((v) << 24) & 0x1f000000) | ||
575 | #define BP_AUDIOOUT_BISTSTAT1_RSVD0 8 | ||
576 | #define BM_AUDIOOUT_BISTSTAT1_RSVD0 0xffff00 | ||
577 | #define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) (((v) << 8) & 0xffff00) | ||
578 | #define BP_AUDIOOUT_BISTSTAT1_ADDR 0 | ||
579 | #define BM_AUDIOOUT_BISTSTAT1_ADDR 0xff | ||
580 | #define BF_AUDIOOUT_BISTSTAT1_ADDR(v) (((v) << 0) & 0xff) | ||
581 | |||
582 | /** | ||
583 | * Register: HW_AUDIOOUT_ANACLKCTRL | ||
584 | * Address: 0xe0 | ||
585 | * SCT: yes | ||
586 | */ | ||
587 | #define HW_AUDIOOUT_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0)) | ||
588 | #define HW_AUDIOOUT_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4)) | ||
589 | #define HW_AUDIOOUT_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8)) | ||
590 | #define HW_AUDIOOUT_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc)) | ||
591 | #define BP_AUDIOOUT_ANACLKCTRL_CLKGATE 31 | ||
592 | #define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 | ||
593 | #define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
594 | #define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5 | ||
595 | #define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7fffffe0 | ||
596 | #define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) (((v) << 5) & 0x7fffffe0) | ||
597 | #define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 4 | ||
598 | #define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x10 | ||
599 | #define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10) | ||
600 | #define BP_AUDIOOUT_ANACLKCTRL_RSRVD2 3 | ||
601 | #define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x8 | ||
602 | #define BF_AUDIOOUT_ANACLKCTRL_RSRVD2(v) (((v) << 3) & 0x8) | ||
603 | #define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 | ||
604 | #define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x7 | ||
605 | #define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) (((v) << 0) & 0x7) | ||
606 | |||
607 | /** | ||
608 | * Register: HW_AUDIOOUT_DATA | ||
609 | * Address: 0xf0 | ||
610 | * SCT: yes | ||
611 | */ | ||
612 | #define HW_AUDIOOUT_DATA (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0)) | ||
613 | #define HW_AUDIOOUT_DATA_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4)) | ||
614 | #define HW_AUDIOOUT_DATA_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8)) | ||
615 | #define HW_AUDIOOUT_DATA_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc)) | ||
616 | #define BP_AUDIOOUT_DATA_HIGH 16 | ||
617 | #define BM_AUDIOOUT_DATA_HIGH 0xffff0000 | ||
618 | #define BF_AUDIOOUT_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
619 | #define BP_AUDIOOUT_DATA_LOW 0 | ||
620 | #define BM_AUDIOOUT_DATA_LOW 0xffff | ||
621 | #define BF_AUDIOOUT_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
622 | |||
623 | /** | ||
624 | * Register: HW_AUDIOOUT_SPEAKERCTRL | ||
625 | * Address: 0x100 | ||
626 | * SCT: yes | ||
627 | */ | ||
628 | #define HW_AUDIOOUT_SPEAKERCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x0)) | ||
629 | #define HW_AUDIOOUT_SPEAKERCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x4)) | ||
630 | #define HW_AUDIOOUT_SPEAKERCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x8)) | ||
631 | #define HW_AUDIOOUT_SPEAKERCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0xc)) | ||
632 | #define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25 | ||
633 | #define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xfe000000 | ||
634 | #define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) (((v) << 25) & 0xfe000000) | ||
635 | #define BP_AUDIOOUT_SPEAKERCTRL_MUTE 24 | ||
636 | #define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x1000000 | ||
637 | #define BF_AUDIOOUT_SPEAKERCTRL_MUTE(v) (((v) << 24) & 0x1000000) | ||
638 | #define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22 | ||
639 | #define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0xc00000 | ||
640 | #define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) (((v) << 22) & 0xc00000) | ||
641 | #define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20 | ||
642 | #define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x300000 | ||
643 | #define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) (((v) << 20) & 0x300000) | ||
644 | #define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16 | ||
645 | #define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0xf0000 | ||
646 | #define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) (((v) << 16) & 0xf0000) | ||
647 | #define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14 | ||
648 | #define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0xc000 | ||
649 | #define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) (((v) << 14) & 0xc000) | ||
650 | #define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12 | ||
651 | #define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x3000 | ||
652 | #define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) (((v) << 12) & 0x3000) | ||
653 | #define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0 | ||
654 | #define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0xfff | ||
655 | #define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) (((v) << 0) & 0xfff) | ||
656 | |||
657 | /** | ||
658 | * Register: HW_AUDIOOUT_VERSION | ||
659 | * Address: 0x200 | ||
660 | * SCT: no | ||
661 | */ | ||
662 | #define HW_AUDIOOUT_VERSION (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x200)) | ||
663 | #define BP_AUDIOOUT_VERSION_MAJOR 24 | ||
664 | #define BM_AUDIOOUT_VERSION_MAJOR 0xff000000 | ||
665 | #define BF_AUDIOOUT_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
666 | #define BP_AUDIOOUT_VERSION_MINOR 16 | ||
667 | #define BM_AUDIOOUT_VERSION_MINOR 0xff0000 | ||
668 | #define BF_AUDIOOUT_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
669 | #define BP_AUDIOOUT_VERSION_STEP 0 | ||
670 | #define BM_AUDIOOUT_VERSION_STEP 0xffff | ||
671 | #define BF_AUDIOOUT_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
672 | |||
673 | #endif /* __HEADERGEN__IMX233__AUDIOOUT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-bch.h b/firmware/target/arm/imx233/regs/imx233/regs-bch.h new file mode 100644 index 0000000000..d8ecf4297c --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-bch.h | |||
@@ -0,0 +1,606 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__BCH__H__ | ||
24 | #define __HEADERGEN__IMX233__BCH__H__ | ||
25 | |||
26 | #define REGS_BCH_BASE (0x8000a000) | ||
27 | |||
28 | #define REGS_BCH_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_BCH_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_BCH_CTRL (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x0)) | ||
36 | #define HW_BCH_CTRL_SET (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x4)) | ||
37 | #define HW_BCH_CTRL_CLR (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x8)) | ||
38 | #define HW_BCH_CTRL_TOG (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0xc)) | ||
39 | #define BP_BCH_CTRL_SFTRST 31 | ||
40 | #define BM_BCH_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_BCH_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_BCH_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_BCH_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_BCH_CTRL_SFTRST_V(v) ((BV_BCH_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_BCH_CTRL_CLKGATE 30 | ||
46 | #define BM_BCH_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_BCH_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_BCH_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_BCH_CTRL_CLKGATE_V(v) ((BV_BCH_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_BCH_CTRL_RSVD5 23 | ||
52 | #define BM_BCH_CTRL_RSVD5 0x3f800000 | ||
53 | #define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & 0x3f800000) | ||
54 | #define BP_BCH_CTRL_DEBUGSYNDROME 22 | ||
55 | #define BM_BCH_CTRL_DEBUGSYNDROME 0x400000 | ||
56 | #define BF_BCH_CTRL_DEBUGSYNDROME(v) (((v) << 22) & 0x400000) | ||
57 | #define BP_BCH_CTRL_RSVD4 20 | ||
58 | #define BM_BCH_CTRL_RSVD4 0x300000 | ||
59 | #define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & 0x300000) | ||
60 | #define BP_BCH_CTRL_M2M_LAYOUT 18 | ||
61 | #define BM_BCH_CTRL_M2M_LAYOUT 0xc0000 | ||
62 | #define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & 0xc0000) | ||
63 | #define BP_BCH_CTRL_M2M_ENCODE 17 | ||
64 | #define BM_BCH_CTRL_M2M_ENCODE 0x20000 | ||
65 | #define BF_BCH_CTRL_M2M_ENCODE(v) (((v) << 17) & 0x20000) | ||
66 | #define BP_BCH_CTRL_M2M_ENABLE 16 | ||
67 | #define BM_BCH_CTRL_M2M_ENABLE 0x10000 | ||
68 | #define BF_BCH_CTRL_M2M_ENABLE(v) (((v) << 16) & 0x10000) | ||
69 | #define BP_BCH_CTRL_RSVD3 11 | ||
70 | #define BM_BCH_CTRL_RSVD3 0xf800 | ||
71 | #define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & 0xf800) | ||
72 | #define BP_BCH_CTRL_DEBUG_STALL_IRQ_EN 10 | ||
73 | #define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x400 | ||
74 | #define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(v) (((v) << 10) & 0x400) | ||
75 | #define BP_BCH_CTRL_RSVD2 9 | ||
76 | #define BM_BCH_CTRL_RSVD2 0x200 | ||
77 | #define BF_BCH_CTRL_RSVD2(v) (((v) << 9) & 0x200) | ||
78 | #define BP_BCH_CTRL_COMPLETE_IRQ_EN 8 | ||
79 | #define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x100 | ||
80 | #define BF_BCH_CTRL_COMPLETE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
81 | #define BP_BCH_CTRL_RSVD1 4 | ||
82 | #define BM_BCH_CTRL_RSVD1 0xf0 | ||
83 | #define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & 0xf0) | ||
84 | #define BP_BCH_CTRL_BM_ERROR_IRQ 3 | ||
85 | #define BM_BCH_CTRL_BM_ERROR_IRQ 0x8 | ||
86 | #define BF_BCH_CTRL_BM_ERROR_IRQ(v) (((v) << 3) & 0x8) | ||
87 | #define BP_BCH_CTRL_DEBUG_STALL_IRQ 2 | ||
88 | #define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x4 | ||
89 | #define BF_BCH_CTRL_DEBUG_STALL_IRQ(v) (((v) << 2) & 0x4) | ||
90 | #define BP_BCH_CTRL_RSVD0 1 | ||
91 | #define BM_BCH_CTRL_RSVD0 0x2 | ||
92 | #define BF_BCH_CTRL_RSVD0(v) (((v) << 1) & 0x2) | ||
93 | #define BP_BCH_CTRL_COMPLETE_IRQ 0 | ||
94 | #define BM_BCH_CTRL_COMPLETE_IRQ 0x1 | ||
95 | #define BF_BCH_CTRL_COMPLETE_IRQ(v) (((v) << 0) & 0x1) | ||
96 | |||
97 | /** | ||
98 | * Register: HW_BCH_STATUS0 | ||
99 | * Address: 0x10 | ||
100 | * SCT: no | ||
101 | */ | ||
102 | #define HW_BCH_STATUS0 (*(volatile unsigned long *)(REGS_BCH_BASE + 0x10)) | ||
103 | #define BP_BCH_STATUS0_HANDLE 20 | ||
104 | #define BM_BCH_STATUS0_HANDLE 0xfff00000 | ||
105 | #define BF_BCH_STATUS0_HANDLE(v) (((v) << 20) & 0xfff00000) | ||
106 | #define BP_BCH_STATUS0_COMPLETED_CE 16 | ||
107 | #define BM_BCH_STATUS0_COMPLETED_CE 0xf0000 | ||
108 | #define BF_BCH_STATUS0_COMPLETED_CE(v) (((v) << 16) & 0xf0000) | ||
109 | #define BP_BCH_STATUS0_STATUS_BLK0 8 | ||
110 | #define BM_BCH_STATUS0_STATUS_BLK0 0xff00 | ||
111 | #define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x0 | ||
112 | #define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x1 | ||
113 | #define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x2 | ||
114 | #define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x3 | ||
115 | #define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x4 | ||
116 | #define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xfe | ||
117 | #define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xff | ||
118 | #define BF_BCH_STATUS0_STATUS_BLK0(v) (((v) << 8) & 0xff00) | ||
119 | #define BF_BCH_STATUS0_STATUS_BLK0_V(v) ((BV_BCH_STATUS0_STATUS_BLK0__##v << 8) & 0xff00) | ||
120 | #define BP_BCH_STATUS0_RSVD1 5 | ||
121 | #define BM_BCH_STATUS0_RSVD1 0xe0 | ||
122 | #define BF_BCH_STATUS0_RSVD1(v) (((v) << 5) & 0xe0) | ||
123 | #define BP_BCH_STATUS0_ALLONES 4 | ||
124 | #define BM_BCH_STATUS0_ALLONES 0x10 | ||
125 | #define BF_BCH_STATUS0_ALLONES(v) (((v) << 4) & 0x10) | ||
126 | #define BP_BCH_STATUS0_CORRECTED 3 | ||
127 | #define BM_BCH_STATUS0_CORRECTED 0x8 | ||
128 | #define BF_BCH_STATUS0_CORRECTED(v) (((v) << 3) & 0x8) | ||
129 | #define BP_BCH_STATUS0_UNCORRECTABLE 2 | ||
130 | #define BM_BCH_STATUS0_UNCORRECTABLE 0x4 | ||
131 | #define BF_BCH_STATUS0_UNCORRECTABLE(v) (((v) << 2) & 0x4) | ||
132 | #define BP_BCH_STATUS0_RSVD0 0 | ||
133 | #define BM_BCH_STATUS0_RSVD0 0x3 | ||
134 | #define BF_BCH_STATUS0_RSVD0(v) (((v) << 0) & 0x3) | ||
135 | |||
136 | /** | ||
137 | * Register: HW_BCH_MODE | ||
138 | * Address: 0x20 | ||
139 | * SCT: no | ||
140 | */ | ||
141 | #define HW_BCH_MODE (*(volatile unsigned long *)(REGS_BCH_BASE + 0x20)) | ||
142 | #define BP_BCH_MODE_RSVD 8 | ||
143 | #define BM_BCH_MODE_RSVD 0xffffff00 | ||
144 | #define BF_BCH_MODE_RSVD(v) (((v) << 8) & 0xffffff00) | ||
145 | #define BP_BCH_MODE_ERASE_THRESHOLD 0 | ||
146 | #define BM_BCH_MODE_ERASE_THRESHOLD 0xff | ||
147 | #define BF_BCH_MODE_ERASE_THRESHOLD(v) (((v) << 0) & 0xff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_BCH_ENCODEPTR | ||
151 | * Address: 0x30 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_BCH_ENCODEPTR (*(volatile unsigned long *)(REGS_BCH_BASE + 0x30)) | ||
155 | #define BP_BCH_ENCODEPTR_ADDR 0 | ||
156 | #define BM_BCH_ENCODEPTR_ADDR 0xffffffff | ||
157 | #define BF_BCH_ENCODEPTR_ADDR(v) (((v) << 0) & 0xffffffff) | ||
158 | |||
159 | /** | ||
160 | * Register: HW_BCH_DATAPTR | ||
161 | * Address: 0x40 | ||
162 | * SCT: no | ||
163 | */ | ||
164 | #define HW_BCH_DATAPTR (*(volatile unsigned long *)(REGS_BCH_BASE + 0x40)) | ||
165 | #define BP_BCH_DATAPTR_ADDR 0 | ||
166 | #define BM_BCH_DATAPTR_ADDR 0xffffffff | ||
167 | #define BF_BCH_DATAPTR_ADDR(v) (((v) << 0) & 0xffffffff) | ||
168 | |||
169 | /** | ||
170 | * Register: HW_BCH_METAPTR | ||
171 | * Address: 0x50 | ||
172 | * SCT: no | ||
173 | */ | ||
174 | #define HW_BCH_METAPTR (*(volatile unsigned long *)(REGS_BCH_BASE + 0x50)) | ||
175 | #define BP_BCH_METAPTR_ADDR 0 | ||
176 | #define BM_BCH_METAPTR_ADDR 0xffffffff | ||
177 | #define BF_BCH_METAPTR_ADDR(v) (((v) << 0) & 0xffffffff) | ||
178 | |||
179 | /** | ||
180 | * Register: HW_BCH_LAYOUTSELECT | ||
181 | * Address: 0x70 | ||
182 | * SCT: no | ||
183 | */ | ||
184 | #define HW_BCH_LAYOUTSELECT (*(volatile unsigned long *)(REGS_BCH_BASE + 0x70)) | ||
185 | #define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 | ||
186 | #define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xc0000000 | ||
187 | #define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) (((v) << 30) & 0xc0000000) | ||
188 | #define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 | ||
189 | #define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 | ||
190 | #define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) (((v) << 28) & 0x30000000) | ||
191 | #define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 | ||
192 | #define BM_BCH_LAYOUTSELECT_CS13_SELECT 0xc000000 | ||
193 | #define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) (((v) << 26) & 0xc000000) | ||
194 | #define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 | ||
195 | #define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x3000000 | ||
196 | #define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) (((v) << 24) & 0x3000000) | ||
197 | #define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 | ||
198 | #define BM_BCH_LAYOUTSELECT_CS11_SELECT 0xc00000 | ||
199 | #define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) (((v) << 22) & 0xc00000) | ||
200 | #define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 | ||
201 | #define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x300000 | ||
202 | #define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) (((v) << 20) & 0x300000) | ||
203 | #define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 | ||
204 | #define BM_BCH_LAYOUTSELECT_CS9_SELECT 0xc0000 | ||
205 | #define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) (((v) << 18) & 0xc0000) | ||
206 | #define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 | ||
207 | #define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x30000 | ||
208 | #define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) (((v) << 16) & 0x30000) | ||
209 | #define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 | ||
210 | #define BM_BCH_LAYOUTSELECT_CS7_SELECT 0xc000 | ||
211 | #define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) (((v) << 14) & 0xc000) | ||
212 | #define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 | ||
213 | #define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x3000 | ||
214 | #define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) (((v) << 12) & 0x3000) | ||
215 | #define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 | ||
216 | #define BM_BCH_LAYOUTSELECT_CS5_SELECT 0xc00 | ||
217 | #define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) (((v) << 10) & 0xc00) | ||
218 | #define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 | ||
219 | #define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x300 | ||
220 | #define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) (((v) << 8) & 0x300) | ||
221 | #define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 | ||
222 | #define BM_BCH_LAYOUTSELECT_CS3_SELECT 0xc0 | ||
223 | #define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) (((v) << 6) & 0xc0) | ||
224 | #define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 | ||
225 | #define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x30 | ||
226 | #define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) (((v) << 4) & 0x30) | ||
227 | #define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 | ||
228 | #define BM_BCH_LAYOUTSELECT_CS1_SELECT 0xc | ||
229 | #define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) (((v) << 2) & 0xc) | ||
230 | #define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 | ||
231 | #define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x3 | ||
232 | #define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) (((v) << 0) & 0x3) | ||
233 | |||
234 | /** | ||
235 | * Register: HW_BCH_FLASH0LAYOUT0 | ||
236 | * Address: 0x80 | ||
237 | * SCT: no | ||
238 | */ | ||
239 | #define HW_BCH_FLASH0LAYOUT0 (*(volatile unsigned long *)(REGS_BCH_BASE + 0x80)) | ||
240 | #define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 | ||
241 | #define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xff000000 | ||
242 | #define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) (((v) << 24) & 0xff000000) | ||
243 | #define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 | ||
244 | #define BM_BCH_FLASH0LAYOUT0_META_SIZE 0xff0000 | ||
245 | #define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) (((v) << 16) & 0xff0000) | ||
246 | #define BP_BCH_FLASH0LAYOUT0_ECC0 12 | ||
247 | #define BM_BCH_FLASH0LAYOUT0_ECC0 0xf000 | ||
248 | #define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 | ||
249 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 | ||
250 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 | ||
251 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 | ||
252 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 | ||
253 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 | ||
254 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 | ||
255 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 | ||
256 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 | ||
257 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 | ||
258 | #define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xa | ||
259 | #define BF_BCH_FLASH0LAYOUT0_ECC0(v) (((v) << 12) & 0xf000) | ||
260 | #define BF_BCH_FLASH0LAYOUT0_ECC0_V(v) ((BV_BCH_FLASH0LAYOUT0_ECC0__##v << 12) & 0xf000) | ||
261 | #define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 | ||
262 | #define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0xfff | ||
263 | #define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) (((v) << 0) & 0xfff) | ||
264 | |||
265 | /** | ||
266 | * Register: HW_BCH_FLASH0LAYOUT1 | ||
267 | * Address: 0x90 | ||
268 | * SCT: no | ||
269 | */ | ||
270 | #define HW_BCH_FLASH0LAYOUT1 (*(volatile unsigned long *)(REGS_BCH_BASE + 0x90)) | ||
271 | #define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 | ||
272 | #define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xffff0000 | ||
273 | #define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (((v) << 16) & 0xffff0000) | ||
274 | #define BP_BCH_FLASH0LAYOUT1_ECCN 12 | ||
275 | #define BM_BCH_FLASH0LAYOUT1_ECCN 0xf000 | ||
276 | #define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 | ||
277 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 | ||
278 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 | ||
279 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 | ||
280 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 | ||
281 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 | ||
282 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 | ||
283 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 | ||
284 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 | ||
285 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 | ||
286 | #define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xa | ||
287 | #define BF_BCH_FLASH0LAYOUT1_ECCN(v) (((v) << 12) & 0xf000) | ||
288 | #define BF_BCH_FLASH0LAYOUT1_ECCN_V(v) ((BV_BCH_FLASH0LAYOUT1_ECCN__##v << 12) & 0xf000) | ||
289 | #define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 | ||
290 | #define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0xfff | ||
291 | #define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) (((v) << 0) & 0xfff) | ||
292 | |||
293 | /** | ||
294 | * Register: HW_BCH_FLASH1LAYOUT0 | ||
295 | * Address: 0xa0 | ||
296 | * SCT: no | ||
297 | */ | ||
298 | #define HW_BCH_FLASH1LAYOUT0 (*(volatile unsigned long *)(REGS_BCH_BASE + 0xa0)) | ||
299 | #define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 | ||
300 | #define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xff000000 | ||
301 | #define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) (((v) << 24) & 0xff000000) | ||
302 | #define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 | ||
303 | #define BM_BCH_FLASH1LAYOUT0_META_SIZE 0xff0000 | ||
304 | #define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) (((v) << 16) & 0xff0000) | ||
305 | #define BP_BCH_FLASH1LAYOUT0_ECC0 12 | ||
306 | #define BM_BCH_FLASH1LAYOUT0_ECC0 0xf000 | ||
307 | #define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 | ||
308 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 | ||
309 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 | ||
310 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 | ||
311 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 | ||
312 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 | ||
313 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 | ||
314 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 | ||
315 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 | ||
316 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 | ||
317 | #define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xa | ||
318 | #define BF_BCH_FLASH1LAYOUT0_ECC0(v) (((v) << 12) & 0xf000) | ||
319 | #define BF_BCH_FLASH1LAYOUT0_ECC0_V(v) ((BV_BCH_FLASH1LAYOUT0_ECC0__##v << 12) & 0xf000) | ||
320 | #define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 | ||
321 | #define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0xfff | ||
322 | #define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) (((v) << 0) & 0xfff) | ||
323 | |||
324 | /** | ||
325 | * Register: HW_BCH_FLASH1LAYOUT1 | ||
326 | * Address: 0xb0 | ||
327 | * SCT: no | ||
328 | */ | ||
329 | #define HW_BCH_FLASH1LAYOUT1 (*(volatile unsigned long *)(REGS_BCH_BASE + 0xb0)) | ||
330 | #define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 | ||
331 | #define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xffff0000 | ||
332 | #define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) (((v) << 16) & 0xffff0000) | ||
333 | #define BP_BCH_FLASH1LAYOUT1_ECCN 12 | ||
334 | #define BM_BCH_FLASH1LAYOUT1_ECCN 0xf000 | ||
335 | #define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 | ||
336 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 | ||
337 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 | ||
338 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 | ||
339 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 | ||
340 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 | ||
341 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 | ||
342 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 | ||
343 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 | ||
344 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 | ||
345 | #define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xa | ||
346 | #define BF_BCH_FLASH1LAYOUT1_ECCN(v) (((v) << 12) & 0xf000) | ||
347 | #define BF_BCH_FLASH1LAYOUT1_ECCN_V(v) ((BV_BCH_FLASH1LAYOUT1_ECCN__##v << 12) & 0xf000) | ||
348 | #define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 | ||
349 | #define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0xfff | ||
350 | #define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) (((v) << 0) & 0xfff) | ||
351 | |||
352 | /** | ||
353 | * Register: HW_BCH_FLASH2LAYOUT0 | ||
354 | * Address: 0xc0 | ||
355 | * SCT: no | ||
356 | */ | ||
357 | #define HW_BCH_FLASH2LAYOUT0 (*(volatile unsigned long *)(REGS_BCH_BASE + 0xc0)) | ||
358 | #define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 | ||
359 | #define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xff000000 | ||
360 | #define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) (((v) << 24) & 0xff000000) | ||
361 | #define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 | ||
362 | #define BM_BCH_FLASH2LAYOUT0_META_SIZE 0xff0000 | ||
363 | #define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) (((v) << 16) & 0xff0000) | ||
364 | #define BP_BCH_FLASH2LAYOUT0_ECC0 12 | ||
365 | #define BM_BCH_FLASH2LAYOUT0_ECC0 0xf000 | ||
366 | #define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 | ||
367 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 | ||
368 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 | ||
369 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 | ||
370 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 | ||
371 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 | ||
372 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 | ||
373 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 | ||
374 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 | ||
375 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 | ||
376 | #define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xa | ||
377 | #define BF_BCH_FLASH2LAYOUT0_ECC0(v) (((v) << 12) & 0xf000) | ||
378 | #define BF_BCH_FLASH2LAYOUT0_ECC0_V(v) ((BV_BCH_FLASH2LAYOUT0_ECC0__##v << 12) & 0xf000) | ||
379 | #define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 | ||
380 | #define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0xfff | ||
381 | #define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) (((v) << 0) & 0xfff) | ||
382 | |||
383 | /** | ||
384 | * Register: HW_BCH_FLASH2LAYOUT1 | ||
385 | * Address: 0xd0 | ||
386 | * SCT: no | ||
387 | */ | ||
388 | #define HW_BCH_FLASH2LAYOUT1 (*(volatile unsigned long *)(REGS_BCH_BASE + 0xd0)) | ||
389 | #define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 | ||
390 | #define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xffff0000 | ||
391 | #define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) (((v) << 16) & 0xffff0000) | ||
392 | #define BP_BCH_FLASH2LAYOUT1_ECCN 12 | ||
393 | #define BM_BCH_FLASH2LAYOUT1_ECCN 0xf000 | ||
394 | #define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 | ||
395 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 | ||
396 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 | ||
397 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 | ||
398 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 | ||
399 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 | ||
400 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 | ||
401 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 | ||
402 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 | ||
403 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 | ||
404 | #define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xa | ||
405 | #define BF_BCH_FLASH2LAYOUT1_ECCN(v) (((v) << 12) & 0xf000) | ||
406 | #define BF_BCH_FLASH2LAYOUT1_ECCN_V(v) ((BV_BCH_FLASH2LAYOUT1_ECCN__##v << 12) & 0xf000) | ||
407 | #define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 | ||
408 | #define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0xfff | ||
409 | #define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) (((v) << 0) & 0xfff) | ||
410 | |||
411 | /** | ||
412 | * Register: HW_BCH_FLASH3LAYOUT0 | ||
413 | * Address: 0xe0 | ||
414 | * SCT: no | ||
415 | */ | ||
416 | #define HW_BCH_FLASH3LAYOUT0 (*(volatile unsigned long *)(REGS_BCH_BASE + 0xe0)) | ||
417 | #define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 | ||
418 | #define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xff000000 | ||
419 | #define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) (((v) << 24) & 0xff000000) | ||
420 | #define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 | ||
421 | #define BM_BCH_FLASH3LAYOUT0_META_SIZE 0xff0000 | ||
422 | #define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) (((v) << 16) & 0xff0000) | ||
423 | #define BP_BCH_FLASH3LAYOUT0_ECC0 12 | ||
424 | #define BM_BCH_FLASH3LAYOUT0_ECC0 0xf000 | ||
425 | #define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 | ||
426 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 | ||
427 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 | ||
428 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 | ||
429 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 | ||
430 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 | ||
431 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 | ||
432 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 | ||
433 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 | ||
434 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 | ||
435 | #define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xa | ||
436 | #define BF_BCH_FLASH3LAYOUT0_ECC0(v) (((v) << 12) & 0xf000) | ||
437 | #define BF_BCH_FLASH3LAYOUT0_ECC0_V(v) ((BV_BCH_FLASH3LAYOUT0_ECC0__##v << 12) & 0xf000) | ||
438 | #define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 | ||
439 | #define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0xfff | ||
440 | #define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) (((v) << 0) & 0xfff) | ||
441 | |||
442 | /** | ||
443 | * Register: HW_BCH_FLASH3LAYOUT1 | ||
444 | * Address: 0xf0 | ||
445 | * SCT: no | ||
446 | */ | ||
447 | #define HW_BCH_FLASH3LAYOUT1 (*(volatile unsigned long *)(REGS_BCH_BASE + 0xf0)) | ||
448 | #define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 | ||
449 | #define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xffff0000 | ||
450 | #define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) (((v) << 16) & 0xffff0000) | ||
451 | #define BP_BCH_FLASH3LAYOUT1_ECCN 12 | ||
452 | #define BM_BCH_FLASH3LAYOUT1_ECCN 0xf000 | ||
453 | #define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 | ||
454 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 | ||
455 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 | ||
456 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 | ||
457 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 | ||
458 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 | ||
459 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 | ||
460 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 | ||
461 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 | ||
462 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 | ||
463 | #define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xa | ||
464 | #define BF_BCH_FLASH3LAYOUT1_ECCN(v) (((v) << 12) & 0xf000) | ||
465 | #define BF_BCH_FLASH3LAYOUT1_ECCN_V(v) ((BV_BCH_FLASH3LAYOUT1_ECCN__##v << 12) & 0xf000) | ||
466 | #define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 | ||
467 | #define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0xfff | ||
468 | #define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) (((v) << 0) & 0xfff) | ||
469 | |||
470 | /** | ||
471 | * Register: HW_BCH_DEBUG0 | ||
472 | * Address: 0x100 | ||
473 | * SCT: yes | ||
474 | */ | ||
475 | #define HW_BCH_DEBUG0 (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x0)) | ||
476 | #define HW_BCH_DEBUG0_SET (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x4)) | ||
477 | #define HW_BCH_DEBUG0_CLR (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x8)) | ||
478 | #define HW_BCH_DEBUG0_TOG (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0xc)) | ||
479 | #define BP_BCH_DEBUG0_RSVD1 27 | ||
480 | #define BM_BCH_DEBUG0_RSVD1 0xf8000000 | ||
481 | #define BF_BCH_DEBUG0_RSVD1(v) (((v) << 27) & 0xf8000000) | ||
482 | #define BP_BCH_DEBUG0_ROM_BIST_ENABLE 26 | ||
483 | #define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x4000000 | ||
484 | #define BF_BCH_DEBUG0_ROM_BIST_ENABLE(v) (((v) << 26) & 0x4000000) | ||
485 | #define BP_BCH_DEBUG0_ROM_BIST_COMPLETE 25 | ||
486 | #define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x2000000 | ||
487 | #define BF_BCH_DEBUG0_ROM_BIST_COMPLETE(v) (((v) << 25) & 0x2000000) | ||
488 | #define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 | ||
489 | #define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x1ff0000 | ||
490 | #define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 | ||
491 | #define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 | ||
492 | #define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << 16) & 0x1ff0000) | ||
493 | #define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v) ((BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000) | ||
494 | #define BP_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 15 | ||
495 | #define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x8000 | ||
496 | #define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v) (((v) << 15) & 0x8000) | ||
497 | #define BP_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 14 | ||
498 | #define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x4000 | ||
499 | #define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 | ||
500 | #define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 | ||
501 | #define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) (((v) << 14) & 0x4000) | ||
502 | #define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v) ((BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000) | ||
503 | #define BP_BCH_DEBUG0_KES_DEBUG_MODE4K 13 | ||
504 | #define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x2000 | ||
505 | #define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 | ||
506 | #define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 | ||
507 | #define BF_BCH_DEBUG0_KES_DEBUG_MODE4K(v) (((v) << 13) & 0x2000) | ||
508 | #define BF_BCH_DEBUG0_KES_DEBUG_MODE4K_V(v) ((BV_BCH_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000) | ||
509 | #define BP_BCH_DEBUG0_KES_DEBUG_KICK 12 | ||
510 | #define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x1000 | ||
511 | #define BF_BCH_DEBUG0_KES_DEBUG_KICK(v) (((v) << 12) & 0x1000) | ||
512 | #define BP_BCH_DEBUG0_KES_STANDALONE 11 | ||
513 | #define BM_BCH_DEBUG0_KES_STANDALONE 0x800 | ||
514 | #define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 | ||
515 | #define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 | ||
516 | #define BF_BCH_DEBUG0_KES_STANDALONE(v) (((v) << 11) & 0x800) | ||
517 | #define BF_BCH_DEBUG0_KES_STANDALONE_V(v) ((BV_BCH_DEBUG0_KES_STANDALONE__##v << 11) & 0x800) | ||
518 | #define BP_BCH_DEBUG0_KES_DEBUG_STEP 10 | ||
519 | #define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x400 | ||
520 | #define BF_BCH_DEBUG0_KES_DEBUG_STEP(v) (((v) << 10) & 0x400) | ||
521 | #define BP_BCH_DEBUG0_KES_DEBUG_STALL 9 | ||
522 | #define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x200 | ||
523 | #define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 | ||
524 | #define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 | ||
525 | #define BF_BCH_DEBUG0_KES_DEBUG_STALL(v) (((v) << 9) & 0x200) | ||
526 | #define BF_BCH_DEBUG0_KES_DEBUG_STALL_V(v) ((BV_BCH_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200) | ||
527 | #define BP_BCH_DEBUG0_BM_KES_TEST_BYPASS 8 | ||
528 | #define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x100 | ||
529 | #define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 | ||
530 | #define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 | ||
531 | #define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(v) (((v) << 8) & 0x100) | ||
532 | #define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS_V(v) ((BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100) | ||
533 | #define BP_BCH_DEBUG0_RSVD0 6 | ||
534 | #define BM_BCH_DEBUG0_RSVD0 0xc0 | ||
535 | #define BF_BCH_DEBUG0_RSVD0(v) (((v) << 6) & 0xc0) | ||
536 | #define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 | ||
537 | #define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x3f | ||
538 | #define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) (((v) << 0) & 0x3f) | ||
539 | |||
540 | /** | ||
541 | * Register: HW_BCH_DBGKESREAD | ||
542 | * Address: 0x110 | ||
543 | * SCT: no | ||
544 | */ | ||
545 | #define HW_BCH_DBGKESREAD (*(volatile unsigned long *)(REGS_BCH_BASE + 0x110)) | ||
546 | #define BP_BCH_DBGKESREAD_VALUES 0 | ||
547 | #define BM_BCH_DBGKESREAD_VALUES 0xffffffff | ||
548 | #define BF_BCH_DBGKESREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
549 | |||
550 | /** | ||
551 | * Register: HW_BCH_DBGCSFEREAD | ||
552 | * Address: 0x120 | ||
553 | * SCT: no | ||
554 | */ | ||
555 | #define HW_BCH_DBGCSFEREAD (*(volatile unsigned long *)(REGS_BCH_BASE + 0x120)) | ||
556 | #define BP_BCH_DBGCSFEREAD_VALUES 0 | ||
557 | #define BM_BCH_DBGCSFEREAD_VALUES 0xffffffff | ||
558 | #define BF_BCH_DBGCSFEREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
559 | |||
560 | /** | ||
561 | * Register: HW_BCH_DBGSYNDGENREAD | ||
562 | * Address: 0x130 | ||
563 | * SCT: no | ||
564 | */ | ||
565 | #define HW_BCH_DBGSYNDGENREAD (*(volatile unsigned long *)(REGS_BCH_BASE + 0x130)) | ||
566 | #define BP_BCH_DBGSYNDGENREAD_VALUES 0 | ||
567 | #define BM_BCH_DBGSYNDGENREAD_VALUES 0xffffffff | ||
568 | #define BF_BCH_DBGSYNDGENREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
569 | |||
570 | /** | ||
571 | * Register: HW_BCH_DBGAHBMREAD | ||
572 | * Address: 0x140 | ||
573 | * SCT: no | ||
574 | */ | ||
575 | #define HW_BCH_DBGAHBMREAD (*(volatile unsigned long *)(REGS_BCH_BASE + 0x140)) | ||
576 | #define BP_BCH_DBGAHBMREAD_VALUES 0 | ||
577 | #define BM_BCH_DBGAHBMREAD_VALUES 0xffffffff | ||
578 | #define BF_BCH_DBGAHBMREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
579 | |||
580 | /** | ||
581 | * Register: HW_BCH_BLOCKNAME | ||
582 | * Address: 0x150 | ||
583 | * SCT: no | ||
584 | */ | ||
585 | #define HW_BCH_BLOCKNAME (*(volatile unsigned long *)(REGS_BCH_BASE + 0x150)) | ||
586 | #define BP_BCH_BLOCKNAME_NAME 0 | ||
587 | #define BM_BCH_BLOCKNAME_NAME 0xffffffff | ||
588 | #define BF_BCH_BLOCKNAME_NAME(v) (((v) << 0) & 0xffffffff) | ||
589 | |||
590 | /** | ||
591 | * Register: HW_BCH_VERSION | ||
592 | * Address: 0x160 | ||
593 | * SCT: no | ||
594 | */ | ||
595 | #define HW_BCH_VERSION (*(volatile unsigned long *)(REGS_BCH_BASE + 0x160)) | ||
596 | #define BP_BCH_VERSION_MAJOR 24 | ||
597 | #define BM_BCH_VERSION_MAJOR 0xff000000 | ||
598 | #define BF_BCH_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
599 | #define BP_BCH_VERSION_MINOR 16 | ||
600 | #define BM_BCH_VERSION_MINOR 0xff0000 | ||
601 | #define BF_BCH_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
602 | #define BP_BCH_VERSION_STEP 0 | ||
603 | #define BM_BCH_VERSION_STEP 0xffff | ||
604 | #define BF_BCH_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
605 | |||
606 | #endif /* __HEADERGEN__IMX233__BCH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h new file mode 100644 index 0000000000..0dca5dbe62 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h | |||
@@ -0,0 +1,655 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__CLKCTRL__H__ | ||
24 | #define __HEADERGEN__IMX233__CLKCTRL__H__ | ||
25 | |||
26 | #define REGS_CLKCTRL_BASE (0x80040000) | ||
27 | |||
28 | #define REGS_CLKCTRL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_CLKCTRL_PLLCTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_CLKCTRL_PLLCTRL0_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_CLKCTRL_PLLCTRL0_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_CLKCTRL_PLLCTRL0_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 | ||
40 | #define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xc0000000 | ||
41 | #define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) (((v) << 30) & 0xc0000000) | ||
42 | #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 | ||
43 | #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 | ||
44 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 | ||
45 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 | ||
46 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 | ||
47 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 | ||
48 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) (((v) << 28) & 0x30000000) | ||
49 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000) | ||
50 | #define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 | ||
51 | #define BM_CLKCTRL_PLLCTRL0_RSRVD5 0xc000000 | ||
52 | #define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) (((v) << 26) & 0xc000000) | ||
53 | #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 | ||
54 | #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x3000000 | ||
55 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 | ||
56 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 | ||
57 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 | ||
58 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 | ||
59 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) (((v) << 24) & 0x3000000) | ||
60 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000) | ||
61 | #define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 | ||
62 | #define BM_CLKCTRL_PLLCTRL0_RSRVD4 0xc00000 | ||
63 | #define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) (((v) << 22) & 0xc00000) | ||
64 | #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 | ||
65 | #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x300000 | ||
66 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 | ||
67 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 | ||
68 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 | ||
69 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 | ||
70 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) (((v) << 20) & 0x300000) | ||
71 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000) | ||
72 | #define BP_CLKCTRL_PLLCTRL0_RSRVD3 19 | ||
73 | #define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x80000 | ||
74 | #define BF_CLKCTRL_PLLCTRL0_RSRVD3(v) (((v) << 19) & 0x80000) | ||
75 | #define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 | ||
76 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 | ||
77 | #define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) << 18) & 0x40000) | ||
78 | #define BP_CLKCTRL_PLLCTRL0_RSRVD2 17 | ||
79 | #define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x20000 | ||
80 | #define BF_CLKCTRL_PLLCTRL0_RSRVD2(v) (((v) << 17) & 0x20000) | ||
81 | #define BP_CLKCTRL_PLLCTRL0_POWER 16 | ||
82 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 | ||
83 | #define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) << 16) & 0x10000) | ||
84 | #define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 | ||
85 | #define BM_CLKCTRL_PLLCTRL0_RSRVD1 0xffff | ||
86 | #define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) (((v) << 0) & 0xffff) | ||
87 | |||
88 | /** | ||
89 | * Register: HW_CLKCTRL_PLLCTRL1 | ||
90 | * Address: 0x10 | ||
91 | * SCT: no | ||
92 | */ | ||
93 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10)) | ||
94 | #define BP_CLKCTRL_PLLCTRL1_LOCK 31 | ||
95 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
96 | #define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) << 31) & 0x80000000) | ||
97 | #define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 | ||
98 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
99 | #define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) << 30) & 0x40000000) | ||
100 | #define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 | ||
101 | #define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3fff0000 | ||
102 | #define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) (((v) << 16) & 0x3fff0000) | ||
103 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
104 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff | ||
105 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) << 0) & 0xffff) | ||
106 | |||
107 | /** | ||
108 | * Register: HW_CLKCTRL_CPU | ||
109 | * Address: 0x20 | ||
110 | * SCT: yes | ||
111 | */ | ||
112 | #define HW_CLKCTRL_CPU (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0)) | ||
113 | #define HW_CLKCTRL_CPU_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4)) | ||
114 | #define HW_CLKCTRL_CPU_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8)) | ||
115 | #define HW_CLKCTRL_CPU_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc)) | ||
116 | #define BP_CLKCTRL_CPU_RSRVD5 30 | ||
117 | #define BM_CLKCTRL_CPU_RSRVD5 0xc0000000 | ||
118 | #define BF_CLKCTRL_CPU_RSRVD5(v) (((v) << 30) & 0xc0000000) | ||
119 | #define BP_CLKCTRL_CPU_BUSY_REF_XTAL 29 | ||
120 | #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 | ||
121 | #define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
122 | #define BP_CLKCTRL_CPU_BUSY_REF_CPU 28 | ||
123 | #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 | ||
124 | #define BF_CLKCTRL_CPU_BUSY_REF_CPU(v) (((v) << 28) & 0x10000000) | ||
125 | #define BP_CLKCTRL_CPU_RSRVD4 27 | ||
126 | #define BM_CLKCTRL_CPU_RSRVD4 0x8000000 | ||
127 | #define BF_CLKCTRL_CPU_RSRVD4(v) (((v) << 27) & 0x8000000) | ||
128 | #define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 26 | ||
129 | #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x4000000 | ||
130 | #define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) (((v) << 26) & 0x4000000) | ||
131 | #define BP_CLKCTRL_CPU_DIV_XTAL 16 | ||
132 | #define BM_CLKCTRL_CPU_DIV_XTAL 0x3ff0000 | ||
133 | #define BF_CLKCTRL_CPU_DIV_XTAL(v) (((v) << 16) & 0x3ff0000) | ||
134 | #define BP_CLKCTRL_CPU_RSRVD3 13 | ||
135 | #define BM_CLKCTRL_CPU_RSRVD3 0xe000 | ||
136 | #define BF_CLKCTRL_CPU_RSRVD3(v) (((v) << 13) & 0xe000) | ||
137 | #define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 | ||
138 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 | ||
139 | #define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) << 12) & 0x1000) | ||
140 | #define BP_CLKCTRL_CPU_RSRVD2 11 | ||
141 | #define BM_CLKCTRL_CPU_RSRVD2 0x800 | ||
142 | #define BF_CLKCTRL_CPU_RSRVD2(v) (((v) << 11) & 0x800) | ||
143 | #define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN 10 | ||
144 | #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x400 | ||
145 | #define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) (((v) << 10) & 0x400) | ||
146 | #define BP_CLKCTRL_CPU_RSRVD1 6 | ||
147 | #define BM_CLKCTRL_CPU_RSRVD1 0x3c0 | ||
148 | #define BF_CLKCTRL_CPU_RSRVD1(v) (((v) << 6) & 0x3c0) | ||
149 | #define BP_CLKCTRL_CPU_DIV_CPU 0 | ||
150 | #define BM_CLKCTRL_CPU_DIV_CPU 0x3f | ||
151 | #define BF_CLKCTRL_CPU_DIV_CPU(v) (((v) << 0) & 0x3f) | ||
152 | |||
153 | /** | ||
154 | * Register: HW_CLKCTRL_HBUS | ||
155 | * Address: 0x30 | ||
156 | * SCT: yes | ||
157 | */ | ||
158 | #define HW_CLKCTRL_HBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0)) | ||
159 | #define HW_CLKCTRL_HBUS_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4)) | ||
160 | #define HW_CLKCTRL_HBUS_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8)) | ||
161 | #define HW_CLKCTRL_HBUS_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc)) | ||
162 | #define BP_CLKCTRL_HBUS_RSRVD4 30 | ||
163 | #define BM_CLKCTRL_HBUS_RSRVD4 0xc0000000 | ||
164 | #define BF_CLKCTRL_HBUS_RSRVD4(v) (((v) << 30) & 0xc0000000) | ||
165 | #define BP_CLKCTRL_HBUS_BUSY 29 | ||
166 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
167 | #define BF_CLKCTRL_HBUS_BUSY(v) (((v) << 29) & 0x20000000) | ||
168 | #define BP_CLKCTRL_HBUS_DCP_AS_ENABLE 28 | ||
169 | #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 | ||
170 | #define BF_CLKCTRL_HBUS_DCP_AS_ENABLE(v) (((v) << 28) & 0x10000000) | ||
171 | #define BP_CLKCTRL_HBUS_PXP_AS_ENABLE 27 | ||
172 | #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x8000000 | ||
173 | #define BF_CLKCTRL_HBUS_PXP_AS_ENABLE(v) (((v) << 27) & 0x8000000) | ||
174 | #define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 26 | ||
175 | #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x4000000 | ||
176 | #define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) (((v) << 26) & 0x4000000) | ||
177 | #define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 25 | ||
178 | #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x2000000 | ||
179 | #define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) (((v) << 25) & 0x2000000) | ||
180 | #define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 24 | ||
181 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x1000000 | ||
182 | #define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) (((v) << 24) & 0x1000000) | ||
183 | #define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 23 | ||
184 | #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x800000 | ||
185 | #define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) (((v) << 23) & 0x800000) | ||
186 | #define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 22 | ||
187 | #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x400000 | ||
188 | #define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) (((v) << 22) & 0x400000) | ||
189 | #define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 21 | ||
190 | #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x200000 | ||
191 | #define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) (((v) << 21) & 0x200000) | ||
192 | #define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 | ||
193 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 | ||
194 | #define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) << 20) & 0x100000) | ||
195 | #define BP_CLKCTRL_HBUS_RSRVD2 19 | ||
196 | #define BM_CLKCTRL_HBUS_RSRVD2 0x80000 | ||
197 | #define BF_CLKCTRL_HBUS_RSRVD2(v) (((v) << 19) & 0x80000) | ||
198 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
199 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x70000 | ||
200 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
201 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
202 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
203 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
204 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 | ||
205 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 | ||
206 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) << 16) & 0x70000) | ||
207 | #define BF_CLKCTRL_HBUS_SLOW_DIV_V(v) ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000) | ||
208 | #define BP_CLKCTRL_HBUS_RSRVD1 6 | ||
209 | #define BM_CLKCTRL_HBUS_RSRVD1 0xffc0 | ||
210 | #define BF_CLKCTRL_HBUS_RSRVD1(v) (((v) << 6) & 0xffc0) | ||
211 | #define BP_CLKCTRL_HBUS_DIV_FRAC_EN 5 | ||
212 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x20 | ||
213 | #define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v) (((v) << 5) & 0x20) | ||
214 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
215 | #define BM_CLKCTRL_HBUS_DIV 0x1f | ||
216 | #define BF_CLKCTRL_HBUS_DIV(v) (((v) << 0) & 0x1f) | ||
217 | |||
218 | /** | ||
219 | * Register: HW_CLKCTRL_XBUS | ||
220 | * Address: 0x40 | ||
221 | * SCT: no | ||
222 | */ | ||
223 | #define HW_CLKCTRL_XBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40)) | ||
224 | #define BP_CLKCTRL_XBUS_BUSY 31 | ||
225 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
226 | #define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000) | ||
227 | #define BP_CLKCTRL_XBUS_RSRVD1 11 | ||
228 | #define BM_CLKCTRL_XBUS_RSRVD1 0x7ffff800 | ||
229 | #define BF_CLKCTRL_XBUS_RSRVD1(v) (((v) << 11) & 0x7ffff800) | ||
230 | #define BP_CLKCTRL_XBUS_DIV_FRAC_EN 10 | ||
231 | #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x400 | ||
232 | #define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
233 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
234 | #define BM_CLKCTRL_XBUS_DIV 0x3ff | ||
235 | #define BF_CLKCTRL_XBUS_DIV(v) (((v) << 0) & 0x3ff) | ||
236 | |||
237 | /** | ||
238 | * Register: HW_CLKCTRL_XTAL | ||
239 | * Address: 0x50 | ||
240 | * SCT: yes | ||
241 | */ | ||
242 | #define HW_CLKCTRL_XTAL (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0)) | ||
243 | #define HW_CLKCTRL_XTAL_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4)) | ||
244 | #define HW_CLKCTRL_XTAL_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8)) | ||
245 | #define HW_CLKCTRL_XTAL_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc)) | ||
246 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
247 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
248 | #define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) << 31) & 0x80000000) | ||
249 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
250 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
251 | #define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) << 30) & 0x40000000) | ||
252 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
253 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
254 | #define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) << 29) & 0x20000000) | ||
255 | #define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 | ||
256 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
257 | #define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) << 28) & 0x10000000) | ||
258 | #define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 | ||
259 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 | ||
260 | #define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) << 27) & 0x8000000) | ||
261 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
262 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 | ||
263 | #define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) << 26) & 0x4000000) | ||
264 | #define BP_CLKCTRL_XTAL_RSRVD1 2 | ||
265 | #define BM_CLKCTRL_XTAL_RSRVD1 0x3fffffc | ||
266 | #define BF_CLKCTRL_XTAL_RSRVD1(v) (((v) << 2) & 0x3fffffc) | ||
267 | #define BP_CLKCTRL_XTAL_DIV_UART 0 | ||
268 | #define BM_CLKCTRL_XTAL_DIV_UART 0x3 | ||
269 | #define BF_CLKCTRL_XTAL_DIV_UART(v) (((v) << 0) & 0x3) | ||
270 | |||
271 | /** | ||
272 | * Register: HW_CLKCTRL_PIX | ||
273 | * Address: 0x60 | ||
274 | * SCT: no | ||
275 | */ | ||
276 | #define HW_CLKCTRL_PIX (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60)) | ||
277 | #define BP_CLKCTRL_PIX_CLKGATE 31 | ||
278 | #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 | ||
279 | #define BF_CLKCTRL_PIX_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
280 | #define BP_CLKCTRL_PIX_RSRVD2 30 | ||
281 | #define BM_CLKCTRL_PIX_RSRVD2 0x40000000 | ||
282 | #define BF_CLKCTRL_PIX_RSRVD2(v) (((v) << 30) & 0x40000000) | ||
283 | #define BP_CLKCTRL_PIX_BUSY 29 | ||
284 | #define BM_CLKCTRL_PIX_BUSY 0x20000000 | ||
285 | #define BF_CLKCTRL_PIX_BUSY(v) (((v) << 29) & 0x20000000) | ||
286 | #define BP_CLKCTRL_PIX_RSRVD1 13 | ||
287 | #define BM_CLKCTRL_PIX_RSRVD1 0x1fffe000 | ||
288 | #define BF_CLKCTRL_PIX_RSRVD1(v) (((v) << 13) & 0x1fffe000) | ||
289 | #define BP_CLKCTRL_PIX_DIV_FRAC_EN 12 | ||
290 | #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x1000 | ||
291 | #define BF_CLKCTRL_PIX_DIV_FRAC_EN(v) (((v) << 12) & 0x1000) | ||
292 | #define BP_CLKCTRL_PIX_DIV 0 | ||
293 | #define BM_CLKCTRL_PIX_DIV 0xfff | ||
294 | #define BF_CLKCTRL_PIX_DIV(v) (((v) << 0) & 0xfff) | ||
295 | |||
296 | /** | ||
297 | * Register: HW_CLKCTRL_SSP | ||
298 | * Address: 0x70 | ||
299 | * SCT: no | ||
300 | */ | ||
301 | #define HW_CLKCTRL_SSP (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70)) | ||
302 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
303 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
304 | #define BF_CLKCTRL_SSP_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
305 | #define BP_CLKCTRL_SSP_RSRVD2 30 | ||
306 | #define BM_CLKCTRL_SSP_RSRVD2 0x40000000 | ||
307 | #define BF_CLKCTRL_SSP_RSRVD2(v) (((v) << 30) & 0x40000000) | ||
308 | #define BP_CLKCTRL_SSP_BUSY 29 | ||
309 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
310 | #define BF_CLKCTRL_SSP_BUSY(v) (((v) << 29) & 0x20000000) | ||
311 | #define BP_CLKCTRL_SSP_RSRVD1 10 | ||
312 | #define BM_CLKCTRL_SSP_RSRVD1 0x1ffffc00 | ||
313 | #define BF_CLKCTRL_SSP_RSRVD1(v) (((v) << 10) & 0x1ffffc00) | ||
314 | #define BP_CLKCTRL_SSP_DIV_FRAC_EN 9 | ||
315 | #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x200 | ||
316 | #define BF_CLKCTRL_SSP_DIV_FRAC_EN(v) (((v) << 9) & 0x200) | ||
317 | #define BP_CLKCTRL_SSP_DIV 0 | ||
318 | #define BM_CLKCTRL_SSP_DIV 0x1ff | ||
319 | #define BF_CLKCTRL_SSP_DIV(v) (((v) << 0) & 0x1ff) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_CLKCTRL_GPMI | ||
323 | * Address: 0x80 | ||
324 | * SCT: no | ||
325 | */ | ||
326 | #define HW_CLKCTRL_GPMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80)) | ||
327 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
328 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
329 | #define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
330 | #define BP_CLKCTRL_GPMI_RSRVD2 30 | ||
331 | #define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 | ||
332 | #define BF_CLKCTRL_GPMI_RSRVD2(v) (((v) << 30) & 0x40000000) | ||
333 | #define BP_CLKCTRL_GPMI_BUSY 29 | ||
334 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
335 | #define BF_CLKCTRL_GPMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
336 | #define BP_CLKCTRL_GPMI_RSRVD1 11 | ||
337 | #define BM_CLKCTRL_GPMI_RSRVD1 0x1ffff800 | ||
338 | #define BF_CLKCTRL_GPMI_RSRVD1(v) (((v) << 11) & 0x1ffff800) | ||
339 | #define BP_CLKCTRL_GPMI_DIV_FRAC_EN 10 | ||
340 | #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x400 | ||
341 | #define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
342 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
343 | #define BM_CLKCTRL_GPMI_DIV 0x3ff | ||
344 | #define BF_CLKCTRL_GPMI_DIV(v) (((v) << 0) & 0x3ff) | ||
345 | |||
346 | /** | ||
347 | * Register: HW_CLKCTRL_SPDIF | ||
348 | * Address: 0x90 | ||
349 | * SCT: no | ||
350 | */ | ||
351 | #define HW_CLKCTRL_SPDIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90)) | ||
352 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
353 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
354 | #define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
355 | #define BP_CLKCTRL_SPDIF_RSRVD 0 | ||
356 | #define BM_CLKCTRL_SPDIF_RSRVD 0x7fffffff | ||
357 | #define BF_CLKCTRL_SPDIF_RSRVD(v) (((v) << 0) & 0x7fffffff) | ||
358 | |||
359 | /** | ||
360 | * Register: HW_CLKCTRL_EMI | ||
361 | * Address: 0xa0 | ||
362 | * SCT: no | ||
363 | */ | ||
364 | #define HW_CLKCTRL_EMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0)) | ||
365 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
366 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
367 | #define BF_CLKCTRL_EMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
368 | #define BP_CLKCTRL_EMI_SYNC_MODE_EN 30 | ||
369 | #define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 | ||
370 | #define BF_CLKCTRL_EMI_SYNC_MODE_EN(v) (((v) << 30) & 0x40000000) | ||
371 | #define BP_CLKCTRL_EMI_BUSY_REF_XTAL 29 | ||
372 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 | ||
373 | #define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
374 | #define BP_CLKCTRL_EMI_BUSY_REF_EMI 28 | ||
375 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 | ||
376 | #define BF_CLKCTRL_EMI_BUSY_REF_EMI(v) (((v) << 28) & 0x10000000) | ||
377 | #define BP_CLKCTRL_EMI_BUSY_REF_CPU 27 | ||
378 | #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x8000000 | ||
379 | #define BF_CLKCTRL_EMI_BUSY_REF_CPU(v) (((v) << 27) & 0x8000000) | ||
380 | #define BP_CLKCTRL_EMI_BUSY_SYNC_MODE 26 | ||
381 | #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x4000000 | ||
382 | #define BF_CLKCTRL_EMI_BUSY_SYNC_MODE(v) (((v) << 26) & 0x4000000) | ||
383 | #define BP_CLKCTRL_EMI_RSRVD3 18 | ||
384 | #define BM_CLKCTRL_EMI_RSRVD3 0x3fc0000 | ||
385 | #define BF_CLKCTRL_EMI_RSRVD3(v) (((v) << 18) & 0x3fc0000) | ||
386 | #define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC 17 | ||
387 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x20000 | ||
388 | #define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) (((v) << 17) & 0x20000) | ||
389 | #define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE 16 | ||
390 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x10000 | ||
391 | #define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000) | ||
392 | #define BP_CLKCTRL_EMI_RSRVD2 12 | ||
393 | #define BM_CLKCTRL_EMI_RSRVD2 0xf000 | ||
394 | #define BF_CLKCTRL_EMI_RSRVD2(v) (((v) << 12) & 0xf000) | ||
395 | #define BP_CLKCTRL_EMI_DIV_XTAL 8 | ||
396 | #define BM_CLKCTRL_EMI_DIV_XTAL 0xf00 | ||
397 | #define BF_CLKCTRL_EMI_DIV_XTAL(v) (((v) << 8) & 0xf00) | ||
398 | #define BP_CLKCTRL_EMI_RSRVD1 6 | ||
399 | #define BM_CLKCTRL_EMI_RSRVD1 0xc0 | ||
400 | #define BF_CLKCTRL_EMI_RSRVD1(v) (((v) << 6) & 0xc0) | ||
401 | #define BP_CLKCTRL_EMI_DIV_EMI 0 | ||
402 | #define BM_CLKCTRL_EMI_DIV_EMI 0x3f | ||
403 | #define BF_CLKCTRL_EMI_DIV_EMI(v) (((v) << 0) & 0x3f) | ||
404 | |||
405 | /** | ||
406 | * Register: HW_CLKCTRL_IR | ||
407 | * Address: 0xb0 | ||
408 | * SCT: no | ||
409 | */ | ||
410 | #define HW_CLKCTRL_IR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0)) | ||
411 | #define BP_CLKCTRL_IR_CLKGATE 31 | ||
412 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
413 | #define BF_CLKCTRL_IR_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
414 | #define BP_CLKCTRL_IR_RSRVD3 30 | ||
415 | #define BM_CLKCTRL_IR_RSRVD3 0x40000000 | ||
416 | #define BF_CLKCTRL_IR_RSRVD3(v) (((v) << 30) & 0x40000000) | ||
417 | #define BP_CLKCTRL_IR_AUTO_DIV 29 | ||
418 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
419 | #define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) << 29) & 0x20000000) | ||
420 | #define BP_CLKCTRL_IR_IR_BUSY 28 | ||
421 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
422 | #define BF_CLKCTRL_IR_IR_BUSY(v) (((v) << 28) & 0x10000000) | ||
423 | #define BP_CLKCTRL_IR_IROV_BUSY 27 | ||
424 | #define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 | ||
425 | #define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) << 27) & 0x8000000) | ||
426 | #define BP_CLKCTRL_IR_RSRVD2 25 | ||
427 | #define BM_CLKCTRL_IR_RSRVD2 0x6000000 | ||
428 | #define BF_CLKCTRL_IR_RSRVD2(v) (((v) << 25) & 0x6000000) | ||
429 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
430 | #define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 | ||
431 | #define BF_CLKCTRL_IR_IROV_DIV(v) (((v) << 16) & 0x1ff0000) | ||
432 | #define BP_CLKCTRL_IR_RSRVD1 10 | ||
433 | #define BM_CLKCTRL_IR_RSRVD1 0xfc00 | ||
434 | #define BF_CLKCTRL_IR_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
435 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
436 | #define BM_CLKCTRL_IR_IR_DIV 0x3ff | ||
437 | #define BF_CLKCTRL_IR_IR_DIV(v) (((v) << 0) & 0x3ff) | ||
438 | |||
439 | /** | ||
440 | * Register: HW_CLKCTRL_SAIF | ||
441 | * Address: 0xc0 | ||
442 | * SCT: no | ||
443 | */ | ||
444 | #define HW_CLKCTRL_SAIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0)) | ||
445 | #define BP_CLKCTRL_SAIF_CLKGATE 31 | ||
446 | #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 | ||
447 | #define BF_CLKCTRL_SAIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
448 | #define BP_CLKCTRL_SAIF_RSRVD2 30 | ||
449 | #define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 | ||
450 | #define BF_CLKCTRL_SAIF_RSRVD2(v) (((v) << 30) & 0x40000000) | ||
451 | #define BP_CLKCTRL_SAIF_BUSY 29 | ||
452 | #define BM_CLKCTRL_SAIF_BUSY 0x20000000 | ||
453 | #define BF_CLKCTRL_SAIF_BUSY(v) (((v) << 29) & 0x20000000) | ||
454 | #define BP_CLKCTRL_SAIF_RSRVD1 17 | ||
455 | #define BM_CLKCTRL_SAIF_RSRVD1 0x1ffe0000 | ||
456 | #define BF_CLKCTRL_SAIF_RSRVD1(v) (((v) << 17) & 0x1ffe0000) | ||
457 | #define BP_CLKCTRL_SAIF_DIV_FRAC_EN 16 | ||
458 | #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x10000 | ||
459 | #define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v) (((v) << 16) & 0x10000) | ||
460 | #define BP_CLKCTRL_SAIF_DIV 0 | ||
461 | #define BM_CLKCTRL_SAIF_DIV 0xffff | ||
462 | #define BF_CLKCTRL_SAIF_DIV(v) (((v) << 0) & 0xffff) | ||
463 | |||
464 | /** | ||
465 | * Register: HW_CLKCTRL_TV | ||
466 | * Address: 0xd0 | ||
467 | * SCT: no | ||
468 | */ | ||
469 | #define HW_CLKCTRL_TV (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0)) | ||
470 | #define BP_CLKCTRL_TV_CLK_TV108M_GATE 31 | ||
471 | #define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 | ||
472 | #define BF_CLKCTRL_TV_CLK_TV108M_GATE(v) (((v) << 31) & 0x80000000) | ||
473 | #define BP_CLKCTRL_TV_CLK_TV_GATE 30 | ||
474 | #define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 | ||
475 | #define BF_CLKCTRL_TV_CLK_TV_GATE(v) (((v) << 30) & 0x40000000) | ||
476 | #define BP_CLKCTRL_TV_RSRVD 0 | ||
477 | #define BM_CLKCTRL_TV_RSRVD 0x3fffffff | ||
478 | #define BF_CLKCTRL_TV_RSRVD(v) (((v) << 0) & 0x3fffffff) | ||
479 | |||
480 | /** | ||
481 | * Register: HW_CLKCTRL_ETM | ||
482 | * Address: 0xe0 | ||
483 | * SCT: no | ||
484 | */ | ||
485 | #define HW_CLKCTRL_ETM (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0)) | ||
486 | #define BP_CLKCTRL_ETM_CLKGATE 31 | ||
487 | #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 | ||
488 | #define BF_CLKCTRL_ETM_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
489 | #define BP_CLKCTRL_ETM_RSRVD2 30 | ||
490 | #define BM_CLKCTRL_ETM_RSRVD2 0x40000000 | ||
491 | #define BF_CLKCTRL_ETM_RSRVD2(v) (((v) << 30) & 0x40000000) | ||
492 | #define BP_CLKCTRL_ETM_BUSY 29 | ||
493 | #define BM_CLKCTRL_ETM_BUSY 0x20000000 | ||
494 | #define BF_CLKCTRL_ETM_BUSY(v) (((v) << 29) & 0x20000000) | ||
495 | #define BP_CLKCTRL_ETM_RSRVD1 7 | ||
496 | #define BM_CLKCTRL_ETM_RSRVD1 0x1fffff80 | ||
497 | #define BF_CLKCTRL_ETM_RSRVD1(v) (((v) << 7) & 0x1fffff80) | ||
498 | #define BP_CLKCTRL_ETM_DIV_FRAC_EN 6 | ||
499 | #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x40 | ||
500 | #define BF_CLKCTRL_ETM_DIV_FRAC_EN(v) (((v) << 6) & 0x40) | ||
501 | #define BP_CLKCTRL_ETM_DIV 0 | ||
502 | #define BM_CLKCTRL_ETM_DIV 0x3f | ||
503 | #define BF_CLKCTRL_ETM_DIV(v) (((v) << 0) & 0x3f) | ||
504 | |||
505 | /** | ||
506 | * Register: HW_CLKCTRL_FRAC | ||
507 | * Address: 0xf0 | ||
508 | * SCT: yes | ||
509 | */ | ||
510 | #define HW_CLKCTRL_FRAC (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x0)) | ||
511 | #define HW_CLKCTRL_FRAC_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x4)) | ||
512 | #define HW_CLKCTRL_FRAC_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x8)) | ||
513 | #define HW_CLKCTRL_FRAC_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0xc)) | ||
514 | #define BP_CLKCTRL_FRAC_CLKGATEIO 31 | ||
515 | #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 | ||
516 | #define BF_CLKCTRL_FRAC_CLKGATEIO(v) (((v) << 31) & 0x80000000) | ||
517 | #define BP_CLKCTRL_FRAC_IO_STABLE 30 | ||
518 | #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 | ||
519 | #define BF_CLKCTRL_FRAC_IO_STABLE(v) (((v) << 30) & 0x40000000) | ||
520 | #define BP_CLKCTRL_FRAC_IOFRAC 24 | ||
521 | #define BM_CLKCTRL_FRAC_IOFRAC 0x3f000000 | ||
522 | #define BF_CLKCTRL_FRAC_IOFRAC(v) (((v) << 24) & 0x3f000000) | ||
523 | #define BP_CLKCTRL_FRAC_CLKGATEPIX 23 | ||
524 | #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x800000 | ||
525 | #define BF_CLKCTRL_FRAC_CLKGATEPIX(v) (((v) << 23) & 0x800000) | ||
526 | #define BP_CLKCTRL_FRAC_PIX_STABLE 22 | ||
527 | #define BM_CLKCTRL_FRAC_PIX_STABLE 0x400000 | ||
528 | #define BF_CLKCTRL_FRAC_PIX_STABLE(v) (((v) << 22) & 0x400000) | ||
529 | #define BP_CLKCTRL_FRAC_PIXFRAC 16 | ||
530 | #define BM_CLKCTRL_FRAC_PIXFRAC 0x3f0000 | ||
531 | #define BF_CLKCTRL_FRAC_PIXFRAC(v) (((v) << 16) & 0x3f0000) | ||
532 | #define BP_CLKCTRL_FRAC_CLKGATEEMI 15 | ||
533 | #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x8000 | ||
534 | #define BF_CLKCTRL_FRAC_CLKGATEEMI(v) (((v) << 15) & 0x8000) | ||
535 | #define BP_CLKCTRL_FRAC_EMI_STABLE 14 | ||
536 | #define BM_CLKCTRL_FRAC_EMI_STABLE 0x4000 | ||
537 | #define BF_CLKCTRL_FRAC_EMI_STABLE(v) (((v) << 14) & 0x4000) | ||
538 | #define BP_CLKCTRL_FRAC_EMIFRAC 8 | ||
539 | #define BM_CLKCTRL_FRAC_EMIFRAC 0x3f00 | ||
540 | #define BF_CLKCTRL_FRAC_EMIFRAC(v) (((v) << 8) & 0x3f00) | ||
541 | #define BP_CLKCTRL_FRAC_CLKGATECPU 7 | ||
542 | #define BM_CLKCTRL_FRAC_CLKGATECPU 0x80 | ||
543 | #define BF_CLKCTRL_FRAC_CLKGATECPU(v) (((v) << 7) & 0x80) | ||
544 | #define BP_CLKCTRL_FRAC_CPU_STABLE 6 | ||
545 | #define BM_CLKCTRL_FRAC_CPU_STABLE 0x40 | ||
546 | #define BF_CLKCTRL_FRAC_CPU_STABLE(v) (((v) << 6) & 0x40) | ||
547 | #define BP_CLKCTRL_FRAC_CPUFRAC 0 | ||
548 | #define BM_CLKCTRL_FRAC_CPUFRAC 0x3f | ||
549 | #define BF_CLKCTRL_FRAC_CPUFRAC(v) (((v) << 0) & 0x3f) | ||
550 | |||
551 | /** | ||
552 | * Register: HW_CLKCTRL_FRAC1 | ||
553 | * Address: 0x100 | ||
554 | * SCT: yes | ||
555 | */ | ||
556 | #define HW_CLKCTRL_FRAC1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x0)) | ||
557 | #define HW_CLKCTRL_FRAC1_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x4)) | ||
558 | #define HW_CLKCTRL_FRAC1_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x8)) | ||
559 | #define HW_CLKCTRL_FRAC1_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0xc)) | ||
560 | #define BP_CLKCTRL_FRAC1_CLKGATEVID 31 | ||
561 | #define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 | ||
562 | #define BF_CLKCTRL_FRAC1_CLKGATEVID(v) (((v) << 31) & 0x80000000) | ||
563 | #define BP_CLKCTRL_FRAC1_VID_STABLE 30 | ||
564 | #define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 | ||
565 | #define BF_CLKCTRL_FRAC1_VID_STABLE(v) (((v) << 30) & 0x40000000) | ||
566 | #define BP_CLKCTRL_FRAC1_RSRVD1 0 | ||
567 | #define BM_CLKCTRL_FRAC1_RSRVD1 0x3fffffff | ||
568 | #define BF_CLKCTRL_FRAC1_RSRVD1(v) (((v) << 0) & 0x3fffffff) | ||
569 | |||
570 | /** | ||
571 | * Register: HW_CLKCTRL_CLKSEQ | ||
572 | * Address: 0x110 | ||
573 | * SCT: yes | ||
574 | */ | ||
575 | #define HW_CLKCTRL_CLKSEQ (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x0)) | ||
576 | #define HW_CLKCTRL_CLKSEQ_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x4)) | ||
577 | #define HW_CLKCTRL_CLKSEQ_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x8)) | ||
578 | #define HW_CLKCTRL_CLKSEQ_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0xc)) | ||
579 | #define BP_CLKCTRL_CLKSEQ_RSRVD1 9 | ||
580 | #define BM_CLKCTRL_CLKSEQ_RSRVD1 0xfffffe00 | ||
581 | #define BF_CLKCTRL_CLKSEQ_RSRVD1(v) (((v) << 9) & 0xfffffe00) | ||
582 | #define BP_CLKCTRL_CLKSEQ_BYPASS_ETM 8 | ||
583 | #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x100 | ||
584 | #define BF_CLKCTRL_CLKSEQ_BYPASS_ETM(v) (((v) << 8) & 0x100) | ||
585 | #define BP_CLKCTRL_CLKSEQ_BYPASS_CPU 7 | ||
586 | #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x80 | ||
587 | #define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v) (((v) << 7) & 0x80) | ||
588 | #define BP_CLKCTRL_CLKSEQ_BYPASS_EMI 6 | ||
589 | #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x40 | ||
590 | #define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v) (((v) << 6) & 0x40) | ||
591 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SSP 5 | ||
592 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x20 | ||
593 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v) (((v) << 5) & 0x20) | ||
594 | #define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI 4 | ||
595 | #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x10 | ||
596 | #define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) (((v) << 4) & 0x10) | ||
597 | #define BP_CLKCTRL_CLKSEQ_BYPASS_IR 3 | ||
598 | #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x8 | ||
599 | #define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v) (((v) << 3) & 0x8) | ||
600 | #define BP_CLKCTRL_CLKSEQ_RSRVD0 2 | ||
601 | #define BM_CLKCTRL_CLKSEQ_RSRVD0 0x4 | ||
602 | #define BF_CLKCTRL_CLKSEQ_RSRVD0(v) (((v) << 2) & 0x4) | ||
603 | #define BP_CLKCTRL_CLKSEQ_BYPASS_PIX 1 | ||
604 | #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x2 | ||
605 | #define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v) (((v) << 1) & 0x2) | ||
606 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF 0 | ||
607 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x1 | ||
608 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) (((v) << 0) & 0x1) | ||
609 | |||
610 | /** | ||
611 | * Register: HW_CLKCTRL_RESET | ||
612 | * Address: 0x120 | ||
613 | * SCT: no | ||
614 | */ | ||
615 | #define HW_CLKCTRL_RESET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x120)) | ||
616 | #define BP_CLKCTRL_RESET_RSRVD 2 | ||
617 | #define BM_CLKCTRL_RESET_RSRVD 0xfffffffc | ||
618 | #define BF_CLKCTRL_RESET_RSRVD(v) (((v) << 2) & 0xfffffffc) | ||
619 | #define BP_CLKCTRL_RESET_CHIP 1 | ||
620 | #define BM_CLKCTRL_RESET_CHIP 0x2 | ||
621 | #define BF_CLKCTRL_RESET_CHIP(v) (((v) << 1) & 0x2) | ||
622 | #define BP_CLKCTRL_RESET_DIG 0 | ||
623 | #define BM_CLKCTRL_RESET_DIG 0x1 | ||
624 | #define BF_CLKCTRL_RESET_DIG(v) (((v) << 0) & 0x1) | ||
625 | |||
626 | /** | ||
627 | * Register: HW_CLKCTRL_STATUS | ||
628 | * Address: 0x130 | ||
629 | * SCT: no | ||
630 | */ | ||
631 | #define HW_CLKCTRL_STATUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x130)) | ||
632 | #define BP_CLKCTRL_STATUS_CPU_LIMIT 30 | ||
633 | #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xc0000000 | ||
634 | #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) (((v) << 30) & 0xc0000000) | ||
635 | #define BP_CLKCTRL_STATUS_RSRVD 0 | ||
636 | #define BM_CLKCTRL_STATUS_RSRVD 0x3fffffff | ||
637 | #define BF_CLKCTRL_STATUS_RSRVD(v) (((v) << 0) & 0x3fffffff) | ||
638 | |||
639 | /** | ||
640 | * Register: HW_CLKCTRL_VERSION | ||
641 | * Address: 0x140 | ||
642 | * SCT: no | ||
643 | */ | ||
644 | #define HW_CLKCTRL_VERSION (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x140)) | ||
645 | #define BP_CLKCTRL_VERSION_MAJOR 24 | ||
646 | #define BM_CLKCTRL_VERSION_MAJOR 0xff000000 | ||
647 | #define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
648 | #define BP_CLKCTRL_VERSION_MINOR 16 | ||
649 | #define BM_CLKCTRL_VERSION_MINOR 0xff0000 | ||
650 | #define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
651 | #define BP_CLKCTRL_VERSION_STEP 0 | ||
652 | #define BM_CLKCTRL_VERSION_STEP 0xffff | ||
653 | #define BF_CLKCTRL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
654 | |||
655 | #endif /* __HEADERGEN__IMX233__CLKCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dcp.h b/firmware/target/arm/imx233/regs/imx233/regs-dcp.h new file mode 100644 index 0000000000..9428f97898 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-dcp.h | |||
@@ -0,0 +1,851 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__DCP__H__ | ||
24 | #define __HEADERGEN__IMX233__DCP__H__ | ||
25 | |||
26 | #define REGS_DCP_BASE (0x80028000) | ||
27 | |||
28 | #define REGS_DCP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DCP_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DCP_CTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DCP_CTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DCP_CTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DCP_CTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DCP_CTRL_SFTRST 31 | ||
40 | #define BM_DCP_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_DCP_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_DCP_CTRL_CLKGATE 30 | ||
43 | #define BM_DCP_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_DCP_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_DCP_CTRL_PRESENT_CRYPTO 29 | ||
46 | #define BM_DCP_CTRL_PRESENT_CRYPTO 0x20000000 | ||
47 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1 | ||
48 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Absent 0x0 | ||
49 | #define BF_DCP_CTRL_PRESENT_CRYPTO(v) (((v) << 29) & 0x20000000) | ||
50 | #define BF_DCP_CTRL_PRESENT_CRYPTO_V(v) ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000) | ||
51 | #define BP_DCP_CTRL_PRESENT_CSC 28 | ||
52 | #define BM_DCP_CTRL_PRESENT_CSC 0x10000000 | ||
53 | #define BV_DCP_CTRL_PRESENT_CSC__Present 0x1 | ||
54 | #define BV_DCP_CTRL_PRESENT_CSC__Absent 0x0 | ||
55 | #define BF_DCP_CTRL_PRESENT_CSC(v) (((v) << 28) & 0x10000000) | ||
56 | #define BF_DCP_CTRL_PRESENT_CSC_V(v) ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000) | ||
57 | #define BP_DCP_CTRL_RSVD1 24 | ||
58 | #define BM_DCP_CTRL_RSVD1 0xf000000 | ||
59 | #define BF_DCP_CTRL_RSVD1(v) (((v) << 24) & 0xf000000) | ||
60 | #define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES 23 | ||
61 | #define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x800000 | ||
62 | #define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v) (((v) << 23) & 0x800000) | ||
63 | #define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING 22 | ||
64 | #define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x400000 | ||
65 | #define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v) (((v) << 22) & 0x400000) | ||
66 | #define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 21 | ||
67 | #define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 0x200000 | ||
68 | #define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v) (((v) << 21) & 0x200000) | ||
69 | #define BP_DCP_CTRL_RSVD0 9 | ||
70 | #define BM_DCP_CTRL_RSVD0 0x1ffe00 | ||
71 | #define BF_DCP_CTRL_RSVD0(v) (((v) << 9) & 0x1ffe00) | ||
72 | #define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE 8 | ||
73 | #define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE 0x100 | ||
74 | #define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v) (((v) << 8) & 0x100) | ||
75 | #define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 | ||
76 | #define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0xff | ||
77 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x1 | ||
78 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x2 | ||
79 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x4 | ||
80 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x8 | ||
81 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) (((v) << 0) & 0xff) | ||
82 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v) ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff) | ||
83 | |||
84 | /** | ||
85 | * Register: HW_DCP_STAT | ||
86 | * Address: 0x10 | ||
87 | * SCT: yes | ||
88 | */ | ||
89 | #define HW_DCP_STAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0)) | ||
90 | #define HW_DCP_STAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4)) | ||
91 | #define HW_DCP_STAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8)) | ||
92 | #define HW_DCP_STAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc)) | ||
93 | #define BP_DCP_STAT_RSVD2 29 | ||
94 | #define BM_DCP_STAT_RSVD2 0xe0000000 | ||
95 | #define BF_DCP_STAT_RSVD2(v) (((v) << 29) & 0xe0000000) | ||
96 | #define BP_DCP_STAT_OTP_KEY_READY 28 | ||
97 | #define BM_DCP_STAT_OTP_KEY_READY 0x10000000 | ||
98 | #define BF_DCP_STAT_OTP_KEY_READY(v) (((v) << 28) & 0x10000000) | ||
99 | #define BP_DCP_STAT_CUR_CHANNEL 24 | ||
100 | #define BM_DCP_STAT_CUR_CHANNEL 0xf000000 | ||
101 | #define BV_DCP_STAT_CUR_CHANNEL__None 0x0 | ||
102 | #define BV_DCP_STAT_CUR_CHANNEL__CH0 0x1 | ||
103 | #define BV_DCP_STAT_CUR_CHANNEL__CH1 0x2 | ||
104 | #define BV_DCP_STAT_CUR_CHANNEL__CH2 0x3 | ||
105 | #define BV_DCP_STAT_CUR_CHANNEL__CH3 0x4 | ||
106 | #define BV_DCP_STAT_CUR_CHANNEL__CSC 0x8 | ||
107 | #define BF_DCP_STAT_CUR_CHANNEL(v) (((v) << 24) & 0xf000000) | ||
108 | #define BF_DCP_STAT_CUR_CHANNEL_V(v) ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000) | ||
109 | #define BP_DCP_STAT_READY_CHANNELS 16 | ||
110 | #define BM_DCP_STAT_READY_CHANNELS 0xff0000 | ||
111 | #define BV_DCP_STAT_READY_CHANNELS__CH0 0x1 | ||
112 | #define BV_DCP_STAT_READY_CHANNELS__CH1 0x2 | ||
113 | #define BV_DCP_STAT_READY_CHANNELS__CH2 0x4 | ||
114 | #define BV_DCP_STAT_READY_CHANNELS__CH3 0x8 | ||
115 | #define BF_DCP_STAT_READY_CHANNELS(v) (((v) << 16) & 0xff0000) | ||
116 | #define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000) | ||
117 | #define BP_DCP_STAT_RSVD1 9 | ||
118 | #define BM_DCP_STAT_RSVD1 0xfe00 | ||
119 | #define BF_DCP_STAT_RSVD1(v) (((v) << 9) & 0xfe00) | ||
120 | #define BP_DCP_STAT_CSCIRQ 8 | ||
121 | #define BM_DCP_STAT_CSCIRQ 0x100 | ||
122 | #define BF_DCP_STAT_CSCIRQ(v) (((v) << 8) & 0x100) | ||
123 | #define BP_DCP_STAT_RSVD0 4 | ||
124 | #define BM_DCP_STAT_RSVD0 0xf0 | ||
125 | #define BF_DCP_STAT_RSVD0(v) (((v) << 4) & 0xf0) | ||
126 | #define BP_DCP_STAT_IRQ 0 | ||
127 | #define BM_DCP_STAT_IRQ 0xf | ||
128 | #define BF_DCP_STAT_IRQ(v) (((v) << 0) & 0xf) | ||
129 | |||
130 | /** | ||
131 | * Register: HW_DCP_CHANNELCTRL | ||
132 | * Address: 0x20 | ||
133 | * SCT: yes | ||
134 | */ | ||
135 | #define HW_DCP_CHANNELCTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0)) | ||
136 | #define HW_DCP_CHANNELCTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4)) | ||
137 | #define HW_DCP_CHANNELCTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8)) | ||
138 | #define HW_DCP_CHANNELCTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc)) | ||
139 | #define BP_DCP_CHANNELCTRL_RSVD 19 | ||
140 | #define BM_DCP_CHANNELCTRL_RSVD 0xfff80000 | ||
141 | #define BF_DCP_CHANNELCTRL_RSVD(v) (((v) << 19) & 0xfff80000) | ||
142 | #define BP_DCP_CHANNELCTRL_CSC_PRIORITY 17 | ||
143 | #define BM_DCP_CHANNELCTRL_CSC_PRIORITY 0x60000 | ||
144 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH 0x3 | ||
145 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED 0x2 | ||
146 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW 0x1 | ||
147 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0 | ||
148 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v) (((v) << 17) & 0x60000) | ||
149 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v) ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000) | ||
150 | #define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED 16 | ||
151 | #define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED 0x10000 | ||
152 | #define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v) (((v) << 16) & 0x10000) | ||
153 | #define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 8 | ||
154 | #define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 0xff00 | ||
155 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x1 | ||
156 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x2 | ||
157 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x4 | ||
158 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x8 | ||
159 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) (((v) << 8) & 0xff00) | ||
160 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00) | ||
161 | #define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 | ||
162 | #define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0xff | ||
163 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x1 | ||
164 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x2 | ||
165 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x4 | ||
166 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x8 | ||
167 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) (((v) << 0) & 0xff) | ||
168 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_DCP_CAPABILITY0 | ||
172 | * Address: 0x30 | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_DCP_CAPABILITY0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30)) | ||
176 | #define BP_DCP_CAPABILITY0_DISABLE_DECRYPT 31 | ||
177 | #define BM_DCP_CAPABILITY0_DISABLE_DECRYPT 0x80000000 | ||
178 | #define BF_DCP_CAPABILITY0_DISABLE_DECRYPT(v) (((v) << 31) & 0x80000000) | ||
179 | #define BP_DCP_CAPABILITY0_ENABLE_TZONE 30 | ||
180 | #define BM_DCP_CAPABILITY0_ENABLE_TZONE 0x40000000 | ||
181 | #define BF_DCP_CAPABILITY0_ENABLE_TZONE(v) (((v) << 30) & 0x40000000) | ||
182 | #define BP_DCP_CAPABILITY0_RSVD 12 | ||
183 | #define BM_DCP_CAPABILITY0_RSVD 0x3ffff000 | ||
184 | #define BF_DCP_CAPABILITY0_RSVD(v) (((v) << 12) & 0x3ffff000) | ||
185 | #define BP_DCP_CAPABILITY0_NUM_CHANNELS 8 | ||
186 | #define BM_DCP_CAPABILITY0_NUM_CHANNELS 0xf00 | ||
187 | #define BF_DCP_CAPABILITY0_NUM_CHANNELS(v) (((v) << 8) & 0xf00) | ||
188 | #define BP_DCP_CAPABILITY0_NUM_KEYS 0 | ||
189 | #define BM_DCP_CAPABILITY0_NUM_KEYS 0xff | ||
190 | #define BF_DCP_CAPABILITY0_NUM_KEYS(v) (((v) << 0) & 0xff) | ||
191 | |||
192 | /** | ||
193 | * Register: HW_DCP_CAPABILITY1 | ||
194 | * Address: 0x40 | ||
195 | * SCT: no | ||
196 | */ | ||
197 | #define HW_DCP_CAPABILITY1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40)) | ||
198 | #define BP_DCP_CAPABILITY1_HASH_ALGORITHMS 16 | ||
199 | #define BM_DCP_CAPABILITY1_HASH_ALGORITHMS 0xffff0000 | ||
200 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1 0x1 | ||
201 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x2 | ||
202 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) (((v) << 16) & 0xffff0000) | ||
203 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000) | ||
204 | #define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0 | ||
205 | #define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0xffff | ||
206 | #define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x1 | ||
207 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) (((v) << 0) & 0xffff) | ||
208 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff) | ||
209 | |||
210 | /** | ||
211 | * Register: HW_DCP_CONTEXT | ||
212 | * Address: 0x50 | ||
213 | * SCT: no | ||
214 | */ | ||
215 | #define HW_DCP_CONTEXT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50)) | ||
216 | #define BP_DCP_CONTEXT_ADDR 0 | ||
217 | #define BM_DCP_CONTEXT_ADDR 0xffffffff | ||
218 | #define BF_DCP_CONTEXT_ADDR(v) (((v) << 0) & 0xffffffff) | ||
219 | |||
220 | /** | ||
221 | * Register: HW_DCP_KEY | ||
222 | * Address: 0x60 | ||
223 | * SCT: no | ||
224 | */ | ||
225 | #define HW_DCP_KEY (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60)) | ||
226 | #define BP_DCP_KEY_RSVD 8 | ||
227 | #define BM_DCP_KEY_RSVD 0xffffff00 | ||
228 | #define BF_DCP_KEY_RSVD(v) (((v) << 8) & 0xffffff00) | ||
229 | #define BP_DCP_KEY_RSVD_INDEX 6 | ||
230 | #define BM_DCP_KEY_RSVD_INDEX 0xc0 | ||
231 | #define BF_DCP_KEY_RSVD_INDEX(v) (((v) << 6) & 0xc0) | ||
232 | #define BP_DCP_KEY_INDEX 4 | ||
233 | #define BM_DCP_KEY_INDEX 0x30 | ||
234 | #define BF_DCP_KEY_INDEX(v) (((v) << 4) & 0x30) | ||
235 | #define BP_DCP_KEY_RSVD_SUBWORD 2 | ||
236 | #define BM_DCP_KEY_RSVD_SUBWORD 0xc | ||
237 | #define BF_DCP_KEY_RSVD_SUBWORD(v) (((v) << 2) & 0xc) | ||
238 | #define BP_DCP_KEY_SUBWORD 0 | ||
239 | #define BM_DCP_KEY_SUBWORD 0x3 | ||
240 | #define BF_DCP_KEY_SUBWORD(v) (((v) << 0) & 0x3) | ||
241 | |||
242 | /** | ||
243 | * Register: HW_DCP_KEYDATA | ||
244 | * Address: 0x70 | ||
245 | * SCT: no | ||
246 | */ | ||
247 | #define HW_DCP_KEYDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70)) | ||
248 | #define BP_DCP_KEYDATA_DATA 0 | ||
249 | #define BM_DCP_KEYDATA_DATA 0xffffffff | ||
250 | #define BF_DCP_KEYDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
251 | |||
252 | /** | ||
253 | * Register: HW_DCP_PACKET0 | ||
254 | * Address: 0x80 | ||
255 | * SCT: no | ||
256 | */ | ||
257 | #define HW_DCP_PACKET0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80)) | ||
258 | #define BP_DCP_PACKET0_ADDR 0 | ||
259 | #define BM_DCP_PACKET0_ADDR 0xffffffff | ||
260 | #define BF_DCP_PACKET0_ADDR(v) (((v) << 0) & 0xffffffff) | ||
261 | |||
262 | /** | ||
263 | * Register: HW_DCP_PACKET1 | ||
264 | * Address: 0x90 | ||
265 | * SCT: no | ||
266 | */ | ||
267 | #define HW_DCP_PACKET1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90)) | ||
268 | #define BP_DCP_PACKET1_TAG 24 | ||
269 | #define BM_DCP_PACKET1_TAG 0xff000000 | ||
270 | #define BF_DCP_PACKET1_TAG(v) (((v) << 24) & 0xff000000) | ||
271 | #define BP_DCP_PACKET1_OUTPUT_WORDSWAP 23 | ||
272 | #define BM_DCP_PACKET1_OUTPUT_WORDSWAP 0x800000 | ||
273 | #define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v) (((v) << 23) & 0x800000) | ||
274 | #define BP_DCP_PACKET1_OUTPUT_BYTESWAP 22 | ||
275 | #define BM_DCP_PACKET1_OUTPUT_BYTESWAP 0x400000 | ||
276 | #define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v) (((v) << 22) & 0x400000) | ||
277 | #define BP_DCP_PACKET1_INPUT_WORDSWAP 21 | ||
278 | #define BM_DCP_PACKET1_INPUT_WORDSWAP 0x200000 | ||
279 | #define BF_DCP_PACKET1_INPUT_WORDSWAP(v) (((v) << 21) & 0x200000) | ||
280 | #define BP_DCP_PACKET1_INPUT_BYTESWAP 20 | ||
281 | #define BM_DCP_PACKET1_INPUT_BYTESWAP 0x100000 | ||
282 | #define BF_DCP_PACKET1_INPUT_BYTESWAP(v) (((v) << 20) & 0x100000) | ||
283 | #define BP_DCP_PACKET1_KEY_WORDSWAP 19 | ||
284 | #define BM_DCP_PACKET1_KEY_WORDSWAP 0x80000 | ||
285 | #define BF_DCP_PACKET1_KEY_WORDSWAP(v) (((v) << 19) & 0x80000) | ||
286 | #define BP_DCP_PACKET1_KEY_BYTESWAP 18 | ||
287 | #define BM_DCP_PACKET1_KEY_BYTESWAP 0x40000 | ||
288 | #define BF_DCP_PACKET1_KEY_BYTESWAP(v) (((v) << 18) & 0x40000) | ||
289 | #define BP_DCP_PACKET1_TEST_SEMA_IRQ 17 | ||
290 | #define BM_DCP_PACKET1_TEST_SEMA_IRQ 0x20000 | ||
291 | #define BF_DCP_PACKET1_TEST_SEMA_IRQ(v) (((v) << 17) & 0x20000) | ||
292 | #define BP_DCP_PACKET1_CONSTANT_FILL 16 | ||
293 | #define BM_DCP_PACKET1_CONSTANT_FILL 0x10000 | ||
294 | #define BF_DCP_PACKET1_CONSTANT_FILL(v) (((v) << 16) & 0x10000) | ||
295 | #define BP_DCP_PACKET1_HASH_OUTPUT 15 | ||
296 | #define BM_DCP_PACKET1_HASH_OUTPUT 0x8000 | ||
297 | #define BV_DCP_PACKET1_HASH_OUTPUT__INPUT 0x0 | ||
298 | #define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x1 | ||
299 | #define BF_DCP_PACKET1_HASH_OUTPUT(v) (((v) << 15) & 0x8000) | ||
300 | #define BF_DCP_PACKET1_HASH_OUTPUT_V(v) ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000) | ||
301 | #define BP_DCP_PACKET1_CHECK_HASH 14 | ||
302 | #define BM_DCP_PACKET1_CHECK_HASH 0x4000 | ||
303 | #define BF_DCP_PACKET1_CHECK_HASH(v) (((v) << 14) & 0x4000) | ||
304 | #define BP_DCP_PACKET1_HASH_TERM 13 | ||
305 | #define BM_DCP_PACKET1_HASH_TERM 0x2000 | ||
306 | #define BF_DCP_PACKET1_HASH_TERM(v) (((v) << 13) & 0x2000) | ||
307 | #define BP_DCP_PACKET1_HASH_INIT 12 | ||
308 | #define BM_DCP_PACKET1_HASH_INIT 0x1000 | ||
309 | #define BF_DCP_PACKET1_HASH_INIT(v) (((v) << 12) & 0x1000) | ||
310 | #define BP_DCP_PACKET1_PAYLOAD_KEY 11 | ||
311 | #define BM_DCP_PACKET1_PAYLOAD_KEY 0x800 | ||
312 | #define BF_DCP_PACKET1_PAYLOAD_KEY(v) (((v) << 11) & 0x800) | ||
313 | #define BP_DCP_PACKET1_OTP_KEY 10 | ||
314 | #define BM_DCP_PACKET1_OTP_KEY 0x400 | ||
315 | #define BF_DCP_PACKET1_OTP_KEY(v) (((v) << 10) & 0x400) | ||
316 | #define BP_DCP_PACKET1_CIPHER_INIT 9 | ||
317 | #define BM_DCP_PACKET1_CIPHER_INIT 0x200 | ||
318 | #define BF_DCP_PACKET1_CIPHER_INIT(v) (((v) << 9) & 0x200) | ||
319 | #define BP_DCP_PACKET1_CIPHER_ENCRYPT 8 | ||
320 | #define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x100 | ||
321 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x1 | ||
322 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x0 | ||
323 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT(v) (((v) << 8) & 0x100) | ||
324 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v) ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100) | ||
325 | #define BP_DCP_PACKET1_ENABLE_BLIT 7 | ||
326 | #define BM_DCP_PACKET1_ENABLE_BLIT 0x80 | ||
327 | #define BF_DCP_PACKET1_ENABLE_BLIT(v) (((v) << 7) & 0x80) | ||
328 | #define BP_DCP_PACKET1_ENABLE_HASH 6 | ||
329 | #define BM_DCP_PACKET1_ENABLE_HASH 0x40 | ||
330 | #define BF_DCP_PACKET1_ENABLE_HASH(v) (((v) << 6) & 0x40) | ||
331 | #define BP_DCP_PACKET1_ENABLE_CIPHER 5 | ||
332 | #define BM_DCP_PACKET1_ENABLE_CIPHER 0x20 | ||
333 | #define BF_DCP_PACKET1_ENABLE_CIPHER(v) (((v) << 5) & 0x20) | ||
334 | #define BP_DCP_PACKET1_ENABLE_MEMCOPY 4 | ||
335 | #define BM_DCP_PACKET1_ENABLE_MEMCOPY 0x10 | ||
336 | #define BF_DCP_PACKET1_ENABLE_MEMCOPY(v) (((v) << 4) & 0x10) | ||
337 | #define BP_DCP_PACKET1_CHAIN_CONTIGUOUS 3 | ||
338 | #define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x8 | ||
339 | #define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v) (((v) << 3) & 0x8) | ||
340 | #define BP_DCP_PACKET1_CHAIN 2 | ||
341 | #define BM_DCP_PACKET1_CHAIN 0x4 | ||
342 | #define BF_DCP_PACKET1_CHAIN(v) (((v) << 2) & 0x4) | ||
343 | #define BP_DCP_PACKET1_DECR_SEMAPHORE 1 | ||
344 | #define BM_DCP_PACKET1_DECR_SEMAPHORE 0x2 | ||
345 | #define BF_DCP_PACKET1_DECR_SEMAPHORE(v) (((v) << 1) & 0x2) | ||
346 | #define BP_DCP_PACKET1_INTERRUPT 0 | ||
347 | #define BM_DCP_PACKET1_INTERRUPT 0x1 | ||
348 | #define BF_DCP_PACKET1_INTERRUPT(v) (((v) << 0) & 0x1) | ||
349 | |||
350 | /** | ||
351 | * Register: HW_DCP_PACKET2 | ||
352 | * Address: 0xa0 | ||
353 | * SCT: no | ||
354 | */ | ||
355 | #define HW_DCP_PACKET2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0)) | ||
356 | #define BP_DCP_PACKET2_CIPHER_CFG 24 | ||
357 | #define BM_DCP_PACKET2_CIPHER_CFG 0xff000000 | ||
358 | #define BF_DCP_PACKET2_CIPHER_CFG(v) (((v) << 24) & 0xff000000) | ||
359 | #define BP_DCP_PACKET2_RSVD 20 | ||
360 | #define BM_DCP_PACKET2_RSVD 0xf00000 | ||
361 | #define BF_DCP_PACKET2_RSVD(v) (((v) << 20) & 0xf00000) | ||
362 | #define BP_DCP_PACKET2_HASH_SELECT 16 | ||
363 | #define BM_DCP_PACKET2_HASH_SELECT 0xf0000 | ||
364 | #define BV_DCP_PACKET2_HASH_SELECT__SHA1 0x0 | ||
365 | #define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x1 | ||
366 | #define BF_DCP_PACKET2_HASH_SELECT(v) (((v) << 16) & 0xf0000) | ||
367 | #define BF_DCP_PACKET2_HASH_SELECT_V(v) ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000) | ||
368 | #define BP_DCP_PACKET2_KEY_SELECT 8 | ||
369 | #define BM_DCP_PACKET2_KEY_SELECT 0xff00 | ||
370 | #define BF_DCP_PACKET2_KEY_SELECT(v) (((v) << 8) & 0xff00) | ||
371 | #define BP_DCP_PACKET2_CIPHER_MODE 4 | ||
372 | #define BM_DCP_PACKET2_CIPHER_MODE 0xf0 | ||
373 | #define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x0 | ||
374 | #define BV_DCP_PACKET2_CIPHER_MODE__CBC 0x1 | ||
375 | #define BF_DCP_PACKET2_CIPHER_MODE(v) (((v) << 4) & 0xf0) | ||
376 | #define BF_DCP_PACKET2_CIPHER_MODE_V(v) ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0) | ||
377 | #define BP_DCP_PACKET2_CIPHER_SELECT 0 | ||
378 | #define BM_DCP_PACKET2_CIPHER_SELECT 0xf | ||
379 | #define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x0 | ||
380 | #define BF_DCP_PACKET2_CIPHER_SELECT(v) (((v) << 0) & 0xf) | ||
381 | #define BF_DCP_PACKET2_CIPHER_SELECT_V(v) ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf) | ||
382 | |||
383 | /** | ||
384 | * Register: HW_DCP_PACKET3 | ||
385 | * Address: 0xb0 | ||
386 | * SCT: no | ||
387 | */ | ||
388 | #define HW_DCP_PACKET3 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0)) | ||
389 | #define BP_DCP_PACKET3_ADDR 0 | ||
390 | #define BM_DCP_PACKET3_ADDR 0xffffffff | ||
391 | #define BF_DCP_PACKET3_ADDR(v) (((v) << 0) & 0xffffffff) | ||
392 | |||
393 | /** | ||
394 | * Register: HW_DCP_PACKET4 | ||
395 | * Address: 0xc0 | ||
396 | * SCT: no | ||
397 | */ | ||
398 | #define HW_DCP_PACKET4 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0)) | ||
399 | #define BP_DCP_PACKET4_ADDR 0 | ||
400 | #define BM_DCP_PACKET4_ADDR 0xffffffff | ||
401 | #define BF_DCP_PACKET4_ADDR(v) (((v) << 0) & 0xffffffff) | ||
402 | |||
403 | /** | ||
404 | * Register: HW_DCP_PACKET5 | ||
405 | * Address: 0xd0 | ||
406 | * SCT: no | ||
407 | */ | ||
408 | #define HW_DCP_PACKET5 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0)) | ||
409 | #define BP_DCP_PACKET5_COUNT 0 | ||
410 | #define BM_DCP_PACKET5_COUNT 0xffffffff | ||
411 | #define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff) | ||
412 | |||
413 | /** | ||
414 | * Register: HW_DCP_PACKET6 | ||
415 | * Address: 0xe0 | ||
416 | * SCT: no | ||
417 | */ | ||
418 | #define HW_DCP_PACKET6 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0)) | ||
419 | #define BP_DCP_PACKET6_ADDR 0 | ||
420 | #define BM_DCP_PACKET6_ADDR 0xffffffff | ||
421 | #define BF_DCP_PACKET6_ADDR(v) (((v) << 0) & 0xffffffff) | ||
422 | |||
423 | /** | ||
424 | * Register: HW_DCP_CHnCMDPTR | ||
425 | * Address: 0x100+n*0x40 | ||
426 | * SCT: no | ||
427 | */ | ||
428 | #define HW_DCP_CHnCMDPTR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40)) | ||
429 | #define BP_DCP_CHnCMDPTR_ADDR 0 | ||
430 | #define BM_DCP_CHnCMDPTR_ADDR 0xffffffff | ||
431 | #define BF_DCP_CHnCMDPTR_ADDR(v) (((v) << 0) & 0xffffffff) | ||
432 | |||
433 | /** | ||
434 | * Register: HW_DCP_CHnSEMA | ||
435 | * Address: 0x110+n*0x40 | ||
436 | * SCT: no | ||
437 | */ | ||
438 | #define HW_DCP_CHnSEMA(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40)) | ||
439 | #define BP_DCP_CHnSEMA_RSVD2 24 | ||
440 | #define BM_DCP_CHnSEMA_RSVD2 0xff000000 | ||
441 | #define BF_DCP_CHnSEMA_RSVD2(v) (((v) << 24) & 0xff000000) | ||
442 | #define BP_DCP_CHnSEMA_VALUE 16 | ||
443 | #define BM_DCP_CHnSEMA_VALUE 0xff0000 | ||
444 | #define BF_DCP_CHnSEMA_VALUE(v) (((v) << 16) & 0xff0000) | ||
445 | #define BP_DCP_CHnSEMA_RSVD1 8 | ||
446 | #define BM_DCP_CHnSEMA_RSVD1 0xff00 | ||
447 | #define BF_DCP_CHnSEMA_RSVD1(v) (((v) << 8) & 0xff00) | ||
448 | #define BP_DCP_CHnSEMA_INCREMENT 0 | ||
449 | #define BM_DCP_CHnSEMA_INCREMENT 0xff | ||
450 | #define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff) | ||
451 | |||
452 | /** | ||
453 | * Register: HW_DCP_CHnSTAT | ||
454 | * Address: 0x120+n*0x40 | ||
455 | * SCT: yes | ||
456 | */ | ||
457 | #define HW_DCP_CHnSTAT(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0)) | ||
458 | #define HW_DCP_CHnSTAT_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4)) | ||
459 | #define HW_DCP_CHnSTAT_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8)) | ||
460 | #define HW_DCP_CHnSTAT_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc)) | ||
461 | #define BP_DCP_CHnSTAT_TAG 24 | ||
462 | #define BM_DCP_CHnSTAT_TAG 0xff000000 | ||
463 | #define BF_DCP_CHnSTAT_TAG(v) (((v) << 24) & 0xff000000) | ||
464 | #define BP_DCP_CHnSTAT_ERROR_CODE 16 | ||
465 | #define BM_DCP_CHnSTAT_ERROR_CODE 0xff0000 | ||
466 | #define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x1 | ||
467 | #define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN 0x2 | ||
468 | #define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR 0x3 | ||
469 | #define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR 0x4 | ||
470 | #define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE 0x5 | ||
471 | #define BF_DCP_CHnSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
472 | #define BF_DCP_CHnSTAT_ERROR_CODE_V(v) ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
473 | #define BP_DCP_CHnSTAT_RSVD0 7 | ||
474 | #define BM_DCP_CHnSTAT_RSVD0 0xff80 | ||
475 | #define BF_DCP_CHnSTAT_RSVD0(v) (((v) << 7) & 0xff80) | ||
476 | #define BP_DCP_CHnSTAT_ERROR_PAGEFAULT 6 | ||
477 | #define BM_DCP_CHnSTAT_ERROR_PAGEFAULT 0x40 | ||
478 | #define BF_DCP_CHnSTAT_ERROR_PAGEFAULT(v) (((v) << 6) & 0x40) | ||
479 | #define BP_DCP_CHnSTAT_ERROR_DST 5 | ||
480 | #define BM_DCP_CHnSTAT_ERROR_DST 0x20 | ||
481 | #define BF_DCP_CHnSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
482 | #define BP_DCP_CHnSTAT_ERROR_SRC 4 | ||
483 | #define BM_DCP_CHnSTAT_ERROR_SRC 0x10 | ||
484 | #define BF_DCP_CHnSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
485 | #define BP_DCP_CHnSTAT_ERROR_PACKET 3 | ||
486 | #define BM_DCP_CHnSTAT_ERROR_PACKET 0x8 | ||
487 | #define BF_DCP_CHnSTAT_ERROR_PACKET(v) (((v) << 3) & 0x8) | ||
488 | #define BP_DCP_CHnSTAT_ERROR_SETUP 2 | ||
489 | #define BM_DCP_CHnSTAT_ERROR_SETUP 0x4 | ||
490 | #define BF_DCP_CHnSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
491 | #define BP_DCP_CHnSTAT_HASH_MISMATCH 1 | ||
492 | #define BM_DCP_CHnSTAT_HASH_MISMATCH 0x2 | ||
493 | #define BF_DCP_CHnSTAT_HASH_MISMATCH(v) (((v) << 1) & 0x2) | ||
494 | #define BP_DCP_CHnSTAT_RSVD_COMPLETE 0 | ||
495 | #define BM_DCP_CHnSTAT_RSVD_COMPLETE 0x1 | ||
496 | #define BF_DCP_CHnSTAT_RSVD_COMPLETE(v) (((v) << 0) & 0x1) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_DCP_CHnOPTS | ||
500 | * Address: 0x130+n*0x40 | ||
501 | * SCT: yes | ||
502 | */ | ||
503 | #define HW_DCP_CHnOPTS(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0)) | ||
504 | #define HW_DCP_CHnOPTS_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4)) | ||
505 | #define HW_DCP_CHnOPTS_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8)) | ||
506 | #define HW_DCP_CHnOPTS_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc)) | ||
507 | #define BP_DCP_CHnOPTS_RSVD 16 | ||
508 | #define BM_DCP_CHnOPTS_RSVD 0xffff0000 | ||
509 | #define BF_DCP_CHnOPTS_RSVD(v) (((v) << 16) & 0xffff0000) | ||
510 | #define BP_DCP_CHnOPTS_RECOVERY_TIMER 0 | ||
511 | #define BM_DCP_CHnOPTS_RECOVERY_TIMER 0xffff | ||
512 | #define BF_DCP_CHnOPTS_RECOVERY_TIMER(v) (((v) << 0) & 0xffff) | ||
513 | |||
514 | /** | ||
515 | * Register: HW_DCP_CSCCTRL0 | ||
516 | * Address: 0x300 | ||
517 | * SCT: yes | ||
518 | */ | ||
519 | #define HW_DCP_CSCCTRL0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0)) | ||
520 | #define HW_DCP_CSCCTRL0_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4)) | ||
521 | #define HW_DCP_CSCCTRL0_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8)) | ||
522 | #define HW_DCP_CSCCTRL0_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc)) | ||
523 | #define BP_DCP_CSCCTRL0_RSVD1 16 | ||
524 | #define BM_DCP_CSCCTRL0_RSVD1 0xffff0000 | ||
525 | #define BF_DCP_CSCCTRL0_RSVD1(v) (((v) << 16) & 0xffff0000) | ||
526 | #define BP_DCP_CSCCTRL0_CLIP 15 | ||
527 | #define BM_DCP_CSCCTRL0_CLIP 0x8000 | ||
528 | #define BF_DCP_CSCCTRL0_CLIP(v) (((v) << 15) & 0x8000) | ||
529 | #define BP_DCP_CSCCTRL0_UPSAMPLE 14 | ||
530 | #define BM_DCP_CSCCTRL0_UPSAMPLE 0x4000 | ||
531 | #define BF_DCP_CSCCTRL0_UPSAMPLE(v) (((v) << 14) & 0x4000) | ||
532 | #define BP_DCP_CSCCTRL0_SCALE 13 | ||
533 | #define BM_DCP_CSCCTRL0_SCALE 0x2000 | ||
534 | #define BF_DCP_CSCCTRL0_SCALE(v) (((v) << 13) & 0x2000) | ||
535 | #define BP_DCP_CSCCTRL0_ROTATE 12 | ||
536 | #define BM_DCP_CSCCTRL0_ROTATE 0x1000 | ||
537 | #define BF_DCP_CSCCTRL0_ROTATE(v) (((v) << 12) & 0x1000) | ||
538 | #define BP_DCP_CSCCTRL0_SUBSAMPLE 11 | ||
539 | #define BM_DCP_CSCCTRL0_SUBSAMPLE 0x800 | ||
540 | #define BF_DCP_CSCCTRL0_SUBSAMPLE(v) (((v) << 11) & 0x800) | ||
541 | #define BP_DCP_CSCCTRL0_DELTA 10 | ||
542 | #define BM_DCP_CSCCTRL0_DELTA 0x400 | ||
543 | #define BF_DCP_CSCCTRL0_DELTA(v) (((v) << 10) & 0x400) | ||
544 | #define BP_DCP_CSCCTRL0_RGB_FORMAT 8 | ||
545 | #define BM_DCP_CSCCTRL0_RGB_FORMAT 0x300 | ||
546 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0 | ||
547 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI 0x1 | ||
548 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24 0x2 | ||
549 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I 0x3 | ||
550 | #define BF_DCP_CSCCTRL0_RGB_FORMAT(v) (((v) << 8) & 0x300) | ||
551 | #define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v) ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300) | ||
552 | #define BP_DCP_CSCCTRL0_YUV_FORMAT 4 | ||
553 | #define BM_DCP_CSCCTRL0_YUV_FORMAT 0xf0 | ||
554 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0 | ||
555 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2 | ||
556 | #define BF_DCP_CSCCTRL0_YUV_FORMAT(v) (((v) << 4) & 0xf0) | ||
557 | #define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v) ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0) | ||
558 | #define BP_DCP_CSCCTRL0_RSVD0 1 | ||
559 | #define BM_DCP_CSCCTRL0_RSVD0 0xe | ||
560 | #define BF_DCP_CSCCTRL0_RSVD0(v) (((v) << 1) & 0xe) | ||
561 | #define BP_DCP_CSCCTRL0_ENABLE 0 | ||
562 | #define BM_DCP_CSCCTRL0_ENABLE 0x1 | ||
563 | #define BF_DCP_CSCCTRL0_ENABLE(v) (((v) << 0) & 0x1) | ||
564 | |||
565 | /** | ||
566 | * Register: HW_DCP_CSCSTAT | ||
567 | * Address: 0x310 | ||
568 | * SCT: yes | ||
569 | */ | ||
570 | #define HW_DCP_CSCSTAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0)) | ||
571 | #define HW_DCP_CSCSTAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4)) | ||
572 | #define HW_DCP_CSCSTAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8)) | ||
573 | #define HW_DCP_CSCSTAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc)) | ||
574 | #define BP_DCP_CSCSTAT_RSVD3 24 | ||
575 | #define BM_DCP_CSCSTAT_RSVD3 0xff000000 | ||
576 | #define BF_DCP_CSCSTAT_RSVD3(v) (((v) << 24) & 0xff000000) | ||
577 | #define BP_DCP_CSCSTAT_ERROR_CODE 16 | ||
578 | #define BM_DCP_CSCSTAT_ERROR_CODE 0xff0000 | ||
579 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1 | ||
580 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2 | ||
581 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3 | ||
582 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4 | ||
583 | #define BF_DCP_CSCSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
584 | #define BF_DCP_CSCSTAT_ERROR_CODE_V(v) ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
585 | #define BP_DCP_CSCSTAT_RSVD2 7 | ||
586 | #define BM_DCP_CSCSTAT_RSVD2 0xff80 | ||
587 | #define BF_DCP_CSCSTAT_RSVD2(v) (((v) << 7) & 0xff80) | ||
588 | #define BP_DCP_CSCSTAT_ERROR_PAGEFAULT 6 | ||
589 | #define BM_DCP_CSCSTAT_ERROR_PAGEFAULT 0x40 | ||
590 | #define BF_DCP_CSCSTAT_ERROR_PAGEFAULT(v) (((v) << 6) & 0x40) | ||
591 | #define BP_DCP_CSCSTAT_ERROR_DST 5 | ||
592 | #define BM_DCP_CSCSTAT_ERROR_DST 0x20 | ||
593 | #define BF_DCP_CSCSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
594 | #define BP_DCP_CSCSTAT_ERROR_SRC 4 | ||
595 | #define BM_DCP_CSCSTAT_ERROR_SRC 0x10 | ||
596 | #define BF_DCP_CSCSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
597 | #define BP_DCP_CSCSTAT_RSVD1 3 | ||
598 | #define BM_DCP_CSCSTAT_RSVD1 0x8 | ||
599 | #define BF_DCP_CSCSTAT_RSVD1(v) (((v) << 3) & 0x8) | ||
600 | #define BP_DCP_CSCSTAT_ERROR_SETUP 2 | ||
601 | #define BM_DCP_CSCSTAT_ERROR_SETUP 0x4 | ||
602 | #define BF_DCP_CSCSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
603 | #define BP_DCP_CSCSTAT_RSVD0 1 | ||
604 | #define BM_DCP_CSCSTAT_RSVD0 0x2 | ||
605 | #define BF_DCP_CSCSTAT_RSVD0(v) (((v) << 1) & 0x2) | ||
606 | #define BP_DCP_CSCSTAT_COMPLETE 0 | ||
607 | #define BM_DCP_CSCSTAT_COMPLETE 0x1 | ||
608 | #define BF_DCP_CSCSTAT_COMPLETE(v) (((v) << 0) & 0x1) | ||
609 | |||
610 | /** | ||
611 | * Register: HW_DCP_CSCOUTBUFPARAM | ||
612 | * Address: 0x320 | ||
613 | * SCT: no | ||
614 | */ | ||
615 | #define HW_DCP_CSCOUTBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320)) | ||
616 | #define BP_DCP_CSCOUTBUFPARAM_RSVD1 24 | ||
617 | #define BM_DCP_CSCOUTBUFPARAM_RSVD1 0xff000000 | ||
618 | #define BF_DCP_CSCOUTBUFPARAM_RSVD1(v) (((v) << 24) & 0xff000000) | ||
619 | #define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE 12 | ||
620 | #define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE 0xfff000 | ||
621 | #define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000) | ||
622 | #define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE 0 | ||
623 | #define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE 0xfff | ||
624 | #define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
625 | |||
626 | /** | ||
627 | * Register: HW_DCP_CSCINBUFPARAM | ||
628 | * Address: 0x330 | ||
629 | * SCT: no | ||
630 | */ | ||
631 | #define HW_DCP_CSCINBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330)) | ||
632 | #define BP_DCP_CSCINBUFPARAM_RSVD1 12 | ||
633 | #define BM_DCP_CSCINBUFPARAM_RSVD1 0xfffff000 | ||
634 | #define BF_DCP_CSCINBUFPARAM_RSVD1(v) (((v) << 12) & 0xfffff000) | ||
635 | #define BP_DCP_CSCINBUFPARAM_LINE_SIZE 0 | ||
636 | #define BM_DCP_CSCINBUFPARAM_LINE_SIZE 0xfff | ||
637 | #define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
638 | |||
639 | /** | ||
640 | * Register: HW_DCP_CSCRGB | ||
641 | * Address: 0x340 | ||
642 | * SCT: no | ||
643 | */ | ||
644 | #define HW_DCP_CSCRGB (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340)) | ||
645 | #define BP_DCP_CSCRGB_ADDR 0 | ||
646 | #define BM_DCP_CSCRGB_ADDR 0xffffffff | ||
647 | #define BF_DCP_CSCRGB_ADDR(v) (((v) << 0) & 0xffffffff) | ||
648 | |||
649 | /** | ||
650 | * Register: HW_DCP_CSCLUMA | ||
651 | * Address: 0x350 | ||
652 | * SCT: no | ||
653 | */ | ||
654 | #define HW_DCP_CSCLUMA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350)) | ||
655 | #define BP_DCP_CSCLUMA_ADDR 0 | ||
656 | #define BM_DCP_CSCLUMA_ADDR 0xffffffff | ||
657 | #define BF_DCP_CSCLUMA_ADDR(v) (((v) << 0) & 0xffffffff) | ||
658 | |||
659 | /** | ||
660 | * Register: HW_DCP_CSCCHROMAU | ||
661 | * Address: 0x360 | ||
662 | * SCT: no | ||
663 | */ | ||
664 | #define HW_DCP_CSCCHROMAU (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360)) | ||
665 | #define BP_DCP_CSCCHROMAU_ADDR 0 | ||
666 | #define BM_DCP_CSCCHROMAU_ADDR 0xffffffff | ||
667 | #define BF_DCP_CSCCHROMAU_ADDR(v) (((v) << 0) & 0xffffffff) | ||
668 | |||
669 | /** | ||
670 | * Register: HW_DCP_CSCCHROMAV | ||
671 | * Address: 0x370 | ||
672 | * SCT: no | ||
673 | */ | ||
674 | #define HW_DCP_CSCCHROMAV (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370)) | ||
675 | #define BP_DCP_CSCCHROMAV_ADDR 0 | ||
676 | #define BM_DCP_CSCCHROMAV_ADDR 0xffffffff | ||
677 | #define BF_DCP_CSCCHROMAV_ADDR(v) (((v) << 0) & 0xffffffff) | ||
678 | |||
679 | /** | ||
680 | * Register: HW_DCP_CSCCOEFF0 | ||
681 | * Address: 0x380 | ||
682 | * SCT: no | ||
683 | */ | ||
684 | #define HW_DCP_CSCCOEFF0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380)) | ||
685 | #define BP_DCP_CSCCOEFF0_RSVD1 26 | ||
686 | #define BM_DCP_CSCCOEFF0_RSVD1 0xfc000000 | ||
687 | #define BF_DCP_CSCCOEFF0_RSVD1(v) (((v) << 26) & 0xfc000000) | ||
688 | #define BP_DCP_CSCCOEFF0_C0 16 | ||
689 | #define BM_DCP_CSCCOEFF0_C0 0x3ff0000 | ||
690 | #define BF_DCP_CSCCOEFF0_C0(v) (((v) << 16) & 0x3ff0000) | ||
691 | #define BP_DCP_CSCCOEFF0_UV_OFFSET 8 | ||
692 | #define BM_DCP_CSCCOEFF0_UV_OFFSET 0xff00 | ||
693 | #define BF_DCP_CSCCOEFF0_UV_OFFSET(v) (((v) << 8) & 0xff00) | ||
694 | #define BP_DCP_CSCCOEFF0_Y_OFFSET 0 | ||
695 | #define BM_DCP_CSCCOEFF0_Y_OFFSET 0xff | ||
696 | #define BF_DCP_CSCCOEFF0_Y_OFFSET(v) (((v) << 0) & 0xff) | ||
697 | |||
698 | /** | ||
699 | * Register: HW_DCP_CSCCOEFF1 | ||
700 | * Address: 0x390 | ||
701 | * SCT: no | ||
702 | */ | ||
703 | #define HW_DCP_CSCCOEFF1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390)) | ||
704 | #define BP_DCP_CSCCOEFF1_RSVD1 26 | ||
705 | #define BM_DCP_CSCCOEFF1_RSVD1 0xfc000000 | ||
706 | #define BF_DCP_CSCCOEFF1_RSVD1(v) (((v) << 26) & 0xfc000000) | ||
707 | #define BP_DCP_CSCCOEFF1_C1 16 | ||
708 | #define BM_DCP_CSCCOEFF1_C1 0x3ff0000 | ||
709 | #define BF_DCP_CSCCOEFF1_C1(v) (((v) << 16) & 0x3ff0000) | ||
710 | #define BP_DCP_CSCCOEFF1_RSVD0 10 | ||
711 | #define BM_DCP_CSCCOEFF1_RSVD0 0xfc00 | ||
712 | #define BF_DCP_CSCCOEFF1_RSVD0(v) (((v) << 10) & 0xfc00) | ||
713 | #define BP_DCP_CSCCOEFF1_C4 0 | ||
714 | #define BM_DCP_CSCCOEFF1_C4 0x3ff | ||
715 | #define BF_DCP_CSCCOEFF1_C4(v) (((v) << 0) & 0x3ff) | ||
716 | |||
717 | /** | ||
718 | * Register: HW_DCP_CSCCOEFF2 | ||
719 | * Address: 0x3a0 | ||
720 | * SCT: no | ||
721 | */ | ||
722 | #define HW_DCP_CSCCOEFF2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0)) | ||
723 | #define BP_DCP_CSCCOEFF2_RSVD1 26 | ||
724 | #define BM_DCP_CSCCOEFF2_RSVD1 0xfc000000 | ||
725 | #define BF_DCP_CSCCOEFF2_RSVD1(v) (((v) << 26) & 0xfc000000) | ||
726 | #define BP_DCP_CSCCOEFF2_C2 16 | ||
727 | #define BM_DCP_CSCCOEFF2_C2 0x3ff0000 | ||
728 | #define BF_DCP_CSCCOEFF2_C2(v) (((v) << 16) & 0x3ff0000) | ||
729 | #define BP_DCP_CSCCOEFF2_RSVD0 10 | ||
730 | #define BM_DCP_CSCCOEFF2_RSVD0 0xfc00 | ||
731 | #define BF_DCP_CSCCOEFF2_RSVD0(v) (((v) << 10) & 0xfc00) | ||
732 | #define BP_DCP_CSCCOEFF2_C3 0 | ||
733 | #define BM_DCP_CSCCOEFF2_C3 0x3ff | ||
734 | #define BF_DCP_CSCCOEFF2_C3(v) (((v) << 0) & 0x3ff) | ||
735 | |||
736 | /** | ||
737 | * Register: HW_DCP_CSCCLIP | ||
738 | * Address: 0x3d0 | ||
739 | * SCT: no | ||
740 | */ | ||
741 | #define HW_DCP_CSCCLIP (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3d0)) | ||
742 | #define BP_DCP_CSCCLIP_RSVD1 24 | ||
743 | #define BM_DCP_CSCCLIP_RSVD1 0xff000000 | ||
744 | #define BF_DCP_CSCCLIP_RSVD1(v) (((v) << 24) & 0xff000000) | ||
745 | #define BP_DCP_CSCCLIP_HEIGHT 12 | ||
746 | #define BM_DCP_CSCCLIP_HEIGHT 0xfff000 | ||
747 | #define BF_DCP_CSCCLIP_HEIGHT(v) (((v) << 12) & 0xfff000) | ||
748 | #define BP_DCP_CSCCLIP_WIDTH 0 | ||
749 | #define BM_DCP_CSCCLIP_WIDTH 0xfff | ||
750 | #define BF_DCP_CSCCLIP_WIDTH(v) (((v) << 0) & 0xfff) | ||
751 | |||
752 | /** | ||
753 | * Register: HW_DCP_CSCXSCALE | ||
754 | * Address: 0x3e0 | ||
755 | * SCT: no | ||
756 | */ | ||
757 | #define HW_DCP_CSCXSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0)) | ||
758 | #define BP_DCP_CSCXSCALE_RSVD1 26 | ||
759 | #define BM_DCP_CSCXSCALE_RSVD1 0xfc000000 | ||
760 | #define BF_DCP_CSCXSCALE_RSVD1(v) (((v) << 26) & 0xfc000000) | ||
761 | #define BP_DCP_CSCXSCALE_INT 24 | ||
762 | #define BM_DCP_CSCXSCALE_INT 0x3000000 | ||
763 | #define BF_DCP_CSCXSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
764 | #define BP_DCP_CSCXSCALE_FRAC 12 | ||
765 | #define BM_DCP_CSCXSCALE_FRAC 0xfff000 | ||
766 | #define BF_DCP_CSCXSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
767 | #define BP_DCP_CSCXSCALE_WIDTH 0 | ||
768 | #define BM_DCP_CSCXSCALE_WIDTH 0xfff | ||
769 | #define BF_DCP_CSCXSCALE_WIDTH(v) (((v) << 0) & 0xfff) | ||
770 | |||
771 | /** | ||
772 | * Register: HW_DCP_CSCYSCALE | ||
773 | * Address: 0x3f0 | ||
774 | * SCT: no | ||
775 | */ | ||
776 | #define HW_DCP_CSCYSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0)) | ||
777 | #define BP_DCP_CSCYSCALE_RSVD1 26 | ||
778 | #define BM_DCP_CSCYSCALE_RSVD1 0xfc000000 | ||
779 | #define BF_DCP_CSCYSCALE_RSVD1(v) (((v) << 26) & 0xfc000000) | ||
780 | #define BP_DCP_CSCYSCALE_INT 24 | ||
781 | #define BM_DCP_CSCYSCALE_INT 0x3000000 | ||
782 | #define BF_DCP_CSCYSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
783 | #define BP_DCP_CSCYSCALE_FRAC 12 | ||
784 | #define BM_DCP_CSCYSCALE_FRAC 0xfff000 | ||
785 | #define BF_DCP_CSCYSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
786 | #define BP_DCP_CSCYSCALE_HEIGHT 0 | ||
787 | #define BM_DCP_CSCYSCALE_HEIGHT 0xfff | ||
788 | #define BF_DCP_CSCYSCALE_HEIGHT(v) (((v) << 0) & 0xfff) | ||
789 | |||
790 | /** | ||
791 | * Register: HW_DCP_DBGSELECT | ||
792 | * Address: 0x400 | ||
793 | * SCT: no | ||
794 | */ | ||
795 | #define HW_DCP_DBGSELECT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400)) | ||
796 | #define BP_DCP_DBGSELECT_RSVD 8 | ||
797 | #define BM_DCP_DBGSELECT_RSVD 0xffffff00 | ||
798 | #define BF_DCP_DBGSELECT_RSVD(v) (((v) << 8) & 0xffffff00) | ||
799 | #define BP_DCP_DBGSELECT_INDEX 0 | ||
800 | #define BM_DCP_DBGSELECT_INDEX 0xff | ||
801 | #define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1 | ||
802 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10 | ||
803 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11 | ||
804 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12 | ||
805 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13 | ||
806 | #define BF_DCP_DBGSELECT_INDEX(v) (((v) << 0) & 0xff) | ||
807 | #define BF_DCP_DBGSELECT_INDEX_V(v) ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff) | ||
808 | |||
809 | /** | ||
810 | * Register: HW_DCP_DBGDATA | ||
811 | * Address: 0x410 | ||
812 | * SCT: no | ||
813 | */ | ||
814 | #define HW_DCP_DBGDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410)) | ||
815 | #define BP_DCP_DBGDATA_DATA 0 | ||
816 | #define BM_DCP_DBGDATA_DATA 0xffffffff | ||
817 | #define BF_DCP_DBGDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
818 | |||
819 | /** | ||
820 | * Register: HW_DCP_PAGETABLE | ||
821 | * Address: 0x420 | ||
822 | * SCT: no | ||
823 | */ | ||
824 | #define HW_DCP_PAGETABLE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420)) | ||
825 | #define BP_DCP_PAGETABLE_BASE 2 | ||
826 | #define BM_DCP_PAGETABLE_BASE 0xfffffffc | ||
827 | #define BF_DCP_PAGETABLE_BASE(v) (((v) << 2) & 0xfffffffc) | ||
828 | #define BP_DCP_PAGETABLE_FLUSH 1 | ||
829 | #define BM_DCP_PAGETABLE_FLUSH 0x2 | ||
830 | #define BF_DCP_PAGETABLE_FLUSH(v) (((v) << 1) & 0x2) | ||
831 | #define BP_DCP_PAGETABLE_ENABLE 0 | ||
832 | #define BM_DCP_PAGETABLE_ENABLE 0x1 | ||
833 | #define BF_DCP_PAGETABLE_ENABLE(v) (((v) << 0) & 0x1) | ||
834 | |||
835 | /** | ||
836 | * Register: HW_DCP_VERSION | ||
837 | * Address: 0x430 | ||
838 | * SCT: no | ||
839 | */ | ||
840 | #define HW_DCP_VERSION (*(volatile unsigned long *)(REGS_DCP_BASE + 0x430)) | ||
841 | #define BP_DCP_VERSION_MAJOR 24 | ||
842 | #define BM_DCP_VERSION_MAJOR 0xff000000 | ||
843 | #define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
844 | #define BP_DCP_VERSION_MINOR 16 | ||
845 | #define BM_DCP_VERSION_MINOR 0xff0000 | ||
846 | #define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
847 | #define BP_DCP_VERSION_STEP 0 | ||
848 | #define BM_DCP_VERSION_STEP 0xffff | ||
849 | #define BF_DCP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
850 | |||
851 | #endif /* __HEADERGEN__IMX233__DCP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-digctl.h b/firmware/target/arm/imx233/regs/imx233/regs-digctl.h new file mode 100644 index 0000000000..a709d296c8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-digctl.h | |||
@@ -0,0 +1,966 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__DIGCTL__H__ | ||
24 | #define __HEADERGEN__IMX233__DIGCTL__H__ | ||
25 | |||
26 | #define REGS_DIGCTL_BASE (0x8001c000) | ||
27 | |||
28 | #define REGS_DIGCTL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DIGCTL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DIGCTL_CTRL_RSVD3 31 | ||
40 | #define BM_DIGCTL_CTRL_RSVD3 0x80000000 | ||
41 | #define BF_DIGCTL_CTRL_RSVD3(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_DIGCTL_CTRL_XTAL24M_GATE 30 | ||
43 | #define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000 | ||
44 | #define BF_DIGCTL_CTRL_XTAL24M_GATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_DIGCTL_CTRL_TRAP_IRQ 29 | ||
46 | #define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 | ||
47 | #define BF_DIGCTL_CTRL_TRAP_IRQ(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_DIGCTL_CTRL_RSVD2 27 | ||
49 | #define BM_DIGCTL_CTRL_RSVD2 0x18000000 | ||
50 | #define BF_DIGCTL_CTRL_RSVD2(v) (((v) << 27) & 0x18000000) | ||
51 | #define BP_DIGCTL_CTRL_CACHE_BIST_TMODE 26 | ||
52 | #define BM_DIGCTL_CTRL_CACHE_BIST_TMODE 0x4000000 | ||
53 | #define BF_DIGCTL_CTRL_CACHE_BIST_TMODE(v) (((v) << 26) & 0x4000000) | ||
54 | #define BP_DIGCTL_CTRL_LCD_BIST_CLKEN 25 | ||
55 | #define BM_DIGCTL_CTRL_LCD_BIST_CLKEN 0x2000000 | ||
56 | #define BF_DIGCTL_CTRL_LCD_BIST_CLKEN(v) (((v) << 25) & 0x2000000) | ||
57 | #define BP_DIGCTL_CTRL_LCD_BIST_START 24 | ||
58 | #define BM_DIGCTL_CTRL_LCD_BIST_START 0x1000000 | ||
59 | #define BF_DIGCTL_CTRL_LCD_BIST_START(v) (((v) << 24) & 0x1000000) | ||
60 | #define BP_DIGCTL_CTRL_DCP_BIST_CLKEN 23 | ||
61 | #define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x800000 | ||
62 | #define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v) (((v) << 23) & 0x800000) | ||
63 | #define BP_DIGCTL_CTRL_DCP_BIST_START 22 | ||
64 | #define BM_DIGCTL_CTRL_DCP_BIST_START 0x400000 | ||
65 | #define BF_DIGCTL_CTRL_DCP_BIST_START(v) (((v) << 22) & 0x400000) | ||
66 | #define BP_DIGCTL_CTRL_ARM_BIST_CLKEN 21 | ||
67 | #define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x200000 | ||
68 | #define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v) (((v) << 21) & 0x200000) | ||
69 | #define BP_DIGCTL_CTRL_USB_TESTMODE 20 | ||
70 | #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 | ||
71 | #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) | ||
72 | #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 | ||
73 | #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 | ||
74 | #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) | ||
75 | #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 | ||
76 | #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 | ||
77 | #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) | ||
78 | #define BP_DIGCTL_CTRL_ARM_BIST_START 17 | ||
79 | #define BM_DIGCTL_CTRL_ARM_BIST_START 0x20000 | ||
80 | #define BF_DIGCTL_CTRL_ARM_BIST_START(v) (((v) << 17) & 0x20000) | ||
81 | #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 | ||
82 | #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 | ||
83 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 | ||
84 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 | ||
85 | #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) | ||
86 | #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) | ||
87 | #define BP_DIGCTL_CTRL_SAIF_LOOPBACK 15 | ||
88 | #define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x8000 | ||
89 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 | ||
90 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 | ||
91 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v) (((v) << 15) & 0x8000) | ||
92 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000) | ||
93 | #define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 | ||
94 | #define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x6000 | ||
95 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 | ||
96 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 | ||
97 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 | ||
98 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 | ||
99 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) (((v) << 13) & 0x6000) | ||
100 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000) | ||
101 | #define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL 12 | ||
102 | #define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x1000 | ||
103 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 | ||
104 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 | ||
105 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) (((v) << 12) & 0x1000) | ||
106 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000) | ||
107 | #define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 11 | ||
108 | #define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x800 | ||
109 | #define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) (((v) << 11) & 0x800) | ||
110 | #define BP_DIGCTL_CTRL_RSVD1 10 | ||
111 | #define BM_DIGCTL_CTRL_RSVD1 0x400 | ||
112 | #define BF_DIGCTL_CTRL_RSVD1(v) (((v) << 10) & 0x400) | ||
113 | #define BP_DIGCTL_CTRL_SY_ENDIAN 9 | ||
114 | #define BM_DIGCTL_CTRL_SY_ENDIAN 0x200 | ||
115 | #define BF_DIGCTL_CTRL_SY_ENDIAN(v) (((v) << 9) & 0x200) | ||
116 | #define BP_DIGCTL_CTRL_SY_SFTRST 8 | ||
117 | #define BM_DIGCTL_CTRL_SY_SFTRST 0x100 | ||
118 | #define BF_DIGCTL_CTRL_SY_SFTRST(v) (((v) << 8) & 0x100) | ||
119 | #define BP_DIGCTL_CTRL_SY_CLKGATE 7 | ||
120 | #define BM_DIGCTL_CTRL_SY_CLKGATE 0x80 | ||
121 | #define BF_DIGCTL_CTRL_SY_CLKGATE(v) (((v) << 7) & 0x80) | ||
122 | #define BP_DIGCTL_CTRL_USE_SERIAL_JTAG 6 | ||
123 | #define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x40 | ||
124 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 | ||
125 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 | ||
126 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v) (((v) << 6) & 0x40) | ||
127 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v) ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40) | ||
128 | #define BP_DIGCTL_CTRL_TRAP_IN_RANGE 5 | ||
129 | #define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x20 | ||
130 | #define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v) (((v) << 5) & 0x20) | ||
131 | #define BP_DIGCTL_CTRL_TRAP_ENABLE 4 | ||
132 | #define BM_DIGCTL_CTRL_TRAP_ENABLE 0x10 | ||
133 | #define BF_DIGCTL_CTRL_TRAP_ENABLE(v) (((v) << 4) & 0x10) | ||
134 | #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 | ||
135 | #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 | ||
136 | #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) | ||
137 | #define BP_DIGCTL_CTRL_USB_CLKGATE 2 | ||
138 | #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 | ||
139 | #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 | ||
140 | #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 | ||
141 | #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) | ||
142 | #define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) | ||
143 | #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 | ||
144 | #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 | ||
145 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 | ||
146 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 | ||
147 | #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) | ||
148 | #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) | ||
149 | #define BP_DIGCTL_CTRL_LATCH_ENTROPY 0 | ||
150 | #define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x1 | ||
151 | #define BF_DIGCTL_CTRL_LATCH_ENTROPY(v) (((v) << 0) & 0x1) | ||
152 | |||
153 | /** | ||
154 | * Register: HW_DIGCTL_STATUS | ||
155 | * Address: 0x10 | ||
156 | * SCT: yes | ||
157 | */ | ||
158 | #define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x0)) | ||
159 | #define HW_DIGCTL_STATUS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x4)) | ||
160 | #define HW_DIGCTL_STATUS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x8)) | ||
161 | #define HW_DIGCTL_STATUS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0xc)) | ||
162 | #define BP_DIGCTL_STATUS_USB_HS_PRESENT 31 | ||
163 | #define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 | ||
164 | #define BF_DIGCTL_STATUS_USB_HS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
165 | #define BP_DIGCTL_STATUS_USB_OTG_PRESENT 30 | ||
166 | #define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 | ||
167 | #define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v) (((v) << 30) & 0x40000000) | ||
168 | #define BP_DIGCTL_STATUS_USB_HOST_PRESENT 29 | ||
169 | #define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 | ||
170 | #define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v) (((v) << 29) & 0x20000000) | ||
171 | #define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT 28 | ||
172 | #define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 | ||
173 | #define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
174 | #define BP_DIGCTL_STATUS_RSVD2 11 | ||
175 | #define BM_DIGCTL_STATUS_RSVD2 0xffff800 | ||
176 | #define BF_DIGCTL_STATUS_RSVD2(v) (((v) << 11) & 0xffff800) | ||
177 | #define BP_DIGCTL_STATUS_DCP_BIST_FAIL 10 | ||
178 | #define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x400 | ||
179 | #define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v) (((v) << 10) & 0x400) | ||
180 | #define BP_DIGCTL_STATUS_DCP_BIST_PASS 9 | ||
181 | #define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x200 | ||
182 | #define BF_DIGCTL_STATUS_DCP_BIST_PASS(v) (((v) << 9) & 0x200) | ||
183 | #define BP_DIGCTL_STATUS_DCP_BIST_DONE 8 | ||
184 | #define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x100 | ||
185 | #define BF_DIGCTL_STATUS_DCP_BIST_DONE(v) (((v) << 8) & 0x100) | ||
186 | #define BP_DIGCTL_STATUS_LCD_BIST_FAIL 7 | ||
187 | #define BM_DIGCTL_STATUS_LCD_BIST_FAIL 0x80 | ||
188 | #define BF_DIGCTL_STATUS_LCD_BIST_FAIL(v) (((v) << 7) & 0x80) | ||
189 | #define BP_DIGCTL_STATUS_LCD_BIST_PASS 6 | ||
190 | #define BM_DIGCTL_STATUS_LCD_BIST_PASS 0x40 | ||
191 | #define BF_DIGCTL_STATUS_LCD_BIST_PASS(v) (((v) << 6) & 0x40) | ||
192 | #define BP_DIGCTL_STATUS_LCD_BIST_DONE 5 | ||
193 | #define BM_DIGCTL_STATUS_LCD_BIST_DONE 0x20 | ||
194 | #define BF_DIGCTL_STATUS_LCD_BIST_DONE(v) (((v) << 5) & 0x20) | ||
195 | #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 | ||
196 | #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 | ||
197 | #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) | ||
198 | #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 | ||
199 | #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0xe | ||
200 | #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0xe) | ||
201 | #define BP_DIGCTL_STATUS_WRITTEN 0 | ||
202 | #define BM_DIGCTL_STATUS_WRITTEN 0x1 | ||
203 | #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) | ||
204 | |||
205 | /** | ||
206 | * Register: HW_DIGCTL_HCLKCOUNT | ||
207 | * Address: 0x20 | ||
208 | * SCT: yes | ||
209 | */ | ||
210 | #define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x0)) | ||
211 | #define HW_DIGCTL_HCLKCOUNT_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x4)) | ||
212 | #define HW_DIGCTL_HCLKCOUNT_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x8)) | ||
213 | #define HW_DIGCTL_HCLKCOUNT_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0xc)) | ||
214 | #define BP_DIGCTL_HCLKCOUNT_COUNT 0 | ||
215 | #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff | ||
216 | #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) | ||
217 | |||
218 | /** | ||
219 | * Register: HW_DIGCTL_RAMCTRL | ||
220 | * Address: 0x30 | ||
221 | * SCT: yes | ||
222 | */ | ||
223 | #define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) | ||
224 | #define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) | ||
225 | #define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) | ||
226 | #define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) | ||
227 | #define BP_DIGCTL_RAMCTRL_RSVD1 12 | ||
228 | #define BM_DIGCTL_RAMCTRL_RSVD1 0xfffff000 | ||
229 | #define BF_DIGCTL_RAMCTRL_RSVD1(v) (((v) << 12) & 0xfffff000) | ||
230 | #define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 | ||
231 | #define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0xf00 | ||
232 | #define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) (((v) << 8) & 0xf00) | ||
233 | #define BP_DIGCTL_RAMCTRL_RSVD0 1 | ||
234 | #define BM_DIGCTL_RAMCTRL_RSVD0 0xfe | ||
235 | #define BF_DIGCTL_RAMCTRL_RSVD0(v) (((v) << 1) & 0xfe) | ||
236 | #define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0 | ||
237 | #define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x1 | ||
238 | #define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) (((v) << 0) & 0x1) | ||
239 | |||
240 | /** | ||
241 | * Register: HW_DIGCTL_RAMREPAIR | ||
242 | * Address: 0x40 | ||
243 | * SCT: yes | ||
244 | */ | ||
245 | #define HW_DIGCTL_RAMREPAIR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) | ||
246 | #define HW_DIGCTL_RAMREPAIR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) | ||
247 | #define HW_DIGCTL_RAMREPAIR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) | ||
248 | #define HW_DIGCTL_RAMREPAIR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) | ||
249 | #define BP_DIGCTL_RAMREPAIR_RSVD1 16 | ||
250 | #define BM_DIGCTL_RAMREPAIR_RSVD1 0xffff0000 | ||
251 | #define BF_DIGCTL_RAMREPAIR_RSVD1(v) (((v) << 16) & 0xffff0000) | ||
252 | #define BP_DIGCTL_RAMREPAIR_ADDR 0 | ||
253 | #define BM_DIGCTL_RAMREPAIR_ADDR 0xffff | ||
254 | #define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) << 0) & 0xffff) | ||
255 | |||
256 | /** | ||
257 | * Register: HW_DIGCTL_ROMCTRL | ||
258 | * Address: 0x50 | ||
259 | * SCT: yes | ||
260 | */ | ||
261 | #define HW_DIGCTL_ROMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) | ||
262 | #define HW_DIGCTL_ROMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) | ||
263 | #define HW_DIGCTL_ROMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) | ||
264 | #define HW_DIGCTL_ROMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) | ||
265 | #define BP_DIGCTL_ROMCTRL_RSVD0 4 | ||
266 | #define BM_DIGCTL_ROMCTRL_RSVD0 0xfffffff0 | ||
267 | #define BF_DIGCTL_ROMCTRL_RSVD0(v) (((v) << 4) & 0xfffffff0) | ||
268 | #define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 | ||
269 | #define BM_DIGCTL_ROMCTRL_RD_MARGIN 0xf | ||
270 | #define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) (((v) << 0) & 0xf) | ||
271 | |||
272 | /** | ||
273 | * Register: HW_DIGCTL_WRITEONCE | ||
274 | * Address: 0x60 | ||
275 | * SCT: no | ||
276 | */ | ||
277 | #define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) | ||
278 | #define BP_DIGCTL_WRITEONCE_BITS 0 | ||
279 | #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff | ||
280 | #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) | ||
281 | |||
282 | /** | ||
283 | * Register: HW_DIGCTL_ENTROPY | ||
284 | * Address: 0x90 | ||
285 | * SCT: no | ||
286 | */ | ||
287 | #define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) | ||
288 | #define BP_DIGCTL_ENTROPY_VALUE 0 | ||
289 | #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff | ||
290 | #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) | ||
291 | |||
292 | /** | ||
293 | * Register: HW_DIGCTL_ENTROPY_LATCHED | ||
294 | * Address: 0xa0 | ||
295 | * SCT: no | ||
296 | */ | ||
297 | #define HW_DIGCTL_ENTROPY_LATCHED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) | ||
298 | #define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 | ||
299 | #define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xffffffff | ||
300 | #define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (((v) << 0) & 0xffffffff) | ||
301 | |||
302 | /** | ||
303 | * Register: HW_DIGCTL_SJTAGDBG | ||
304 | * Address: 0xb0 | ||
305 | * SCT: yes | ||
306 | */ | ||
307 | #define HW_DIGCTL_SJTAGDBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) | ||
308 | #define HW_DIGCTL_SJTAGDBG_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) | ||
309 | #define HW_DIGCTL_SJTAGDBG_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) | ||
310 | #define HW_DIGCTL_SJTAGDBG_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) | ||
311 | #define BP_DIGCTL_SJTAGDBG_RSVD2 27 | ||
312 | #define BM_DIGCTL_SJTAGDBG_RSVD2 0xf8000000 | ||
313 | #define BF_DIGCTL_SJTAGDBG_RSVD2(v) (((v) << 27) & 0xf8000000) | ||
314 | #define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 | ||
315 | #define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x7ff0000 | ||
316 | #define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) (((v) << 16) & 0x7ff0000) | ||
317 | #define BP_DIGCTL_SJTAGDBG_RSVD1 11 | ||
318 | #define BM_DIGCTL_SJTAGDBG_RSVD1 0xf800 | ||
319 | #define BF_DIGCTL_SJTAGDBG_RSVD1(v) (((v) << 11) & 0xf800) | ||
320 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDO 10 | ||
321 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x400 | ||
322 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v) (((v) << 10) & 0x400) | ||
323 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDI 9 | ||
324 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x200 | ||
325 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v) (((v) << 9) & 0x200) | ||
326 | #define BP_DIGCTL_SJTAGDBG_SJTAG_MODE 8 | ||
327 | #define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x100 | ||
328 | #define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v) (((v) << 8) & 0x100) | ||
329 | #define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 | ||
330 | #define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0xf0 | ||
331 | #define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) (((v) << 4) & 0xf0) | ||
332 | #define BP_DIGCTL_SJTAGDBG_ACTIVE 3 | ||
333 | #define BM_DIGCTL_SJTAGDBG_ACTIVE 0x8 | ||
334 | #define BF_DIGCTL_SJTAGDBG_ACTIVE(v) (((v) << 3) & 0x8) | ||
335 | #define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 2 | ||
336 | #define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x4 | ||
337 | #define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) (((v) << 2) & 0x4) | ||
338 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 1 | ||
339 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x2 | ||
340 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) (((v) << 1) & 0x2) | ||
341 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0 | ||
342 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x1 | ||
343 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) (((v) << 0) & 0x1) | ||
344 | |||
345 | /** | ||
346 | * Register: HW_DIGCTL_MICROSECONDS | ||
347 | * Address: 0xc0 | ||
348 | * SCT: yes | ||
349 | */ | ||
350 | #define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0)) | ||
351 | #define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4)) | ||
352 | #define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8)) | ||
353 | #define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc)) | ||
354 | #define BP_DIGCTL_MICROSECONDS_VALUE 0 | ||
355 | #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff | ||
356 | #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) | ||
357 | |||
358 | /** | ||
359 | * Register: HW_DIGCTL_DBGRD | ||
360 | * Address: 0xd0 | ||
361 | * SCT: no | ||
362 | */ | ||
363 | #define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) | ||
364 | #define BP_DIGCTL_DBGRD_COMPLEMENT 0 | ||
365 | #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff | ||
366 | #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) | ||
367 | |||
368 | /** | ||
369 | * Register: HW_DIGCTL_DBG | ||
370 | * Address: 0xe0 | ||
371 | * SCT: no | ||
372 | */ | ||
373 | #define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0)) | ||
374 | #define BP_DIGCTL_DBG_VALUE 0 | ||
375 | #define BM_DIGCTL_DBG_VALUE 0xffffffff | ||
376 | #define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) | ||
377 | |||
378 | /** | ||
379 | * Register: HW_DIGCTL_OCRAM_BIST_CSR | ||
380 | * Address: 0xf0 | ||
381 | * SCT: yes | ||
382 | */ | ||
383 | #define HW_DIGCTL_OCRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0)) | ||
384 | #define HW_DIGCTL_OCRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4)) | ||
385 | #define HW_DIGCTL_OCRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8)) | ||
386 | #define HW_DIGCTL_OCRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc)) | ||
387 | #define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1 11 | ||
388 | #define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 0xfffff800 | ||
389 | #define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) (((v) << 11) & 0xfffff800) | ||
390 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 10 | ||
391 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 0x400 | ||
392 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(v) (((v) << 10) & 0x400) | ||
393 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 9 | ||
394 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x200 | ||
395 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) (((v) << 9) & 0x200) | ||
396 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 8 | ||
397 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x100 | ||
398 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) (((v) << 8) & 0x100) | ||
399 | #define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0 4 | ||
400 | #define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 0xf0 | ||
401 | #define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v) (((v) << 4) & 0xf0) | ||
402 | #define BP_DIGCTL_OCRAM_BIST_CSR_FAIL 3 | ||
403 | #define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x8 | ||
404 | #define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) | ||
405 | #define BP_DIGCTL_OCRAM_BIST_CSR_PASS 2 | ||
406 | #define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x4 | ||
407 | #define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) | ||
408 | #define BP_DIGCTL_OCRAM_BIST_CSR_DONE 1 | ||
409 | #define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x2 | ||
410 | #define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) | ||
411 | #define BP_DIGCTL_OCRAM_BIST_CSR_START 0 | ||
412 | #define BM_DIGCTL_OCRAM_BIST_CSR_START 0x1 | ||
413 | #define BF_DIGCTL_OCRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) | ||
414 | |||
415 | /** | ||
416 | * Register: HW_DIGCTL_OCRAM_STATUS0 | ||
417 | * Address: 0x110 | ||
418 | * SCT: yes | ||
419 | */ | ||
420 | #define HW_DIGCTL_OCRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x0)) | ||
421 | #define HW_DIGCTL_OCRAM_STATUS0_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x4)) | ||
422 | #define HW_DIGCTL_OCRAM_STATUS0_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x8)) | ||
423 | #define HW_DIGCTL_OCRAM_STATUS0_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0xc)) | ||
424 | #define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 | ||
425 | #define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xffffffff | ||
426 | #define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) | ||
427 | |||
428 | /** | ||
429 | * Register: HW_DIGCTL_OCRAM_STATUS1 | ||
430 | * Address: 0x120 | ||
431 | * SCT: yes | ||
432 | */ | ||
433 | #define HW_DIGCTL_OCRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x0)) | ||
434 | #define HW_DIGCTL_OCRAM_STATUS1_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x4)) | ||
435 | #define HW_DIGCTL_OCRAM_STATUS1_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x8)) | ||
436 | #define HW_DIGCTL_OCRAM_STATUS1_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0xc)) | ||
437 | #define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 | ||
438 | #define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xffffffff | ||
439 | #define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) | ||
440 | |||
441 | /** | ||
442 | * Register: HW_DIGCTL_OCRAM_STATUS2 | ||
443 | * Address: 0x130 | ||
444 | * SCT: yes | ||
445 | */ | ||
446 | #define HW_DIGCTL_OCRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x0)) | ||
447 | #define HW_DIGCTL_OCRAM_STATUS2_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x4)) | ||
448 | #define HW_DIGCTL_OCRAM_STATUS2_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x8)) | ||
449 | #define HW_DIGCTL_OCRAM_STATUS2_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0xc)) | ||
450 | #define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 | ||
451 | #define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xffffffff | ||
452 | #define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) | ||
453 | |||
454 | /** | ||
455 | * Register: HW_DIGCTL_OCRAM_STATUS3 | ||
456 | * Address: 0x140 | ||
457 | * SCT: yes | ||
458 | */ | ||
459 | #define HW_DIGCTL_OCRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x0)) | ||
460 | #define HW_DIGCTL_OCRAM_STATUS3_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x4)) | ||
461 | #define HW_DIGCTL_OCRAM_STATUS3_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x8)) | ||
462 | #define HW_DIGCTL_OCRAM_STATUS3_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0xc)) | ||
463 | #define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 | ||
464 | #define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xffffffff | ||
465 | #define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) | ||
466 | |||
467 | /** | ||
468 | * Register: HW_DIGCTL_OCRAM_STATUS4 | ||
469 | * Address: 0x150 | ||
470 | * SCT: yes | ||
471 | */ | ||
472 | #define HW_DIGCTL_OCRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x0)) | ||
473 | #define HW_DIGCTL_OCRAM_STATUS4_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x4)) | ||
474 | #define HW_DIGCTL_OCRAM_STATUS4_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x8)) | ||
475 | #define HW_DIGCTL_OCRAM_STATUS4_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0xc)) | ||
476 | #define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 | ||
477 | #define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xffffffff | ||
478 | #define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) | ||
479 | |||
480 | /** | ||
481 | * Register: HW_DIGCTL_OCRAM_STATUS5 | ||
482 | * Address: 0x160 | ||
483 | * SCT: yes | ||
484 | */ | ||
485 | #define HW_DIGCTL_OCRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x0)) | ||
486 | #define HW_DIGCTL_OCRAM_STATUS5_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x4)) | ||
487 | #define HW_DIGCTL_OCRAM_STATUS5_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x8)) | ||
488 | #define HW_DIGCTL_OCRAM_STATUS5_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0xc)) | ||
489 | #define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 | ||
490 | #define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xffffffff | ||
491 | #define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) | ||
492 | |||
493 | /** | ||
494 | * Register: HW_DIGCTL_OCRAM_STATUS6 | ||
495 | * Address: 0x170 | ||
496 | * SCT: yes | ||
497 | */ | ||
498 | #define HW_DIGCTL_OCRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x0)) | ||
499 | #define HW_DIGCTL_OCRAM_STATUS6_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x4)) | ||
500 | #define HW_DIGCTL_OCRAM_STATUS6_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x8)) | ||
501 | #define HW_DIGCTL_OCRAM_STATUS6_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0xc)) | ||
502 | #define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 | ||
503 | #define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xffffffff | ||
504 | #define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) | ||
505 | |||
506 | /** | ||
507 | * Register: HW_DIGCTL_OCRAM_STATUS7 | ||
508 | * Address: 0x180 | ||
509 | * SCT: yes | ||
510 | */ | ||
511 | #define HW_DIGCTL_OCRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x0)) | ||
512 | #define HW_DIGCTL_OCRAM_STATUS7_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x4)) | ||
513 | #define HW_DIGCTL_OCRAM_STATUS7_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x8)) | ||
514 | #define HW_DIGCTL_OCRAM_STATUS7_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0xc)) | ||
515 | #define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 | ||
516 | #define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xffffffff | ||
517 | #define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) | ||
518 | |||
519 | /** | ||
520 | * Register: HW_DIGCTL_OCRAM_STATUS8 | ||
521 | * Address: 0x190 | ||
522 | * SCT: yes | ||
523 | */ | ||
524 | #define HW_DIGCTL_OCRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x0)) | ||
525 | #define HW_DIGCTL_OCRAM_STATUS8_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x4)) | ||
526 | #define HW_DIGCTL_OCRAM_STATUS8_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x8)) | ||
527 | #define HW_DIGCTL_OCRAM_STATUS8_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0xc)) | ||
528 | #define BP_DIGCTL_OCRAM_STATUS8_RSVD3 29 | ||
529 | #define BM_DIGCTL_OCRAM_STATUS8_RSVD3 0xe0000000 | ||
530 | #define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v) (((v) << 29) & 0xe0000000) | ||
531 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 | ||
532 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0x1fff0000 | ||
533 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0x1fff0000) | ||
534 | #define BP_DIGCTL_OCRAM_STATUS8_RSVD2 13 | ||
535 | #define BM_DIGCTL_OCRAM_STATUS8_RSVD2 0xe000 | ||
536 | #define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v) (((v) << 13) & 0xe000) | ||
537 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 | ||
538 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x1fff | ||
539 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0x1fff) | ||
540 | |||
541 | /** | ||
542 | * Register: HW_DIGCTL_OCRAM_STATUS9 | ||
543 | * Address: 0x1a0 | ||
544 | * SCT: yes | ||
545 | */ | ||
546 | #define HW_DIGCTL_OCRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x0)) | ||
547 | #define HW_DIGCTL_OCRAM_STATUS9_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x4)) | ||
548 | #define HW_DIGCTL_OCRAM_STATUS9_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x8)) | ||
549 | #define HW_DIGCTL_OCRAM_STATUS9_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0xc)) | ||
550 | #define BP_DIGCTL_OCRAM_STATUS9_RSVD3 29 | ||
551 | #define BM_DIGCTL_OCRAM_STATUS9_RSVD3 0xe0000000 | ||
552 | #define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v) (((v) << 29) & 0xe0000000) | ||
553 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 | ||
554 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0x1fff0000 | ||
555 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0x1fff0000) | ||
556 | #define BP_DIGCTL_OCRAM_STATUS9_RSVD2 13 | ||
557 | #define BM_DIGCTL_OCRAM_STATUS9_RSVD2 0xe000 | ||
558 | #define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v) (((v) << 13) & 0xe000) | ||
559 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 | ||
560 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x1fff | ||
561 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0x1fff) | ||
562 | |||
563 | /** | ||
564 | * Register: HW_DIGCTL_OCRAM_STATUS10 | ||
565 | * Address: 0x1b0 | ||
566 | * SCT: yes | ||
567 | */ | ||
568 | #define HW_DIGCTL_OCRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x0)) | ||
569 | #define HW_DIGCTL_OCRAM_STATUS10_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x4)) | ||
570 | #define HW_DIGCTL_OCRAM_STATUS10_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x8)) | ||
571 | #define HW_DIGCTL_OCRAM_STATUS10_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0xc)) | ||
572 | #define BP_DIGCTL_OCRAM_STATUS10_RSVD3 29 | ||
573 | #define BM_DIGCTL_OCRAM_STATUS10_RSVD3 0xe0000000 | ||
574 | #define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v) (((v) << 29) & 0xe0000000) | ||
575 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 | ||
576 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0x1fff0000 | ||
577 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0x1fff0000) | ||
578 | #define BP_DIGCTL_OCRAM_STATUS10_RSVD2 13 | ||
579 | #define BM_DIGCTL_OCRAM_STATUS10_RSVD2 0xe000 | ||
580 | #define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v) (((v) << 13) & 0xe000) | ||
581 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 | ||
582 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x1fff | ||
583 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0x1fff) | ||
584 | |||
585 | /** | ||
586 | * Register: HW_DIGCTL_OCRAM_STATUS11 | ||
587 | * Address: 0x1c0 | ||
588 | * SCT: yes | ||
589 | */ | ||
590 | #define HW_DIGCTL_OCRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x0)) | ||
591 | #define HW_DIGCTL_OCRAM_STATUS11_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x4)) | ||
592 | #define HW_DIGCTL_OCRAM_STATUS11_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x8)) | ||
593 | #define HW_DIGCTL_OCRAM_STATUS11_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0xc)) | ||
594 | #define BP_DIGCTL_OCRAM_STATUS11_RSVD3 29 | ||
595 | #define BM_DIGCTL_OCRAM_STATUS11_RSVD3 0xe0000000 | ||
596 | #define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v) (((v) << 29) & 0xe0000000) | ||
597 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 | ||
598 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0x1fff0000 | ||
599 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0x1fff0000) | ||
600 | #define BP_DIGCTL_OCRAM_STATUS11_RSVD2 13 | ||
601 | #define BM_DIGCTL_OCRAM_STATUS11_RSVD2 0xe000 | ||
602 | #define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v) (((v) << 13) & 0xe000) | ||
603 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 | ||
604 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x1fff | ||
605 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0x1fff) | ||
606 | |||
607 | /** | ||
608 | * Register: HW_DIGCTL_OCRAM_STATUS12 | ||
609 | * Address: 0x1d0 | ||
610 | * SCT: yes | ||
611 | */ | ||
612 | #define HW_DIGCTL_OCRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x0)) | ||
613 | #define HW_DIGCTL_OCRAM_STATUS12_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x4)) | ||
614 | #define HW_DIGCTL_OCRAM_STATUS12_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x8)) | ||
615 | #define HW_DIGCTL_OCRAM_STATUS12_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0xc)) | ||
616 | #define BP_DIGCTL_OCRAM_STATUS12_RSVD3 28 | ||
617 | #define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0xf0000000 | ||
618 | #define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v) (((v) << 28) & 0xf0000000) | ||
619 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 | ||
620 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0xf000000 | ||
621 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0xf000000) | ||
622 | #define BP_DIGCTL_OCRAM_STATUS12_RSVD2 20 | ||
623 | #define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0xf00000 | ||
624 | #define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v) (((v) << 20) & 0xf00000) | ||
625 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 | ||
626 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0xf0000 | ||
627 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0xf0000) | ||
628 | #define BP_DIGCTL_OCRAM_STATUS12_RSVD1 12 | ||
629 | #define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0xf000 | ||
630 | #define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v) (((v) << 12) & 0xf000) | ||
631 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 | ||
632 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0xf00 | ||
633 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0xf00) | ||
634 | #define BP_DIGCTL_OCRAM_STATUS12_RSVD0 4 | ||
635 | #define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0xf0 | ||
636 | #define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v) (((v) << 4) & 0xf0) | ||
637 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 | ||
638 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0xf | ||
639 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0xf) | ||
640 | |||
641 | /** | ||
642 | * Register: HW_DIGCTL_OCRAM_STATUS13 | ||
643 | * Address: 0x1e0 | ||
644 | * SCT: yes | ||
645 | */ | ||
646 | #define HW_DIGCTL_OCRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x0)) | ||
647 | #define HW_DIGCTL_OCRAM_STATUS13_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x4)) | ||
648 | #define HW_DIGCTL_OCRAM_STATUS13_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x8)) | ||
649 | #define HW_DIGCTL_OCRAM_STATUS13_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0xc)) | ||
650 | #define BP_DIGCTL_OCRAM_STATUS13_RSVD3 28 | ||
651 | #define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0xf0000000 | ||
652 | #define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v) (((v) << 28) & 0xf0000000) | ||
653 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 | ||
654 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0xf000000 | ||
655 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0xf000000) | ||
656 | #define BP_DIGCTL_OCRAM_STATUS13_RSVD2 20 | ||
657 | #define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0xf00000 | ||
658 | #define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v) (((v) << 20) & 0xf00000) | ||
659 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 | ||
660 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0xf0000 | ||
661 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0xf0000) | ||
662 | #define BP_DIGCTL_OCRAM_STATUS13_RSVD1 12 | ||
663 | #define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0xf000 | ||
664 | #define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v) (((v) << 12) & 0xf000) | ||
665 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 | ||
666 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0xf00 | ||
667 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0xf00) | ||
668 | #define BP_DIGCTL_OCRAM_STATUS13_RSVD0 4 | ||
669 | #define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0xf0 | ||
670 | #define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v) (((v) << 4) & 0xf0) | ||
671 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 | ||
672 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0xf | ||
673 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0xf) | ||
674 | |||
675 | /** | ||
676 | * Register: HW_DIGCTL_SCRATCH0 | ||
677 | * Address: 0x290 | ||
678 | * SCT: no | ||
679 | */ | ||
680 | #define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) | ||
681 | #define BP_DIGCTL_SCRATCH0_PTR 0 | ||
682 | #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff | ||
683 | #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) | ||
684 | |||
685 | /** | ||
686 | * Register: HW_DIGCTL_SCRATCH1 | ||
687 | * Address: 0x2a0 | ||
688 | * SCT: no | ||
689 | */ | ||
690 | #define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) | ||
691 | #define BP_DIGCTL_SCRATCH1_PTR 0 | ||
692 | #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff | ||
693 | #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) | ||
694 | |||
695 | /** | ||
696 | * Register: HW_DIGCTL_ARMCACHE | ||
697 | * Address: 0x2b0 | ||
698 | * SCT: no | ||
699 | */ | ||
700 | #define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) | ||
701 | #define BP_DIGCTL_ARMCACHE_RSVD4 18 | ||
702 | #define BM_DIGCTL_ARMCACHE_RSVD4 0xfffc0000 | ||
703 | #define BF_DIGCTL_ARMCACHE_RSVD4(v) (((v) << 18) & 0xfffc0000) | ||
704 | #define BP_DIGCTL_ARMCACHE_VALID_SS 16 | ||
705 | #define BM_DIGCTL_ARMCACHE_VALID_SS 0x30000 | ||
706 | #define BF_DIGCTL_ARMCACHE_VALID_SS(v) (((v) << 16) & 0x30000) | ||
707 | #define BP_DIGCTL_ARMCACHE_RSVD3 14 | ||
708 | #define BM_DIGCTL_ARMCACHE_RSVD3 0xc000 | ||
709 | #define BF_DIGCTL_ARMCACHE_RSVD3(v) (((v) << 14) & 0xc000) | ||
710 | #define BP_DIGCTL_ARMCACHE_DRTY_SS 12 | ||
711 | #define BM_DIGCTL_ARMCACHE_DRTY_SS 0x3000 | ||
712 | #define BF_DIGCTL_ARMCACHE_DRTY_SS(v) (((v) << 12) & 0x3000) | ||
713 | #define BP_DIGCTL_ARMCACHE_RSVD2 10 | ||
714 | #define BM_DIGCTL_ARMCACHE_RSVD2 0xc00 | ||
715 | #define BF_DIGCTL_ARMCACHE_RSVD2(v) (((v) << 10) & 0xc00) | ||
716 | #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 | ||
717 | #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 | ||
718 | #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) | ||
719 | #define BP_DIGCTL_ARMCACHE_RSVD1 6 | ||
720 | #define BM_DIGCTL_ARMCACHE_RSVD1 0xc0 | ||
721 | #define BF_DIGCTL_ARMCACHE_RSVD1(v) (((v) << 6) & 0xc0) | ||
722 | #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 | ||
723 | #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 | ||
724 | #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) | ||
725 | #define BP_DIGCTL_ARMCACHE_RSVD0 2 | ||
726 | #define BM_DIGCTL_ARMCACHE_RSVD0 0xc | ||
727 | #define BF_DIGCTL_ARMCACHE_RSVD0(v) (((v) << 2) & 0xc) | ||
728 | #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 | ||
729 | #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 | ||
730 | #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) | ||
731 | |||
732 | /** | ||
733 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW | ||
734 | * Address: 0x2c0 | ||
735 | * SCT: no | ||
736 | */ | ||
737 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0)) | ||
738 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 | ||
739 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xffffffff | ||
740 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (((v) << 0) & 0xffffffff) | ||
741 | |||
742 | /** | ||
743 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH | ||
744 | * Address: 0x2d0 | ||
745 | * SCT: no | ||
746 | */ | ||
747 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0)) | ||
748 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 | ||
749 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xffffffff | ||
750 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (((v) << 0) & 0xffffffff) | ||
751 | |||
752 | /** | ||
753 | * Register: HW_DIGCTL_SGTL | ||
754 | * Address: 0x300 | ||
755 | * SCT: no | ||
756 | */ | ||
757 | #define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) | ||
758 | #define BP_DIGCTL_SGTL_COPYRIGHT 0 | ||
759 | #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff | ||
760 | #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) | ||
761 | |||
762 | /** | ||
763 | * Register: HW_DIGCTL_CHIPID | ||
764 | * Address: 0x310 | ||
765 | * SCT: no | ||
766 | */ | ||
767 | #define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) | ||
768 | #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 | ||
769 | #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 | ||
770 | #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) | ||
771 | #define BP_DIGCTL_CHIPID_RSVD0 8 | ||
772 | #define BM_DIGCTL_CHIPID_RSVD0 0xff00 | ||
773 | #define BF_DIGCTL_CHIPID_RSVD0(v) (((v) << 8) & 0xff00) | ||
774 | #define BP_DIGCTL_CHIPID_REVISION 0 | ||
775 | #define BM_DIGCTL_CHIPID_REVISION 0xff | ||
776 | #define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) | ||
777 | |||
778 | /** | ||
779 | * Register: HW_DIGCTL_AHB_STATS_SELECT | ||
780 | * Address: 0x330 | ||
781 | * SCT: no | ||
782 | */ | ||
783 | #define HW_DIGCTL_AHB_STATS_SELECT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330)) | ||
784 | #define BP_DIGCTL_AHB_STATS_SELECT_RSVD3 28 | ||
785 | #define BM_DIGCTL_AHB_STATS_SELECT_RSVD3 0xf0000000 | ||
786 | #define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v) (((v) << 28) & 0xf0000000) | ||
787 | #define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 | ||
788 | #define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0xf000000 | ||
789 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 | ||
790 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 | ||
791 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 | ||
792 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) (((v) << 24) & 0xf000000) | ||
793 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000) | ||
794 | #define BP_DIGCTL_AHB_STATS_SELECT_RSVD2 20 | ||
795 | #define BM_DIGCTL_AHB_STATS_SELECT_RSVD2 0xf00000 | ||
796 | #define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v) (((v) << 20) & 0xf00000) | ||
797 | #define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 | ||
798 | #define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0xf0000 | ||
799 | #define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 | ||
800 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) (((v) << 16) & 0xf0000) | ||
801 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000) | ||
802 | #define BP_DIGCTL_AHB_STATS_SELECT_RSVD1 12 | ||
803 | #define BM_DIGCTL_AHB_STATS_SELECT_RSVD1 0xf000 | ||
804 | #define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v) (((v) << 12) & 0xf000) | ||
805 | #define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 | ||
806 | #define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0xf00 | ||
807 | #define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 | ||
808 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) (((v) << 8) & 0xf00) | ||
809 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00) | ||
810 | #define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 4 | ||
811 | #define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0xf0 | ||
812 | #define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) (((v) << 4) & 0xf0) | ||
813 | #define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 | ||
814 | #define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0xf | ||
815 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 | ||
816 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 | ||
817 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) (((v) << 0) & 0xf) | ||
818 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf) | ||
819 | |||
820 | /** | ||
821 | * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES | ||
822 | * Address: 0x340 | ||
823 | * SCT: no | ||
824 | */ | ||
825 | #define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340)) | ||
826 | #define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 | ||
827 | #define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
828 | #define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
829 | |||
830 | /** | ||
831 | * Register: HW_DIGCTL_L0_AHB_DATA_STALLED | ||
832 | * Address: 0x350 | ||
833 | * SCT: no | ||
834 | */ | ||
835 | #define HW_DIGCTL_L0_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350)) | ||
836 | #define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 | ||
837 | #define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xffffffff | ||
838 | #define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
839 | |||
840 | /** | ||
841 | * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES | ||
842 | * Address: 0x360 | ||
843 | * SCT: no | ||
844 | */ | ||
845 | #define HW_DIGCTL_L0_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360)) | ||
846 | #define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 | ||
847 | #define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
848 | #define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
849 | |||
850 | /** | ||
851 | * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES | ||
852 | * Address: 0x370 | ||
853 | * SCT: no | ||
854 | */ | ||
855 | #define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370)) | ||
856 | #define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 | ||
857 | #define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
858 | #define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
859 | |||
860 | /** | ||
861 | * Register: HW_DIGCTL_L1_AHB_DATA_STALLED | ||
862 | * Address: 0x380 | ||
863 | * SCT: no | ||
864 | */ | ||
865 | #define HW_DIGCTL_L1_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380)) | ||
866 | #define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 | ||
867 | #define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xffffffff | ||
868 | #define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
869 | |||
870 | /** | ||
871 | * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES | ||
872 | * Address: 0x390 | ||
873 | * SCT: no | ||
874 | */ | ||
875 | #define HW_DIGCTL_L1_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390)) | ||
876 | #define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 | ||
877 | #define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
878 | #define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
879 | |||
880 | /** | ||
881 | * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES | ||
882 | * Address: 0x3a0 | ||
883 | * SCT: no | ||
884 | */ | ||
885 | #define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0)) | ||
886 | #define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 | ||
887 | #define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
888 | #define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
889 | |||
890 | /** | ||
891 | * Register: HW_DIGCTL_L2_AHB_DATA_STALLED | ||
892 | * Address: 0x3b0 | ||
893 | * SCT: no | ||
894 | */ | ||
895 | #define HW_DIGCTL_L2_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0)) | ||
896 | #define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 | ||
897 | #define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xffffffff | ||
898 | #define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
899 | |||
900 | /** | ||
901 | * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES | ||
902 | * Address: 0x3c0 | ||
903 | * SCT: no | ||
904 | */ | ||
905 | #define HW_DIGCTL_L2_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0)) | ||
906 | #define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 | ||
907 | #define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
908 | #define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
909 | |||
910 | /** | ||
911 | * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES | ||
912 | * Address: 0x3d0 | ||
913 | * SCT: no | ||
914 | */ | ||
915 | #define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0)) | ||
916 | #define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 | ||
917 | #define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
918 | #define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
919 | |||
920 | /** | ||
921 | * Register: HW_DIGCTL_L3_AHB_DATA_STALLED | ||
922 | * Address: 0x3e0 | ||
923 | * SCT: no | ||
924 | */ | ||
925 | #define HW_DIGCTL_L3_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0)) | ||
926 | #define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 | ||
927 | #define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xffffffff | ||
928 | #define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
929 | |||
930 | /** | ||
931 | * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES | ||
932 | * Address: 0x3f0 | ||
933 | * SCT: no | ||
934 | */ | ||
935 | #define HW_DIGCTL_L3_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0)) | ||
936 | #define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 | ||
937 | #define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
938 | #define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
939 | |||
940 | /** | ||
941 | * Register: HW_DIGCTL_MPTEn_LOC | ||
942 | * Address: 0x400+n*0x10 | ||
943 | * SCT: no | ||
944 | */ | ||
945 | #define HW_DIGCTL_MPTEn_LOC(n) (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10)) | ||
946 | #define BP_DIGCTL_MPTEn_LOC_RSVD0 12 | ||
947 | #define BM_DIGCTL_MPTEn_LOC_RSVD0 0xfffff000 | ||
948 | #define BF_DIGCTL_MPTEn_LOC_RSVD0(v) (((v) << 12) & 0xfffff000) | ||
949 | #define BP_DIGCTL_MPTEn_LOC_LOC 0 | ||
950 | #define BM_DIGCTL_MPTEn_LOC_LOC 0xfff | ||
951 | #define BF_DIGCTL_MPTEn_LOC_LOC(v) (((v) << 0) & 0xfff) | ||
952 | |||
953 | /** | ||
954 | * Register: HW_DIGCTL_EMICLK_DELAY | ||
955 | * Address: 0x500 | ||
956 | * SCT: no | ||
957 | */ | ||
958 | #define HW_DIGCTL_EMICLK_DELAY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x500)) | ||
959 | #define BP_DIGCTL_EMICLK_DELAY_RSVD0 5 | ||
960 | #define BM_DIGCTL_EMICLK_DELAY_RSVD0 0xffffffe0 | ||
961 | #define BF_DIGCTL_EMICLK_DELAY_RSVD0(v) (((v) << 5) & 0xffffffe0) | ||
962 | #define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 | ||
963 | #define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x1f | ||
964 | #define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) (((v) << 0) & 0x1f) | ||
965 | |||
966 | #endif /* __HEADERGEN__IMX233__DIGCTL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dram.h b/firmware/target/arm/imx233/regs/imx233/regs-dram.h new file mode 100644 index 0000000000..144861d2fd --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-dram.h | |||
@@ -0,0 +1,980 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__DRAM__H__ | ||
24 | #define __HEADERGEN__IMX233__DRAM__H__ | ||
25 | |||
26 | #define REGS_DRAM_BASE (0x800e0000) | ||
27 | |||
28 | #define REGS_DRAM_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DRAM_CTL00 | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_DRAM_CTL00 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0)) | ||
36 | #define BP_DRAM_CTL00_RSVD4 25 | ||
37 | #define BM_DRAM_CTL00_RSVD4 0xfe000000 | ||
38 | #define BF_DRAM_CTL00_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
39 | #define BP_DRAM_CTL00_AHB0_W_PRIORITY 24 | ||
40 | #define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x1000000 | ||
41 | #define BF_DRAM_CTL00_AHB0_W_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
42 | #define BP_DRAM_CTL00_RSVD3 17 | ||
43 | #define BM_DRAM_CTL00_RSVD3 0xfe0000 | ||
44 | #define BF_DRAM_CTL00_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
45 | #define BP_DRAM_CTL00_AHB0_R_PRIORITY 16 | ||
46 | #define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x10000 | ||
47 | #define BF_DRAM_CTL00_AHB0_R_PRIORITY(v) (((v) << 16) & 0x10000) | ||
48 | #define BP_DRAM_CTL00_RSVD2 9 | ||
49 | #define BM_DRAM_CTL00_RSVD2 0xfe00 | ||
50 | #define BF_DRAM_CTL00_RSVD2(v) (((v) << 9) & 0xfe00) | ||
51 | #define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG 8 | ||
52 | #define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x100 | ||
53 | #define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100) | ||
54 | #define BP_DRAM_CTL00_RSVD1 1 | ||
55 | #define BM_DRAM_CTL00_RSVD1 0xfe | ||
56 | #define BF_DRAM_CTL00_RSVD1(v) (((v) << 1) & 0xfe) | ||
57 | #define BP_DRAM_CTL00_ADDR_CMP_EN 0 | ||
58 | #define BM_DRAM_CTL00_ADDR_CMP_EN 0x1 | ||
59 | #define BF_DRAM_CTL00_ADDR_CMP_EN(v) (((v) << 0) & 0x1) | ||
60 | |||
61 | /** | ||
62 | * Register: HW_DRAM_CTL01 | ||
63 | * Address: 0x4 | ||
64 | * SCT: no | ||
65 | */ | ||
66 | #define HW_DRAM_CTL01 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4)) | ||
67 | #define BP_DRAM_CTL01_RSVD4 25 | ||
68 | #define BM_DRAM_CTL01_RSVD4 0xfe000000 | ||
69 | #define BF_DRAM_CTL01_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
70 | #define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG 24 | ||
71 | #define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x1000000 | ||
72 | #define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000) | ||
73 | #define BP_DRAM_CTL01_RSVD3 17 | ||
74 | #define BM_DRAM_CTL01_RSVD3 0xfe0000 | ||
75 | #define BF_DRAM_CTL01_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
76 | #define BP_DRAM_CTL01_AHB1_W_PRIORITY 16 | ||
77 | #define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x10000 | ||
78 | #define BF_DRAM_CTL01_AHB1_W_PRIORITY(v) (((v) << 16) & 0x10000) | ||
79 | #define BP_DRAM_CTL01_RSVD2 9 | ||
80 | #define BM_DRAM_CTL01_RSVD2 0xfe00 | ||
81 | #define BF_DRAM_CTL01_RSVD2(v) (((v) << 9) & 0xfe00) | ||
82 | #define BP_DRAM_CTL01_AHB1_R_PRIORITY 8 | ||
83 | #define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x100 | ||
84 | #define BF_DRAM_CTL01_AHB1_R_PRIORITY(v) (((v) << 8) & 0x100) | ||
85 | #define BP_DRAM_CTL01_RSVD1 1 | ||
86 | #define BM_DRAM_CTL01_RSVD1 0xfe | ||
87 | #define BF_DRAM_CTL01_RSVD1(v) (((v) << 1) & 0xfe) | ||
88 | #define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0 | ||
89 | #define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x1 | ||
90 | #define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_DRAM_CTL02 | ||
94 | * Address: 0x8 | ||
95 | * SCT: no | ||
96 | */ | ||
97 | #define HW_DRAM_CTL02 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8)) | ||
98 | #define BP_DRAM_CTL02_RSVD4 25 | ||
99 | #define BM_DRAM_CTL02_RSVD4 0xfe000000 | ||
100 | #define BF_DRAM_CTL02_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
101 | #define BP_DRAM_CTL02_AHB3_R_PRIORITY 24 | ||
102 | #define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x1000000 | ||
103 | #define BF_DRAM_CTL02_AHB3_R_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
104 | #define BP_DRAM_CTL02_RSVD3 17 | ||
105 | #define BM_DRAM_CTL02_RSVD3 0xfe0000 | ||
106 | #define BF_DRAM_CTL02_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
107 | #define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG 16 | ||
108 | #define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x10000 | ||
109 | #define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000) | ||
110 | #define BP_DRAM_CTL02_RSVD2 9 | ||
111 | #define BM_DRAM_CTL02_RSVD2 0xfe00 | ||
112 | #define BF_DRAM_CTL02_RSVD2(v) (((v) << 9) & 0xfe00) | ||
113 | #define BP_DRAM_CTL02_AHB2_W_PRIORITY 8 | ||
114 | #define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x100 | ||
115 | #define BF_DRAM_CTL02_AHB2_W_PRIORITY(v) (((v) << 8) & 0x100) | ||
116 | #define BP_DRAM_CTL02_RSVD1 1 | ||
117 | #define BM_DRAM_CTL02_RSVD1 0xfe | ||
118 | #define BF_DRAM_CTL02_RSVD1(v) (((v) << 1) & 0xfe) | ||
119 | #define BP_DRAM_CTL02_AHB2_R_PRIORITY 0 | ||
120 | #define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x1 | ||
121 | #define BF_DRAM_CTL02_AHB2_R_PRIORITY(v) (((v) << 0) & 0x1) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_DRAM_CTL03 | ||
125 | * Address: 0xc | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_DRAM_CTL03 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc)) | ||
129 | #define BP_DRAM_CTL03_RSVD4 25 | ||
130 | #define BM_DRAM_CTL03_RSVD4 0xfe000000 | ||
131 | #define BF_DRAM_CTL03_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
132 | #define BP_DRAM_CTL03_AUTO_REFRESH_MODE 24 | ||
133 | #define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x1000000 | ||
134 | #define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v) (((v) << 24) & 0x1000000) | ||
135 | #define BP_DRAM_CTL03_RSVD3 17 | ||
136 | #define BM_DRAM_CTL03_RSVD3 0xfe0000 | ||
137 | #define BF_DRAM_CTL03_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
138 | #define BP_DRAM_CTL03_AREFRESH 16 | ||
139 | #define BM_DRAM_CTL03_AREFRESH 0x10000 | ||
140 | #define BF_DRAM_CTL03_AREFRESH(v) (((v) << 16) & 0x10000) | ||
141 | #define BP_DRAM_CTL03_RSVD2 9 | ||
142 | #define BM_DRAM_CTL03_RSVD2 0xfe00 | ||
143 | #define BF_DRAM_CTL03_RSVD2(v) (((v) << 9) & 0xfe00) | ||
144 | #define BP_DRAM_CTL03_AP 8 | ||
145 | #define BM_DRAM_CTL03_AP 0x100 | ||
146 | #define BF_DRAM_CTL03_AP(v) (((v) << 8) & 0x100) | ||
147 | #define BP_DRAM_CTL03_RSVD1 1 | ||
148 | #define BM_DRAM_CTL03_RSVD1 0xfe | ||
149 | #define BF_DRAM_CTL03_RSVD1(v) (((v) << 1) & 0xfe) | ||
150 | #define BP_DRAM_CTL03_AHB3_W_PRIORITY 0 | ||
151 | #define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x1 | ||
152 | #define BF_DRAM_CTL03_AHB3_W_PRIORITY(v) (((v) << 0) & 0x1) | ||
153 | |||
154 | /** | ||
155 | * Register: HW_DRAM_CTL04 | ||
156 | * Address: 0x10 | ||
157 | * SCT: no | ||
158 | */ | ||
159 | #define HW_DRAM_CTL04 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10)) | ||
160 | #define BP_DRAM_CTL04_RSVD4 25 | ||
161 | #define BM_DRAM_CTL04_RSVD4 0xfe000000 | ||
162 | #define BF_DRAM_CTL04_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
163 | #define BP_DRAM_CTL04_DLL_BYPASS_MODE 24 | ||
164 | #define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x1000000 | ||
165 | #define BF_DRAM_CTL04_DLL_BYPASS_MODE(v) (((v) << 24) & 0x1000000) | ||
166 | #define BP_DRAM_CTL04_RSVD3 17 | ||
167 | #define BM_DRAM_CTL04_RSVD3 0xfe0000 | ||
168 | #define BF_DRAM_CTL04_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
169 | #define BP_DRAM_CTL04_DLLLOCKREG 16 | ||
170 | #define BM_DRAM_CTL04_DLLLOCKREG 0x10000 | ||
171 | #define BF_DRAM_CTL04_DLLLOCKREG(v) (((v) << 16) & 0x10000) | ||
172 | #define BP_DRAM_CTL04_RSVD2 9 | ||
173 | #define BM_DRAM_CTL04_RSVD2 0xfe00 | ||
174 | #define BF_DRAM_CTL04_RSVD2(v) (((v) << 9) & 0xfe00) | ||
175 | #define BP_DRAM_CTL04_CONCURRENTAP 8 | ||
176 | #define BM_DRAM_CTL04_CONCURRENTAP 0x100 | ||
177 | #define BF_DRAM_CTL04_CONCURRENTAP(v) (((v) << 8) & 0x100) | ||
178 | #define BP_DRAM_CTL04_RSVD1 1 | ||
179 | #define BM_DRAM_CTL04_RSVD1 0xfe | ||
180 | #define BF_DRAM_CTL04_RSVD1(v) (((v) << 1) & 0xfe) | ||
181 | #define BP_DRAM_CTL04_BANK_SPLIT_EN 0 | ||
182 | #define BM_DRAM_CTL04_BANK_SPLIT_EN 0x1 | ||
183 | #define BF_DRAM_CTL04_BANK_SPLIT_EN(v) (((v) << 0) & 0x1) | ||
184 | |||
185 | /** | ||
186 | * Register: HW_DRAM_CTL05 | ||
187 | * Address: 0x14 | ||
188 | * SCT: no | ||
189 | */ | ||
190 | #define HW_DRAM_CTL05 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14)) | ||
191 | #define BP_DRAM_CTL05_RSVD4 25 | ||
192 | #define BM_DRAM_CTL05_RSVD4 0xfe000000 | ||
193 | #define BF_DRAM_CTL05_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
194 | #define BP_DRAM_CTL05_INTRPTREADA 24 | ||
195 | #define BM_DRAM_CTL05_INTRPTREADA 0x1000000 | ||
196 | #define BF_DRAM_CTL05_INTRPTREADA(v) (((v) << 24) & 0x1000000) | ||
197 | #define BP_DRAM_CTL05_RSVD3 17 | ||
198 | #define BM_DRAM_CTL05_RSVD3 0xfe0000 | ||
199 | #define BF_DRAM_CTL05_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
200 | #define BP_DRAM_CTL05_INTRPTAPBURST 16 | ||
201 | #define BM_DRAM_CTL05_INTRPTAPBURST 0x10000 | ||
202 | #define BF_DRAM_CTL05_INTRPTAPBURST(v) (((v) << 16) & 0x10000) | ||
203 | #define BP_DRAM_CTL05_RSVD2 9 | ||
204 | #define BM_DRAM_CTL05_RSVD2 0xfe00 | ||
205 | #define BF_DRAM_CTL05_RSVD2(v) (((v) << 9) & 0xfe00) | ||
206 | #define BP_DRAM_CTL05_FAST_WRITE 8 | ||
207 | #define BM_DRAM_CTL05_FAST_WRITE 0x100 | ||
208 | #define BF_DRAM_CTL05_FAST_WRITE(v) (((v) << 8) & 0x100) | ||
209 | #define BP_DRAM_CTL05_RSVD1 1 | ||
210 | #define BM_DRAM_CTL05_RSVD1 0xfe | ||
211 | #define BF_DRAM_CTL05_RSVD1(v) (((v) << 1) & 0xfe) | ||
212 | #define BP_DRAM_CTL05_EN_LOWPOWER_MODE 0 | ||
213 | #define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x1 | ||
214 | #define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v) (((v) << 0) & 0x1) | ||
215 | |||
216 | /** | ||
217 | * Register: HW_DRAM_CTL06 | ||
218 | * Address: 0x18 | ||
219 | * SCT: no | ||
220 | */ | ||
221 | #define HW_DRAM_CTL06 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18)) | ||
222 | #define BP_DRAM_CTL06_RSVD4 25 | ||
223 | #define BM_DRAM_CTL06_RSVD4 0xfe000000 | ||
224 | #define BF_DRAM_CTL06_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
225 | #define BP_DRAM_CTL06_POWER_DOWN 24 | ||
226 | #define BM_DRAM_CTL06_POWER_DOWN 0x1000000 | ||
227 | #define BF_DRAM_CTL06_POWER_DOWN(v) (((v) << 24) & 0x1000000) | ||
228 | #define BP_DRAM_CTL06_RSVD3 17 | ||
229 | #define BM_DRAM_CTL06_RSVD3 0xfe0000 | ||
230 | #define BF_DRAM_CTL06_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
231 | #define BP_DRAM_CTL06_PLACEMENT_EN 16 | ||
232 | #define BM_DRAM_CTL06_PLACEMENT_EN 0x10000 | ||
233 | #define BF_DRAM_CTL06_PLACEMENT_EN(v) (((v) << 16) & 0x10000) | ||
234 | #define BP_DRAM_CTL06_RSVD2 9 | ||
235 | #define BM_DRAM_CTL06_RSVD2 0xfe00 | ||
236 | #define BF_DRAM_CTL06_RSVD2(v) (((v) << 9) & 0xfe00) | ||
237 | #define BP_DRAM_CTL06_NO_CMD_INIT 8 | ||
238 | #define BM_DRAM_CTL06_NO_CMD_INIT 0x100 | ||
239 | #define BF_DRAM_CTL06_NO_CMD_INIT(v) (((v) << 8) & 0x100) | ||
240 | #define BP_DRAM_CTL06_RSVD1 1 | ||
241 | #define BM_DRAM_CTL06_RSVD1 0xfe | ||
242 | #define BF_DRAM_CTL06_RSVD1(v) (((v) << 1) & 0xfe) | ||
243 | #define BP_DRAM_CTL06_INTRPTWRITEA 0 | ||
244 | #define BM_DRAM_CTL06_INTRPTWRITEA 0x1 | ||
245 | #define BF_DRAM_CTL06_INTRPTWRITEA(v) (((v) << 0) & 0x1) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_DRAM_CTL07 | ||
249 | * Address: 0x1c | ||
250 | * SCT: no | ||
251 | */ | ||
252 | #define HW_DRAM_CTL07 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c)) | ||
253 | #define BP_DRAM_CTL07_RSVD4 25 | ||
254 | #define BM_DRAM_CTL07_RSVD4 0xfe000000 | ||
255 | #define BF_DRAM_CTL07_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
256 | #define BP_DRAM_CTL07_RW_SAME_EN 24 | ||
257 | #define BM_DRAM_CTL07_RW_SAME_EN 0x1000000 | ||
258 | #define BF_DRAM_CTL07_RW_SAME_EN(v) (((v) << 24) & 0x1000000) | ||
259 | #define BP_DRAM_CTL07_RSVD3 17 | ||
260 | #define BM_DRAM_CTL07_RSVD3 0xfe0000 | ||
261 | #define BF_DRAM_CTL07_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
262 | #define BP_DRAM_CTL07_REG_DIMM_ENABLE 16 | ||
263 | #define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x10000 | ||
264 | #define BF_DRAM_CTL07_REG_DIMM_ENABLE(v) (((v) << 16) & 0x10000) | ||
265 | #define BP_DRAM_CTL07_RSVD2 9 | ||
266 | #define BM_DRAM_CTL07_RSVD2 0xfe00 | ||
267 | #define BF_DRAM_CTL07_RSVD2(v) (((v) << 9) & 0xfe00) | ||
268 | #define BP_DRAM_CTL07_RD2RD_TURN 8 | ||
269 | #define BM_DRAM_CTL07_RD2RD_TURN 0x100 | ||
270 | #define BF_DRAM_CTL07_RD2RD_TURN(v) (((v) << 8) & 0x100) | ||
271 | #define BP_DRAM_CTL07_RSVD1 1 | ||
272 | #define BM_DRAM_CTL07_RSVD1 0xfe | ||
273 | #define BF_DRAM_CTL07_RSVD1(v) (((v) << 1) & 0xfe) | ||
274 | #define BP_DRAM_CTL07_PRIORITY_EN 0 | ||
275 | #define BM_DRAM_CTL07_PRIORITY_EN 0x1 | ||
276 | #define BF_DRAM_CTL07_PRIORITY_EN(v) (((v) << 0) & 0x1) | ||
277 | |||
278 | /** | ||
279 | * Register: HW_DRAM_CTL08 | ||
280 | * Address: 0x20 | ||
281 | * SCT: no | ||
282 | */ | ||
283 | #define HW_DRAM_CTL08 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20)) | ||
284 | #define BP_DRAM_CTL08_RSVD4 25 | ||
285 | #define BM_DRAM_CTL08_RSVD4 0xfe000000 | ||
286 | #define BF_DRAM_CTL08_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
287 | #define BP_DRAM_CTL08_TRAS_LOCKOUT 24 | ||
288 | #define BM_DRAM_CTL08_TRAS_LOCKOUT 0x1000000 | ||
289 | #define BF_DRAM_CTL08_TRAS_LOCKOUT(v) (((v) << 24) & 0x1000000) | ||
290 | #define BP_DRAM_CTL08_RSVD3 17 | ||
291 | #define BM_DRAM_CTL08_RSVD3 0xfe0000 | ||
292 | #define BF_DRAM_CTL08_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
293 | #define BP_DRAM_CTL08_START 16 | ||
294 | #define BM_DRAM_CTL08_START 0x10000 | ||
295 | #define BF_DRAM_CTL08_START(v) (((v) << 16) & 0x10000) | ||
296 | #define BP_DRAM_CTL08_RSVD2 9 | ||
297 | #define BM_DRAM_CTL08_RSVD2 0xfe00 | ||
298 | #define BF_DRAM_CTL08_RSVD2(v) (((v) << 9) & 0xfe00) | ||
299 | #define BP_DRAM_CTL08_SREFRESH 8 | ||
300 | #define BM_DRAM_CTL08_SREFRESH 0x100 | ||
301 | #define BF_DRAM_CTL08_SREFRESH(v) (((v) << 8) & 0x100) | ||
302 | #define BP_DRAM_CTL08_RSVD1 1 | ||
303 | #define BM_DRAM_CTL08_RSVD1 0xfe | ||
304 | #define BF_DRAM_CTL08_RSVD1(v) (((v) << 1) & 0xfe) | ||
305 | #define BP_DRAM_CTL08_SDR_MODE 0 | ||
306 | #define BM_DRAM_CTL08_SDR_MODE 0x1 | ||
307 | #define BF_DRAM_CTL08_SDR_MODE(v) (((v) << 0) & 0x1) | ||
308 | |||
309 | /** | ||
310 | * Register: HW_DRAM_CTL09 | ||
311 | * Address: 0x24 | ||
312 | * SCT: no | ||
313 | */ | ||
314 | #define HW_DRAM_CTL09 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24)) | ||
315 | #define BP_DRAM_CTL09_RSVD4 26 | ||
316 | #define BM_DRAM_CTL09_RSVD4 0xfc000000 | ||
317 | #define BF_DRAM_CTL09_RSVD4(v) (((v) << 26) & 0xfc000000) | ||
318 | #define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24 | ||
319 | #define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x3000000 | ||
320 | #define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) (((v) << 24) & 0x3000000) | ||
321 | #define BP_DRAM_CTL09_RSVD3 18 | ||
322 | #define BM_DRAM_CTL09_RSVD3 0xfc0000 | ||
323 | #define BF_DRAM_CTL09_RSVD3(v) (((v) << 18) & 0xfc0000) | ||
324 | #define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16 | ||
325 | #define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x30000 | ||
326 | #define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000) | ||
327 | #define BP_DRAM_CTL09_RSVD2 9 | ||
328 | #define BM_DRAM_CTL09_RSVD2 0xfe00 | ||
329 | #define BF_DRAM_CTL09_RSVD2(v) (((v) << 9) & 0xfe00) | ||
330 | #define BP_DRAM_CTL09_WRITE_MODEREG 8 | ||
331 | #define BM_DRAM_CTL09_WRITE_MODEREG 0x100 | ||
332 | #define BF_DRAM_CTL09_WRITE_MODEREG(v) (((v) << 8) & 0x100) | ||
333 | #define BP_DRAM_CTL09_RSVD1 1 | ||
334 | #define BM_DRAM_CTL09_RSVD1 0xfe | ||
335 | #define BF_DRAM_CTL09_RSVD1(v) (((v) << 1) & 0xfe) | ||
336 | #define BP_DRAM_CTL09_WRITEINTERP 0 | ||
337 | #define BM_DRAM_CTL09_WRITEINTERP 0x1 | ||
338 | #define BF_DRAM_CTL09_WRITEINTERP(v) (((v) << 0) & 0x1) | ||
339 | |||
340 | /** | ||
341 | * Register: HW_DRAM_CTL10 | ||
342 | * Address: 0x28 | ||
343 | * SCT: no | ||
344 | */ | ||
345 | #define HW_DRAM_CTL10 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28)) | ||
346 | #define BP_DRAM_CTL10_RSVD4 27 | ||
347 | #define BM_DRAM_CTL10_RSVD4 0xf8000000 | ||
348 | #define BF_DRAM_CTL10_RSVD4(v) (((v) << 27) & 0xf8000000) | ||
349 | #define BP_DRAM_CTL10_AGE_COUNT 24 | ||
350 | #define BM_DRAM_CTL10_AGE_COUNT 0x7000000 | ||
351 | #define BF_DRAM_CTL10_AGE_COUNT(v) (((v) << 24) & 0x7000000) | ||
352 | #define BP_DRAM_CTL10_RSVD3 19 | ||
353 | #define BM_DRAM_CTL10_RSVD3 0xf80000 | ||
354 | #define BF_DRAM_CTL10_RSVD3(v) (((v) << 19) & 0xf80000) | ||
355 | #define BP_DRAM_CTL10_ADDR_PINS 16 | ||
356 | #define BM_DRAM_CTL10_ADDR_PINS 0x70000 | ||
357 | #define BF_DRAM_CTL10_ADDR_PINS(v) (((v) << 16) & 0x70000) | ||
358 | #define BP_DRAM_CTL10_RSVD2 10 | ||
359 | #define BM_DRAM_CTL10_RSVD2 0xfc00 | ||
360 | #define BF_DRAM_CTL10_RSVD2(v) (((v) << 10) & 0xfc00) | ||
361 | #define BP_DRAM_CTL10_TEMRS 8 | ||
362 | #define BM_DRAM_CTL10_TEMRS 0x300 | ||
363 | #define BF_DRAM_CTL10_TEMRS(v) (((v) << 8) & 0x300) | ||
364 | #define BP_DRAM_CTL10_RSVD1 2 | ||
365 | #define BM_DRAM_CTL10_RSVD1 0xfc | ||
366 | #define BF_DRAM_CTL10_RSVD1(v) (((v) << 2) & 0xfc) | ||
367 | #define BP_DRAM_CTL10_Q_FULLNESS 0 | ||
368 | #define BM_DRAM_CTL10_Q_FULLNESS 0x3 | ||
369 | #define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3) | ||
370 | |||
371 | /** | ||
372 | * Register: HW_DRAM_CTL11 | ||
373 | * Address: 0x2c | ||
374 | * SCT: no | ||
375 | */ | ||
376 | #define HW_DRAM_CTL11 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c)) | ||
377 | #define BP_DRAM_CTL11_RSVD4 27 | ||
378 | #define BM_DRAM_CTL11_RSVD4 0xf8000000 | ||
379 | #define BF_DRAM_CTL11_RSVD4(v) (((v) << 27) & 0xf8000000) | ||
380 | #define BP_DRAM_CTL11_MAX_CS_REG 24 | ||
381 | #define BM_DRAM_CTL11_MAX_CS_REG 0x7000000 | ||
382 | #define BF_DRAM_CTL11_MAX_CS_REG(v) (((v) << 24) & 0x7000000) | ||
383 | #define BP_DRAM_CTL11_RSVD3 19 | ||
384 | #define BM_DRAM_CTL11_RSVD3 0xf80000 | ||
385 | #define BF_DRAM_CTL11_RSVD3(v) (((v) << 19) & 0xf80000) | ||
386 | #define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16 | ||
387 | #define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x70000 | ||
388 | #define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) (((v) << 16) & 0x70000) | ||
389 | #define BP_DRAM_CTL11_RSVD2 11 | ||
390 | #define BM_DRAM_CTL11_RSVD2 0xf800 | ||
391 | #define BF_DRAM_CTL11_RSVD2(v) (((v) << 11) & 0xf800) | ||
392 | #define BP_DRAM_CTL11_COLUMN_SIZE 8 | ||
393 | #define BM_DRAM_CTL11_COLUMN_SIZE 0x700 | ||
394 | #define BF_DRAM_CTL11_COLUMN_SIZE(v) (((v) << 8) & 0x700) | ||
395 | #define BP_DRAM_CTL11_RSVD1 3 | ||
396 | #define BM_DRAM_CTL11_RSVD1 0xf8 | ||
397 | #define BF_DRAM_CTL11_RSVD1(v) (((v) << 3) & 0xf8) | ||
398 | #define BP_DRAM_CTL11_CASLAT 0 | ||
399 | #define BM_DRAM_CTL11_CASLAT 0x7 | ||
400 | #define BF_DRAM_CTL11_CASLAT(v) (((v) << 0) & 0x7) | ||
401 | |||
402 | /** | ||
403 | * Register: HW_DRAM_CTL12 | ||
404 | * Address: 0x30 | ||
405 | * SCT: no | ||
406 | */ | ||
407 | #define HW_DRAM_CTL12 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30)) | ||
408 | #define BP_DRAM_CTL12_RSVD3 27 | ||
409 | #define BM_DRAM_CTL12_RSVD3 0xf8000000 | ||
410 | #define BF_DRAM_CTL12_RSVD3(v) (((v) << 27) & 0xf8000000) | ||
411 | #define BP_DRAM_CTL12_TWR_INT 24 | ||
412 | #define BM_DRAM_CTL12_TWR_INT 0x7000000 | ||
413 | #define BF_DRAM_CTL12_TWR_INT(v) (((v) << 24) & 0x7000000) | ||
414 | #define BP_DRAM_CTL12_RSVD2 19 | ||
415 | #define BM_DRAM_CTL12_RSVD2 0xf80000 | ||
416 | #define BF_DRAM_CTL12_RSVD2(v) (((v) << 19) & 0xf80000) | ||
417 | #define BP_DRAM_CTL12_TRRD 16 | ||
418 | #define BM_DRAM_CTL12_TRRD 0x70000 | ||
419 | #define BF_DRAM_CTL12_TRRD(v) (((v) << 16) & 0x70000) | ||
420 | #define BP_DRAM_CTL12_OBSOLETE 8 | ||
421 | #define BM_DRAM_CTL12_OBSOLETE 0xff00 | ||
422 | #define BF_DRAM_CTL12_OBSOLETE(v) (((v) << 8) & 0xff00) | ||
423 | #define BP_DRAM_CTL12_RSVD1 3 | ||
424 | #define BM_DRAM_CTL12_RSVD1 0xf8 | ||
425 | #define BF_DRAM_CTL12_RSVD1(v) (((v) << 3) & 0xf8) | ||
426 | #define BP_DRAM_CTL12_TCKE 0 | ||
427 | #define BM_DRAM_CTL12_TCKE 0x7 | ||
428 | #define BF_DRAM_CTL12_TCKE(v) (((v) << 0) & 0x7) | ||
429 | |||
430 | /** | ||
431 | * Register: HW_DRAM_CTL13 | ||
432 | * Address: 0x34 | ||
433 | * SCT: no | ||
434 | */ | ||
435 | #define HW_DRAM_CTL13 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34)) | ||
436 | #define BP_DRAM_CTL13_RSVD4 28 | ||
437 | #define BM_DRAM_CTL13_RSVD4 0xf0000000 | ||
438 | #define BF_DRAM_CTL13_RSVD4(v) (((v) << 28) & 0xf0000000) | ||
439 | #define BP_DRAM_CTL13_CASLAT_LIN_GATE 24 | ||
440 | #define BM_DRAM_CTL13_CASLAT_LIN_GATE 0xf000000 | ||
441 | #define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) (((v) << 24) & 0xf000000) | ||
442 | #define BP_DRAM_CTL13_RSVD3 20 | ||
443 | #define BM_DRAM_CTL13_RSVD3 0xf00000 | ||
444 | #define BF_DRAM_CTL13_RSVD3(v) (((v) << 20) & 0xf00000) | ||
445 | #define BP_DRAM_CTL13_CASLAT_LIN 16 | ||
446 | #define BM_DRAM_CTL13_CASLAT_LIN 0xf0000 | ||
447 | #define BF_DRAM_CTL13_CASLAT_LIN(v) (((v) << 16) & 0xf0000) | ||
448 | #define BP_DRAM_CTL13_RSVD2 12 | ||
449 | #define BM_DRAM_CTL13_RSVD2 0xf000 | ||
450 | #define BF_DRAM_CTL13_RSVD2(v) (((v) << 12) & 0xf000) | ||
451 | #define BP_DRAM_CTL13_APREBIT 8 | ||
452 | #define BM_DRAM_CTL13_APREBIT 0xf00 | ||
453 | #define BF_DRAM_CTL13_APREBIT(v) (((v) << 8) & 0xf00) | ||
454 | #define BP_DRAM_CTL13_RSVD1 3 | ||
455 | #define BM_DRAM_CTL13_RSVD1 0xf8 | ||
456 | #define BF_DRAM_CTL13_RSVD1(v) (((v) << 3) & 0xf8) | ||
457 | #define BP_DRAM_CTL13_TWTR 0 | ||
458 | #define BM_DRAM_CTL13_TWTR 0x7 | ||
459 | #define BF_DRAM_CTL13_TWTR(v) (((v) << 0) & 0x7) | ||
460 | |||
461 | /** | ||
462 | * Register: HW_DRAM_CTL14 | ||
463 | * Address: 0x38 | ||
464 | * SCT: no | ||
465 | */ | ||
466 | #define HW_DRAM_CTL14 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38)) | ||
467 | #define BP_DRAM_CTL14_RSVD4 28 | ||
468 | #define BM_DRAM_CTL14_RSVD4 0xf0000000 | ||
469 | #define BF_DRAM_CTL14_RSVD4(v) (((v) << 28) & 0xf0000000) | ||
470 | #define BP_DRAM_CTL14_MAX_COL_REG 24 | ||
471 | #define BM_DRAM_CTL14_MAX_COL_REG 0xf000000 | ||
472 | #define BF_DRAM_CTL14_MAX_COL_REG(v) (((v) << 24) & 0xf000000) | ||
473 | #define BP_DRAM_CTL14_RSVD3 20 | ||
474 | #define BM_DRAM_CTL14_RSVD3 0xf00000 | ||
475 | #define BF_DRAM_CTL14_RSVD3(v) (((v) << 20) & 0xf00000) | ||
476 | #define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16 | ||
477 | #define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0xf0000 | ||
478 | #define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) (((v) << 16) & 0xf0000) | ||
479 | #define BP_DRAM_CTL14_RSVD2 12 | ||
480 | #define BM_DRAM_CTL14_RSVD2 0xf000 | ||
481 | #define BF_DRAM_CTL14_RSVD2(v) (((v) << 12) & 0xf000) | ||
482 | #define BP_DRAM_CTL14_INITAREF 8 | ||
483 | #define BM_DRAM_CTL14_INITAREF 0xf00 | ||
484 | #define BF_DRAM_CTL14_INITAREF(v) (((v) << 8) & 0xf00) | ||
485 | #define BP_DRAM_CTL14_RSVD1 4 | ||
486 | #define BM_DRAM_CTL14_RSVD1 0xf0 | ||
487 | #define BF_DRAM_CTL14_RSVD1(v) (((v) << 4) & 0xf0) | ||
488 | #define BP_DRAM_CTL14_CS_MAP 0 | ||
489 | #define BM_DRAM_CTL14_CS_MAP 0xf | ||
490 | #define BF_DRAM_CTL14_CS_MAP(v) (((v) << 0) & 0xf) | ||
491 | |||
492 | /** | ||
493 | * Register: HW_DRAM_CTL15 | ||
494 | * Address: 0x3c | ||
495 | * SCT: no | ||
496 | */ | ||
497 | #define HW_DRAM_CTL15 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c)) | ||
498 | #define BP_DRAM_CTL15_RSVD4 28 | ||
499 | #define BM_DRAM_CTL15_RSVD4 0xf0000000 | ||
500 | #define BF_DRAM_CTL15_RSVD4(v) (((v) << 28) & 0xf0000000) | ||
501 | #define BP_DRAM_CTL15_TRP 24 | ||
502 | #define BM_DRAM_CTL15_TRP 0xf000000 | ||
503 | #define BF_DRAM_CTL15_TRP(v) (((v) << 24) & 0xf000000) | ||
504 | #define BP_DRAM_CTL15_RSVD3 20 | ||
505 | #define BM_DRAM_CTL15_RSVD3 0xf00000 | ||
506 | #define BF_DRAM_CTL15_RSVD3(v) (((v) << 20) & 0xf00000) | ||
507 | #define BP_DRAM_CTL15_TDAL 16 | ||
508 | #define BM_DRAM_CTL15_TDAL 0xf0000 | ||
509 | #define BF_DRAM_CTL15_TDAL(v) (((v) << 16) & 0xf0000) | ||
510 | #define BP_DRAM_CTL15_RSVD2 12 | ||
511 | #define BM_DRAM_CTL15_RSVD2 0xf000 | ||
512 | #define BF_DRAM_CTL15_RSVD2(v) (((v) << 12) & 0xf000) | ||
513 | #define BP_DRAM_CTL15_PORT_BUSY 8 | ||
514 | #define BM_DRAM_CTL15_PORT_BUSY 0xf00 | ||
515 | #define BF_DRAM_CTL15_PORT_BUSY(v) (((v) << 8) & 0xf00) | ||
516 | #define BP_DRAM_CTL15_RSVD1 4 | ||
517 | #define BM_DRAM_CTL15_RSVD1 0xf0 | ||
518 | #define BF_DRAM_CTL15_RSVD1(v) (((v) << 4) & 0xf0) | ||
519 | #define BP_DRAM_CTL15_MAX_ROW_REG 0 | ||
520 | #define BM_DRAM_CTL15_MAX_ROW_REG 0xf | ||
521 | #define BF_DRAM_CTL15_MAX_ROW_REG(v) (((v) << 0) & 0xf) | ||
522 | |||
523 | /** | ||
524 | * Register: HW_DRAM_CTL16 | ||
525 | * Address: 0x40 | ||
526 | * SCT: no | ||
527 | */ | ||
528 | #define HW_DRAM_CTL16 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40)) | ||
529 | #define BP_DRAM_CTL16_RSVD4 29 | ||
530 | #define BM_DRAM_CTL16_RSVD4 0xe0000000 | ||
531 | #define BF_DRAM_CTL16_RSVD4(v) (((v) << 29) & 0xe0000000) | ||
532 | #define BP_DRAM_CTL16_TMRD 24 | ||
533 | #define BM_DRAM_CTL16_TMRD 0x1f000000 | ||
534 | #define BF_DRAM_CTL16_TMRD(v) (((v) << 24) & 0x1f000000) | ||
535 | #define BP_DRAM_CTL16_RSVD3 21 | ||
536 | #define BM_DRAM_CTL16_RSVD3 0xe00000 | ||
537 | #define BF_DRAM_CTL16_RSVD3(v) (((v) << 21) & 0xe00000) | ||
538 | #define BP_DRAM_CTL16_LOWPOWER_CONTROL 16 | ||
539 | #define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x1f0000 | ||
540 | #define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) (((v) << 16) & 0x1f0000) | ||
541 | #define BP_DRAM_CTL16_RSVD2 13 | ||
542 | #define BM_DRAM_CTL16_RSVD2 0xe000 | ||
543 | #define BF_DRAM_CTL16_RSVD2(v) (((v) << 13) & 0xe000) | ||
544 | #define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8 | ||
545 | #define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x1f00 | ||
546 | #define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) (((v) << 8) & 0x1f00) | ||
547 | #define BP_DRAM_CTL16_RSVD1 4 | ||
548 | #define BM_DRAM_CTL16_RSVD1 0xf0 | ||
549 | #define BF_DRAM_CTL16_RSVD1(v) (((v) << 4) & 0xf0) | ||
550 | #define BP_DRAM_CTL16_INT_ACK 0 | ||
551 | #define BM_DRAM_CTL16_INT_ACK 0xf | ||
552 | #define BF_DRAM_CTL16_INT_ACK(v) (((v) << 0) & 0xf) | ||
553 | |||
554 | /** | ||
555 | * Register: HW_DRAM_CTL17 | ||
556 | * Address: 0x44 | ||
557 | * SCT: no | ||
558 | */ | ||
559 | #define HW_DRAM_CTL17 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44)) | ||
560 | #define BP_DRAM_CTL17_DLL_START_POINT 24 | ||
561 | #define BM_DRAM_CTL17_DLL_START_POINT 0xff000000 | ||
562 | #define BF_DRAM_CTL17_DLL_START_POINT(v) (((v) << 24) & 0xff000000) | ||
563 | #define BP_DRAM_CTL17_DLL_LOCK 16 | ||
564 | #define BM_DRAM_CTL17_DLL_LOCK 0xff0000 | ||
565 | #define BF_DRAM_CTL17_DLL_LOCK(v) (((v) << 16) & 0xff0000) | ||
566 | #define BP_DRAM_CTL17_DLL_INCREMENT 8 | ||
567 | #define BM_DRAM_CTL17_DLL_INCREMENT 0xff00 | ||
568 | #define BF_DRAM_CTL17_DLL_INCREMENT(v) (((v) << 8) & 0xff00) | ||
569 | #define BP_DRAM_CTL17_RSVD1 5 | ||
570 | #define BM_DRAM_CTL17_RSVD1 0xe0 | ||
571 | #define BF_DRAM_CTL17_RSVD1(v) (((v) << 5) & 0xe0) | ||
572 | #define BP_DRAM_CTL17_TRC 0 | ||
573 | #define BM_DRAM_CTL17_TRC 0x1f | ||
574 | #define BF_DRAM_CTL17_TRC(v) (((v) << 0) & 0x1f) | ||
575 | |||
576 | /** | ||
577 | * Register: HW_DRAM_CTL18 | ||
578 | * Address: 0x48 | ||
579 | * SCT: no | ||
580 | */ | ||
581 | #define HW_DRAM_CTL18 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48)) | ||
582 | #define BP_DRAM_CTL18_RSVD4 31 | ||
583 | #define BM_DRAM_CTL18_RSVD4 0x80000000 | ||
584 | #define BF_DRAM_CTL18_RSVD4(v) (((v) << 31) & 0x80000000) | ||
585 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24 | ||
586 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7f000000 | ||
587 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) (((v) << 24) & 0x7f000000) | ||
588 | #define BP_DRAM_CTL18_RSVD3 23 | ||
589 | #define BM_DRAM_CTL18_RSVD3 0x800000 | ||
590 | #define BF_DRAM_CTL18_RSVD3(v) (((v) << 23) & 0x800000) | ||
591 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16 | ||
592 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x7f0000 | ||
593 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) (((v) << 16) & 0x7f0000) | ||
594 | #define BP_DRAM_CTL18_RSVD2 13 | ||
595 | #define BM_DRAM_CTL18_RSVD2 0xe000 | ||
596 | #define BF_DRAM_CTL18_RSVD2(v) (((v) << 13) & 0xe000) | ||
597 | #define BP_DRAM_CTL18_INT_STATUS 8 | ||
598 | #define BM_DRAM_CTL18_INT_STATUS 0x1f00 | ||
599 | #define BF_DRAM_CTL18_INT_STATUS(v) (((v) << 8) & 0x1f00) | ||
600 | #define BP_DRAM_CTL18_RSVD1 5 | ||
601 | #define BM_DRAM_CTL18_RSVD1 0xe0 | ||
602 | #define BF_DRAM_CTL18_RSVD1(v) (((v) << 5) & 0xe0) | ||
603 | #define BP_DRAM_CTL18_INT_MASK 0 | ||
604 | #define BM_DRAM_CTL18_INT_MASK 0x1f | ||
605 | #define BF_DRAM_CTL18_INT_MASK(v) (((v) << 0) & 0x1f) | ||
606 | |||
607 | /** | ||
608 | * Register: HW_DRAM_CTL19 | ||
609 | * Address: 0x4c | ||
610 | * SCT: no | ||
611 | */ | ||
612 | #define HW_DRAM_CTL19 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c)) | ||
613 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24 | ||
614 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xff000000 | ||
615 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) (((v) << 24) & 0xff000000) | ||
616 | #define BP_DRAM_CTL19_RSVD1 23 | ||
617 | #define BM_DRAM_CTL19_RSVD1 0x800000 | ||
618 | #define BF_DRAM_CTL19_RSVD1(v) (((v) << 23) & 0x800000) | ||
619 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT 16 | ||
620 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x7f0000 | ||
621 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) (((v) << 16) & 0x7f0000) | ||
622 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8 | ||
623 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0xff00 | ||
624 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00) | ||
625 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0 | ||
626 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0xff | ||
627 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff) | ||
628 | |||
629 | /** | ||
630 | * Register: HW_DRAM_CTL20 | ||
631 | * Address: 0x50 | ||
632 | * SCT: no | ||
633 | */ | ||
634 | #define HW_DRAM_CTL20 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50)) | ||
635 | #define BP_DRAM_CTL20_TRCD_INT 24 | ||
636 | #define BM_DRAM_CTL20_TRCD_INT 0xff000000 | ||
637 | #define BF_DRAM_CTL20_TRCD_INT(v) (((v) << 24) & 0xff000000) | ||
638 | #define BP_DRAM_CTL20_TRAS_MIN 16 | ||
639 | #define BM_DRAM_CTL20_TRAS_MIN 0xff0000 | ||
640 | #define BF_DRAM_CTL20_TRAS_MIN(v) (((v) << 16) & 0xff0000) | ||
641 | #define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8 | ||
642 | #define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0xff00 | ||
643 | #define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) (((v) << 8) & 0xff00) | ||
644 | #define BP_DRAM_CTL20_RSVD1 7 | ||
645 | #define BM_DRAM_CTL20_RSVD1 0x80 | ||
646 | #define BF_DRAM_CTL20_RSVD1(v) (((v) << 7) & 0x80) | ||
647 | #define BP_DRAM_CTL20_WR_DQS_SHIFT 0 | ||
648 | #define BM_DRAM_CTL20_WR_DQS_SHIFT 0x7f | ||
649 | #define BF_DRAM_CTL20_WR_DQS_SHIFT(v) (((v) << 0) & 0x7f) | ||
650 | |||
651 | /** | ||
652 | * Register: HW_DRAM_CTL21 | ||
653 | * Address: 0x54 | ||
654 | * SCT: no | ||
655 | */ | ||
656 | #define HW_DRAM_CTL21 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54)) | ||
657 | #define BP_DRAM_CTL21_OBSOLETE 24 | ||
658 | #define BM_DRAM_CTL21_OBSOLETE 0xff000000 | ||
659 | #define BF_DRAM_CTL21_OBSOLETE(v) (((v) << 24) & 0xff000000) | ||
660 | #define BP_DRAM_CTL21_RSVD1 18 | ||
661 | #define BM_DRAM_CTL21_RSVD1 0xfc0000 | ||
662 | #define BF_DRAM_CTL21_RSVD1(v) (((v) << 18) & 0xfc0000) | ||
663 | #define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8 | ||
664 | #define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x3ff00 | ||
665 | #define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) (((v) << 8) & 0x3ff00) | ||
666 | #define BP_DRAM_CTL21_TRFC 0 | ||
667 | #define BM_DRAM_CTL21_TRFC 0xff | ||
668 | #define BF_DRAM_CTL21_TRFC(v) (((v) << 0) & 0xff) | ||
669 | |||
670 | /** | ||
671 | * Register: HW_DRAM_CTL22 | ||
672 | * Address: 0x58 | ||
673 | * SCT: no | ||
674 | */ | ||
675 | #define HW_DRAM_CTL22 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58)) | ||
676 | #define BP_DRAM_CTL22_RSVD2 27 | ||
677 | #define BM_DRAM_CTL22_RSVD2 0xf8000000 | ||
678 | #define BF_DRAM_CTL22_RSVD2(v) (((v) << 27) & 0xf8000000) | ||
679 | #define BP_DRAM_CTL22_AHB0_WRCNT 16 | ||
680 | #define BM_DRAM_CTL22_AHB0_WRCNT 0x7ff0000 | ||
681 | #define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
682 | #define BP_DRAM_CTL22_RSVD1 11 | ||
683 | #define BM_DRAM_CTL22_RSVD1 0xf800 | ||
684 | #define BF_DRAM_CTL22_RSVD1(v) (((v) << 11) & 0xf800) | ||
685 | #define BP_DRAM_CTL22_AHB0_RDCNT 0 | ||
686 | #define BM_DRAM_CTL22_AHB0_RDCNT 0x7ff | ||
687 | #define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff) | ||
688 | |||
689 | /** | ||
690 | * Register: HW_DRAM_CTL23 | ||
691 | * Address: 0x5c | ||
692 | * SCT: no | ||
693 | */ | ||
694 | #define HW_DRAM_CTL23 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c)) | ||
695 | #define BP_DRAM_CTL23_RSVD2 27 | ||
696 | #define BM_DRAM_CTL23_RSVD2 0xf8000000 | ||
697 | #define BF_DRAM_CTL23_RSVD2(v) (((v) << 27) & 0xf8000000) | ||
698 | #define BP_DRAM_CTL23_AHB1_WRCNT 16 | ||
699 | #define BM_DRAM_CTL23_AHB1_WRCNT 0x7ff0000 | ||
700 | #define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
701 | #define BP_DRAM_CTL23_RSVD1 11 | ||
702 | #define BM_DRAM_CTL23_RSVD1 0xf800 | ||
703 | #define BF_DRAM_CTL23_RSVD1(v) (((v) << 11) & 0xf800) | ||
704 | #define BP_DRAM_CTL23_AHB1_RDCNT 0 | ||
705 | #define BM_DRAM_CTL23_AHB1_RDCNT 0x7ff | ||
706 | #define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff) | ||
707 | |||
708 | /** | ||
709 | * Register: HW_DRAM_CTL24 | ||
710 | * Address: 0x60 | ||
711 | * SCT: no | ||
712 | */ | ||
713 | #define HW_DRAM_CTL24 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60)) | ||
714 | #define BP_DRAM_CTL24_RSVD2 27 | ||
715 | #define BM_DRAM_CTL24_RSVD2 0xf8000000 | ||
716 | #define BF_DRAM_CTL24_RSVD2(v) (((v) << 27) & 0xf8000000) | ||
717 | #define BP_DRAM_CTL24_AHB2_WRCNT 16 | ||
718 | #define BM_DRAM_CTL24_AHB2_WRCNT 0x7ff0000 | ||
719 | #define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
720 | #define BP_DRAM_CTL24_RSVD1 11 | ||
721 | #define BM_DRAM_CTL24_RSVD1 0xf800 | ||
722 | #define BF_DRAM_CTL24_RSVD1(v) (((v) << 11) & 0xf800) | ||
723 | #define BP_DRAM_CTL24_AHB2_RDCNT 0 | ||
724 | #define BM_DRAM_CTL24_AHB2_RDCNT 0x7ff | ||
725 | #define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff) | ||
726 | |||
727 | /** | ||
728 | * Register: HW_DRAM_CTL25 | ||
729 | * Address: 0x64 | ||
730 | * SCT: no | ||
731 | */ | ||
732 | #define HW_DRAM_CTL25 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64)) | ||
733 | #define BP_DRAM_CTL25_RSVD2 27 | ||
734 | #define BM_DRAM_CTL25_RSVD2 0xf8000000 | ||
735 | #define BF_DRAM_CTL25_RSVD2(v) (((v) << 27) & 0xf8000000) | ||
736 | #define BP_DRAM_CTL25_AHB3_WRCNT 16 | ||
737 | #define BM_DRAM_CTL25_AHB3_WRCNT 0x7ff0000 | ||
738 | #define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
739 | #define BP_DRAM_CTL25_RSVD1 11 | ||
740 | #define BM_DRAM_CTL25_RSVD1 0xf800 | ||
741 | #define BF_DRAM_CTL25_RSVD1(v) (((v) << 11) & 0xf800) | ||
742 | #define BP_DRAM_CTL25_AHB3_RDCNT 0 | ||
743 | #define BM_DRAM_CTL25_AHB3_RDCNT 0x7ff | ||
744 | #define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff) | ||
745 | |||
746 | /** | ||
747 | * Register: HW_DRAM_CTL26 | ||
748 | * Address: 0x68 | ||
749 | * SCT: no | ||
750 | */ | ||
751 | #define HW_DRAM_CTL26 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68)) | ||
752 | #define BP_DRAM_CTL26_OBSOLETE 16 | ||
753 | #define BM_DRAM_CTL26_OBSOLETE 0xffff0000 | ||
754 | #define BF_DRAM_CTL26_OBSOLETE(v) (((v) << 16) & 0xffff0000) | ||
755 | #define BP_DRAM_CTL26_RSVD1 12 | ||
756 | #define BM_DRAM_CTL26_RSVD1 0xf000 | ||
757 | #define BF_DRAM_CTL26_RSVD1(v) (((v) << 12) & 0xf000) | ||
758 | #define BP_DRAM_CTL26_TREF 0 | ||
759 | #define BM_DRAM_CTL26_TREF 0xfff | ||
760 | #define BF_DRAM_CTL26_TREF(v) (((v) << 0) & 0xfff) | ||
761 | |||
762 | /** | ||
763 | * Register: HW_DRAM_CTL27 | ||
764 | * Address: 0x6c | ||
765 | * SCT: no | ||
766 | */ | ||
767 | #define HW_DRAM_CTL27 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c)) | ||
768 | #define BP_DRAM_CTL27_OBSOLETE 0 | ||
769 | #define BM_DRAM_CTL27_OBSOLETE 0xffffffff | ||
770 | #define BF_DRAM_CTL27_OBSOLETE(v) (((v) << 0) & 0xffffffff) | ||
771 | |||
772 | /** | ||
773 | * Register: HW_DRAM_CTL28 | ||
774 | * Address: 0x70 | ||
775 | * SCT: no | ||
776 | */ | ||
777 | #define HW_DRAM_CTL28 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70)) | ||
778 | #define BP_DRAM_CTL28_OBSOLETE 0 | ||
779 | #define BM_DRAM_CTL28_OBSOLETE 0xffffffff | ||
780 | #define BF_DRAM_CTL28_OBSOLETE(v) (((v) << 0) & 0xffffffff) | ||
781 | |||
782 | /** | ||
783 | * Register: HW_DRAM_CTL29 | ||
784 | * Address: 0x74 | ||
785 | * SCT: no | ||
786 | */ | ||
787 | #define HW_DRAM_CTL29 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74)) | ||
788 | #define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 16 | ||
789 | #define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 0xffff0000 | ||
790 | #define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v) (((v) << 16) & 0xffff0000) | ||
791 | #define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0 | ||
792 | #define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0xffff | ||
793 | #define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v) (((v) << 0) & 0xffff) | ||
794 | |||
795 | /** | ||
796 | * Register: HW_DRAM_CTL30 | ||
797 | * Address: 0x78 | ||
798 | * SCT: no | ||
799 | */ | ||
800 | #define HW_DRAM_CTL30 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78)) | ||
801 | #define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 16 | ||
802 | #define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 0xffff0000 | ||
803 | #define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v) (((v) << 16) & 0xffff0000) | ||
804 | #define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0 | ||
805 | #define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0xffff | ||
806 | #define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v) (((v) << 0) & 0xffff) | ||
807 | |||
808 | /** | ||
809 | * Register: HW_DRAM_CTL31 | ||
810 | * Address: 0x7c | ||
811 | * SCT: no | ||
812 | */ | ||
813 | #define HW_DRAM_CTL31 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c)) | ||
814 | #define BP_DRAM_CTL31_TDLL 16 | ||
815 | #define BM_DRAM_CTL31_TDLL 0xffff0000 | ||
816 | #define BF_DRAM_CTL31_TDLL(v) (((v) << 16) & 0xffff0000) | ||
817 | #define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0 | ||
818 | #define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0xffff | ||
819 | #define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v) (((v) << 0) & 0xffff) | ||
820 | |||
821 | /** | ||
822 | * Register: HW_DRAM_CTL32 | ||
823 | * Address: 0x80 | ||
824 | * SCT: no | ||
825 | */ | ||
826 | #define HW_DRAM_CTL32 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80)) | ||
827 | #define BP_DRAM_CTL32_TXSNR 16 | ||
828 | #define BM_DRAM_CTL32_TXSNR 0xffff0000 | ||
829 | #define BF_DRAM_CTL32_TXSNR(v) (((v) << 16) & 0xffff0000) | ||
830 | #define BP_DRAM_CTL32_TRAS_MAX 0 | ||
831 | #define BM_DRAM_CTL32_TRAS_MAX 0xffff | ||
832 | #define BF_DRAM_CTL32_TRAS_MAX(v) (((v) << 0) & 0xffff) | ||
833 | |||
834 | /** | ||
835 | * Register: HW_DRAM_CTL33 | ||
836 | * Address: 0x84 | ||
837 | * SCT: no | ||
838 | */ | ||
839 | #define HW_DRAM_CTL33 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84)) | ||
840 | #define BP_DRAM_CTL33_VERSION 16 | ||
841 | #define BM_DRAM_CTL33_VERSION 0xffff0000 | ||
842 | #define BF_DRAM_CTL33_VERSION(v) (((v) << 16) & 0xffff0000) | ||
843 | #define BP_DRAM_CTL33_TXSR 0 | ||
844 | #define BM_DRAM_CTL33_TXSR 0xffff | ||
845 | #define BF_DRAM_CTL33_TXSR(v) (((v) << 0) & 0xffff) | ||
846 | |||
847 | /** | ||
848 | * Register: HW_DRAM_CTL34 | ||
849 | * Address: 0x88 | ||
850 | * SCT: no | ||
851 | */ | ||
852 | #define HW_DRAM_CTL34 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88)) | ||
853 | #define BP_DRAM_CTL34_RSVD1 24 | ||
854 | #define BM_DRAM_CTL34_RSVD1 0xff000000 | ||
855 | #define BF_DRAM_CTL34_RSVD1(v) (((v) << 24) & 0xff000000) | ||
856 | #define BP_DRAM_CTL34_TINIT 0 | ||
857 | #define BM_DRAM_CTL34_TINIT 0xffffff | ||
858 | #define BF_DRAM_CTL34_TINIT(v) (((v) << 0) & 0xffffff) | ||
859 | |||
860 | /** | ||
861 | * Register: HW_DRAM_CTL35 | ||
862 | * Address: 0x8c | ||
863 | * SCT: no | ||
864 | */ | ||
865 | #define HW_DRAM_CTL35 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c)) | ||
866 | #define BP_DRAM_CTL35_RSVD1 31 | ||
867 | #define BM_DRAM_CTL35_RSVD1 0x80000000 | ||
868 | #define BF_DRAM_CTL35_RSVD1(v) (((v) << 31) & 0x80000000) | ||
869 | #define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR 0 | ||
870 | #define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR 0x7fffffff | ||
871 | #define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v) (((v) << 0) & 0x7fffffff) | ||
872 | |||
873 | /** | ||
874 | * Register: HW_DRAM_CTL36 | ||
875 | * Address: 0x90 | ||
876 | * SCT: no | ||
877 | */ | ||
878 | #define HW_DRAM_CTL36 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90)) | ||
879 | #define BP_DRAM_CTL36_RSVD4 25 | ||
880 | #define BM_DRAM_CTL36_RSVD4 0xfe000000 | ||
881 | #define BF_DRAM_CTL36_RSVD4(v) (((v) << 25) & 0xfe000000) | ||
882 | #define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT 24 | ||
883 | #define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT 0x1000000 | ||
884 | #define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v) (((v) << 24) & 0x1000000) | ||
885 | #define BP_DRAM_CTL36_RSVD3 17 | ||
886 | #define BM_DRAM_CTL36_RSVD3 0xfe0000 | ||
887 | #define BF_DRAM_CTL36_RSVD3(v) (((v) << 17) & 0xfe0000) | ||
888 | #define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH 16 | ||
889 | #define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH 0x10000 | ||
890 | #define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v) (((v) << 16) & 0x10000) | ||
891 | #define BP_DRAM_CTL36_RSVD2 9 | ||
892 | #define BM_DRAM_CTL36_RSVD2 0xfe00 | ||
893 | #define BF_DRAM_CTL36_RSVD2(v) (((v) << 9) & 0xfe00) | ||
894 | #define BP_DRAM_CTL36_BUS_SHARE_ENABLE 8 | ||
895 | #define BM_DRAM_CTL36_BUS_SHARE_ENABLE 0x100 | ||
896 | #define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v) (((v) << 8) & 0x100) | ||
897 | #define BP_DRAM_CTL36_RSVD1 1 | ||
898 | #define BM_DRAM_CTL36_RSVD1 0xfe | ||
899 | #define BF_DRAM_CTL36_RSVD1(v) (((v) << 1) & 0xfe) | ||
900 | #define BP_DRAM_CTL36_ACTIVE_AGING 0 | ||
901 | #define BM_DRAM_CTL36_ACTIVE_AGING 0x1 | ||
902 | #define BF_DRAM_CTL36_ACTIVE_AGING(v) (((v) << 0) & 0x1) | ||
903 | |||
904 | /** | ||
905 | * Register: HW_DRAM_CTL37 | ||
906 | * Address: 0x94 | ||
907 | * SCT: no | ||
908 | */ | ||
909 | #define HW_DRAM_CTL37 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94)) | ||
910 | #define BP_DRAM_CTL37_OBSOLETE 24 | ||
911 | #define BM_DRAM_CTL37_OBSOLETE 0xff000000 | ||
912 | #define BF_DRAM_CTL37_OBSOLETE(v) (((v) << 24) & 0xff000000) | ||
913 | #define BP_DRAM_CTL37_RSVD2 18 | ||
914 | #define BM_DRAM_CTL37_RSVD2 0xfc0000 | ||
915 | #define BF_DRAM_CTL37_RSVD2(v) (((v) << 18) & 0xfc0000) | ||
916 | #define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT 8 | ||
917 | #define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT 0x3ff00 | ||
918 | #define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v) (((v) << 8) & 0x3ff00) | ||
919 | #define BP_DRAM_CTL37_RSVD1 1 | ||
920 | #define BM_DRAM_CTL37_RSVD1 0xfe | ||
921 | #define BF_DRAM_CTL37_RSVD1(v) (((v) << 1) & 0xfe) | ||
922 | #define BP_DRAM_CTL37_TREF_ENABLE 0 | ||
923 | #define BM_DRAM_CTL37_TREF_ENABLE 0x1 | ||
924 | #define BF_DRAM_CTL37_TREF_ENABLE(v) (((v) << 0) & 0x1) | ||
925 | |||
926 | /** | ||
927 | * Register: HW_DRAM_CTL38 | ||
928 | * Address: 0x98 | ||
929 | * SCT: no | ||
930 | */ | ||
931 | #define HW_DRAM_CTL38 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98)) | ||
932 | #define BP_DRAM_CTL38_RSVD2 29 | ||
933 | #define BM_DRAM_CTL38_RSVD2 0xe0000000 | ||
934 | #define BF_DRAM_CTL38_RSVD2(v) (((v) << 29) & 0xe0000000) | ||
935 | #define BP_DRAM_CTL38_EMRS2_DATA_0 16 | ||
936 | #define BM_DRAM_CTL38_EMRS2_DATA_0 0x1fff0000 | ||
937 | #define BF_DRAM_CTL38_EMRS2_DATA_0(v) (((v) << 16) & 0x1fff0000) | ||
938 | #define BP_DRAM_CTL38_RSVD1 13 | ||
939 | #define BM_DRAM_CTL38_RSVD1 0xe000 | ||
940 | #define BF_DRAM_CTL38_RSVD1(v) (((v) << 13) & 0xe000) | ||
941 | #define BP_DRAM_CTL38_EMRS1_DATA 0 | ||
942 | #define BM_DRAM_CTL38_EMRS1_DATA 0x1fff | ||
943 | #define BF_DRAM_CTL38_EMRS1_DATA(v) (((v) << 0) & 0x1fff) | ||
944 | |||
945 | /** | ||
946 | * Register: HW_DRAM_CTL39 | ||
947 | * Address: 0x9c | ||
948 | * SCT: no | ||
949 | */ | ||
950 | #define HW_DRAM_CTL39 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c)) | ||
951 | #define BP_DRAM_CTL39_RSVD2 29 | ||
952 | #define BM_DRAM_CTL39_RSVD2 0xe0000000 | ||
953 | #define BF_DRAM_CTL39_RSVD2(v) (((v) << 29) & 0xe0000000) | ||
954 | #define BP_DRAM_CTL39_EMRS2_DATA_2 16 | ||
955 | #define BM_DRAM_CTL39_EMRS2_DATA_2 0x1fff0000 | ||
956 | #define BF_DRAM_CTL39_EMRS2_DATA_2(v) (((v) << 16) & 0x1fff0000) | ||
957 | #define BP_DRAM_CTL39_RSVD1 13 | ||
958 | #define BM_DRAM_CTL39_RSVD1 0xe000 | ||
959 | #define BF_DRAM_CTL39_RSVD1(v) (((v) << 13) & 0xe000) | ||
960 | #define BP_DRAM_CTL39_EMRS2_DATA_1 0 | ||
961 | #define BM_DRAM_CTL39_EMRS2_DATA_1 0x1fff | ||
962 | #define BF_DRAM_CTL39_EMRS2_DATA_1(v) (((v) << 0) & 0x1fff) | ||
963 | |||
964 | /** | ||
965 | * Register: HW_DRAM_CTL40 | ||
966 | * Address: 0xa0 | ||
967 | * SCT: no | ||
968 | */ | ||
969 | #define HW_DRAM_CTL40 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0)) | ||
970 | #define BP_DRAM_CTL40_TPDEX 16 | ||
971 | #define BM_DRAM_CTL40_TPDEX 0xffff0000 | ||
972 | #define BF_DRAM_CTL40_TPDEX(v) (((v) << 16) & 0xffff0000) | ||
973 | #define BP_DRAM_CTL40_RSVD1 13 | ||
974 | #define BM_DRAM_CTL40_RSVD1 0xe000 | ||
975 | #define BF_DRAM_CTL40_RSVD1(v) (((v) << 13) & 0xe000) | ||
976 | #define BP_DRAM_CTL40_EMRS2_DATA_3 0 | ||
977 | #define BM_DRAM_CTL40_EMRS2_DATA_3 0x1fff | ||
978 | #define BF_DRAM_CTL40_EMRS2_DATA_3(v) (((v) << 0) & 0x1fff) | ||
979 | |||
980 | #endif /* __HEADERGEN__IMX233__DRAM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dri.h b/firmware/target/arm/imx233/regs/imx233/regs-dri.h new file mode 100644 index 0000000000..4802b28c12 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-dri.h | |||
@@ -0,0 +1,304 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__DRI__H__ | ||
24 | #define __HEADERGEN__IMX233__DRI__H__ | ||
25 | |||
26 | #define REGS_DRI_BASE (0x80074000) | ||
27 | |||
28 | #define REGS_DRI_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DRI_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DRI_CTRL_SFTRST 31 | ||
40 | #define BM_DRI_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_DRI_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_DRI_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_DRI_CTRL_CLKGATE 30 | ||
46 | #define BM_DRI_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_DRI_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_DRI_CTRL_ENABLE_INPUTS 29 | ||
52 | #define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 | ||
53 | #define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0 | ||
54 | #define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1 | ||
55 | #define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000) | ||
57 | #define BP_DRI_CTRL_RSVD4 27 | ||
58 | #define BM_DRI_CTRL_RSVD4 0x18000000 | ||
59 | #define BF_DRI_CTRL_RSVD4(v) (((v) << 27) & 0x18000000) | ||
60 | #define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26 | ||
61 | #define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000 | ||
62 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0 | ||
63 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1 | ||
64 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000) | ||
65 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000) | ||
66 | #define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25 | ||
67 | #define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000 | ||
68 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0 | ||
69 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1 | ||
70 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000) | ||
71 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000) | ||
72 | #define BP_DRI_CTRL_RSVD3 21 | ||
73 | #define BM_DRI_CTRL_RSVD3 0x1e00000 | ||
74 | #define BF_DRI_CTRL_RSVD3(v) (((v) << 21) & 0x1e00000) | ||
75 | #define BP_DRI_CTRL_DMA_DELAY_COUNT 16 | ||
76 | #define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000 | ||
77 | #define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000) | ||
78 | #define BP_DRI_CTRL_REACQUIRE_PHASE 15 | ||
79 | #define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000 | ||
80 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0 | ||
81 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1 | ||
82 | #define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000) | ||
83 | #define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000) | ||
84 | #define BP_DRI_CTRL_RSVD2 12 | ||
85 | #define BM_DRI_CTRL_RSVD2 0x7000 | ||
86 | #define BF_DRI_CTRL_RSVD2(v) (((v) << 12) & 0x7000) | ||
87 | #define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11 | ||
88 | #define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800 | ||
89 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0 | ||
90 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1 | ||
91 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800) | ||
92 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800) | ||
93 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10 | ||
94 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400 | ||
95 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0 | ||
96 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1 | ||
97 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
98 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
99 | #define BP_DRI_CTRL_ATTENTION_IRQ_EN 9 | ||
100 | #define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200 | ||
101 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0 | ||
102 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1 | ||
103 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200) | ||
104 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200) | ||
105 | #define BP_DRI_CTRL_RSVD1 4 | ||
106 | #define BM_DRI_CTRL_RSVD1 0x1f0 | ||
107 | #define BF_DRI_CTRL_RSVD1(v) (((v) << 4) & 0x1f0) | ||
108 | #define BP_DRI_CTRL_OVERFLOW_IRQ 3 | ||
109 | #define BM_DRI_CTRL_OVERFLOW_IRQ 0x8 | ||
110 | #define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
111 | #define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1 | ||
112 | #define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
113 | #define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8) | ||
114 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2 | ||
115 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4 | ||
116 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0 | ||
117 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1 | ||
118 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
119 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4) | ||
120 | #define BP_DRI_CTRL_ATTENTION_IRQ 1 | ||
121 | #define BM_DRI_CTRL_ATTENTION_IRQ 0x2 | ||
122 | #define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0 | ||
123 | #define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1 | ||
124 | #define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2) | ||
125 | #define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2) | ||
126 | #define BP_DRI_CTRL_RUN 0 | ||
127 | #define BM_DRI_CTRL_RUN 0x1 | ||
128 | #define BV_DRI_CTRL_RUN__HALT 0x0 | ||
129 | #define BV_DRI_CTRL_RUN__RUN 0x1 | ||
130 | #define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
131 | #define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_DRI_TIMING | ||
135 | * Address: 0x10 | ||
136 | * SCT: no | ||
137 | */ | ||
138 | #define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10)) | ||
139 | #define BP_DRI_TIMING_RSVD2 20 | ||
140 | #define BM_DRI_TIMING_RSVD2 0xfff00000 | ||
141 | #define BF_DRI_TIMING_RSVD2(v) (((v) << 20) & 0xfff00000) | ||
142 | #define BP_DRI_TIMING_PILOT_REP_RATE 16 | ||
143 | #define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000 | ||
144 | #define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000) | ||
145 | #define BP_DRI_TIMING_RSVD1 8 | ||
146 | #define BM_DRI_TIMING_RSVD1 0xff00 | ||
147 | #define BF_DRI_TIMING_RSVD1(v) (((v) << 8) & 0xff00) | ||
148 | #define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 | ||
149 | #define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff | ||
150 | #define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_DRI_STAT | ||
154 | * Address: 0x20 | ||
155 | * SCT: no | ||
156 | */ | ||
157 | #define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20)) | ||
158 | #define BP_DRI_STAT_DRI_PRESENT 31 | ||
159 | #define BM_DRI_STAT_DRI_PRESENT 0x80000000 | ||
160 | #define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0 | ||
161 | #define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1 | ||
162 | #define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000) | ||
163 | #define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000) | ||
164 | #define BP_DRI_STAT_RSVD3 20 | ||
165 | #define BM_DRI_STAT_RSVD3 0x7ff00000 | ||
166 | #define BF_DRI_STAT_RSVD3(v) (((v) << 20) & 0x7ff00000) | ||
167 | #define BP_DRI_STAT_PILOT_PHASE 16 | ||
168 | #define BM_DRI_STAT_PILOT_PHASE 0xf0000 | ||
169 | #define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000) | ||
170 | #define BP_DRI_STAT_RSVD2 4 | ||
171 | #define BM_DRI_STAT_RSVD2 0xfff0 | ||
172 | #define BF_DRI_STAT_RSVD2(v) (((v) << 4) & 0xfff0) | ||
173 | #define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3 | ||
174 | #define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8 | ||
175 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
176 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1 | ||
177 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
178 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8) | ||
179 | #define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2 | ||
180 | #define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4 | ||
181 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
182 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
183 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
184 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
185 | #define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1 | ||
186 | #define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2 | ||
187 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
188 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1 | ||
189 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
190 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2) | ||
191 | #define BP_DRI_STAT_RSVD1 0 | ||
192 | #define BM_DRI_STAT_RSVD1 0x1 | ||
193 | #define BF_DRI_STAT_RSVD1(v) (((v) << 0) & 0x1) | ||
194 | |||
195 | /** | ||
196 | * Register: HW_DRI_DATA | ||
197 | * Address: 0x30 | ||
198 | * SCT: no | ||
199 | */ | ||
200 | #define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30)) | ||
201 | #define BP_DRI_DATA_DATA 0 | ||
202 | #define BM_DRI_DATA_DATA 0xffffffff | ||
203 | #define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
204 | |||
205 | /** | ||
206 | * Register: HW_DRI_DEBUG0 | ||
207 | * Address: 0x40 | ||
208 | * SCT: yes | ||
209 | */ | ||
210 | #define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0)) | ||
211 | #define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4)) | ||
212 | #define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8)) | ||
213 | #define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc)) | ||
214 | #define BP_DRI_DEBUG0_DMAREQ 31 | ||
215 | #define BM_DRI_DEBUG0_DMAREQ 0x80000000 | ||
216 | #define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
217 | #define BP_DRI_DEBUG0_DMACMDKICK 30 | ||
218 | #define BM_DRI_DEBUG0_DMACMDKICK 0x40000000 | ||
219 | #define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000) | ||
220 | #define BP_DRI_DEBUG0_DRI_CLK_INPUT 29 | ||
221 | #define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000 | ||
222 | #define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000) | ||
223 | #define BP_DRI_DEBUG0_DRI_DATA_INPUT 28 | ||
224 | #define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000 | ||
225 | #define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000) | ||
226 | #define BP_DRI_DEBUG0_TEST_MODE 27 | ||
227 | #define BM_DRI_DEBUG0_TEST_MODE 0x8000000 | ||
228 | #define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000) | ||
229 | #define BP_DRI_DEBUG0_PILOT_REP_RATE 26 | ||
230 | #define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000 | ||
231 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0 | ||
232 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1 | ||
233 | #define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000) | ||
234 | #define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000) | ||
235 | #define BP_DRI_DEBUG0_SPARE 18 | ||
236 | #define BM_DRI_DEBUG0_SPARE 0x3fc0000 | ||
237 | #define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000) | ||
238 | #define BP_DRI_DEBUG0_FRAME 0 | ||
239 | #define BM_DRI_DEBUG0_FRAME 0x3ffff | ||
240 | #define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff) | ||
241 | |||
242 | /** | ||
243 | * Register: HW_DRI_DEBUG1 | ||
244 | * Address: 0x50 | ||
245 | * SCT: yes | ||
246 | */ | ||
247 | #define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0)) | ||
248 | #define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4)) | ||
249 | #define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8)) | ||
250 | #define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc)) | ||
251 | #define BP_DRI_DEBUG1_INVERT_PILOT 31 | ||
252 | #define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000 | ||
253 | #define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0 | ||
254 | #define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1 | ||
255 | #define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000) | ||
256 | #define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000) | ||
257 | #define BP_DRI_DEBUG1_INVERT_ATTENTION 30 | ||
258 | #define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000 | ||
259 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0 | ||
260 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1 | ||
261 | #define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000) | ||
262 | #define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000) | ||
263 | #define BP_DRI_DEBUG1_INVERT_DRI_DATA 29 | ||
264 | #define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000 | ||
265 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0 | ||
266 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1 | ||
267 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000) | ||
268 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000) | ||
269 | #define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28 | ||
270 | #define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000 | ||
271 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0 | ||
272 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1 | ||
273 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000) | ||
274 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000) | ||
275 | #define BP_DRI_DEBUG1_REVERSE_FRAME 27 | ||
276 | #define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000 | ||
277 | #define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0 | ||
278 | #define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1 | ||
279 | #define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000) | ||
280 | #define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000) | ||
281 | #define BP_DRI_DEBUG1_RSVD1 18 | ||
282 | #define BM_DRI_DEBUG1_RSVD1 0x7fc0000 | ||
283 | #define BF_DRI_DEBUG1_RSVD1(v) (((v) << 18) & 0x7fc0000) | ||
284 | #define BP_DRI_DEBUG1_SWIZZLED_FRAME 0 | ||
285 | #define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff | ||
286 | #define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff) | ||
287 | |||
288 | /** | ||
289 | * Register: HW_DRI_VERSION | ||
290 | * Address: 0x60 | ||
291 | * SCT: no | ||
292 | */ | ||
293 | #define HW_DRI_VERSION (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60)) | ||
294 | #define BP_DRI_VERSION_MAJOR 24 | ||
295 | #define BM_DRI_VERSION_MAJOR 0xff000000 | ||
296 | #define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
297 | #define BP_DRI_VERSION_MINOR 16 | ||
298 | #define BM_DRI_VERSION_MINOR 0xff0000 | ||
299 | #define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
300 | #define BP_DRI_VERSION_STEP 0 | ||
301 | #define BM_DRI_VERSION_STEP 0xffff | ||
302 | #define BF_DRI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
303 | |||
304 | #endif /* __HEADERGEN__IMX233__DRI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h b/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h new file mode 100644 index 0000000000..0cdb62a096 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h | |||
@@ -0,0 +1,408 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__ECC8__H__ | ||
24 | #define __HEADERGEN__IMX233__ECC8__H__ | ||
25 | |||
26 | #define REGS_ECC8_BASE (0x80008000) | ||
27 | |||
28 | #define REGS_ECC8_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ECC8_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_ECC8_CTRL (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x0)) | ||
36 | #define HW_ECC8_CTRL_SET (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x4)) | ||
37 | #define HW_ECC8_CTRL_CLR (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x8)) | ||
38 | #define HW_ECC8_CTRL_TOG (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0xc)) | ||
39 | #define BP_ECC8_CTRL_SFTRST 31 | ||
40 | #define BM_ECC8_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_ECC8_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_ECC8_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_ECC8_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_ECC8_CTRL_SFTRST_V(v) ((BV_ECC8_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_ECC8_CTRL_CLKGATE 30 | ||
46 | #define BM_ECC8_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_ECC8_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_ECC8_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_ECC8_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_ECC8_CTRL_CLKGATE_V(v) ((BV_ECC8_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_ECC8_CTRL_AHBM_SFTRST 29 | ||
52 | #define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 | ||
53 | #define BV_ECC8_CTRL_AHBM_SFTRST__RUN 0x0 | ||
54 | #define BV_ECC8_CTRL_AHBM_SFTRST__RESET 0x1 | ||
55 | #define BF_ECC8_CTRL_AHBM_SFTRST(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_ECC8_CTRL_AHBM_SFTRST_V(v) ((BV_ECC8_CTRL_AHBM_SFTRST__##v << 29) & 0x20000000) | ||
57 | #define BP_ECC8_CTRL_RSRVD2 28 | ||
58 | #define BM_ECC8_CTRL_RSRVD2 0x10000000 | ||
59 | #define BF_ECC8_CTRL_RSRVD2(v) (((v) << 28) & 0x10000000) | ||
60 | #define BP_ECC8_CTRL_THROTTLE 24 | ||
61 | #define BM_ECC8_CTRL_THROTTLE 0xf000000 | ||
62 | #define BF_ECC8_CTRL_THROTTLE(v) (((v) << 24) & 0xf000000) | ||
63 | #define BP_ECC8_CTRL_RSRVD1 11 | ||
64 | #define BM_ECC8_CTRL_RSRVD1 0xfff800 | ||
65 | #define BF_ECC8_CTRL_RSRVD1(v) (((v) << 11) & 0xfff800) | ||
66 | #define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN 10 | ||
67 | #define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN 0x400 | ||
68 | #define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v) (((v) << 10) & 0x400) | ||
69 | #define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN 9 | ||
70 | #define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN 0x200 | ||
71 | #define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v) (((v) << 9) & 0x200) | ||
72 | #define BP_ECC8_CTRL_COMPLETE_IRQ_EN 8 | ||
73 | #define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x100 | ||
74 | #define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
75 | #define BP_ECC8_CTRL_RSRVD0 4 | ||
76 | #define BM_ECC8_CTRL_RSRVD0 0xf0 | ||
77 | #define BF_ECC8_CTRL_RSRVD0(v) (((v) << 4) & 0xf0) | ||
78 | #define BP_ECC8_CTRL_BM_ERROR_IRQ 3 | ||
79 | #define BM_ECC8_CTRL_BM_ERROR_IRQ 0x8 | ||
80 | #define BF_ECC8_CTRL_BM_ERROR_IRQ(v) (((v) << 3) & 0x8) | ||
81 | #define BP_ECC8_CTRL_DEBUG_STALL_IRQ 2 | ||
82 | #define BM_ECC8_CTRL_DEBUG_STALL_IRQ 0x4 | ||
83 | #define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v) (((v) << 2) & 0x4) | ||
84 | #define BP_ECC8_CTRL_DEBUG_WRITE_IRQ 1 | ||
85 | #define BM_ECC8_CTRL_DEBUG_WRITE_IRQ 0x2 | ||
86 | #define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v) (((v) << 1) & 0x2) | ||
87 | #define BP_ECC8_CTRL_COMPLETE_IRQ 0 | ||
88 | #define BM_ECC8_CTRL_COMPLETE_IRQ 0x1 | ||
89 | #define BF_ECC8_CTRL_COMPLETE_IRQ(v) (((v) << 0) & 0x1) | ||
90 | |||
91 | /** | ||
92 | * Register: HW_ECC8_STATUS0 | ||
93 | * Address: 0x10 | ||
94 | * SCT: no | ||
95 | */ | ||
96 | #define HW_ECC8_STATUS0 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x10)) | ||
97 | #define BP_ECC8_STATUS0_HANDLE 20 | ||
98 | #define BM_ECC8_STATUS0_HANDLE 0xfff00000 | ||
99 | #define BF_ECC8_STATUS0_HANDLE(v) (((v) << 20) & 0xfff00000) | ||
100 | #define BP_ECC8_STATUS0_COMPLETED_CE 16 | ||
101 | #define BM_ECC8_STATUS0_COMPLETED_CE 0xf0000 | ||
102 | #define BF_ECC8_STATUS0_COMPLETED_CE(v) (((v) << 16) & 0xf0000) | ||
103 | #define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT 15 | ||
104 | #define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT 0x8000 | ||
105 | #define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v) (((v) << 15) & 0x8000) | ||
106 | #define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT 14 | ||
107 | #define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT 0x4000 | ||
108 | #define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v) (((v) << 14) & 0x4000) | ||
109 | #define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT 13 | ||
110 | #define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT 0x2000 | ||
111 | #define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v) (((v) << 13) & 0x2000) | ||
112 | #define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT 12 | ||
113 | #define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT 0x1000 | ||
114 | #define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v) (((v) << 12) & 0x1000) | ||
115 | #define BP_ECC8_STATUS0_STATUS_AUX 8 | ||
116 | #define BM_ECC8_STATUS0_STATUS_AUX 0xf00 | ||
117 | #define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS 0x0 | ||
118 | #define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE 0x1 | ||
119 | #define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE 0x2 | ||
120 | #define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE 0x3 | ||
121 | #define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE 0x4 | ||
122 | #define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED 0xc | ||
123 | #define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE 0xe | ||
124 | #define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES 0xf | ||
125 | #define BF_ECC8_STATUS0_STATUS_AUX(v) (((v) << 8) & 0xf00) | ||
126 | #define BF_ECC8_STATUS0_STATUS_AUX_V(v) ((BV_ECC8_STATUS0_STATUS_AUX__##v << 8) & 0xf00) | ||
127 | #define BP_ECC8_STATUS0_RSVD1 5 | ||
128 | #define BM_ECC8_STATUS0_RSVD1 0xe0 | ||
129 | #define BF_ECC8_STATUS0_RSVD1(v) (((v) << 5) & 0xe0) | ||
130 | #define BP_ECC8_STATUS0_ALLONES 4 | ||
131 | #define BM_ECC8_STATUS0_ALLONES 0x10 | ||
132 | #define BF_ECC8_STATUS0_ALLONES(v) (((v) << 4) & 0x10) | ||
133 | #define BP_ECC8_STATUS0_CORRECTED 3 | ||
134 | #define BM_ECC8_STATUS0_CORRECTED 0x8 | ||
135 | #define BF_ECC8_STATUS0_CORRECTED(v) (((v) << 3) & 0x8) | ||
136 | #define BP_ECC8_STATUS0_UNCORRECTABLE 2 | ||
137 | #define BM_ECC8_STATUS0_UNCORRECTABLE 0x4 | ||
138 | #define BF_ECC8_STATUS0_UNCORRECTABLE(v) (((v) << 2) & 0x4) | ||
139 | #define BP_ECC8_STATUS0_RSVD0 0 | ||
140 | #define BM_ECC8_STATUS0_RSVD0 0x3 | ||
141 | #define BF_ECC8_STATUS0_RSVD0(v) (((v) << 0) & 0x3) | ||
142 | |||
143 | /** | ||
144 | * Register: HW_ECC8_STATUS1 | ||
145 | * Address: 0x20 | ||
146 | * SCT: no | ||
147 | */ | ||
148 | #define HW_ECC8_STATUS1 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x20)) | ||
149 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD7 28 | ||
150 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD7 0xf0000000 | ||
151 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS 0x0 | ||
152 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE 0x1 | ||
153 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE 0x2 | ||
154 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE 0x3 | ||
155 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE 0x4 | ||
156 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE 0x5 | ||
157 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE 0x6 | ||
158 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE 0x7 | ||
159 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE 0x8 | ||
160 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED 0xc | ||
161 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE 0xe | ||
162 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES 0xf | ||
163 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v) (((v) << 28) & 0xf0000000) | ||
164 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD7__##v << 28) & 0xf0000000) | ||
165 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD6 24 | ||
166 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD6 0xf000000 | ||
167 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS 0x0 | ||
168 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE 0x1 | ||
169 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE 0x2 | ||
170 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE 0x3 | ||
171 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE 0x4 | ||
172 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE 0x5 | ||
173 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE 0x6 | ||
174 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE 0x7 | ||
175 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE 0x8 | ||
176 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED 0xc | ||
177 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE 0xe | ||
178 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES 0xf | ||
179 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v) (((v) << 24) & 0xf000000) | ||
180 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD6__##v << 24) & 0xf000000) | ||
181 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD5 20 | ||
182 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD5 0xf00000 | ||
183 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS 0x0 | ||
184 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE 0x1 | ||
185 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE 0x2 | ||
186 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE 0x3 | ||
187 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE 0x4 | ||
188 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE 0x5 | ||
189 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE 0x6 | ||
190 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE 0x7 | ||
191 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE 0x8 | ||
192 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED 0xc | ||
193 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE 0xe | ||
194 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES 0xf | ||
195 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v) (((v) << 20) & 0xf00000) | ||
196 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD5__##v << 20) & 0xf00000) | ||
197 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD4 16 | ||
198 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD4 0xf0000 | ||
199 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS 0x0 | ||
200 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE 0x1 | ||
201 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE 0x2 | ||
202 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE 0x3 | ||
203 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE 0x4 | ||
204 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE 0x5 | ||
205 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE 0x6 | ||
206 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE 0x7 | ||
207 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE 0x8 | ||
208 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED 0xc | ||
209 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE 0xe | ||
210 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES 0xf | ||
211 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v) (((v) << 16) & 0xf0000) | ||
212 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD4__##v << 16) & 0xf0000) | ||
213 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD3 12 | ||
214 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD3 0xf000 | ||
215 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS 0x0 | ||
216 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE 0x1 | ||
217 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE 0x2 | ||
218 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE 0x3 | ||
219 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE 0x4 | ||
220 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE 0x5 | ||
221 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE 0x6 | ||
222 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE 0x7 | ||
223 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE 0x8 | ||
224 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED 0xc | ||
225 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE 0xe | ||
226 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES 0xf | ||
227 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v) (((v) << 12) & 0xf000) | ||
228 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD3__##v << 12) & 0xf000) | ||
229 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD2 8 | ||
230 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD2 0xf00 | ||
231 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS 0x0 | ||
232 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE 0x1 | ||
233 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE 0x2 | ||
234 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE 0x3 | ||
235 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE 0x4 | ||
236 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE 0x5 | ||
237 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE 0x6 | ||
238 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE 0x7 | ||
239 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE 0x8 | ||
240 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED 0xc | ||
241 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE 0xe | ||
242 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES 0xf | ||
243 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v) (((v) << 8) & 0xf00) | ||
244 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD2__##v << 8) & 0xf00) | ||
245 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD1 4 | ||
246 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD1 0xf0 | ||
247 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS 0x0 | ||
248 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE 0x1 | ||
249 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE 0x2 | ||
250 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE 0x3 | ||
251 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE 0x4 | ||
252 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE 0x5 | ||
253 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE 0x6 | ||
254 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE 0x7 | ||
255 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE 0x8 | ||
256 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED 0xc | ||
257 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE 0xe | ||
258 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES 0xf | ||
259 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v) (((v) << 4) & 0xf0) | ||
260 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD1__##v << 4) & 0xf0) | ||
261 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD0 0 | ||
262 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD0 0xf | ||
263 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS 0x0 | ||
264 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE 0x1 | ||
265 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE 0x2 | ||
266 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE 0x3 | ||
267 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE 0x4 | ||
268 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE 0x5 | ||
269 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE 0x6 | ||
270 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE 0x7 | ||
271 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE 0x8 | ||
272 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED 0xc | ||
273 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE 0xe | ||
274 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES 0xf | ||
275 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v) (((v) << 0) & 0xf) | ||
276 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD0__##v << 0) & 0xf) | ||
277 | |||
278 | /** | ||
279 | * Register: HW_ECC8_DEBUG0 | ||
280 | * Address: 0x30 | ||
281 | * SCT: yes | ||
282 | */ | ||
283 | #define HW_ECC8_DEBUG0 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x0)) | ||
284 | #define HW_ECC8_DEBUG0_SET (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x4)) | ||
285 | #define HW_ECC8_DEBUG0_CLR (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x8)) | ||
286 | #define HW_ECC8_DEBUG0_TOG (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0xc)) | ||
287 | #define BP_ECC8_DEBUG0_RSRVD1 25 | ||
288 | #define BM_ECC8_DEBUG0_RSRVD1 0xfe000000 | ||
289 | #define BF_ECC8_DEBUG0_RSRVD1(v) (((v) << 25) & 0xfe000000) | ||
290 | #define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 | ||
291 | #define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x1ff0000 | ||
292 | #define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 | ||
293 | #define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 | ||
294 | #define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << 16) & 0x1ff0000) | ||
295 | #define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000) | ||
296 | #define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND 15 | ||
297 | #define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND 0x8000 | ||
298 | #define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v) (((v) << 15) & 0x8000) | ||
299 | #define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 14 | ||
300 | #define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x4000 | ||
301 | #define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 | ||
302 | #define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 | ||
303 | #define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) (((v) << 14) & 0x4000) | ||
304 | #define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000) | ||
305 | #define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K 13 | ||
306 | #define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K 0x2000 | ||
307 | #define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 | ||
308 | #define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 | ||
309 | #define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v) (((v) << 13) & 0x2000) | ||
310 | #define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000) | ||
311 | #define BP_ECC8_DEBUG0_KES_DEBUG_KICK 12 | ||
312 | #define BM_ECC8_DEBUG0_KES_DEBUG_KICK 0x1000 | ||
313 | #define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v) (((v) << 12) & 0x1000) | ||
314 | #define BP_ECC8_DEBUG0_KES_STANDALONE 11 | ||
315 | #define BM_ECC8_DEBUG0_KES_STANDALONE 0x800 | ||
316 | #define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL 0x0 | ||
317 | #define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 | ||
318 | #define BF_ECC8_DEBUG0_KES_STANDALONE(v) (((v) << 11) & 0x800) | ||
319 | #define BF_ECC8_DEBUG0_KES_STANDALONE_V(v) ((BV_ECC8_DEBUG0_KES_STANDALONE__##v << 11) & 0x800) | ||
320 | #define BP_ECC8_DEBUG0_KES_DEBUG_STEP 10 | ||
321 | #define BM_ECC8_DEBUG0_KES_DEBUG_STEP 0x400 | ||
322 | #define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v) (((v) << 10) & 0x400) | ||
323 | #define BP_ECC8_DEBUG0_KES_DEBUG_STALL 9 | ||
324 | #define BM_ECC8_DEBUG0_KES_DEBUG_STALL 0x200 | ||
325 | #define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 | ||
326 | #define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 | ||
327 | #define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v) (((v) << 9) & 0x200) | ||
328 | #define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200) | ||
329 | #define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS 8 | ||
330 | #define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS 0x100 | ||
331 | #define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 | ||
332 | #define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 | ||
333 | #define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v) (((v) << 8) & 0x100) | ||
334 | #define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v) ((BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100) | ||
335 | #define BP_ECC8_DEBUG0_RSRVD0 6 | ||
336 | #define BM_ECC8_DEBUG0_RSRVD0 0xc0 | ||
337 | #define BF_ECC8_DEBUG0_RSRVD0(v) (((v) << 6) & 0xc0) | ||
338 | #define BP_ECC8_DEBUG0_DEBUG_REG_SELECT 0 | ||
339 | #define BM_ECC8_DEBUG0_DEBUG_REG_SELECT 0x3f | ||
340 | #define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v) (((v) << 0) & 0x3f) | ||
341 | |||
342 | /** | ||
343 | * Register: HW_ECC8_DBGKESREAD | ||
344 | * Address: 0x40 | ||
345 | * SCT: no | ||
346 | */ | ||
347 | #define HW_ECC8_DBGKESREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x40)) | ||
348 | #define BP_ECC8_DBGKESREAD_VALUES 0 | ||
349 | #define BM_ECC8_DBGKESREAD_VALUES 0xffffffff | ||
350 | #define BF_ECC8_DBGKESREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
351 | |||
352 | /** | ||
353 | * Register: HW_ECC8_DBGCSFEREAD | ||
354 | * Address: 0x50 | ||
355 | * SCT: no | ||
356 | */ | ||
357 | #define HW_ECC8_DBGCSFEREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x50)) | ||
358 | #define BP_ECC8_DBGCSFEREAD_VALUES 0 | ||
359 | #define BM_ECC8_DBGCSFEREAD_VALUES 0xffffffff | ||
360 | #define BF_ECC8_DBGCSFEREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
361 | |||
362 | /** | ||
363 | * Register: HW_ECC8_DBGSYNDGENREAD | ||
364 | * Address: 0x60 | ||
365 | * SCT: no | ||
366 | */ | ||
367 | #define HW_ECC8_DBGSYNDGENREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x60)) | ||
368 | #define BP_ECC8_DBGSYNDGENREAD_VALUES 0 | ||
369 | #define BM_ECC8_DBGSYNDGENREAD_VALUES 0xffffffff | ||
370 | #define BF_ECC8_DBGSYNDGENREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
371 | |||
372 | /** | ||
373 | * Register: HW_ECC8_DBGAHBMREAD | ||
374 | * Address: 0x70 | ||
375 | * SCT: no | ||
376 | */ | ||
377 | #define HW_ECC8_DBGAHBMREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x70)) | ||
378 | #define BP_ECC8_DBGAHBMREAD_VALUES 0 | ||
379 | #define BM_ECC8_DBGAHBMREAD_VALUES 0xffffffff | ||
380 | #define BF_ECC8_DBGAHBMREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
381 | |||
382 | /** | ||
383 | * Register: HW_ECC8_BLOCKNAME | ||
384 | * Address: 0x80 | ||
385 | * SCT: no | ||
386 | */ | ||
387 | #define HW_ECC8_BLOCKNAME (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x80)) | ||
388 | #define BP_ECC8_BLOCKNAME_NAME 0 | ||
389 | #define BM_ECC8_BLOCKNAME_NAME 0xffffffff | ||
390 | #define BF_ECC8_BLOCKNAME_NAME(v) (((v) << 0) & 0xffffffff) | ||
391 | |||
392 | /** | ||
393 | * Register: HW_ECC8_VERSION | ||
394 | * Address: 0xa0 | ||
395 | * SCT: no | ||
396 | */ | ||
397 | #define HW_ECC8_VERSION (*(volatile unsigned long *)(REGS_ECC8_BASE + 0xa0)) | ||
398 | #define BP_ECC8_VERSION_MAJOR 24 | ||
399 | #define BM_ECC8_VERSION_MAJOR 0xff000000 | ||
400 | #define BF_ECC8_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
401 | #define BP_ECC8_VERSION_MINOR 16 | ||
402 | #define BM_ECC8_VERSION_MINOR 0xff0000 | ||
403 | #define BF_ECC8_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
404 | #define BP_ECC8_VERSION_STEP 0 | ||
405 | #define BM_ECC8_VERSION_STEP 0xffff | ||
406 | #define BF_ECC8_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
407 | |||
408 | #endif /* __HEADERGEN__IMX233__ECC8__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-emi.h b/firmware/target/arm/imx233/regs/imx233/regs-emi.h new file mode 100644 index 0000000000..4a2106e9be --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-emi.h | |||
@@ -0,0 +1,296 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__EMI__H__ | ||
24 | #define __HEADERGEN__IMX233__EMI__H__ | ||
25 | |||
26 | #define REGS_EMI_BASE (0x80020000) | ||
27 | |||
28 | #define REGS_EMI_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_EMI_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_EMI_CTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_EMI_CTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_EMI_CTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_EMI_CTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_EMI_CTRL_SFTRST 31 | ||
40 | #define BM_EMI_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_EMI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_EMI_CTRL_CLKGATE 30 | ||
43 | #define BM_EMI_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_EMI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_EMI_CTRL_TRAP_SR 29 | ||
46 | #define BM_EMI_CTRL_TRAP_SR 0x20000000 | ||
47 | #define BF_EMI_CTRL_TRAP_SR(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_EMI_CTRL_TRAP_INIT 28 | ||
49 | #define BM_EMI_CTRL_TRAP_INIT 0x10000000 | ||
50 | #define BF_EMI_CTRL_TRAP_INIT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_EMI_CTRL_AXI_DEPTH 26 | ||
52 | #define BM_EMI_CTRL_AXI_DEPTH 0xc000000 | ||
53 | #define BV_EMI_CTRL_AXI_DEPTH__ONE 0x0 | ||
54 | #define BV_EMI_CTRL_AXI_DEPTH__TWO 0x1 | ||
55 | #define BV_EMI_CTRL_AXI_DEPTH__THREE 0x2 | ||
56 | #define BV_EMI_CTRL_AXI_DEPTH__FOUR 0x3 | ||
57 | #define BF_EMI_CTRL_AXI_DEPTH(v) (((v) << 26) & 0xc000000) | ||
58 | #define BF_EMI_CTRL_AXI_DEPTH_V(v) ((BV_EMI_CTRL_AXI_DEPTH__##v << 26) & 0xc000000) | ||
59 | #define BP_EMI_CTRL_DLL_SHIFT_RESET 25 | ||
60 | #define BM_EMI_CTRL_DLL_SHIFT_RESET 0x2000000 | ||
61 | #define BF_EMI_CTRL_DLL_SHIFT_RESET(v) (((v) << 25) & 0x2000000) | ||
62 | #define BP_EMI_CTRL_DLL_RESET 24 | ||
63 | #define BM_EMI_CTRL_DLL_RESET 0x1000000 | ||
64 | #define BF_EMI_CTRL_DLL_RESET(v) (((v) << 24) & 0x1000000) | ||
65 | #define BP_EMI_CTRL_ARB_MODE 22 | ||
66 | #define BM_EMI_CTRL_ARB_MODE 0xc00000 | ||
67 | #define BV_EMI_CTRL_ARB_MODE__TIMESTAMP 0x0 | ||
68 | #define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID 0x1 | ||
69 | #define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY 0x2 | ||
70 | #define BF_EMI_CTRL_ARB_MODE(v) (((v) << 22) & 0xc00000) | ||
71 | #define BF_EMI_CTRL_ARB_MODE_V(v) ((BV_EMI_CTRL_ARB_MODE__##v << 22) & 0xc00000) | ||
72 | #define BP_EMI_CTRL_RSVD3 21 | ||
73 | #define BM_EMI_CTRL_RSVD3 0x200000 | ||
74 | #define BF_EMI_CTRL_RSVD3(v) (((v) << 21) & 0x200000) | ||
75 | #define BP_EMI_CTRL_PORT_PRIORITY_ORDER 16 | ||
76 | #define BM_EMI_CTRL_PORT_PRIORITY_ORDER 0x1f0000 | ||
77 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123 0x0 | ||
78 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312 0x1 | ||
79 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231 0x2 | ||
80 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321 0x3 | ||
81 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213 0x4 | ||
82 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132 0x5 | ||
83 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023 0x6 | ||
84 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302 0x7 | ||
85 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230 0x8 | ||
86 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320 0x9 | ||
87 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203 0xa | ||
88 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032 0xb | ||
89 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013 0xc | ||
90 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301 0xd | ||
91 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130 0xe | ||
92 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310 0xf | ||
93 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103 0x10 | ||
94 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031 0x11 | ||
95 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012 0x12 | ||
96 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201 0x13 | ||
97 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120 0x14 | ||
98 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210 0x15 | ||
99 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102 0x16 | ||
100 | #define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021 0x17 | ||
101 | #define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v) (((v) << 16) & 0x1f0000) | ||
102 | #define BF_EMI_CTRL_PORT_PRIORITY_ORDER_V(v) ((BV_EMI_CTRL_PORT_PRIORITY_ORDER__##v << 16) & 0x1f0000) | ||
103 | #define BP_EMI_CTRL_RSVD2 15 | ||
104 | #define BM_EMI_CTRL_RSVD2 0x8000 | ||
105 | #define BF_EMI_CTRL_RSVD2(v) (((v) << 15) & 0x8000) | ||
106 | #define BP_EMI_CTRL_PRIORITY_WRITE_ITER 12 | ||
107 | #define BM_EMI_CTRL_PRIORITY_WRITE_ITER 0x7000 | ||
108 | #define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v) (((v) << 12) & 0x7000) | ||
109 | #define BP_EMI_CTRL_RSVD1 11 | ||
110 | #define BM_EMI_CTRL_RSVD1 0x800 | ||
111 | #define BF_EMI_CTRL_RSVD1(v) (((v) << 11) & 0x800) | ||
112 | #define BP_EMI_CTRL_HIGH_PRIORITY_WRITE 8 | ||
113 | #define BM_EMI_CTRL_HIGH_PRIORITY_WRITE 0x700 | ||
114 | #define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v) (((v) << 8) & 0x700) | ||
115 | #define BP_EMI_CTRL_RSVD0 7 | ||
116 | #define BM_EMI_CTRL_RSVD0 0x80 | ||
117 | #define BF_EMI_CTRL_RSVD0(v) (((v) << 7) & 0x80) | ||
118 | #define BP_EMI_CTRL_MEM_WIDTH 6 | ||
119 | #define BM_EMI_CTRL_MEM_WIDTH 0x40 | ||
120 | #define BF_EMI_CTRL_MEM_WIDTH(v) (((v) << 6) & 0x40) | ||
121 | #define BP_EMI_CTRL_WRITE_PROTECT 5 | ||
122 | #define BM_EMI_CTRL_WRITE_PROTECT 0x20 | ||
123 | #define BF_EMI_CTRL_WRITE_PROTECT(v) (((v) << 5) & 0x20) | ||
124 | #define BP_EMI_CTRL_RESET_OUT 4 | ||
125 | #define BM_EMI_CTRL_RESET_OUT 0x10 | ||
126 | #define BF_EMI_CTRL_RESET_OUT(v) (((v) << 4) & 0x10) | ||
127 | #define BP_EMI_CTRL_CE_SELECT 0 | ||
128 | #define BM_EMI_CTRL_CE_SELECT 0xf | ||
129 | #define BV_EMI_CTRL_CE_SELECT__NONE 0x0 | ||
130 | #define BV_EMI_CTRL_CE_SELECT__CE0 0x1 | ||
131 | #define BV_EMI_CTRL_CE_SELECT__CE1 0x2 | ||
132 | #define BV_EMI_CTRL_CE_SELECT__CE2 0x4 | ||
133 | #define BV_EMI_CTRL_CE_SELECT__CE3 0x8 | ||
134 | #define BF_EMI_CTRL_CE_SELECT(v) (((v) << 0) & 0xf) | ||
135 | #define BF_EMI_CTRL_CE_SELECT_V(v) ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf) | ||
136 | |||
137 | /** | ||
138 | * Register: HW_EMI_STAT | ||
139 | * Address: 0x10 | ||
140 | * SCT: no | ||
141 | */ | ||
142 | #define HW_EMI_STAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10)) | ||
143 | #define BP_EMI_STAT_DRAM_PRESENT 31 | ||
144 | #define BM_EMI_STAT_DRAM_PRESENT 0x80000000 | ||
145 | #define BF_EMI_STAT_DRAM_PRESENT(v) (((v) << 31) & 0x80000000) | ||
146 | #define BP_EMI_STAT_NOR_PRESENT 30 | ||
147 | #define BM_EMI_STAT_NOR_PRESENT 0x40000000 | ||
148 | #define BF_EMI_STAT_NOR_PRESENT(v) (((v) << 30) & 0x40000000) | ||
149 | #define BP_EMI_STAT_LARGE_DRAM_ENABLED 29 | ||
150 | #define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000 | ||
151 | #define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) << 29) & 0x20000000) | ||
152 | #define BP_EMI_STAT_RSVD0 2 | ||
153 | #define BM_EMI_STAT_RSVD0 0x1ffffffc | ||
154 | #define BF_EMI_STAT_RSVD0(v) (((v) << 2) & 0x1ffffffc) | ||
155 | #define BP_EMI_STAT_DRAM_HALTED 1 | ||
156 | #define BM_EMI_STAT_DRAM_HALTED 0x2 | ||
157 | #define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0 | ||
158 | #define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1 | ||
159 | #define BF_EMI_STAT_DRAM_HALTED(v) (((v) << 1) & 0x2) | ||
160 | #define BF_EMI_STAT_DRAM_HALTED_V(v) ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2) | ||
161 | #define BP_EMI_STAT_NOR_BUSY 0 | ||
162 | #define BM_EMI_STAT_NOR_BUSY 0x1 | ||
163 | #define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0 | ||
164 | #define BV_EMI_STAT_NOR_BUSY__BUSY 0x1 | ||
165 | #define BF_EMI_STAT_NOR_BUSY(v) (((v) << 0) & 0x1) | ||
166 | #define BF_EMI_STAT_NOR_BUSY_V(v) ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1) | ||
167 | |||
168 | /** | ||
169 | * Register: HW_EMI_TIME | ||
170 | * Address: 0x20 | ||
171 | * SCT: yes | ||
172 | */ | ||
173 | #define HW_EMI_TIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0)) | ||
174 | #define HW_EMI_TIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4)) | ||
175 | #define HW_EMI_TIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8)) | ||
176 | #define HW_EMI_TIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc)) | ||
177 | #define BP_EMI_TIME_RSVD4 28 | ||
178 | #define BM_EMI_TIME_RSVD4 0xf0000000 | ||
179 | #define BF_EMI_TIME_RSVD4(v) (((v) << 28) & 0xf0000000) | ||
180 | #define BP_EMI_TIME_THZ 24 | ||
181 | #define BM_EMI_TIME_THZ 0xf000000 | ||
182 | #define BF_EMI_TIME_THZ(v) (((v) << 24) & 0xf000000) | ||
183 | #define BP_EMI_TIME_RSVD2 20 | ||
184 | #define BM_EMI_TIME_RSVD2 0xf00000 | ||
185 | #define BF_EMI_TIME_RSVD2(v) (((v) << 20) & 0xf00000) | ||
186 | #define BP_EMI_TIME_TDH 16 | ||
187 | #define BM_EMI_TIME_TDH 0xf0000 | ||
188 | #define BF_EMI_TIME_TDH(v) (((v) << 16) & 0xf0000) | ||
189 | #define BP_EMI_TIME_RSVD1 13 | ||
190 | #define BM_EMI_TIME_RSVD1 0xe000 | ||
191 | #define BF_EMI_TIME_RSVD1(v) (((v) << 13) & 0xe000) | ||
192 | #define BP_EMI_TIME_TDS 8 | ||
193 | #define BM_EMI_TIME_TDS 0x1f00 | ||
194 | #define BF_EMI_TIME_TDS(v) (((v) << 8) & 0x1f00) | ||
195 | #define BP_EMI_TIME_RSVD0 4 | ||
196 | #define BM_EMI_TIME_RSVD0 0xf0 | ||
197 | #define BF_EMI_TIME_RSVD0(v) (((v) << 4) & 0xf0) | ||
198 | #define BP_EMI_TIME_TAS 0 | ||
199 | #define BM_EMI_TIME_TAS 0xf | ||
200 | #define BF_EMI_TIME_TAS(v) (((v) << 0) & 0xf) | ||
201 | |||
202 | /** | ||
203 | * Register: HW_EMI_DDR_TEST_MODE_CSR | ||
204 | * Address: 0x30 | ||
205 | * SCT: yes | ||
206 | */ | ||
207 | #define HW_EMI_DDR_TEST_MODE_CSR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0)) | ||
208 | #define HW_EMI_DDR_TEST_MODE_CSR_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4)) | ||
209 | #define HW_EMI_DDR_TEST_MODE_CSR_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8)) | ||
210 | #define HW_EMI_DDR_TEST_MODE_CSR_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc)) | ||
211 | #define BP_EMI_DDR_TEST_MODE_CSR_RSVD1 2 | ||
212 | #define BM_EMI_DDR_TEST_MODE_CSR_RSVD1 0xfffffffc | ||
213 | #define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v) (((v) << 2) & 0xfffffffc) | ||
214 | #define BP_EMI_DDR_TEST_MODE_CSR_DONE 1 | ||
215 | #define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x2 | ||
216 | #define BF_EMI_DDR_TEST_MODE_CSR_DONE(v) (((v) << 1) & 0x2) | ||
217 | #define BP_EMI_DDR_TEST_MODE_CSR_START 0 | ||
218 | #define BM_EMI_DDR_TEST_MODE_CSR_START 0x1 | ||
219 | #define BF_EMI_DDR_TEST_MODE_CSR_START(v) (((v) << 0) & 0x1) | ||
220 | |||
221 | /** | ||
222 | * Register: HW_EMI_DEBUG | ||
223 | * Address: 0x80 | ||
224 | * SCT: no | ||
225 | */ | ||
226 | #define HW_EMI_DEBUG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80)) | ||
227 | #define BP_EMI_DEBUG_RSVD1 4 | ||
228 | #define BM_EMI_DEBUG_RSVD1 0xfffffff0 | ||
229 | #define BF_EMI_DEBUG_RSVD1(v) (((v) << 4) & 0xfffffff0) | ||
230 | #define BP_EMI_DEBUG_NOR_STATE 0 | ||
231 | #define BM_EMI_DEBUG_NOR_STATE 0xf | ||
232 | #define BF_EMI_DEBUG_NOR_STATE(v) (((v) << 0) & 0xf) | ||
233 | |||
234 | /** | ||
235 | * Register: HW_EMI_DDR_TEST_MODE_STATUS0 | ||
236 | * Address: 0x90 | ||
237 | * SCT: no | ||
238 | */ | ||
239 | #define HW_EMI_DDR_TEST_MODE_STATUS0 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90)) | ||
240 | #define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1 13 | ||
241 | #define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1 0xffffe000 | ||
242 | #define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v) (((v) << 13) & 0xffffe000) | ||
243 | #define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0 | ||
244 | #define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x1fff | ||
245 | #define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) (((v) << 0) & 0x1fff) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_EMI_DDR_TEST_MODE_STATUS1 | ||
249 | * Address: 0xa0 | ||
250 | * SCT: no | ||
251 | */ | ||
252 | #define HW_EMI_DDR_TEST_MODE_STATUS1 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0)) | ||
253 | #define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1 13 | ||
254 | #define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1 0xffffe000 | ||
255 | #define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v) (((v) << 13) & 0xffffe000) | ||
256 | #define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0 | ||
257 | #define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x1fff | ||
258 | #define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) (((v) << 0) & 0x1fff) | ||
259 | |||
260 | /** | ||
261 | * Register: HW_EMI_DDR_TEST_MODE_STATUS2 | ||
262 | * Address: 0xb0 | ||
263 | * SCT: no | ||
264 | */ | ||
265 | #define HW_EMI_DDR_TEST_MODE_STATUS2 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0)) | ||
266 | #define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0 | ||
267 | #define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xffffffff | ||
268 | #define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (((v) << 0) & 0xffffffff) | ||
269 | |||
270 | /** | ||
271 | * Register: HW_EMI_DDR_TEST_MODE_STATUS3 | ||
272 | * Address: 0xc0 | ||
273 | * SCT: no | ||
274 | */ | ||
275 | #define HW_EMI_DDR_TEST_MODE_STATUS3 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0)) | ||
276 | #define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0 | ||
277 | #define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xffffffff | ||
278 | #define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (((v) << 0) & 0xffffffff) | ||
279 | |||
280 | /** | ||
281 | * Register: HW_EMI_VERSION | ||
282 | * Address: 0xf0 | ||
283 | * SCT: no | ||
284 | */ | ||
285 | #define HW_EMI_VERSION (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0)) | ||
286 | #define BP_EMI_VERSION_MAJOR 24 | ||
287 | #define BM_EMI_VERSION_MAJOR 0xff000000 | ||
288 | #define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
289 | #define BP_EMI_VERSION_MINOR 16 | ||
290 | #define BM_EMI_VERSION_MINOR 0xff0000 | ||
291 | #define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
292 | #define BP_EMI_VERSION_STEP 0 | ||
293 | #define BM_EMI_VERSION_STEP 0xffff | ||
294 | #define BF_EMI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
295 | |||
296 | #endif /* __HEADERGEN__IMX233__EMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h b/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h new file mode 100644 index 0000000000..895057db69 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h | |||
@@ -0,0 +1,561 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__GPMI__H__ | ||
24 | #define __HEADERGEN__IMX233__GPMI__H__ | ||
25 | |||
26 | #define REGS_GPMI_BASE (0x8000c000) | ||
27 | |||
28 | #define REGS_GPMI_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_GPMI_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_GPMI_CTRL0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_GPMI_CTRL0_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_GPMI_CTRL0_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_GPMI_CTRL0_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_GPMI_CTRL0_SFTRST 31 | ||
40 | #define BM_GPMI_CTRL0_SFTRST 0x80000000 | ||
41 | #define BV_GPMI_CTRL0_SFTRST__RUN 0x0 | ||
42 | #define BV_GPMI_CTRL0_SFTRST__RESET 0x1 | ||
43 | #define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_GPMI_CTRL0_SFTRST_V(v) ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_GPMI_CTRL0_CLKGATE 30 | ||
46 | #define BM_GPMI_CTRL0_CLKGATE 0x40000000 | ||
47 | #define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 | ||
48 | #define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_GPMI_CTRL0_CLKGATE_V(v) ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_GPMI_CTRL0_RUN 29 | ||
52 | #define BM_GPMI_CTRL0_RUN 0x20000000 | ||
53 | #define BV_GPMI_CTRL0_RUN__IDLE 0x0 | ||
54 | #define BV_GPMI_CTRL0_RUN__BUSY 0x1 | ||
55 | #define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_GPMI_CTRL0_RUN_V(v) ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000) | ||
57 | #define BP_GPMI_CTRL0_DEV_IRQ_EN 28 | ||
58 | #define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 | ||
59 | #define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
60 | #define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27 | ||
61 | #define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x8000000 | ||
62 | #define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & 0x8000000) | ||
63 | #define BP_GPMI_CTRL0_UDMA 26 | ||
64 | #define BM_GPMI_CTRL0_UDMA 0x4000000 | ||
65 | #define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 | ||
66 | #define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 | ||
67 | #define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & 0x4000000) | ||
68 | #define BF_GPMI_CTRL0_UDMA_V(v) ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000) | ||
69 | #define BP_GPMI_CTRL0_COMMAND_MODE 24 | ||
70 | #define BM_GPMI_CTRL0_COMMAND_MODE 0x3000000 | ||
71 | #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 | ||
72 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 | ||
73 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 | ||
74 | #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 | ||
75 | #define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & 0x3000000) | ||
76 | #define BF_GPMI_CTRL0_COMMAND_MODE_V(v) ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000) | ||
77 | #define BP_GPMI_CTRL0_WORD_LENGTH 23 | ||
78 | #define BM_GPMI_CTRL0_WORD_LENGTH 0x800000 | ||
79 | #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 | ||
80 | #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 | ||
81 | #define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & 0x800000) | ||
82 | #define BF_GPMI_CTRL0_WORD_LENGTH_V(v) ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000) | ||
83 | #define BP_GPMI_CTRL0_LOCK_CS 22 | ||
84 | #define BM_GPMI_CTRL0_LOCK_CS 0x400000 | ||
85 | #define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 | ||
86 | #define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 | ||
87 | #define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & 0x400000) | ||
88 | #define BF_GPMI_CTRL0_LOCK_CS_V(v) ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000) | ||
89 | #define BP_GPMI_CTRL0_CS 20 | ||
90 | #define BM_GPMI_CTRL0_CS 0x300000 | ||
91 | #define BF_GPMI_CTRL0_CS(v) (((v) << 20) & 0x300000) | ||
92 | #define BP_GPMI_CTRL0_ADDRESS 17 | ||
93 | #define BM_GPMI_CTRL0_ADDRESS 0xe0000 | ||
94 | #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 | ||
95 | #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 | ||
96 | #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 | ||
97 | #define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & 0xe0000) | ||
98 | #define BF_GPMI_CTRL0_ADDRESS_V(v) ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000) | ||
99 | #define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 | ||
100 | #define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x10000 | ||
101 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 | ||
102 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 | ||
103 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & 0x10000) | ||
104 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000) | ||
105 | #define BP_GPMI_CTRL0_XFER_COUNT 0 | ||
106 | #define BM_GPMI_CTRL0_XFER_COUNT 0xffff | ||
107 | #define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_GPMI_COMPARE | ||
111 | * Address: 0x10 | ||
112 | * SCT: no | ||
113 | */ | ||
114 | #define HW_GPMI_COMPARE (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10)) | ||
115 | #define BP_GPMI_COMPARE_MASK 16 | ||
116 | #define BM_GPMI_COMPARE_MASK 0xffff0000 | ||
117 | #define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & 0xffff0000) | ||
118 | #define BP_GPMI_COMPARE_REFERENCE 0 | ||
119 | #define BM_GPMI_COMPARE_REFERENCE 0xffff | ||
120 | #define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & 0xffff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_GPMI_ECCCTRL | ||
124 | * Address: 0x20 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_GPMI_ECCCTRL (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0)) | ||
128 | #define HW_GPMI_ECCCTRL_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4)) | ||
129 | #define HW_GPMI_ECCCTRL_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8)) | ||
130 | #define HW_GPMI_ECCCTRL_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc)) | ||
131 | #define BP_GPMI_ECCCTRL_HANDLE 16 | ||
132 | #define BM_GPMI_ECCCTRL_HANDLE 0xffff0000 | ||
133 | #define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & 0xffff0000) | ||
134 | #define BP_GPMI_ECCCTRL_RSVD2 15 | ||
135 | #define BM_GPMI_ECCCTRL_RSVD2 0x8000 | ||
136 | #define BF_GPMI_ECCCTRL_RSVD2(v) (((v) << 15) & 0x8000) | ||
137 | #define BP_GPMI_ECCCTRL_ECC_CMD 13 | ||
138 | #define BM_GPMI_ECCCTRL_ECC_CMD 0x6000 | ||
139 | #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 | ||
140 | #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 | ||
141 | #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 | ||
142 | #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 | ||
143 | #define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & 0x6000) | ||
144 | #define BF_GPMI_ECCCTRL_ECC_CMD_V(v) ((BV_GPMI_ECCCTRL_ECC_CMD__##v << 13) & 0x6000) | ||
145 | #define BP_GPMI_ECCCTRL_ENABLE_ECC 12 | ||
146 | #define BM_GPMI_ECCCTRL_ENABLE_ECC 0x1000 | ||
147 | #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 | ||
148 | #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 | ||
149 | #define BF_GPMI_ECCCTRL_ENABLE_ECC(v) (((v) << 12) & 0x1000) | ||
150 | #define BF_GPMI_ECCCTRL_ENABLE_ECC_V(v) ((BV_GPMI_ECCCTRL_ENABLE_ECC__##v << 12) & 0x1000) | ||
151 | #define BP_GPMI_ECCCTRL_RSVD1 9 | ||
152 | #define BM_GPMI_ECCCTRL_RSVD1 0xe00 | ||
153 | #define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & 0xe00) | ||
154 | #define BP_GPMI_ECCCTRL_BUFFER_MASK 0 | ||
155 | #define BM_GPMI_ECCCTRL_BUFFER_MASK 0x1ff | ||
156 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 | ||
157 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1ff | ||
158 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 | ||
159 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x80 | ||
160 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x40 | ||
161 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x20 | ||
162 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x10 | ||
163 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x8 | ||
164 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x4 | ||
165 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x2 | ||
166 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x1 | ||
167 | #define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & 0x1ff) | ||
168 | #define BF_GPMI_ECCCTRL_BUFFER_MASK_V(v) ((BV_GPMI_ECCCTRL_BUFFER_MASK__##v << 0) & 0x1ff) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_GPMI_ECCCOUNT | ||
172 | * Address: 0x30 | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_GPMI_ECCCOUNT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30)) | ||
176 | #define BP_GPMI_ECCCOUNT_RSVD2 16 | ||
177 | #define BM_GPMI_ECCCOUNT_RSVD2 0xffff0000 | ||
178 | #define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & 0xffff0000) | ||
179 | #define BP_GPMI_ECCCOUNT_COUNT 0 | ||
180 | #define BM_GPMI_ECCCOUNT_COUNT 0xffff | ||
181 | #define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & 0xffff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_GPMI_PAYLOAD | ||
185 | * Address: 0x40 | ||
186 | * SCT: no | ||
187 | */ | ||
188 | #define HW_GPMI_PAYLOAD (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40)) | ||
189 | #define BP_GPMI_PAYLOAD_ADDRESS 2 | ||
190 | #define BM_GPMI_PAYLOAD_ADDRESS 0xfffffffc | ||
191 | #define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
192 | #define BP_GPMI_PAYLOAD_RSVD0 0 | ||
193 | #define BM_GPMI_PAYLOAD_RSVD0 0x3 | ||
194 | #define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & 0x3) | ||
195 | |||
196 | /** | ||
197 | * Register: HW_GPMI_AUXILIARY | ||
198 | * Address: 0x50 | ||
199 | * SCT: no | ||
200 | */ | ||
201 | #define HW_GPMI_AUXILIARY (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50)) | ||
202 | #define BP_GPMI_AUXILIARY_ADDRESS 2 | ||
203 | #define BM_GPMI_AUXILIARY_ADDRESS 0xfffffffc | ||
204 | #define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
205 | #define BP_GPMI_AUXILIARY_RSVD0 0 | ||
206 | #define BM_GPMI_AUXILIARY_RSVD0 0x3 | ||
207 | #define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & 0x3) | ||
208 | |||
209 | /** | ||
210 | * Register: HW_GPMI_CTRL1 | ||
211 | * Address: 0x60 | ||
212 | * SCT: yes | ||
213 | */ | ||
214 | #define HW_GPMI_CTRL1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x0)) | ||
215 | #define HW_GPMI_CTRL1_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x4)) | ||
216 | #define HW_GPMI_CTRL1_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x8)) | ||
217 | #define HW_GPMI_CTRL1_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0xc)) | ||
218 | #define BP_GPMI_CTRL1_RSVD2 24 | ||
219 | #define BM_GPMI_CTRL1_RSVD2 0xff000000 | ||
220 | #define BF_GPMI_CTRL1_RSVD2(v) (((v) << 24) & 0xff000000) | ||
221 | #define BP_GPMI_CTRL1_CE3_SEL 23 | ||
222 | #define BM_GPMI_CTRL1_CE3_SEL 0x800000 | ||
223 | #define BF_GPMI_CTRL1_CE3_SEL(v) (((v) << 23) & 0x800000) | ||
224 | #define BP_GPMI_CTRL1_CE2_SEL 22 | ||
225 | #define BM_GPMI_CTRL1_CE2_SEL 0x400000 | ||
226 | #define BF_GPMI_CTRL1_CE2_SEL(v) (((v) << 22) & 0x400000) | ||
227 | #define BP_GPMI_CTRL1_CE1_SEL 21 | ||
228 | #define BM_GPMI_CTRL1_CE1_SEL 0x200000 | ||
229 | #define BF_GPMI_CTRL1_CE1_SEL(v) (((v) << 21) & 0x200000) | ||
230 | #define BP_GPMI_CTRL1_CE0_SEL 20 | ||
231 | #define BM_GPMI_CTRL1_CE0_SEL 0x100000 | ||
232 | #define BF_GPMI_CTRL1_CE0_SEL(v) (((v) << 20) & 0x100000) | ||
233 | #define BP_GPMI_CTRL1_GANGED_RDYBUSY 19 | ||
234 | #define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x80000 | ||
235 | #define BF_GPMI_CTRL1_GANGED_RDYBUSY(v) (((v) << 19) & 0x80000) | ||
236 | #define BP_GPMI_CTRL1_BCH_MODE 18 | ||
237 | #define BM_GPMI_CTRL1_BCH_MODE 0x40000 | ||
238 | #define BF_GPMI_CTRL1_BCH_MODE(v) (((v) << 18) & 0x40000) | ||
239 | #define BP_GPMI_CTRL1_DLL_ENABLE 17 | ||
240 | #define BM_GPMI_CTRL1_DLL_ENABLE 0x20000 | ||
241 | #define BF_GPMI_CTRL1_DLL_ENABLE(v) (((v) << 17) & 0x20000) | ||
242 | #define BP_GPMI_CTRL1_HALF_PERIOD 16 | ||
243 | #define BM_GPMI_CTRL1_HALF_PERIOD 0x10000 | ||
244 | #define BF_GPMI_CTRL1_HALF_PERIOD(v) (((v) << 16) & 0x10000) | ||
245 | #define BP_GPMI_CTRL1_RDN_DELAY 12 | ||
246 | #define BM_GPMI_CTRL1_RDN_DELAY 0xf000 | ||
247 | #define BF_GPMI_CTRL1_RDN_DELAY(v) (((v) << 12) & 0xf000) | ||
248 | #define BP_GPMI_CTRL1_DMA2ECC_MODE 11 | ||
249 | #define BM_GPMI_CTRL1_DMA2ECC_MODE 0x800 | ||
250 | #define BF_GPMI_CTRL1_DMA2ECC_MODE(v) (((v) << 11) & 0x800) | ||
251 | #define BP_GPMI_CTRL1_DEV_IRQ 10 | ||
252 | #define BM_GPMI_CTRL1_DEV_IRQ 0x400 | ||
253 | #define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & 0x400) | ||
254 | #define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 | ||
255 | #define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x200 | ||
256 | #define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & 0x200) | ||
257 | #define BP_GPMI_CTRL1_BURST_EN 8 | ||
258 | #define BM_GPMI_CTRL1_BURST_EN 0x100 | ||
259 | #define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & 0x100) | ||
260 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7 | ||
261 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x80 | ||
262 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & 0x80) | ||
263 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6 | ||
264 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x40 | ||
265 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & 0x40) | ||
266 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5 | ||
267 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x20 | ||
268 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & 0x20) | ||
269 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4 | ||
270 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x10 | ||
271 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & 0x10) | ||
272 | #define BP_GPMI_CTRL1_DEV_RESET 3 | ||
273 | #define BM_GPMI_CTRL1_DEV_RESET 0x8 | ||
274 | #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 | ||
275 | #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 | ||
276 | #define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & 0x8) | ||
277 | #define BF_GPMI_CTRL1_DEV_RESET_V(v) ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8) | ||
278 | #define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 | ||
279 | #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x4 | ||
280 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 | ||
281 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 | ||
282 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & 0x4) | ||
283 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v) ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4) | ||
284 | #define BP_GPMI_CTRL1_CAMERA_MODE 1 | ||
285 | #define BM_GPMI_CTRL1_CAMERA_MODE 0x2 | ||
286 | #define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & 0x2) | ||
287 | #define BP_GPMI_CTRL1_GPMI_MODE 0 | ||
288 | #define BM_GPMI_CTRL1_GPMI_MODE 0x1 | ||
289 | #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 | ||
290 | #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 | ||
291 | #define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & 0x1) | ||
292 | #define BF_GPMI_CTRL1_GPMI_MODE_V(v) ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1) | ||
293 | |||
294 | /** | ||
295 | * Register: HW_GPMI_TIMING0 | ||
296 | * Address: 0x70 | ||
297 | * SCT: no | ||
298 | */ | ||
299 | #define HW_GPMI_TIMING0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70)) | ||
300 | #define BP_GPMI_TIMING0_RSVD1 24 | ||
301 | #define BM_GPMI_TIMING0_RSVD1 0xff000000 | ||
302 | #define BF_GPMI_TIMING0_RSVD1(v) (((v) << 24) & 0xff000000) | ||
303 | #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 | ||
304 | #define BM_GPMI_TIMING0_ADDRESS_SETUP 0xff0000 | ||
305 | #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & 0xff0000) | ||
306 | #define BP_GPMI_TIMING0_DATA_HOLD 8 | ||
307 | #define BM_GPMI_TIMING0_DATA_HOLD 0xff00 | ||
308 | #define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
309 | #define BP_GPMI_TIMING0_DATA_SETUP 0 | ||
310 | #define BM_GPMI_TIMING0_DATA_SETUP 0xff | ||
311 | #define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
312 | |||
313 | /** | ||
314 | * Register: HW_GPMI_TIMING1 | ||
315 | * Address: 0x80 | ||
316 | * SCT: no | ||
317 | */ | ||
318 | #define HW_GPMI_TIMING1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80)) | ||
319 | #define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 | ||
320 | #define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xffff0000 | ||
321 | #define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
322 | #define BP_GPMI_TIMING1_RSVD1 0 | ||
323 | #define BM_GPMI_TIMING1_RSVD1 0xffff | ||
324 | #define BF_GPMI_TIMING1_RSVD1(v) (((v) << 0) & 0xffff) | ||
325 | |||
326 | /** | ||
327 | * Register: HW_GPMI_TIMING2 | ||
328 | * Address: 0x90 | ||
329 | * SCT: no | ||
330 | */ | ||
331 | #define HW_GPMI_TIMING2 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x90)) | ||
332 | #define BP_GPMI_TIMING2_UDMA_TRP 24 | ||
333 | #define BM_GPMI_TIMING2_UDMA_TRP 0xff000000 | ||
334 | #define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & 0xff000000) | ||
335 | #define BP_GPMI_TIMING2_UDMA_ENV 16 | ||
336 | #define BM_GPMI_TIMING2_UDMA_ENV 0xff0000 | ||
337 | #define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & 0xff0000) | ||
338 | #define BP_GPMI_TIMING2_UDMA_HOLD 8 | ||
339 | #define BM_GPMI_TIMING2_UDMA_HOLD 0xff00 | ||
340 | #define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & 0xff00) | ||
341 | #define BP_GPMI_TIMING2_UDMA_SETUP 0 | ||
342 | #define BM_GPMI_TIMING2_UDMA_SETUP 0xff | ||
343 | #define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & 0xff) | ||
344 | |||
345 | /** | ||
346 | * Register: HW_GPMI_DATA | ||
347 | * Address: 0xa0 | ||
348 | * SCT: no | ||
349 | */ | ||
350 | #define HW_GPMI_DATA (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xa0)) | ||
351 | #define BP_GPMI_DATA_DATA 0 | ||
352 | #define BM_GPMI_DATA_DATA 0xffffffff | ||
353 | #define BF_GPMI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
354 | |||
355 | /** | ||
356 | * Register: HW_GPMI_STAT | ||
357 | * Address: 0xb0 | ||
358 | * SCT: no | ||
359 | */ | ||
360 | #define HW_GPMI_STAT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xb0)) | ||
361 | #define BP_GPMI_STAT_PRESENT 31 | ||
362 | #define BM_GPMI_STAT_PRESENT 0x80000000 | ||
363 | #define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 | ||
364 | #define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 | ||
365 | #define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
366 | #define BF_GPMI_STAT_PRESENT_V(v) ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000) | ||
367 | #define BP_GPMI_STAT_RSVD1 12 | ||
368 | #define BM_GPMI_STAT_RSVD1 0x7ffff000 | ||
369 | #define BF_GPMI_STAT_RSVD1(v) (((v) << 12) & 0x7ffff000) | ||
370 | #define BP_GPMI_STAT_RDY_TIMEOUT 8 | ||
371 | #define BM_GPMI_STAT_RDY_TIMEOUT 0xf00 | ||
372 | #define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & 0xf00) | ||
373 | #define BP_GPMI_STAT_ATA_IRQ 7 | ||
374 | #define BM_GPMI_STAT_ATA_IRQ 0x80 | ||
375 | #define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & 0x80) | ||
376 | #define BP_GPMI_STAT_INVALID_BUFFER_MASK 6 | ||
377 | #define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x40 | ||
378 | #define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & 0x40) | ||
379 | #define BP_GPMI_STAT_FIFO_EMPTY 5 | ||
380 | #define BM_GPMI_STAT_FIFO_EMPTY 0x20 | ||
381 | #define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 | ||
382 | #define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 | ||
383 | #define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
384 | #define BF_GPMI_STAT_FIFO_EMPTY_V(v) ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20) | ||
385 | #define BP_GPMI_STAT_FIFO_FULL 4 | ||
386 | #define BM_GPMI_STAT_FIFO_FULL 0x10 | ||
387 | #define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 | ||
388 | #define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 | ||
389 | #define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & 0x10) | ||
390 | #define BF_GPMI_STAT_FIFO_FULL_V(v) ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10) | ||
391 | #define BP_GPMI_STAT_DEV3_ERROR 3 | ||
392 | #define BM_GPMI_STAT_DEV3_ERROR 0x8 | ||
393 | #define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & 0x8) | ||
394 | #define BP_GPMI_STAT_DEV2_ERROR 2 | ||
395 | #define BM_GPMI_STAT_DEV2_ERROR 0x4 | ||
396 | #define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & 0x4) | ||
397 | #define BP_GPMI_STAT_DEV1_ERROR 1 | ||
398 | #define BM_GPMI_STAT_DEV1_ERROR 0x2 | ||
399 | #define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & 0x2) | ||
400 | #define BP_GPMI_STAT_DEV0_ERROR 0 | ||
401 | #define BM_GPMI_STAT_DEV0_ERROR 0x1 | ||
402 | #define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & 0x1) | ||
403 | |||
404 | /** | ||
405 | * Register: HW_GPMI_DEBUG | ||
406 | * Address: 0xc0 | ||
407 | * SCT: no | ||
408 | */ | ||
409 | #define HW_GPMI_DEBUG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xc0)) | ||
410 | #define BP_GPMI_DEBUG_READY3 31 | ||
411 | #define BM_GPMI_DEBUG_READY3 0x80000000 | ||
412 | #define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & 0x80000000) | ||
413 | #define BP_GPMI_DEBUG_READY2 30 | ||
414 | #define BM_GPMI_DEBUG_READY2 0x40000000 | ||
415 | #define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & 0x40000000) | ||
416 | #define BP_GPMI_DEBUG_READY1 29 | ||
417 | #define BM_GPMI_DEBUG_READY1 0x20000000 | ||
418 | #define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & 0x20000000) | ||
419 | #define BP_GPMI_DEBUG_READY0 28 | ||
420 | #define BM_GPMI_DEBUG_READY0 0x10000000 | ||
421 | #define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & 0x10000000) | ||
422 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27 | ||
423 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x8000000 | ||
424 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & 0x8000000) | ||
425 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26 | ||
426 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x4000000 | ||
427 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & 0x4000000) | ||
428 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25 | ||
429 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x2000000 | ||
430 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & 0x2000000) | ||
431 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24 | ||
432 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x1000000 | ||
433 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & 0x1000000) | ||
434 | #define BP_GPMI_DEBUG_SENSE3 23 | ||
435 | #define BM_GPMI_DEBUG_SENSE3 0x800000 | ||
436 | #define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & 0x800000) | ||
437 | #define BP_GPMI_DEBUG_SENSE2 22 | ||
438 | #define BM_GPMI_DEBUG_SENSE2 0x400000 | ||
439 | #define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & 0x400000) | ||
440 | #define BP_GPMI_DEBUG_SENSE1 21 | ||
441 | #define BM_GPMI_DEBUG_SENSE1 0x200000 | ||
442 | #define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & 0x200000) | ||
443 | #define BP_GPMI_DEBUG_SENSE0 20 | ||
444 | #define BM_GPMI_DEBUG_SENSE0 0x100000 | ||
445 | #define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & 0x100000) | ||
446 | #define BP_GPMI_DEBUG_DMAREQ3 19 | ||
447 | #define BM_GPMI_DEBUG_DMAREQ3 0x80000 | ||
448 | #define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & 0x80000) | ||
449 | #define BP_GPMI_DEBUG_DMAREQ2 18 | ||
450 | #define BM_GPMI_DEBUG_DMAREQ2 0x40000 | ||
451 | #define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & 0x40000) | ||
452 | #define BP_GPMI_DEBUG_DMAREQ1 17 | ||
453 | #define BM_GPMI_DEBUG_DMAREQ1 0x20000 | ||
454 | #define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & 0x20000) | ||
455 | #define BP_GPMI_DEBUG_DMAREQ0 16 | ||
456 | #define BM_GPMI_DEBUG_DMAREQ0 0x10000 | ||
457 | #define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & 0x10000) | ||
458 | #define BP_GPMI_DEBUG_CMD_END 12 | ||
459 | #define BM_GPMI_DEBUG_CMD_END 0xf000 | ||
460 | #define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & 0xf000) | ||
461 | #define BP_GPMI_DEBUG_UDMA_STATE 8 | ||
462 | #define BM_GPMI_DEBUG_UDMA_STATE 0xf00 | ||
463 | #define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & 0xf00) | ||
464 | #define BP_GPMI_DEBUG_BUSY 7 | ||
465 | #define BM_GPMI_DEBUG_BUSY 0x80 | ||
466 | #define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 | ||
467 | #define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 | ||
468 | #define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & 0x80) | ||
469 | #define BF_GPMI_DEBUG_BUSY_V(v) ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80) | ||
470 | #define BP_GPMI_DEBUG_PIN_STATE 4 | ||
471 | #define BM_GPMI_DEBUG_PIN_STATE 0x70 | ||
472 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 | ||
473 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 | ||
474 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 | ||
475 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 | ||
476 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 | ||
477 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 | ||
478 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 | ||
479 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 | ||
480 | #define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & 0x70) | ||
481 | #define BF_GPMI_DEBUG_PIN_STATE_V(v) ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70) | ||
482 | #define BP_GPMI_DEBUG_MAIN_STATE 0 | ||
483 | #define BM_GPMI_DEBUG_MAIN_STATE 0xf | ||
484 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 | ||
485 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 | ||
486 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 | ||
487 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 | ||
488 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 | ||
489 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 | ||
490 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 | ||
491 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 | ||
492 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 | ||
493 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 | ||
494 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xa | ||
495 | #define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & 0xf) | ||
496 | #define BF_GPMI_DEBUG_MAIN_STATE_V(v) ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_GPMI_VERSION | ||
500 | * Address: 0xd0 | ||
501 | * SCT: no | ||
502 | */ | ||
503 | #define HW_GPMI_VERSION (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xd0)) | ||
504 | #define BP_GPMI_VERSION_MAJOR 24 | ||
505 | #define BM_GPMI_VERSION_MAJOR 0xff000000 | ||
506 | #define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
507 | #define BP_GPMI_VERSION_MINOR 16 | ||
508 | #define BM_GPMI_VERSION_MINOR 0xff0000 | ||
509 | #define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
510 | #define BP_GPMI_VERSION_STEP 0 | ||
511 | #define BM_GPMI_VERSION_STEP 0xffff | ||
512 | #define BF_GPMI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
513 | |||
514 | /** | ||
515 | * Register: HW_GPMI_DEBUG2 | ||
516 | * Address: 0xe0 | ||
517 | * SCT: no | ||
518 | */ | ||
519 | #define HW_GPMI_DEBUG2 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xe0)) | ||
520 | #define BP_GPMI_DEBUG2_RSVD1 16 | ||
521 | #define BM_GPMI_DEBUG2_RSVD1 0xffff0000 | ||
522 | #define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 16) & 0xffff0000) | ||
523 | #define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 | ||
524 | #define BM_GPMI_DEBUG2_SYND2GPMI_BE 0xf000 | ||
525 | #define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) (((v) << 12) & 0xf000) | ||
526 | #define BP_GPMI_DEBUG2_GPMI2SYND_VALID 11 | ||
527 | #define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x800 | ||
528 | #define BF_GPMI_DEBUG2_GPMI2SYND_VALID(v) (((v) << 11) & 0x800) | ||
529 | #define BP_GPMI_DEBUG2_GPMI2SYND_READY 10 | ||
530 | #define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x400 | ||
531 | #define BF_GPMI_DEBUG2_GPMI2SYND_READY(v) (((v) << 10) & 0x400) | ||
532 | #define BP_GPMI_DEBUG2_SYND2GPMI_VALID 9 | ||
533 | #define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x200 | ||
534 | #define BF_GPMI_DEBUG2_SYND2GPMI_VALID(v) (((v) << 9) & 0x200) | ||
535 | #define BP_GPMI_DEBUG2_SYND2GPMI_READY 8 | ||
536 | #define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x100 | ||
537 | #define BF_GPMI_DEBUG2_SYND2GPMI_READY(v) (((v) << 8) & 0x100) | ||
538 | #define BP_GPMI_DEBUG2_VIEW_DELAYED_RDN 7 | ||
539 | #define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x80 | ||
540 | #define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(v) (((v) << 7) & 0x80) | ||
541 | #define BP_GPMI_DEBUG2_UPDATE_WINDOW 6 | ||
542 | #define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x40 | ||
543 | #define BF_GPMI_DEBUG2_UPDATE_WINDOW(v) (((v) << 6) & 0x40) | ||
544 | #define BP_GPMI_DEBUG2_RDN_TAP 0 | ||
545 | #define BM_GPMI_DEBUG2_RDN_TAP 0x3f | ||
546 | #define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & 0x3f) | ||
547 | |||
548 | /** | ||
549 | * Register: HW_GPMI_DEBUG3 | ||
550 | * Address: 0xf0 | ||
551 | * SCT: no | ||
552 | */ | ||
553 | #define HW_GPMI_DEBUG3 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xf0)) | ||
554 | #define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 | ||
555 | #define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xffff0000 | ||
556 | #define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << 16) & 0xffff0000) | ||
557 | #define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 | ||
558 | #define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0xffff | ||
559 | #define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << 0) & 0xffff) | ||
560 | |||
561 | #endif /* __HEADERGEN__IMX233__GPMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-i2c.h b/firmware/target/arm/imx233/regs/imx233/regs-i2c.h new file mode 100644 index 0000000000..593a3ed04b --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-i2c.h | |||
@@ -0,0 +1,597 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__I2C__H__ | ||
24 | #define __HEADERGEN__IMX233__I2C__H__ | ||
25 | |||
26 | #define REGS_I2C_BASE (0x80058000) | ||
27 | |||
28 | #define REGS_I2C_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_I2C_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_I2C_CTRL0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0)) | ||
36 | #define HW_I2C_CTRL0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4)) | ||
37 | #define HW_I2C_CTRL0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8)) | ||
38 | #define HW_I2C_CTRL0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc)) | ||
39 | #define BP_I2C_CTRL0_SFTRST 31 | ||
40 | #define BM_I2C_CTRL0_SFTRST 0x80000000 | ||
41 | #define BV_I2C_CTRL0_SFTRST__RUN 0x0 | ||
42 | #define BV_I2C_CTRL0_SFTRST__RESET 0x1 | ||
43 | #define BF_I2C_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_I2C_CTRL0_SFTRST_V(v) ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_I2C_CTRL0_CLKGATE 30 | ||
46 | #define BM_I2C_CTRL0_CLKGATE 0x40000000 | ||
47 | #define BV_I2C_CTRL0_CLKGATE__RUN 0x0 | ||
48 | #define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_I2C_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_I2C_CTRL0_CLKGATE_V(v) ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_I2C_CTRL0_RUN 29 | ||
52 | #define BM_I2C_CTRL0_RUN 0x20000000 | ||
53 | #define BV_I2C_CTRL0_RUN__HALT 0x0 | ||
54 | #define BV_I2C_CTRL0_RUN__RUN 0x1 | ||
55 | #define BF_I2C_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_I2C_CTRL0_RUN_V(v) ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000) | ||
57 | #define BP_I2C_CTRL0_RSVD1 28 | ||
58 | #define BM_I2C_CTRL0_RSVD1 0x10000000 | ||
59 | #define BF_I2C_CTRL0_RSVD1(v) (((v) << 28) & 0x10000000) | ||
60 | #define BP_I2C_CTRL0_PRE_ACK 27 | ||
61 | #define BM_I2C_CTRL0_PRE_ACK 0x8000000 | ||
62 | #define BF_I2C_CTRL0_PRE_ACK(v) (((v) << 27) & 0x8000000) | ||
63 | #define BP_I2C_CTRL0_ACKNOWLEDGE 26 | ||
64 | #define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000 | ||
65 | #define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 | ||
66 | #define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 | ||
67 | #define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) << 26) & 0x4000000) | ||
68 | #define BF_I2C_CTRL0_ACKNOWLEDGE_V(v) ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000) | ||
69 | #define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25 | ||
70 | #define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000 | ||
71 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 | ||
72 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 | ||
73 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) << 25) & 0x2000000) | ||
74 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000) | ||
75 | #define BP_I2C_CTRL0_PIO_MODE 24 | ||
76 | #define BM_I2C_CTRL0_PIO_MODE 0x1000000 | ||
77 | #define BF_I2C_CTRL0_PIO_MODE(v) (((v) << 24) & 0x1000000) | ||
78 | #define BP_I2C_CTRL0_MULTI_MASTER 23 | ||
79 | #define BM_I2C_CTRL0_MULTI_MASTER 0x800000 | ||
80 | #define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 | ||
81 | #define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 | ||
82 | #define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) << 23) & 0x800000) | ||
83 | #define BF_I2C_CTRL0_MULTI_MASTER_V(v) ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000) | ||
84 | #define BP_I2C_CTRL0_CLOCK_HELD 22 | ||
85 | #define BM_I2C_CTRL0_CLOCK_HELD 0x400000 | ||
86 | #define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 | ||
87 | #define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 | ||
88 | #define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) << 22) & 0x400000) | ||
89 | #define BF_I2C_CTRL0_CLOCK_HELD_V(v) ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000) | ||
90 | #define BP_I2C_CTRL0_RETAIN_CLOCK 21 | ||
91 | #define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000 | ||
92 | #define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 | ||
93 | #define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 | ||
94 | #define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) << 21) & 0x200000) | ||
95 | #define BF_I2C_CTRL0_RETAIN_CLOCK_V(v) ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000) | ||
96 | #define BP_I2C_CTRL0_POST_SEND_STOP 20 | ||
97 | #define BM_I2C_CTRL0_POST_SEND_STOP 0x100000 | ||
98 | #define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 | ||
99 | #define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 | ||
100 | #define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) << 20) & 0x100000) | ||
101 | #define BF_I2C_CTRL0_POST_SEND_STOP_V(v) ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000) | ||
102 | #define BP_I2C_CTRL0_PRE_SEND_START 19 | ||
103 | #define BM_I2C_CTRL0_PRE_SEND_START 0x80000 | ||
104 | #define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 | ||
105 | #define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 | ||
106 | #define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) << 19) & 0x80000) | ||
107 | #define BF_I2C_CTRL0_PRE_SEND_START_V(v) ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000) | ||
108 | #define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18 | ||
109 | #define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000 | ||
110 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 | ||
111 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 | ||
112 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) << 18) & 0x40000) | ||
113 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000) | ||
114 | #define BP_I2C_CTRL0_MASTER_MODE 17 | ||
115 | #define BM_I2C_CTRL0_MASTER_MODE 0x20000 | ||
116 | #define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 | ||
117 | #define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 | ||
118 | #define BF_I2C_CTRL0_MASTER_MODE(v) (((v) << 17) & 0x20000) | ||
119 | #define BF_I2C_CTRL0_MASTER_MODE_V(v) ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000) | ||
120 | #define BP_I2C_CTRL0_DIRECTION 16 | ||
121 | #define BM_I2C_CTRL0_DIRECTION 0x10000 | ||
122 | #define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 | ||
123 | #define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 | ||
124 | #define BF_I2C_CTRL0_DIRECTION(v) (((v) << 16) & 0x10000) | ||
125 | #define BF_I2C_CTRL0_DIRECTION_V(v) ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000) | ||
126 | #define BP_I2C_CTRL0_XFER_COUNT 0 | ||
127 | #define BM_I2C_CTRL0_XFER_COUNT 0xffff | ||
128 | #define BF_I2C_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
129 | |||
130 | /** | ||
131 | * Register: HW_I2C_TIMING0 | ||
132 | * Address: 0x10 | ||
133 | * SCT: yes | ||
134 | */ | ||
135 | #define HW_I2C_TIMING0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0)) | ||
136 | #define HW_I2C_TIMING0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4)) | ||
137 | #define HW_I2C_TIMING0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8)) | ||
138 | #define HW_I2C_TIMING0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc)) | ||
139 | #define BP_I2C_TIMING0_RSVD2 26 | ||
140 | #define BM_I2C_TIMING0_RSVD2 0xfc000000 | ||
141 | #define BF_I2C_TIMING0_RSVD2(v) (((v) << 26) & 0xfc000000) | ||
142 | #define BP_I2C_TIMING0_HIGH_COUNT 16 | ||
143 | #define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000 | ||
144 | #define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
145 | #define BP_I2C_TIMING0_RSVD1 10 | ||
146 | #define BM_I2C_TIMING0_RSVD1 0xfc00 | ||
147 | #define BF_I2C_TIMING0_RSVD1(v) (((v) << 10) & 0xfc00) | ||
148 | #define BP_I2C_TIMING0_RCV_COUNT 0 | ||
149 | #define BM_I2C_TIMING0_RCV_COUNT 0x3ff | ||
150 | #define BF_I2C_TIMING0_RCV_COUNT(v) (((v) << 0) & 0x3ff) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_I2C_TIMING1 | ||
154 | * Address: 0x20 | ||
155 | * SCT: yes | ||
156 | */ | ||
157 | #define HW_I2C_TIMING1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0)) | ||
158 | #define HW_I2C_TIMING1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4)) | ||
159 | #define HW_I2C_TIMING1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8)) | ||
160 | #define HW_I2C_TIMING1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc)) | ||
161 | #define BP_I2C_TIMING1_RSVD2 26 | ||
162 | #define BM_I2C_TIMING1_RSVD2 0xfc000000 | ||
163 | #define BF_I2C_TIMING1_RSVD2(v) (((v) << 26) & 0xfc000000) | ||
164 | #define BP_I2C_TIMING1_LOW_COUNT 16 | ||
165 | #define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000 | ||
166 | #define BF_I2C_TIMING1_LOW_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
167 | #define BP_I2C_TIMING1_RSVD1 10 | ||
168 | #define BM_I2C_TIMING1_RSVD1 0xfc00 | ||
169 | #define BF_I2C_TIMING1_RSVD1(v) (((v) << 10) & 0xfc00) | ||
170 | #define BP_I2C_TIMING1_XMIT_COUNT 0 | ||
171 | #define BM_I2C_TIMING1_XMIT_COUNT 0x3ff | ||
172 | #define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) << 0) & 0x3ff) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_I2C_TIMING2 | ||
176 | * Address: 0x30 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_I2C_TIMING2 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0)) | ||
180 | #define HW_I2C_TIMING2_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4)) | ||
181 | #define HW_I2C_TIMING2_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8)) | ||
182 | #define HW_I2C_TIMING2_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc)) | ||
183 | #define BP_I2C_TIMING2_RSVD2 26 | ||
184 | #define BM_I2C_TIMING2_RSVD2 0xfc000000 | ||
185 | #define BF_I2C_TIMING2_RSVD2(v) (((v) << 26) & 0xfc000000) | ||
186 | #define BP_I2C_TIMING2_BUS_FREE 16 | ||
187 | #define BM_I2C_TIMING2_BUS_FREE 0x3ff0000 | ||
188 | #define BF_I2C_TIMING2_BUS_FREE(v) (((v) << 16) & 0x3ff0000) | ||
189 | #define BP_I2C_TIMING2_RSVD1 10 | ||
190 | #define BM_I2C_TIMING2_RSVD1 0xfc00 | ||
191 | #define BF_I2C_TIMING2_RSVD1(v) (((v) << 10) & 0xfc00) | ||
192 | #define BP_I2C_TIMING2_LEADIN_COUNT 0 | ||
193 | #define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff | ||
194 | #define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) << 0) & 0x3ff) | ||
195 | |||
196 | /** | ||
197 | * Register: HW_I2C_CTRL1 | ||
198 | * Address: 0x40 | ||
199 | * SCT: yes | ||
200 | */ | ||
201 | #define HW_I2C_CTRL1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0)) | ||
202 | #define HW_I2C_CTRL1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4)) | ||
203 | #define HW_I2C_CTRL1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8)) | ||
204 | #define HW_I2C_CTRL1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc)) | ||
205 | #define BP_I2C_CTRL1_RSVD1 29 | ||
206 | #define BM_I2C_CTRL1_RSVD1 0xe0000000 | ||
207 | #define BF_I2C_CTRL1_RSVD1(v) (((v) << 29) & 0xe0000000) | ||
208 | #define BP_I2C_CTRL1_CLR_GOT_A_NAK 28 | ||
209 | #define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 | ||
210 | #define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0 | ||
211 | #define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1 | ||
212 | #define BF_I2C_CTRL1_CLR_GOT_A_NAK(v) (((v) << 28) & 0x10000000) | ||
213 | #define BF_I2C_CTRL1_CLR_GOT_A_NAK_V(v) ((BV_I2C_CTRL1_CLR_GOT_A_NAK__##v << 28) & 0x10000000) | ||
214 | #define BP_I2C_CTRL1_ACK_MODE 27 | ||
215 | #define BM_I2C_CTRL1_ACK_MODE 0x8000000 | ||
216 | #define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0 | ||
217 | #define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1 | ||
218 | #define BF_I2C_CTRL1_ACK_MODE(v) (((v) << 27) & 0x8000000) | ||
219 | #define BF_I2C_CTRL1_ACK_MODE_V(v) ((BV_I2C_CTRL1_ACK_MODE__##v << 27) & 0x8000000) | ||
220 | #define BP_I2C_CTRL1_FORCE_DATA_IDLE 26 | ||
221 | #define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x4000000 | ||
222 | #define BF_I2C_CTRL1_FORCE_DATA_IDLE(v) (((v) << 26) & 0x4000000) | ||
223 | #define BP_I2C_CTRL1_FORCE_CLK_IDLE 25 | ||
224 | #define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x2000000 | ||
225 | #define BF_I2C_CTRL1_FORCE_CLK_IDLE(v) (((v) << 25) & 0x2000000) | ||
226 | #define BP_I2C_CTRL1_BCAST_SLAVE_EN 24 | ||
227 | #define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000 | ||
228 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 | ||
229 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 | ||
230 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) << 24) & 0x1000000) | ||
231 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v) ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000) | ||
232 | #define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 | ||
233 | #define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000 | ||
234 | #define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) << 16) & 0xff0000) | ||
235 | #define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15 | ||
236 | #define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000 | ||
237 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 | ||
238 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 | ||
239 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
240 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000) | ||
241 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14 | ||
242 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000 | ||
243 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 | ||
244 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 | ||
245 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
246 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000) | ||
247 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13 | ||
248 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000 | ||
249 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 | ||
250 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 | ||
251 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
252 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000) | ||
253 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12 | ||
254 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000 | ||
255 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 | ||
256 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 | ||
257 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
258 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000) | ||
259 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11 | ||
260 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800 | ||
261 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 | ||
262 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 | ||
263 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) << 11) & 0x800) | ||
264 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800) | ||
265 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10 | ||
266 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400 | ||
267 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 | ||
268 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 | ||
269 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
270 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
271 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9 | ||
272 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200 | ||
273 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 | ||
274 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 | ||
275 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) << 9) & 0x200) | ||
276 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200) | ||
277 | #define BP_I2C_CTRL1_SLAVE_IRQ_EN 8 | ||
278 | #define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100 | ||
279 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 | ||
280 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 | ||
281 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
282 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100) | ||
283 | #define BP_I2C_CTRL1_BUS_FREE_IRQ 7 | ||
284 | #define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80 | ||
285 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 | ||
286 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 | ||
287 | #define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) << 7) & 0x80) | ||
288 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80) | ||
289 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6 | ||
290 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | ||
291 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 | ||
292 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 | ||
293 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) << 6) & 0x40) | ||
294 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40) | ||
295 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5 | ||
296 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | ||
297 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 | ||
298 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 | ||
299 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) << 5) & 0x20) | ||
300 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20) | ||
301 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4 | ||
302 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | ||
303 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 | ||
304 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 | ||
305 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) << 4) & 0x10) | ||
306 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10) | ||
307 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ 3 | ||
308 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8 | ||
309 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 | ||
310 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 | ||
311 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) << 3) & 0x8) | ||
312 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8) | ||
313 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2 | ||
314 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4 | ||
315 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 | ||
316 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 | ||
317 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
318 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4) | ||
319 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1 | ||
320 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2 | ||
321 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 | ||
322 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 | ||
323 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) << 1) & 0x2) | ||
324 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2) | ||
325 | #define BP_I2C_CTRL1_SLAVE_IRQ 0 | ||
326 | #define BM_I2C_CTRL1_SLAVE_IRQ 0x1 | ||
327 | #define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 | ||
328 | #define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 | ||
329 | #define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) << 0) & 0x1) | ||
330 | #define BF_I2C_CTRL1_SLAVE_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1) | ||
331 | |||
332 | /** | ||
333 | * Register: HW_I2C_STAT | ||
334 | * Address: 0x50 | ||
335 | * SCT: no | ||
336 | */ | ||
337 | #define HW_I2C_STAT (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50)) | ||
338 | #define BP_I2C_STAT_MASTER_PRESENT 31 | ||
339 | #define BM_I2C_STAT_MASTER_PRESENT 0x80000000 | ||
340 | #define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 | ||
341 | #define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 | ||
342 | #define BF_I2C_STAT_MASTER_PRESENT(v) (((v) << 31) & 0x80000000) | ||
343 | #define BF_I2C_STAT_MASTER_PRESENT_V(v) ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000) | ||
344 | #define BP_I2C_STAT_SLAVE_PRESENT 30 | ||
345 | #define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 | ||
346 | #define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 | ||
347 | #define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 | ||
348 | #define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) << 30) & 0x40000000) | ||
349 | #define BF_I2C_STAT_SLAVE_PRESENT_V(v) ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000) | ||
350 | #define BP_I2C_STAT_ANY_ENABLED_IRQ 29 | ||
351 | #define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 | ||
352 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 | ||
353 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 | ||
354 | #define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) << 29) & 0x20000000) | ||
355 | #define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v) ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000) | ||
356 | #define BP_I2C_STAT_GOT_A_NAK 28 | ||
357 | #define BM_I2C_STAT_GOT_A_NAK 0x10000000 | ||
358 | #define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0 | ||
359 | #define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1 | ||
360 | #define BF_I2C_STAT_GOT_A_NAK(v) (((v) << 28) & 0x10000000) | ||
361 | #define BF_I2C_STAT_GOT_A_NAK_V(v) ((BV_I2C_STAT_GOT_A_NAK__##v << 28) & 0x10000000) | ||
362 | #define BP_I2C_STAT_RSVD1 24 | ||
363 | #define BM_I2C_STAT_RSVD1 0xf000000 | ||
364 | #define BF_I2C_STAT_RSVD1(v) (((v) << 24) & 0xf000000) | ||
365 | #define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 | ||
366 | #define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000 | ||
367 | #define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) << 16) & 0xff0000) | ||
368 | #define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15 | ||
369 | #define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000 | ||
370 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 | ||
371 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 | ||
372 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) << 15) & 0x8000) | ||
373 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000) | ||
374 | #define BP_I2C_STAT_SLAVE_FOUND 14 | ||
375 | #define BM_I2C_STAT_SLAVE_FOUND 0x4000 | ||
376 | #define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 | ||
377 | #define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 | ||
378 | #define BF_I2C_STAT_SLAVE_FOUND(v) (((v) << 14) & 0x4000) | ||
379 | #define BF_I2C_STAT_SLAVE_FOUND_V(v) ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000) | ||
380 | #define BP_I2C_STAT_SLAVE_SEARCHING 13 | ||
381 | #define BM_I2C_STAT_SLAVE_SEARCHING 0x2000 | ||
382 | #define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 | ||
383 | #define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 | ||
384 | #define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) << 13) & 0x2000) | ||
385 | #define BF_I2C_STAT_SLAVE_SEARCHING_V(v) ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000) | ||
386 | #define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12 | ||
387 | #define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000 | ||
388 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 | ||
389 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 | ||
390 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) << 12) & 0x1000) | ||
391 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000) | ||
392 | #define BP_I2C_STAT_BUS_BUSY 11 | ||
393 | #define BM_I2C_STAT_BUS_BUSY 0x800 | ||
394 | #define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 | ||
395 | #define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 | ||
396 | #define BF_I2C_STAT_BUS_BUSY(v) (((v) << 11) & 0x800) | ||
397 | #define BF_I2C_STAT_BUS_BUSY_V(v) ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800) | ||
398 | #define BP_I2C_STAT_CLK_GEN_BUSY 10 | ||
399 | #define BM_I2C_STAT_CLK_GEN_BUSY 0x400 | ||
400 | #define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 | ||
401 | #define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 | ||
402 | #define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) << 10) & 0x400) | ||
403 | #define BF_I2C_STAT_CLK_GEN_BUSY_V(v) ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400) | ||
404 | #define BP_I2C_STAT_DATA_ENGINE_BUSY 9 | ||
405 | #define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200 | ||
406 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 | ||
407 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 | ||
408 | #define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) << 9) & 0x200) | ||
409 | #define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v) ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200) | ||
410 | #define BP_I2C_STAT_SLAVE_BUSY 8 | ||
411 | #define BM_I2C_STAT_SLAVE_BUSY 0x100 | ||
412 | #define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 | ||
413 | #define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 | ||
414 | #define BF_I2C_STAT_SLAVE_BUSY(v) (((v) << 8) & 0x100) | ||
415 | #define BF_I2C_STAT_SLAVE_BUSY_V(v) ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100) | ||
416 | #define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7 | ||
417 | #define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80 | ||
418 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
419 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 | ||
420 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) << 7) & 0x80) | ||
421 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80) | ||
422 | #define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6 | ||
423 | #define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40 | ||
424 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
425 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 | ||
426 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) << 6) & 0x40) | ||
427 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40) | ||
428 | #define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5 | ||
429 | #define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20 | ||
430 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
431 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 | ||
432 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) << 5) & 0x20) | ||
433 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20) | ||
434 | #define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4 | ||
435 | #define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10 | ||
436 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
437 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
438 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) << 4) & 0x10) | ||
439 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10) | ||
440 | #define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3 | ||
441 | #define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8 | ||
442 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
443 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
444 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
445 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8) | ||
446 | #define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2 | ||
447 | #define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4 | ||
448 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
449 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
450 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
451 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
452 | #define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1 | ||
453 | #define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2 | ||
454 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
455 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 | ||
456 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
457 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2) | ||
458 | #define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0 | ||
459 | #define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1 | ||
460 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
461 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 | ||
462 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) << 0) & 0x1) | ||
463 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1) | ||
464 | |||
465 | /** | ||
466 | * Register: HW_I2C_DATA | ||
467 | * Address: 0x60 | ||
468 | * SCT: no | ||
469 | */ | ||
470 | #define HW_I2C_DATA (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60)) | ||
471 | #define BP_I2C_DATA_DATA 0 | ||
472 | #define BM_I2C_DATA_DATA 0xffffffff | ||
473 | #define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
474 | |||
475 | /** | ||
476 | * Register: HW_I2C_DEBUG0 | ||
477 | * Address: 0x70 | ||
478 | * SCT: yes | ||
479 | */ | ||
480 | #define HW_I2C_DEBUG0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0)) | ||
481 | #define HW_I2C_DEBUG0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4)) | ||
482 | #define HW_I2C_DEBUG0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8)) | ||
483 | #define HW_I2C_DEBUG0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc)) | ||
484 | #define BP_I2C_DEBUG0_DMAREQ 31 | ||
485 | #define BM_I2C_DEBUG0_DMAREQ 0x80000000 | ||
486 | #define BF_I2C_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
487 | #define BP_I2C_DEBUG0_DMAENDCMD 30 | ||
488 | #define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 | ||
489 | #define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) << 30) & 0x40000000) | ||
490 | #define BP_I2C_DEBUG0_DMAKICK 29 | ||
491 | #define BM_I2C_DEBUG0_DMAKICK 0x20000000 | ||
492 | #define BF_I2C_DEBUG0_DMAKICK(v) (((v) << 29) & 0x20000000) | ||
493 | #define BP_I2C_DEBUG0_DMATERMINATE 28 | ||
494 | #define BM_I2C_DEBUG0_DMATERMINATE 0x10000000 | ||
495 | #define BF_I2C_DEBUG0_DMATERMINATE(v) (((v) << 28) & 0x10000000) | ||
496 | #define BP_I2C_DEBUG0_TBD 26 | ||
497 | #define BM_I2C_DEBUG0_TBD 0xc000000 | ||
498 | #define BF_I2C_DEBUG0_TBD(v) (((v) << 26) & 0xc000000) | ||
499 | #define BP_I2C_DEBUG0_DMA_STATE 16 | ||
500 | #define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000 | ||
501 | #define BF_I2C_DEBUG0_DMA_STATE(v) (((v) << 16) & 0x3ff0000) | ||
502 | #define BP_I2C_DEBUG0_START_TOGGLE 15 | ||
503 | #define BM_I2C_DEBUG0_START_TOGGLE 0x8000 | ||
504 | #define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) << 15) & 0x8000) | ||
505 | #define BP_I2C_DEBUG0_STOP_TOGGLE 14 | ||
506 | #define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000 | ||
507 | #define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) << 14) & 0x4000) | ||
508 | #define BP_I2C_DEBUG0_GRAB_TOGGLE 13 | ||
509 | #define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000 | ||
510 | #define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) << 13) & 0x2000) | ||
511 | #define BP_I2C_DEBUG0_CHANGE_TOGGLE 12 | ||
512 | #define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000 | ||
513 | #define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) << 12) & 0x1000) | ||
514 | #define BP_I2C_DEBUG0_TESTMODE 11 | ||
515 | #define BM_I2C_DEBUG0_TESTMODE 0x800 | ||
516 | #define BF_I2C_DEBUG0_TESTMODE(v) (((v) << 11) & 0x800) | ||
517 | #define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10 | ||
518 | #define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400 | ||
519 | #define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400) | ||
520 | #define BP_I2C_DEBUG0_SLAVE_STATE 0 | ||
521 | #define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff | ||
522 | #define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) << 0) & 0x3ff) | ||
523 | |||
524 | /** | ||
525 | * Register: HW_I2C_DEBUG1 | ||
526 | * Address: 0x80 | ||
527 | * SCT: yes | ||
528 | */ | ||
529 | #define HW_I2C_DEBUG1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0)) | ||
530 | #define HW_I2C_DEBUG1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4)) | ||
531 | #define HW_I2C_DEBUG1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8)) | ||
532 | #define HW_I2C_DEBUG1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc)) | ||
533 | #define BP_I2C_DEBUG1_I2C_CLK_IN 31 | ||
534 | #define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 | ||
535 | #define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) << 31) & 0x80000000) | ||
536 | #define BP_I2C_DEBUG1_I2C_DATA_IN 30 | ||
537 | #define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 | ||
538 | #define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) << 30) & 0x40000000) | ||
539 | #define BP_I2C_DEBUG1_RSVD4 28 | ||
540 | #define BM_I2C_DEBUG1_RSVD4 0x30000000 | ||
541 | #define BF_I2C_DEBUG1_RSVD4(v) (((v) << 28) & 0x30000000) | ||
542 | #define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 | ||
543 | #define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000 | ||
544 | #define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) << 24) & 0xf000000) | ||
545 | #define BP_I2C_DEBUG1_CLK_GEN_STATE 16 | ||
546 | #define BM_I2C_DEBUG1_CLK_GEN_STATE 0xff0000 | ||
547 | #define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) << 16) & 0xff0000) | ||
548 | #define BP_I2C_DEBUG1_RSVD2 11 | ||
549 | #define BM_I2C_DEBUG1_RSVD2 0xf800 | ||
550 | #define BF_I2C_DEBUG1_RSVD2(v) (((v) << 11) & 0xf800) | ||
551 | #define BP_I2C_DEBUG1_LST_MODE 9 | ||
552 | #define BM_I2C_DEBUG1_LST_MODE 0x600 | ||
553 | #define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 | ||
554 | #define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 | ||
555 | #define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 | ||
556 | #define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 | ||
557 | #define BF_I2C_DEBUG1_LST_MODE(v) (((v) << 9) & 0x600) | ||
558 | #define BF_I2C_DEBUG1_LST_MODE_V(v) ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600) | ||
559 | #define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8 | ||
560 | #define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100 | ||
561 | #define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) << 8) & 0x100) | ||
562 | #define BP_I2C_DEBUG1_RSVD1 5 | ||
563 | #define BM_I2C_DEBUG1_RSVD1 0xe0 | ||
564 | #define BF_I2C_DEBUG1_RSVD1(v) (((v) << 5) & 0xe0) | ||
565 | #define BP_I2C_DEBUG1_FORCE_CLK_ON 4 | ||
566 | #define BM_I2C_DEBUG1_FORCE_CLK_ON 0x10 | ||
567 | #define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) << 4) & 0x10) | ||
568 | #define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3 | ||
569 | #define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8 | ||
570 | #define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) << 3) & 0x8) | ||
571 | #define BP_I2C_DEBUG1_FORCE_RCV_ACK 2 | ||
572 | #define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4 | ||
573 | #define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) << 2) & 0x4) | ||
574 | #define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1 | ||
575 | #define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2 | ||
576 | #define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) << 1) & 0x2) | ||
577 | #define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0 | ||
578 | #define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1 | ||
579 | #define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) << 0) & 0x1) | ||
580 | |||
581 | /** | ||
582 | * Register: HW_I2C_VERSION | ||
583 | * Address: 0x90 | ||
584 | * SCT: no | ||
585 | */ | ||
586 | #define HW_I2C_VERSION (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90)) | ||
587 | #define BP_I2C_VERSION_MAJOR 24 | ||
588 | #define BM_I2C_VERSION_MAJOR 0xff000000 | ||
589 | #define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
590 | #define BP_I2C_VERSION_MINOR 16 | ||
591 | #define BM_I2C_VERSION_MINOR 0xff0000 | ||
592 | #define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
593 | #define BP_I2C_VERSION_STEP 0 | ||
594 | #define BM_I2C_VERSION_STEP 0xffff | ||
595 | #define BF_I2C_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
596 | |||
597 | #endif /* __HEADERGEN__IMX233__I2C__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-icoll.h b/firmware/target/arm/imx233/regs/imx233/regs-icoll.h new file mode 100644 index 0000000000..e110c52ba1 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-icoll.h | |||
@@ -0,0 +1,350 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__ICOLL__H__ | ||
24 | #define __HEADERGEN__IMX233__ICOLL__H__ | ||
25 | |||
26 | #define REGS_ICOLL_BASE (0x80000000) | ||
27 | |||
28 | #define REGS_ICOLL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ICOLL_VECTOR | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_ICOLL_VECTOR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_ICOLL_VECTOR_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_ICOLL_VECTOR_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_ICOLL_VECTOR_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_ICOLL_VECTOR_IRQVECTOR 2 | ||
40 | #define BM_ICOLL_VECTOR_IRQVECTOR 0xfffffffc | ||
41 | #define BF_ICOLL_VECTOR_IRQVECTOR(v) (((v) << 2) & 0xfffffffc) | ||
42 | #define BP_ICOLL_VECTOR_RSRVD1 0 | ||
43 | #define BM_ICOLL_VECTOR_RSRVD1 0x3 | ||
44 | #define BF_ICOLL_VECTOR_RSRVD1(v) (((v) << 0) & 0x3) | ||
45 | |||
46 | /** | ||
47 | * Register: HW_ICOLL_LEVELACK | ||
48 | * Address: 0x10 | ||
49 | * SCT: no | ||
50 | */ | ||
51 | #define HW_ICOLL_LEVELACK (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10)) | ||
52 | #define BP_ICOLL_LEVELACK_RSRVD1 4 | ||
53 | #define BM_ICOLL_LEVELACK_RSRVD1 0xfffffff0 | ||
54 | #define BF_ICOLL_LEVELACK_RSRVD1(v) (((v) << 4) & 0xfffffff0) | ||
55 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 | ||
56 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0xf | ||
57 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | ||
58 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 | ||
59 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 | ||
60 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 | ||
61 | #define BF_ICOLL_LEVELACK_IRQLEVELACK(v) (((v) << 0) & 0xf) | ||
62 | #define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v) ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf) | ||
63 | |||
64 | /** | ||
65 | * Register: HW_ICOLL_CTRL | ||
66 | * Address: 0x20 | ||
67 | * SCT: yes | ||
68 | */ | ||
69 | #define HW_ICOLL_CTRL (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0)) | ||
70 | #define HW_ICOLL_CTRL_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4)) | ||
71 | #define HW_ICOLL_CTRL_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8)) | ||
72 | #define HW_ICOLL_CTRL_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc)) | ||
73 | #define BP_ICOLL_CTRL_SFTRST 31 | ||
74 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 | ||
75 | #define BV_ICOLL_CTRL_SFTRST__RUN 0x0 | ||
76 | #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 | ||
77 | #define BF_ICOLL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
78 | #define BF_ICOLL_CTRL_SFTRST_V(v) ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
79 | #define BP_ICOLL_CTRL_CLKGATE 30 | ||
80 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 | ||
81 | #define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 | ||
82 | #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 | ||
83 | #define BF_ICOLL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
84 | #define BF_ICOLL_CTRL_CLKGATE_V(v) ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
85 | #define BP_ICOLL_CTRL_RSRVD3 24 | ||
86 | #define BM_ICOLL_CTRL_RSRVD3 0x3f000000 | ||
87 | #define BF_ICOLL_CTRL_RSRVD3(v) (((v) << 24) & 0x3f000000) | ||
88 | #define BP_ICOLL_CTRL_VECTOR_PITCH 21 | ||
89 | #define BM_ICOLL_CTRL_VECTOR_PITCH 0xe00000 | ||
90 | #define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 | ||
91 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 | ||
92 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 | ||
93 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 | ||
94 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 | ||
95 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 | ||
96 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 | ||
97 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 | ||
98 | #define BF_ICOLL_CTRL_VECTOR_PITCH(v) (((v) << 21) & 0xe00000) | ||
99 | #define BF_ICOLL_CTRL_VECTOR_PITCH_V(v) ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000) | ||
100 | #define BP_ICOLL_CTRL_BYPASS_FSM 20 | ||
101 | #define BM_ICOLL_CTRL_BYPASS_FSM 0x100000 | ||
102 | #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 | ||
103 | #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 | ||
104 | #define BF_ICOLL_CTRL_BYPASS_FSM(v) (((v) << 20) & 0x100000) | ||
105 | #define BF_ICOLL_CTRL_BYPASS_FSM_V(v) ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000) | ||
106 | #define BP_ICOLL_CTRL_NO_NESTING 19 | ||
107 | #define BM_ICOLL_CTRL_NO_NESTING 0x80000 | ||
108 | #define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 | ||
109 | #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 | ||
110 | #define BF_ICOLL_CTRL_NO_NESTING(v) (((v) << 19) & 0x80000) | ||
111 | #define BF_ICOLL_CTRL_NO_NESTING_V(v) ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000) | ||
112 | #define BP_ICOLL_CTRL_ARM_RSE_MODE 18 | ||
113 | #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x40000 | ||
114 | #define BF_ICOLL_CTRL_ARM_RSE_MODE(v) (((v) << 18) & 0x40000) | ||
115 | #define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE 17 | ||
116 | #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x20000 | ||
117 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 | ||
118 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 | ||
119 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v) (((v) << 17) & 0x20000) | ||
120 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000) | ||
121 | #define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE 16 | ||
122 | #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x10000 | ||
123 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 | ||
124 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 | ||
125 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v) (((v) << 16) & 0x10000) | ||
126 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000) | ||
127 | #define BP_ICOLL_CTRL_RSRVD1 0 | ||
128 | #define BM_ICOLL_CTRL_RSRVD1 0xffff | ||
129 | #define BF_ICOLL_CTRL_RSRVD1(v) (((v) << 0) & 0xffff) | ||
130 | |||
131 | /** | ||
132 | * Register: HW_ICOLL_VBASE | ||
133 | * Address: 0x40 | ||
134 | * SCT: yes | ||
135 | */ | ||
136 | #define HW_ICOLL_VBASE (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x0)) | ||
137 | #define HW_ICOLL_VBASE_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x4)) | ||
138 | #define HW_ICOLL_VBASE_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x8)) | ||
139 | #define HW_ICOLL_VBASE_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0xc)) | ||
140 | #define BP_ICOLL_VBASE_TABLE_ADDRESS 2 | ||
141 | #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xfffffffc | ||
142 | #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
143 | #define BP_ICOLL_VBASE_RSRVD1 0 | ||
144 | #define BM_ICOLL_VBASE_RSRVD1 0x3 | ||
145 | #define BF_ICOLL_VBASE_RSRVD1(v) (((v) << 0) & 0x3) | ||
146 | |||
147 | /** | ||
148 | * Register: HW_ICOLL_STAT | ||
149 | * Address: 0x70 | ||
150 | * SCT: no | ||
151 | */ | ||
152 | #define HW_ICOLL_STAT (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x70)) | ||
153 | #define BP_ICOLL_STAT_RSRVD1 7 | ||
154 | #define BM_ICOLL_STAT_RSRVD1 0xffffff80 | ||
155 | #define BF_ICOLL_STAT_RSRVD1(v) (((v) << 7) & 0xffffff80) | ||
156 | #define BP_ICOLL_STAT_VECTOR_NUMBER 0 | ||
157 | #define BM_ICOLL_STAT_VECTOR_NUMBER 0x7f | ||
158 | #define BF_ICOLL_STAT_VECTOR_NUMBER(v) (((v) << 0) & 0x7f) | ||
159 | |||
160 | /** | ||
161 | * Register: HW_ICOLL_RAWn | ||
162 | * Address: 0xa0+n*0x10 | ||
163 | * SCT: yes | ||
164 | */ | ||
165 | #define HW_ICOLL_RAWn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x0)) | ||
166 | #define HW_ICOLL_RAWn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x4)) | ||
167 | #define HW_ICOLL_RAWn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x8)) | ||
168 | #define HW_ICOLL_RAWn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0xc)) | ||
169 | #define BP_ICOLL_RAWn_RAW_IRQS 0 | ||
170 | #define BM_ICOLL_RAWn_RAW_IRQS 0xffffffff | ||
171 | #define BF_ICOLL_RAWn_RAW_IRQS(v) (((v) << 0) & 0xffffffff) | ||
172 | |||
173 | /** | ||
174 | * Register: HW_ICOLL_INTERRUPTn | ||
175 | * Address: 0x120+n*0x10 | ||
176 | * SCT: yes | ||
177 | */ | ||
178 | #define HW_ICOLL_INTERRUPTn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x0)) | ||
179 | #define HW_ICOLL_INTERRUPTn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x4)) | ||
180 | #define HW_ICOLL_INTERRUPTn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x8)) | ||
181 | #define HW_ICOLL_INTERRUPTn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0xc)) | ||
182 | #define BP_ICOLL_INTERRUPTn_RSRVD1 5 | ||
183 | #define BM_ICOLL_INTERRUPTn_RSRVD1 0xffffffe0 | ||
184 | #define BF_ICOLL_INTERRUPTn_RSRVD1(v) (((v) << 5) & 0xffffffe0) | ||
185 | #define BP_ICOLL_INTERRUPTn_ENFIQ 4 | ||
186 | #define BM_ICOLL_INTERRUPTn_ENFIQ 0x10 | ||
187 | #define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 | ||
188 | #define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 | ||
189 | #define BF_ICOLL_INTERRUPTn_ENFIQ(v) (((v) << 4) & 0x10) | ||
190 | #define BF_ICOLL_INTERRUPTn_ENFIQ_V(v) ((BV_ICOLL_INTERRUPTn_ENFIQ__##v << 4) & 0x10) | ||
191 | #define BP_ICOLL_INTERRUPTn_SOFTIRQ 3 | ||
192 | #define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x8 | ||
193 | #define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 | ||
194 | #define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 | ||
195 | #define BF_ICOLL_INTERRUPTn_SOFTIRQ(v) (((v) << 3) & 0x8) | ||
196 | #define BF_ICOLL_INTERRUPTn_SOFTIRQ_V(v) ((BV_ICOLL_INTERRUPTn_SOFTIRQ__##v << 3) & 0x8) | ||
197 | #define BP_ICOLL_INTERRUPTn_ENABLE 2 | ||
198 | #define BM_ICOLL_INTERRUPTn_ENABLE 0x4 | ||
199 | #define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 | ||
200 | #define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 | ||
201 | #define BF_ICOLL_INTERRUPTn_ENABLE(v) (((v) << 2) & 0x4) | ||
202 | #define BF_ICOLL_INTERRUPTn_ENABLE_V(v) ((BV_ICOLL_INTERRUPTn_ENABLE__##v << 2) & 0x4) | ||
203 | #define BP_ICOLL_INTERRUPTn_PRIORITY 0 | ||
204 | #define BM_ICOLL_INTERRUPTn_PRIORITY 0x3 | ||
205 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 | ||
206 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 | ||
207 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 | ||
208 | #define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 | ||
209 | #define BF_ICOLL_INTERRUPTn_PRIORITY(v) (((v) << 0) & 0x3) | ||
210 | #define BF_ICOLL_INTERRUPTn_PRIORITY_V(v) ((BV_ICOLL_INTERRUPTn_PRIORITY__##v << 0) & 0x3) | ||
211 | |||
212 | /** | ||
213 | * Register: HW_ICOLL_DEBUG | ||
214 | * Address: 0x1120 | ||
215 | * SCT: yes | ||
216 | */ | ||
217 | #define HW_ICOLL_DEBUG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x0)) | ||
218 | #define HW_ICOLL_DEBUG_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x4)) | ||
219 | #define HW_ICOLL_DEBUG_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x8)) | ||
220 | #define HW_ICOLL_DEBUG_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0xc)) | ||
221 | #define BP_ICOLL_DEBUG_INSERVICE 28 | ||
222 | #define BM_ICOLL_DEBUG_INSERVICE 0xf0000000 | ||
223 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 | ||
224 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 | ||
225 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 | ||
226 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 | ||
227 | #define BF_ICOLL_DEBUG_INSERVICE(v) (((v) << 28) & 0xf0000000) | ||
228 | #define BF_ICOLL_DEBUG_INSERVICE_V(v) ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000) | ||
229 | #define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 | ||
230 | #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0xf000000 | ||
231 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 | ||
232 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 | ||
233 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 | ||
234 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 | ||
235 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) (((v) << 24) & 0xf000000) | ||
236 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v) ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000) | ||
237 | #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 | ||
238 | #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0xf00000 | ||
239 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 | ||
240 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 | ||
241 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 | ||
242 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 | ||
243 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) (((v) << 20) & 0xf00000) | ||
244 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v) ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000) | ||
245 | #define BP_ICOLL_DEBUG_RSRVD2 18 | ||
246 | #define BM_ICOLL_DEBUG_RSRVD2 0xc0000 | ||
247 | #define BF_ICOLL_DEBUG_RSRVD2(v) (((v) << 18) & 0xc0000) | ||
248 | #define BP_ICOLL_DEBUG_FIQ 17 | ||
249 | #define BM_ICOLL_DEBUG_FIQ 0x20000 | ||
250 | #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 | ||
251 | #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 | ||
252 | #define BF_ICOLL_DEBUG_FIQ(v) (((v) << 17) & 0x20000) | ||
253 | #define BF_ICOLL_DEBUG_FIQ_V(v) ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000) | ||
254 | #define BP_ICOLL_DEBUG_IRQ 16 | ||
255 | #define BM_ICOLL_DEBUG_IRQ 0x10000 | ||
256 | #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 | ||
257 | #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 | ||
258 | #define BF_ICOLL_DEBUG_IRQ(v) (((v) << 16) & 0x10000) | ||
259 | #define BF_ICOLL_DEBUG_IRQ_V(v) ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000) | ||
260 | #define BP_ICOLL_DEBUG_RSRVD1 10 | ||
261 | #define BM_ICOLL_DEBUG_RSRVD1 0xfc00 | ||
262 | #define BF_ICOLL_DEBUG_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
263 | #define BP_ICOLL_DEBUG_VECTOR_FSM 0 | ||
264 | #define BM_ICOLL_DEBUG_VECTOR_FSM 0x3ff | ||
265 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x0 | ||
266 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x1 | ||
267 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x2 | ||
268 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x4 | ||
269 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x8 | ||
270 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x10 | ||
271 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20 | ||
272 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40 | ||
273 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80 | ||
274 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 | ||
275 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 | ||
276 | #define BF_ICOLL_DEBUG_VECTOR_FSM(v) (((v) << 0) & 0x3ff) | ||
277 | #define BF_ICOLL_DEBUG_VECTOR_FSM_V(v) ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff) | ||
278 | |||
279 | /** | ||
280 | * Register: HW_ICOLL_DBGREAD0 | ||
281 | * Address: 0x1130 | ||
282 | * SCT: yes | ||
283 | */ | ||
284 | #define HW_ICOLL_DBGREAD0 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x0)) | ||
285 | #define HW_ICOLL_DBGREAD0_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x4)) | ||
286 | #define HW_ICOLL_DBGREAD0_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x8)) | ||
287 | #define HW_ICOLL_DBGREAD0_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0xc)) | ||
288 | #define BP_ICOLL_DBGREAD0_VALUE 0 | ||
289 | #define BM_ICOLL_DBGREAD0_VALUE 0xffffffff | ||
290 | #define BF_ICOLL_DBGREAD0_VALUE(v) (((v) << 0) & 0xffffffff) | ||
291 | |||
292 | /** | ||
293 | * Register: HW_ICOLL_DBGREAD1 | ||
294 | * Address: 0x1140 | ||
295 | * SCT: yes | ||
296 | */ | ||
297 | #define HW_ICOLL_DBGREAD1 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x0)) | ||
298 | #define HW_ICOLL_DBGREAD1_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x4)) | ||
299 | #define HW_ICOLL_DBGREAD1_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x8)) | ||
300 | #define HW_ICOLL_DBGREAD1_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0xc)) | ||
301 | #define BP_ICOLL_DBGREAD1_VALUE 0 | ||
302 | #define BM_ICOLL_DBGREAD1_VALUE 0xffffffff | ||
303 | #define BF_ICOLL_DBGREAD1_VALUE(v) (((v) << 0) & 0xffffffff) | ||
304 | |||
305 | /** | ||
306 | * Register: HW_ICOLL_DBGFLAG | ||
307 | * Address: 0x1150 | ||
308 | * SCT: yes | ||
309 | */ | ||
310 | #define HW_ICOLL_DBGFLAG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x0)) | ||
311 | #define HW_ICOLL_DBGFLAG_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x4)) | ||
312 | #define HW_ICOLL_DBGFLAG_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x8)) | ||
313 | #define HW_ICOLL_DBGFLAG_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0xc)) | ||
314 | #define BP_ICOLL_DBGFLAG_RSRVD1 16 | ||
315 | #define BM_ICOLL_DBGFLAG_RSRVD1 0xffff0000 | ||
316 | #define BF_ICOLL_DBGFLAG_RSRVD1(v) (((v) << 16) & 0xffff0000) | ||
317 | #define BP_ICOLL_DBGFLAG_FLAG 0 | ||
318 | #define BM_ICOLL_DBGFLAG_FLAG 0xffff | ||
319 | #define BF_ICOLL_DBGFLAG_FLAG(v) (((v) << 0) & 0xffff) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_ICOLL_DBGREQUESTn | ||
323 | * Address: 0x1160+n*0x10 | ||
324 | * SCT: yes | ||
325 | */ | ||
326 | #define HW_ICOLL_DBGREQUESTn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x0)) | ||
327 | #define HW_ICOLL_DBGREQUESTn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x4)) | ||
328 | #define HW_ICOLL_DBGREQUESTn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x8)) | ||
329 | #define HW_ICOLL_DBGREQUESTn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0xc)) | ||
330 | #define BP_ICOLL_DBGREQUESTn_BITS 0 | ||
331 | #define BM_ICOLL_DBGREQUESTn_BITS 0xffffffff | ||
332 | #define BF_ICOLL_DBGREQUESTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
333 | |||
334 | /** | ||
335 | * Register: HW_ICOLL_VERSION | ||
336 | * Address: 0x11e0 | ||
337 | * SCT: no | ||
338 | */ | ||
339 | #define HW_ICOLL_VERSION (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x11e0)) | ||
340 | #define BP_ICOLL_VERSION_MAJOR 24 | ||
341 | #define BM_ICOLL_VERSION_MAJOR 0xff000000 | ||
342 | #define BF_ICOLL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
343 | #define BP_ICOLL_VERSION_MINOR 16 | ||
344 | #define BM_ICOLL_VERSION_MINOR 0xff0000 | ||
345 | #define BF_ICOLL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
346 | #define BP_ICOLL_VERSION_STEP 0 | ||
347 | #define BM_ICOLL_VERSION_STEP 0xffff | ||
348 | #define BF_ICOLL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
349 | |||
350 | #endif /* __HEADERGEN__IMX233__ICOLL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ir.h b/firmware/target/arm/imx233/regs/imx233/regs-ir.h new file mode 100644 index 0000000000..e744b00298 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-ir.h | |||
@@ -0,0 +1,529 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__IR__H__ | ||
24 | #define __HEADERGEN__IMX233__IR__H__ | ||
25 | |||
26 | #define REGS_IR_BASE (0x80078000) | ||
27 | |||
28 | #define REGS_IR_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_IR_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_IR_CTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0)) | ||
36 | #define HW_IR_CTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4)) | ||
37 | #define HW_IR_CTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8)) | ||
38 | #define HW_IR_CTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc)) | ||
39 | #define BP_IR_CTRL_SFTRST 31 | ||
40 | #define BM_IR_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_IR_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_IR_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_IR_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_IR_CTRL_SFTRST_V(v) ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_IR_CTRL_CLKGATE 30 | ||
46 | #define BM_IR_CTRL_CLKGATE 0x40000000 | ||
47 | #define BF_IR_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
48 | #define BP_IR_CTRL_RSVD2 27 | ||
49 | #define BM_IR_CTRL_RSVD2 0x38000000 | ||
50 | #define BF_IR_CTRL_RSVD2(v) (((v) << 27) & 0x38000000) | ||
51 | #define BP_IR_CTRL_MTA 24 | ||
52 | #define BM_IR_CTRL_MTA 0x7000000 | ||
53 | #define BV_IR_CTRL_MTA__MTA_10MS 0x0 | ||
54 | #define BV_IR_CTRL_MTA__MTA_5MS 0x1 | ||
55 | #define BV_IR_CTRL_MTA__MTA_1MS 0x2 | ||
56 | #define BV_IR_CTRL_MTA__MTA_500US 0x3 | ||
57 | #define BV_IR_CTRL_MTA__MTA_100US 0x4 | ||
58 | #define BV_IR_CTRL_MTA__MTA_50US 0x5 | ||
59 | #define BV_IR_CTRL_MTA__MTA_10US 0x6 | ||
60 | #define BV_IR_CTRL_MTA__MTA_0 0x7 | ||
61 | #define BF_IR_CTRL_MTA(v) (((v) << 24) & 0x7000000) | ||
62 | #define BF_IR_CTRL_MTA_V(v) ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000) | ||
63 | #define BP_IR_CTRL_MODE 22 | ||
64 | #define BM_IR_CTRL_MODE 0xc00000 | ||
65 | #define BV_IR_CTRL_MODE__SIR 0x0 | ||
66 | #define BV_IR_CTRL_MODE__MIR 0x1 | ||
67 | #define BV_IR_CTRL_MODE__FIR 0x2 | ||
68 | #define BV_IR_CTRL_MODE__VFIR 0x3 | ||
69 | #define BF_IR_CTRL_MODE(v) (((v) << 22) & 0xc00000) | ||
70 | #define BF_IR_CTRL_MODE_V(v) ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000) | ||
71 | #define BP_IR_CTRL_SPEED 19 | ||
72 | #define BM_IR_CTRL_SPEED 0x380000 | ||
73 | #define BV_IR_CTRL_SPEED__SPD000 0x0 | ||
74 | #define BV_IR_CTRL_SPEED__SPD001 0x1 | ||
75 | #define BV_IR_CTRL_SPEED__SPD010 0x2 | ||
76 | #define BV_IR_CTRL_SPEED__SPD011 0x3 | ||
77 | #define BV_IR_CTRL_SPEED__SPD100 0x4 | ||
78 | #define BV_IR_CTRL_SPEED__SPD101 0x5 | ||
79 | #define BF_IR_CTRL_SPEED(v) (((v) << 19) & 0x380000) | ||
80 | #define BF_IR_CTRL_SPEED_V(v) ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000) | ||
81 | #define BP_IR_CTRL_RSVD1 14 | ||
82 | #define BM_IR_CTRL_RSVD1 0x7c000 | ||
83 | #define BF_IR_CTRL_RSVD1(v) (((v) << 14) & 0x7c000) | ||
84 | #define BP_IR_CTRL_TC_TIME_DIV 8 | ||
85 | #define BM_IR_CTRL_TC_TIME_DIV 0x3f00 | ||
86 | #define BF_IR_CTRL_TC_TIME_DIV(v) (((v) << 8) & 0x3f00) | ||
87 | #define BP_IR_CTRL_TC_TYPE 7 | ||
88 | #define BM_IR_CTRL_TC_TYPE 0x80 | ||
89 | #define BF_IR_CTRL_TC_TYPE(v) (((v) << 7) & 0x80) | ||
90 | #define BP_IR_CTRL_SIR_GAP 4 | ||
91 | #define BM_IR_CTRL_SIR_GAP 0x70 | ||
92 | #define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0 | ||
93 | #define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1 | ||
94 | #define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2 | ||
95 | #define BV_IR_CTRL_SIR_GAP__GAP_500 0x3 | ||
96 | #define BV_IR_CTRL_SIR_GAP__GAP_100 0x4 | ||
97 | #define BV_IR_CTRL_SIR_GAP__GAP_50 0x5 | ||
98 | #define BV_IR_CTRL_SIR_GAP__GAP_10 0x6 | ||
99 | #define BV_IR_CTRL_SIR_GAP__GAP_0 0x7 | ||
100 | #define BF_IR_CTRL_SIR_GAP(v) (((v) << 4) & 0x70) | ||
101 | #define BF_IR_CTRL_SIR_GAP_V(v) ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70) | ||
102 | #define BP_IR_CTRL_SIPEN 3 | ||
103 | #define BM_IR_CTRL_SIPEN 0x8 | ||
104 | #define BF_IR_CTRL_SIPEN(v) (((v) << 3) & 0x8) | ||
105 | #define BP_IR_CTRL_TCEN 2 | ||
106 | #define BM_IR_CTRL_TCEN 0x4 | ||
107 | #define BF_IR_CTRL_TCEN(v) (((v) << 2) & 0x4) | ||
108 | #define BP_IR_CTRL_TXEN 1 | ||
109 | #define BM_IR_CTRL_TXEN 0x2 | ||
110 | #define BF_IR_CTRL_TXEN(v) (((v) << 1) & 0x2) | ||
111 | #define BP_IR_CTRL_RXEN 0 | ||
112 | #define BM_IR_CTRL_RXEN 0x1 | ||
113 | #define BF_IR_CTRL_RXEN(v) (((v) << 0) & 0x1) | ||
114 | |||
115 | /** | ||
116 | * Register: HW_IR_TXDMA | ||
117 | * Address: 0x10 | ||
118 | * SCT: yes | ||
119 | */ | ||
120 | #define HW_IR_TXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0)) | ||
121 | #define HW_IR_TXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4)) | ||
122 | #define HW_IR_TXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8)) | ||
123 | #define HW_IR_TXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc)) | ||
124 | #define BP_IR_TXDMA_RUN 31 | ||
125 | #define BM_IR_TXDMA_RUN 0x80000000 | ||
126 | #define BF_IR_TXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
127 | #define BP_IR_TXDMA_RSVD2 30 | ||
128 | #define BM_IR_TXDMA_RSVD2 0x40000000 | ||
129 | #define BF_IR_TXDMA_RSVD2(v) (((v) << 30) & 0x40000000) | ||
130 | #define BP_IR_TXDMA_EMPTY 29 | ||
131 | #define BM_IR_TXDMA_EMPTY 0x20000000 | ||
132 | #define BF_IR_TXDMA_EMPTY(v) (((v) << 29) & 0x20000000) | ||
133 | #define BP_IR_TXDMA_INT 28 | ||
134 | #define BM_IR_TXDMA_INT 0x10000000 | ||
135 | #define BF_IR_TXDMA_INT(v) (((v) << 28) & 0x10000000) | ||
136 | #define BP_IR_TXDMA_CHANGE 27 | ||
137 | #define BM_IR_TXDMA_CHANGE 0x8000000 | ||
138 | #define BF_IR_TXDMA_CHANGE(v) (((v) << 27) & 0x8000000) | ||
139 | #define BP_IR_TXDMA_NEW_MTA 24 | ||
140 | #define BM_IR_TXDMA_NEW_MTA 0x7000000 | ||
141 | #define BF_IR_TXDMA_NEW_MTA(v) (((v) << 24) & 0x7000000) | ||
142 | #define BP_IR_TXDMA_NEW_MODE 22 | ||
143 | #define BM_IR_TXDMA_NEW_MODE 0xc00000 | ||
144 | #define BF_IR_TXDMA_NEW_MODE(v) (((v) << 22) & 0xc00000) | ||
145 | #define BP_IR_TXDMA_NEW_SPEED 19 | ||
146 | #define BM_IR_TXDMA_NEW_SPEED 0x380000 | ||
147 | #define BF_IR_TXDMA_NEW_SPEED(v) (((v) << 19) & 0x380000) | ||
148 | #define BP_IR_TXDMA_BOF_TYPE 18 | ||
149 | #define BM_IR_TXDMA_BOF_TYPE 0x40000 | ||
150 | #define BF_IR_TXDMA_BOF_TYPE(v) (((v) << 18) & 0x40000) | ||
151 | #define BP_IR_TXDMA_XBOFS 12 | ||
152 | #define BM_IR_TXDMA_XBOFS 0x3f000 | ||
153 | #define BF_IR_TXDMA_XBOFS(v) (((v) << 12) & 0x3f000) | ||
154 | #define BP_IR_TXDMA_XFER_COUNT 0 | ||
155 | #define BM_IR_TXDMA_XFER_COUNT 0xfff | ||
156 | #define BF_IR_TXDMA_XFER_COUNT(v) (((v) << 0) & 0xfff) | ||
157 | |||
158 | /** | ||
159 | * Register: HW_IR_RXDMA | ||
160 | * Address: 0x20 | ||
161 | * SCT: yes | ||
162 | */ | ||
163 | #define HW_IR_RXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0)) | ||
164 | #define HW_IR_RXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4)) | ||
165 | #define HW_IR_RXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8)) | ||
166 | #define HW_IR_RXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc)) | ||
167 | #define BP_IR_RXDMA_RUN 31 | ||
168 | #define BM_IR_RXDMA_RUN 0x80000000 | ||
169 | #define BF_IR_RXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
170 | #define BP_IR_RXDMA_RSVD 10 | ||
171 | #define BM_IR_RXDMA_RSVD 0x7ffffc00 | ||
172 | #define BF_IR_RXDMA_RSVD(v) (((v) << 10) & 0x7ffffc00) | ||
173 | #define BP_IR_RXDMA_XFER_COUNT 0 | ||
174 | #define BM_IR_RXDMA_XFER_COUNT 0x3ff | ||
175 | #define BF_IR_RXDMA_XFER_COUNT(v) (((v) << 0) & 0x3ff) | ||
176 | |||
177 | /** | ||
178 | * Register: HW_IR_DBGCTRL | ||
179 | * Address: 0x30 | ||
180 | * SCT: yes | ||
181 | */ | ||
182 | #define HW_IR_DBGCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0)) | ||
183 | #define HW_IR_DBGCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4)) | ||
184 | #define HW_IR_DBGCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8)) | ||
185 | #define HW_IR_DBGCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc)) | ||
186 | #define BP_IR_DBGCTRL_RSVD2 13 | ||
187 | #define BM_IR_DBGCTRL_RSVD2 0xffffe000 | ||
188 | #define BF_IR_DBGCTRL_RSVD2(v) (((v) << 13) & 0xffffe000) | ||
189 | #define BP_IR_DBGCTRL_VFIRSWZ 12 | ||
190 | #define BM_IR_DBGCTRL_VFIRSWZ 0x1000 | ||
191 | #define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0 | ||
192 | #define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1 | ||
193 | #define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) << 12) & 0x1000) | ||
194 | #define BF_IR_DBGCTRL_VFIRSWZ_V(v) ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000) | ||
195 | #define BP_IR_DBGCTRL_RXFRMOFF 11 | ||
196 | #define BM_IR_DBGCTRL_RXFRMOFF 0x800 | ||
197 | #define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) << 11) & 0x800) | ||
198 | #define BP_IR_DBGCTRL_RXCRCOFF 10 | ||
199 | #define BM_IR_DBGCTRL_RXCRCOFF 0x400 | ||
200 | #define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) << 10) & 0x400) | ||
201 | #define BP_IR_DBGCTRL_RXINVERT 9 | ||
202 | #define BM_IR_DBGCTRL_RXINVERT 0x200 | ||
203 | #define BF_IR_DBGCTRL_RXINVERT(v) (((v) << 9) & 0x200) | ||
204 | #define BP_IR_DBGCTRL_TXFRMOFF 8 | ||
205 | #define BM_IR_DBGCTRL_TXFRMOFF 0x100 | ||
206 | #define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) << 8) & 0x100) | ||
207 | #define BP_IR_DBGCTRL_TXCRCOFF 7 | ||
208 | #define BM_IR_DBGCTRL_TXCRCOFF 0x80 | ||
209 | #define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) << 7) & 0x80) | ||
210 | #define BP_IR_DBGCTRL_TXINVERT 6 | ||
211 | #define BM_IR_DBGCTRL_TXINVERT 0x40 | ||
212 | #define BF_IR_DBGCTRL_TXINVERT(v) (((v) << 6) & 0x40) | ||
213 | #define BP_IR_DBGCTRL_INTLOOPBACK 5 | ||
214 | #define BM_IR_DBGCTRL_INTLOOPBACK 0x20 | ||
215 | #define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) << 5) & 0x20) | ||
216 | #define BP_IR_DBGCTRL_DUPLEX 4 | ||
217 | #define BM_IR_DBGCTRL_DUPLEX 0x10 | ||
218 | #define BF_IR_DBGCTRL_DUPLEX(v) (((v) << 4) & 0x10) | ||
219 | #define BP_IR_DBGCTRL_MIO_RX 3 | ||
220 | #define BM_IR_DBGCTRL_MIO_RX 0x8 | ||
221 | #define BF_IR_DBGCTRL_MIO_RX(v) (((v) << 3) & 0x8) | ||
222 | #define BP_IR_DBGCTRL_MIO_TX 2 | ||
223 | #define BM_IR_DBGCTRL_MIO_TX 0x4 | ||
224 | #define BF_IR_DBGCTRL_MIO_TX(v) (((v) << 2) & 0x4) | ||
225 | #define BP_IR_DBGCTRL_MIO_SCLK 1 | ||
226 | #define BM_IR_DBGCTRL_MIO_SCLK 0x2 | ||
227 | #define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) << 1) & 0x2) | ||
228 | #define BP_IR_DBGCTRL_MIO_EN 0 | ||
229 | #define BM_IR_DBGCTRL_MIO_EN 0x1 | ||
230 | #define BF_IR_DBGCTRL_MIO_EN(v) (((v) << 0) & 0x1) | ||
231 | |||
232 | /** | ||
233 | * Register: HW_IR_INTR | ||
234 | * Address: 0x40 | ||
235 | * SCT: yes | ||
236 | */ | ||
237 | #define HW_IR_INTR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0)) | ||
238 | #define HW_IR_INTR_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4)) | ||
239 | #define HW_IR_INTR_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8)) | ||
240 | #define HW_IR_INTR_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc)) | ||
241 | #define BP_IR_INTR_RSVD2 23 | ||
242 | #define BM_IR_INTR_RSVD2 0xff800000 | ||
243 | #define BF_IR_INTR_RSVD2(v) (((v) << 23) & 0xff800000) | ||
244 | #define BP_IR_INTR_RXABORT_IRQ_EN 22 | ||
245 | #define BM_IR_INTR_RXABORT_IRQ_EN 0x400000 | ||
246 | #define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0 | ||
247 | #define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1 | ||
248 | #define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
249 | #define BF_IR_INTR_RXABORT_IRQ_EN_V(v) ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000) | ||
250 | #define BP_IR_INTR_SPEED_IRQ_EN 21 | ||
251 | #define BM_IR_INTR_SPEED_IRQ_EN 0x200000 | ||
252 | #define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0 | ||
253 | #define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1 | ||
254 | #define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
255 | #define BF_IR_INTR_SPEED_IRQ_EN_V(v) ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000) | ||
256 | #define BP_IR_INTR_RXOF_IRQ_EN 20 | ||
257 | #define BM_IR_INTR_RXOF_IRQ_EN 0x100000 | ||
258 | #define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0 | ||
259 | #define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1 | ||
260 | #define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
261 | #define BF_IR_INTR_RXOF_IRQ_EN_V(v) ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000) | ||
262 | #define BP_IR_INTR_TXUF_IRQ_EN 19 | ||
263 | #define BM_IR_INTR_TXUF_IRQ_EN 0x80000 | ||
264 | #define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0 | ||
265 | #define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1 | ||
266 | #define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
267 | #define BF_IR_INTR_TXUF_IRQ_EN_V(v) ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000) | ||
268 | #define BP_IR_INTR_TC_IRQ_EN 18 | ||
269 | #define BM_IR_INTR_TC_IRQ_EN 0x40000 | ||
270 | #define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0 | ||
271 | #define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1 | ||
272 | #define BF_IR_INTR_TC_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
273 | #define BF_IR_INTR_TC_IRQ_EN_V(v) ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000) | ||
274 | #define BP_IR_INTR_RX_IRQ_EN 17 | ||
275 | #define BM_IR_INTR_RX_IRQ_EN 0x20000 | ||
276 | #define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0 | ||
277 | #define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1 | ||
278 | #define BF_IR_INTR_RX_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
279 | #define BF_IR_INTR_RX_IRQ_EN_V(v) ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000) | ||
280 | #define BP_IR_INTR_TX_IRQ_EN 16 | ||
281 | #define BM_IR_INTR_TX_IRQ_EN 0x10000 | ||
282 | #define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0 | ||
283 | #define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1 | ||
284 | #define BF_IR_INTR_TX_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
285 | #define BF_IR_INTR_TX_IRQ_EN_V(v) ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000) | ||
286 | #define BP_IR_INTR_RSVD1 7 | ||
287 | #define BM_IR_INTR_RSVD1 0xff80 | ||
288 | #define BF_IR_INTR_RSVD1(v) (((v) << 7) & 0xff80) | ||
289 | #define BP_IR_INTR_RXABORT_IRQ 6 | ||
290 | #define BM_IR_INTR_RXABORT_IRQ 0x40 | ||
291 | #define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0 | ||
292 | #define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1 | ||
293 | #define BF_IR_INTR_RXABORT_IRQ(v) (((v) << 6) & 0x40) | ||
294 | #define BF_IR_INTR_RXABORT_IRQ_V(v) ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40) | ||
295 | #define BP_IR_INTR_SPEED_IRQ 5 | ||
296 | #define BM_IR_INTR_SPEED_IRQ 0x20 | ||
297 | #define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0 | ||
298 | #define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1 | ||
299 | #define BF_IR_INTR_SPEED_IRQ(v) (((v) << 5) & 0x20) | ||
300 | #define BF_IR_INTR_SPEED_IRQ_V(v) ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20) | ||
301 | #define BP_IR_INTR_RXOF_IRQ 4 | ||
302 | #define BM_IR_INTR_RXOF_IRQ 0x10 | ||
303 | #define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0 | ||
304 | #define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1 | ||
305 | #define BF_IR_INTR_RXOF_IRQ(v) (((v) << 4) & 0x10) | ||
306 | #define BF_IR_INTR_RXOF_IRQ_V(v) ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10) | ||
307 | #define BP_IR_INTR_TXUF_IRQ 3 | ||
308 | #define BM_IR_INTR_TXUF_IRQ 0x8 | ||
309 | #define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0 | ||
310 | #define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1 | ||
311 | #define BF_IR_INTR_TXUF_IRQ(v) (((v) << 3) & 0x8) | ||
312 | #define BF_IR_INTR_TXUF_IRQ_V(v) ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8) | ||
313 | #define BP_IR_INTR_TC_IRQ 2 | ||
314 | #define BM_IR_INTR_TC_IRQ 0x4 | ||
315 | #define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0 | ||
316 | #define BV_IR_INTR_TC_IRQ__REQUEST 0x1 | ||
317 | #define BF_IR_INTR_TC_IRQ(v) (((v) << 2) & 0x4) | ||
318 | #define BF_IR_INTR_TC_IRQ_V(v) ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4) | ||
319 | #define BP_IR_INTR_RX_IRQ 1 | ||
320 | #define BM_IR_INTR_RX_IRQ 0x2 | ||
321 | #define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0 | ||
322 | #define BV_IR_INTR_RX_IRQ__REQUEST 0x1 | ||
323 | #define BF_IR_INTR_RX_IRQ(v) (((v) << 1) & 0x2) | ||
324 | #define BF_IR_INTR_RX_IRQ_V(v) ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2) | ||
325 | #define BP_IR_INTR_TX_IRQ 0 | ||
326 | #define BM_IR_INTR_TX_IRQ 0x1 | ||
327 | #define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0 | ||
328 | #define BV_IR_INTR_TX_IRQ__REQUEST 0x1 | ||
329 | #define BF_IR_INTR_TX_IRQ(v) (((v) << 0) & 0x1) | ||
330 | #define BF_IR_INTR_TX_IRQ_V(v) ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1) | ||
331 | |||
332 | /** | ||
333 | * Register: HW_IR_DATA | ||
334 | * Address: 0x50 | ||
335 | * SCT: no | ||
336 | */ | ||
337 | #define HW_IR_DATA (*(volatile unsigned long *)(REGS_IR_BASE + 0x50)) | ||
338 | #define BP_IR_DATA_DATA 0 | ||
339 | #define BM_IR_DATA_DATA 0xffffffff | ||
340 | #define BF_IR_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
341 | |||
342 | /** | ||
343 | * Register: HW_IR_STAT | ||
344 | * Address: 0x60 | ||
345 | * SCT: no | ||
346 | */ | ||
347 | #define HW_IR_STAT (*(volatile unsigned long *)(REGS_IR_BASE + 0x60)) | ||
348 | #define BP_IR_STAT_PRESENT 31 | ||
349 | #define BM_IR_STAT_PRESENT 0x80000000 | ||
350 | #define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0 | ||
351 | #define BV_IR_STAT_PRESENT__AVAILABLE 0x1 | ||
352 | #define BF_IR_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
353 | #define BF_IR_STAT_PRESENT_V(v) ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000) | ||
354 | #define BP_IR_STAT_MODE_ALLOWED 29 | ||
355 | #define BM_IR_STAT_MODE_ALLOWED 0x60000000 | ||
356 | #define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0 | ||
357 | #define BV_IR_STAT_MODE_ALLOWED__FIR 0x1 | ||
358 | #define BV_IR_STAT_MODE_ALLOWED__MIR 0x2 | ||
359 | #define BV_IR_STAT_MODE_ALLOWED__SIR 0x3 | ||
360 | #define BF_IR_STAT_MODE_ALLOWED(v) (((v) << 29) & 0x60000000) | ||
361 | #define BF_IR_STAT_MODE_ALLOWED_V(v) ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000) | ||
362 | #define BP_IR_STAT_ANY_IRQ 28 | ||
363 | #define BM_IR_STAT_ANY_IRQ 0x10000000 | ||
364 | #define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0 | ||
365 | #define BV_IR_STAT_ANY_IRQ__REQUEST 0x1 | ||
366 | #define BF_IR_STAT_ANY_IRQ(v) (((v) << 28) & 0x10000000) | ||
367 | #define BF_IR_STAT_ANY_IRQ_V(v) ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000) | ||
368 | #define BP_IR_STAT_RSVD2 23 | ||
369 | #define BM_IR_STAT_RSVD2 0xf800000 | ||
370 | #define BF_IR_STAT_RSVD2(v) (((v) << 23) & 0xf800000) | ||
371 | #define BP_IR_STAT_RXABORT_SUMMARY 22 | ||
372 | #define BM_IR_STAT_RXABORT_SUMMARY 0x400000 | ||
373 | #define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0 | ||
374 | #define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1 | ||
375 | #define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) << 22) & 0x400000) | ||
376 | #define BF_IR_STAT_RXABORT_SUMMARY_V(v) ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000) | ||
377 | #define BP_IR_STAT_SPEED_SUMMARY 21 | ||
378 | #define BM_IR_STAT_SPEED_SUMMARY 0x200000 | ||
379 | #define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0 | ||
380 | #define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1 | ||
381 | #define BF_IR_STAT_SPEED_SUMMARY(v) (((v) << 21) & 0x200000) | ||
382 | #define BF_IR_STAT_SPEED_SUMMARY_V(v) ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000) | ||
383 | #define BP_IR_STAT_RXOF_SUMMARY 20 | ||
384 | #define BM_IR_STAT_RXOF_SUMMARY 0x100000 | ||
385 | #define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0 | ||
386 | #define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1 | ||
387 | #define BF_IR_STAT_RXOF_SUMMARY(v) (((v) << 20) & 0x100000) | ||
388 | #define BF_IR_STAT_RXOF_SUMMARY_V(v) ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000) | ||
389 | #define BP_IR_STAT_TXUF_SUMMARY 19 | ||
390 | #define BM_IR_STAT_TXUF_SUMMARY 0x80000 | ||
391 | #define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0 | ||
392 | #define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1 | ||
393 | #define BF_IR_STAT_TXUF_SUMMARY(v) (((v) << 19) & 0x80000) | ||
394 | #define BF_IR_STAT_TXUF_SUMMARY_V(v) ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000) | ||
395 | #define BP_IR_STAT_TC_SUMMARY 18 | ||
396 | #define BM_IR_STAT_TC_SUMMARY 0x40000 | ||
397 | #define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0 | ||
398 | #define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1 | ||
399 | #define BF_IR_STAT_TC_SUMMARY(v) (((v) << 18) & 0x40000) | ||
400 | #define BF_IR_STAT_TC_SUMMARY_V(v) ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000) | ||
401 | #define BP_IR_STAT_RX_SUMMARY 17 | ||
402 | #define BM_IR_STAT_RX_SUMMARY 0x20000 | ||
403 | #define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0 | ||
404 | #define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1 | ||
405 | #define BF_IR_STAT_RX_SUMMARY(v) (((v) << 17) & 0x20000) | ||
406 | #define BF_IR_STAT_RX_SUMMARY_V(v) ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000) | ||
407 | #define BP_IR_STAT_TX_SUMMARY 16 | ||
408 | #define BM_IR_STAT_TX_SUMMARY 0x10000 | ||
409 | #define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0 | ||
410 | #define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1 | ||
411 | #define BF_IR_STAT_TX_SUMMARY(v) (((v) << 16) & 0x10000) | ||
412 | #define BF_IR_STAT_TX_SUMMARY_V(v) ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000) | ||
413 | #define BP_IR_STAT_RSVD1 3 | ||
414 | #define BM_IR_STAT_RSVD1 0xfff8 | ||
415 | #define BF_IR_STAT_RSVD1(v) (((v) << 3) & 0xfff8) | ||
416 | #define BP_IR_STAT_MEDIA_BUSY 2 | ||
417 | #define BM_IR_STAT_MEDIA_BUSY 0x4 | ||
418 | #define BF_IR_STAT_MEDIA_BUSY(v) (((v) << 2) & 0x4) | ||
419 | #define BP_IR_STAT_RX_ACTIVE 1 | ||
420 | #define BM_IR_STAT_RX_ACTIVE 0x2 | ||
421 | #define BF_IR_STAT_RX_ACTIVE(v) (((v) << 1) & 0x2) | ||
422 | #define BP_IR_STAT_TX_ACTIVE 0 | ||
423 | #define BM_IR_STAT_TX_ACTIVE 0x1 | ||
424 | #define BF_IR_STAT_TX_ACTIVE(v) (((v) << 0) & 0x1) | ||
425 | |||
426 | /** | ||
427 | * Register: HW_IR_TCCTRL | ||
428 | * Address: 0x70 | ||
429 | * SCT: yes | ||
430 | */ | ||
431 | #define HW_IR_TCCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0)) | ||
432 | #define HW_IR_TCCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4)) | ||
433 | #define HW_IR_TCCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8)) | ||
434 | #define HW_IR_TCCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc)) | ||
435 | #define BP_IR_TCCTRL_INIT 31 | ||
436 | #define BM_IR_TCCTRL_INIT 0x80000000 | ||
437 | #define BF_IR_TCCTRL_INIT(v) (((v) << 31) & 0x80000000) | ||
438 | #define BP_IR_TCCTRL_GO 30 | ||
439 | #define BM_IR_TCCTRL_GO 0x40000000 | ||
440 | #define BF_IR_TCCTRL_GO(v) (((v) << 30) & 0x40000000) | ||
441 | #define BP_IR_TCCTRL_BUSY 29 | ||
442 | #define BM_IR_TCCTRL_BUSY 0x20000000 | ||
443 | #define BF_IR_TCCTRL_BUSY(v) (((v) << 29) & 0x20000000) | ||
444 | #define BP_IR_TCCTRL_RSVD 25 | ||
445 | #define BM_IR_TCCTRL_RSVD 0x1e000000 | ||
446 | #define BF_IR_TCCTRL_RSVD(v) (((v) << 25) & 0x1e000000) | ||
447 | #define BP_IR_TCCTRL_TEMIC 24 | ||
448 | #define BM_IR_TCCTRL_TEMIC 0x1000000 | ||
449 | #define BV_IR_TCCTRL_TEMIC__LOW 0x0 | ||
450 | #define BV_IR_TCCTRL_TEMIC__HIGH 0x1 | ||
451 | #define BF_IR_TCCTRL_TEMIC(v) (((v) << 24) & 0x1000000) | ||
452 | #define BF_IR_TCCTRL_TEMIC_V(v) ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000) | ||
453 | #define BP_IR_TCCTRL_EXT_DATA 16 | ||
454 | #define BM_IR_TCCTRL_EXT_DATA 0xff0000 | ||
455 | #define BF_IR_TCCTRL_EXT_DATA(v) (((v) << 16) & 0xff0000) | ||
456 | #define BP_IR_TCCTRL_DATA 8 | ||
457 | #define BM_IR_TCCTRL_DATA 0xff00 | ||
458 | #define BF_IR_TCCTRL_DATA(v) (((v) << 8) & 0xff00) | ||
459 | #define BP_IR_TCCTRL_ADDR 5 | ||
460 | #define BM_IR_TCCTRL_ADDR 0xe0 | ||
461 | #define BF_IR_TCCTRL_ADDR(v) (((v) << 5) & 0xe0) | ||
462 | #define BP_IR_TCCTRL_INDX 1 | ||
463 | #define BM_IR_TCCTRL_INDX 0x1e | ||
464 | #define BF_IR_TCCTRL_INDX(v) (((v) << 1) & 0x1e) | ||
465 | #define BP_IR_TCCTRL_C 0 | ||
466 | #define BM_IR_TCCTRL_C 0x1 | ||
467 | #define BF_IR_TCCTRL_C(v) (((v) << 0) & 0x1) | ||
468 | |||
469 | /** | ||
470 | * Register: HW_IR_SI_READ | ||
471 | * Address: 0x80 | ||
472 | * SCT: no | ||
473 | */ | ||
474 | #define HW_IR_SI_READ (*(volatile unsigned long *)(REGS_IR_BASE + 0x80)) | ||
475 | #define BP_IR_SI_READ_RSVD1 9 | ||
476 | #define BM_IR_SI_READ_RSVD1 0xfffffe00 | ||
477 | #define BF_IR_SI_READ_RSVD1(v) (((v) << 9) & 0xfffffe00) | ||
478 | #define BP_IR_SI_READ_ABORT 8 | ||
479 | #define BM_IR_SI_READ_ABORT 0x100 | ||
480 | #define BF_IR_SI_READ_ABORT(v) (((v) << 8) & 0x100) | ||
481 | #define BP_IR_SI_READ_DATA 0 | ||
482 | #define BM_IR_SI_READ_DATA 0xff | ||
483 | #define BF_IR_SI_READ_DATA(v) (((v) << 0) & 0xff) | ||
484 | |||
485 | /** | ||
486 | * Register: HW_IR_DEBUG | ||
487 | * Address: 0x90 | ||
488 | * SCT: no | ||
489 | */ | ||
490 | #define HW_IR_DEBUG (*(volatile unsigned long *)(REGS_IR_BASE + 0x90)) | ||
491 | #define BP_IR_DEBUG_RSVD1 6 | ||
492 | #define BM_IR_DEBUG_RSVD1 0xffffffc0 | ||
493 | #define BF_IR_DEBUG_RSVD1(v) (((v) << 6) & 0xffffffc0) | ||
494 | #define BP_IR_DEBUG_TXDMAKICK 5 | ||
495 | #define BM_IR_DEBUG_TXDMAKICK 0x20 | ||
496 | #define BF_IR_DEBUG_TXDMAKICK(v) (((v) << 5) & 0x20) | ||
497 | #define BP_IR_DEBUG_RXDMAKICK 4 | ||
498 | #define BM_IR_DEBUG_RXDMAKICK 0x10 | ||
499 | #define BF_IR_DEBUG_RXDMAKICK(v) (((v) << 4) & 0x10) | ||
500 | #define BP_IR_DEBUG_TXDMAEND 3 | ||
501 | #define BM_IR_DEBUG_TXDMAEND 0x8 | ||
502 | #define BF_IR_DEBUG_TXDMAEND(v) (((v) << 3) & 0x8) | ||
503 | #define BP_IR_DEBUG_RXDMAEND 2 | ||
504 | #define BM_IR_DEBUG_RXDMAEND 0x4 | ||
505 | #define BF_IR_DEBUG_RXDMAEND(v) (((v) << 2) & 0x4) | ||
506 | #define BP_IR_DEBUG_TXDMAREQ 1 | ||
507 | #define BM_IR_DEBUG_TXDMAREQ 0x2 | ||
508 | #define BF_IR_DEBUG_TXDMAREQ(v) (((v) << 1) & 0x2) | ||
509 | #define BP_IR_DEBUG_RXDMAREQ 0 | ||
510 | #define BM_IR_DEBUG_RXDMAREQ 0x1 | ||
511 | #define BF_IR_DEBUG_RXDMAREQ(v) (((v) << 0) & 0x1) | ||
512 | |||
513 | /** | ||
514 | * Register: HW_IR_VERSION | ||
515 | * Address: 0xa0 | ||
516 | * SCT: no | ||
517 | */ | ||
518 | #define HW_IR_VERSION (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0)) | ||
519 | #define BP_IR_VERSION_MAJOR 24 | ||
520 | #define BM_IR_VERSION_MAJOR 0xff000000 | ||
521 | #define BF_IR_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
522 | #define BP_IR_VERSION_MINOR 16 | ||
523 | #define BM_IR_VERSION_MINOR 0xff0000 | ||
524 | #define BF_IR_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
525 | #define BP_IR_VERSION_STEP 0 | ||
526 | #define BM_IR_VERSION_STEP 0xffff | ||
527 | #define BF_IR_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
528 | |||
529 | #endif /* __HEADERGEN__IMX233__IR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h b/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h new file mode 100644 index 0000000000..2e56999191 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h | |||
@@ -0,0 +1,886 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__LCDIF__H__ | ||
24 | #define __HEADERGEN__IMX233__LCDIF__H__ | ||
25 | |||
26 | #define REGS_LCDIF_BASE (0x80030000) | ||
27 | |||
28 | #define REGS_LCDIF_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_LCDIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_LCDIF_CTRL (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0)) | ||
36 | #define HW_LCDIF_CTRL_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4)) | ||
37 | #define HW_LCDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8)) | ||
38 | #define HW_LCDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc)) | ||
39 | #define BP_LCDIF_CTRL_SFTRST 31 | ||
40 | #define BM_LCDIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_LCDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_LCDIF_CTRL_CLKGATE 30 | ||
43 | #define BM_LCDIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_LCDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_LCDIF_CTRL_YCBCR422_INPUT 29 | ||
46 | #define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000 | ||
47 | #define BF_LCDIF_CTRL_YCBCR422_INPUT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_LCDIF_CTRL_RSRVD0 28 | ||
49 | #define BM_LCDIF_CTRL_RSRVD0 0x10000000 | ||
50 | #define BF_LCDIF_CTRL_RSRVD0(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 27 | ||
52 | #define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x8000000 | ||
53 | #define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_LCDIF_CTRL_DATA_SHIFT_DIR 26 | ||
55 | #define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x4000000 | ||
56 | #define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 | ||
57 | #define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 | ||
58 | #define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v) (((v) << 26) & 0x4000000) | ||
59 | #define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v) ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 26) & 0x4000000) | ||
60 | #define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 | ||
61 | #define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x3e00000 | ||
62 | #define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) (((v) << 21) & 0x3e00000) | ||
63 | #define BP_LCDIF_CTRL_DVI_MODE 20 | ||
64 | #define BM_LCDIF_CTRL_DVI_MODE 0x100000 | ||
65 | #define BF_LCDIF_CTRL_DVI_MODE(v) (((v) << 20) & 0x100000) | ||
66 | #define BP_LCDIF_CTRL_BYPASS_COUNT 19 | ||
67 | #define BM_LCDIF_CTRL_BYPASS_COUNT 0x80000 | ||
68 | #define BF_LCDIF_CTRL_BYPASS_COUNT(v) (((v) << 19) & 0x80000) | ||
69 | #define BP_LCDIF_CTRL_VSYNC_MODE 18 | ||
70 | #define BM_LCDIF_CTRL_VSYNC_MODE 0x40000 | ||
71 | #define BF_LCDIF_CTRL_VSYNC_MODE(v) (((v) << 18) & 0x40000) | ||
72 | #define BP_LCDIF_CTRL_DOTCLK_MODE 17 | ||
73 | #define BM_LCDIF_CTRL_DOTCLK_MODE 0x20000 | ||
74 | #define BF_LCDIF_CTRL_DOTCLK_MODE(v) (((v) << 17) & 0x20000) | ||
75 | #define BP_LCDIF_CTRL_DATA_SELECT 16 | ||
76 | #define BM_LCDIF_CTRL_DATA_SELECT 0x10000 | ||
77 | #define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 | ||
78 | #define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 | ||
79 | #define BF_LCDIF_CTRL_DATA_SELECT(v) (((v) << 16) & 0x10000) | ||
80 | #define BF_LCDIF_CTRL_DATA_SELECT_V(v) ((BV_LCDIF_CTRL_DATA_SELECT__##v << 16) & 0x10000) | ||
81 | #define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 | ||
82 | #define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0xc000 | ||
83 | #define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 | ||
84 | #define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 | ||
85 | #define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 | ||
86 | #define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 | ||
87 | #define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 | ||
88 | #define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 | ||
89 | #define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) (((v) << 14) & 0xc000) | ||
90 | #define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE_V(v) ((BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__##v << 14) & 0xc000) | ||
91 | #define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12 | ||
92 | #define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x3000 | ||
93 | #define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 | ||
94 | #define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 | ||
95 | #define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 | ||
96 | #define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 | ||
97 | #define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 | ||
98 | #define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 | ||
99 | #define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) (((v) << 12) & 0x3000) | ||
100 | #define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE_V(v) ((BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__##v << 12) & 0x3000) | ||
101 | #define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 | ||
102 | #define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0xc00 | ||
103 | #define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 | ||
104 | #define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 | ||
105 | #define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 | ||
106 | #define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 | ||
107 | #define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) (((v) << 10) & 0xc00) | ||
108 | #define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH_V(v) ((BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__##v << 10) & 0xc00) | ||
109 | #define BP_LCDIF_CTRL_WORD_LENGTH 8 | ||
110 | #define BM_LCDIF_CTRL_WORD_LENGTH 0x300 | ||
111 | #define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 | ||
112 | #define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 | ||
113 | #define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 | ||
114 | #define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 | ||
115 | #define BF_LCDIF_CTRL_WORD_LENGTH(v) (((v) << 8) & 0x300) | ||
116 | #define BF_LCDIF_CTRL_WORD_LENGTH_V(v) ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 8) & 0x300) | ||
117 | #define BP_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 7 | ||
118 | #define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x80 | ||
119 | #define BF_LCDIF_CTRL_RGB_TO_YCBCR422_CSC(v) (((v) << 7) & 0x80) | ||
120 | #define BP_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 6 | ||
121 | #define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x40 | ||
122 | #define BF_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(v) (((v) << 6) & 0x40) | ||
123 | #define BP_LCDIF_CTRL_LCDIF_MASTER 5 | ||
124 | #define BM_LCDIF_CTRL_LCDIF_MASTER 0x20 | ||
125 | #define BF_LCDIF_CTRL_LCDIF_MASTER(v) (((v) << 5) & 0x20) | ||
126 | #define BP_LCDIF_CTRL_DMA_BURST_LENGTH 4 | ||
127 | #define BM_LCDIF_CTRL_DMA_BURST_LENGTH 0x10 | ||
128 | #define BF_LCDIF_CTRL_DMA_BURST_LENGTH(v) (((v) << 4) & 0x10) | ||
129 | #define BP_LCDIF_CTRL_DATA_FORMAT_16_BIT 3 | ||
130 | #define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x8 | ||
131 | #define BF_LCDIF_CTRL_DATA_FORMAT_16_BIT(v) (((v) << 3) & 0x8) | ||
132 | #define BP_LCDIF_CTRL_DATA_FORMAT_18_BIT 2 | ||
133 | #define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x4 | ||
134 | #define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 | ||
135 | #define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 | ||
136 | #define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT(v) (((v) << 2) & 0x4) | ||
137 | #define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT_V(v) ((BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__##v << 2) & 0x4) | ||
138 | #define BP_LCDIF_CTRL_DATA_FORMAT_24_BIT 1 | ||
139 | #define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x2 | ||
140 | #define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 | ||
141 | #define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 | ||
142 | #define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT(v) (((v) << 1) & 0x2) | ||
143 | #define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT_V(v) ((BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__##v << 1) & 0x2) | ||
144 | #define BP_LCDIF_CTRL_RUN 0 | ||
145 | #define BM_LCDIF_CTRL_RUN 0x1 | ||
146 | #define BF_LCDIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
147 | |||
148 | /** | ||
149 | * Register: HW_LCDIF_CTRL1 | ||
150 | * Address: 0x10 | ||
151 | * SCT: yes | ||
152 | */ | ||
153 | #define HW_LCDIF_CTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0)) | ||
154 | #define HW_LCDIF_CTRL1_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4)) | ||
155 | #define HW_LCDIF_CTRL1_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8)) | ||
156 | #define HW_LCDIF_CTRL1_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc)) | ||
157 | #define BP_LCDIF_CTRL1_RSRVD1 27 | ||
158 | #define BM_LCDIF_CTRL1_RSRVD1 0xf8000000 | ||
159 | #define BF_LCDIF_CTRL1_RSRVD1(v) (((v) << 27) & 0xf8000000) | ||
160 | #define BP_LCDIF_CTRL1_BM_ERROR_IRQ_EN 26 | ||
161 | #define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x4000000 | ||
162 | #define BF_LCDIF_CTRL1_BM_ERROR_IRQ_EN(v) (((v) << 26) & 0x4000000) | ||
163 | #define BP_LCDIF_CTRL1_BM_ERROR_IRQ 25 | ||
164 | #define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x2000000 | ||
165 | #define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 | ||
166 | #define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 | ||
167 | #define BF_LCDIF_CTRL1_BM_ERROR_IRQ(v) (((v) << 25) & 0x2000000) | ||
168 | #define BF_LCDIF_CTRL1_BM_ERROR_IRQ_V(v) ((BV_LCDIF_CTRL1_BM_ERROR_IRQ__##v << 25) & 0x2000000) | ||
169 | #define BP_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 24 | ||
170 | #define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x1000000 | ||
171 | #define BF_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(v) (((v) << 24) & 0x1000000) | ||
172 | #define BP_LCDIF_CTRL1_INTERLACE_FIELDS 23 | ||
173 | #define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x800000 | ||
174 | #define BF_LCDIF_CTRL1_INTERLACE_FIELDS(v) (((v) << 23) & 0x800000) | ||
175 | #define BP_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 22 | ||
176 | #define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x400000 | ||
177 | #define BF_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(v) (((v) << 22) & 0x400000) | ||
178 | #define BP_LCDIF_CTRL1_FIFO_CLEAR 21 | ||
179 | #define BM_LCDIF_CTRL1_FIFO_CLEAR 0x200000 | ||
180 | #define BF_LCDIF_CTRL1_FIFO_CLEAR(v) (((v) << 21) & 0x200000) | ||
181 | #define BP_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 20 | ||
182 | #define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x100000 | ||
183 | #define BF_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(v) (((v) << 20) & 0x100000) | ||
184 | #define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 | ||
185 | #define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0xf0000 | ||
186 | #define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) (((v) << 16) & 0xf0000) | ||
187 | #define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN 15 | ||
188 | #define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x8000 | ||
189 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
190 | #define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 14 | ||
191 | #define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x4000 | ||
192 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
193 | #define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 13 | ||
194 | #define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x2000 | ||
195 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
196 | #define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 12 | ||
197 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x1000 | ||
198 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
199 | #define BP_LCDIF_CTRL1_OVERFLOW_IRQ 11 | ||
200 | #define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x800 | ||
201 | #define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
202 | #define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 | ||
203 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v) (((v) << 11) & 0x800) | ||
204 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v) ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800) | ||
205 | #define BP_LCDIF_CTRL1_UNDERFLOW_IRQ 10 | ||
206 | #define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x400 | ||
207 | #define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 | ||
208 | #define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 | ||
209 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v) (((v) << 10) & 0x400) | ||
210 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v) ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400) | ||
211 | #define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 9 | ||
212 | #define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x200 | ||
213 | #define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 | ||
214 | #define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 | ||
215 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v) (((v) << 9) & 0x200) | ||
216 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v) ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200) | ||
217 | #define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ 8 | ||
218 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x100 | ||
219 | #define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 | ||
220 | #define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 | ||
221 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v) (((v) << 8) & 0x100) | ||
222 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v) ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100) | ||
223 | #define BP_LCDIF_CTRL1_RSRVD0 7 | ||
224 | #define BM_LCDIF_CTRL1_RSRVD0 0x80 | ||
225 | #define BF_LCDIF_CTRL1_RSRVD0(v) (((v) << 7) & 0x80) | ||
226 | #define BP_LCDIF_CTRL1_PAUSE_TRANSFER 6 | ||
227 | #define BM_LCDIF_CTRL1_PAUSE_TRANSFER 0x40 | ||
228 | #define BF_LCDIF_CTRL1_PAUSE_TRANSFER(v) (((v) << 6) & 0x40) | ||
229 | #define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN 5 | ||
230 | #define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN 0x20 | ||
231 | #define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN(v) (((v) << 5) & 0x20) | ||
232 | #define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ 4 | ||
233 | #define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ 0x10 | ||
234 | #define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST 0x0 | ||
235 | #define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST 0x1 | ||
236 | #define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ(v) (((v) << 4) & 0x10) | ||
237 | #define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_V(v) ((BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__##v << 4) & 0x10) | ||
238 | #define BP_LCDIF_CTRL1_LCD_CS_CTRL 3 | ||
239 | #define BM_LCDIF_CTRL1_LCD_CS_CTRL 0x8 | ||
240 | #define BF_LCDIF_CTRL1_LCD_CS_CTRL(v) (((v) << 3) & 0x8) | ||
241 | #define BP_LCDIF_CTRL1_BUSY_ENABLE 2 | ||
242 | #define BM_LCDIF_CTRL1_BUSY_ENABLE 0x4 | ||
243 | #define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 | ||
244 | #define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 | ||
245 | #define BF_LCDIF_CTRL1_BUSY_ENABLE(v) (((v) << 2) & 0x4) | ||
246 | #define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v) ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4) | ||
247 | #define BP_LCDIF_CTRL1_MODE86 1 | ||
248 | #define BM_LCDIF_CTRL1_MODE86 0x2 | ||
249 | #define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 | ||
250 | #define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 | ||
251 | #define BF_LCDIF_CTRL1_MODE86(v) (((v) << 1) & 0x2) | ||
252 | #define BF_LCDIF_CTRL1_MODE86_V(v) ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2) | ||
253 | #define BP_LCDIF_CTRL1_RESET 0 | ||
254 | #define BM_LCDIF_CTRL1_RESET 0x1 | ||
255 | #define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 | ||
256 | #define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 | ||
257 | #define BF_LCDIF_CTRL1_RESET(v) (((v) << 0) & 0x1) | ||
258 | #define BF_LCDIF_CTRL1_RESET_V(v) ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1) | ||
259 | |||
260 | /** | ||
261 | * Register: HW_LCDIF_TRANSFER_COUNT | ||
262 | * Address: 0x20 | ||
263 | * SCT: no | ||
264 | */ | ||
265 | #define HW_LCDIF_TRANSFER_COUNT (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20)) | ||
266 | #define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 | ||
267 | #define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xffff0000 | ||
268 | #define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) (((v) << 16) & 0xffff0000) | ||
269 | #define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 | ||
270 | #define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0xffff | ||
271 | #define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) (((v) << 0) & 0xffff) | ||
272 | |||
273 | /** | ||
274 | * Register: HW_LCDIF_CUR_BUF | ||
275 | * Address: 0x30 | ||
276 | * SCT: no | ||
277 | */ | ||
278 | #define HW_LCDIF_CUR_BUF (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30)) | ||
279 | #define BP_LCDIF_CUR_BUF_ADDR 0 | ||
280 | #define BM_LCDIF_CUR_BUF_ADDR 0xffffffff | ||
281 | #define BF_LCDIF_CUR_BUF_ADDR(v) (((v) << 0) & 0xffffffff) | ||
282 | |||
283 | /** | ||
284 | * Register: HW_LCDIF_NEXT_BUF | ||
285 | * Address: 0x40 | ||
286 | * SCT: no | ||
287 | */ | ||
288 | #define HW_LCDIF_NEXT_BUF (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40)) | ||
289 | #define BP_LCDIF_NEXT_BUF_ADDR 0 | ||
290 | #define BM_LCDIF_NEXT_BUF_ADDR 0xffffffff | ||
291 | #define BF_LCDIF_NEXT_BUF_ADDR(v) (((v) << 0) & 0xffffffff) | ||
292 | |||
293 | /** | ||
294 | * Register: HW_LCDIF_PAGETABLE | ||
295 | * Address: 0x50 | ||
296 | * SCT: no | ||
297 | */ | ||
298 | #define HW_LCDIF_PAGETABLE (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50)) | ||
299 | #define BP_LCDIF_PAGETABLE_BASE 14 | ||
300 | #define BM_LCDIF_PAGETABLE_BASE 0xffffc000 | ||
301 | #define BF_LCDIF_PAGETABLE_BASE(v) (((v) << 14) & 0xffffc000) | ||
302 | #define BP_LCDIF_PAGETABLE_RSVD1 2 | ||
303 | #define BM_LCDIF_PAGETABLE_RSVD1 0x3ffc | ||
304 | #define BF_LCDIF_PAGETABLE_RSVD1(v) (((v) << 2) & 0x3ffc) | ||
305 | #define BP_LCDIF_PAGETABLE_FLUSH 1 | ||
306 | #define BM_LCDIF_PAGETABLE_FLUSH 0x2 | ||
307 | #define BF_LCDIF_PAGETABLE_FLUSH(v) (((v) << 1) & 0x2) | ||
308 | #define BP_LCDIF_PAGETABLE_ENABLE 0 | ||
309 | #define BM_LCDIF_PAGETABLE_ENABLE 0x1 | ||
310 | #define BF_LCDIF_PAGETABLE_ENABLE(v) (((v) << 0) & 0x1) | ||
311 | |||
312 | /** | ||
313 | * Register: HW_LCDIF_TIMING | ||
314 | * Address: 0x60 | ||
315 | * SCT: no | ||
316 | */ | ||
317 | #define HW_LCDIF_TIMING (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60)) | ||
318 | #define BP_LCDIF_TIMING_CMD_HOLD 24 | ||
319 | #define BM_LCDIF_TIMING_CMD_HOLD 0xff000000 | ||
320 | #define BF_LCDIF_TIMING_CMD_HOLD(v) (((v) << 24) & 0xff000000) | ||
321 | #define BP_LCDIF_TIMING_CMD_SETUP 16 | ||
322 | #define BM_LCDIF_TIMING_CMD_SETUP 0xff0000 | ||
323 | #define BF_LCDIF_TIMING_CMD_SETUP(v) (((v) << 16) & 0xff0000) | ||
324 | #define BP_LCDIF_TIMING_DATA_HOLD 8 | ||
325 | #define BM_LCDIF_TIMING_DATA_HOLD 0xff00 | ||
326 | #define BF_LCDIF_TIMING_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
327 | #define BP_LCDIF_TIMING_DATA_SETUP 0 | ||
328 | #define BM_LCDIF_TIMING_DATA_SETUP 0xff | ||
329 | #define BF_LCDIF_TIMING_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_LCDIF_VDCTRL0 | ||
333 | * Address: 0x70 | ||
334 | * SCT: yes | ||
335 | */ | ||
336 | #define HW_LCDIF_VDCTRL0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x0)) | ||
337 | #define HW_LCDIF_VDCTRL0_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x4)) | ||
338 | #define HW_LCDIF_VDCTRL0_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x8)) | ||
339 | #define HW_LCDIF_VDCTRL0_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0xc)) | ||
340 | #define BP_LCDIF_VDCTRL0_RSRVD2 30 | ||
341 | #define BM_LCDIF_VDCTRL0_RSRVD2 0xc0000000 | ||
342 | #define BF_LCDIF_VDCTRL0_RSRVD2(v) (((v) << 30) & 0xc0000000) | ||
343 | #define BP_LCDIF_VDCTRL0_VSYNC_OEB 29 | ||
344 | #define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 | ||
345 | #define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 | ||
346 | #define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 | ||
347 | #define BF_LCDIF_VDCTRL0_VSYNC_OEB(v) (((v) << 29) & 0x20000000) | ||
348 | #define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v) ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000) | ||
349 | #define BP_LCDIF_VDCTRL0_ENABLE_PRESENT 28 | ||
350 | #define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 | ||
351 | #define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
352 | #define BP_LCDIF_VDCTRL0_VSYNC_POL 27 | ||
353 | #define BM_LCDIF_VDCTRL0_VSYNC_POL 0x8000000 | ||
354 | #define BF_LCDIF_VDCTRL0_VSYNC_POL(v) (((v) << 27) & 0x8000000) | ||
355 | #define BP_LCDIF_VDCTRL0_HSYNC_POL 26 | ||
356 | #define BM_LCDIF_VDCTRL0_HSYNC_POL 0x4000000 | ||
357 | #define BF_LCDIF_VDCTRL0_HSYNC_POL(v) (((v) << 26) & 0x4000000) | ||
358 | #define BP_LCDIF_VDCTRL0_DOTCLK_POL 25 | ||
359 | #define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x2000000 | ||
360 | #define BF_LCDIF_VDCTRL0_DOTCLK_POL(v) (((v) << 25) & 0x2000000) | ||
361 | #define BP_LCDIF_VDCTRL0_ENABLE_POL 24 | ||
362 | #define BM_LCDIF_VDCTRL0_ENABLE_POL 0x1000000 | ||
363 | #define BF_LCDIF_VDCTRL0_ENABLE_POL(v) (((v) << 24) & 0x1000000) | ||
364 | #define BP_LCDIF_VDCTRL0_RSRVD1 22 | ||
365 | #define BM_LCDIF_VDCTRL0_RSRVD1 0xc00000 | ||
366 | #define BF_LCDIF_VDCTRL0_RSRVD1(v) (((v) << 22) & 0xc00000) | ||
367 | #define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 21 | ||
368 | #define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x200000 | ||
369 | #define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v) (((v) << 21) & 0x200000) | ||
370 | #define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 20 | ||
371 | #define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x100000 | ||
372 | #define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v) (((v) << 20) & 0x100000) | ||
373 | #define BP_LCDIF_VDCTRL0_HALF_LINE 19 | ||
374 | #define BM_LCDIF_VDCTRL0_HALF_LINE 0x80000 | ||
375 | #define BF_LCDIF_VDCTRL0_HALF_LINE(v) (((v) << 19) & 0x80000) | ||
376 | #define BP_LCDIF_VDCTRL0_HALF_LINE_MODE 18 | ||
377 | #define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x40000 | ||
378 | #define BF_LCDIF_VDCTRL0_HALF_LINE_MODE(v) (((v) << 18) & 0x40000) | ||
379 | #define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 | ||
380 | #define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x3ffff | ||
381 | #define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) (((v) << 0) & 0x3ffff) | ||
382 | |||
383 | /** | ||
384 | * Register: HW_LCDIF_VDCTRL1 | ||
385 | * Address: 0x80 | ||
386 | * SCT: no | ||
387 | */ | ||
388 | #define HW_LCDIF_VDCTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80)) | ||
389 | #define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 | ||
390 | #define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xffffffff | ||
391 | #define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (((v) << 0) & 0xffffffff) | ||
392 | |||
393 | /** | ||
394 | * Register: HW_LCDIF_VDCTRL2 | ||
395 | * Address: 0x90 | ||
396 | * SCT: no | ||
397 | */ | ||
398 | #define HW_LCDIF_VDCTRL2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90)) | ||
399 | #define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 | ||
400 | #define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xff000000 | ||
401 | #define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) (((v) << 24) & 0xff000000) | ||
402 | #define BP_LCDIF_VDCTRL2_RSRVD0 18 | ||
403 | #define BM_LCDIF_VDCTRL2_RSRVD0 0xfc0000 | ||
404 | #define BF_LCDIF_VDCTRL2_RSRVD0(v) (((v) << 18) & 0xfc0000) | ||
405 | #define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 | ||
406 | #define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x3ffff | ||
407 | #define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) (((v) << 0) & 0x3ffff) | ||
408 | |||
409 | /** | ||
410 | * Register: HW_LCDIF_VDCTRL3 | ||
411 | * Address: 0xa0 | ||
412 | * SCT: no | ||
413 | */ | ||
414 | #define HW_LCDIF_VDCTRL3 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0)) | ||
415 | #define BP_LCDIF_VDCTRL3_RSRVD0 30 | ||
416 | #define BM_LCDIF_VDCTRL3_RSRVD0 0xc0000000 | ||
417 | #define BF_LCDIF_VDCTRL3_RSRVD0(v) (((v) << 30) & 0xc0000000) | ||
418 | #define BP_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 29 | ||
419 | #define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 | ||
420 | #define BF_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(v) (((v) << 29) & 0x20000000) | ||
421 | #define BP_LCDIF_VDCTRL3_VSYNC_ONLY 28 | ||
422 | #define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 | ||
423 | #define BF_LCDIF_VDCTRL3_VSYNC_ONLY(v) (((v) << 28) & 0x10000000) | ||
424 | #define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 | ||
425 | #define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0xfff0000 | ||
426 | #define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 16) & 0xfff0000) | ||
427 | #define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 | ||
428 | #define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0xffff | ||
429 | #define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) (((v) << 0) & 0xffff) | ||
430 | |||
431 | /** | ||
432 | * Register: HW_LCDIF_VDCTRL4 | ||
433 | * Address: 0xb0 | ||
434 | * SCT: no | ||
435 | */ | ||
436 | #define HW_LCDIF_VDCTRL4 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0)) | ||
437 | #define BP_LCDIF_VDCTRL4_RSRVD0 19 | ||
438 | #define BM_LCDIF_VDCTRL4_RSRVD0 0xfff80000 | ||
439 | #define BF_LCDIF_VDCTRL4_RSRVD0(v) (((v) << 19) & 0xfff80000) | ||
440 | #define BP_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 18 | ||
441 | #define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x40000 | ||
442 | #define BF_LCDIF_VDCTRL4_SYNC_SIGNALS_ON(v) (((v) << 18) & 0x40000) | ||
443 | #define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 | ||
444 | #define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x3ffff | ||
445 | #define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x3ffff) | ||
446 | |||
447 | /** | ||
448 | * Register: HW_LCDIF_DVICTRL0 | ||
449 | * Address: 0xc0 | ||
450 | * SCT: no | ||
451 | */ | ||
452 | #define HW_LCDIF_DVICTRL0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0)) | ||
453 | #define BP_LCDIF_DVICTRL0_START_TRS 31 | ||
454 | #define BM_LCDIF_DVICTRL0_START_TRS 0x80000000 | ||
455 | #define BF_LCDIF_DVICTRL0_START_TRS(v) (((v) << 31) & 0x80000000) | ||
456 | #define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 | ||
457 | #define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7ff00000 | ||
458 | #define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) (((v) << 20) & 0x7ff00000) | ||
459 | #define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 | ||
460 | #define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0xffc00 | ||
461 | #define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00) | ||
462 | #define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 | ||
463 | #define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x3ff | ||
464 | #define BF_LCDIF_DVICTRL0_V_LINES_CNT(v) (((v) << 0) & 0x3ff) | ||
465 | |||
466 | /** | ||
467 | * Register: HW_LCDIF_DVICTRL1 | ||
468 | * Address: 0xd0 | ||
469 | * SCT: no | ||
470 | */ | ||
471 | #define HW_LCDIF_DVICTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0)) | ||
472 | #define BP_LCDIF_DVICTRL1_RSRVD0 30 | ||
473 | #define BM_LCDIF_DVICTRL1_RSRVD0 0xc0000000 | ||
474 | #define BF_LCDIF_DVICTRL1_RSRVD0(v) (((v) << 30) & 0xc0000000) | ||
475 | #define BP_LCDIF_DVICTRL1_F1_START_LINE 20 | ||
476 | #define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3ff00000 | ||
477 | #define BF_LCDIF_DVICTRL1_F1_START_LINE(v) (((v) << 20) & 0x3ff00000) | ||
478 | #define BP_LCDIF_DVICTRL1_F1_END_LINE 10 | ||
479 | #define BM_LCDIF_DVICTRL1_F1_END_LINE 0xffc00 | ||
480 | #define BF_LCDIF_DVICTRL1_F1_END_LINE(v) (((v) << 10) & 0xffc00) | ||
481 | #define BP_LCDIF_DVICTRL1_F2_START_LINE 0 | ||
482 | #define BM_LCDIF_DVICTRL1_F2_START_LINE 0x3ff | ||
483 | #define BF_LCDIF_DVICTRL1_F2_START_LINE(v) (((v) << 0) & 0x3ff) | ||
484 | |||
485 | /** | ||
486 | * Register: HW_LCDIF_DVICTRL2 | ||
487 | * Address: 0xe0 | ||
488 | * SCT: no | ||
489 | */ | ||
490 | #define HW_LCDIF_DVICTRL2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0)) | ||
491 | #define BP_LCDIF_DVICTRL2_RSRVD0 30 | ||
492 | #define BM_LCDIF_DVICTRL2_RSRVD0 0xc0000000 | ||
493 | #define BF_LCDIF_DVICTRL2_RSRVD0(v) (((v) << 30) & 0xc0000000) | ||
494 | #define BP_LCDIF_DVICTRL2_F2_END_LINE 20 | ||
495 | #define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3ff00000 | ||
496 | #define BF_LCDIF_DVICTRL2_F2_END_LINE(v) (((v) << 20) & 0x3ff00000) | ||
497 | #define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 | ||
498 | #define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0xffc00 | ||
499 | #define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) (((v) << 10) & 0xffc00) | ||
500 | #define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 | ||
501 | #define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x3ff | ||
502 | #define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) (((v) << 0) & 0x3ff) | ||
503 | |||
504 | /** | ||
505 | * Register: HW_LCDIF_DVICTRL3 | ||
506 | * Address: 0xf0 | ||
507 | * SCT: no | ||
508 | */ | ||
509 | #define HW_LCDIF_DVICTRL3 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xf0)) | ||
510 | #define BP_LCDIF_DVICTRL3_RSRVD1 26 | ||
511 | #define BM_LCDIF_DVICTRL3_RSRVD1 0xfc000000 | ||
512 | #define BF_LCDIF_DVICTRL3_RSRVD1(v) (((v) << 26) & 0xfc000000) | ||
513 | #define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 | ||
514 | #define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3ff0000 | ||
515 | #define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) (((v) << 16) & 0x3ff0000) | ||
516 | #define BP_LCDIF_DVICTRL3_RSRVD0 10 | ||
517 | #define BM_LCDIF_DVICTRL3_RSRVD0 0xfc00 | ||
518 | #define BF_LCDIF_DVICTRL3_RSRVD0(v) (((v) << 10) & 0xfc00) | ||
519 | #define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 | ||
520 | #define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x3ff | ||
521 | #define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) (((v) << 0) & 0x3ff) | ||
522 | |||
523 | /** | ||
524 | * Register: HW_LCDIF_DVICTRL4 | ||
525 | * Address: 0x100 | ||
526 | * SCT: no | ||
527 | */ | ||
528 | #define HW_LCDIF_DVICTRL4 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x100)) | ||
529 | #define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 | ||
530 | #define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xff000000 | ||
531 | #define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) (((v) << 24) & 0xff000000) | ||
532 | #define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 | ||
533 | #define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0xff0000 | ||
534 | #define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) (((v) << 16) & 0xff0000) | ||
535 | #define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 | ||
536 | #define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0xff00 | ||
537 | #define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) (((v) << 8) & 0xff00) | ||
538 | #define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 | ||
539 | #define BM_LCDIF_DVICTRL4_H_FILL_CNT 0xff | ||
540 | #define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) (((v) << 0) & 0xff) | ||
541 | |||
542 | /** | ||
543 | * Register: HW_LCDIF_CSC_COEFF0 | ||
544 | * Address: 0x110 | ||
545 | * SCT: no | ||
546 | */ | ||
547 | #define HW_LCDIF_CSC_COEFF0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x110)) | ||
548 | #define BP_LCDIF_CSC_COEFF0_RSRVD1 26 | ||
549 | #define BM_LCDIF_CSC_COEFF0_RSRVD1 0xfc000000 | ||
550 | #define BF_LCDIF_CSC_COEFF0_RSRVD1(v) (((v) << 26) & 0xfc000000) | ||
551 | #define BP_LCDIF_CSC_COEFF0_C0 16 | ||
552 | #define BM_LCDIF_CSC_COEFF0_C0 0x3ff0000 | ||
553 | #define BF_LCDIF_CSC_COEFF0_C0(v) (((v) << 16) & 0x3ff0000) | ||
554 | #define BP_LCDIF_CSC_COEFF0_RSRVD0 2 | ||
555 | #define BM_LCDIF_CSC_COEFF0_RSRVD0 0xfffc | ||
556 | #define BF_LCDIF_CSC_COEFF0_RSRVD0(v) (((v) << 2) & 0xfffc) | ||
557 | #define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 | ||
558 | #define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x3 | ||
559 | #define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 | ||
560 | #define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 | ||
561 | #define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 | ||
562 | #define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 | ||
563 | #define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) (((v) << 0) & 0x3) | ||
564 | #define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_V(v) ((BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__##v << 0) & 0x3) | ||
565 | |||
566 | /** | ||
567 | * Register: HW_LCDIF_CSC_COEFF1 | ||
568 | * Address: 0x120 | ||
569 | * SCT: no | ||
570 | */ | ||
571 | #define HW_LCDIF_CSC_COEFF1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x120)) | ||
572 | #define BP_LCDIF_CSC_COEFF1_RSRVD1 26 | ||
573 | #define BM_LCDIF_CSC_COEFF1_RSRVD1 0xfc000000 | ||
574 | #define BF_LCDIF_CSC_COEFF1_RSRVD1(v) (((v) << 26) & 0xfc000000) | ||
575 | #define BP_LCDIF_CSC_COEFF1_C2 16 | ||
576 | #define BM_LCDIF_CSC_COEFF1_C2 0x3ff0000 | ||
577 | #define BF_LCDIF_CSC_COEFF1_C2(v) (((v) << 16) & 0x3ff0000) | ||
578 | #define BP_LCDIF_CSC_COEFF1_RSRVD0 10 | ||
579 | #define BM_LCDIF_CSC_COEFF1_RSRVD0 0xfc00 | ||
580 | #define BF_LCDIF_CSC_COEFF1_RSRVD0(v) (((v) << 10) & 0xfc00) | ||
581 | #define BP_LCDIF_CSC_COEFF1_C1 0 | ||
582 | #define BM_LCDIF_CSC_COEFF1_C1 0x3ff | ||
583 | #define BF_LCDIF_CSC_COEFF1_C1(v) (((v) << 0) & 0x3ff) | ||
584 | |||
585 | /** | ||
586 | * Register: HW_LCDIF_CSC_COEFF2 | ||
587 | * Address: 0x130 | ||
588 | * SCT: no | ||
589 | */ | ||
590 | #define HW_LCDIF_CSC_COEFF2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x130)) | ||
591 | #define BP_LCDIF_CSC_COEFF2_RSRVD1 26 | ||
592 | #define BM_LCDIF_CSC_COEFF2_RSRVD1 0xfc000000 | ||
593 | #define BF_LCDIF_CSC_COEFF2_RSRVD1(v) (((v) << 26) & 0xfc000000) | ||
594 | #define BP_LCDIF_CSC_COEFF2_C4 16 | ||
595 | #define BM_LCDIF_CSC_COEFF2_C4 0x3ff0000 | ||
596 | #define BF_LCDIF_CSC_COEFF2_C4(v) (((v) << 16) & 0x3ff0000) | ||
597 | #define BP_LCDIF_CSC_COEFF2_RSRVD0 10 | ||
598 | #define BM_LCDIF_CSC_COEFF2_RSRVD0 0xfc00 | ||
599 | #define BF_LCDIF_CSC_COEFF2_RSRVD0(v) (((v) << 10) & 0xfc00) | ||
600 | #define BP_LCDIF_CSC_COEFF2_C3 0 | ||
601 | #define BM_LCDIF_CSC_COEFF2_C3 0x3ff | ||
602 | #define BF_LCDIF_CSC_COEFF2_C3(v) (((v) << 0) & 0x3ff) | ||
603 | |||
604 | /** | ||
605 | * Register: HW_LCDIF_CSC_COEFF3 | ||
606 | * Address: 0x140 | ||
607 | * SCT: no | ||
608 | */ | ||
609 | #define HW_LCDIF_CSC_COEFF3 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x140)) | ||
610 | #define BP_LCDIF_CSC_COEFF3_RSRVD1 26 | ||
611 | #define BM_LCDIF_CSC_COEFF3_RSRVD1 0xfc000000 | ||
612 | #define BF_LCDIF_CSC_COEFF3_RSRVD1(v) (((v) << 26) & 0xfc000000) | ||
613 | #define BP_LCDIF_CSC_COEFF3_C6 16 | ||
614 | #define BM_LCDIF_CSC_COEFF3_C6 0x3ff0000 | ||
615 | #define BF_LCDIF_CSC_COEFF3_C6(v) (((v) << 16) & 0x3ff0000) | ||
616 | #define BP_LCDIF_CSC_COEFF3_RSRVD0 10 | ||
617 | #define BM_LCDIF_CSC_COEFF3_RSRVD0 0xfc00 | ||
618 | #define BF_LCDIF_CSC_COEFF3_RSRVD0(v) (((v) << 10) & 0xfc00) | ||
619 | #define BP_LCDIF_CSC_COEFF3_C5 0 | ||
620 | #define BM_LCDIF_CSC_COEFF3_C5 0x3ff | ||
621 | #define BF_LCDIF_CSC_COEFF3_C5(v) (((v) << 0) & 0x3ff) | ||
622 | |||
623 | /** | ||
624 | * Register: HW_LCDIF_CSC_COEFF4 | ||
625 | * Address: 0x150 | ||
626 | * SCT: no | ||
627 | */ | ||
628 | #define HW_LCDIF_CSC_COEFF4 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x150)) | ||
629 | #define BP_LCDIF_CSC_COEFF4_RSRVD1 26 | ||
630 | #define BM_LCDIF_CSC_COEFF4_RSRVD1 0xfc000000 | ||
631 | #define BF_LCDIF_CSC_COEFF4_RSRVD1(v) (((v) << 26) & 0xfc000000) | ||
632 | #define BP_LCDIF_CSC_COEFF4_C8 16 | ||
633 | #define BM_LCDIF_CSC_COEFF4_C8 0x3ff0000 | ||
634 | #define BF_LCDIF_CSC_COEFF4_C8(v) (((v) << 16) & 0x3ff0000) | ||
635 | #define BP_LCDIF_CSC_COEFF4_RSRVD0 10 | ||
636 | #define BM_LCDIF_CSC_COEFF4_RSRVD0 0xfc00 | ||
637 | #define BF_LCDIF_CSC_COEFF4_RSRVD0(v) (((v) << 10) & 0xfc00) | ||
638 | #define BP_LCDIF_CSC_COEFF4_C7 0 | ||
639 | #define BM_LCDIF_CSC_COEFF4_C7 0x3ff | ||
640 | #define BF_LCDIF_CSC_COEFF4_C7(v) (((v) << 0) & 0x3ff) | ||
641 | |||
642 | /** | ||
643 | * Register: HW_LCDIF_CSC_OFFSET | ||
644 | * Address: 0x160 | ||
645 | * SCT: no | ||
646 | */ | ||
647 | #define HW_LCDIF_CSC_OFFSET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x160)) | ||
648 | #define BP_LCDIF_CSC_OFFSET_RSRVD1 25 | ||
649 | #define BM_LCDIF_CSC_OFFSET_RSRVD1 0xfe000000 | ||
650 | #define BF_LCDIF_CSC_OFFSET_RSRVD1(v) (((v) << 25) & 0xfe000000) | ||
651 | #define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 | ||
652 | #define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x1ff0000 | ||
653 | #define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) (((v) << 16) & 0x1ff0000) | ||
654 | #define BP_LCDIF_CSC_OFFSET_RSRVD0 9 | ||
655 | #define BM_LCDIF_CSC_OFFSET_RSRVD0 0xfe00 | ||
656 | #define BF_LCDIF_CSC_OFFSET_RSRVD0(v) (((v) << 9) & 0xfe00) | ||
657 | #define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 | ||
658 | #define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x1ff | ||
659 | #define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) (((v) << 0) & 0x1ff) | ||
660 | |||
661 | /** | ||
662 | * Register: HW_LCDIF_CSC_LIMIT | ||
663 | * Address: 0x170 | ||
664 | * SCT: no | ||
665 | */ | ||
666 | #define HW_LCDIF_CSC_LIMIT (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x170)) | ||
667 | #define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 | ||
668 | #define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xff000000 | ||
669 | #define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) (((v) << 24) & 0xff000000) | ||
670 | #define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 | ||
671 | #define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0xff0000 | ||
672 | #define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) (((v) << 16) & 0xff0000) | ||
673 | #define BP_LCDIF_CSC_LIMIT_Y_MIN 8 | ||
674 | #define BM_LCDIF_CSC_LIMIT_Y_MIN 0xff00 | ||
675 | #define BF_LCDIF_CSC_LIMIT_Y_MIN(v) (((v) << 8) & 0xff00) | ||
676 | #define BP_LCDIF_CSC_LIMIT_Y_MAX 0 | ||
677 | #define BM_LCDIF_CSC_LIMIT_Y_MAX 0xff | ||
678 | #define BF_LCDIF_CSC_LIMIT_Y_MAX(v) (((v) << 0) & 0xff) | ||
679 | |||
680 | /** | ||
681 | * Register: HW_LCDIF_PIN_SHARING_CTRL0 | ||
682 | * Address: 0x180 | ||
683 | * SCT: yes | ||
684 | */ | ||
685 | #define HW_LCDIF_PIN_SHARING_CTRL0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x0)) | ||
686 | #define HW_LCDIF_PIN_SHARING_CTRL0_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x4)) | ||
687 | #define HW_LCDIF_PIN_SHARING_CTRL0_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x8)) | ||
688 | #define HW_LCDIF_PIN_SHARING_CTRL0_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0xc)) | ||
689 | #define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1 6 | ||
690 | #define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1 0xffffffc0 | ||
691 | #define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v) (((v) << 6) & 0xffffffc0) | ||
692 | #define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 4 | ||
693 | #define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 0x30 | ||
694 | #define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE 0x0 | ||
695 | #define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD 0x1 | ||
696 | #define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL 0x2 | ||
697 | #define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL 0x3 | ||
698 | #define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v) (((v) << 4) & 0x30) | ||
699 | #define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE_V(v) ((BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__##v << 4) & 0x30) | ||
700 | #define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD0 3 | ||
701 | #define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0 0x8 | ||
702 | #define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD0(v) (((v) << 3) & 0x8) | ||
703 | #define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN 2 | ||
704 | #define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN 0x4 | ||
705 | #define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN(v) (((v) << 2) & 0x4) | ||
706 | #define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ 1 | ||
707 | #define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ 0x2 | ||
708 | #define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST 0x0 | ||
709 | #define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST 0x1 | ||
710 | #define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ(v) (((v) << 1) & 0x2) | ||
711 | #define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_V(v) ((BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__##v << 1) & 0x2) | ||
712 | #define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE 0 | ||
713 | #define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE 0x1 | ||
714 | #define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE(v) (((v) << 0) & 0x1) | ||
715 | |||
716 | /** | ||
717 | * Register: HW_LCDIF_PIN_SHARING_CTRL1 | ||
718 | * Address: 0x190 | ||
719 | * SCT: no | ||
720 | */ | ||
721 | #define HW_LCDIF_PIN_SHARING_CTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x190)) | ||
722 | #define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0 | ||
723 | #define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0xffffffff | ||
724 | #define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v) (((v) << 0) & 0xffffffff) | ||
725 | |||
726 | /** | ||
727 | * Register: HW_LCDIF_PIN_SHARING_CTRL2 | ||
728 | * Address: 0x1a0 | ||
729 | * SCT: no | ||
730 | */ | ||
731 | #define HW_LCDIF_PIN_SHARING_CTRL2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1a0)) | ||
732 | #define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0 | ||
733 | #define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0xffffffff | ||
734 | #define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v) (((v) << 0) & 0xffffffff) | ||
735 | |||
736 | /** | ||
737 | * Register: HW_LCDIF_DATA | ||
738 | * Address: 0x1b0 | ||
739 | * SCT: no | ||
740 | */ | ||
741 | #define HW_LCDIF_DATA (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1b0)) | ||
742 | #define BP_LCDIF_DATA_DATA_THREE 24 | ||
743 | #define BM_LCDIF_DATA_DATA_THREE 0xff000000 | ||
744 | #define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000) | ||
745 | #define BP_LCDIF_DATA_DATA_TWO 16 | ||
746 | #define BM_LCDIF_DATA_DATA_TWO 0xff0000 | ||
747 | #define BF_LCDIF_DATA_DATA_TWO(v) (((v) << 16) & 0xff0000) | ||
748 | #define BP_LCDIF_DATA_DATA_ONE 8 | ||
749 | #define BM_LCDIF_DATA_DATA_ONE 0xff00 | ||
750 | #define BF_LCDIF_DATA_DATA_ONE(v) (((v) << 8) & 0xff00) | ||
751 | #define BP_LCDIF_DATA_DATA_ZERO 0 | ||
752 | #define BM_LCDIF_DATA_DATA_ZERO 0xff | ||
753 | #define BF_LCDIF_DATA_DATA_ZERO(v) (((v) << 0) & 0xff) | ||
754 | |||
755 | /** | ||
756 | * Register: HW_LCDIF_BM_ERROR_STAT | ||
757 | * Address: 0x1c0 | ||
758 | * SCT: no | ||
759 | */ | ||
760 | #define HW_LCDIF_BM_ERROR_STAT (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1c0)) | ||
761 | #define BP_LCDIF_BM_ERROR_STAT_ADDR 0 | ||
762 | #define BM_LCDIF_BM_ERROR_STAT_ADDR 0xffffffff | ||
763 | #define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (((v) << 0) & 0xffffffff) | ||
764 | |||
765 | /** | ||
766 | * Register: HW_LCDIF_STAT | ||
767 | * Address: 0x1d0 | ||
768 | * SCT: no | ||
769 | */ | ||
770 | #define HW_LCDIF_STAT (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1d0)) | ||
771 | #define BP_LCDIF_STAT_PRESENT 31 | ||
772 | #define BM_LCDIF_STAT_PRESENT 0x80000000 | ||
773 | #define BF_LCDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
774 | #define BP_LCDIF_STAT_DMA_REQ 30 | ||
775 | #define BM_LCDIF_STAT_DMA_REQ 0x40000000 | ||
776 | #define BF_LCDIF_STAT_DMA_REQ(v) (((v) << 30) & 0x40000000) | ||
777 | #define BP_LCDIF_STAT_LFIFO_FULL 29 | ||
778 | #define BM_LCDIF_STAT_LFIFO_FULL 0x20000000 | ||
779 | #define BF_LCDIF_STAT_LFIFO_FULL(v) (((v) << 29) & 0x20000000) | ||
780 | #define BP_LCDIF_STAT_LFIFO_EMPTY 28 | ||
781 | #define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000 | ||
782 | #define BF_LCDIF_STAT_LFIFO_EMPTY(v) (((v) << 28) & 0x10000000) | ||
783 | #define BP_LCDIF_STAT_TXFIFO_FULL 27 | ||
784 | #define BM_LCDIF_STAT_TXFIFO_FULL 0x8000000 | ||
785 | #define BF_LCDIF_STAT_TXFIFO_FULL(v) (((v) << 27) & 0x8000000) | ||
786 | #define BP_LCDIF_STAT_TXFIFO_EMPTY 26 | ||
787 | #define BM_LCDIF_STAT_TXFIFO_EMPTY 0x4000000 | ||
788 | #define BF_LCDIF_STAT_TXFIFO_EMPTY(v) (((v) << 26) & 0x4000000) | ||
789 | #define BP_LCDIF_STAT_BUSY 25 | ||
790 | #define BM_LCDIF_STAT_BUSY 0x2000000 | ||
791 | #define BF_LCDIF_STAT_BUSY(v) (((v) << 25) & 0x2000000) | ||
792 | #define BP_LCDIF_STAT_DVI_CURRENT_FIELD 24 | ||
793 | #define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x1000000 | ||
794 | #define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v) (((v) << 24) & 0x1000000) | ||
795 | #define BP_LCDIF_STAT_RSRVD0 0 | ||
796 | #define BM_LCDIF_STAT_RSRVD0 0xffffff | ||
797 | #define BF_LCDIF_STAT_RSRVD0(v) (((v) << 0) & 0xffffff) | ||
798 | |||
799 | /** | ||
800 | * Register: HW_LCDIF_VERSION | ||
801 | * Address: 0x1e0 | ||
802 | * SCT: no | ||
803 | */ | ||
804 | #define HW_LCDIF_VERSION (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1e0)) | ||
805 | #define BP_LCDIF_VERSION_MAJOR 24 | ||
806 | #define BM_LCDIF_VERSION_MAJOR 0xff000000 | ||
807 | #define BF_LCDIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
808 | #define BP_LCDIF_VERSION_MINOR 16 | ||
809 | #define BM_LCDIF_VERSION_MINOR 0xff0000 | ||
810 | #define BF_LCDIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
811 | #define BP_LCDIF_VERSION_STEP 0 | ||
812 | #define BM_LCDIF_VERSION_STEP 0xffff | ||
813 | #define BF_LCDIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
814 | |||
815 | /** | ||
816 | * Register: HW_LCDIF_DEBUG0 | ||
817 | * Address: 0x1f0 | ||
818 | * SCT: no | ||
819 | */ | ||
820 | #define HW_LCDIF_DEBUG0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1f0)) | ||
821 | #define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED 31 | ||
822 | #define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 | ||
823 | #define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v) (((v) << 31) & 0x80000000) | ||
824 | #define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 30 | ||
825 | #define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 | ||
826 | #define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v) (((v) << 30) & 0x40000000) | ||
827 | #define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 29 | ||
828 | #define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 | ||
829 | #define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v) (((v) << 29) & 0x20000000) | ||
830 | #define BP_LCDIF_DEBUG0_DMACMDKICK 28 | ||
831 | #define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 | ||
832 | #define BF_LCDIF_DEBUG0_DMACMDKICK(v) (((v) << 28) & 0x10000000) | ||
833 | #define BP_LCDIF_DEBUG0_ENABLE 27 | ||
834 | #define BM_LCDIF_DEBUG0_ENABLE 0x8000000 | ||
835 | #define BF_LCDIF_DEBUG0_ENABLE(v) (((v) << 27) & 0x8000000) | ||
836 | #define BP_LCDIF_DEBUG0_HSYNC 26 | ||
837 | #define BM_LCDIF_DEBUG0_HSYNC 0x4000000 | ||
838 | #define BF_LCDIF_DEBUG0_HSYNC(v) (((v) << 26) & 0x4000000) | ||
839 | #define BP_LCDIF_DEBUG0_VSYNC 25 | ||
840 | #define BM_LCDIF_DEBUG0_VSYNC 0x2000000 | ||
841 | #define BF_LCDIF_DEBUG0_VSYNC(v) (((v) << 25) & 0x2000000) | ||
842 | #define BP_LCDIF_DEBUG0_CUR_FRAME_TX 24 | ||
843 | #define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x1000000 | ||
844 | #define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v) (((v) << 24) & 0x1000000) | ||
845 | #define BP_LCDIF_DEBUG0_EMPTY_WORD 23 | ||
846 | #define BM_LCDIF_DEBUG0_EMPTY_WORD 0x800000 | ||
847 | #define BF_LCDIF_DEBUG0_EMPTY_WORD(v) (((v) << 23) & 0x800000) | ||
848 | #define BP_LCDIF_DEBUG0_CUR_STATE 16 | ||
849 | #define BM_LCDIF_DEBUG0_CUR_STATE 0x7f0000 | ||
850 | #define BF_LCDIF_DEBUG0_CUR_STATE(v) (((v) << 16) & 0x7f0000) | ||
851 | #define BP_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 15 | ||
852 | #define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x8000 | ||
853 | #define BF_LCDIF_DEBUG0_PXP_LCDIF_B0_READY(v) (((v) << 15) & 0x8000) | ||
854 | #define BP_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 14 | ||
855 | #define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x4000 | ||
856 | #define BF_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE(v) (((v) << 14) & 0x4000) | ||
857 | #define BP_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 13 | ||
858 | #define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x2000 | ||
859 | #define BF_LCDIF_DEBUG0_PXP_LCDIF_B1_READY(v) (((v) << 13) & 0x2000) | ||
860 | #define BP_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 12 | ||
861 | #define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x1000 | ||
862 | #define BF_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE(v) (((v) << 12) & 0x1000) | ||
863 | #define BP_LCDIF_DEBUG0_GPMI_LCDIF_REQ 11 | ||
864 | #define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ 0x800 | ||
865 | #define BF_LCDIF_DEBUG0_GPMI_LCDIF_REQ(v) (((v) << 11) & 0x800) | ||
866 | #define BP_LCDIF_DEBUG0_LCDIF_GPMI_GRANT 10 | ||
867 | #define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT 0x400 | ||
868 | #define BF_LCDIF_DEBUG0_LCDIF_GPMI_GRANT(v) (((v) << 10) & 0x400) | ||
869 | #define BP_LCDIF_DEBUG0_RSRVD0 0 | ||
870 | #define BM_LCDIF_DEBUG0_RSRVD0 0x3ff | ||
871 | #define BF_LCDIF_DEBUG0_RSRVD0(v) (((v) << 0) & 0x3ff) | ||
872 | |||
873 | /** | ||
874 | * Register: HW_LCDIF_DEBUG1 | ||
875 | * Address: 0x200 | ||
876 | * SCT: no | ||
877 | */ | ||
878 | #define HW_LCDIF_DEBUG1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x200)) | ||
879 | #define BP_LCDIF_DEBUG1_H_DATA_COUNT 16 | ||
880 | #define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xffff0000 | ||
881 | #define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) (((v) << 16) & 0xffff0000) | ||
882 | #define BP_LCDIF_DEBUG1_V_DATA_COUNT 0 | ||
883 | #define BM_LCDIF_DEBUG1_V_DATA_COUNT 0xffff | ||
884 | #define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) (((v) << 0) & 0xffff) | ||
885 | |||
886 | #endif /* __HEADERGEN__IMX233__LCDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-lradc.h b/firmware/target/arm/imx233/regs/imx233/regs-lradc.h new file mode 100644 index 0000000000..0948e0fe75 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-lradc.h | |||
@@ -0,0 +1,783 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__LRADC__H__ | ||
24 | #define __HEADERGEN__IMX233__LRADC__H__ | ||
25 | |||
26 | #define REGS_LRADC_BASE (0x80050000) | ||
27 | |||
28 | #define REGS_LRADC_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_LRADC_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_LRADC_CTRL0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_LRADC_CTRL0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_LRADC_CTRL0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_LRADC_CTRL0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_LRADC_CTRL0_SFTRST 31 | ||
40 | #define BM_LRADC_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_LRADC_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_LRADC_CTRL0_CLKGATE 30 | ||
43 | #define BM_LRADC_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_LRADC_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_LRADC_CTRL0_RSRVD2 22 | ||
46 | #define BM_LRADC_CTRL0_RSRVD2 0x3fc00000 | ||
47 | #define BF_LRADC_CTRL0_RSRVD2(v) (((v) << 22) & 0x3fc00000) | ||
48 | #define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21 | ||
49 | #define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000 | ||
50 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 | ||
51 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 | ||
52 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) << 21) & 0x200000) | ||
53 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000) | ||
54 | #define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20 | ||
55 | #define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000 | ||
56 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 | ||
57 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 | ||
58 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) << 20) & 0x100000) | ||
59 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000) | ||
60 | #define BP_LRADC_CTRL0_YMINUS_ENABLE 19 | ||
61 | #define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000 | ||
62 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 | ||
63 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 | ||
64 | #define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) << 19) & 0x80000) | ||
65 | #define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000) | ||
66 | #define BP_LRADC_CTRL0_XMINUS_ENABLE 18 | ||
67 | #define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000 | ||
68 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 | ||
69 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 | ||
70 | #define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) << 18) & 0x40000) | ||
71 | #define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000) | ||
72 | #define BP_LRADC_CTRL0_YPLUS_ENABLE 17 | ||
73 | #define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000 | ||
74 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 | ||
75 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 | ||
76 | #define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) << 17) & 0x20000) | ||
77 | #define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000) | ||
78 | #define BP_LRADC_CTRL0_XPLUS_ENABLE 16 | ||
79 | #define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000 | ||
80 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 | ||
81 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 | ||
82 | #define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) << 16) & 0x10000) | ||
83 | #define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000) | ||
84 | #define BP_LRADC_CTRL0_RSRVD1 8 | ||
85 | #define BM_LRADC_CTRL0_RSRVD1 0xff00 | ||
86 | #define BF_LRADC_CTRL0_RSRVD1(v) (((v) << 8) & 0xff00) | ||
87 | #define BP_LRADC_CTRL0_SCHEDULE 0 | ||
88 | #define BM_LRADC_CTRL0_SCHEDULE 0xff | ||
89 | #define BF_LRADC_CTRL0_SCHEDULE(v) (((v) << 0) & 0xff) | ||
90 | |||
91 | /** | ||
92 | * Register: HW_LRADC_CTRL1 | ||
93 | * Address: 0x10 | ||
94 | * SCT: yes | ||
95 | */ | ||
96 | #define HW_LRADC_CTRL1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0)) | ||
97 | #define HW_LRADC_CTRL1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4)) | ||
98 | #define HW_LRADC_CTRL1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8)) | ||
99 | #define HW_LRADC_CTRL1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc)) | ||
100 | #define BP_LRADC_CTRL1_RSRVD2 25 | ||
101 | #define BM_LRADC_CTRL1_RSRVD2 0xfe000000 | ||
102 | #define BF_LRADC_CTRL1_RSRVD2(v) (((v) << 25) & 0xfe000000) | ||
103 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24 | ||
104 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000 | ||
105 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 | ||
106 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 | ||
107 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
108 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000) | ||
109 | #define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23 | ||
110 | #define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000 | ||
111 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 | ||
112 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 | ||
113 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) << 23) & 0x800000) | ||
114 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000) | ||
115 | #define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22 | ||
116 | #define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000 | ||
117 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 | ||
118 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 | ||
119 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
120 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000) | ||
121 | #define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21 | ||
122 | #define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000 | ||
123 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 | ||
124 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 | ||
125 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
126 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000) | ||
127 | #define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20 | ||
128 | #define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000 | ||
129 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 | ||
130 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 | ||
131 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
132 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000) | ||
133 | #define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19 | ||
134 | #define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000 | ||
135 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 | ||
136 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 | ||
137 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
138 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000) | ||
139 | #define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18 | ||
140 | #define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000 | ||
141 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 | ||
142 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 | ||
143 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
144 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000) | ||
145 | #define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17 | ||
146 | #define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000 | ||
147 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 | ||
148 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 | ||
149 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
150 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000) | ||
151 | #define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16 | ||
152 | #define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000 | ||
153 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 | ||
154 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 | ||
155 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
156 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000) | ||
157 | #define BP_LRADC_CTRL1_RSRVD1 9 | ||
158 | #define BM_LRADC_CTRL1_RSRVD1 0xfe00 | ||
159 | #define BF_LRADC_CTRL1_RSRVD1(v) (((v) << 9) & 0xfe00) | ||
160 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8 | ||
161 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100 | ||
162 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 | ||
163 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 | ||
164 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) << 8) & 0x100) | ||
165 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100) | ||
166 | #define BP_LRADC_CTRL1_LRADC7_IRQ 7 | ||
167 | #define BM_LRADC_CTRL1_LRADC7_IRQ 0x80 | ||
168 | #define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 | ||
169 | #define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 | ||
170 | #define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) << 7) & 0x80) | ||
171 | #define BF_LRADC_CTRL1_LRADC7_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80) | ||
172 | #define BP_LRADC_CTRL1_LRADC6_IRQ 6 | ||
173 | #define BM_LRADC_CTRL1_LRADC6_IRQ 0x40 | ||
174 | #define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 | ||
175 | #define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 | ||
176 | #define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) << 6) & 0x40) | ||
177 | #define BF_LRADC_CTRL1_LRADC6_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40) | ||
178 | #define BP_LRADC_CTRL1_LRADC5_IRQ 5 | ||
179 | #define BM_LRADC_CTRL1_LRADC5_IRQ 0x20 | ||
180 | #define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 | ||
181 | #define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 | ||
182 | #define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) << 5) & 0x20) | ||
183 | #define BF_LRADC_CTRL1_LRADC5_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20) | ||
184 | #define BP_LRADC_CTRL1_LRADC4_IRQ 4 | ||
185 | #define BM_LRADC_CTRL1_LRADC4_IRQ 0x10 | ||
186 | #define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 | ||
187 | #define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 | ||
188 | #define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) << 4) & 0x10) | ||
189 | #define BF_LRADC_CTRL1_LRADC4_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10) | ||
190 | #define BP_LRADC_CTRL1_LRADC3_IRQ 3 | ||
191 | #define BM_LRADC_CTRL1_LRADC3_IRQ 0x8 | ||
192 | #define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 | ||
193 | #define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 | ||
194 | #define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) << 3) & 0x8) | ||
195 | #define BF_LRADC_CTRL1_LRADC3_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8) | ||
196 | #define BP_LRADC_CTRL1_LRADC2_IRQ 2 | ||
197 | #define BM_LRADC_CTRL1_LRADC2_IRQ 0x4 | ||
198 | #define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 | ||
199 | #define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 | ||
200 | #define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) << 2) & 0x4) | ||
201 | #define BF_LRADC_CTRL1_LRADC2_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4) | ||
202 | #define BP_LRADC_CTRL1_LRADC1_IRQ 1 | ||
203 | #define BM_LRADC_CTRL1_LRADC1_IRQ 0x2 | ||
204 | #define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 | ||
205 | #define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 | ||
206 | #define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) << 1) & 0x2) | ||
207 | #define BF_LRADC_CTRL1_LRADC1_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2) | ||
208 | #define BP_LRADC_CTRL1_LRADC0_IRQ 0 | ||
209 | #define BM_LRADC_CTRL1_LRADC0_IRQ 0x1 | ||
210 | #define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 | ||
211 | #define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 | ||
212 | #define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) << 0) & 0x1) | ||
213 | #define BF_LRADC_CTRL1_LRADC0_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1) | ||
214 | |||
215 | /** | ||
216 | * Register: HW_LRADC_CTRL2 | ||
217 | * Address: 0x20 | ||
218 | * SCT: yes | ||
219 | */ | ||
220 | #define HW_LRADC_CTRL2 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0)) | ||
221 | #define HW_LRADC_CTRL2_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4)) | ||
222 | #define HW_LRADC_CTRL2_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8)) | ||
223 | #define HW_LRADC_CTRL2_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc)) | ||
224 | #define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 | ||
225 | #define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000 | ||
226 | #define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) << 24) & 0xff000000) | ||
227 | #define BP_LRADC_CTRL2_BL_AMP_BYPASS 23 | ||
228 | #define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x800000 | ||
229 | #define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0 | ||
230 | #define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1 | ||
231 | #define BF_LRADC_CTRL2_BL_AMP_BYPASS(v) (((v) << 23) & 0x800000) | ||
232 | #define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v) ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000) | ||
233 | #define BP_LRADC_CTRL2_BL_ENABLE 22 | ||
234 | #define BM_LRADC_CTRL2_BL_ENABLE 0x400000 | ||
235 | #define BF_LRADC_CTRL2_BL_ENABLE(v) (((v) << 22) & 0x400000) | ||
236 | #define BP_LRADC_CTRL2_BL_MUX_SELECT 21 | ||
237 | #define BM_LRADC_CTRL2_BL_MUX_SELECT 0x200000 | ||
238 | #define BF_LRADC_CTRL2_BL_MUX_SELECT(v) (((v) << 21) & 0x200000) | ||
239 | #define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 | ||
240 | #define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x1f0000 | ||
241 | #define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) (((v) << 16) & 0x1f0000) | ||
242 | #define BP_LRADC_CTRL2_TEMPSENSE_PWD 15 | ||
243 | #define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x8000 | ||
244 | #define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0 | ||
245 | #define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1 | ||
246 | #define BF_LRADC_CTRL2_TEMPSENSE_PWD(v) (((v) << 15) & 0x8000) | ||
247 | #define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v) ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000) | ||
248 | #define BP_LRADC_CTRL2_RSRVD1 14 | ||
249 | #define BM_LRADC_CTRL2_RSRVD1 0x4000 | ||
250 | #define BF_LRADC_CTRL2_RSRVD1(v) (((v) << 14) & 0x4000) | ||
251 | #define BP_LRADC_CTRL2_EXT_EN1 13 | ||
252 | #define BM_LRADC_CTRL2_EXT_EN1 0x2000 | ||
253 | #define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0 | ||
254 | #define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1 | ||
255 | #define BF_LRADC_CTRL2_EXT_EN1(v) (((v) << 13) & 0x2000) | ||
256 | #define BF_LRADC_CTRL2_EXT_EN1_V(v) ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000) | ||
257 | #define BP_LRADC_CTRL2_EXT_EN0 12 | ||
258 | #define BM_LRADC_CTRL2_EXT_EN0 0x1000 | ||
259 | #define BF_LRADC_CTRL2_EXT_EN0(v) (((v) << 12) & 0x1000) | ||
260 | #define BP_LRADC_CTRL2_RSRVD2 10 | ||
261 | #define BM_LRADC_CTRL2_RSRVD2 0xc00 | ||
262 | #define BF_LRADC_CTRL2_RSRVD2(v) (((v) << 10) & 0xc00) | ||
263 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9 | ||
264 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200 | ||
265 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 | ||
266 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 | ||
267 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) << 9) & 0x200) | ||
268 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200) | ||
269 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8 | ||
270 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100 | ||
271 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 | ||
272 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 | ||
273 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) << 8) & 0x100) | ||
274 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100) | ||
275 | #define BP_LRADC_CTRL2_TEMP_ISRC1 4 | ||
276 | #define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0 | ||
277 | #define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf | ||
278 | #define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe | ||
279 | #define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd | ||
280 | #define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc | ||
281 | #define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb | ||
282 | #define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa | ||
283 | #define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 | ||
284 | #define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 | ||
285 | #define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 | ||
286 | #define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 | ||
287 | #define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 | ||
288 | #define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 | ||
289 | #define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 | ||
290 | #define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 | ||
291 | #define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 | ||
292 | #define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 | ||
293 | #define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) << 4) & 0xf0) | ||
294 | #define BF_LRADC_CTRL2_TEMP_ISRC1_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0) | ||
295 | #define BP_LRADC_CTRL2_TEMP_ISRC0 0 | ||
296 | #define BM_LRADC_CTRL2_TEMP_ISRC0 0xf | ||
297 | #define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf | ||
298 | #define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe | ||
299 | #define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd | ||
300 | #define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc | ||
301 | #define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb | ||
302 | #define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa | ||
303 | #define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 | ||
304 | #define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 | ||
305 | #define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 | ||
306 | #define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 | ||
307 | #define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 | ||
308 | #define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 | ||
309 | #define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 | ||
310 | #define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 | ||
311 | #define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 | ||
312 | #define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 | ||
313 | #define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) << 0) & 0xf) | ||
314 | #define BF_LRADC_CTRL2_TEMP_ISRC0_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf) | ||
315 | |||
316 | /** | ||
317 | * Register: HW_LRADC_CTRL3 | ||
318 | * Address: 0x30 | ||
319 | * SCT: yes | ||
320 | */ | ||
321 | #define HW_LRADC_CTRL3 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0)) | ||
322 | #define HW_LRADC_CTRL3_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4)) | ||
323 | #define HW_LRADC_CTRL3_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8)) | ||
324 | #define HW_LRADC_CTRL3_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc)) | ||
325 | #define BP_LRADC_CTRL3_RSRVD5 26 | ||
326 | #define BM_LRADC_CTRL3_RSRVD5 0xfc000000 | ||
327 | #define BF_LRADC_CTRL3_RSRVD5(v) (((v) << 26) & 0xfc000000) | ||
328 | #define BP_LRADC_CTRL3_DISCARD 24 | ||
329 | #define BM_LRADC_CTRL3_DISCARD 0x3000000 | ||
330 | #define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 | ||
331 | #define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 | ||
332 | #define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 | ||
333 | #define BF_LRADC_CTRL3_DISCARD(v) (((v) << 24) & 0x3000000) | ||
334 | #define BF_LRADC_CTRL3_DISCARD_V(v) ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000) | ||
335 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23 | ||
336 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000 | ||
337 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 | ||
338 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 | ||
339 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) << 23) & 0x800000) | ||
340 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000) | ||
341 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22 | ||
342 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000 | ||
343 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 | ||
344 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 | ||
345 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) << 22) & 0x400000) | ||
346 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000) | ||
347 | #define BP_LRADC_CTRL3_RSRVD4 14 | ||
348 | #define BM_LRADC_CTRL3_RSRVD4 0x3fc000 | ||
349 | #define BF_LRADC_CTRL3_RSRVD4(v) (((v) << 14) & 0x3fc000) | ||
350 | #define BP_LRADC_CTRL3_RSRVD3 10 | ||
351 | #define BM_LRADC_CTRL3_RSRVD3 0x3c00 | ||
352 | #define BF_LRADC_CTRL3_RSRVD3(v) (((v) << 10) & 0x3c00) | ||
353 | #define BP_LRADC_CTRL3_CYCLE_TIME 8 | ||
354 | #define BM_LRADC_CTRL3_CYCLE_TIME 0x300 | ||
355 | #define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 | ||
356 | #define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 | ||
357 | #define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 | ||
358 | #define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 | ||
359 | #define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) << 8) & 0x300) | ||
360 | #define BF_LRADC_CTRL3_CYCLE_TIME_V(v) ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300) | ||
361 | #define BP_LRADC_CTRL3_RSRVD2 6 | ||
362 | #define BM_LRADC_CTRL3_RSRVD2 0xc0 | ||
363 | #define BF_LRADC_CTRL3_RSRVD2(v) (((v) << 6) & 0xc0) | ||
364 | #define BP_LRADC_CTRL3_HIGH_TIME 4 | ||
365 | #define BM_LRADC_CTRL3_HIGH_TIME 0x30 | ||
366 | #define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 | ||
367 | #define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 | ||
368 | #define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 | ||
369 | #define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 | ||
370 | #define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) << 4) & 0x30) | ||
371 | #define BF_LRADC_CTRL3_HIGH_TIME_V(v) ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30) | ||
372 | #define BP_LRADC_CTRL3_RSRVD1 2 | ||
373 | #define BM_LRADC_CTRL3_RSRVD1 0xc | ||
374 | #define BF_LRADC_CTRL3_RSRVD1(v) (((v) << 2) & 0xc) | ||
375 | #define BP_LRADC_CTRL3_DELAY_CLOCK 1 | ||
376 | #define BM_LRADC_CTRL3_DELAY_CLOCK 0x2 | ||
377 | #define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 | ||
378 | #define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 | ||
379 | #define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) << 1) & 0x2) | ||
380 | #define BF_LRADC_CTRL3_DELAY_CLOCK_V(v) ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2) | ||
381 | #define BP_LRADC_CTRL3_INVERT_CLOCK 0 | ||
382 | #define BM_LRADC_CTRL3_INVERT_CLOCK 0x1 | ||
383 | #define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 | ||
384 | #define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 | ||
385 | #define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) << 0) & 0x1) | ||
386 | #define BF_LRADC_CTRL3_INVERT_CLOCK_V(v) ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1) | ||
387 | |||
388 | /** | ||
389 | * Register: HW_LRADC_STATUS | ||
390 | * Address: 0x40 | ||
391 | * SCT: yes | ||
392 | */ | ||
393 | #define HW_LRADC_STATUS (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x0)) | ||
394 | #define HW_LRADC_STATUS_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x4)) | ||
395 | #define HW_LRADC_STATUS_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x8)) | ||
396 | #define HW_LRADC_STATUS_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0xc)) | ||
397 | #define BP_LRADC_STATUS_RSRVD3 27 | ||
398 | #define BM_LRADC_STATUS_RSRVD3 0xf8000000 | ||
399 | #define BF_LRADC_STATUS_RSRVD3(v) (((v) << 27) & 0xf8000000) | ||
400 | #define BP_LRADC_STATUS_TEMP1_PRESENT 26 | ||
401 | #define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000 | ||
402 | #define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
403 | #define BP_LRADC_STATUS_TEMP0_PRESENT 25 | ||
404 | #define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000 | ||
405 | #define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
406 | #define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24 | ||
407 | #define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000 | ||
408 | #define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) << 24) & 0x1000000) | ||
409 | #define BP_LRADC_STATUS_CHANNEL7_PRESENT 23 | ||
410 | #define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000 | ||
411 | #define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) << 23) & 0x800000) | ||
412 | #define BP_LRADC_STATUS_CHANNEL6_PRESENT 22 | ||
413 | #define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000 | ||
414 | #define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) << 22) & 0x400000) | ||
415 | #define BP_LRADC_STATUS_CHANNEL5_PRESENT 21 | ||
416 | #define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000 | ||
417 | #define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) << 21) & 0x200000) | ||
418 | #define BP_LRADC_STATUS_CHANNEL4_PRESENT 20 | ||
419 | #define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000 | ||
420 | #define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) << 20) & 0x100000) | ||
421 | #define BP_LRADC_STATUS_CHANNEL3_PRESENT 19 | ||
422 | #define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000 | ||
423 | #define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) << 19) & 0x80000) | ||
424 | #define BP_LRADC_STATUS_CHANNEL2_PRESENT 18 | ||
425 | #define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000 | ||
426 | #define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) << 18) & 0x40000) | ||
427 | #define BP_LRADC_STATUS_CHANNEL1_PRESENT 17 | ||
428 | #define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000 | ||
429 | #define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) << 17) & 0x20000) | ||
430 | #define BP_LRADC_STATUS_CHANNEL0_PRESENT 16 | ||
431 | #define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000 | ||
432 | #define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) << 16) & 0x10000) | ||
433 | #define BP_LRADC_STATUS_RSRVD2 1 | ||
434 | #define BM_LRADC_STATUS_RSRVD2 0xfffe | ||
435 | #define BF_LRADC_STATUS_RSRVD2(v) (((v) << 1) & 0xfffe) | ||
436 | #define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 | ||
437 | #define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1 | ||
438 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 | ||
439 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 | ||
440 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) << 0) & 0x1) | ||
441 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1) | ||
442 | |||
443 | /** | ||
444 | * Register: HW_LRADC_CHn | ||
445 | * Address: 0x50+n*0x10 | ||
446 | * SCT: yes | ||
447 | */ | ||
448 | #define HW_LRADC_CHn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0)) | ||
449 | #define HW_LRADC_CHn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4)) | ||
450 | #define HW_LRADC_CHn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8)) | ||
451 | #define HW_LRADC_CHn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc)) | ||
452 | #define BP_LRADC_CHn_TOGGLE 31 | ||
453 | #define BM_LRADC_CHn_TOGGLE 0x80000000 | ||
454 | #define BF_LRADC_CHn_TOGGLE(v) (((v) << 31) & 0x80000000) | ||
455 | #define BP_LRADC_CHn_RSRVD2 30 | ||
456 | #define BM_LRADC_CHn_RSRVD2 0x40000000 | ||
457 | #define BF_LRADC_CHn_RSRVD2(v) (((v) << 30) & 0x40000000) | ||
458 | #define BP_LRADC_CHn_ACCUMULATE 29 | ||
459 | #define BM_LRADC_CHn_ACCUMULATE 0x20000000 | ||
460 | #define BF_LRADC_CHn_ACCUMULATE(v) (((v) << 29) & 0x20000000) | ||
461 | #define BP_LRADC_CHn_NUM_SAMPLES 24 | ||
462 | #define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000 | ||
463 | #define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000) | ||
464 | #define BP_LRADC_CHn_RSRVD1 18 | ||
465 | #define BM_LRADC_CHn_RSRVD1 0xfc0000 | ||
466 | #define BF_LRADC_CHn_RSRVD1(v) (((v) << 18) & 0xfc0000) | ||
467 | #define BP_LRADC_CHn_VALUE 0 | ||
468 | #define BM_LRADC_CHn_VALUE 0x3ffff | ||
469 | #define BF_LRADC_CHn_VALUE(v) (((v) << 0) & 0x3ffff) | ||
470 | |||
471 | /** | ||
472 | * Register: HW_LRADC_DELAYn | ||
473 | * Address: 0xd0+n*0x10 | ||
474 | * SCT: yes | ||
475 | */ | ||
476 | #define HW_LRADC_DELAYn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0)) | ||
477 | #define HW_LRADC_DELAYn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4)) | ||
478 | #define HW_LRADC_DELAYn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8)) | ||
479 | #define HW_LRADC_DELAYn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc)) | ||
480 | #define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 | ||
481 | #define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000 | ||
482 | #define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) << 24) & 0xff000000) | ||
483 | #define BP_LRADC_DELAYn_RSRVD2 21 | ||
484 | #define BM_LRADC_DELAYn_RSRVD2 0xe00000 | ||
485 | #define BF_LRADC_DELAYn_RSRVD2(v) (((v) << 21) & 0xe00000) | ||
486 | #define BP_LRADC_DELAYn_KICK 20 | ||
487 | #define BM_LRADC_DELAYn_KICK 0x100000 | ||
488 | #define BF_LRADC_DELAYn_KICK(v) (((v) << 20) & 0x100000) | ||
489 | #define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 | ||
490 | #define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000 | ||
491 | #define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) << 16) & 0xf0000) | ||
492 | #define BP_LRADC_DELAYn_LOOP_COUNT 11 | ||
493 | #define BM_LRADC_DELAYn_LOOP_COUNT 0xf800 | ||
494 | #define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) << 11) & 0xf800) | ||
495 | #define BP_LRADC_DELAYn_DELAY 0 | ||
496 | #define BM_LRADC_DELAYn_DELAY 0x7ff | ||
497 | #define BF_LRADC_DELAYn_DELAY(v) (((v) << 0) & 0x7ff) | ||
498 | |||
499 | /** | ||
500 | * Register: HW_LRADC_DEBUG0 | ||
501 | * Address: 0x110 | ||
502 | * SCT: yes | ||
503 | */ | ||
504 | #define HW_LRADC_DEBUG0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x0)) | ||
505 | #define HW_LRADC_DEBUG0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x4)) | ||
506 | #define HW_LRADC_DEBUG0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x8)) | ||
507 | #define HW_LRADC_DEBUG0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0xc)) | ||
508 | #define BP_LRADC_DEBUG0_READONLY 16 | ||
509 | #define BM_LRADC_DEBUG0_READONLY 0xffff0000 | ||
510 | #define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000) | ||
511 | #define BP_LRADC_DEBUG0_RSRVD1 12 | ||
512 | #define BM_LRADC_DEBUG0_RSRVD1 0xf000 | ||
513 | #define BF_LRADC_DEBUG0_RSRVD1(v) (((v) << 12) & 0xf000) | ||
514 | #define BP_LRADC_DEBUG0_STATE 0 | ||
515 | #define BM_LRADC_DEBUG0_STATE 0xfff | ||
516 | #define BF_LRADC_DEBUG0_STATE(v) (((v) << 0) & 0xfff) | ||
517 | |||
518 | /** | ||
519 | * Register: HW_LRADC_DEBUG1 | ||
520 | * Address: 0x120 | ||
521 | * SCT: yes | ||
522 | */ | ||
523 | #define HW_LRADC_DEBUG1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0)) | ||
524 | #define HW_LRADC_DEBUG1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4)) | ||
525 | #define HW_LRADC_DEBUG1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8)) | ||
526 | #define HW_LRADC_DEBUG1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc)) | ||
527 | #define BP_LRADC_DEBUG1_RSRVD3 24 | ||
528 | #define BM_LRADC_DEBUG1_RSRVD3 0xff000000 | ||
529 | #define BF_LRADC_DEBUG1_RSRVD3(v) (((v) << 24) & 0xff000000) | ||
530 | #define BP_LRADC_DEBUG1_REQUEST 16 | ||
531 | #define BM_LRADC_DEBUG1_REQUEST 0xff0000 | ||
532 | #define BF_LRADC_DEBUG1_REQUEST(v) (((v) << 16) & 0xff0000) | ||
533 | #define BP_LRADC_DEBUG1_RSRVD2 13 | ||
534 | #define BM_LRADC_DEBUG1_RSRVD2 0xe000 | ||
535 | #define BF_LRADC_DEBUG1_RSRVD2(v) (((v) << 13) & 0xe000) | ||
536 | #define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 | ||
537 | #define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00 | ||
538 | #define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) << 8) & 0x1f00) | ||
539 | #define BP_LRADC_DEBUG1_RSRVD1 3 | ||
540 | #define BM_LRADC_DEBUG1_RSRVD1 0xf8 | ||
541 | #define BF_LRADC_DEBUG1_RSRVD1(v) (((v) << 3) & 0xf8) | ||
542 | #define BP_LRADC_DEBUG1_TESTMODE6 2 | ||
543 | #define BM_LRADC_DEBUG1_TESTMODE6 0x4 | ||
544 | #define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 | ||
545 | #define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 | ||
546 | #define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) << 2) & 0x4) | ||
547 | #define BF_LRADC_DEBUG1_TESTMODE6_V(v) ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4) | ||
548 | #define BP_LRADC_DEBUG1_TESTMODE5 1 | ||
549 | #define BM_LRADC_DEBUG1_TESTMODE5 0x2 | ||
550 | #define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 | ||
551 | #define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 | ||
552 | #define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) << 1) & 0x2) | ||
553 | #define BF_LRADC_DEBUG1_TESTMODE5_V(v) ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2) | ||
554 | #define BP_LRADC_DEBUG1_TESTMODE 0 | ||
555 | #define BM_LRADC_DEBUG1_TESTMODE 0x1 | ||
556 | #define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 | ||
557 | #define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 | ||
558 | #define BF_LRADC_DEBUG1_TESTMODE(v) (((v) << 0) & 0x1) | ||
559 | #define BF_LRADC_DEBUG1_TESTMODE_V(v) ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1) | ||
560 | |||
561 | /** | ||
562 | * Register: HW_LRADC_CONVERSION | ||
563 | * Address: 0x130 | ||
564 | * SCT: yes | ||
565 | */ | ||
566 | #define HW_LRADC_CONVERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0)) | ||
567 | #define HW_LRADC_CONVERSION_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4)) | ||
568 | #define HW_LRADC_CONVERSION_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8)) | ||
569 | #define HW_LRADC_CONVERSION_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc)) | ||
570 | #define BP_LRADC_CONVERSION_RSRVD3 21 | ||
571 | #define BM_LRADC_CONVERSION_RSRVD3 0xffe00000 | ||
572 | #define BF_LRADC_CONVERSION_RSRVD3(v) (((v) << 21) & 0xffe00000) | ||
573 | #define BP_LRADC_CONVERSION_AUTOMATIC 20 | ||
574 | #define BM_LRADC_CONVERSION_AUTOMATIC 0x100000 | ||
575 | #define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 | ||
576 | #define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 | ||
577 | #define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) << 20) & 0x100000) | ||
578 | #define BF_LRADC_CONVERSION_AUTOMATIC_V(v) ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000) | ||
579 | #define BP_LRADC_CONVERSION_RSRVD2 18 | ||
580 | #define BM_LRADC_CONVERSION_RSRVD2 0xc0000 | ||
581 | #define BF_LRADC_CONVERSION_RSRVD2(v) (((v) << 18) & 0xc0000) | ||
582 | #define BP_LRADC_CONVERSION_SCALE_FACTOR 16 | ||
583 | #define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000 | ||
584 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 | ||
585 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 | ||
586 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 | ||
587 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 | ||
588 | #define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) << 16) & 0x30000) | ||
589 | #define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v) ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000) | ||
590 | #define BP_LRADC_CONVERSION_RSRVD1 10 | ||
591 | #define BM_LRADC_CONVERSION_RSRVD1 0xfc00 | ||
592 | #define BF_LRADC_CONVERSION_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
593 | #define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 | ||
594 | #define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff | ||
595 | #define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) << 0) & 0x3ff) | ||
596 | |||
597 | /** | ||
598 | * Register: HW_LRADC_CTRL4 | ||
599 | * Address: 0x140 | ||
600 | * SCT: yes | ||
601 | */ | ||
602 | #define HW_LRADC_CTRL4 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0)) | ||
603 | #define HW_LRADC_CTRL4_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4)) | ||
604 | #define HW_LRADC_CTRL4_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8)) | ||
605 | #define HW_LRADC_CTRL4_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc)) | ||
606 | #define BP_LRADC_CTRL4_LRADC7SELECT 28 | ||
607 | #define BM_LRADC_CTRL4_LRADC7SELECT 0xf0000000 | ||
608 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 | ||
609 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 | ||
610 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 | ||
611 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 | ||
612 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 | ||
613 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 | ||
614 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 | ||
615 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 | ||
616 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 | ||
617 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 | ||
618 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xa | ||
619 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xb | ||
620 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xc | ||
621 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xd | ||
622 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xe | ||
623 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xf | ||
624 | #define BF_LRADC_CTRL4_LRADC7SELECT(v) (((v) << 28) & 0xf0000000) | ||
625 | #define BF_LRADC_CTRL4_LRADC7SELECT_V(v) ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000) | ||
626 | #define BP_LRADC_CTRL4_LRADC6SELECT 24 | ||
627 | #define BM_LRADC_CTRL4_LRADC6SELECT 0xf000000 | ||
628 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 | ||
629 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 | ||
630 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 | ||
631 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 | ||
632 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 | ||
633 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 | ||
634 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 | ||
635 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 | ||
636 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 | ||
637 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 | ||
638 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xa | ||
639 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xb | ||
640 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xc | ||
641 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xd | ||
642 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xe | ||
643 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xf | ||
644 | #define BF_LRADC_CTRL4_LRADC6SELECT(v) (((v) << 24) & 0xf000000) | ||
645 | #define BF_LRADC_CTRL4_LRADC6SELECT_V(v) ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000) | ||
646 | #define BP_LRADC_CTRL4_LRADC5SELECT 20 | ||
647 | #define BM_LRADC_CTRL4_LRADC5SELECT 0xf00000 | ||
648 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 | ||
649 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 | ||
650 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 | ||
651 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 | ||
652 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 | ||
653 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 | ||
654 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 | ||
655 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 | ||
656 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 | ||
657 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 | ||
658 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xa | ||
659 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xb | ||
660 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xc | ||
661 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xd | ||
662 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xe | ||
663 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xf | ||
664 | #define BF_LRADC_CTRL4_LRADC5SELECT(v) (((v) << 20) & 0xf00000) | ||
665 | #define BF_LRADC_CTRL4_LRADC5SELECT_V(v) ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000) | ||
666 | #define BP_LRADC_CTRL4_LRADC4SELECT 16 | ||
667 | #define BM_LRADC_CTRL4_LRADC4SELECT 0xf0000 | ||
668 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 | ||
669 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 | ||
670 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 | ||
671 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 | ||
672 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 | ||
673 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 | ||
674 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 | ||
675 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 | ||
676 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 | ||
677 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 | ||
678 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xa | ||
679 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xb | ||
680 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xc | ||
681 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xd | ||
682 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xe | ||
683 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xf | ||
684 | #define BF_LRADC_CTRL4_LRADC4SELECT(v) (((v) << 16) & 0xf0000) | ||
685 | #define BF_LRADC_CTRL4_LRADC4SELECT_V(v) ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000) | ||
686 | #define BP_LRADC_CTRL4_LRADC3SELECT 12 | ||
687 | #define BM_LRADC_CTRL4_LRADC3SELECT 0xf000 | ||
688 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 | ||
689 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 | ||
690 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 | ||
691 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 | ||
692 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 | ||
693 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 | ||
694 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 | ||
695 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 | ||
696 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 | ||
697 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 | ||
698 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xa | ||
699 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xb | ||
700 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xc | ||
701 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xd | ||
702 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xe | ||
703 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xf | ||
704 | #define BF_LRADC_CTRL4_LRADC3SELECT(v) (((v) << 12) & 0xf000) | ||
705 | #define BF_LRADC_CTRL4_LRADC3SELECT_V(v) ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000) | ||
706 | #define BP_LRADC_CTRL4_LRADC2SELECT 8 | ||
707 | #define BM_LRADC_CTRL4_LRADC2SELECT 0xf00 | ||
708 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 | ||
709 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 | ||
710 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 | ||
711 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 | ||
712 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 | ||
713 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 | ||
714 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 | ||
715 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 | ||
716 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 | ||
717 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 | ||
718 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xa | ||
719 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xb | ||
720 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xc | ||
721 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xd | ||
722 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xe | ||
723 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xf | ||
724 | #define BF_LRADC_CTRL4_LRADC2SELECT(v) (((v) << 8) & 0xf00) | ||
725 | #define BF_LRADC_CTRL4_LRADC2SELECT_V(v) ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00) | ||
726 | #define BP_LRADC_CTRL4_LRADC1SELECT 4 | ||
727 | #define BM_LRADC_CTRL4_LRADC1SELECT 0xf0 | ||
728 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 | ||
729 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 | ||
730 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 | ||
731 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 | ||
732 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 | ||
733 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 | ||
734 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 | ||
735 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 | ||
736 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 | ||
737 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 | ||
738 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xa | ||
739 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xb | ||
740 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xc | ||
741 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xd | ||
742 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xe | ||
743 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xf | ||
744 | #define BF_LRADC_CTRL4_LRADC1SELECT(v) (((v) << 4) & 0xf0) | ||
745 | #define BF_LRADC_CTRL4_LRADC1SELECT_V(v) ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0) | ||
746 | #define BP_LRADC_CTRL4_LRADC0SELECT 0 | ||
747 | #define BM_LRADC_CTRL4_LRADC0SELECT 0xf | ||
748 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 | ||
749 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 | ||
750 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 | ||
751 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 | ||
752 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 | ||
753 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 | ||
754 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 | ||
755 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 | ||
756 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 | ||
757 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 | ||
758 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xa | ||
759 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xb | ||
760 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xc | ||
761 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xd | ||
762 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xe | ||
763 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xf | ||
764 | #define BF_LRADC_CTRL4_LRADC0SELECT(v) (((v) << 0) & 0xf) | ||
765 | #define BF_LRADC_CTRL4_LRADC0SELECT_V(v) ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf) | ||
766 | |||
767 | /** | ||
768 | * Register: HW_LRADC_VERSION | ||
769 | * Address: 0x150 | ||
770 | * SCT: no | ||
771 | */ | ||
772 | #define HW_LRADC_VERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150)) | ||
773 | #define BP_LRADC_VERSION_MAJOR 24 | ||
774 | #define BM_LRADC_VERSION_MAJOR 0xff000000 | ||
775 | #define BF_LRADC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
776 | #define BP_LRADC_VERSION_MINOR 16 | ||
777 | #define BM_LRADC_VERSION_MINOR 0xff0000 | ||
778 | #define BF_LRADC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
779 | #define BP_LRADC_VERSION_STEP 0 | ||
780 | #define BM_LRADC_VERSION_STEP 0xffff | ||
781 | #define BF_LRADC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
782 | |||
783 | #endif /* __HEADERGEN__IMX233__LRADC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h b/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h new file mode 100644 index 0000000000..a9066895fc --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h | |||
@@ -0,0 +1,287 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__OCOTP__H__ | ||
24 | #define __HEADERGEN__IMX233__OCOTP__H__ | ||
25 | |||
26 | #define REGS_OCOTP_BASE (0x8002c000) | ||
27 | |||
28 | #define REGS_OCOTP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_OCOTP_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_OCOTP_CTRL (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_OCOTP_CTRL_SET (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_OCOTP_CTRL_CLR (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_OCOTP_CTRL_TOG (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_OCOTP_CTRL_WR_UNLOCK 16 | ||
40 | #define BM_OCOTP_CTRL_WR_UNLOCK 0xffff0000 | ||
41 | #define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3e77 | ||
42 | #define BF_OCOTP_CTRL_WR_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
43 | #define BF_OCOTP_CTRL_WR_UNLOCK_V(v) ((BV_OCOTP_CTRL_WR_UNLOCK__##v << 16) & 0xffff0000) | ||
44 | #define BP_OCOTP_CTRL_RSRVD2 14 | ||
45 | #define BM_OCOTP_CTRL_RSRVD2 0xc000 | ||
46 | #define BF_OCOTP_CTRL_RSRVD2(v) (((v) << 14) & 0xc000) | ||
47 | #define BP_OCOTP_CTRL_RELOAD_SHADOWS 13 | ||
48 | #define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x2000 | ||
49 | #define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) (((v) << 13) & 0x2000) | ||
50 | #define BP_OCOTP_CTRL_RD_BANK_OPEN 12 | ||
51 | #define BM_OCOTP_CTRL_RD_BANK_OPEN 0x1000 | ||
52 | #define BF_OCOTP_CTRL_RD_BANK_OPEN(v) (((v) << 12) & 0x1000) | ||
53 | #define BP_OCOTP_CTRL_RSRVD1 10 | ||
54 | #define BM_OCOTP_CTRL_RSRVD1 0xc00 | ||
55 | #define BF_OCOTP_CTRL_RSRVD1(v) (((v) << 10) & 0xc00) | ||
56 | #define BP_OCOTP_CTRL_ERROR 9 | ||
57 | #define BM_OCOTP_CTRL_ERROR 0x200 | ||
58 | #define BF_OCOTP_CTRL_ERROR(v) (((v) << 9) & 0x200) | ||
59 | #define BP_OCOTP_CTRL_BUSY 8 | ||
60 | #define BM_OCOTP_CTRL_BUSY 0x100 | ||
61 | #define BF_OCOTP_CTRL_BUSY(v) (((v) << 8) & 0x100) | ||
62 | #define BP_OCOTP_CTRL_RSRVD0 5 | ||
63 | #define BM_OCOTP_CTRL_RSRVD0 0xe0 | ||
64 | #define BF_OCOTP_CTRL_RSRVD0(v) (((v) << 5) & 0xe0) | ||
65 | #define BP_OCOTP_CTRL_ADDR 0 | ||
66 | #define BM_OCOTP_CTRL_ADDR 0x1f | ||
67 | #define BF_OCOTP_CTRL_ADDR(v) (((v) << 0) & 0x1f) | ||
68 | |||
69 | /** | ||
70 | * Register: HW_OCOTP_DATA | ||
71 | * Address: 0x10 | ||
72 | * SCT: no | ||
73 | */ | ||
74 | #define HW_OCOTP_DATA (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x10)) | ||
75 | #define BP_OCOTP_DATA_DATA 0 | ||
76 | #define BM_OCOTP_DATA_DATA 0xffffffff | ||
77 | #define BF_OCOTP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
78 | |||
79 | /** | ||
80 | * Register: HW_OCOTP_CUSTn | ||
81 | * Address: 0x20+n*0x10 | ||
82 | * SCT: no | ||
83 | */ | ||
84 | #define HW_OCOTP_CUSTn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x20+(n)*0x10)) | ||
85 | #define BP_OCOTP_CUSTn_BITS 0 | ||
86 | #define BM_OCOTP_CUSTn_BITS 0xffffffff | ||
87 | #define BF_OCOTP_CUSTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
88 | |||
89 | /** | ||
90 | * Register: HW_OCOTP_CRYPTOn | ||
91 | * Address: 0x60+n*0x10 | ||
92 | * SCT: no | ||
93 | */ | ||
94 | #define HW_OCOTP_CRYPTOn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x60+(n)*0x10)) | ||
95 | #define BP_OCOTP_CRYPTOn_BITS 0 | ||
96 | #define BM_OCOTP_CRYPTOn_BITS 0xffffffff | ||
97 | #define BF_OCOTP_CRYPTOn_BITS(v) (((v) << 0) & 0xffffffff) | ||
98 | |||
99 | /** | ||
100 | * Register: HW_OCOTP_HWCAPn | ||
101 | * Address: 0xa0+n*0x10 | ||
102 | * SCT: no | ||
103 | */ | ||
104 | #define HW_OCOTP_HWCAPn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0xa0+(n)*0x10)) | ||
105 | #define BP_OCOTP_HWCAPn_BITS 0 | ||
106 | #define BM_OCOTP_HWCAPn_BITS 0xffffffff | ||
107 | #define BF_OCOTP_HWCAPn_BITS(v) (((v) << 0) & 0xffffffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_OCOTP_SWCAP | ||
111 | * Address: 0x100 | ||
112 | * SCT: no | ||
113 | */ | ||
114 | #define HW_OCOTP_SWCAP (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x100)) | ||
115 | #define BP_OCOTP_SWCAP_BITS 0 | ||
116 | #define BM_OCOTP_SWCAP_BITS 0xffffffff | ||
117 | #define BF_OCOTP_SWCAP_BITS(v) (((v) << 0) & 0xffffffff) | ||
118 | |||
119 | /** | ||
120 | * Register: HW_OCOTP_CUSTCAP | ||
121 | * Address: 0x110 | ||
122 | * SCT: no | ||
123 | */ | ||
124 | #define HW_OCOTP_CUSTCAP (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x110)) | ||
125 | #define BP_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9 31 | ||
126 | #define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9 0x80000000 | ||
127 | #define BF_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9(v) (((v) << 31) & 0x80000000) | ||
128 | #define BP_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10 30 | ||
129 | #define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10 0x40000000 | ||
130 | #define BF_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10(v) (((v) << 30) & 0x40000000) | ||
131 | #define BP_OCOTP_CUSTCAP_RSRVD1 5 | ||
132 | #define BM_OCOTP_CUSTCAP_RSRVD1 0x3fffffe0 | ||
133 | #define BF_OCOTP_CUSTCAP_RSRVD1(v) (((v) << 5) & 0x3fffffe0) | ||
134 | #define BP_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE 4 | ||
135 | #define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE 0x10 | ||
136 | #define BF_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE(v) (((v) << 4) & 0x10) | ||
137 | #define BP_OCOTP_CUSTCAP_USE_PARALLEL_JTAG 3 | ||
138 | #define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG 0x8 | ||
139 | #define BF_OCOTP_CUSTCAP_USE_PARALLEL_JTAG(v) (((v) << 3) & 0x8) | ||
140 | #define BP_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 2 | ||
141 | #define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x4 | ||
142 | #define BF_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT(v) (((v) << 2) & 0x4) | ||
143 | #define BP_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 1 | ||
144 | #define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x2 | ||
145 | #define BF_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT(v) (((v) << 1) & 0x2) | ||
146 | #define BP_OCOTP_CUSTCAP_RSRVD0 0 | ||
147 | #define BM_OCOTP_CUSTCAP_RSRVD0 0x1 | ||
148 | #define BF_OCOTP_CUSTCAP_RSRVD0(v) (((v) << 0) & 0x1) | ||
149 | |||
150 | /** | ||
151 | * Register: HW_OCOTP_LOCK | ||
152 | * Address: 0x120 | ||
153 | * SCT: no | ||
154 | */ | ||
155 | #define HW_OCOTP_LOCK (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x120)) | ||
156 | #define BP_OCOTP_LOCK_ROM7 31 | ||
157 | #define BM_OCOTP_LOCK_ROM7 0x80000000 | ||
158 | #define BF_OCOTP_LOCK_ROM7(v) (((v) << 31) & 0x80000000) | ||
159 | #define BP_OCOTP_LOCK_ROM6 30 | ||
160 | #define BM_OCOTP_LOCK_ROM6 0x40000000 | ||
161 | #define BF_OCOTP_LOCK_ROM6(v) (((v) << 30) & 0x40000000) | ||
162 | #define BP_OCOTP_LOCK_ROM5 29 | ||
163 | #define BM_OCOTP_LOCK_ROM5 0x20000000 | ||
164 | #define BF_OCOTP_LOCK_ROM5(v) (((v) << 29) & 0x20000000) | ||
165 | #define BP_OCOTP_LOCK_ROM4 28 | ||
166 | #define BM_OCOTP_LOCK_ROM4 0x10000000 | ||
167 | #define BF_OCOTP_LOCK_ROM4(v) (((v) << 28) & 0x10000000) | ||
168 | #define BP_OCOTP_LOCK_ROM3 27 | ||
169 | #define BM_OCOTP_LOCK_ROM3 0x8000000 | ||
170 | #define BF_OCOTP_LOCK_ROM3(v) (((v) << 27) & 0x8000000) | ||
171 | #define BP_OCOTP_LOCK_ROM2 26 | ||
172 | #define BM_OCOTP_LOCK_ROM2 0x4000000 | ||
173 | #define BF_OCOTP_LOCK_ROM2(v) (((v) << 26) & 0x4000000) | ||
174 | #define BP_OCOTP_LOCK_ROM1 25 | ||
175 | #define BM_OCOTP_LOCK_ROM1 0x2000000 | ||
176 | #define BF_OCOTP_LOCK_ROM1(v) (((v) << 25) & 0x2000000) | ||
177 | #define BP_OCOTP_LOCK_ROM0 24 | ||
178 | #define BM_OCOTP_LOCK_ROM0 0x1000000 | ||
179 | #define BF_OCOTP_LOCK_ROM0(v) (((v) << 24) & 0x1000000) | ||
180 | #define BP_OCOTP_LOCK_HWSW_SHADOW_ALT 23 | ||
181 | #define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x800000 | ||
182 | #define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v) (((v) << 23) & 0x800000) | ||
183 | #define BP_OCOTP_LOCK_CRYPTODCP_ALT 22 | ||
184 | #define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x400000 | ||
185 | #define BF_OCOTP_LOCK_CRYPTODCP_ALT(v) (((v) << 22) & 0x400000) | ||
186 | #define BP_OCOTP_LOCK_CRYPTOKEY_ALT 21 | ||
187 | #define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x200000 | ||
188 | #define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v) (((v) << 21) & 0x200000) | ||
189 | #define BP_OCOTP_LOCK_PIN 20 | ||
190 | #define BM_OCOTP_LOCK_PIN 0x100000 | ||
191 | #define BF_OCOTP_LOCK_PIN(v) (((v) << 20) & 0x100000) | ||
192 | #define BP_OCOTP_LOCK_OPS 19 | ||
193 | #define BM_OCOTP_LOCK_OPS 0x80000 | ||
194 | #define BF_OCOTP_LOCK_OPS(v) (((v) << 19) & 0x80000) | ||
195 | #define BP_OCOTP_LOCK_UN2 18 | ||
196 | #define BM_OCOTP_LOCK_UN2 0x40000 | ||
197 | #define BF_OCOTP_LOCK_UN2(v) (((v) << 18) & 0x40000) | ||
198 | #define BP_OCOTP_LOCK_UN1 17 | ||
199 | #define BM_OCOTP_LOCK_UN1 0x20000 | ||
200 | #define BF_OCOTP_LOCK_UN1(v) (((v) << 17) & 0x20000) | ||
201 | #define BP_OCOTP_LOCK_UN0 16 | ||
202 | #define BM_OCOTP_LOCK_UN0 0x10000 | ||
203 | #define BF_OCOTP_LOCK_UN0(v) (((v) << 16) & 0x10000) | ||
204 | #define BP_OCOTP_LOCK_UNALLOCATED 11 | ||
205 | #define BM_OCOTP_LOCK_UNALLOCATED 0xf800 | ||
206 | #define BF_OCOTP_LOCK_UNALLOCATED(v) (((v) << 11) & 0xf800) | ||
207 | #define BP_OCOTP_LOCK_ROM_SHADOW 10 | ||
208 | #define BM_OCOTP_LOCK_ROM_SHADOW 0x400 | ||
209 | #define BF_OCOTP_LOCK_ROM_SHADOW(v) (((v) << 10) & 0x400) | ||
210 | #define BP_OCOTP_LOCK_CUSTCAP 9 | ||
211 | #define BM_OCOTP_LOCK_CUSTCAP 0x200 | ||
212 | #define BF_OCOTP_LOCK_CUSTCAP(v) (((v) << 9) & 0x200) | ||
213 | #define BP_OCOTP_LOCK_HWSW 8 | ||
214 | #define BM_OCOTP_LOCK_HWSW 0x100 | ||
215 | #define BF_OCOTP_LOCK_HWSW(v) (((v) << 8) & 0x100) | ||
216 | #define BP_OCOTP_LOCK_CUSTCAP_SHADOW 7 | ||
217 | #define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x80 | ||
218 | #define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v) (((v) << 7) & 0x80) | ||
219 | #define BP_OCOTP_LOCK_HWSW_SHADOW 6 | ||
220 | #define BM_OCOTP_LOCK_HWSW_SHADOW 0x40 | ||
221 | #define BF_OCOTP_LOCK_HWSW_SHADOW(v) (((v) << 6) & 0x40) | ||
222 | #define BP_OCOTP_LOCK_CRYPTODCP 5 | ||
223 | #define BM_OCOTP_LOCK_CRYPTODCP 0x20 | ||
224 | #define BF_OCOTP_LOCK_CRYPTODCP(v) (((v) << 5) & 0x20) | ||
225 | #define BP_OCOTP_LOCK_CRYPTOKEY 4 | ||
226 | #define BM_OCOTP_LOCK_CRYPTOKEY 0x10 | ||
227 | #define BF_OCOTP_LOCK_CRYPTOKEY(v) (((v) << 4) & 0x10) | ||
228 | #define BP_OCOTP_LOCK_CUST3 3 | ||
229 | #define BM_OCOTP_LOCK_CUST3 0x8 | ||
230 | #define BF_OCOTP_LOCK_CUST3(v) (((v) << 3) & 0x8) | ||
231 | #define BP_OCOTP_LOCK_CUST2 2 | ||
232 | #define BM_OCOTP_LOCK_CUST2 0x4 | ||
233 | #define BF_OCOTP_LOCK_CUST2(v) (((v) << 2) & 0x4) | ||
234 | #define BP_OCOTP_LOCK_CUST1 1 | ||
235 | #define BM_OCOTP_LOCK_CUST1 0x2 | ||
236 | #define BF_OCOTP_LOCK_CUST1(v) (((v) << 1) & 0x2) | ||
237 | #define BP_OCOTP_LOCK_CUST0 0 | ||
238 | #define BM_OCOTP_LOCK_CUST0 0x1 | ||
239 | #define BF_OCOTP_LOCK_CUST0(v) (((v) << 0) & 0x1) | ||
240 | |||
241 | /** | ||
242 | * Register: HW_OCOTP_OPSn | ||
243 | * Address: 0x130+n*0x10 | ||
244 | * SCT: no | ||
245 | */ | ||
246 | #define HW_OCOTP_OPSn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x130+(n)*0x10)) | ||
247 | #define BP_OCOTP_OPSn_BITS 0 | ||
248 | #define BM_OCOTP_OPSn_BITS 0xffffffff | ||
249 | #define BF_OCOTP_OPSn_BITS(v) (((v) << 0) & 0xffffffff) | ||
250 | |||
251 | /** | ||
252 | * Register: HW_OCOTP_UNn | ||
253 | * Address: 0x170+n*0x10 | ||
254 | * SCT: no | ||
255 | */ | ||
256 | #define HW_OCOTP_UNn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x170+(n)*0x10)) | ||
257 | #define BP_OCOTP_UNn_BITS 0 | ||
258 | #define BM_OCOTP_UNn_BITS 0xffffffff | ||
259 | #define BF_OCOTP_UNn_BITS(v) (((v) << 0) & 0xffffffff) | ||
260 | |||
261 | /** | ||
262 | * Register: HW_OCOTP_ROMn | ||
263 | * Address: 0x1a0+n*0x10 | ||
264 | * SCT: no | ||
265 | */ | ||
266 | #define HW_OCOTP_ROMn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x1a0+(n)*0x10)) | ||
267 | #define BP_OCOTP_ROMn_BITS 0 | ||
268 | #define BM_OCOTP_ROMn_BITS 0xffffffff | ||
269 | #define BF_OCOTP_ROMn_BITS(v) (((v) << 0) & 0xffffffff) | ||
270 | |||
271 | /** | ||
272 | * Register: HW_OCOTP_VERSION | ||
273 | * Address: 0x220 | ||
274 | * SCT: no | ||
275 | */ | ||
276 | #define HW_OCOTP_VERSION (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x220)) | ||
277 | #define BP_OCOTP_VERSION_MAJOR 24 | ||
278 | #define BM_OCOTP_VERSION_MAJOR 0xff000000 | ||
279 | #define BF_OCOTP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
280 | #define BP_OCOTP_VERSION_MINOR 16 | ||
281 | #define BM_OCOTP_VERSION_MINOR 0xff0000 | ||
282 | #define BF_OCOTP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
283 | #define BP_OCOTP_VERSION_STEP 0 | ||
284 | #define BM_OCOTP_VERSION_STEP 0xffff | ||
285 | #define BF_OCOTP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
286 | |||
287 | #endif /* __HEADERGEN__IMX233__OCOTP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h new file mode 100644 index 0000000000..a8faa358c5 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h | |||
@@ -0,0 +1,216 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__PINCTRL__H__ | ||
24 | #define __HEADERGEN__IMX233__PINCTRL__H__ | ||
25 | |||
26 | #define REGS_PINCTRL_BASE (0x80018000) | ||
27 | |||
28 | #define REGS_PINCTRL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_PINCTRL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_PINCTRL_CTRL_SFTRST 31 | ||
40 | #define BM_PINCTRL_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_PINCTRL_CTRL_CLKGATE 30 | ||
43 | #define BM_PINCTRL_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_PINCTRL_CTRL_RSRVD2 28 | ||
46 | #define BM_PINCTRL_CTRL_RSRVD2 0x30000000 | ||
47 | #define BF_PINCTRL_CTRL_RSRVD2(v) (((v) << 28) & 0x30000000) | ||
48 | #define BP_PINCTRL_CTRL_PRESENT3 27 | ||
49 | #define BM_PINCTRL_CTRL_PRESENT3 0x8000000 | ||
50 | #define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 27) & 0x8000000) | ||
51 | #define BP_PINCTRL_CTRL_PRESENT2 26 | ||
52 | #define BM_PINCTRL_CTRL_PRESENT2 0x4000000 | ||
53 | #define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 26) & 0x4000000) | ||
54 | #define BP_PINCTRL_CTRL_PRESENT1 25 | ||
55 | #define BM_PINCTRL_CTRL_PRESENT1 0x2000000 | ||
56 | #define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 25) & 0x2000000) | ||
57 | #define BP_PINCTRL_CTRL_PRESENT0 24 | ||
58 | #define BM_PINCTRL_CTRL_PRESENT0 0x1000000 | ||
59 | #define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 24) & 0x1000000) | ||
60 | #define BP_PINCTRL_CTRL_RSRVD1 3 | ||
61 | #define BM_PINCTRL_CTRL_RSRVD1 0xfffff8 | ||
62 | #define BF_PINCTRL_CTRL_RSRVD1(v) (((v) << 3) & 0xfffff8) | ||
63 | #define BP_PINCTRL_CTRL_IRQOUT2 2 | ||
64 | #define BM_PINCTRL_CTRL_IRQOUT2 0x4 | ||
65 | #define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4) | ||
66 | #define BP_PINCTRL_CTRL_IRQOUT1 1 | ||
67 | #define BM_PINCTRL_CTRL_IRQOUT1 0x2 | ||
68 | #define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2) | ||
69 | #define BP_PINCTRL_CTRL_IRQOUT0 0 | ||
70 | #define BM_PINCTRL_CTRL_IRQOUT0 0x1 | ||
71 | #define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1) | ||
72 | |||
73 | /** | ||
74 | * Register: HW_PINCTRL_MUXSELn | ||
75 | * Address: 0x100+n*0x10 | ||
76 | * SCT: yes | ||
77 | */ | ||
78 | #define HW_PINCTRL_MUXSELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0)) | ||
79 | #define HW_PINCTRL_MUXSELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4)) | ||
80 | #define HW_PINCTRL_MUXSELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8)) | ||
81 | #define HW_PINCTRL_MUXSELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc)) | ||
82 | #define BP_PINCTRL_MUXSELn_BITS 0 | ||
83 | #define BM_PINCTRL_MUXSELn_BITS 0xffffffff | ||
84 | #define BF_PINCTRL_MUXSELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
85 | |||
86 | /** | ||
87 | * Register: HW_PINCTRL_DRIVEn | ||
88 | * Address: 0x200+n*0x10 | ||
89 | * SCT: yes | ||
90 | */ | ||
91 | #define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0)) | ||
92 | #define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4)) | ||
93 | #define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8)) | ||
94 | #define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc)) | ||
95 | #define BP_PINCTRL_DRIVEn_BITS 0 | ||
96 | #define BM_PINCTRL_DRIVEn_BITS 0xffffffff | ||
97 | #define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
98 | |||
99 | /** | ||
100 | * Register: HW_PINCTRL_PULLn | ||
101 | * Address: 0x400+n*0x10 | ||
102 | * SCT: yes | ||
103 | */ | ||
104 | #define HW_PINCTRL_PULLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0)) | ||
105 | #define HW_PINCTRL_PULLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4)) | ||
106 | #define HW_PINCTRL_PULLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8)) | ||
107 | #define HW_PINCTRL_PULLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc)) | ||
108 | #define BP_PINCTRL_PULLn_BITS 0 | ||
109 | #define BM_PINCTRL_PULLn_BITS 0xffffffff | ||
110 | #define BF_PINCTRL_PULLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
111 | |||
112 | /** | ||
113 | * Register: HW_PINCTRL_DOUTn | ||
114 | * Address: 0x500+n*0x10 | ||
115 | * SCT: yes | ||
116 | */ | ||
117 | #define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0)) | ||
118 | #define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4)) | ||
119 | #define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8)) | ||
120 | #define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc)) | ||
121 | #define BP_PINCTRL_DOUTn_BITS 0 | ||
122 | #define BM_PINCTRL_DOUTn_BITS 0xffffffff | ||
123 | #define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
124 | |||
125 | /** | ||
126 | * Register: HW_PINCTRL_DINn | ||
127 | * Address: 0x600+n*0x10 | ||
128 | * SCT: yes | ||
129 | */ | ||
130 | #define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0)) | ||
131 | #define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4)) | ||
132 | #define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8)) | ||
133 | #define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc)) | ||
134 | #define BP_PINCTRL_DINn_BITS 0 | ||
135 | #define BM_PINCTRL_DINn_BITS 0xffffffff | ||
136 | #define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff) | ||
137 | |||
138 | /** | ||
139 | * Register: HW_PINCTRL_DOEn | ||
140 | * Address: 0x700+n*0x10 | ||
141 | * SCT: yes | ||
142 | */ | ||
143 | #define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0)) | ||
144 | #define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4)) | ||
145 | #define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8)) | ||
146 | #define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc)) | ||
147 | #define BP_PINCTRL_DOEn_BITS 0 | ||
148 | #define BM_PINCTRL_DOEn_BITS 0xffffffff | ||
149 | #define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
150 | |||
151 | /** | ||
152 | * Register: HW_PINCTRL_PIN2IRQn | ||
153 | * Address: 0x800+n*0x10 | ||
154 | * SCT: yes | ||
155 | */ | ||
156 | #define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0)) | ||
157 | #define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4)) | ||
158 | #define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8)) | ||
159 | #define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc)) | ||
160 | #define BP_PINCTRL_PIN2IRQn_BITS 0 | ||
161 | #define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff | ||
162 | #define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff) | ||
163 | |||
164 | /** | ||
165 | * Register: HW_PINCTRL_IRQENn | ||
166 | * Address: 0x900+n*0x10 | ||
167 | * SCT: yes | ||
168 | */ | ||
169 | #define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0)) | ||
170 | #define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4)) | ||
171 | #define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8)) | ||
172 | #define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc)) | ||
173 | #define BP_PINCTRL_IRQENn_BITS 0 | ||
174 | #define BM_PINCTRL_IRQENn_BITS 0xffffffff | ||
175 | #define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff) | ||
176 | |||
177 | /** | ||
178 | * Register: HW_PINCTRL_IRQLEVELn | ||
179 | * Address: 0xa00+n*0x10 | ||
180 | * SCT: yes | ||
181 | */ | ||
182 | #define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0)) | ||
183 | #define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4)) | ||
184 | #define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8)) | ||
185 | #define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc)) | ||
186 | #define BP_PINCTRL_IRQLEVELn_BITS 0 | ||
187 | #define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff | ||
188 | #define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
189 | |||
190 | /** | ||
191 | * Register: HW_PINCTRL_IRQPOLn | ||
192 | * Address: 0xb00+n*0x10 | ||
193 | * SCT: yes | ||
194 | */ | ||
195 | #define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0)) | ||
196 | #define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4)) | ||
197 | #define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8)) | ||
198 | #define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc)) | ||
199 | #define BP_PINCTRL_IRQPOLn_BITS 0 | ||
200 | #define BM_PINCTRL_IRQPOLn_BITS 0xffffffff | ||
201 | #define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_PINCTRL_IRQSTATn | ||
205 | * Address: 0xc00+n*0x10 | ||
206 | * SCT: yes | ||
207 | */ | ||
208 | #define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x0)) | ||
209 | #define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x4)) | ||
210 | #define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x8)) | ||
211 | #define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0xc)) | ||
212 | #define BP_PINCTRL_IRQSTATn_BITS 0 | ||
213 | #define BM_PINCTRL_IRQSTATn_BITS 0xffffffff | ||
214 | #define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff) | ||
215 | |||
216 | #endif /* __HEADERGEN__IMX233__PINCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-power.h b/firmware/target/arm/imx233/regs/imx233/regs-power.h new file mode 100644 index 0000000000..27357c9fe2 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-power.h | |||
@@ -0,0 +1,807 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__POWER__H__ | ||
24 | #define __HEADERGEN__IMX233__POWER__H__ | ||
25 | |||
26 | #define REGS_POWER_BASE (0x80044000) | ||
27 | |||
28 | #define REGS_POWER_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_POWER_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_POWER_CTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0)) | ||
36 | #define HW_POWER_CTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4)) | ||
37 | #define HW_POWER_CTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8)) | ||
38 | #define HW_POWER_CTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc)) | ||
39 | #define BP_POWER_CTRL_RSRVD3 31 | ||
40 | #define BM_POWER_CTRL_RSRVD3 0x80000000 | ||
41 | #define BF_POWER_CTRL_RSRVD3(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_POWER_CTRL_CLKGATE 30 | ||
43 | #define BM_POWER_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_POWER_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_POWER_CTRL_RSRVD2 28 | ||
46 | #define BM_POWER_CTRL_RSRVD2 0x30000000 | ||
47 | #define BF_POWER_CTRL_RSRVD2(v) (((v) << 28) & 0x30000000) | ||
48 | #define BP_POWER_CTRL_PSWITCH_MID_TRAN 27 | ||
49 | #define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x8000000 | ||
50 | #define BF_POWER_CTRL_PSWITCH_MID_TRAN(v) (((v) << 27) & 0x8000000) | ||
51 | #define BP_POWER_CTRL_RSRVD1 25 | ||
52 | #define BM_POWER_CTRL_RSRVD1 0x6000000 | ||
53 | #define BF_POWER_CTRL_RSRVD1(v) (((v) << 25) & 0x6000000) | ||
54 | #define BP_POWER_CTRL_DCDC4P2_BO_IRQ 24 | ||
55 | #define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x1000000 | ||
56 | #define BF_POWER_CTRL_DCDC4P2_BO_IRQ(v) (((v) << 24) & 0x1000000) | ||
57 | #define BP_POWER_CTRL_ENIRQ_DCDC4P2_BO 23 | ||
58 | #define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x800000 | ||
59 | #define BF_POWER_CTRL_ENIRQ_DCDC4P2_BO(v) (((v) << 23) & 0x800000) | ||
60 | #define BP_POWER_CTRL_VDD5V_DROOP_IRQ 22 | ||
61 | #define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x400000 | ||
62 | #define BF_POWER_CTRL_VDD5V_DROOP_IRQ(v) (((v) << 22) & 0x400000) | ||
63 | #define BP_POWER_CTRL_ENIRQ_VDD5V_DROOP 21 | ||
64 | #define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x200000 | ||
65 | #define BF_POWER_CTRL_ENIRQ_VDD5V_DROOP(v) (((v) << 21) & 0x200000) | ||
66 | #define BP_POWER_CTRL_PSWITCH_IRQ 20 | ||
67 | #define BM_POWER_CTRL_PSWITCH_IRQ 0x100000 | ||
68 | #define BF_POWER_CTRL_PSWITCH_IRQ(v) (((v) << 20) & 0x100000) | ||
69 | #define BP_POWER_CTRL_PSWITCH_IRQ_SRC 19 | ||
70 | #define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x80000 | ||
71 | #define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v) (((v) << 19) & 0x80000) | ||
72 | #define BP_POWER_CTRL_POLARITY_PSWITCH 18 | ||
73 | #define BM_POWER_CTRL_POLARITY_PSWITCH 0x40000 | ||
74 | #define BF_POWER_CTRL_POLARITY_PSWITCH(v) (((v) << 18) & 0x40000) | ||
75 | #define BP_POWER_CTRL_ENIRQ_PSWITCH 17 | ||
76 | #define BM_POWER_CTRL_ENIRQ_PSWITCH 0x20000 | ||
77 | #define BF_POWER_CTRL_ENIRQ_PSWITCH(v) (((v) << 17) & 0x20000) | ||
78 | #define BP_POWER_CTRL_POLARITY_DC_OK 16 | ||
79 | #define BM_POWER_CTRL_POLARITY_DC_OK 0x10000 | ||
80 | #define BF_POWER_CTRL_POLARITY_DC_OK(v) (((v) << 16) & 0x10000) | ||
81 | #define BP_POWER_CTRL_DC_OK_IRQ 15 | ||
82 | #define BM_POWER_CTRL_DC_OK_IRQ 0x8000 | ||
83 | #define BF_POWER_CTRL_DC_OK_IRQ(v) (((v) << 15) & 0x8000) | ||
84 | #define BP_POWER_CTRL_ENIRQ_DC_OK 14 | ||
85 | #define BM_POWER_CTRL_ENIRQ_DC_OK 0x4000 | ||
86 | #define BF_POWER_CTRL_ENIRQ_DC_OK(v) (((v) << 14) & 0x4000) | ||
87 | #define BP_POWER_CTRL_BATT_BO_IRQ 13 | ||
88 | #define BM_POWER_CTRL_BATT_BO_IRQ 0x2000 | ||
89 | #define BF_POWER_CTRL_BATT_BO_IRQ(v) (((v) << 13) & 0x2000) | ||
90 | #define BP_POWER_CTRL_ENIRQBATT_BO 12 | ||
91 | #define BM_POWER_CTRL_ENIRQBATT_BO 0x1000 | ||
92 | #define BF_POWER_CTRL_ENIRQBATT_BO(v) (((v) << 12) & 0x1000) | ||
93 | #define BP_POWER_CTRL_VDDIO_BO_IRQ 11 | ||
94 | #define BM_POWER_CTRL_VDDIO_BO_IRQ 0x800 | ||
95 | #define BF_POWER_CTRL_VDDIO_BO_IRQ(v) (((v) << 11) & 0x800) | ||
96 | #define BP_POWER_CTRL_ENIRQ_VDDIO_BO 10 | ||
97 | #define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x400 | ||
98 | #define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v) (((v) << 10) & 0x400) | ||
99 | #define BP_POWER_CTRL_VDDA_BO_IRQ 9 | ||
100 | #define BM_POWER_CTRL_VDDA_BO_IRQ 0x200 | ||
101 | #define BF_POWER_CTRL_VDDA_BO_IRQ(v) (((v) << 9) & 0x200) | ||
102 | #define BP_POWER_CTRL_ENIRQ_VDDA_BO 8 | ||
103 | #define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x100 | ||
104 | #define BF_POWER_CTRL_ENIRQ_VDDA_BO(v) (((v) << 8) & 0x100) | ||
105 | #define BP_POWER_CTRL_VDDD_BO_IRQ 7 | ||
106 | #define BM_POWER_CTRL_VDDD_BO_IRQ 0x80 | ||
107 | #define BF_POWER_CTRL_VDDD_BO_IRQ(v) (((v) << 7) & 0x80) | ||
108 | #define BP_POWER_CTRL_ENIRQ_VDDD_BO 6 | ||
109 | #define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x40 | ||
110 | #define BF_POWER_CTRL_ENIRQ_VDDD_BO(v) (((v) << 6) & 0x40) | ||
111 | #define BP_POWER_CTRL_POLARITY_VBUSVALID 5 | ||
112 | #define BM_POWER_CTRL_POLARITY_VBUSVALID 0x20 | ||
113 | #define BF_POWER_CTRL_POLARITY_VBUSVALID(v) (((v) << 5) & 0x20) | ||
114 | #define BP_POWER_CTRL_VBUSVALID_IRQ 4 | ||
115 | #define BM_POWER_CTRL_VBUSVALID_IRQ 0x10 | ||
116 | #define BF_POWER_CTRL_VBUSVALID_IRQ(v) (((v) << 4) & 0x10) | ||
117 | #define BP_POWER_CTRL_ENIRQ_VBUS_VALID 3 | ||
118 | #define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x8 | ||
119 | #define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v) (((v) << 3) & 0x8) | ||
120 | #define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 2 | ||
121 | #define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x4 | ||
122 | #define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v) (((v) << 2) & 0x4) | ||
123 | #define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 1 | ||
124 | #define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x2 | ||
125 | #define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v) (((v) << 1) & 0x2) | ||
126 | #define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 | ||
127 | #define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x1 | ||
128 | #define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v) (((v) << 0) & 0x1) | ||
129 | |||
130 | /** | ||
131 | * Register: HW_POWER_5VCTRL | ||
132 | * Address: 0x10 | ||
133 | * SCT: yes | ||
134 | */ | ||
135 | #define HW_POWER_5VCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0)) | ||
136 | #define HW_POWER_5VCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4)) | ||
137 | #define HW_POWER_5VCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8)) | ||
138 | #define HW_POWER_5VCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc)) | ||
139 | #define BP_POWER_5VCTRL_RSRVD6 30 | ||
140 | #define BM_POWER_5VCTRL_RSRVD6 0xc0000000 | ||
141 | #define BF_POWER_5VCTRL_RSRVD6(v) (((v) << 30) & 0xc0000000) | ||
142 | #define BP_POWER_5VCTRL_VBUSDROOP_TRSH 28 | ||
143 | #define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000 | ||
144 | #define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v) (((v) << 28) & 0x30000000) | ||
145 | #define BP_POWER_5VCTRL_RSRVD5 27 | ||
146 | #define BM_POWER_5VCTRL_RSRVD5 0x8000000 | ||
147 | #define BF_POWER_5VCTRL_RSRVD5(v) (((v) << 27) & 0x8000000) | ||
148 | #define BP_POWER_5VCTRL_HEADROOM_ADJ 24 | ||
149 | #define BM_POWER_5VCTRL_HEADROOM_ADJ 0x7000000 | ||
150 | #define BF_POWER_5VCTRL_HEADROOM_ADJ(v) (((v) << 24) & 0x7000000) | ||
151 | #define BP_POWER_5VCTRL_RSRVD4 21 | ||
152 | #define BM_POWER_5VCTRL_RSRVD4 0xe00000 | ||
153 | #define BF_POWER_5VCTRL_RSRVD4(v) (((v) << 21) & 0xe00000) | ||
154 | #define BP_POWER_5VCTRL_PWD_CHARGE_4P2 20 | ||
155 | #define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x100000 | ||
156 | #define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v) (((v) << 20) & 0x100000) | ||
157 | #define BP_POWER_5VCTRL_RSRVD3 18 | ||
158 | #define BM_POWER_5VCTRL_RSRVD3 0xc0000 | ||
159 | #define BF_POWER_5VCTRL_RSRVD3(v) (((v) << 18) & 0xc0000) | ||
160 | #define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT 12 | ||
161 | #define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x3f000 | ||
162 | #define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v) (((v) << 12) & 0x3f000) | ||
163 | #define BP_POWER_5VCTRL_RSRVD2 11 | ||
164 | #define BM_POWER_5VCTRL_RSRVD2 0x800 | ||
165 | #define BF_POWER_5VCTRL_RSRVD2(v) (((v) << 11) & 0x800) | ||
166 | #define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 | ||
167 | #define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x700 | ||
168 | #define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) (((v) << 8) & 0x700) | ||
169 | #define BP_POWER_5VCTRL_PWDN_5VBRNOUT 7 | ||
170 | #define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x80 | ||
171 | #define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v) (((v) << 7) & 0x80) | ||
172 | #define BP_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 6 | ||
173 | #define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x40 | ||
174 | #define BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(v) (((v) << 6) & 0x40) | ||
175 | #define BP_POWER_5VCTRL_DCDC_XFER 5 | ||
176 | #define BM_POWER_5VCTRL_DCDC_XFER 0x20 | ||
177 | #define BF_POWER_5VCTRL_DCDC_XFER(v) (((v) << 5) & 0x20) | ||
178 | #define BP_POWER_5VCTRL_VBUSVALID_5VDETECT 4 | ||
179 | #define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x10 | ||
180 | #define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v) (((v) << 4) & 0x10) | ||
181 | #define BP_POWER_5VCTRL_VBUSVALID_TO_B 3 | ||
182 | #define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x8 | ||
183 | #define BF_POWER_5VCTRL_VBUSVALID_TO_B(v) (((v) << 3) & 0x8) | ||
184 | #define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO 2 | ||
185 | #define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x4 | ||
186 | #define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v) (((v) << 2) & 0x4) | ||
187 | #define BP_POWER_5VCTRL_PWRUP_VBUS_CMPS 1 | ||
188 | #define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x2 | ||
189 | #define BF_POWER_5VCTRL_PWRUP_VBUS_CMPS(v) (((v) << 1) & 0x2) | ||
190 | #define BP_POWER_5VCTRL_ENABLE_DCDC 0 | ||
191 | #define BM_POWER_5VCTRL_ENABLE_DCDC 0x1 | ||
192 | #define BF_POWER_5VCTRL_ENABLE_DCDC(v) (((v) << 0) & 0x1) | ||
193 | |||
194 | /** | ||
195 | * Register: HW_POWER_MINPWR | ||
196 | * Address: 0x20 | ||
197 | * SCT: yes | ||
198 | */ | ||
199 | #define HW_POWER_MINPWR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0)) | ||
200 | #define HW_POWER_MINPWR_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4)) | ||
201 | #define HW_POWER_MINPWR_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8)) | ||
202 | #define HW_POWER_MINPWR_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc)) | ||
203 | #define BP_POWER_MINPWR_RSRVD1 15 | ||
204 | #define BM_POWER_MINPWR_RSRVD1 0xffff8000 | ||
205 | #define BF_POWER_MINPWR_RSRVD1(v) (((v) << 15) & 0xffff8000) | ||
206 | #define BP_POWER_MINPWR_LOWPWR_4P2 14 | ||
207 | #define BM_POWER_MINPWR_LOWPWR_4P2 0x4000 | ||
208 | #define BF_POWER_MINPWR_LOWPWR_4P2(v) (((v) << 14) & 0x4000) | ||
209 | #define BP_POWER_MINPWR_VDAC_DUMP_CTRL 13 | ||
210 | #define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x2000 | ||
211 | #define BF_POWER_MINPWR_VDAC_DUMP_CTRL(v) (((v) << 13) & 0x2000) | ||
212 | #define BP_POWER_MINPWR_PWD_BO 12 | ||
213 | #define BM_POWER_MINPWR_PWD_BO 0x1000 | ||
214 | #define BF_POWER_MINPWR_PWD_BO(v) (((v) << 12) & 0x1000) | ||
215 | #define BP_POWER_MINPWR_USE_VDDXTAL_VBG 11 | ||
216 | #define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x800 | ||
217 | #define BF_POWER_MINPWR_USE_VDDXTAL_VBG(v) (((v) << 11) & 0x800) | ||
218 | #define BP_POWER_MINPWR_PWD_ANA_CMPS 10 | ||
219 | #define BM_POWER_MINPWR_PWD_ANA_CMPS 0x400 | ||
220 | #define BF_POWER_MINPWR_PWD_ANA_CMPS(v) (((v) << 10) & 0x400) | ||
221 | #define BP_POWER_MINPWR_ENABLE_OSC 9 | ||
222 | #define BM_POWER_MINPWR_ENABLE_OSC 0x200 | ||
223 | #define BF_POWER_MINPWR_ENABLE_OSC(v) (((v) << 9) & 0x200) | ||
224 | #define BP_POWER_MINPWR_SELECT_OSC 8 | ||
225 | #define BM_POWER_MINPWR_SELECT_OSC 0x100 | ||
226 | #define BF_POWER_MINPWR_SELECT_OSC(v) (((v) << 8) & 0x100) | ||
227 | #define BP_POWER_MINPWR_VBG_OFF 7 | ||
228 | #define BM_POWER_MINPWR_VBG_OFF 0x80 | ||
229 | #define BF_POWER_MINPWR_VBG_OFF(v) (((v) << 7) & 0x80) | ||
230 | #define BP_POWER_MINPWR_DOUBLE_FETS 6 | ||
231 | #define BM_POWER_MINPWR_DOUBLE_FETS 0x40 | ||
232 | #define BF_POWER_MINPWR_DOUBLE_FETS(v) (((v) << 6) & 0x40) | ||
233 | #define BP_POWER_MINPWR_HALF_FETS 5 | ||
234 | #define BM_POWER_MINPWR_HALF_FETS 0x20 | ||
235 | #define BF_POWER_MINPWR_HALF_FETS(v) (((v) << 5) & 0x20) | ||
236 | #define BP_POWER_MINPWR_LESSANA_I 4 | ||
237 | #define BM_POWER_MINPWR_LESSANA_I 0x10 | ||
238 | #define BF_POWER_MINPWR_LESSANA_I(v) (((v) << 4) & 0x10) | ||
239 | #define BP_POWER_MINPWR_PWD_XTAL24 3 | ||
240 | #define BM_POWER_MINPWR_PWD_XTAL24 0x8 | ||
241 | #define BF_POWER_MINPWR_PWD_XTAL24(v) (((v) << 3) & 0x8) | ||
242 | #define BP_POWER_MINPWR_DC_STOPCLK 2 | ||
243 | #define BM_POWER_MINPWR_DC_STOPCLK 0x4 | ||
244 | #define BF_POWER_MINPWR_DC_STOPCLK(v) (((v) << 2) & 0x4) | ||
245 | #define BP_POWER_MINPWR_EN_DC_PFM 1 | ||
246 | #define BM_POWER_MINPWR_EN_DC_PFM 0x2 | ||
247 | #define BF_POWER_MINPWR_EN_DC_PFM(v) (((v) << 1) & 0x2) | ||
248 | #define BP_POWER_MINPWR_DC_HALFCLK 0 | ||
249 | #define BM_POWER_MINPWR_DC_HALFCLK 0x1 | ||
250 | #define BF_POWER_MINPWR_DC_HALFCLK(v) (((v) << 0) & 0x1) | ||
251 | |||
252 | /** | ||
253 | * Register: HW_POWER_CHARGE | ||
254 | * Address: 0x30 | ||
255 | * SCT: yes | ||
256 | */ | ||
257 | #define HW_POWER_CHARGE (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0)) | ||
258 | #define HW_POWER_CHARGE_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4)) | ||
259 | #define HW_POWER_CHARGE_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8)) | ||
260 | #define HW_POWER_CHARGE_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc)) | ||
261 | #define BP_POWER_CHARGE_RSRVD4 27 | ||
262 | #define BM_POWER_CHARGE_RSRVD4 0xf8000000 | ||
263 | #define BF_POWER_CHARGE_RSRVD4(v) (((v) << 27) & 0xf8000000) | ||
264 | #define BP_POWER_CHARGE_ADJ_VOLT 24 | ||
265 | #define BM_POWER_CHARGE_ADJ_VOLT 0x7000000 | ||
266 | #define BF_POWER_CHARGE_ADJ_VOLT(v) (((v) << 24) & 0x7000000) | ||
267 | #define BP_POWER_CHARGE_RSRVD3 23 | ||
268 | #define BM_POWER_CHARGE_RSRVD3 0x800000 | ||
269 | #define BF_POWER_CHARGE_RSRVD3(v) (((v) << 23) & 0x800000) | ||
270 | #define BP_POWER_CHARGE_ENABLE_LOAD 22 | ||
271 | #define BM_POWER_CHARGE_ENABLE_LOAD 0x400000 | ||
272 | #define BF_POWER_CHARGE_ENABLE_LOAD(v) (((v) << 22) & 0x400000) | ||
273 | #define BP_POWER_CHARGE_ENABLE_CHARGER_RESISTORS 21 | ||
274 | #define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS 0x200000 | ||
275 | #define BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(v) (((v) << 21) & 0x200000) | ||
276 | #define BP_POWER_CHARGE_ENABLE_FAULT_DETECT 20 | ||
277 | #define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x100000 | ||
278 | #define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v) (((v) << 20) & 0x100000) | ||
279 | #define BP_POWER_CHARGE_CHRG_STS_OFF 19 | ||
280 | #define BM_POWER_CHARGE_CHRG_STS_OFF 0x80000 | ||
281 | #define BF_POWER_CHARGE_CHRG_STS_OFF(v) (((v) << 19) & 0x80000) | ||
282 | #define BP_POWER_CHARGE_LIION_4P1 18 | ||
283 | #define BM_POWER_CHARGE_LIION_4P1 0x40000 | ||
284 | #define BF_POWER_CHARGE_LIION_4P1(v) (((v) << 18) & 0x40000) | ||
285 | #define BP_POWER_CHARGE_USE_EXTERN_R 17 | ||
286 | #define BM_POWER_CHARGE_USE_EXTERN_R 0x20000 | ||
287 | #define BF_POWER_CHARGE_USE_EXTERN_R(v) (((v) << 17) & 0x20000) | ||
288 | #define BP_POWER_CHARGE_PWD_BATTCHRG 16 | ||
289 | #define BM_POWER_CHARGE_PWD_BATTCHRG 0x10000 | ||
290 | #define BF_POWER_CHARGE_PWD_BATTCHRG(v) (((v) << 16) & 0x10000) | ||
291 | #define BP_POWER_CHARGE_RSRVD2 12 | ||
292 | #define BM_POWER_CHARGE_RSRVD2 0xf000 | ||
293 | #define BF_POWER_CHARGE_RSRVD2(v) (((v) << 12) & 0xf000) | ||
294 | #define BP_POWER_CHARGE_STOP_ILIMIT 8 | ||
295 | #define BM_POWER_CHARGE_STOP_ILIMIT 0xf00 | ||
296 | #define BF_POWER_CHARGE_STOP_ILIMIT(v) (((v) << 8) & 0xf00) | ||
297 | #define BP_POWER_CHARGE_RSRVD1 6 | ||
298 | #define BM_POWER_CHARGE_RSRVD1 0xc0 | ||
299 | #define BF_POWER_CHARGE_RSRVD1(v) (((v) << 6) & 0xc0) | ||
300 | #define BP_POWER_CHARGE_BATTCHRG_I 0 | ||
301 | #define BM_POWER_CHARGE_BATTCHRG_I 0x3f | ||
302 | #define BF_POWER_CHARGE_BATTCHRG_I(v) (((v) << 0) & 0x3f) | ||
303 | |||
304 | /** | ||
305 | * Register: HW_POWER_VDDDCTRL | ||
306 | * Address: 0x40 | ||
307 | * SCT: no | ||
308 | */ | ||
309 | #define HW_POWER_VDDDCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40)) | ||
310 | #define BP_POWER_VDDDCTRL_ADJTN 28 | ||
311 | #define BM_POWER_VDDDCTRL_ADJTN 0xf0000000 | ||
312 | #define BF_POWER_VDDDCTRL_ADJTN(v) (((v) << 28) & 0xf0000000) | ||
313 | #define BP_POWER_VDDDCTRL_RSRVD4 24 | ||
314 | #define BM_POWER_VDDDCTRL_RSRVD4 0xf000000 | ||
315 | #define BF_POWER_VDDDCTRL_RSRVD4(v) (((v) << 24) & 0xf000000) | ||
316 | #define BP_POWER_VDDDCTRL_PWDN_BRNOUT 23 | ||
317 | #define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x800000 | ||
318 | #define BF_POWER_VDDDCTRL_PWDN_BRNOUT(v) (((v) << 23) & 0x800000) | ||
319 | #define BP_POWER_VDDDCTRL_DISABLE_STEPPING 22 | ||
320 | #define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x400000 | ||
321 | #define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v) (((v) << 22) & 0x400000) | ||
322 | #define BP_POWER_VDDDCTRL_ENABLE_LINREG 21 | ||
323 | #define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x200000 | ||
324 | #define BF_POWER_VDDDCTRL_ENABLE_LINREG(v) (((v) << 21) & 0x200000) | ||
325 | #define BP_POWER_VDDDCTRL_DISABLE_FET 20 | ||
326 | #define BM_POWER_VDDDCTRL_DISABLE_FET 0x100000 | ||
327 | #define BF_POWER_VDDDCTRL_DISABLE_FET(v) (((v) << 20) & 0x100000) | ||
328 | #define BP_POWER_VDDDCTRL_RSRVD3 18 | ||
329 | #define BM_POWER_VDDDCTRL_RSRVD3 0xc0000 | ||
330 | #define BF_POWER_VDDDCTRL_RSRVD3(v) (((v) << 18) & 0xc0000) | ||
331 | #define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 | ||
332 | #define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x30000 | ||
333 | #define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) (((v) << 16) & 0x30000) | ||
334 | #define BP_POWER_VDDDCTRL_RSRVD2 11 | ||
335 | #define BM_POWER_VDDDCTRL_RSRVD2 0xf800 | ||
336 | #define BF_POWER_VDDDCTRL_RSRVD2(v) (((v) << 11) & 0xf800) | ||
337 | #define BP_POWER_VDDDCTRL_BO_OFFSET 8 | ||
338 | #define BM_POWER_VDDDCTRL_BO_OFFSET 0x700 | ||
339 | #define BF_POWER_VDDDCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
340 | #define BP_POWER_VDDDCTRL_RSRVD1 5 | ||
341 | #define BM_POWER_VDDDCTRL_RSRVD1 0xe0 | ||
342 | #define BF_POWER_VDDDCTRL_RSRVD1(v) (((v) << 5) & 0xe0) | ||
343 | #define BP_POWER_VDDDCTRL_TRG 0 | ||
344 | #define BM_POWER_VDDDCTRL_TRG 0x1f | ||
345 | #define BF_POWER_VDDDCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
346 | |||
347 | /** | ||
348 | * Register: HW_POWER_VDDACTRL | ||
349 | * Address: 0x50 | ||
350 | * SCT: no | ||
351 | */ | ||
352 | #define HW_POWER_VDDACTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50)) | ||
353 | #define BP_POWER_VDDACTRL_RSRVD4 20 | ||
354 | #define BM_POWER_VDDACTRL_RSRVD4 0xfff00000 | ||
355 | #define BF_POWER_VDDACTRL_RSRVD4(v) (((v) << 20) & 0xfff00000) | ||
356 | #define BP_POWER_VDDACTRL_PWDN_BRNOUT 19 | ||
357 | #define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x80000 | ||
358 | #define BF_POWER_VDDACTRL_PWDN_BRNOUT(v) (((v) << 19) & 0x80000) | ||
359 | #define BP_POWER_VDDACTRL_DISABLE_STEPPING 18 | ||
360 | #define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x40000 | ||
361 | #define BF_POWER_VDDACTRL_DISABLE_STEPPING(v) (((v) << 18) & 0x40000) | ||
362 | #define BP_POWER_VDDACTRL_ENABLE_LINREG 17 | ||
363 | #define BM_POWER_VDDACTRL_ENABLE_LINREG 0x20000 | ||
364 | #define BF_POWER_VDDACTRL_ENABLE_LINREG(v) (((v) << 17) & 0x20000) | ||
365 | #define BP_POWER_VDDACTRL_DISABLE_FET 16 | ||
366 | #define BM_POWER_VDDACTRL_DISABLE_FET 0x10000 | ||
367 | #define BF_POWER_VDDACTRL_DISABLE_FET(v) (((v) << 16) & 0x10000) | ||
368 | #define BP_POWER_VDDACTRL_RSRVD3 14 | ||
369 | #define BM_POWER_VDDACTRL_RSRVD3 0xc000 | ||
370 | #define BF_POWER_VDDACTRL_RSRVD3(v) (((v) << 14) & 0xc000) | ||
371 | #define BP_POWER_VDDACTRL_LINREG_OFFSET 12 | ||
372 | #define BM_POWER_VDDACTRL_LINREG_OFFSET 0x3000 | ||
373 | #define BF_POWER_VDDACTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
374 | #define BP_POWER_VDDACTRL_RSRVD2 11 | ||
375 | #define BM_POWER_VDDACTRL_RSRVD2 0x800 | ||
376 | #define BF_POWER_VDDACTRL_RSRVD2(v) (((v) << 11) & 0x800) | ||
377 | #define BP_POWER_VDDACTRL_BO_OFFSET 8 | ||
378 | #define BM_POWER_VDDACTRL_BO_OFFSET 0x700 | ||
379 | #define BF_POWER_VDDACTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
380 | #define BP_POWER_VDDACTRL_RSRVD1 5 | ||
381 | #define BM_POWER_VDDACTRL_RSRVD1 0xe0 | ||
382 | #define BF_POWER_VDDACTRL_RSRVD1(v) (((v) << 5) & 0xe0) | ||
383 | #define BP_POWER_VDDACTRL_TRG 0 | ||
384 | #define BM_POWER_VDDACTRL_TRG 0x1f | ||
385 | #define BF_POWER_VDDACTRL_TRG(v) (((v) << 0) & 0x1f) | ||
386 | |||
387 | /** | ||
388 | * Register: HW_POWER_VDDIOCTRL | ||
389 | * Address: 0x60 | ||
390 | * SCT: no | ||
391 | */ | ||
392 | #define HW_POWER_VDDIOCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60)) | ||
393 | #define BP_POWER_VDDIOCTRL_RSRVD5 24 | ||
394 | #define BM_POWER_VDDIOCTRL_RSRVD5 0xff000000 | ||
395 | #define BF_POWER_VDDIOCTRL_RSRVD5(v) (((v) << 24) & 0xff000000) | ||
396 | #define BP_POWER_VDDIOCTRL_ADJTN 20 | ||
397 | #define BM_POWER_VDDIOCTRL_ADJTN 0xf00000 | ||
398 | #define BF_POWER_VDDIOCTRL_ADJTN(v) (((v) << 20) & 0xf00000) | ||
399 | #define BP_POWER_VDDIOCTRL_RSRVD4 19 | ||
400 | #define BM_POWER_VDDIOCTRL_RSRVD4 0x80000 | ||
401 | #define BF_POWER_VDDIOCTRL_RSRVD4(v) (((v) << 19) & 0x80000) | ||
402 | #define BP_POWER_VDDIOCTRL_PWDN_BRNOUT 18 | ||
403 | #define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x40000 | ||
404 | #define BF_POWER_VDDIOCTRL_PWDN_BRNOUT(v) (((v) << 18) & 0x40000) | ||
405 | #define BP_POWER_VDDIOCTRL_DISABLE_STEPPING 17 | ||
406 | #define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x20000 | ||
407 | #define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v) (((v) << 17) & 0x20000) | ||
408 | #define BP_POWER_VDDIOCTRL_DISABLE_FET 16 | ||
409 | #define BM_POWER_VDDIOCTRL_DISABLE_FET 0x10000 | ||
410 | #define BF_POWER_VDDIOCTRL_DISABLE_FET(v) (((v) << 16) & 0x10000) | ||
411 | #define BP_POWER_VDDIOCTRL_RSRVD3 14 | ||
412 | #define BM_POWER_VDDIOCTRL_RSRVD3 0xc000 | ||
413 | #define BF_POWER_VDDIOCTRL_RSRVD3(v) (((v) << 14) & 0xc000) | ||
414 | #define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 | ||
415 | #define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x3000 | ||
416 | #define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
417 | #define BP_POWER_VDDIOCTRL_RSRVD2 11 | ||
418 | #define BM_POWER_VDDIOCTRL_RSRVD2 0x800 | ||
419 | #define BF_POWER_VDDIOCTRL_RSRVD2(v) (((v) << 11) & 0x800) | ||
420 | #define BP_POWER_VDDIOCTRL_BO_OFFSET 8 | ||
421 | #define BM_POWER_VDDIOCTRL_BO_OFFSET 0x700 | ||
422 | #define BF_POWER_VDDIOCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
423 | #define BP_POWER_VDDIOCTRL_RSRVD1 5 | ||
424 | #define BM_POWER_VDDIOCTRL_RSRVD1 0xe0 | ||
425 | #define BF_POWER_VDDIOCTRL_RSRVD1(v) (((v) << 5) & 0xe0) | ||
426 | #define BP_POWER_VDDIOCTRL_TRG 0 | ||
427 | #define BM_POWER_VDDIOCTRL_TRG 0x1f | ||
428 | #define BF_POWER_VDDIOCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
429 | |||
430 | /** | ||
431 | * Register: HW_POWER_VDDMEMCTRL | ||
432 | * Address: 0x70 | ||
433 | * SCT: no | ||
434 | */ | ||
435 | #define HW_POWER_VDDMEMCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70)) | ||
436 | #define BP_POWER_VDDMEMCTRL_RSRVD2 11 | ||
437 | #define BM_POWER_VDDMEMCTRL_RSRVD2 0xfffff800 | ||
438 | #define BF_POWER_VDDMEMCTRL_RSRVD2(v) (((v) << 11) & 0xfffff800) | ||
439 | #define BP_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 10 | ||
440 | #define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x400 | ||
441 | #define BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(v) (((v) << 10) & 0x400) | ||
442 | #define BP_POWER_VDDMEMCTRL_ENABLE_ILIMIT 9 | ||
443 | #define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x200 | ||
444 | #define BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT(v) (((v) << 9) & 0x200) | ||
445 | #define BP_POWER_VDDMEMCTRL_ENABLE_LINREG 8 | ||
446 | #define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x100 | ||
447 | #define BF_POWER_VDDMEMCTRL_ENABLE_LINREG(v) (((v) << 8) & 0x100) | ||
448 | #define BP_POWER_VDDMEMCTRL_RSRVD1 5 | ||
449 | #define BM_POWER_VDDMEMCTRL_RSRVD1 0xe0 | ||
450 | #define BF_POWER_VDDMEMCTRL_RSRVD1(v) (((v) << 5) & 0xe0) | ||
451 | #define BP_POWER_VDDMEMCTRL_TRG 0 | ||
452 | #define BM_POWER_VDDMEMCTRL_TRG 0x1f | ||
453 | #define BF_POWER_VDDMEMCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
454 | |||
455 | /** | ||
456 | * Register: HW_POWER_DCDC4P2 | ||
457 | * Address: 0x80 | ||
458 | * SCT: no | ||
459 | */ | ||
460 | #define HW_POWER_DCDC4P2 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80)) | ||
461 | #define BP_POWER_DCDC4P2_DROPOUT_CTRL 28 | ||
462 | #define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xf0000000 | ||
463 | #define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) (((v) << 28) & 0xf0000000) | ||
464 | #define BP_POWER_DCDC4P2_RSRVD5 26 | ||
465 | #define BM_POWER_DCDC4P2_RSRVD5 0xc000000 | ||
466 | #define BF_POWER_DCDC4P2_RSRVD5(v) (((v) << 26) & 0xc000000) | ||
467 | #define BP_POWER_DCDC4P2_ISTEAL_THRESH 24 | ||
468 | #define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x3000000 | ||
469 | #define BF_POWER_DCDC4P2_ISTEAL_THRESH(v) (((v) << 24) & 0x3000000) | ||
470 | #define BP_POWER_DCDC4P2_ENABLE_4P2 23 | ||
471 | #define BM_POWER_DCDC4P2_ENABLE_4P2 0x800000 | ||
472 | #define BF_POWER_DCDC4P2_ENABLE_4P2(v) (((v) << 23) & 0x800000) | ||
473 | #define BP_POWER_DCDC4P2_ENABLE_DCDC 22 | ||
474 | #define BM_POWER_DCDC4P2_ENABLE_DCDC 0x400000 | ||
475 | #define BF_POWER_DCDC4P2_ENABLE_DCDC(v) (((v) << 22) & 0x400000) | ||
476 | #define BP_POWER_DCDC4P2_HYST_DIR 21 | ||
477 | #define BM_POWER_DCDC4P2_HYST_DIR 0x200000 | ||
478 | #define BF_POWER_DCDC4P2_HYST_DIR(v) (((v) << 21) & 0x200000) | ||
479 | #define BP_POWER_DCDC4P2_HYST_THRESH 20 | ||
480 | #define BM_POWER_DCDC4P2_HYST_THRESH 0x100000 | ||
481 | #define BF_POWER_DCDC4P2_HYST_THRESH(v) (((v) << 20) & 0x100000) | ||
482 | #define BP_POWER_DCDC4P2_RSRVD3 19 | ||
483 | #define BM_POWER_DCDC4P2_RSRVD3 0x80000 | ||
484 | #define BF_POWER_DCDC4P2_RSRVD3(v) (((v) << 19) & 0x80000) | ||
485 | #define BP_POWER_DCDC4P2_TRG 16 | ||
486 | #define BM_POWER_DCDC4P2_TRG 0x70000 | ||
487 | #define BF_POWER_DCDC4P2_TRG(v) (((v) << 16) & 0x70000) | ||
488 | #define BP_POWER_DCDC4P2_RSRVD2 13 | ||
489 | #define BM_POWER_DCDC4P2_RSRVD2 0xe000 | ||
490 | #define BF_POWER_DCDC4P2_RSRVD2(v) (((v) << 13) & 0xe000) | ||
491 | #define BP_POWER_DCDC4P2_BO 8 | ||
492 | #define BM_POWER_DCDC4P2_BO 0x1f00 | ||
493 | #define BF_POWER_DCDC4P2_BO(v) (((v) << 8) & 0x1f00) | ||
494 | #define BP_POWER_DCDC4P2_RSRVD1 5 | ||
495 | #define BM_POWER_DCDC4P2_RSRVD1 0xe0 | ||
496 | #define BF_POWER_DCDC4P2_RSRVD1(v) (((v) << 5) & 0xe0) | ||
497 | #define BP_POWER_DCDC4P2_CMPTRIP 0 | ||
498 | #define BM_POWER_DCDC4P2_CMPTRIP 0x1f | ||
499 | #define BF_POWER_DCDC4P2_CMPTRIP(v) (((v) << 0) & 0x1f) | ||
500 | |||
501 | /** | ||
502 | * Register: HW_POWER_MISC | ||
503 | * Address: 0x90 | ||
504 | * SCT: no | ||
505 | */ | ||
506 | #define HW_POWER_MISC (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90)) | ||
507 | #define BP_POWER_MISC_RSRVD2 7 | ||
508 | #define BM_POWER_MISC_RSRVD2 0xffffff80 | ||
509 | #define BF_POWER_MISC_RSRVD2(v) (((v) << 7) & 0xffffff80) | ||
510 | #define BP_POWER_MISC_FREQSEL 4 | ||
511 | #define BM_POWER_MISC_FREQSEL 0x70 | ||
512 | #define BF_POWER_MISC_FREQSEL(v) (((v) << 4) & 0x70) | ||
513 | #define BP_POWER_MISC_RSRVD1 3 | ||
514 | #define BM_POWER_MISC_RSRVD1 0x8 | ||
515 | #define BF_POWER_MISC_RSRVD1(v) (((v) << 3) & 0x8) | ||
516 | #define BP_POWER_MISC_DELAY_TIMING 2 | ||
517 | #define BM_POWER_MISC_DELAY_TIMING 0x4 | ||
518 | #define BF_POWER_MISC_DELAY_TIMING(v) (((v) << 2) & 0x4) | ||
519 | #define BP_POWER_MISC_TEST 1 | ||
520 | #define BM_POWER_MISC_TEST 0x2 | ||
521 | #define BF_POWER_MISC_TEST(v) (((v) << 1) & 0x2) | ||
522 | #define BP_POWER_MISC_SEL_PLLCLK 0 | ||
523 | #define BM_POWER_MISC_SEL_PLLCLK 0x1 | ||
524 | #define BF_POWER_MISC_SEL_PLLCLK(v) (((v) << 0) & 0x1) | ||
525 | |||
526 | /** | ||
527 | * Register: HW_POWER_DCLIMITS | ||
528 | * Address: 0xa0 | ||
529 | * SCT: no | ||
530 | */ | ||
531 | #define HW_POWER_DCLIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0)) | ||
532 | #define BP_POWER_DCLIMITS_RSRVD3 16 | ||
533 | #define BM_POWER_DCLIMITS_RSRVD3 0xffff0000 | ||
534 | #define BF_POWER_DCLIMITS_RSRVD3(v) (((v) << 16) & 0xffff0000) | ||
535 | #define BP_POWER_DCLIMITS_RSRVD2 15 | ||
536 | #define BM_POWER_DCLIMITS_RSRVD2 0x8000 | ||
537 | #define BF_POWER_DCLIMITS_RSRVD2(v) (((v) << 15) & 0x8000) | ||
538 | #define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 | ||
539 | #define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x7f00 | ||
540 | #define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
541 | #define BP_POWER_DCLIMITS_RSRVD1 7 | ||
542 | #define BM_POWER_DCLIMITS_RSRVD1 0x80 | ||
543 | #define BF_POWER_DCLIMITS_RSRVD1(v) (((v) << 7) & 0x80) | ||
544 | #define BP_POWER_DCLIMITS_NEGLIMIT 0 | ||
545 | #define BM_POWER_DCLIMITS_NEGLIMIT 0x7f | ||
546 | #define BF_POWER_DCLIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
547 | |||
548 | /** | ||
549 | * Register: HW_POWER_LOOPCTRL | ||
550 | * Address: 0xb0 | ||
551 | * SCT: yes | ||
552 | */ | ||
553 | #define HW_POWER_LOOPCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x0)) | ||
554 | #define HW_POWER_LOOPCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x4)) | ||
555 | #define HW_POWER_LOOPCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x8)) | ||
556 | #define HW_POWER_LOOPCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0xc)) | ||
557 | #define BP_POWER_LOOPCTRL_RSRVD3 21 | ||
558 | #define BM_POWER_LOOPCTRL_RSRVD3 0xffe00000 | ||
559 | #define BF_POWER_LOOPCTRL_RSRVD3(v) (((v) << 21) & 0xffe00000) | ||
560 | #define BP_POWER_LOOPCTRL_TOGGLE_DIF 20 | ||
561 | #define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x100000 | ||
562 | #define BF_POWER_LOOPCTRL_TOGGLE_DIF(v) (((v) << 20) & 0x100000) | ||
563 | #define BP_POWER_LOOPCTRL_HYST_SIGN 19 | ||
564 | #define BM_POWER_LOOPCTRL_HYST_SIGN 0x80000 | ||
565 | #define BF_POWER_LOOPCTRL_HYST_SIGN(v) (((v) << 19) & 0x80000) | ||
566 | #define BP_POWER_LOOPCTRL_EN_CM_HYST 18 | ||
567 | #define BM_POWER_LOOPCTRL_EN_CM_HYST 0x40000 | ||
568 | #define BF_POWER_LOOPCTRL_EN_CM_HYST(v) (((v) << 18) & 0x40000) | ||
569 | #define BP_POWER_LOOPCTRL_EN_DF_HYST 17 | ||
570 | #define BM_POWER_LOOPCTRL_EN_DF_HYST 0x20000 | ||
571 | #define BF_POWER_LOOPCTRL_EN_DF_HYST(v) (((v) << 17) & 0x20000) | ||
572 | #define BP_POWER_LOOPCTRL_CM_HYST_THRESH 16 | ||
573 | #define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x10000 | ||
574 | #define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000) | ||
575 | #define BP_POWER_LOOPCTRL_DF_HYST_THRESH 15 | ||
576 | #define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x8000 | ||
577 | #define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000) | ||
578 | #define BP_POWER_LOOPCTRL_RCSCALE_THRESH 14 | ||
579 | #define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x4000 | ||
580 | #define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000) | ||
581 | #define BP_POWER_LOOPCTRL_EN_RCSCALE 12 | ||
582 | #define BM_POWER_LOOPCTRL_EN_RCSCALE 0x3000 | ||
583 | #define BF_POWER_LOOPCTRL_EN_RCSCALE(v) (((v) << 12) & 0x3000) | ||
584 | #define BP_POWER_LOOPCTRL_RSRVD2 11 | ||
585 | #define BM_POWER_LOOPCTRL_RSRVD2 0x800 | ||
586 | #define BF_POWER_LOOPCTRL_RSRVD2(v) (((v) << 11) & 0x800) | ||
587 | #define BP_POWER_LOOPCTRL_DC_FF 8 | ||
588 | #define BM_POWER_LOOPCTRL_DC_FF 0x700 | ||
589 | #define BF_POWER_LOOPCTRL_DC_FF(v) (((v) << 8) & 0x700) | ||
590 | #define BP_POWER_LOOPCTRL_DC_R 4 | ||
591 | #define BM_POWER_LOOPCTRL_DC_R 0xf0 | ||
592 | #define BF_POWER_LOOPCTRL_DC_R(v) (((v) << 4) & 0xf0) | ||
593 | #define BP_POWER_LOOPCTRL_RSRVD1 2 | ||
594 | #define BM_POWER_LOOPCTRL_RSRVD1 0xc | ||
595 | #define BF_POWER_LOOPCTRL_RSRVD1(v) (((v) << 2) & 0xc) | ||
596 | #define BP_POWER_LOOPCTRL_DC_C 0 | ||
597 | #define BM_POWER_LOOPCTRL_DC_C 0x3 | ||
598 | #define BF_POWER_LOOPCTRL_DC_C(v) (((v) << 0) & 0x3) | ||
599 | |||
600 | /** | ||
601 | * Register: HW_POWER_STS | ||
602 | * Address: 0xc0 | ||
603 | * SCT: no | ||
604 | */ | ||
605 | #define HW_POWER_STS (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0)) | ||
606 | #define BP_POWER_STS_RSRVD3 30 | ||
607 | #define BM_POWER_STS_RSRVD3 0xc0000000 | ||
608 | #define BF_POWER_STS_RSRVD3(v) (((v) << 30) & 0xc0000000) | ||
609 | #define BP_POWER_STS_PWRUP_SOURCE 24 | ||
610 | #define BM_POWER_STS_PWRUP_SOURCE 0x3f000000 | ||
611 | #define BF_POWER_STS_PWRUP_SOURCE(v) (((v) << 24) & 0x3f000000) | ||
612 | #define BP_POWER_STS_RSRVD2 22 | ||
613 | #define BM_POWER_STS_RSRVD2 0xc00000 | ||
614 | #define BF_POWER_STS_RSRVD2(v) (((v) << 22) & 0xc00000) | ||
615 | #define BP_POWER_STS_PSWITCH 20 | ||
616 | #define BM_POWER_STS_PSWITCH 0x300000 | ||
617 | #define BF_POWER_STS_PSWITCH(v) (((v) << 20) & 0x300000) | ||
618 | #define BP_POWER_STS_RSRVD1 18 | ||
619 | #define BM_POWER_STS_RSRVD1 0xc0000 | ||
620 | #define BF_POWER_STS_RSRVD1(v) (((v) << 18) & 0xc0000) | ||
621 | #define BP_POWER_STS_AVALID_STATUS 17 | ||
622 | #define BM_POWER_STS_AVALID_STATUS 0x20000 | ||
623 | #define BF_POWER_STS_AVALID_STATUS(v) (((v) << 17) & 0x20000) | ||
624 | #define BP_POWER_STS_BVALID_STATUS 16 | ||
625 | #define BM_POWER_STS_BVALID_STATUS 0x10000 | ||
626 | #define BF_POWER_STS_BVALID_STATUS(v) (((v) << 16) & 0x10000) | ||
627 | #define BP_POWER_STS_VBUSVALID_STATUS 15 | ||
628 | #define BM_POWER_STS_VBUSVALID_STATUS 0x8000 | ||
629 | #define BF_POWER_STS_VBUSVALID_STATUS(v) (((v) << 15) & 0x8000) | ||
630 | #define BP_POWER_STS_SESSEND_STATUS 14 | ||
631 | #define BM_POWER_STS_SESSEND_STATUS 0x4000 | ||
632 | #define BF_POWER_STS_SESSEND_STATUS(v) (((v) << 14) & 0x4000) | ||
633 | #define BP_POWER_STS_BATT_BO 13 | ||
634 | #define BM_POWER_STS_BATT_BO 0x2000 | ||
635 | #define BF_POWER_STS_BATT_BO(v) (((v) << 13) & 0x2000) | ||
636 | #define BP_POWER_STS_VDD5V_FAULT 12 | ||
637 | #define BM_POWER_STS_VDD5V_FAULT 0x1000 | ||
638 | #define BF_POWER_STS_VDD5V_FAULT(v) (((v) << 12) & 0x1000) | ||
639 | #define BP_POWER_STS_CHRGSTS 11 | ||
640 | #define BM_POWER_STS_CHRGSTS 0x800 | ||
641 | #define BF_POWER_STS_CHRGSTS(v) (((v) << 11) & 0x800) | ||
642 | #define BP_POWER_STS_DCDC_4P2_BO 10 | ||
643 | #define BM_POWER_STS_DCDC_4P2_BO 0x400 | ||
644 | #define BF_POWER_STS_DCDC_4P2_BO(v) (((v) << 10) & 0x400) | ||
645 | #define BP_POWER_STS_DC_OK 9 | ||
646 | #define BM_POWER_STS_DC_OK 0x200 | ||
647 | #define BF_POWER_STS_DC_OK(v) (((v) << 9) & 0x200) | ||
648 | #define BP_POWER_STS_VDDIO_BO 8 | ||
649 | #define BM_POWER_STS_VDDIO_BO 0x100 | ||
650 | #define BF_POWER_STS_VDDIO_BO(v) (((v) << 8) & 0x100) | ||
651 | #define BP_POWER_STS_VDDA_BO 7 | ||
652 | #define BM_POWER_STS_VDDA_BO 0x80 | ||
653 | #define BF_POWER_STS_VDDA_BO(v) (((v) << 7) & 0x80) | ||
654 | #define BP_POWER_STS_VDDD_BO 6 | ||
655 | #define BM_POWER_STS_VDDD_BO 0x40 | ||
656 | #define BF_POWER_STS_VDDD_BO(v) (((v) << 6) & 0x40) | ||
657 | #define BP_POWER_STS_VDD5V_GT_VDDIO 5 | ||
658 | #define BM_POWER_STS_VDD5V_GT_VDDIO 0x20 | ||
659 | #define BF_POWER_STS_VDD5V_GT_VDDIO(v) (((v) << 5) & 0x20) | ||
660 | #define BP_POWER_STS_VDD5V_DROOP 4 | ||
661 | #define BM_POWER_STS_VDD5V_DROOP 0x10 | ||
662 | #define BF_POWER_STS_VDD5V_DROOP(v) (((v) << 4) & 0x10) | ||
663 | #define BP_POWER_STS_AVALID 3 | ||
664 | #define BM_POWER_STS_AVALID 0x8 | ||
665 | #define BF_POWER_STS_AVALID(v) (((v) << 3) & 0x8) | ||
666 | #define BP_POWER_STS_BVALID 2 | ||
667 | #define BM_POWER_STS_BVALID 0x4 | ||
668 | #define BF_POWER_STS_BVALID(v) (((v) << 2) & 0x4) | ||
669 | #define BP_POWER_STS_VBUSVALID 1 | ||
670 | #define BM_POWER_STS_VBUSVALID 0x2 | ||
671 | #define BF_POWER_STS_VBUSVALID(v) (((v) << 1) & 0x2) | ||
672 | #define BP_POWER_STS_SESSEND 0 | ||
673 | #define BM_POWER_STS_SESSEND 0x1 | ||
674 | #define BF_POWER_STS_SESSEND(v) (((v) << 0) & 0x1) | ||
675 | |||
676 | /** | ||
677 | * Register: HW_POWER_SPEED | ||
678 | * Address: 0xd0 | ||
679 | * SCT: yes | ||
680 | */ | ||
681 | #define HW_POWER_SPEED (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0)) | ||
682 | #define HW_POWER_SPEED_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4)) | ||
683 | #define HW_POWER_SPEED_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8)) | ||
684 | #define HW_POWER_SPEED_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc)) | ||
685 | #define BP_POWER_SPEED_RSRVD1 24 | ||
686 | #define BM_POWER_SPEED_RSRVD1 0xff000000 | ||
687 | #define BF_POWER_SPEED_RSRVD1(v) (((v) << 24) & 0xff000000) | ||
688 | #define BP_POWER_SPEED_STATUS 16 | ||
689 | #define BM_POWER_SPEED_STATUS 0xff0000 | ||
690 | #define BF_POWER_SPEED_STATUS(v) (((v) << 16) & 0xff0000) | ||
691 | #define BP_POWER_SPEED_RSRVD0 2 | ||
692 | #define BM_POWER_SPEED_RSRVD0 0xfffc | ||
693 | #define BF_POWER_SPEED_RSRVD0(v) (((v) << 2) & 0xfffc) | ||
694 | #define BP_POWER_SPEED_CTRL 0 | ||
695 | #define BM_POWER_SPEED_CTRL 0x3 | ||
696 | #define BF_POWER_SPEED_CTRL(v) (((v) << 0) & 0x3) | ||
697 | |||
698 | /** | ||
699 | * Register: HW_POWER_BATTMONITOR | ||
700 | * Address: 0xe0 | ||
701 | * SCT: no | ||
702 | */ | ||
703 | #define HW_POWER_BATTMONITOR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0)) | ||
704 | #define BP_POWER_BATTMONITOR_RSRVD3 26 | ||
705 | #define BM_POWER_BATTMONITOR_RSRVD3 0xfc000000 | ||
706 | #define BF_POWER_BATTMONITOR_RSRVD3(v) (((v) << 26) & 0xfc000000) | ||
707 | #define BP_POWER_BATTMONITOR_BATT_VAL 16 | ||
708 | #define BM_POWER_BATTMONITOR_BATT_VAL 0x3ff0000 | ||
709 | #define BF_POWER_BATTMONITOR_BATT_VAL(v) (((v) << 16) & 0x3ff0000) | ||
710 | #define BP_POWER_BATTMONITOR_RSRVD2 11 | ||
711 | #define BM_POWER_BATTMONITOR_RSRVD2 0xf800 | ||
712 | #define BF_POWER_BATTMONITOR_RSRVD2(v) (((v) << 11) & 0xf800) | ||
713 | #define BP_POWER_BATTMONITOR_EN_BATADJ 10 | ||
714 | #define BM_POWER_BATTMONITOR_EN_BATADJ 0x400 | ||
715 | #define BF_POWER_BATTMONITOR_EN_BATADJ(v) (((v) << 10) & 0x400) | ||
716 | #define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT 9 | ||
717 | #define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x200 | ||
718 | #define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200) | ||
719 | #define BP_POWER_BATTMONITOR_BRWNOUT_PWD 8 | ||
720 | #define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x100 | ||
721 | #define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v) (((v) << 8) & 0x100) | ||
722 | #define BP_POWER_BATTMONITOR_RSRVD1 5 | ||
723 | #define BM_POWER_BATTMONITOR_RSRVD1 0xe0 | ||
724 | #define BF_POWER_BATTMONITOR_RSRVD1(v) (((v) << 5) & 0xe0) | ||
725 | #define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 | ||
726 | #define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x1f | ||
727 | #define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) (((v) << 0) & 0x1f) | ||
728 | |||
729 | /** | ||
730 | * Register: HW_POWER_RESET | ||
731 | * Address: 0x100 | ||
732 | * SCT: yes | ||
733 | */ | ||
734 | #define HW_POWER_RESET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0)) | ||
735 | #define HW_POWER_RESET_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4)) | ||
736 | #define HW_POWER_RESET_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8)) | ||
737 | #define HW_POWER_RESET_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc)) | ||
738 | #define BP_POWER_RESET_UNLOCK 16 | ||
739 | #define BM_POWER_RESET_UNLOCK 0xffff0000 | ||
740 | #define BV_POWER_RESET_UNLOCK__KEY 0x3e77 | ||
741 | #define BF_POWER_RESET_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
742 | #define BF_POWER_RESET_UNLOCK_V(v) ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000) | ||
743 | #define BP_POWER_RESET_RSRVD1 2 | ||
744 | #define BM_POWER_RESET_RSRVD1 0xfffc | ||
745 | #define BF_POWER_RESET_RSRVD1(v) (((v) << 2) & 0xfffc) | ||
746 | #define BP_POWER_RESET_PWD_OFF 1 | ||
747 | #define BM_POWER_RESET_PWD_OFF 0x2 | ||
748 | #define BF_POWER_RESET_PWD_OFF(v) (((v) << 1) & 0x2) | ||
749 | #define BP_POWER_RESET_PWD 0 | ||
750 | #define BM_POWER_RESET_PWD 0x1 | ||
751 | #define BF_POWER_RESET_PWD(v) (((v) << 0) & 0x1) | ||
752 | |||
753 | /** | ||
754 | * Register: HW_POWER_DEBUG | ||
755 | * Address: 0x110 | ||
756 | * SCT: yes | ||
757 | */ | ||
758 | #define HW_POWER_DEBUG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x0)) | ||
759 | #define HW_POWER_DEBUG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x4)) | ||
760 | #define HW_POWER_DEBUG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x8)) | ||
761 | #define HW_POWER_DEBUG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0xc)) | ||
762 | #define BP_POWER_DEBUG_RSRVD0 4 | ||
763 | #define BM_POWER_DEBUG_RSRVD0 0xfffffff0 | ||
764 | #define BF_POWER_DEBUG_RSRVD0(v) (((v) << 4) & 0xfffffff0) | ||
765 | #define BP_POWER_DEBUG_VBUSVALIDPIOLOCK 3 | ||
766 | #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x8 | ||
767 | #define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v) (((v) << 3) & 0x8) | ||
768 | #define BP_POWER_DEBUG_AVALIDPIOLOCK 2 | ||
769 | #define BM_POWER_DEBUG_AVALIDPIOLOCK 0x4 | ||
770 | #define BF_POWER_DEBUG_AVALIDPIOLOCK(v) (((v) << 2) & 0x4) | ||
771 | #define BP_POWER_DEBUG_BVALIDPIOLOCK 1 | ||
772 | #define BM_POWER_DEBUG_BVALIDPIOLOCK 0x2 | ||
773 | #define BF_POWER_DEBUG_BVALIDPIOLOCK(v) (((v) << 1) & 0x2) | ||
774 | #define BP_POWER_DEBUG_SESSENDPIOLOCK 0 | ||
775 | #define BM_POWER_DEBUG_SESSENDPIOLOCK 0x1 | ||
776 | #define BF_POWER_DEBUG_SESSENDPIOLOCK(v) (((v) << 0) & 0x1) | ||
777 | |||
778 | /** | ||
779 | * Register: HW_POWER_SPECIAL | ||
780 | * Address: 0x120 | ||
781 | * SCT: yes | ||
782 | */ | ||
783 | #define HW_POWER_SPECIAL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x0)) | ||
784 | #define HW_POWER_SPECIAL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x4)) | ||
785 | #define HW_POWER_SPECIAL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x8)) | ||
786 | #define HW_POWER_SPECIAL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0xc)) | ||
787 | #define BP_POWER_SPECIAL_TEST 0 | ||
788 | #define BM_POWER_SPECIAL_TEST 0xffffffff | ||
789 | #define BF_POWER_SPECIAL_TEST(v) (((v) << 0) & 0xffffffff) | ||
790 | |||
791 | /** | ||
792 | * Register: HW_POWER_VERSION | ||
793 | * Address: 0x130 | ||
794 | * SCT: no | ||
795 | */ | ||
796 | #define HW_POWER_VERSION (*(volatile unsigned long *)(REGS_POWER_BASE + 0x130)) | ||
797 | #define BP_POWER_VERSION_MAJOR 24 | ||
798 | #define BM_POWER_VERSION_MAJOR 0xff000000 | ||
799 | #define BF_POWER_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
800 | #define BP_POWER_VERSION_MINOR 16 | ||
801 | #define BM_POWER_VERSION_MINOR 0xff0000 | ||
802 | #define BF_POWER_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
803 | #define BP_POWER_VERSION_STEP 0 | ||
804 | #define BM_POWER_VERSION_STEP 0xffff | ||
805 | #define BF_POWER_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
806 | |||
807 | #endif /* __HEADERGEN__IMX233__POWER__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pwm.h b/firmware/target/arm/imx233/regs/imx233/regs-pwm.h new file mode 100644 index 0000000000..2a822714d8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-pwm.h | |||
@@ -0,0 +1,165 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__PWM__H__ | ||
24 | #define __HEADERGEN__IMX233__PWM__H__ | ||
25 | |||
26 | #define REGS_PWM_BASE (0x80064000) | ||
27 | |||
28 | #define REGS_PWM_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_PWM_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_PWM_CTRL (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0)) | ||
36 | #define HW_PWM_CTRL_SET (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4)) | ||
37 | #define HW_PWM_CTRL_CLR (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8)) | ||
38 | #define HW_PWM_CTRL_TOG (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc)) | ||
39 | #define BP_PWM_CTRL_SFTRST 31 | ||
40 | #define BM_PWM_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_PWM_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_PWM_CTRL_CLKGATE 30 | ||
43 | #define BM_PWM_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_PWM_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_PWM_CTRL_PWM4_PRESENT 29 | ||
46 | #define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 | ||
47 | #define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_PWM_CTRL_PWM3_PRESENT 28 | ||
49 | #define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 | ||
50 | #define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_PWM_CTRL_PWM2_PRESENT 27 | ||
52 | #define BM_PWM_CTRL_PWM2_PRESENT 0x8000000 | ||
53 | #define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_PWM_CTRL_PWM1_PRESENT 26 | ||
55 | #define BM_PWM_CTRL_PWM1_PRESENT 0x4000000 | ||
56 | #define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_PWM_CTRL_PWM0_PRESENT 25 | ||
58 | #define BM_PWM_CTRL_PWM0_PRESENT 0x2000000 | ||
59 | #define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_PWM_CTRL_RSRVD1 7 | ||
61 | #define BM_PWM_CTRL_RSRVD1 0x1ffff80 | ||
62 | #define BF_PWM_CTRL_RSRVD1(v) (((v) << 7) & 0x1ffff80) | ||
63 | #define BP_PWM_CTRL_OUTPUT_CUTOFF_EN 6 | ||
64 | #define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x40 | ||
65 | #define BF_PWM_CTRL_OUTPUT_CUTOFF_EN(v) (((v) << 6) & 0x40) | ||
66 | #define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 5 | ||
67 | #define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x20 | ||
68 | #define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v) (((v) << 5) & 0x20) | ||
69 | #define BP_PWM_CTRL_PWM4_ENABLE 4 | ||
70 | #define BM_PWM_CTRL_PWM4_ENABLE 0x10 | ||
71 | #define BF_PWM_CTRL_PWM4_ENABLE(v) (((v) << 4) & 0x10) | ||
72 | #define BP_PWM_CTRL_PWM3_ENABLE 3 | ||
73 | #define BM_PWM_CTRL_PWM3_ENABLE 0x8 | ||
74 | #define BF_PWM_CTRL_PWM3_ENABLE(v) (((v) << 3) & 0x8) | ||
75 | #define BP_PWM_CTRL_PWM2_ENABLE 2 | ||
76 | #define BM_PWM_CTRL_PWM2_ENABLE 0x4 | ||
77 | #define BF_PWM_CTRL_PWM2_ENABLE(v) (((v) << 2) & 0x4) | ||
78 | #define BP_PWM_CTRL_PWM1_ENABLE 1 | ||
79 | #define BM_PWM_CTRL_PWM1_ENABLE 0x2 | ||
80 | #define BF_PWM_CTRL_PWM1_ENABLE(v) (((v) << 1) & 0x2) | ||
81 | #define BP_PWM_CTRL_PWM0_ENABLE 0 | ||
82 | #define BM_PWM_CTRL_PWM0_ENABLE 0x1 | ||
83 | #define BF_PWM_CTRL_PWM0_ENABLE(v) (((v) << 0) & 0x1) | ||
84 | |||
85 | /** | ||
86 | * Register: HW_PWM_ACTIVEn | ||
87 | * Address: 0x10+n*0x20 | ||
88 | * SCT: yes | ||
89 | */ | ||
90 | #define HW_PWM_ACTIVEn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0)) | ||
91 | #define HW_PWM_ACTIVEn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4)) | ||
92 | #define HW_PWM_ACTIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8)) | ||
93 | #define HW_PWM_ACTIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc)) | ||
94 | #define BP_PWM_ACTIVEn_INACTIVE 16 | ||
95 | #define BM_PWM_ACTIVEn_INACTIVE 0xffff0000 | ||
96 | #define BF_PWM_ACTIVEn_INACTIVE(v) (((v) << 16) & 0xffff0000) | ||
97 | #define BP_PWM_ACTIVEn_ACTIVE 0 | ||
98 | #define BM_PWM_ACTIVEn_ACTIVE 0xffff | ||
99 | #define BF_PWM_ACTIVEn_ACTIVE(v) (((v) << 0) & 0xffff) | ||
100 | |||
101 | /** | ||
102 | * Register: HW_PWM_PERIODn | ||
103 | * Address: 0x20+n*0x20 | ||
104 | * SCT: yes | ||
105 | */ | ||
106 | #define HW_PWM_PERIODn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0)) | ||
107 | #define HW_PWM_PERIODn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4)) | ||
108 | #define HW_PWM_PERIODn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8)) | ||
109 | #define HW_PWM_PERIODn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc)) | ||
110 | #define BP_PWM_PERIODn_RSRVD2 25 | ||
111 | #define BM_PWM_PERIODn_RSRVD2 0xfe000000 | ||
112 | #define BF_PWM_PERIODn_RSRVD2(v) (((v) << 25) & 0xfe000000) | ||
113 | #define BP_PWM_PERIODn_MATT_SEL 24 | ||
114 | #define BM_PWM_PERIODn_MATT_SEL 0x1000000 | ||
115 | #define BF_PWM_PERIODn_MATT_SEL(v) (((v) << 24) & 0x1000000) | ||
116 | #define BP_PWM_PERIODn_MATT 23 | ||
117 | #define BM_PWM_PERIODn_MATT 0x800000 | ||
118 | #define BF_PWM_PERIODn_MATT(v) (((v) << 23) & 0x800000) | ||
119 | #define BP_PWM_PERIODn_CDIV 20 | ||
120 | #define BM_PWM_PERIODn_CDIV 0x700000 | ||
121 | #define BV_PWM_PERIODn_CDIV__DIV_1 0x0 | ||
122 | #define BV_PWM_PERIODn_CDIV__DIV_2 0x1 | ||
123 | #define BV_PWM_PERIODn_CDIV__DIV_4 0x2 | ||
124 | #define BV_PWM_PERIODn_CDIV__DIV_8 0x3 | ||
125 | #define BV_PWM_PERIODn_CDIV__DIV_16 0x4 | ||
126 | #define BV_PWM_PERIODn_CDIV__DIV_64 0x5 | ||
127 | #define BV_PWM_PERIODn_CDIV__DIV_256 0x6 | ||
128 | #define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 | ||
129 | #define BF_PWM_PERIODn_CDIV(v) (((v) << 20) & 0x700000) | ||
130 | #define BF_PWM_PERIODn_CDIV_V(v) ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000) | ||
131 | #define BP_PWM_PERIODn_INACTIVE_STATE 18 | ||
132 | #define BM_PWM_PERIODn_INACTIVE_STATE 0xc0000 | ||
133 | #define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 | ||
134 | #define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 | ||
135 | #define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 | ||
136 | #define BF_PWM_PERIODn_INACTIVE_STATE(v) (((v) << 18) & 0xc0000) | ||
137 | #define BF_PWM_PERIODn_INACTIVE_STATE_V(v) ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000) | ||
138 | #define BP_PWM_PERIODn_ACTIVE_STATE 16 | ||
139 | #define BM_PWM_PERIODn_ACTIVE_STATE 0x30000 | ||
140 | #define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 | ||
141 | #define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 | ||
142 | #define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 | ||
143 | #define BF_PWM_PERIODn_ACTIVE_STATE(v) (((v) << 16) & 0x30000) | ||
144 | #define BF_PWM_PERIODn_ACTIVE_STATE_V(v) ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000) | ||
145 | #define BP_PWM_PERIODn_PERIOD 0 | ||
146 | #define BM_PWM_PERIODn_PERIOD 0xffff | ||
147 | #define BF_PWM_PERIODn_PERIOD(v) (((v) << 0) & 0xffff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_PWM_VERSION | ||
151 | * Address: 0xb0 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_PWM_VERSION (*(volatile unsigned long *)(REGS_PWM_BASE + 0xb0)) | ||
155 | #define BP_PWM_VERSION_MAJOR 24 | ||
156 | #define BM_PWM_VERSION_MAJOR 0xff000000 | ||
157 | #define BF_PWM_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
158 | #define BP_PWM_VERSION_MINOR 16 | ||
159 | #define BM_PWM_VERSION_MINOR 0xff0000 | ||
160 | #define BF_PWM_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
161 | #define BP_PWM_VERSION_STEP 0 | ||
162 | #define BM_PWM_VERSION_STEP 0xffff | ||
163 | #define BF_PWM_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
164 | |||
165 | #endif /* __HEADERGEN__IMX233__PWM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pxp.h b/firmware/target/arm/imx233/regs/imx233/regs-pxp.h new file mode 100644 index 0000000000..839998a2d1 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-pxp.h | |||
@@ -0,0 +1,612 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__PXP__H__ | ||
24 | #define __HEADERGEN__IMX233__PXP__H__ | ||
25 | |||
26 | #define REGS_PXP_BASE (0x8002a000) | ||
27 | |||
28 | #define REGS_PXP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_PXP_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_PXP_CTRL (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_PXP_CTRL_SET (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_PXP_CTRL_CLR (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_PXP_CTRL_TOG (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_PXP_CTRL_SFTRST 31 | ||
40 | #define BM_PXP_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_PXP_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_PXP_CTRL_CLKGATE 30 | ||
43 | #define BM_PXP_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_PXP_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_PXP_CTRL_RSVD2 28 | ||
46 | #define BM_PXP_CTRL_RSVD2 0x30000000 | ||
47 | #define BF_PXP_CTRL_RSVD2(v) (((v) << 28) & 0x30000000) | ||
48 | #define BP_PXP_CTRL_INTERLACED_OUTPUT 26 | ||
49 | #define BM_PXP_CTRL_INTERLACED_OUTPUT 0xc000000 | ||
50 | #define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 | ||
51 | #define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 | ||
52 | #define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 | ||
53 | #define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 | ||
54 | #define BF_PXP_CTRL_INTERLACED_OUTPUT(v) (((v) << 26) & 0xc000000) | ||
55 | #define BF_PXP_CTRL_INTERLACED_OUTPUT_V(v) ((BV_PXP_CTRL_INTERLACED_OUTPUT__##v << 26) & 0xc000000) | ||
56 | #define BP_PXP_CTRL_INTERLACED_INPUT 24 | ||
57 | #define BM_PXP_CTRL_INTERLACED_INPUT 0x3000000 | ||
58 | #define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 | ||
59 | #define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 | ||
60 | #define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 | ||
61 | #define BF_PXP_CTRL_INTERLACED_INPUT(v) (((v) << 24) & 0x3000000) | ||
62 | #define BF_PXP_CTRL_INTERLACED_INPUT_V(v) ((BV_PXP_CTRL_INTERLACED_INPUT__##v << 24) & 0x3000000) | ||
63 | #define BP_PXP_CTRL_RSVD1 23 | ||
64 | #define BM_PXP_CTRL_RSVD1 0x800000 | ||
65 | #define BF_PXP_CTRL_RSVD1(v) (((v) << 23) & 0x800000) | ||
66 | #define BP_PXP_CTRL_ALPHA_OUTPUT 22 | ||
67 | #define BM_PXP_CTRL_ALPHA_OUTPUT 0x400000 | ||
68 | #define BF_PXP_CTRL_ALPHA_OUTPUT(v) (((v) << 22) & 0x400000) | ||
69 | #define BP_PXP_CTRL_IN_PLACE 21 | ||
70 | #define BM_PXP_CTRL_IN_PLACE 0x200000 | ||
71 | #define BF_PXP_CTRL_IN_PLACE(v) (((v) << 21) & 0x200000) | ||
72 | #define BP_PXP_CTRL_DELTA 20 | ||
73 | #define BM_PXP_CTRL_DELTA 0x100000 | ||
74 | #define BF_PXP_CTRL_DELTA(v) (((v) << 20) & 0x100000) | ||
75 | #define BP_PXP_CTRL_CROP 19 | ||
76 | #define BM_PXP_CTRL_CROP 0x80000 | ||
77 | #define BF_PXP_CTRL_CROP(v) (((v) << 19) & 0x80000) | ||
78 | #define BP_PXP_CTRL_SCALE 18 | ||
79 | #define BM_PXP_CTRL_SCALE 0x40000 | ||
80 | #define BF_PXP_CTRL_SCALE(v) (((v) << 18) & 0x40000) | ||
81 | #define BP_PXP_CTRL_UPSAMPLE 17 | ||
82 | #define BM_PXP_CTRL_UPSAMPLE 0x20000 | ||
83 | #define BF_PXP_CTRL_UPSAMPLE(v) (((v) << 17) & 0x20000) | ||
84 | #define BP_PXP_CTRL_SUBSAMPLE 16 | ||
85 | #define BM_PXP_CTRL_SUBSAMPLE 0x10000 | ||
86 | #define BF_PXP_CTRL_SUBSAMPLE(v) (((v) << 16) & 0x10000) | ||
87 | #define BP_PXP_CTRL_S0_FORMAT 12 | ||
88 | #define BM_PXP_CTRL_S0_FORMAT 0xf000 | ||
89 | #define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 | ||
90 | #define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 | ||
91 | #define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 | ||
92 | #define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 | ||
93 | #define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 | ||
94 | #define BF_PXP_CTRL_S0_FORMAT(v) (((v) << 12) & 0xf000) | ||
95 | #define BF_PXP_CTRL_S0_FORMAT_V(v) ((BV_PXP_CTRL_S0_FORMAT__##v << 12) & 0xf000) | ||
96 | #define BP_PXP_CTRL_VFLIP 11 | ||
97 | #define BM_PXP_CTRL_VFLIP 0x800 | ||
98 | #define BF_PXP_CTRL_VFLIP(v) (((v) << 11) & 0x800) | ||
99 | #define BP_PXP_CTRL_HFLIP 10 | ||
100 | #define BM_PXP_CTRL_HFLIP 0x400 | ||
101 | #define BF_PXP_CTRL_HFLIP(v) (((v) << 10) & 0x400) | ||
102 | #define BP_PXP_CTRL_ROTATE 8 | ||
103 | #define BM_PXP_CTRL_ROTATE 0x300 | ||
104 | #define BV_PXP_CTRL_ROTATE__ROT_0 0x0 | ||
105 | #define BV_PXP_CTRL_ROTATE__ROT_90 0x1 | ||
106 | #define BV_PXP_CTRL_ROTATE__ROT_180 0x2 | ||
107 | #define BV_PXP_CTRL_ROTATE__ROT_270 0x3 | ||
108 | #define BF_PXP_CTRL_ROTATE(v) (((v) << 8) & 0x300) | ||
109 | #define BF_PXP_CTRL_ROTATE_V(v) ((BV_PXP_CTRL_ROTATE__##v << 8) & 0x300) | ||
110 | #define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 | ||
111 | #define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0xf0 | ||
112 | #define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888 0x0 | ||
113 | #define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888 0x1 | ||
114 | #define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P 0x2 | ||
115 | #define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555 0x3 | ||
116 | #define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565 0x4 | ||
117 | #define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555 0x5 | ||
118 | #define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v) (((v) << 4) & 0xf0) | ||
119 | #define BF_PXP_CTRL_OUTPUT_RGB_FORMAT_V(v) ((BV_PXP_CTRL_OUTPUT_RGB_FORMAT__##v << 4) & 0xf0) | ||
120 | #define BP_PXP_CTRL_RSVD0 3 | ||
121 | #define BM_PXP_CTRL_RSVD0 0x8 | ||
122 | #define BF_PXP_CTRL_RSVD0(v) (((v) << 3) & 0x8) | ||
123 | #define BP_PXP_CTRL_ENABLE_LCD_HANDSHAKE 2 | ||
124 | #define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x4 | ||
125 | #define BF_PXP_CTRL_ENABLE_LCD_HANDSHAKE(v) (((v) << 2) & 0x4) | ||
126 | #define BP_PXP_CTRL_IRQ_ENABLE 1 | ||
127 | #define BM_PXP_CTRL_IRQ_ENABLE 0x2 | ||
128 | #define BF_PXP_CTRL_IRQ_ENABLE(v) (((v) << 1) & 0x2) | ||
129 | #define BP_PXP_CTRL_ENABLE 0 | ||
130 | #define BM_PXP_CTRL_ENABLE 0x1 | ||
131 | #define BF_PXP_CTRL_ENABLE(v) (((v) << 0) & 0x1) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_PXP_STAT | ||
135 | * Address: 0x10 | ||
136 | * SCT: yes | ||
137 | */ | ||
138 | #define HW_PXP_STAT (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x0)) | ||
139 | #define HW_PXP_STAT_SET (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x4)) | ||
140 | #define HW_PXP_STAT_CLR (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x8)) | ||
141 | #define HW_PXP_STAT_TOG (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0xc)) | ||
142 | #define BP_PXP_STAT_BLOCKX 24 | ||
143 | #define BM_PXP_STAT_BLOCKX 0xff000000 | ||
144 | #define BF_PXP_STAT_BLOCKX(v) (((v) << 24) & 0xff000000) | ||
145 | #define BP_PXP_STAT_BLOCKY 16 | ||
146 | #define BM_PXP_STAT_BLOCKY 0xff0000 | ||
147 | #define BF_PXP_STAT_BLOCKY(v) (((v) << 16) & 0xff0000) | ||
148 | #define BP_PXP_STAT_RSVD2 8 | ||
149 | #define BM_PXP_STAT_RSVD2 0xff00 | ||
150 | #define BF_PXP_STAT_RSVD2(v) (((v) << 8) & 0xff00) | ||
151 | #define BP_PXP_STAT_AXI_ERROR_ID 4 | ||
152 | #define BM_PXP_STAT_AXI_ERROR_ID 0xf0 | ||
153 | #define BF_PXP_STAT_AXI_ERROR_ID(v) (((v) << 4) & 0xf0) | ||
154 | #define BP_PXP_STAT_RSVD1 3 | ||
155 | #define BM_PXP_STAT_RSVD1 0x8 | ||
156 | #define BF_PXP_STAT_RSVD1(v) (((v) << 3) & 0x8) | ||
157 | #define BP_PXP_STAT_AXI_READ_ERROR 2 | ||
158 | #define BM_PXP_STAT_AXI_READ_ERROR 0x4 | ||
159 | #define BF_PXP_STAT_AXI_READ_ERROR(v) (((v) << 2) & 0x4) | ||
160 | #define BP_PXP_STAT_AXI_WRITE_ERROR 1 | ||
161 | #define BM_PXP_STAT_AXI_WRITE_ERROR 0x2 | ||
162 | #define BF_PXP_STAT_AXI_WRITE_ERROR(v) (((v) << 1) & 0x2) | ||
163 | #define BP_PXP_STAT_IRQ 0 | ||
164 | #define BM_PXP_STAT_IRQ 0x1 | ||
165 | #define BF_PXP_STAT_IRQ(v) (((v) << 0) & 0x1) | ||
166 | |||
167 | /** | ||
168 | * Register: HW_PXP_RGBBUF | ||
169 | * Address: 0x20 | ||
170 | * SCT: no | ||
171 | */ | ||
172 | #define HW_PXP_RGBBUF (*(volatile unsigned long *)(REGS_PXP_BASE + 0x20)) | ||
173 | #define BP_PXP_RGBBUF_ADDR 0 | ||
174 | #define BM_PXP_RGBBUF_ADDR 0xffffffff | ||
175 | #define BF_PXP_RGBBUF_ADDR(v) (((v) << 0) & 0xffffffff) | ||
176 | |||
177 | /** | ||
178 | * Register: HW_PXP_RGBBUF2 | ||
179 | * Address: 0x30 | ||
180 | * SCT: no | ||
181 | */ | ||
182 | #define HW_PXP_RGBBUF2 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x30)) | ||
183 | #define BP_PXP_RGBBUF2_ADDR 0 | ||
184 | #define BM_PXP_RGBBUF2_ADDR 0xffffffff | ||
185 | #define BF_PXP_RGBBUF2_ADDR(v) (((v) << 0) & 0xffffffff) | ||
186 | |||
187 | /** | ||
188 | * Register: HW_PXP_RGBSIZE | ||
189 | * Address: 0x40 | ||
190 | * SCT: no | ||
191 | */ | ||
192 | #define HW_PXP_RGBSIZE (*(volatile unsigned long *)(REGS_PXP_BASE + 0x40)) | ||
193 | #define BP_PXP_RGBSIZE_ALPHA 24 | ||
194 | #define BM_PXP_RGBSIZE_ALPHA 0xff000000 | ||
195 | #define BF_PXP_RGBSIZE_ALPHA(v) (((v) << 24) & 0xff000000) | ||
196 | #define BP_PXP_RGBSIZE_WIDTH 12 | ||
197 | #define BM_PXP_RGBSIZE_WIDTH 0xfff000 | ||
198 | #define BF_PXP_RGBSIZE_WIDTH(v) (((v) << 12) & 0xfff000) | ||
199 | #define BP_PXP_RGBSIZE_HEIGHT 0 | ||
200 | #define BM_PXP_RGBSIZE_HEIGHT 0xfff | ||
201 | #define BF_PXP_RGBSIZE_HEIGHT(v) (((v) << 0) & 0xfff) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_PXP_S0BUF | ||
205 | * Address: 0x50 | ||
206 | * SCT: no | ||
207 | */ | ||
208 | #define HW_PXP_S0BUF (*(volatile unsigned long *)(REGS_PXP_BASE + 0x50)) | ||
209 | #define BP_PXP_S0BUF_ADDR 0 | ||
210 | #define BM_PXP_S0BUF_ADDR 0xffffffff | ||
211 | #define BF_PXP_S0BUF_ADDR(v) (((v) << 0) & 0xffffffff) | ||
212 | |||
213 | /** | ||
214 | * Register: HW_PXP_S0UBUF | ||
215 | * Address: 0x60 | ||
216 | * SCT: no | ||
217 | */ | ||
218 | #define HW_PXP_S0UBUF (*(volatile unsigned long *)(REGS_PXP_BASE + 0x60)) | ||
219 | #define BP_PXP_S0UBUF_ADDR 0 | ||
220 | #define BM_PXP_S0UBUF_ADDR 0xffffffff | ||
221 | #define BF_PXP_S0UBUF_ADDR(v) (((v) << 0) & 0xffffffff) | ||
222 | |||
223 | /** | ||
224 | * Register: HW_PXP_S0VBUF | ||
225 | * Address: 0x70 | ||
226 | * SCT: no | ||
227 | */ | ||
228 | #define HW_PXP_S0VBUF (*(volatile unsigned long *)(REGS_PXP_BASE + 0x70)) | ||
229 | #define BP_PXP_S0VBUF_ADDR 0 | ||
230 | #define BM_PXP_S0VBUF_ADDR 0xffffffff | ||
231 | #define BF_PXP_S0VBUF_ADDR(v) (((v) << 0) & 0xffffffff) | ||
232 | |||
233 | /** | ||
234 | * Register: HW_PXP_S0PARAM | ||
235 | * Address: 0x80 | ||
236 | * SCT: no | ||
237 | */ | ||
238 | #define HW_PXP_S0PARAM (*(volatile unsigned long *)(REGS_PXP_BASE + 0x80)) | ||
239 | #define BP_PXP_S0PARAM_XBASE 24 | ||
240 | #define BM_PXP_S0PARAM_XBASE 0xff000000 | ||
241 | #define BF_PXP_S0PARAM_XBASE(v) (((v) << 24) & 0xff000000) | ||
242 | #define BP_PXP_S0PARAM_YBASE 16 | ||
243 | #define BM_PXP_S0PARAM_YBASE 0xff0000 | ||
244 | #define BF_PXP_S0PARAM_YBASE(v) (((v) << 16) & 0xff0000) | ||
245 | #define BP_PXP_S0PARAM_WIDTH 8 | ||
246 | #define BM_PXP_S0PARAM_WIDTH 0xff00 | ||
247 | #define BF_PXP_S0PARAM_WIDTH(v) (((v) << 8) & 0xff00) | ||
248 | #define BP_PXP_S0PARAM_HEIGHT 0 | ||
249 | #define BM_PXP_S0PARAM_HEIGHT 0xff | ||
250 | #define BF_PXP_S0PARAM_HEIGHT(v) (((v) << 0) & 0xff) | ||
251 | |||
252 | /** | ||
253 | * Register: HW_PXP_S0BACKGROUND | ||
254 | * Address: 0x90 | ||
255 | * SCT: no | ||
256 | */ | ||
257 | #define HW_PXP_S0BACKGROUND (*(volatile unsigned long *)(REGS_PXP_BASE + 0x90)) | ||
258 | #define BP_PXP_S0BACKGROUND_COLOR 0 | ||
259 | #define BM_PXP_S0BACKGROUND_COLOR 0xffffffff | ||
260 | #define BF_PXP_S0BACKGROUND_COLOR(v) (((v) << 0) & 0xffffffff) | ||
261 | |||
262 | /** | ||
263 | * Register: HW_PXP_S0CROP | ||
264 | * Address: 0xa0 | ||
265 | * SCT: no | ||
266 | */ | ||
267 | #define HW_PXP_S0CROP (*(volatile unsigned long *)(REGS_PXP_BASE + 0xa0)) | ||
268 | #define BP_PXP_S0CROP_XBASE 24 | ||
269 | #define BM_PXP_S0CROP_XBASE 0xff000000 | ||
270 | #define BF_PXP_S0CROP_XBASE(v) (((v) << 24) & 0xff000000) | ||
271 | #define BP_PXP_S0CROP_YBASE 16 | ||
272 | #define BM_PXP_S0CROP_YBASE 0xff0000 | ||
273 | #define BF_PXP_S0CROP_YBASE(v) (((v) << 16) & 0xff0000) | ||
274 | #define BP_PXP_S0CROP_WIDTH 8 | ||
275 | #define BM_PXP_S0CROP_WIDTH 0xff00 | ||
276 | #define BF_PXP_S0CROP_WIDTH(v) (((v) << 8) & 0xff00) | ||
277 | #define BP_PXP_S0CROP_HEIGHT 0 | ||
278 | #define BM_PXP_S0CROP_HEIGHT 0xff | ||
279 | #define BF_PXP_S0CROP_HEIGHT(v) (((v) << 0) & 0xff) | ||
280 | |||
281 | /** | ||
282 | * Register: HW_PXP_S0SCALE | ||
283 | * Address: 0xb0 | ||
284 | * SCT: no | ||
285 | */ | ||
286 | #define HW_PXP_S0SCALE (*(volatile unsigned long *)(REGS_PXP_BASE + 0xb0)) | ||
287 | #define BP_PXP_S0SCALE_RSVD2 30 | ||
288 | #define BM_PXP_S0SCALE_RSVD2 0xc0000000 | ||
289 | #define BF_PXP_S0SCALE_RSVD2(v) (((v) << 30) & 0xc0000000) | ||
290 | #define BP_PXP_S0SCALE_YSCALE 16 | ||
291 | #define BM_PXP_S0SCALE_YSCALE 0x3fff0000 | ||
292 | #define BF_PXP_S0SCALE_YSCALE(v) (((v) << 16) & 0x3fff0000) | ||
293 | #define BP_PXP_S0SCALE_RSVD1 14 | ||
294 | #define BM_PXP_S0SCALE_RSVD1 0xc000 | ||
295 | #define BF_PXP_S0SCALE_RSVD1(v) (((v) << 14) & 0xc000) | ||
296 | #define BP_PXP_S0SCALE_XSCALE 0 | ||
297 | #define BM_PXP_S0SCALE_XSCALE 0x3fff | ||
298 | #define BF_PXP_S0SCALE_XSCALE(v) (((v) << 0) & 0x3fff) | ||
299 | |||
300 | /** | ||
301 | * Register: HW_PXP_S0OFFSET | ||
302 | * Address: 0xc0 | ||
303 | * SCT: no | ||
304 | */ | ||
305 | #define HW_PXP_S0OFFSET (*(volatile unsigned long *)(REGS_PXP_BASE + 0xc0)) | ||
306 | #define BP_PXP_S0OFFSET_RSVD2 28 | ||
307 | #define BM_PXP_S0OFFSET_RSVD2 0xf0000000 | ||
308 | #define BF_PXP_S0OFFSET_RSVD2(v) (((v) << 28) & 0xf0000000) | ||
309 | #define BP_PXP_S0OFFSET_YOFFSET 16 | ||
310 | #define BM_PXP_S0OFFSET_YOFFSET 0xfff0000 | ||
311 | #define BF_PXP_S0OFFSET_YOFFSET(v) (((v) << 16) & 0xfff0000) | ||
312 | #define BP_PXP_S0OFFSET_RSVD1 12 | ||
313 | #define BM_PXP_S0OFFSET_RSVD1 0xf000 | ||
314 | #define BF_PXP_S0OFFSET_RSVD1(v) (((v) << 12) & 0xf000) | ||
315 | #define BP_PXP_S0OFFSET_XOFFSET 0 | ||
316 | #define BM_PXP_S0OFFSET_XOFFSET 0xfff | ||
317 | #define BF_PXP_S0OFFSET_XOFFSET(v) (((v) << 0) & 0xfff) | ||
318 | |||
319 | /** | ||
320 | * Register: HW_PXP_CSCCOEFF0 | ||
321 | * Address: 0xd0 | ||
322 | * SCT: no | ||
323 | */ | ||
324 | #define HW_PXP_CSCCOEFF0 (*(volatile unsigned long *)(REGS_PXP_BASE + 0xd0)) | ||
325 | #define BP_PXP_CSCCOEFF0_YCBCR_MODE 31 | ||
326 | #define BM_PXP_CSCCOEFF0_YCBCR_MODE 0x80000000 | ||
327 | #define BF_PXP_CSCCOEFF0_YCBCR_MODE(v) (((v) << 31) & 0x80000000) | ||
328 | #define BP_PXP_CSCCOEFF0_RSVD1 29 | ||
329 | #define BM_PXP_CSCCOEFF0_RSVD1 0x60000000 | ||
330 | #define BF_PXP_CSCCOEFF0_RSVD1(v) (((v) << 29) & 0x60000000) | ||
331 | #define BP_PXP_CSCCOEFF0_C0 18 | ||
332 | #define BM_PXP_CSCCOEFF0_C0 0x1ffc0000 | ||
333 | #define BF_PXP_CSCCOEFF0_C0(v) (((v) << 18) & 0x1ffc0000) | ||
334 | #define BP_PXP_CSCCOEFF0_UV_OFFSET 9 | ||
335 | #define BM_PXP_CSCCOEFF0_UV_OFFSET 0x3fe00 | ||
336 | #define BF_PXP_CSCCOEFF0_UV_OFFSET(v) (((v) << 9) & 0x3fe00) | ||
337 | #define BP_PXP_CSCCOEFF0_Y_OFFSET 0 | ||
338 | #define BM_PXP_CSCCOEFF0_Y_OFFSET 0x1ff | ||
339 | #define BF_PXP_CSCCOEFF0_Y_OFFSET(v) (((v) << 0) & 0x1ff) | ||
340 | |||
341 | /** | ||
342 | * Register: HW_PXP_CSCCOEFF1 | ||
343 | * Address: 0xe0 | ||
344 | * SCT: no | ||
345 | */ | ||
346 | #define HW_PXP_CSCCOEFF1 (*(volatile unsigned long *)(REGS_PXP_BASE + 0xe0)) | ||
347 | #define BP_PXP_CSCCOEFF1_RSVD1 27 | ||
348 | #define BM_PXP_CSCCOEFF1_RSVD1 0xf8000000 | ||
349 | #define BF_PXP_CSCCOEFF1_RSVD1(v) (((v) << 27) & 0xf8000000) | ||
350 | #define BP_PXP_CSCCOEFF1_C1 16 | ||
351 | #define BM_PXP_CSCCOEFF1_C1 0x7ff0000 | ||
352 | #define BF_PXP_CSCCOEFF1_C1(v) (((v) << 16) & 0x7ff0000) | ||
353 | #define BP_PXP_CSCCOEFF1_RSVD0 11 | ||
354 | #define BM_PXP_CSCCOEFF1_RSVD0 0xf800 | ||
355 | #define BF_PXP_CSCCOEFF1_RSVD0(v) (((v) << 11) & 0xf800) | ||
356 | #define BP_PXP_CSCCOEFF1_C4 0 | ||
357 | #define BM_PXP_CSCCOEFF1_C4 0x7ff | ||
358 | #define BF_PXP_CSCCOEFF1_C4(v) (((v) << 0) & 0x7ff) | ||
359 | |||
360 | /** | ||
361 | * Register: HW_PXP_CSCCOEFF2 | ||
362 | * Address: 0xf0 | ||
363 | * SCT: no | ||
364 | */ | ||
365 | #define HW_PXP_CSCCOEFF2 (*(volatile unsigned long *)(REGS_PXP_BASE + 0xf0)) | ||
366 | #define BP_PXP_CSCCOEFF2_RSVD1 27 | ||
367 | #define BM_PXP_CSCCOEFF2_RSVD1 0xf8000000 | ||
368 | #define BF_PXP_CSCCOEFF2_RSVD1(v) (((v) << 27) & 0xf8000000) | ||
369 | #define BP_PXP_CSCCOEFF2_C2 16 | ||
370 | #define BM_PXP_CSCCOEFF2_C2 0x7ff0000 | ||
371 | #define BF_PXP_CSCCOEFF2_C2(v) (((v) << 16) & 0x7ff0000) | ||
372 | #define BP_PXP_CSCCOEFF2_RSVD0 11 | ||
373 | #define BM_PXP_CSCCOEFF2_RSVD0 0xf800 | ||
374 | #define BF_PXP_CSCCOEFF2_RSVD0(v) (((v) << 11) & 0xf800) | ||
375 | #define BP_PXP_CSCCOEFF2_C3 0 | ||
376 | #define BM_PXP_CSCCOEFF2_C3 0x7ff | ||
377 | #define BF_PXP_CSCCOEFF2_C3(v) (((v) << 0) & 0x7ff) | ||
378 | |||
379 | /** | ||
380 | * Register: HW_PXP_NEXT | ||
381 | * Address: 0x100 | ||
382 | * SCT: yes | ||
383 | */ | ||
384 | #define HW_PXP_NEXT (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x0)) | ||
385 | #define HW_PXP_NEXT_SET (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x4)) | ||
386 | #define HW_PXP_NEXT_CLR (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x8)) | ||
387 | #define HW_PXP_NEXT_TOG (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0xc)) | ||
388 | #define BP_PXP_NEXT_POINTER 2 | ||
389 | #define BM_PXP_NEXT_POINTER 0xfffffffc | ||
390 | #define BF_PXP_NEXT_POINTER(v) (((v) << 2) & 0xfffffffc) | ||
391 | #define BP_PXP_NEXT_RSVD 1 | ||
392 | #define BM_PXP_NEXT_RSVD 0x2 | ||
393 | #define BF_PXP_NEXT_RSVD(v) (((v) << 1) & 0x2) | ||
394 | #define BP_PXP_NEXT_ENABLED 0 | ||
395 | #define BM_PXP_NEXT_ENABLED 0x1 | ||
396 | #define BF_PXP_NEXT_ENABLED(v) (((v) << 0) & 0x1) | ||
397 | |||
398 | /** | ||
399 | * Register: HW_PXP_PAGETABLE | ||
400 | * Address: 0x170 | ||
401 | * SCT: no | ||
402 | */ | ||
403 | #define HW_PXP_PAGETABLE (*(volatile unsigned long *)(REGS_PXP_BASE + 0x170)) | ||
404 | #define BP_PXP_PAGETABLE_BASE 14 | ||
405 | #define BM_PXP_PAGETABLE_BASE 0xffffc000 | ||
406 | #define BF_PXP_PAGETABLE_BASE(v) (((v) << 14) & 0xffffc000) | ||
407 | #define BP_PXP_PAGETABLE_RSVD1 2 | ||
408 | #define BM_PXP_PAGETABLE_RSVD1 0x3ffc | ||
409 | #define BF_PXP_PAGETABLE_RSVD1(v) (((v) << 2) & 0x3ffc) | ||
410 | #define BP_PXP_PAGETABLE_FLUSH 1 | ||
411 | #define BM_PXP_PAGETABLE_FLUSH 0x2 | ||
412 | #define BF_PXP_PAGETABLE_FLUSH(v) (((v) << 1) & 0x2) | ||
413 | #define BP_PXP_PAGETABLE_ENABLE 0 | ||
414 | #define BM_PXP_PAGETABLE_ENABLE 0x1 | ||
415 | #define BF_PXP_PAGETABLE_ENABLE(v) (((v) << 0) & 0x1) | ||
416 | |||
417 | /** | ||
418 | * Register: HW_PXP_S0COLORKEYLOW | ||
419 | * Address: 0x180 | ||
420 | * SCT: no | ||
421 | */ | ||
422 | #define HW_PXP_S0COLORKEYLOW (*(volatile unsigned long *)(REGS_PXP_BASE + 0x180)) | ||
423 | #define BP_PXP_S0COLORKEYLOW_RSVD1 24 | ||
424 | #define BM_PXP_S0COLORKEYLOW_RSVD1 0xff000000 | ||
425 | #define BF_PXP_S0COLORKEYLOW_RSVD1(v) (((v) << 24) & 0xff000000) | ||
426 | #define BP_PXP_S0COLORKEYLOW_PIXEL 0 | ||
427 | #define BM_PXP_S0COLORKEYLOW_PIXEL 0xffffff | ||
428 | #define BF_PXP_S0COLORKEYLOW_PIXEL(v) (((v) << 0) & 0xffffff) | ||
429 | |||
430 | /** | ||
431 | * Register: HW_PXP_S0COLORKEYHIGH | ||
432 | * Address: 0x190 | ||
433 | * SCT: no | ||
434 | */ | ||
435 | #define HW_PXP_S0COLORKEYHIGH (*(volatile unsigned long *)(REGS_PXP_BASE + 0x190)) | ||
436 | #define BP_PXP_S0COLORKEYHIGH_RSVD1 24 | ||
437 | #define BM_PXP_S0COLORKEYHIGH_RSVD1 0xff000000 | ||
438 | #define BF_PXP_S0COLORKEYHIGH_RSVD1(v) (((v) << 24) & 0xff000000) | ||
439 | #define BP_PXP_S0COLORKEYHIGH_PIXEL 0 | ||
440 | #define BM_PXP_S0COLORKEYHIGH_PIXEL 0xffffff | ||
441 | #define BF_PXP_S0COLORKEYHIGH_PIXEL(v) (((v) << 0) & 0xffffff) | ||
442 | |||
443 | /** | ||
444 | * Register: HW_PXP_OLCOLORKEYLOW | ||
445 | * Address: 0x1a0 | ||
446 | * SCT: no | ||
447 | */ | ||
448 | #define HW_PXP_OLCOLORKEYLOW (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1a0)) | ||
449 | #define BP_PXP_OLCOLORKEYLOW_RSVD1 24 | ||
450 | #define BM_PXP_OLCOLORKEYLOW_RSVD1 0xff000000 | ||
451 | #define BF_PXP_OLCOLORKEYLOW_RSVD1(v) (((v) << 24) & 0xff000000) | ||
452 | #define BP_PXP_OLCOLORKEYLOW_PIXEL 0 | ||
453 | #define BM_PXP_OLCOLORKEYLOW_PIXEL 0xffffff | ||
454 | #define BF_PXP_OLCOLORKEYLOW_PIXEL(v) (((v) << 0) & 0xffffff) | ||
455 | |||
456 | /** | ||
457 | * Register: HW_PXP_OLCOLORKEYHIGH | ||
458 | * Address: 0x1b0 | ||
459 | * SCT: no | ||
460 | */ | ||
461 | #define HW_PXP_OLCOLORKEYHIGH (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1b0)) | ||
462 | #define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 | ||
463 | #define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xff000000 | ||
464 | #define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) (((v) << 24) & 0xff000000) | ||
465 | #define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 | ||
466 | #define BM_PXP_OLCOLORKEYHIGH_PIXEL 0xffffff | ||
467 | #define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) (((v) << 0) & 0xffffff) | ||
468 | |||
469 | /** | ||
470 | * Register: HW_PXP_DEBUGCTRL | ||
471 | * Address: 0x1d0 | ||
472 | * SCT: no | ||
473 | */ | ||
474 | #define HW_PXP_DEBUGCTRL (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1d0)) | ||
475 | #define BP_PXP_DEBUGCTRL_RSVD 9 | ||
476 | #define BM_PXP_DEBUGCTRL_RSVD 0xfffffe00 | ||
477 | #define BF_PXP_DEBUGCTRL_RSVD(v) (((v) << 9) & 0xfffffe00) | ||
478 | #define BP_PXP_DEBUGCTRL_RESET_TLB_STATS 8 | ||
479 | #define BM_PXP_DEBUGCTRL_RESET_TLB_STATS 0x100 | ||
480 | #define BF_PXP_DEBUGCTRL_RESET_TLB_STATS(v) (((v) << 8) & 0x100) | ||
481 | #define BP_PXP_DEBUGCTRL_SELECT 0 | ||
482 | #define BM_PXP_DEBUGCTRL_SELECT 0xff | ||
483 | #define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 | ||
484 | #define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 | ||
485 | #define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 | ||
486 | #define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 | ||
487 | #define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 | ||
488 | #define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 | ||
489 | #define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 | ||
490 | #define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 | ||
491 | #define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 | ||
492 | #define BF_PXP_DEBUGCTRL_SELECT(v) (((v) << 0) & 0xff) | ||
493 | #define BF_PXP_DEBUGCTRL_SELECT_V(v) ((BV_PXP_DEBUGCTRL_SELECT__##v << 0) & 0xff) | ||
494 | |||
495 | /** | ||
496 | * Register: HW_PXP_DEBUG | ||
497 | * Address: 0x1e0 | ||
498 | * SCT: no | ||
499 | */ | ||
500 | #define HW_PXP_DEBUG (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1e0)) | ||
501 | #define BP_PXP_DEBUG_DATA 0 | ||
502 | #define BM_PXP_DEBUG_DATA 0xffffffff | ||
503 | #define BF_PXP_DEBUG_DATA(v) (((v) << 0) & 0xffffffff) | ||
504 | |||
505 | /** | ||
506 | * Register: HW_PXP_VERSION | ||
507 | * Address: 0x1f0 | ||
508 | * SCT: no | ||
509 | */ | ||
510 | #define HW_PXP_VERSION (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1f0)) | ||
511 | #define BP_PXP_VERSION_MAJOR 24 | ||
512 | #define BM_PXP_VERSION_MAJOR 0xff000000 | ||
513 | #define BF_PXP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
514 | #define BP_PXP_VERSION_MINOR 16 | ||
515 | #define BM_PXP_VERSION_MINOR 0xff0000 | ||
516 | #define BF_PXP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
517 | #define BP_PXP_VERSION_STEP 0 | ||
518 | #define BM_PXP_VERSION_STEP 0xffff | ||
519 | #define BF_PXP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
520 | |||
521 | /** | ||
522 | * Register: HW_PXP_OLn | ||
523 | * Address: 0x200+n*0x40 | ||
524 | * SCT: no | ||
525 | */ | ||
526 | #define HW_PXP_OLn(n) (*(volatile unsigned long *)(REGS_PXP_BASE + 0x200+(n)*0x40)) | ||
527 | #define BP_PXP_OLn_ADDR 0 | ||
528 | #define BM_PXP_OLn_ADDR 0xffffffff | ||
529 | #define BF_PXP_OLn_ADDR(v) (((v) << 0) & 0xffffffff) | ||
530 | |||
531 | /** | ||
532 | * Register: HW_PXP_OLnSIZE | ||
533 | * Address: 0x210+n*0x40 | ||
534 | * SCT: no | ||
535 | */ | ||
536 | #define HW_PXP_OLnSIZE(n) (*(volatile unsigned long *)(REGS_PXP_BASE + 0x210+(n)*0x40)) | ||
537 | #define BP_PXP_OLnSIZE_XBASE 24 | ||
538 | #define BM_PXP_OLnSIZE_XBASE 0xff000000 | ||
539 | #define BF_PXP_OLnSIZE_XBASE(v) (((v) << 24) & 0xff000000) | ||
540 | #define BP_PXP_OLnSIZE_YBASE 16 | ||
541 | #define BM_PXP_OLnSIZE_YBASE 0xff0000 | ||
542 | #define BF_PXP_OLnSIZE_YBASE(v) (((v) << 16) & 0xff0000) | ||
543 | #define BP_PXP_OLnSIZE_WIDTH 8 | ||
544 | #define BM_PXP_OLnSIZE_WIDTH 0xff00 | ||
545 | #define BF_PXP_OLnSIZE_WIDTH(v) (((v) << 8) & 0xff00) | ||
546 | #define BP_PXP_OLnSIZE_HEIGHT 0 | ||
547 | #define BM_PXP_OLnSIZE_HEIGHT 0xff | ||
548 | #define BF_PXP_OLnSIZE_HEIGHT(v) (((v) << 0) & 0xff) | ||
549 | |||
550 | /** | ||
551 | * Register: HW_PXP_OLnPARAM | ||
552 | * Address: 0x220+n*0x40 | ||
553 | * SCT: no | ||
554 | */ | ||
555 | #define HW_PXP_OLnPARAM(n) (*(volatile unsigned long *)(REGS_PXP_BASE + 0x220+(n)*0x40)) | ||
556 | #define BP_PXP_OLnPARAM_RSVD1 20 | ||
557 | #define BM_PXP_OLnPARAM_RSVD1 0xfff00000 | ||
558 | #define BF_PXP_OLnPARAM_RSVD1(v) (((v) << 20) & 0xfff00000) | ||
559 | #define BP_PXP_OLnPARAM_ROP 16 | ||
560 | #define BM_PXP_OLnPARAM_ROP 0xf0000 | ||
561 | #define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 | ||
562 | #define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 | ||
563 | #define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 | ||
564 | #define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 | ||
565 | #define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 | ||
566 | #define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 | ||
567 | #define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 | ||
568 | #define BV_PXP_OLnPARAM_ROP__NOT 0x7 | ||
569 | #define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 | ||
570 | #define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 | ||
571 | #define BV_PXP_OLnPARAM_ROP__XOROL 0xa | ||
572 | #define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xb | ||
573 | #define BF_PXP_OLnPARAM_ROP(v) (((v) << 16) & 0xf0000) | ||
574 | #define BF_PXP_OLnPARAM_ROP_V(v) ((BV_PXP_OLnPARAM_ROP__##v << 16) & 0xf0000) | ||
575 | #define BP_PXP_OLnPARAM_ALPHA 8 | ||
576 | #define BM_PXP_OLnPARAM_ALPHA 0xff00 | ||
577 | #define BF_PXP_OLnPARAM_ALPHA(v) (((v) << 8) & 0xff00) | ||
578 | #define BP_PXP_OLnPARAM_FORMAT 4 | ||
579 | #define BM_PXP_OLnPARAM_FORMAT 0xf0 | ||
580 | #define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 | ||
581 | #define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 | ||
582 | #define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 | ||
583 | #define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 | ||
584 | #define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 | ||
585 | #define BF_PXP_OLnPARAM_FORMAT(v) (((v) << 4) & 0xf0) | ||
586 | #define BF_PXP_OLnPARAM_FORMAT_V(v) ((BV_PXP_OLnPARAM_FORMAT__##v << 4) & 0xf0) | ||
587 | #define BP_PXP_OLnPARAM_ENABLE_COLORKEY 3 | ||
588 | #define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x8 | ||
589 | #define BF_PXP_OLnPARAM_ENABLE_COLORKEY(v) (((v) << 3) & 0x8) | ||
590 | #define BP_PXP_OLnPARAM_ALPHA_CNTL 1 | ||
591 | #define BM_PXP_OLnPARAM_ALPHA_CNTL 0x6 | ||
592 | #define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 | ||
593 | #define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 | ||
594 | #define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 | ||
595 | #define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 | ||
596 | #define BF_PXP_OLnPARAM_ALPHA_CNTL(v) (((v) << 1) & 0x6) | ||
597 | #define BF_PXP_OLnPARAM_ALPHA_CNTL_V(v) ((BV_PXP_OLnPARAM_ALPHA_CNTL__##v << 1) & 0x6) | ||
598 | #define BP_PXP_OLnPARAM_ENABLE 0 | ||
599 | #define BM_PXP_OLnPARAM_ENABLE 0x1 | ||
600 | #define BF_PXP_OLnPARAM_ENABLE(v) (((v) << 0) & 0x1) | ||
601 | |||
602 | /** | ||
603 | * Register: HW_PXP_OLnPARAM2 | ||
604 | * Address: 0x230+n*0x40 | ||
605 | * SCT: no | ||
606 | */ | ||
607 | #define HW_PXP_OLnPARAM2(n) (*(volatile unsigned long *)(REGS_PXP_BASE + 0x230+(n)*0x40)) | ||
608 | #define BP_PXP_OLnPARAM2_RSVD 0 | ||
609 | #define BM_PXP_OLnPARAM2_RSVD 0xffffffff | ||
610 | #define BF_PXP_OLnPARAM2_RSVD(v) (((v) << 0) & 0xffffffff) | ||
611 | |||
612 | #endif /* __HEADERGEN__IMX233__PXP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-rtc.h b/firmware/target/arm/imx233/regs/imx233/regs-rtc.h new file mode 100644 index 0000000000..fbca279a54 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-rtc.h | |||
@@ -0,0 +1,318 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__RTC__H__ | ||
24 | #define __HEADERGEN__IMX233__RTC__H__ | ||
25 | |||
26 | #define REGS_RTC_BASE (0x8005c000) | ||
27 | |||
28 | #define REGS_RTC_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_RTC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_RTC_CTRL (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_RTC_CTRL_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_RTC_CTRL_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_RTC_CTRL_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_RTC_CTRL_SFTRST 31 | ||
40 | #define BM_RTC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_RTC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_RTC_CTRL_CLKGATE 30 | ||
43 | #define BM_RTC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_RTC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_RTC_CTRL_RSVD0 7 | ||
46 | #define BM_RTC_CTRL_RSVD0 0x3fffff80 | ||
47 | #define BF_RTC_CTRL_RSVD0(v) (((v) << 7) & 0x3fffff80) | ||
48 | #define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG 6 | ||
49 | #define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x40 | ||
50 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40) | ||
51 | #define BP_RTC_CTRL_FORCE_UPDATE 5 | ||
52 | #define BM_RTC_CTRL_FORCE_UPDATE 0x20 | ||
53 | #define BF_RTC_CTRL_FORCE_UPDATE(v) (((v) << 5) & 0x20) | ||
54 | #define BP_RTC_CTRL_WATCHDOGEN 4 | ||
55 | #define BM_RTC_CTRL_WATCHDOGEN 0x10 | ||
56 | #define BF_RTC_CTRL_WATCHDOGEN(v) (((v) << 4) & 0x10) | ||
57 | #define BP_RTC_CTRL_ONEMSEC_IRQ 3 | ||
58 | #define BM_RTC_CTRL_ONEMSEC_IRQ 0x8 | ||
59 | #define BF_RTC_CTRL_ONEMSEC_IRQ(v) (((v) << 3) & 0x8) | ||
60 | #define BP_RTC_CTRL_ALARM_IRQ 2 | ||
61 | #define BM_RTC_CTRL_ALARM_IRQ 0x4 | ||
62 | #define BF_RTC_CTRL_ALARM_IRQ(v) (((v) << 2) & 0x4) | ||
63 | #define BP_RTC_CTRL_ONEMSEC_IRQ_EN 1 | ||
64 | #define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x2 | ||
65 | #define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v) (((v) << 1) & 0x2) | ||
66 | #define BP_RTC_CTRL_ALARM_IRQ_EN 0 | ||
67 | #define BM_RTC_CTRL_ALARM_IRQ_EN 0x1 | ||
68 | #define BF_RTC_CTRL_ALARM_IRQ_EN(v) (((v) << 0) & 0x1) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_RTC_STAT | ||
72 | * Address: 0x10 | ||
73 | * SCT: yes | ||
74 | */ | ||
75 | #define HW_RTC_STAT (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x0)) | ||
76 | #define HW_RTC_STAT_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x4)) | ||
77 | #define HW_RTC_STAT_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x8)) | ||
78 | #define HW_RTC_STAT_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0xc)) | ||
79 | #define BP_RTC_STAT_RTC_PRESENT 31 | ||
80 | #define BM_RTC_STAT_RTC_PRESENT 0x80000000 | ||
81 | #define BF_RTC_STAT_RTC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
82 | #define BP_RTC_STAT_ALARM_PRESENT 30 | ||
83 | #define BM_RTC_STAT_ALARM_PRESENT 0x40000000 | ||
84 | #define BF_RTC_STAT_ALARM_PRESENT(v) (((v) << 30) & 0x40000000) | ||
85 | #define BP_RTC_STAT_WATCHDOG_PRESENT 29 | ||
86 | #define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 | ||
87 | #define BF_RTC_STAT_WATCHDOG_PRESENT(v) (((v) << 29) & 0x20000000) | ||
88 | #define BP_RTC_STAT_XTAL32000_PRESENT 28 | ||
89 | #define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 | ||
90 | #define BF_RTC_STAT_XTAL32000_PRESENT(v) (((v) << 28) & 0x10000000) | ||
91 | #define BP_RTC_STAT_XTAL32768_PRESENT 27 | ||
92 | #define BM_RTC_STAT_XTAL32768_PRESENT 0x8000000 | ||
93 | #define BF_RTC_STAT_XTAL32768_PRESENT(v) (((v) << 27) & 0x8000000) | ||
94 | #define BP_RTC_STAT_RSVD1 24 | ||
95 | #define BM_RTC_STAT_RSVD1 0x7000000 | ||
96 | #define BF_RTC_STAT_RSVD1(v) (((v) << 24) & 0x7000000) | ||
97 | #define BP_RTC_STAT_STALE_REGS 16 | ||
98 | #define BM_RTC_STAT_STALE_REGS 0xff0000 | ||
99 | #define BF_RTC_STAT_STALE_REGS(v) (((v) << 16) & 0xff0000) | ||
100 | #define BP_RTC_STAT_NEW_REGS 8 | ||
101 | #define BM_RTC_STAT_NEW_REGS 0xff00 | ||
102 | #define BF_RTC_STAT_NEW_REGS(v) (((v) << 8) & 0xff00) | ||
103 | #define BP_RTC_STAT_RSVD0 0 | ||
104 | #define BM_RTC_STAT_RSVD0 0xff | ||
105 | #define BF_RTC_STAT_RSVD0(v) (((v) << 0) & 0xff) | ||
106 | |||
107 | /** | ||
108 | * Register: HW_RTC_MILLISECONDS | ||
109 | * Address: 0x20 | ||
110 | * SCT: yes | ||
111 | */ | ||
112 | #define HW_RTC_MILLISECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0)) | ||
113 | #define HW_RTC_MILLISECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4)) | ||
114 | #define HW_RTC_MILLISECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8)) | ||
115 | #define HW_RTC_MILLISECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc)) | ||
116 | #define BP_RTC_MILLISECONDS_COUNT 0 | ||
117 | #define BM_RTC_MILLISECONDS_COUNT 0xffffffff | ||
118 | #define BF_RTC_MILLISECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
119 | |||
120 | /** | ||
121 | * Register: HW_RTC_SECONDS | ||
122 | * Address: 0x30 | ||
123 | * SCT: yes | ||
124 | */ | ||
125 | #define HW_RTC_SECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0)) | ||
126 | #define HW_RTC_SECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4)) | ||
127 | #define HW_RTC_SECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8)) | ||
128 | #define HW_RTC_SECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc)) | ||
129 | #define BP_RTC_SECONDS_COUNT 0 | ||
130 | #define BM_RTC_SECONDS_COUNT 0xffffffff | ||
131 | #define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_RTC_ALARM | ||
135 | * Address: 0x40 | ||
136 | * SCT: yes | ||
137 | */ | ||
138 | #define HW_RTC_ALARM (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0)) | ||
139 | #define HW_RTC_ALARM_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4)) | ||
140 | #define HW_RTC_ALARM_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8)) | ||
141 | #define HW_RTC_ALARM_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc)) | ||
142 | #define BP_RTC_ALARM_VALUE 0 | ||
143 | #define BM_RTC_ALARM_VALUE 0xffffffff | ||
144 | #define BF_RTC_ALARM_VALUE(v) (((v) << 0) & 0xffffffff) | ||
145 | |||
146 | /** | ||
147 | * Register: HW_RTC_WATCHDOG | ||
148 | * Address: 0x50 | ||
149 | * SCT: yes | ||
150 | */ | ||
151 | #define HW_RTC_WATCHDOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0)) | ||
152 | #define HW_RTC_WATCHDOG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4)) | ||
153 | #define HW_RTC_WATCHDOG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8)) | ||
154 | #define HW_RTC_WATCHDOG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc)) | ||
155 | #define BP_RTC_WATCHDOG_COUNT 0 | ||
156 | #define BM_RTC_WATCHDOG_COUNT 0xffffffff | ||
157 | #define BF_RTC_WATCHDOG_COUNT(v) (((v) << 0) & 0xffffffff) | ||
158 | |||
159 | /** | ||
160 | * Register: HW_RTC_PERSISTENT0 | ||
161 | * Address: 0x60 | ||
162 | * SCT: yes | ||
163 | */ | ||
164 | #define HW_RTC_PERSISTENT0 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0)) | ||
165 | #define HW_RTC_PERSISTENT0_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4)) | ||
166 | #define HW_RTC_PERSISTENT0_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8)) | ||
167 | #define HW_RTC_PERSISTENT0_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc)) | ||
168 | #define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 | ||
169 | #define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xfffc0000 | ||
170 | #define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) (((v) << 18) & 0xfffc0000) | ||
171 | #define BP_RTC_PERSISTENT0_AUTO_RESTART 17 | ||
172 | #define BM_RTC_PERSISTENT0_AUTO_RESTART 0x20000 | ||
173 | #define BF_RTC_PERSISTENT0_AUTO_RESTART(v) (((v) << 17) & 0x20000) | ||
174 | #define BP_RTC_PERSISTENT0_DISABLE_PSWITCH 16 | ||
175 | #define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x10000 | ||
176 | #define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v) (((v) << 16) & 0x10000) | ||
177 | #define BP_RTC_PERSISTENT0_LOWERBIAS 14 | ||
178 | #define BM_RTC_PERSISTENT0_LOWERBIAS 0xc000 | ||
179 | #define BF_RTC_PERSISTENT0_LOWERBIAS(v) (((v) << 14) & 0xc000) | ||
180 | #define BP_RTC_PERSISTENT0_DISABLE_XTALOK 13 | ||
181 | #define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x2000 | ||
182 | #define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v) (((v) << 13) & 0x2000) | ||
183 | #define BP_RTC_PERSISTENT0_MSEC_RES 8 | ||
184 | #define BM_RTC_PERSISTENT0_MSEC_RES 0x1f00 | ||
185 | #define BF_RTC_PERSISTENT0_MSEC_RES(v) (((v) << 8) & 0x1f00) | ||
186 | #define BP_RTC_PERSISTENT0_ALARM_WAKE 7 | ||
187 | #define BM_RTC_PERSISTENT0_ALARM_WAKE 0x80 | ||
188 | #define BF_RTC_PERSISTENT0_ALARM_WAKE(v) (((v) << 7) & 0x80) | ||
189 | #define BP_RTC_PERSISTENT0_XTAL32_FREQ 6 | ||
190 | #define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x40 | ||
191 | #define BF_RTC_PERSISTENT0_XTAL32_FREQ(v) (((v) << 6) & 0x40) | ||
192 | #define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 5 | ||
193 | #define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x20 | ||
194 | #define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v) (((v) << 5) & 0x20) | ||
195 | #define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 4 | ||
196 | #define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x10 | ||
197 | #define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v) (((v) << 4) & 0x10) | ||
198 | #define BP_RTC_PERSISTENT0_LCK_SECS 3 | ||
199 | #define BM_RTC_PERSISTENT0_LCK_SECS 0x8 | ||
200 | #define BF_RTC_PERSISTENT0_LCK_SECS(v) (((v) << 3) & 0x8) | ||
201 | #define BP_RTC_PERSISTENT0_ALARM_EN 2 | ||
202 | #define BM_RTC_PERSISTENT0_ALARM_EN 0x4 | ||
203 | #define BF_RTC_PERSISTENT0_ALARM_EN(v) (((v) << 2) & 0x4) | ||
204 | #define BP_RTC_PERSISTENT0_ALARM_WAKE_EN 1 | ||
205 | #define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x2 | ||
206 | #define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v) (((v) << 1) & 0x2) | ||
207 | #define BP_RTC_PERSISTENT0_CLOCKSOURCE 0 | ||
208 | #define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x1 | ||
209 | #define BF_RTC_PERSISTENT0_CLOCKSOURCE(v) (((v) << 0) & 0x1) | ||
210 | |||
211 | /** | ||
212 | * Register: HW_RTC_PERSISTENT1 | ||
213 | * Address: 0x70 | ||
214 | * SCT: yes | ||
215 | */ | ||
216 | #define HW_RTC_PERSISTENT1 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0)) | ||
217 | #define HW_RTC_PERSISTENT1_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4)) | ||
218 | #define HW_RTC_PERSISTENT1_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8)) | ||
219 | #define HW_RTC_PERSISTENT1_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc)) | ||
220 | #define BP_RTC_PERSISTENT1_GENERAL 0 | ||
221 | #define BM_RTC_PERSISTENT1_GENERAL 0xffffffff | ||
222 | #define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 | ||
223 | #define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x800 | ||
224 | #define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x400 | ||
225 | #define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x200 | ||
226 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x100 | ||
227 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x80 | ||
228 | #define BF_RTC_PERSISTENT1_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
229 | #define BF_RTC_PERSISTENT1_GENERAL_V(v) ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff) | ||
230 | |||
231 | /** | ||
232 | * Register: HW_RTC_PERSISTENT2 | ||
233 | * Address: 0x80 | ||
234 | * SCT: yes | ||
235 | */ | ||
236 | #define HW_RTC_PERSISTENT2 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0)) | ||
237 | #define HW_RTC_PERSISTENT2_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4)) | ||
238 | #define HW_RTC_PERSISTENT2_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8)) | ||
239 | #define HW_RTC_PERSISTENT2_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc)) | ||
240 | #define BP_RTC_PERSISTENT2_GENERAL 0 | ||
241 | #define BM_RTC_PERSISTENT2_GENERAL 0xffffffff | ||
242 | #define BF_RTC_PERSISTENT2_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
243 | |||
244 | /** | ||
245 | * Register: HW_RTC_PERSISTENT3 | ||
246 | * Address: 0x90 | ||
247 | * SCT: yes | ||
248 | */ | ||
249 | #define HW_RTC_PERSISTENT3 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0)) | ||
250 | #define HW_RTC_PERSISTENT3_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4)) | ||
251 | #define HW_RTC_PERSISTENT3_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8)) | ||
252 | #define HW_RTC_PERSISTENT3_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc)) | ||
253 | #define BP_RTC_PERSISTENT3_GENERAL 0 | ||
254 | #define BM_RTC_PERSISTENT3_GENERAL 0xffffffff | ||
255 | #define BF_RTC_PERSISTENT3_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
256 | |||
257 | /** | ||
258 | * Register: HW_RTC_PERSISTENT4 | ||
259 | * Address: 0xa0 | ||
260 | * SCT: yes | ||
261 | */ | ||
262 | #define HW_RTC_PERSISTENT4 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0)) | ||
263 | #define HW_RTC_PERSISTENT4_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4)) | ||
264 | #define HW_RTC_PERSISTENT4_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8)) | ||
265 | #define HW_RTC_PERSISTENT4_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc)) | ||
266 | #define BP_RTC_PERSISTENT4_GENERAL 0 | ||
267 | #define BM_RTC_PERSISTENT4_GENERAL 0xffffffff | ||
268 | #define BF_RTC_PERSISTENT4_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
269 | |||
270 | /** | ||
271 | * Register: HW_RTC_PERSISTENT5 | ||
272 | * Address: 0xb0 | ||
273 | * SCT: yes | ||
274 | */ | ||
275 | #define HW_RTC_PERSISTENT5 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0)) | ||
276 | #define HW_RTC_PERSISTENT5_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4)) | ||
277 | #define HW_RTC_PERSISTENT5_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8)) | ||
278 | #define HW_RTC_PERSISTENT5_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc)) | ||
279 | #define BP_RTC_PERSISTENT5_GENERAL 0 | ||
280 | #define BM_RTC_PERSISTENT5_GENERAL 0xffffffff | ||
281 | #define BF_RTC_PERSISTENT5_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
282 | |||
283 | /** | ||
284 | * Register: HW_RTC_DEBUG | ||
285 | * Address: 0xc0 | ||
286 | * SCT: yes | ||
287 | */ | ||
288 | #define HW_RTC_DEBUG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0)) | ||
289 | #define HW_RTC_DEBUG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4)) | ||
290 | #define HW_RTC_DEBUG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8)) | ||
291 | #define HW_RTC_DEBUG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc)) | ||
292 | #define BP_RTC_DEBUG_RSVD0 2 | ||
293 | #define BM_RTC_DEBUG_RSVD0 0xfffffffc | ||
294 | #define BF_RTC_DEBUG_RSVD0(v) (((v) << 2) & 0xfffffffc) | ||
295 | #define BP_RTC_DEBUG_WATCHDOG_RESET_MASK 1 | ||
296 | #define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x2 | ||
297 | #define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2) | ||
298 | #define BP_RTC_DEBUG_WATCHDOG_RESET 0 | ||
299 | #define BM_RTC_DEBUG_WATCHDOG_RESET 0x1 | ||
300 | #define BF_RTC_DEBUG_WATCHDOG_RESET(v) (((v) << 0) & 0x1) | ||
301 | |||
302 | /** | ||
303 | * Register: HW_RTC_VERSION | ||
304 | * Address: 0xd0 | ||
305 | * SCT: no | ||
306 | */ | ||
307 | #define HW_RTC_VERSION (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0)) | ||
308 | #define BP_RTC_VERSION_MAJOR 24 | ||
309 | #define BM_RTC_VERSION_MAJOR 0xff000000 | ||
310 | #define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
311 | #define BP_RTC_VERSION_MINOR 16 | ||
312 | #define BM_RTC_VERSION_MINOR 0xff0000 | ||
313 | #define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
314 | #define BP_RTC_VERSION_STEP 0 | ||
315 | #define BM_RTC_VERSION_STEP 0xffff | ||
316 | #define BF_RTC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
317 | |||
318 | #endif /* __HEADERGEN__IMX233__RTC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-saif.h b/firmware/target/arm/imx233/regs/imx233/regs-saif.h new file mode 100644 index 0000000000..21171f4c18 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-saif.h | |||
@@ -0,0 +1,169 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__SAIF__H__ | ||
24 | #define __HEADERGEN__IMX233__SAIF__H__ | ||
25 | |||
26 | #define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000) | ||
27 | |||
28 | #define REGS_SAIF_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SAIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SAIF_CTRL(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0)) | ||
36 | #define HW_SAIF_CTRL_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4)) | ||
37 | #define HW_SAIF_CTRL_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8)) | ||
38 | #define HW_SAIF_CTRL_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc)) | ||
39 | #define BP_SAIF_CTRL_SFTRST 31 | ||
40 | #define BM_SAIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_SAIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SAIF_CTRL_CLKGATE 30 | ||
43 | #define BM_SAIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_SAIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 | ||
46 | #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 | ||
47 | #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) (((v) << 27) & 0x38000000) | ||
48 | #define BP_SAIF_CTRL_BITCLK_BASE_RATE 26 | ||
49 | #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x4000000 | ||
50 | #define BF_SAIF_CTRL_BITCLK_BASE_RATE(v) (((v) << 26) & 0x4000000) | ||
51 | #define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN 25 | ||
52 | #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x2000000 | ||
53 | #define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 25) & 0x2000000) | ||
54 | #define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 24 | ||
55 | #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x1000000 | ||
56 | #define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
57 | #define BP_SAIF_CTRL_RSRVD2 21 | ||
58 | #define BM_SAIF_CTRL_RSRVD2 0xe00000 | ||
59 | #define BF_SAIF_CTRL_RSRVD2(v) (((v) << 21) & 0xe00000) | ||
60 | #define BP_SAIF_CTRL_DMAWAIT_COUNT 16 | ||
61 | #define BM_SAIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
62 | #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
63 | #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 | ||
64 | #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0xc000 | ||
65 | #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) (((v) << 14) & 0xc000) | ||
66 | #define BP_SAIF_CTRL_RSRVD1 13 | ||
67 | #define BM_SAIF_CTRL_RSRVD1 0x2000 | ||
68 | #define BF_SAIF_CTRL_RSRVD1(v) (((v) << 13) & 0x2000) | ||
69 | #define BP_SAIF_CTRL_BIT_ORDER 12 | ||
70 | #define BM_SAIF_CTRL_BIT_ORDER 0x1000 | ||
71 | #define BF_SAIF_CTRL_BIT_ORDER(v) (((v) << 12) & 0x1000) | ||
72 | #define BP_SAIF_CTRL_DELAY 11 | ||
73 | #define BM_SAIF_CTRL_DELAY 0x800 | ||
74 | #define BF_SAIF_CTRL_DELAY(v) (((v) << 11) & 0x800) | ||
75 | #define BP_SAIF_CTRL_JUSTIFY 10 | ||
76 | #define BM_SAIF_CTRL_JUSTIFY 0x400 | ||
77 | #define BF_SAIF_CTRL_JUSTIFY(v) (((v) << 10) & 0x400) | ||
78 | #define BP_SAIF_CTRL_LRCLK_POLARITY 9 | ||
79 | #define BM_SAIF_CTRL_LRCLK_POLARITY 0x200 | ||
80 | #define BF_SAIF_CTRL_LRCLK_POLARITY(v) (((v) << 9) & 0x200) | ||
81 | #define BP_SAIF_CTRL_BITCLK_EDGE 8 | ||
82 | #define BM_SAIF_CTRL_BITCLK_EDGE 0x100 | ||
83 | #define BF_SAIF_CTRL_BITCLK_EDGE(v) (((v) << 8) & 0x100) | ||
84 | #define BP_SAIF_CTRL_WORD_LENGTH 4 | ||
85 | #define BM_SAIF_CTRL_WORD_LENGTH 0xf0 | ||
86 | #define BF_SAIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
87 | #define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE 3 | ||
88 | #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x8 | ||
89 | #define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8) | ||
90 | #define BP_SAIF_CTRL_SLAVE_MODE 2 | ||
91 | #define BM_SAIF_CTRL_SLAVE_MODE 0x4 | ||
92 | #define BF_SAIF_CTRL_SLAVE_MODE(v) (((v) << 2) & 0x4) | ||
93 | #define BP_SAIF_CTRL_READ_MODE 1 | ||
94 | #define BM_SAIF_CTRL_READ_MODE 0x2 | ||
95 | #define BF_SAIF_CTRL_READ_MODE(v) (((v) << 1) & 0x2) | ||
96 | #define BP_SAIF_CTRL_RUN 0 | ||
97 | #define BM_SAIF_CTRL_RUN 0x1 | ||
98 | #define BF_SAIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
99 | |||
100 | /** | ||
101 | * Register: HW_SAIF_STAT | ||
102 | * Address: 0x10 | ||
103 | * SCT: yes | ||
104 | */ | ||
105 | #define HW_SAIF_STAT(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0)) | ||
106 | #define HW_SAIF_STAT_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4)) | ||
107 | #define HW_SAIF_STAT_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8)) | ||
108 | #define HW_SAIF_STAT_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc)) | ||
109 | #define BP_SAIF_STAT_PRESENT 31 | ||
110 | #define BM_SAIF_STAT_PRESENT 0x80000000 | ||
111 | #define BF_SAIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
112 | #define BP_SAIF_STAT_RSRVD2 17 | ||
113 | #define BM_SAIF_STAT_RSRVD2 0x7ffe0000 | ||
114 | #define BF_SAIF_STAT_RSRVD2(v) (((v) << 17) & 0x7ffe0000) | ||
115 | #define BP_SAIF_STAT_DMA_PREQ 16 | ||
116 | #define BM_SAIF_STAT_DMA_PREQ 0x10000 | ||
117 | #define BF_SAIF_STAT_DMA_PREQ(v) (((v) << 16) & 0x10000) | ||
118 | #define BP_SAIF_STAT_RSRVD1 7 | ||
119 | #define BM_SAIF_STAT_RSRVD1 0xff80 | ||
120 | #define BF_SAIF_STAT_RSRVD1(v) (((v) << 7) & 0xff80) | ||
121 | #define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ 6 | ||
122 | #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x40 | ||
123 | #define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v) (((v) << 6) & 0x40) | ||
124 | #define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ 5 | ||
125 | #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x20 | ||
126 | #define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v) (((v) << 5) & 0x20) | ||
127 | #define BP_SAIF_STAT_FIFO_SERVICE_IRQ 4 | ||
128 | #define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x10 | ||
129 | #define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v) (((v) << 4) & 0x10) | ||
130 | #define BP_SAIF_STAT_RSRVD0 1 | ||
131 | #define BM_SAIF_STAT_RSRVD0 0xe | ||
132 | #define BF_SAIF_STAT_RSRVD0(v) (((v) << 1) & 0xe) | ||
133 | #define BP_SAIF_STAT_BUSY 0 | ||
134 | #define BM_SAIF_STAT_BUSY 0x1 | ||
135 | #define BF_SAIF_STAT_BUSY(v) (((v) << 0) & 0x1) | ||
136 | |||
137 | /** | ||
138 | * Register: HW_SAIF_DATA | ||
139 | * Address: 0x20 | ||
140 | * SCT: yes | ||
141 | */ | ||
142 | #define HW_SAIF_DATA(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0)) | ||
143 | #define HW_SAIF_DATA_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4)) | ||
144 | #define HW_SAIF_DATA_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8)) | ||
145 | #define HW_SAIF_DATA_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc)) | ||
146 | #define BP_SAIF_DATA_PCM_RIGHT 16 | ||
147 | #define BM_SAIF_DATA_PCM_RIGHT 0xffff0000 | ||
148 | #define BF_SAIF_DATA_PCM_RIGHT(v) (((v) << 16) & 0xffff0000) | ||
149 | #define BP_SAIF_DATA_PCM_LEFT 0 | ||
150 | #define BM_SAIF_DATA_PCM_LEFT 0xffff | ||
151 | #define BF_SAIF_DATA_PCM_LEFT(v) (((v) << 0) & 0xffff) | ||
152 | |||
153 | /** | ||
154 | * Register: HW_SAIF_VERSION | ||
155 | * Address: 0x30 | ||
156 | * SCT: no | ||
157 | */ | ||
158 | #define HW_SAIF_VERSION(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30)) | ||
159 | #define BP_SAIF_VERSION_MAJOR 24 | ||
160 | #define BM_SAIF_VERSION_MAJOR 0xff000000 | ||
161 | #define BF_SAIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
162 | #define BP_SAIF_VERSION_MINOR 16 | ||
163 | #define BM_SAIF_VERSION_MINOR 0xff0000 | ||
164 | #define BF_SAIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
165 | #define BP_SAIF_VERSION_STEP 0 | ||
166 | #define BM_SAIF_VERSION_STEP 0xffff | ||
167 | #define BF_SAIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
168 | |||
169 | #endif /* __HEADERGEN__IMX233__SAIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-spdif.h b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h new file mode 100644 index 0000000000..168e88bdb0 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h | |||
@@ -0,0 +1,214 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__SPDIF__H__ | ||
24 | #define __HEADERGEN__IMX233__SPDIF__H__ | ||
25 | |||
26 | #define REGS_SPDIF_BASE (0x80054000) | ||
27 | |||
28 | #define REGS_SPDIF_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SPDIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SPDIF_CTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0)) | ||
36 | #define HW_SPDIF_CTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4)) | ||
37 | #define HW_SPDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8)) | ||
38 | #define HW_SPDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc)) | ||
39 | #define BP_SPDIF_CTRL_SFTRST 31 | ||
40 | #define BM_SPDIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_SPDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SPDIF_CTRL_CLKGATE 30 | ||
43 | #define BM_SPDIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_SPDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SPDIF_CTRL_RSRVD1 21 | ||
46 | #define BM_SPDIF_CTRL_RSRVD1 0x3fe00000 | ||
47 | #define BF_SPDIF_CTRL_RSRVD1(v) (((v) << 21) & 0x3fe00000) | ||
48 | #define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 | ||
49 | #define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
50 | #define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
51 | #define BP_SPDIF_CTRL_RSRVD0 6 | ||
52 | #define BM_SPDIF_CTRL_RSRVD0 0xffc0 | ||
53 | #define BF_SPDIF_CTRL_RSRVD0(v) (((v) << 6) & 0xffc0) | ||
54 | #define BP_SPDIF_CTRL_WAIT_END_XFER 5 | ||
55 | #define BM_SPDIF_CTRL_WAIT_END_XFER 0x20 | ||
56 | #define BF_SPDIF_CTRL_WAIT_END_XFER(v) (((v) << 5) & 0x20) | ||
57 | #define BP_SPDIF_CTRL_WORD_LENGTH 4 | ||
58 | #define BM_SPDIF_CTRL_WORD_LENGTH 0x10 | ||
59 | #define BF_SPDIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0x10) | ||
60 | #define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
61 | #define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
62 | #define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
63 | #define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
64 | #define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
65 | #define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
66 | #define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
67 | #define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
68 | #define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
69 | #define BP_SPDIF_CTRL_RUN 0 | ||
70 | #define BM_SPDIF_CTRL_RUN 0x1 | ||
71 | #define BF_SPDIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
72 | |||
73 | /** | ||
74 | * Register: HW_SPDIF_STAT | ||
75 | * Address: 0x10 | ||
76 | * SCT: yes | ||
77 | */ | ||
78 | #define HW_SPDIF_STAT (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x0)) | ||
79 | #define HW_SPDIF_STAT_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x4)) | ||
80 | #define HW_SPDIF_STAT_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x8)) | ||
81 | #define HW_SPDIF_STAT_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0xc)) | ||
82 | #define BP_SPDIF_STAT_PRESENT 31 | ||
83 | #define BM_SPDIF_STAT_PRESENT 0x80000000 | ||
84 | #define BF_SPDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
85 | #define BP_SPDIF_STAT_RSRVD1 1 | ||
86 | #define BM_SPDIF_STAT_RSRVD1 0x7ffffffe | ||
87 | #define BF_SPDIF_STAT_RSRVD1(v) (((v) << 1) & 0x7ffffffe) | ||
88 | #define BP_SPDIF_STAT_END_XFER 0 | ||
89 | #define BM_SPDIF_STAT_END_XFER 0x1 | ||
90 | #define BF_SPDIF_STAT_END_XFER(v) (((v) << 0) & 0x1) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_SPDIF_FRAMECTRL | ||
94 | * Address: 0x20 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_SPDIF_FRAMECTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0)) | ||
98 | #define HW_SPDIF_FRAMECTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4)) | ||
99 | #define HW_SPDIF_FRAMECTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8)) | ||
100 | #define HW_SPDIF_FRAMECTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc)) | ||
101 | #define BP_SPDIF_FRAMECTRL_RSRVD2 18 | ||
102 | #define BM_SPDIF_FRAMECTRL_RSRVD2 0xfffc0000 | ||
103 | #define BF_SPDIF_FRAMECTRL_RSRVD2(v) (((v) << 18) & 0xfffc0000) | ||
104 | #define BP_SPDIF_FRAMECTRL_V_CONFIG 17 | ||
105 | #define BM_SPDIF_FRAMECTRL_V_CONFIG 0x20000 | ||
106 | #define BF_SPDIF_FRAMECTRL_V_CONFIG(v) (((v) << 17) & 0x20000) | ||
107 | #define BP_SPDIF_FRAMECTRL_AUTO_MUTE 16 | ||
108 | #define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x10000 | ||
109 | #define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000) | ||
110 | #define BP_SPDIF_FRAMECTRL_RSRVD1 15 | ||
111 | #define BM_SPDIF_FRAMECTRL_RSRVD1 0x8000 | ||
112 | #define BF_SPDIF_FRAMECTRL_RSRVD1(v) (((v) << 15) & 0x8000) | ||
113 | #define BP_SPDIF_FRAMECTRL_USER_DATA 14 | ||
114 | #define BM_SPDIF_FRAMECTRL_USER_DATA 0x4000 | ||
115 | #define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000) | ||
116 | #define BP_SPDIF_FRAMECTRL_V 13 | ||
117 | #define BM_SPDIF_FRAMECTRL_V 0x2000 | ||
118 | #define BF_SPDIF_FRAMECTRL_V(v) (((v) << 13) & 0x2000) | ||
119 | #define BP_SPDIF_FRAMECTRL_L 12 | ||
120 | #define BM_SPDIF_FRAMECTRL_L 0x1000 | ||
121 | #define BF_SPDIF_FRAMECTRL_L(v) (((v) << 12) & 0x1000) | ||
122 | #define BP_SPDIF_FRAMECTRL_RSRVD0 11 | ||
123 | #define BM_SPDIF_FRAMECTRL_RSRVD0 0x800 | ||
124 | #define BF_SPDIF_FRAMECTRL_RSRVD0(v) (((v) << 11) & 0x800) | ||
125 | #define BP_SPDIF_FRAMECTRL_CC 4 | ||
126 | #define BM_SPDIF_FRAMECTRL_CC 0x7f0 | ||
127 | #define BF_SPDIF_FRAMECTRL_CC(v) (((v) << 4) & 0x7f0) | ||
128 | #define BP_SPDIF_FRAMECTRL_PRE 3 | ||
129 | #define BM_SPDIF_FRAMECTRL_PRE 0x8 | ||
130 | #define BF_SPDIF_FRAMECTRL_PRE(v) (((v) << 3) & 0x8) | ||
131 | #define BP_SPDIF_FRAMECTRL_COPY 2 | ||
132 | #define BM_SPDIF_FRAMECTRL_COPY 0x4 | ||
133 | #define BF_SPDIF_FRAMECTRL_COPY(v) (((v) << 2) & 0x4) | ||
134 | #define BP_SPDIF_FRAMECTRL_AUDIO 1 | ||
135 | #define BM_SPDIF_FRAMECTRL_AUDIO 0x2 | ||
136 | #define BF_SPDIF_FRAMECTRL_AUDIO(v) (((v) << 1) & 0x2) | ||
137 | #define BP_SPDIF_FRAMECTRL_PRO 0 | ||
138 | #define BM_SPDIF_FRAMECTRL_PRO 0x1 | ||
139 | #define BF_SPDIF_FRAMECTRL_PRO(v) (((v) << 0) & 0x1) | ||
140 | |||
141 | /** | ||
142 | * Register: HW_SPDIF_SRR | ||
143 | * Address: 0x30 | ||
144 | * SCT: yes | ||
145 | */ | ||
146 | #define HW_SPDIF_SRR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0)) | ||
147 | #define HW_SPDIF_SRR_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4)) | ||
148 | #define HW_SPDIF_SRR_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8)) | ||
149 | #define HW_SPDIF_SRR_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc)) | ||
150 | #define BP_SPDIF_SRR_RSRVD1 31 | ||
151 | #define BM_SPDIF_SRR_RSRVD1 0x80000000 | ||
152 | #define BF_SPDIF_SRR_RSRVD1(v) (((v) << 31) & 0x80000000) | ||
153 | #define BP_SPDIF_SRR_BASEMULT 28 | ||
154 | #define BM_SPDIF_SRR_BASEMULT 0x70000000 | ||
155 | #define BF_SPDIF_SRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
156 | #define BP_SPDIF_SRR_RSRVD0 20 | ||
157 | #define BM_SPDIF_SRR_RSRVD0 0xff00000 | ||
158 | #define BF_SPDIF_SRR_RSRVD0(v) (((v) << 20) & 0xff00000) | ||
159 | #define BP_SPDIF_SRR_RATE 0 | ||
160 | #define BM_SPDIF_SRR_RATE 0xfffff | ||
161 | #define BF_SPDIF_SRR_RATE(v) (((v) << 0) & 0xfffff) | ||
162 | |||
163 | /** | ||
164 | * Register: HW_SPDIF_DEBUG | ||
165 | * Address: 0x40 | ||
166 | * SCT: yes | ||
167 | */ | ||
168 | #define HW_SPDIF_DEBUG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x0)) | ||
169 | #define HW_SPDIF_DEBUG_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x4)) | ||
170 | #define HW_SPDIF_DEBUG_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x8)) | ||
171 | #define HW_SPDIF_DEBUG_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0xc)) | ||
172 | #define BP_SPDIF_DEBUG_RSRVD1 2 | ||
173 | #define BM_SPDIF_DEBUG_RSRVD1 0xfffffffc | ||
174 | #define BF_SPDIF_DEBUG_RSRVD1(v) (((v) << 2) & 0xfffffffc) | ||
175 | #define BP_SPDIF_DEBUG_DMA_PREQ 1 | ||
176 | #define BM_SPDIF_DEBUG_DMA_PREQ 0x2 | ||
177 | #define BF_SPDIF_DEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
178 | #define BP_SPDIF_DEBUG_FIFO_STATUS 0 | ||
179 | #define BM_SPDIF_DEBUG_FIFO_STATUS 0x1 | ||
180 | #define BF_SPDIF_DEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
181 | |||
182 | /** | ||
183 | * Register: HW_SPDIF_DATA | ||
184 | * Address: 0x50 | ||
185 | * SCT: yes | ||
186 | */ | ||
187 | #define HW_SPDIF_DATA (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0)) | ||
188 | #define HW_SPDIF_DATA_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4)) | ||
189 | #define HW_SPDIF_DATA_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8)) | ||
190 | #define HW_SPDIF_DATA_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc)) | ||
191 | #define BP_SPDIF_DATA_HIGH 16 | ||
192 | #define BM_SPDIF_DATA_HIGH 0xffff0000 | ||
193 | #define BF_SPDIF_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
194 | #define BP_SPDIF_DATA_LOW 0 | ||
195 | #define BM_SPDIF_DATA_LOW 0xffff | ||
196 | #define BF_SPDIF_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
197 | |||
198 | /** | ||
199 | * Register: HW_SPDIF_VERSION | ||
200 | * Address: 0x60 | ||
201 | * SCT: no | ||
202 | */ | ||
203 | #define HW_SPDIF_VERSION (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60)) | ||
204 | #define BP_SPDIF_VERSION_MAJOR 24 | ||
205 | #define BM_SPDIF_VERSION_MAJOR 0xff000000 | ||
206 | #define BF_SPDIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
207 | #define BP_SPDIF_VERSION_MINOR 16 | ||
208 | #define BM_SPDIF_VERSION_MINOR 0xff0000 | ||
209 | #define BF_SPDIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
210 | #define BP_SPDIF_VERSION_STEP 0 | ||
211 | #define BM_SPDIF_VERSION_STEP 0xffff | ||
212 | #define BF_SPDIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
213 | |||
214 | #endif /* __HEADERGEN__IMX233__SPDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ssp.h b/firmware/target/arm/imx233/regs/imx233/regs-ssp.h new file mode 100644 index 0000000000..012b251bcc --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-ssp.h | |||
@@ -0,0 +1,576 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__SSP__H__ | ||
24 | #define __HEADERGEN__IMX233__SSP__H__ | ||
25 | |||
26 | #define REGS_SSP_BASE(i) ((i) == 1 ? 0x80010000 : 0x80034000) | ||
27 | |||
28 | #define REGS_SSP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SSP_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SSP_CTRL0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x0)) | ||
36 | #define HW_SSP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x4)) | ||
37 | #define HW_SSP_CTRL0_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x8)) | ||
38 | #define HW_SSP_CTRL0_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0xc)) | ||
39 | #define BP_SSP_CTRL0_SFTRST 31 | ||
40 | #define BM_SSP_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_SSP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SSP_CTRL0_CLKGATE 30 | ||
43 | #define BM_SSP_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_SSP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SSP_CTRL0_RUN 29 | ||
46 | #define BM_SSP_CTRL0_RUN 0x20000000 | ||
47 | #define BF_SSP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_SSP_CTRL0_SDIO_IRQ_CHECK 28 | ||
49 | #define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 | ||
50 | #define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_SSP_CTRL0_LOCK_CS 27 | ||
52 | #define BM_SSP_CTRL0_LOCK_CS 0x8000000 | ||
53 | #define BF_SSP_CTRL0_LOCK_CS(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_SSP_CTRL0_IGNORE_CRC 26 | ||
55 | #define BM_SSP_CTRL0_IGNORE_CRC 0x4000000 | ||
56 | #define BF_SSP_CTRL0_IGNORE_CRC(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_SSP_CTRL0_READ 25 | ||
58 | #define BM_SSP_CTRL0_READ 0x2000000 | ||
59 | #define BF_SSP_CTRL0_READ(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_SSP_CTRL0_DATA_XFER 24 | ||
61 | #define BM_SSP_CTRL0_DATA_XFER 0x1000000 | ||
62 | #define BF_SSP_CTRL0_DATA_XFER(v) (((v) << 24) & 0x1000000) | ||
63 | #define BP_SSP_CTRL0_BUS_WIDTH 22 | ||
64 | #define BM_SSP_CTRL0_BUS_WIDTH 0xc00000 | ||
65 | #define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 | ||
66 | #define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 | ||
67 | #define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 | ||
68 | #define BF_SSP_CTRL0_BUS_WIDTH(v) (((v) << 22) & 0xc00000) | ||
69 | #define BF_SSP_CTRL0_BUS_WIDTH_V(v) ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0xc00000) | ||
70 | #define BP_SSP_CTRL0_WAIT_FOR_IRQ 21 | ||
71 | #define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x200000 | ||
72 | #define BF_SSP_CTRL0_WAIT_FOR_IRQ(v) (((v) << 21) & 0x200000) | ||
73 | #define BP_SSP_CTRL0_WAIT_FOR_CMD 20 | ||
74 | #define BM_SSP_CTRL0_WAIT_FOR_CMD 0x100000 | ||
75 | #define BF_SSP_CTRL0_WAIT_FOR_CMD(v) (((v) << 20) & 0x100000) | ||
76 | #define BP_SSP_CTRL0_LONG_RESP 19 | ||
77 | #define BM_SSP_CTRL0_LONG_RESP 0x80000 | ||
78 | #define BF_SSP_CTRL0_LONG_RESP(v) (((v) << 19) & 0x80000) | ||
79 | #define BP_SSP_CTRL0_CHECK_RESP 18 | ||
80 | #define BM_SSP_CTRL0_CHECK_RESP 0x40000 | ||
81 | #define BF_SSP_CTRL0_CHECK_RESP(v) (((v) << 18) & 0x40000) | ||
82 | #define BP_SSP_CTRL0_GET_RESP 17 | ||
83 | #define BM_SSP_CTRL0_GET_RESP 0x20000 | ||
84 | #define BF_SSP_CTRL0_GET_RESP(v) (((v) << 17) & 0x20000) | ||
85 | #define BP_SSP_CTRL0_ENABLE 16 | ||
86 | #define BM_SSP_CTRL0_ENABLE 0x10000 | ||
87 | #define BF_SSP_CTRL0_ENABLE(v) (((v) << 16) & 0x10000) | ||
88 | #define BP_SSP_CTRL0_XFER_COUNT 0 | ||
89 | #define BM_SSP_CTRL0_XFER_COUNT 0xffff | ||
90 | #define BF_SSP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_SSP_CMD0 | ||
94 | * Address: 0x10 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_SSP_CMD0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x0)) | ||
98 | #define HW_SSP_CMD0_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x4)) | ||
99 | #define HW_SSP_CMD0_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x8)) | ||
100 | #define HW_SSP_CMD0_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0xc)) | ||
101 | #define BP_SSP_CMD0_RSVD0 23 | ||
102 | #define BM_SSP_CMD0_RSVD0 0xff800000 | ||
103 | #define BF_SSP_CMD0_RSVD0(v) (((v) << 23) & 0xff800000) | ||
104 | #define BP_SSP_CMD0_SLOW_CLKING_EN 22 | ||
105 | #define BM_SSP_CMD0_SLOW_CLKING_EN 0x400000 | ||
106 | #define BF_SSP_CMD0_SLOW_CLKING_EN(v) (((v) << 22) & 0x400000) | ||
107 | #define BP_SSP_CMD0_CONT_CLKING_EN 21 | ||
108 | #define BM_SSP_CMD0_CONT_CLKING_EN 0x200000 | ||
109 | #define BF_SSP_CMD0_CONT_CLKING_EN(v) (((v) << 21) & 0x200000) | ||
110 | #define BP_SSP_CMD0_APPEND_8CYC 20 | ||
111 | #define BM_SSP_CMD0_APPEND_8CYC 0x100000 | ||
112 | #define BF_SSP_CMD0_APPEND_8CYC(v) (((v) << 20) & 0x100000) | ||
113 | #define BP_SSP_CMD0_BLOCK_SIZE 16 | ||
114 | #define BM_SSP_CMD0_BLOCK_SIZE 0xf0000 | ||
115 | #define BF_SSP_CMD0_BLOCK_SIZE(v) (((v) << 16) & 0xf0000) | ||
116 | #define BP_SSP_CMD0_BLOCK_COUNT 8 | ||
117 | #define BM_SSP_CMD0_BLOCK_COUNT 0xff00 | ||
118 | #define BF_SSP_CMD0_BLOCK_COUNT(v) (((v) << 8) & 0xff00) | ||
119 | #define BP_SSP_CMD0_CMD 0 | ||
120 | #define BM_SSP_CMD0_CMD 0xff | ||
121 | #define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x0 | ||
122 | #define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x1 | ||
123 | #define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x2 | ||
124 | #define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x3 | ||
125 | #define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x4 | ||
126 | #define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x5 | ||
127 | #define BV_SSP_CMD0_CMD__MMC_SWITCH 0x6 | ||
128 | #define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x7 | ||
129 | #define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x8 | ||
130 | #define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x9 | ||
131 | #define BV_SSP_CMD0_CMD__MMC_SEND_CID 0xa | ||
132 | #define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0xb | ||
133 | #define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0xc | ||
134 | #define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0xd | ||
135 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0xe | ||
136 | #define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0xf | ||
137 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 | ||
138 | #define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 | ||
139 | #define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 | ||
140 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 | ||
141 | #define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 | ||
142 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 | ||
143 | #define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 | ||
144 | #define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 | ||
145 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1a | ||
146 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1b | ||
147 | #define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1c | ||
148 | #define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1d | ||
149 | #define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1e | ||
150 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 | ||
151 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 | ||
152 | #define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 | ||
153 | #define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 | ||
154 | #define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 | ||
155 | #define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2a | ||
156 | #define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 | ||
157 | #define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 | ||
158 | #define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x0 | ||
159 | #define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x2 | ||
160 | #define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x3 | ||
161 | #define BV_SSP_CMD0_CMD__SD_SET_DSR 0x4 | ||
162 | #define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x5 | ||
163 | #define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x7 | ||
164 | #define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x9 | ||
165 | #define BV_SSP_CMD0_CMD__SD_SEND_CID 0xa | ||
166 | #define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0xc | ||
167 | #define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0xd | ||
168 | #define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0xf | ||
169 | #define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 | ||
170 | #define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 | ||
171 | #define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 | ||
172 | #define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 | ||
173 | #define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 | ||
174 | #define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1b | ||
175 | #define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1c | ||
176 | #define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1d | ||
177 | #define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1e | ||
178 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 | ||
179 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 | ||
180 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 | ||
181 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 | ||
182 | #define BV_SSP_CMD0_CMD__SD_ERASE 0x26 | ||
183 | #define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2a | ||
184 | #define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 | ||
185 | #define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 | ||
186 | #define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 | ||
187 | #define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 | ||
188 | #define BF_SSP_CMD0_CMD(v) (((v) << 0) & 0xff) | ||
189 | #define BF_SSP_CMD0_CMD_V(v) ((BV_SSP_CMD0_CMD__##v << 0) & 0xff) | ||
190 | |||
191 | /** | ||
192 | * Register: HW_SSP_CMD1 | ||
193 | * Address: 0x20 | ||
194 | * SCT: no | ||
195 | */ | ||
196 | #define HW_SSP_CMD1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x20)) | ||
197 | #define BP_SSP_CMD1_CMD_ARG 0 | ||
198 | #define BM_SSP_CMD1_CMD_ARG 0xffffffff | ||
199 | #define BF_SSP_CMD1_CMD_ARG(v) (((v) << 0) & 0xffffffff) | ||
200 | |||
201 | /** | ||
202 | * Register: HW_SSP_COMPREF | ||
203 | * Address: 0x30 | ||
204 | * SCT: no | ||
205 | */ | ||
206 | #define HW_SSP_COMPREF(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x30)) | ||
207 | #define BP_SSP_COMPREF_REFERENCE 0 | ||
208 | #define BM_SSP_COMPREF_REFERENCE 0xffffffff | ||
209 | #define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff) | ||
210 | |||
211 | /** | ||
212 | * Register: HW_SSP_COMPMASK | ||
213 | * Address: 0x40 | ||
214 | * SCT: no | ||
215 | */ | ||
216 | #define HW_SSP_COMPMASK(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x40)) | ||
217 | #define BP_SSP_COMPMASK_MASK 0 | ||
218 | #define BM_SSP_COMPMASK_MASK 0xffffffff | ||
219 | #define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff) | ||
220 | |||
221 | /** | ||
222 | * Register: HW_SSP_TIMING | ||
223 | * Address: 0x50 | ||
224 | * SCT: no | ||
225 | */ | ||
226 | #define HW_SSP_TIMING(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x50)) | ||
227 | #define BP_SSP_TIMING_TIMEOUT 16 | ||
228 | #define BM_SSP_TIMING_TIMEOUT 0xffff0000 | ||
229 | #define BF_SSP_TIMING_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
230 | #define BP_SSP_TIMING_CLOCK_DIVIDE 8 | ||
231 | #define BM_SSP_TIMING_CLOCK_DIVIDE 0xff00 | ||
232 | #define BF_SSP_TIMING_CLOCK_DIVIDE(v) (((v) << 8) & 0xff00) | ||
233 | #define BP_SSP_TIMING_CLOCK_RATE 0 | ||
234 | #define BM_SSP_TIMING_CLOCK_RATE 0xff | ||
235 | #define BF_SSP_TIMING_CLOCK_RATE(v) (((v) << 0) & 0xff) | ||
236 | |||
237 | /** | ||
238 | * Register: HW_SSP_CTRL1 | ||
239 | * Address: 0x60 | ||
240 | * SCT: yes | ||
241 | */ | ||
242 | #define HW_SSP_CTRL1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x0)) | ||
243 | #define HW_SSP_CTRL1_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x4)) | ||
244 | #define HW_SSP_CTRL1_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x8)) | ||
245 | #define HW_SSP_CTRL1_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0xc)) | ||
246 | #define BP_SSP_CTRL1_SDIO_IRQ 31 | ||
247 | #define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 | ||
248 | #define BF_SSP_CTRL1_SDIO_IRQ(v) (((v) << 31) & 0x80000000) | ||
249 | #define BP_SSP_CTRL1_SDIO_IRQ_EN 30 | ||
250 | #define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 | ||
251 | #define BF_SSP_CTRL1_SDIO_IRQ_EN(v) (((v) << 30) & 0x40000000) | ||
252 | #define BP_SSP_CTRL1_RESP_ERR_IRQ 29 | ||
253 | #define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 | ||
254 | #define BF_SSP_CTRL1_RESP_ERR_IRQ(v) (((v) << 29) & 0x20000000) | ||
255 | #define BP_SSP_CTRL1_RESP_ERR_IRQ_EN 28 | ||
256 | #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 | ||
257 | #define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
258 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ 27 | ||
259 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x8000000 | ||
260 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v) (((v) << 27) & 0x8000000) | ||
261 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 26 | ||
262 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x4000000 | ||
263 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v) (((v) << 26) & 0x4000000) | ||
264 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ 25 | ||
265 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x2000000 | ||
266 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v) (((v) << 25) & 0x2000000) | ||
267 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 24 | ||
268 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x1000000 | ||
269 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
270 | #define BP_SSP_CTRL1_DATA_CRC_IRQ 23 | ||
271 | #define BM_SSP_CTRL1_DATA_CRC_IRQ 0x800000 | ||
272 | #define BF_SSP_CTRL1_DATA_CRC_IRQ(v) (((v) << 23) & 0x800000) | ||
273 | #define BP_SSP_CTRL1_DATA_CRC_IRQ_EN 22 | ||
274 | #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x400000 | ||
275 | #define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
276 | #define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ 21 | ||
277 | #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x200000 | ||
278 | #define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v) (((v) << 21) & 0x200000) | ||
279 | #define BP_SSP_CTRL1_FIFO_UNDERRUN_EN 20 | ||
280 | #define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x100000 | ||
281 | #define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v) (((v) << 20) & 0x100000) | ||
282 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ 19 | ||
283 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x80000 | ||
284 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v) (((v) << 19) & 0x80000) | ||
285 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 18 | ||
286 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x40000 | ||
287 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
288 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ 17 | ||
289 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x20000 | ||
290 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v) (((v) << 17) & 0x20000) | ||
291 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 16 | ||
292 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x10000 | ||
293 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
294 | #define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ 15 | ||
295 | #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x8000 | ||
296 | #define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v) (((v) << 15) & 0x8000) | ||
297 | #define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 14 | ||
298 | #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x4000 | ||
299 | #define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
300 | #define BP_SSP_CTRL1_DMA_ENABLE 13 | ||
301 | #define BM_SSP_CTRL1_DMA_ENABLE 0x2000 | ||
302 | #define BF_SSP_CTRL1_DMA_ENABLE(v) (((v) << 13) & 0x2000) | ||
303 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_EN 12 | ||
304 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x1000 | ||
305 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v) (((v) << 12) & 0x1000) | ||
306 | #define BP_SSP_CTRL1_SLAVE_OUT_DISABLE 11 | ||
307 | #define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x800 | ||
308 | #define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v) (((v) << 11) & 0x800) | ||
309 | #define BP_SSP_CTRL1_PHASE 10 | ||
310 | #define BM_SSP_CTRL1_PHASE 0x400 | ||
311 | #define BF_SSP_CTRL1_PHASE(v) (((v) << 10) & 0x400) | ||
312 | #define BP_SSP_CTRL1_POLARITY 9 | ||
313 | #define BM_SSP_CTRL1_POLARITY 0x200 | ||
314 | #define BF_SSP_CTRL1_POLARITY(v) (((v) << 9) & 0x200) | ||
315 | #define BP_SSP_CTRL1_SLAVE_MODE 8 | ||
316 | #define BM_SSP_CTRL1_SLAVE_MODE 0x100 | ||
317 | #define BF_SSP_CTRL1_SLAVE_MODE(v) (((v) << 8) & 0x100) | ||
318 | #define BP_SSP_CTRL1_WORD_LENGTH 4 | ||
319 | #define BM_SSP_CTRL1_WORD_LENGTH 0xf0 | ||
320 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 | ||
321 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 | ||
322 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 | ||
323 | #define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 | ||
324 | #define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 | ||
325 | #define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xf | ||
326 | #define BF_SSP_CTRL1_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
327 | #define BF_SSP_CTRL1_WORD_LENGTH_V(v) ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0) | ||
328 | #define BP_SSP_CTRL1_SSP_MODE 0 | ||
329 | #define BM_SSP_CTRL1_SSP_MODE 0xf | ||
330 | #define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 | ||
331 | #define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 | ||
332 | #define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 | ||
333 | #define BV_SSP_CTRL1_SSP_MODE__MS 0x4 | ||
334 | #define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7 | ||
335 | #define BF_SSP_CTRL1_SSP_MODE(v) (((v) << 0) & 0xf) | ||
336 | #define BF_SSP_CTRL1_SSP_MODE_V(v) ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf) | ||
337 | |||
338 | /** | ||
339 | * Register: HW_SSP_DATA | ||
340 | * Address: 0x70 | ||
341 | * SCT: no | ||
342 | */ | ||
343 | #define HW_SSP_DATA(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x70)) | ||
344 | #define BP_SSP_DATA_DATA 0 | ||
345 | #define BM_SSP_DATA_DATA 0xffffffff | ||
346 | #define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
347 | |||
348 | /** | ||
349 | * Register: HW_SSP_SDRESP0 | ||
350 | * Address: 0x80 | ||
351 | * SCT: no | ||
352 | */ | ||
353 | #define HW_SSP_SDRESP0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x80)) | ||
354 | #define BP_SSP_SDRESP0_RESP0 0 | ||
355 | #define BM_SSP_SDRESP0_RESP0 0xffffffff | ||
356 | #define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff) | ||
357 | |||
358 | /** | ||
359 | * Register: HW_SSP_SDRESP1 | ||
360 | * Address: 0x90 | ||
361 | * SCT: no | ||
362 | */ | ||
363 | #define HW_SSP_SDRESP1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x90)) | ||
364 | #define BP_SSP_SDRESP1_RESP1 0 | ||
365 | #define BM_SSP_SDRESP1_RESP1 0xffffffff | ||
366 | #define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff) | ||
367 | |||
368 | /** | ||
369 | * Register: HW_SSP_SDRESP2 | ||
370 | * Address: 0xa0 | ||
371 | * SCT: no | ||
372 | */ | ||
373 | #define HW_SSP_SDRESP2(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xa0)) | ||
374 | #define BP_SSP_SDRESP2_RESP2 0 | ||
375 | #define BM_SSP_SDRESP2_RESP2 0xffffffff | ||
376 | #define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff) | ||
377 | |||
378 | /** | ||
379 | * Register: HW_SSP_SDRESP3 | ||
380 | * Address: 0xb0 | ||
381 | * SCT: no | ||
382 | */ | ||
383 | #define HW_SSP_SDRESP3(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xb0)) | ||
384 | #define BP_SSP_SDRESP3_RESP3 0 | ||
385 | #define BM_SSP_SDRESP3_RESP3 0xffffffff | ||
386 | #define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff) | ||
387 | |||
388 | /** | ||
389 | * Register: HW_SSP_STATUS | ||
390 | * Address: 0xc0 | ||
391 | * SCT: no | ||
392 | */ | ||
393 | #define HW_SSP_STATUS(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xc0)) | ||
394 | #define BP_SSP_STATUS_PRESENT 31 | ||
395 | #define BM_SSP_STATUS_PRESENT 0x80000000 | ||
396 | #define BF_SSP_STATUS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
397 | #define BP_SSP_STATUS_MS_PRESENT 30 | ||
398 | #define BM_SSP_STATUS_MS_PRESENT 0x40000000 | ||
399 | #define BF_SSP_STATUS_MS_PRESENT(v) (((v) << 30) & 0x40000000) | ||
400 | #define BP_SSP_STATUS_SD_PRESENT 29 | ||
401 | #define BM_SSP_STATUS_SD_PRESENT 0x20000000 | ||
402 | #define BF_SSP_STATUS_SD_PRESENT(v) (((v) << 29) & 0x20000000) | ||
403 | #define BP_SSP_STATUS_CARD_DETECT 28 | ||
404 | #define BM_SSP_STATUS_CARD_DETECT 0x10000000 | ||
405 | #define BF_SSP_STATUS_CARD_DETECT(v) (((v) << 28) & 0x10000000) | ||
406 | #define BP_SSP_STATUS_RSVD3 22 | ||
407 | #define BM_SSP_STATUS_RSVD3 0xfc00000 | ||
408 | #define BF_SSP_STATUS_RSVD3(v) (((v) << 22) & 0xfc00000) | ||
409 | #define BP_SSP_STATUS_DMASENSE 21 | ||
410 | #define BM_SSP_STATUS_DMASENSE 0x200000 | ||
411 | #define BF_SSP_STATUS_DMASENSE(v) (((v) << 21) & 0x200000) | ||
412 | #define BP_SSP_STATUS_DMATERM 20 | ||
413 | #define BM_SSP_STATUS_DMATERM 0x100000 | ||
414 | #define BF_SSP_STATUS_DMATERM(v) (((v) << 20) & 0x100000) | ||
415 | #define BP_SSP_STATUS_DMAREQ 19 | ||
416 | #define BM_SSP_STATUS_DMAREQ 0x80000 | ||
417 | #define BF_SSP_STATUS_DMAREQ(v) (((v) << 19) & 0x80000) | ||
418 | #define BP_SSP_STATUS_DMAEND 18 | ||
419 | #define BM_SSP_STATUS_DMAEND 0x40000 | ||
420 | #define BF_SSP_STATUS_DMAEND(v) (((v) << 18) & 0x40000) | ||
421 | #define BP_SSP_STATUS_SDIO_IRQ 17 | ||
422 | #define BM_SSP_STATUS_SDIO_IRQ 0x20000 | ||
423 | #define BF_SSP_STATUS_SDIO_IRQ(v) (((v) << 17) & 0x20000) | ||
424 | #define BP_SSP_STATUS_RESP_CRC_ERR 16 | ||
425 | #define BM_SSP_STATUS_RESP_CRC_ERR 0x10000 | ||
426 | #define BF_SSP_STATUS_RESP_CRC_ERR(v) (((v) << 16) & 0x10000) | ||
427 | #define BP_SSP_STATUS_RESP_ERR 15 | ||
428 | #define BM_SSP_STATUS_RESP_ERR 0x8000 | ||
429 | #define BF_SSP_STATUS_RESP_ERR(v) (((v) << 15) & 0x8000) | ||
430 | #define BP_SSP_STATUS_RESP_TIMEOUT 14 | ||
431 | #define BM_SSP_STATUS_RESP_TIMEOUT 0x4000 | ||
432 | #define BF_SSP_STATUS_RESP_TIMEOUT(v) (((v) << 14) & 0x4000) | ||
433 | #define BP_SSP_STATUS_DATA_CRC_ERR 13 | ||
434 | #define BM_SSP_STATUS_DATA_CRC_ERR 0x2000 | ||
435 | #define BF_SSP_STATUS_DATA_CRC_ERR(v) (((v) << 13) & 0x2000) | ||
436 | #define BP_SSP_STATUS_TIMEOUT 12 | ||
437 | #define BM_SSP_STATUS_TIMEOUT 0x1000 | ||
438 | #define BF_SSP_STATUS_TIMEOUT(v) (((v) << 12) & 0x1000) | ||
439 | #define BP_SSP_STATUS_RECV_TIMEOUT_STAT 11 | ||
440 | #define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x800 | ||
441 | #define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v) (((v) << 11) & 0x800) | ||
442 | #define BP_SSP_STATUS_CEATA_CCS_ERR 10 | ||
443 | #define BM_SSP_STATUS_CEATA_CCS_ERR 0x400 | ||
444 | #define BF_SSP_STATUS_CEATA_CCS_ERR(v) (((v) << 10) & 0x400) | ||
445 | #define BP_SSP_STATUS_FIFO_OVRFLW 9 | ||
446 | #define BM_SSP_STATUS_FIFO_OVRFLW 0x200 | ||
447 | #define BF_SSP_STATUS_FIFO_OVRFLW(v) (((v) << 9) & 0x200) | ||
448 | #define BP_SSP_STATUS_FIFO_FULL 8 | ||
449 | #define BM_SSP_STATUS_FIFO_FULL 0x100 | ||
450 | #define BF_SSP_STATUS_FIFO_FULL(v) (((v) << 8) & 0x100) | ||
451 | #define BP_SSP_STATUS_RSVD1 6 | ||
452 | #define BM_SSP_STATUS_RSVD1 0xc0 | ||
453 | #define BF_SSP_STATUS_RSVD1(v) (((v) << 6) & 0xc0) | ||
454 | #define BP_SSP_STATUS_FIFO_EMPTY 5 | ||
455 | #define BM_SSP_STATUS_FIFO_EMPTY 0x20 | ||
456 | #define BF_SSP_STATUS_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
457 | #define BP_SSP_STATUS_FIFO_UNDRFLW 4 | ||
458 | #define BM_SSP_STATUS_FIFO_UNDRFLW 0x10 | ||
459 | #define BF_SSP_STATUS_FIFO_UNDRFLW(v) (((v) << 4) & 0x10) | ||
460 | #define BP_SSP_STATUS_CMD_BUSY 3 | ||
461 | #define BM_SSP_STATUS_CMD_BUSY 0x8 | ||
462 | #define BF_SSP_STATUS_CMD_BUSY(v) (((v) << 3) & 0x8) | ||
463 | #define BP_SSP_STATUS_DATA_BUSY 2 | ||
464 | #define BM_SSP_STATUS_DATA_BUSY 0x4 | ||
465 | #define BF_SSP_STATUS_DATA_BUSY(v) (((v) << 2) & 0x4) | ||
466 | #define BP_SSP_STATUS_RSVD0 1 | ||
467 | #define BM_SSP_STATUS_RSVD0 0x2 | ||
468 | #define BF_SSP_STATUS_RSVD0(v) (((v) << 1) & 0x2) | ||
469 | #define BP_SSP_STATUS_BUSY 0 | ||
470 | #define BM_SSP_STATUS_BUSY 0x1 | ||
471 | #define BF_SSP_STATUS_BUSY(v) (((v) << 0) & 0x1) | ||
472 | |||
473 | /** | ||
474 | * Register: HW_SSP_DEBUG | ||
475 | * Address: 0x100 | ||
476 | * SCT: no | ||
477 | */ | ||
478 | #define HW_SSP_DEBUG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x100)) | ||
479 | #define BP_SSP_DEBUG_DATACRC_ERR 28 | ||
480 | #define BM_SSP_DEBUG_DATACRC_ERR 0xf0000000 | ||
481 | #define BF_SSP_DEBUG_DATACRC_ERR(v) (((v) << 28) & 0xf0000000) | ||
482 | #define BP_SSP_DEBUG_DATA_STALL 27 | ||
483 | #define BM_SSP_DEBUG_DATA_STALL 0x8000000 | ||
484 | #define BF_SSP_DEBUG_DATA_STALL(v) (((v) << 27) & 0x8000000) | ||
485 | #define BP_SSP_DEBUG_DAT_SM 24 | ||
486 | #define BM_SSP_DEBUG_DAT_SM 0x7000000 | ||
487 | #define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 | ||
488 | #define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 | ||
489 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 | ||
490 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 | ||
491 | #define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 | ||
492 | #define BF_SSP_DEBUG_DAT_SM(v) (((v) << 24) & 0x7000000) | ||
493 | #define BF_SSP_DEBUG_DAT_SM_V(v) ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000) | ||
494 | #define BP_SSP_DEBUG_MSTK_SM 20 | ||
495 | #define BM_SSP_DEBUG_MSTK_SM 0xf00000 | ||
496 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 | ||
497 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 | ||
498 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 | ||
499 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 | ||
500 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 | ||
501 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 | ||
502 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 | ||
503 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 | ||
504 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 | ||
505 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 | ||
506 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xa | ||
507 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xb | ||
508 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xc | ||
509 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xd | ||
510 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xe | ||
511 | #define BF_SSP_DEBUG_MSTK_SM(v) (((v) << 20) & 0xf00000) | ||
512 | #define BF_SSP_DEBUG_MSTK_SM_V(v) ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000) | ||
513 | #define BP_SSP_DEBUG_CMD_OE 19 | ||
514 | #define BM_SSP_DEBUG_CMD_OE 0x80000 | ||
515 | #define BF_SSP_DEBUG_CMD_OE(v) (((v) << 19) & 0x80000) | ||
516 | #define BP_SSP_DEBUG_DMA_SM 16 | ||
517 | #define BM_SSP_DEBUG_DMA_SM 0x70000 | ||
518 | #define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 | ||
519 | #define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 | ||
520 | #define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 | ||
521 | #define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 | ||
522 | #define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 | ||
523 | #define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 | ||
524 | #define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 | ||
525 | #define BF_SSP_DEBUG_DMA_SM(v) (((v) << 16) & 0x70000) | ||
526 | #define BF_SSP_DEBUG_DMA_SM_V(v) ((BV_SSP_DEBUG_DMA_SM__##v << 16) & 0x70000) | ||
527 | #define BP_SSP_DEBUG_MMC_SM 12 | ||
528 | #define BM_SSP_DEBUG_MMC_SM 0xf000 | ||
529 | #define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 | ||
530 | #define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 | ||
531 | #define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 | ||
532 | #define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 | ||
533 | #define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 | ||
534 | #define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 | ||
535 | #define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 | ||
536 | #define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 | ||
537 | #define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 | ||
538 | #define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 | ||
539 | #define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xa | ||
540 | #define BF_SSP_DEBUG_MMC_SM(v) (((v) << 12) & 0xf000) | ||
541 | #define BF_SSP_DEBUG_MMC_SM_V(v) ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0xf000) | ||
542 | #define BP_SSP_DEBUG_CMD_SM 10 | ||
543 | #define BM_SSP_DEBUG_CMD_SM 0xc00 | ||
544 | #define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 | ||
545 | #define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 | ||
546 | #define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 | ||
547 | #define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 | ||
548 | #define BF_SSP_DEBUG_CMD_SM(v) (((v) << 10) & 0xc00) | ||
549 | #define BF_SSP_DEBUG_CMD_SM_V(v) ((BV_SSP_DEBUG_CMD_SM__##v << 10) & 0xc00) | ||
550 | #define BP_SSP_DEBUG_SSP_CMD 9 | ||
551 | #define BM_SSP_DEBUG_SSP_CMD 0x200 | ||
552 | #define BF_SSP_DEBUG_SSP_CMD(v) (((v) << 9) & 0x200) | ||
553 | #define BP_SSP_DEBUG_SSP_RESP 8 | ||
554 | #define BM_SSP_DEBUG_SSP_RESP 0x100 | ||
555 | #define BF_SSP_DEBUG_SSP_RESP(v) (((v) << 8) & 0x100) | ||
556 | #define BP_SSP_DEBUG_SSP_RXD 0 | ||
557 | #define BM_SSP_DEBUG_SSP_RXD 0xff | ||
558 | #define BF_SSP_DEBUG_SSP_RXD(v) (((v) << 0) & 0xff) | ||
559 | |||
560 | /** | ||
561 | * Register: HW_SSP_VERSION | ||
562 | * Address: 0x110 | ||
563 | * SCT: no | ||
564 | */ | ||
565 | #define HW_SSP_VERSION(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x110)) | ||
566 | #define BP_SSP_VERSION_MAJOR 24 | ||
567 | #define BM_SSP_VERSION_MAJOR 0xff000000 | ||
568 | #define BF_SSP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
569 | #define BP_SSP_VERSION_MINOR 16 | ||
570 | #define BM_SSP_VERSION_MINOR 0xff0000 | ||
571 | #define BF_SSP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
572 | #define BP_SSP_VERSION_STEP 0 | ||
573 | #define BM_SSP_VERSION_STEP 0xffff | ||
574 | #define BF_SSP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
575 | |||
576 | #endif /* __HEADERGEN__IMX233__SSP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-sydma.h b/firmware/target/arm/imx233/regs/imx233/regs-sydma.h new file mode 100644 index 0000000000..ec0a4bc959 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-sydma.h | |||
@@ -0,0 +1,194 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__SYDMA__H__ | ||
24 | #define __HEADERGEN__IMX233__SYDMA__H__ | ||
25 | |||
26 | #define REGS_SYDMA_BASE (0x80026000) | ||
27 | |||
28 | #define REGS_SYDMA_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SYDMA_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SYDMA_CTRL (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x0)) | ||
36 | #define HW_SYDMA_CTRL_SET (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x4)) | ||
37 | #define HW_SYDMA_CTRL_CLR (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x8)) | ||
38 | #define HW_SYDMA_CTRL_TOG (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0xc)) | ||
39 | #define BP_SYDMA_CTRL_SFTRST 31 | ||
40 | #define BM_SYDMA_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_SYDMA_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_SYDMA_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_SYDMA_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_SYDMA_CTRL_SFTRST_V(v) ((BV_SYDMA_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_SYDMA_CTRL_CLKGATE 30 | ||
46 | #define BM_SYDMA_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_SYDMA_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_SYDMA_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_SYDMA_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_SYDMA_CTRL_CLKGATE_V(v) ((BV_SYDMA_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_SYDMA_CTRL_RSVD1 10 | ||
52 | #define BM_SYDMA_CTRL_RSVD1 0x3ffffc00 | ||
53 | #define BF_SYDMA_CTRL_RSVD1(v) (((v) << 10) & 0x3ffffc00) | ||
54 | #define BP_SYDMA_CTRL_COMPLETE_IRQ_EN 9 | ||
55 | #define BM_SYDMA_CTRL_COMPLETE_IRQ_EN 0x200 | ||
56 | #define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0 | ||
57 | #define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED 0x1 | ||
58 | #define BF_SYDMA_CTRL_COMPLETE_IRQ_EN(v) (((v) << 9) & 0x200) | ||
59 | #define BF_SYDMA_CTRL_COMPLETE_IRQ_EN_V(v) ((BV_SYDMA_CTRL_COMPLETE_IRQ_EN__##v << 9) & 0x200) | ||
60 | #define BP_SYDMA_CTRL_RSVD0 3 | ||
61 | #define BM_SYDMA_CTRL_RSVD0 0x1f8 | ||
62 | #define BF_SYDMA_CTRL_RSVD0(v) (((v) << 3) & 0x1f8) | ||
63 | #define BP_SYDMA_CTRL_ERROR_IRQ 2 | ||
64 | #define BM_SYDMA_CTRL_ERROR_IRQ 0x4 | ||
65 | #define BF_SYDMA_CTRL_ERROR_IRQ(v) (((v) << 2) & 0x4) | ||
66 | #define BP_SYDMA_CTRL_COMPLETE_IRQ 1 | ||
67 | #define BM_SYDMA_CTRL_COMPLETE_IRQ 0x2 | ||
68 | #define BF_SYDMA_CTRL_COMPLETE_IRQ(v) (((v) << 1) & 0x2) | ||
69 | #define BP_SYDMA_CTRL_RUN 0 | ||
70 | #define BM_SYDMA_CTRL_RUN 0x1 | ||
71 | #define BV_SYDMA_CTRL_RUN__HALT 0x0 | ||
72 | #define BV_SYDMA_CTRL_RUN__RUN 0x1 | ||
73 | #define BF_SYDMA_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
74 | #define BF_SYDMA_CTRL_RUN_V(v) ((BV_SYDMA_CTRL_RUN__##v << 0) & 0x1) | ||
75 | |||
76 | /** | ||
77 | * Register: HW_SYDMA_RADDR | ||
78 | * Address: 0x10 | ||
79 | * SCT: no | ||
80 | */ | ||
81 | #define HW_SYDMA_RADDR (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x10)) | ||
82 | #define BP_SYDMA_RADDR_RSRC_ADDR 0 | ||
83 | #define BM_SYDMA_RADDR_RSRC_ADDR 0xffffffff | ||
84 | #define BF_SYDMA_RADDR_RSRC_ADDR(v) (((v) << 0) & 0xffffffff) | ||
85 | |||
86 | /** | ||
87 | * Register: HW_SYDMA_WADDR | ||
88 | * Address: 0x20 | ||
89 | * SCT: no | ||
90 | */ | ||
91 | #define HW_SYDMA_WADDR (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x20)) | ||
92 | #define BP_SYDMA_WADDR_WSRC_ADDR 0 | ||
93 | #define BM_SYDMA_WADDR_WSRC_ADDR 0xffffffff | ||
94 | #define BF_SYDMA_WADDR_WSRC_ADDR(v) (((v) << 0) & 0xffffffff) | ||
95 | |||
96 | /** | ||
97 | * Register: HW_SYDMA_XFER_COUNT | ||
98 | * Address: 0x30 | ||
99 | * SCT: no | ||
100 | */ | ||
101 | #define HW_SYDMA_XFER_COUNT (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x30)) | ||
102 | #define BP_SYDMA_XFER_COUNT_SIZE 0 | ||
103 | #define BM_SYDMA_XFER_COUNT_SIZE 0xffffffff | ||
104 | #define BF_SYDMA_XFER_COUNT_SIZE(v) (((v) << 0) & 0xffffffff) | ||
105 | |||
106 | /** | ||
107 | * Register: HW_SYDMA_BURST | ||
108 | * Address: 0x40 | ||
109 | * SCT: no | ||
110 | */ | ||
111 | #define HW_SYDMA_BURST (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x40)) | ||
112 | #define BP_SYDMA_BURST_RSVD0 4 | ||
113 | #define BM_SYDMA_BURST_RSVD0 0xfffffff0 | ||
114 | #define BF_SYDMA_BURST_RSVD0(v) (((v) << 4) & 0xfffffff0) | ||
115 | #define BP_SYDMA_BURST_WLEN 2 | ||
116 | #define BM_SYDMA_BURST_WLEN 0xc | ||
117 | #define BV_SYDMA_BURST_WLEN__1 0x0 | ||
118 | #define BV_SYDMA_BURST_WLEN__2 0x1 | ||
119 | #define BV_SYDMA_BURST_WLEN__4 0x2 | ||
120 | #define BV_SYDMA_BURST_WLEN__8 0x3 | ||
121 | #define BF_SYDMA_BURST_WLEN(v) (((v) << 2) & 0xc) | ||
122 | #define BF_SYDMA_BURST_WLEN_V(v) ((BV_SYDMA_BURST_WLEN__##v << 2) & 0xc) | ||
123 | #define BP_SYDMA_BURST_RLEN 0 | ||
124 | #define BM_SYDMA_BURST_RLEN 0x3 | ||
125 | #define BV_SYDMA_BURST_RLEN__1 0x0 | ||
126 | #define BV_SYDMA_BURST_RLEN__2 0x1 | ||
127 | #define BV_SYDMA_BURST_RLEN__4 0x2 | ||
128 | #define BV_SYDMA_BURST_RLEN__8 0x3 | ||
129 | #define BF_SYDMA_BURST_RLEN(v) (((v) << 0) & 0x3) | ||
130 | #define BF_SYDMA_BURST_RLEN_V(v) ((BV_SYDMA_BURST_RLEN__##v << 0) & 0x3) | ||
131 | |||
132 | /** | ||
133 | * Register: HW_SYDMA_DACK | ||
134 | * Address: 0x50 | ||
135 | * SCT: no | ||
136 | */ | ||
137 | #define HW_SYDMA_DACK (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x50)) | ||
138 | #define BP_SYDMA_DACK_RSVD0 8 | ||
139 | #define BM_SYDMA_DACK_RSVD0 0xffffff00 | ||
140 | #define BF_SYDMA_DACK_RSVD0(v) (((v) << 8) & 0xffffff00) | ||
141 | #define BP_SYDMA_DACK_WDELAY 4 | ||
142 | #define BM_SYDMA_DACK_WDELAY 0xf0 | ||
143 | #define BF_SYDMA_DACK_WDELAY(v) (((v) << 4) & 0xf0) | ||
144 | #define BP_SYDMA_DACK_RDELAY 0 | ||
145 | #define BM_SYDMA_DACK_RDELAY 0xf | ||
146 | #define BF_SYDMA_DACK_RDELAY(v) (((v) << 0) & 0xf) | ||
147 | |||
148 | /** | ||
149 | * Register: HW_SYDMA_DEBUG0 | ||
150 | * Address: 0x100 | ||
151 | * SCT: no | ||
152 | */ | ||
153 | #define HW_SYDMA_DEBUG0 (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x100)) | ||
154 | #define BP_SYDMA_DEBUG0_DATA 0 | ||
155 | #define BM_SYDMA_DEBUG0_DATA 0xffffffff | ||
156 | #define BF_SYDMA_DEBUG0_DATA(v) (((v) << 0) & 0xffffffff) | ||
157 | |||
158 | /** | ||
159 | * Register: HW_SYDMA_DEBUG1 | ||
160 | * Address: 0x110 | ||
161 | * SCT: no | ||
162 | */ | ||
163 | #define HW_SYDMA_DEBUG1 (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x110)) | ||
164 | #define BP_SYDMA_DEBUG1_DATA 0 | ||
165 | #define BM_SYDMA_DEBUG1_DATA 0xffffffff | ||
166 | #define BF_SYDMA_DEBUG1_DATA(v) (((v) << 0) & 0xffffffff) | ||
167 | |||
168 | /** | ||
169 | * Register: HW_SYDMA_DEBUG2 | ||
170 | * Address: 0x120 | ||
171 | * SCT: no | ||
172 | */ | ||
173 | #define HW_SYDMA_DEBUG2 (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x120)) | ||
174 | #define BP_SYDMA_DEBUG2_DATA 0 | ||
175 | #define BM_SYDMA_DEBUG2_DATA 0xffffffff | ||
176 | #define BF_SYDMA_DEBUG2_DATA(v) (((v) << 0) & 0xffffffff) | ||
177 | |||
178 | /** | ||
179 | * Register: HW_SYDMA_VERSION | ||
180 | * Address: 0x130 | ||
181 | * SCT: no | ||
182 | */ | ||
183 | #define HW_SYDMA_VERSION (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x130)) | ||
184 | #define BP_SYDMA_VERSION_MAJOR 24 | ||
185 | #define BM_SYDMA_VERSION_MAJOR 0xff000000 | ||
186 | #define BF_SYDMA_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
187 | #define BP_SYDMA_VERSION_MINOR 16 | ||
188 | #define BM_SYDMA_VERSION_MINOR 0xff0000 | ||
189 | #define BF_SYDMA_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
190 | #define BP_SYDMA_VERSION_STEP 0 | ||
191 | #define BM_SYDMA_VERSION_STEP 0xffff | ||
192 | #define BF_SYDMA_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
193 | |||
194 | #endif /* __HEADERGEN__IMX233__SYDMA__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-timrot.h b/firmware/target/arm/imx233/regs/imx233/regs-timrot.h new file mode 100644 index 0000000000..f6c24f4ef8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-timrot.h | |||
@@ -0,0 +1,307 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__TIMROT__H__ | ||
24 | #define __HEADERGEN__IMX233__TIMROT__H__ | ||
25 | |||
26 | #define REGS_TIMROT_BASE (0x80068000) | ||
27 | |||
28 | #define REGS_TIMROT_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_TIMROT_ROTCTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_TIMROT_ROTCTRL (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0)) | ||
36 | #define HW_TIMROT_ROTCTRL_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4)) | ||
37 | #define HW_TIMROT_ROTCTRL_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8)) | ||
38 | #define HW_TIMROT_ROTCTRL_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc)) | ||
39 | #define BP_TIMROT_ROTCTRL_SFTRST 31 | ||
40 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | ||
41 | #define BF_TIMROT_ROTCTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_TIMROT_ROTCTRL_CLKGATE 30 | ||
43 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | ||
44 | #define BF_TIMROT_ROTCTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_TIMROT_ROTCTRL_ROTARY_PRESENT 29 | ||
46 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | ||
47 | #define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_TIMROT_ROTCTRL_TIM3_PRESENT 28 | ||
49 | #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 | ||
50 | #define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_TIMROT_ROTCTRL_TIM2_PRESENT 27 | ||
52 | #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x8000000 | ||
53 | #define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_TIMROT_ROTCTRL_TIM1_PRESENT 26 | ||
55 | #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x4000000 | ||
56 | #define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_TIMROT_ROTCTRL_TIM0_PRESENT 25 | ||
58 | #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x2000000 | ||
59 | #define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_TIMROT_ROTCTRL_STATE 22 | ||
61 | #define BM_TIMROT_ROTCTRL_STATE 0x1c00000 | ||
62 | #define BF_TIMROT_ROTCTRL_STATE(v) (((v) << 22) & 0x1c00000) | ||
63 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | ||
64 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x3f0000 | ||
65 | #define BF_TIMROT_ROTCTRL_DIVIDER(v) (((v) << 16) & 0x3f0000) | ||
66 | #define BP_TIMROT_ROTCTRL_RSRVD3 13 | ||
67 | #define BM_TIMROT_ROTCTRL_RSRVD3 0xe000 | ||
68 | #define BF_TIMROT_ROTCTRL_RSRVD3(v) (((v) << 13) & 0xe000) | ||
69 | #define BP_TIMROT_ROTCTRL_RELATIVE 12 | ||
70 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x1000 | ||
71 | #define BF_TIMROT_ROTCTRL_RELATIVE(v) (((v) << 12) & 0x1000) | ||
72 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | ||
73 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0xc00 | ||
74 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 | ||
75 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 | ||
76 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 | ||
77 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 | ||
78 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) (((v) << 10) & 0xc00) | ||
79 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v) ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00) | ||
80 | #define BP_TIMROT_ROTCTRL_POLARITY_B 9 | ||
81 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x200 | ||
82 | #define BF_TIMROT_ROTCTRL_POLARITY_B(v) (((v) << 9) & 0x200) | ||
83 | #define BP_TIMROT_ROTCTRL_POLARITY_A 8 | ||
84 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x100 | ||
85 | #define BF_TIMROT_ROTCTRL_POLARITY_A(v) (((v) << 8) & 0x100) | ||
86 | #define BP_TIMROT_ROTCTRL_RSRVD2 7 | ||
87 | #define BM_TIMROT_ROTCTRL_RSRVD2 0x80 | ||
88 | #define BF_TIMROT_ROTCTRL_RSRVD2(v) (((v) << 7) & 0x80) | ||
89 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
90 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x70 | ||
91 | #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 | ||
92 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 | ||
93 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 | ||
94 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 | ||
95 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 | ||
96 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 | ||
97 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 | ||
98 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 | ||
99 | #define BF_TIMROT_ROTCTRL_SELECT_B(v) (((v) << 4) & 0x70) | ||
100 | #define BF_TIMROT_ROTCTRL_SELECT_B_V(v) ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70) | ||
101 | #define BP_TIMROT_ROTCTRL_RSRVD1 3 | ||
102 | #define BM_TIMROT_ROTCTRL_RSRVD1 0x8 | ||
103 | #define BF_TIMROT_ROTCTRL_RSRVD1(v) (((v) << 3) & 0x8) | ||
104 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
105 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x7 | ||
106 | #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 | ||
107 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 | ||
108 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 | ||
109 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 | ||
110 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 | ||
111 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 | ||
112 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 | ||
113 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 | ||
114 | #define BF_TIMROT_ROTCTRL_SELECT_A(v) (((v) << 0) & 0x7) | ||
115 | #define BF_TIMROT_ROTCTRL_SELECT_A_V(v) ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7) | ||
116 | |||
117 | /** | ||
118 | * Register: HW_TIMROT_ROTCOUNT | ||
119 | * Address: 0x10 | ||
120 | * SCT: no | ||
121 | */ | ||
122 | #define HW_TIMROT_ROTCOUNT (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10)) | ||
123 | #define BP_TIMROT_ROTCOUNT_RSRVD1 16 | ||
124 | #define BM_TIMROT_ROTCOUNT_RSRVD1 0xffff0000 | ||
125 | #define BF_TIMROT_ROTCOUNT_RSRVD1(v) (((v) << 16) & 0xffff0000) | ||
126 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 | ||
127 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0xffff | ||
128 | #define BF_TIMROT_ROTCOUNT_UPDOWN(v) (((v) << 0) & 0xffff) | ||
129 | |||
130 | /** | ||
131 | * Register: HW_TIMROT_TIMCTRLn | ||
132 | * Address: 0x20+n*0x20 | ||
133 | * SCT: yes | ||
134 | */ | ||
135 | #define HW_TIMROT_TIMCTRLn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0)) | ||
136 | #define HW_TIMROT_TIMCTRLn_SET(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4)) | ||
137 | #define HW_TIMROT_TIMCTRLn_CLR(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8)) | ||
138 | #define HW_TIMROT_TIMCTRLn_TOG(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc)) | ||
139 | #define BP_TIMROT_TIMCTRLn_RSRVD2 16 | ||
140 | #define BM_TIMROT_TIMCTRLn_RSRVD2 0xffff0000 | ||
141 | #define BF_TIMROT_TIMCTRLn_RSRVD2(v) (((v) << 16) & 0xffff0000) | ||
142 | #define BP_TIMROT_TIMCTRLn_IRQ 15 | ||
143 | #define BM_TIMROT_TIMCTRLn_IRQ 0x8000 | ||
144 | #define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & 0x8000) | ||
145 | #define BP_TIMROT_TIMCTRLn_IRQ_EN 14 | ||
146 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x4000 | ||
147 | #define BF_TIMROT_TIMCTRLn_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
148 | #define BP_TIMROT_TIMCTRLn_RSRVD1 9 | ||
149 | #define BM_TIMROT_TIMCTRLn_RSRVD1 0x3e00 | ||
150 | #define BF_TIMROT_TIMCTRLn_RSRVD1(v) (((v) << 9) & 0x3e00) | ||
151 | #define BP_TIMROT_TIMCTRLn_POLARITY 8 | ||
152 | #define BM_TIMROT_TIMCTRLn_POLARITY 0x100 | ||
153 | #define BF_TIMROT_TIMCTRLn_POLARITY(v) (((v) << 8) & 0x100) | ||
154 | #define BP_TIMROT_TIMCTRLn_UPDATE 7 | ||
155 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x80 | ||
156 | #define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & 0x80) | ||
157 | #define BP_TIMROT_TIMCTRLn_RELOAD 6 | ||
158 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x40 | ||
159 | #define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & 0x40) | ||
160 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 | ||
161 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x30 | ||
162 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 | ||
163 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 | ||
164 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 | ||
165 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 | ||
166 | #define BF_TIMROT_TIMCTRLn_PRESCALE(v) (((v) << 4) & 0x30) | ||
167 | #define BF_TIMROT_TIMCTRLn_PRESCALE_V(v) ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30) | ||
168 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
169 | #define BM_TIMROT_TIMCTRLn_SELECT 0xf | ||
170 | #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 | ||
171 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 | ||
172 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 | ||
173 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 | ||
174 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 | ||
175 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 | ||
176 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 | ||
177 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 | ||
178 | #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
179 | #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 | ||
180 | #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xa | ||
181 | #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xb | ||
182 | #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xc | ||
183 | #define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & 0xf) | ||
184 | #define BF_TIMROT_TIMCTRLn_SELECT_V(v) ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf) | ||
185 | |||
186 | /** | ||
187 | * Register: HW_TIMROT_TIMCOUNTn | ||
188 | * Address: 0x30+n*0x20 | ||
189 | * SCT: no | ||
190 | */ | ||
191 | #define HW_TIMROT_TIMCOUNTn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20)) | ||
192 | #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 | ||
193 | #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xffff0000 | ||
194 | #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
195 | #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 | ||
196 | #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0xffff | ||
197 | #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_TIMROT_TIMCTRL3 | ||
201 | * Address: 0x80 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_TIMROT_TIMCTRL3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0)) | ||
205 | #define HW_TIMROT_TIMCTRL3_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4)) | ||
206 | #define HW_TIMROT_TIMCTRL3_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8)) | ||
207 | #define HW_TIMROT_TIMCTRL3_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc)) | ||
208 | #define BP_TIMROT_TIMCTRL3_RSRVD2 20 | ||
209 | #define BM_TIMROT_TIMCTRL3_RSRVD2 0xfff00000 | ||
210 | #define BF_TIMROT_TIMCTRL3_RSRVD2(v) (((v) << 20) & 0xfff00000) | ||
211 | #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 | ||
212 | #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0xf0000 | ||
213 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 | ||
214 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 | ||
215 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 | ||
216 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 | ||
217 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 | ||
218 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 | ||
219 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 | ||
220 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 | ||
221 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 | ||
222 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 | ||
223 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xa | ||
224 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xb | ||
225 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc | ||
226 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) (((v) << 16) & 0xf0000) | ||
227 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v) ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000) | ||
228 | #define BP_TIMROT_TIMCTRL3_IRQ 15 | ||
229 | #define BM_TIMROT_TIMCTRL3_IRQ 0x8000 | ||
230 | #define BF_TIMROT_TIMCTRL3_IRQ(v) (((v) << 15) & 0x8000) | ||
231 | #define BP_TIMROT_TIMCTRL3_IRQ_EN 14 | ||
232 | #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x4000 | ||
233 | #define BF_TIMROT_TIMCTRL3_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
234 | #define BP_TIMROT_TIMCTRL3_RSRVD1 11 | ||
235 | #define BM_TIMROT_TIMCTRL3_RSRVD1 0x3800 | ||
236 | #define BF_TIMROT_TIMCTRL3_RSRVD1(v) (((v) << 11) & 0x3800) | ||
237 | #define BP_TIMROT_TIMCTRL3_DUTY_VALID 10 | ||
238 | #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x400 | ||
239 | #define BF_TIMROT_TIMCTRL3_DUTY_VALID(v) (((v) << 10) & 0x400) | ||
240 | #define BP_TIMROT_TIMCTRL3_DUTY_CYCLE 9 | ||
241 | #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x200 | ||
242 | #define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v) (((v) << 9) & 0x200) | ||
243 | #define BP_TIMROT_TIMCTRL3_POLARITY 8 | ||
244 | #define BM_TIMROT_TIMCTRL3_POLARITY 0x100 | ||
245 | #define BF_TIMROT_TIMCTRL3_POLARITY(v) (((v) << 8) & 0x100) | ||
246 | #define BP_TIMROT_TIMCTRL3_UPDATE 7 | ||
247 | #define BM_TIMROT_TIMCTRL3_UPDATE 0x80 | ||
248 | #define BF_TIMROT_TIMCTRL3_UPDATE(v) (((v) << 7) & 0x80) | ||
249 | #define BP_TIMROT_TIMCTRL3_RELOAD 6 | ||
250 | #define BM_TIMROT_TIMCTRL3_RELOAD 0x40 | ||
251 | #define BF_TIMROT_TIMCTRL3_RELOAD(v) (((v) << 6) & 0x40) | ||
252 | #define BP_TIMROT_TIMCTRL3_PRESCALE 4 | ||
253 | #define BM_TIMROT_TIMCTRL3_PRESCALE 0x30 | ||
254 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 | ||
255 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 | ||
256 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 | ||
257 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 | ||
258 | #define BF_TIMROT_TIMCTRL3_PRESCALE(v) (((v) << 4) & 0x30) | ||
259 | #define BF_TIMROT_TIMCTRL3_PRESCALE_V(v) ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30) | ||
260 | #define BP_TIMROT_TIMCTRL3_SELECT 0 | ||
261 | #define BM_TIMROT_TIMCTRL3_SELECT 0xf | ||
262 | #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 | ||
263 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 | ||
264 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 | ||
265 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 | ||
266 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 | ||
267 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 | ||
268 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 | ||
269 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 | ||
270 | #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 | ||
271 | #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 | ||
272 | #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xa | ||
273 | #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xb | ||
274 | #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xc | ||
275 | #define BF_TIMROT_TIMCTRL3_SELECT(v) (((v) << 0) & 0xf) | ||
276 | #define BF_TIMROT_TIMCTRL3_SELECT_V(v) ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf) | ||
277 | |||
278 | /** | ||
279 | * Register: HW_TIMROT_TIMCOUNT3 | ||
280 | * Address: 0x90 | ||
281 | * SCT: no | ||
282 | */ | ||
283 | #define HW_TIMROT_TIMCOUNT3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90)) | ||
284 | #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 | ||
285 | #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xffff0000 | ||
286 | #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
287 | #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 | ||
288 | #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0xffff | ||
289 | #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
290 | |||
291 | /** | ||
292 | * Register: HW_TIMROT_VERSION | ||
293 | * Address: 0xa0 | ||
294 | * SCT: no | ||
295 | */ | ||
296 | #define HW_TIMROT_VERSION (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0xa0)) | ||
297 | #define BP_TIMROT_VERSION_MAJOR 24 | ||
298 | #define BM_TIMROT_VERSION_MAJOR 0xff000000 | ||
299 | #define BF_TIMROT_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
300 | #define BP_TIMROT_VERSION_MINOR 16 | ||
301 | #define BM_TIMROT_VERSION_MINOR 0xff0000 | ||
302 | #define BF_TIMROT_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
303 | #define BP_TIMROT_VERSION_STEP 0 | ||
304 | #define BM_TIMROT_VERSION_STEP 0xffff | ||
305 | #define BF_TIMROT_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
306 | |||
307 | #endif /* __HEADERGEN__IMX233__TIMROT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h b/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h new file mode 100644 index 0000000000..c587f5f7fa --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h | |||
@@ -0,0 +1,776 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__TVENC__H__ | ||
24 | #define __HEADERGEN__IMX233__TVENC__H__ | ||
25 | |||
26 | #define REGS_TVENC_BASE (0x80038000) | ||
27 | |||
28 | #define REGS_TVENC_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_TVENC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_TVENC_CTRL (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_TVENC_CTRL_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_TVENC_CTRL_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_TVENC_CTRL_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_TVENC_CTRL_SFTRST 31 | ||
40 | #define BM_TVENC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_TVENC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_TVENC_CTRL_CLKGATE 30 | ||
43 | #define BM_TVENC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_TVENC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_TVENC_CTRL_TVENC_MACROVISION_PRESENT 29 | ||
46 | #define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT 0x20000000 | ||
47 | #define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_TVENC_CTRL_TVENC_COMPOSITE_PRESENT 28 | ||
49 | #define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT 0x10000000 | ||
50 | #define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_TVENC_CTRL_TVENC_SVIDEO_PRESENT 27 | ||
52 | #define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT 0x8000000 | ||
53 | #define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_TVENC_CTRL_TVENC_COMPONENT_PRESENT 26 | ||
55 | #define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT 0x4000000 | ||
56 | #define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_TVENC_CTRL_RSRVD1 6 | ||
58 | #define BM_TVENC_CTRL_RSRVD1 0x3ffffc0 | ||
59 | #define BF_TVENC_CTRL_RSRVD1(v) (((v) << 6) & 0x3ffffc0) | ||
60 | #define BP_TVENC_CTRL_DAC_FIFO_NO_WRITE 5 | ||
61 | #define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE 0x20 | ||
62 | #define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(v) (((v) << 5) & 0x20) | ||
63 | #define BP_TVENC_CTRL_DAC_FIFO_NO_READ 4 | ||
64 | #define BM_TVENC_CTRL_DAC_FIFO_NO_READ 0x10 | ||
65 | #define BF_TVENC_CTRL_DAC_FIFO_NO_READ(v) (((v) << 4) & 0x10) | ||
66 | #define BP_TVENC_CTRL_DAC_DATA_FIFO_RST 3 | ||
67 | #define BM_TVENC_CTRL_DAC_DATA_FIFO_RST 0x8 | ||
68 | #define BF_TVENC_CTRL_DAC_DATA_FIFO_RST(v) (((v) << 3) & 0x8) | ||
69 | #define BP_TVENC_CTRL_RSRVD2 1 | ||
70 | #define BM_TVENC_CTRL_RSRVD2 0x6 | ||
71 | #define BF_TVENC_CTRL_RSRVD2(v) (((v) << 1) & 0x6) | ||
72 | #define BP_TVENC_CTRL_DAC_MUX_MODE 0 | ||
73 | #define BM_TVENC_CTRL_DAC_MUX_MODE 0x1 | ||
74 | #define BF_TVENC_CTRL_DAC_MUX_MODE(v) (((v) << 0) & 0x1) | ||
75 | |||
76 | /** | ||
77 | * Register: HW_TVENC_CONFIG | ||
78 | * Address: 0x10 | ||
79 | * SCT: yes | ||
80 | */ | ||
81 | #define HW_TVENC_CONFIG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x0)) | ||
82 | #define HW_TVENC_CONFIG_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x4)) | ||
83 | #define HW_TVENC_CONFIG_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x8)) | ||
84 | #define HW_TVENC_CONFIG_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0xc)) | ||
85 | #define BP_TVENC_CONFIG_RSRVD5 28 | ||
86 | #define BM_TVENC_CONFIG_RSRVD5 0xf0000000 | ||
87 | #define BF_TVENC_CONFIG_RSRVD5(v) (((v) << 28) & 0xf0000000) | ||
88 | #define BP_TVENC_CONFIG_DEFAULT_PICFORM 27 | ||
89 | #define BM_TVENC_CONFIG_DEFAULT_PICFORM 0x8000000 | ||
90 | #define BF_TVENC_CONFIG_DEFAULT_PICFORM(v) (((v) << 27) & 0x8000000) | ||
91 | #define BP_TVENC_CONFIG_YDEL_ADJ 24 | ||
92 | #define BM_TVENC_CONFIG_YDEL_ADJ 0x7000000 | ||
93 | #define BF_TVENC_CONFIG_YDEL_ADJ(v) (((v) << 24) & 0x7000000) | ||
94 | #define BP_TVENC_CONFIG_RSRVD4 23 | ||
95 | #define BM_TVENC_CONFIG_RSRVD4 0x800000 | ||
96 | #define BF_TVENC_CONFIG_RSRVD4(v) (((v) << 23) & 0x800000) | ||
97 | #define BP_TVENC_CONFIG_RSRVD3 22 | ||
98 | #define BM_TVENC_CONFIG_RSRVD3 0x400000 | ||
99 | #define BF_TVENC_CONFIG_RSRVD3(v) (((v) << 22) & 0x400000) | ||
100 | #define BP_TVENC_CONFIG_ADD_YPBPR_PED 21 | ||
101 | #define BM_TVENC_CONFIG_ADD_YPBPR_PED 0x200000 | ||
102 | #define BF_TVENC_CONFIG_ADD_YPBPR_PED(v) (((v) << 21) & 0x200000) | ||
103 | #define BP_TVENC_CONFIG_PAL_SHAPE 20 | ||
104 | #define BM_TVENC_CONFIG_PAL_SHAPE 0x100000 | ||
105 | #define BF_TVENC_CONFIG_PAL_SHAPE(v) (((v) << 20) & 0x100000) | ||
106 | #define BP_TVENC_CONFIG_NO_PED 19 | ||
107 | #define BM_TVENC_CONFIG_NO_PED 0x80000 | ||
108 | #define BF_TVENC_CONFIG_NO_PED(v) (((v) << 19) & 0x80000) | ||
109 | #define BP_TVENC_CONFIG_COLOR_BAR_EN 18 | ||
110 | #define BM_TVENC_CONFIG_COLOR_BAR_EN 0x40000 | ||
111 | #define BF_TVENC_CONFIG_COLOR_BAR_EN(v) (((v) << 18) & 0x40000) | ||
112 | #define BP_TVENC_CONFIG_YGAIN_SEL 16 | ||
113 | #define BM_TVENC_CONFIG_YGAIN_SEL 0x30000 | ||
114 | #define BF_TVENC_CONFIG_YGAIN_SEL(v) (((v) << 16) & 0x30000) | ||
115 | #define BP_TVENC_CONFIG_CGAIN 14 | ||
116 | #define BM_TVENC_CONFIG_CGAIN 0xc000 | ||
117 | #define BF_TVENC_CONFIG_CGAIN(v) (((v) << 14) & 0xc000) | ||
118 | #define BP_TVENC_CONFIG_CLK_PHS 12 | ||
119 | #define BM_TVENC_CONFIG_CLK_PHS 0x3000 | ||
120 | #define BF_TVENC_CONFIG_CLK_PHS(v) (((v) << 12) & 0x3000) | ||
121 | #define BP_TVENC_CONFIG_RSRVD2 11 | ||
122 | #define BM_TVENC_CONFIG_RSRVD2 0x800 | ||
123 | #define BF_TVENC_CONFIG_RSRVD2(v) (((v) << 11) & 0x800) | ||
124 | #define BP_TVENC_CONFIG_FSYNC_ENBL 10 | ||
125 | #define BM_TVENC_CONFIG_FSYNC_ENBL 0x400 | ||
126 | #define BF_TVENC_CONFIG_FSYNC_ENBL(v) (((v) << 10) & 0x400) | ||
127 | #define BP_TVENC_CONFIG_FSYNC_PHS 9 | ||
128 | #define BM_TVENC_CONFIG_FSYNC_PHS 0x200 | ||
129 | #define BF_TVENC_CONFIG_FSYNC_PHS(v) (((v) << 9) & 0x200) | ||
130 | #define BP_TVENC_CONFIG_HSYNC_PHS 8 | ||
131 | #define BM_TVENC_CONFIG_HSYNC_PHS 0x100 | ||
132 | #define BF_TVENC_CONFIG_HSYNC_PHS(v) (((v) << 8) & 0x100) | ||
133 | #define BP_TVENC_CONFIG_VSYNC_PHS 7 | ||
134 | #define BM_TVENC_CONFIG_VSYNC_PHS 0x80 | ||
135 | #define BF_TVENC_CONFIG_VSYNC_PHS(v) (((v) << 7) & 0x80) | ||
136 | #define BP_TVENC_CONFIG_SYNC_MODE 4 | ||
137 | #define BM_TVENC_CONFIG_SYNC_MODE 0x70 | ||
138 | #define BF_TVENC_CONFIG_SYNC_MODE(v) (((v) << 4) & 0x70) | ||
139 | #define BP_TVENC_CONFIG_RSRVD1 3 | ||
140 | #define BM_TVENC_CONFIG_RSRVD1 0x8 | ||
141 | #define BF_TVENC_CONFIG_RSRVD1(v) (((v) << 3) & 0x8) | ||
142 | #define BP_TVENC_CONFIG_ENCD_MODE 0 | ||
143 | #define BM_TVENC_CONFIG_ENCD_MODE 0x7 | ||
144 | #define BF_TVENC_CONFIG_ENCD_MODE(v) (((v) << 0) & 0x7) | ||
145 | |||
146 | /** | ||
147 | * Register: HW_TVENC_FILTCTRL | ||
148 | * Address: 0x20 | ||
149 | * SCT: yes | ||
150 | */ | ||
151 | #define HW_TVENC_FILTCTRL (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x0)) | ||
152 | #define HW_TVENC_FILTCTRL_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x4)) | ||
153 | #define HW_TVENC_FILTCTRL_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x8)) | ||
154 | #define HW_TVENC_FILTCTRL_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0xc)) | ||
155 | #define BP_TVENC_FILTCTRL_RSRVD1 20 | ||
156 | #define BM_TVENC_FILTCTRL_RSRVD1 0xfff00000 | ||
157 | #define BF_TVENC_FILTCTRL_RSRVD1(v) (((v) << 20) & 0xfff00000) | ||
158 | #define BP_TVENC_FILTCTRL_YSHARP_BW 19 | ||
159 | #define BM_TVENC_FILTCTRL_YSHARP_BW 0x80000 | ||
160 | #define BF_TVENC_FILTCTRL_YSHARP_BW(v) (((v) << 19) & 0x80000) | ||
161 | #define BP_TVENC_FILTCTRL_YD_OFFSETSEL 18 | ||
162 | #define BM_TVENC_FILTCTRL_YD_OFFSETSEL 0x40000 | ||
163 | #define BF_TVENC_FILTCTRL_YD_OFFSETSEL(v) (((v) << 18) & 0x40000) | ||
164 | #define BP_TVENC_FILTCTRL_SEL_YLPF 17 | ||
165 | #define BM_TVENC_FILTCTRL_SEL_YLPF 0x20000 | ||
166 | #define BF_TVENC_FILTCTRL_SEL_YLPF(v) (((v) << 17) & 0x20000) | ||
167 | #define BP_TVENC_FILTCTRL_SEL_CLPF 16 | ||
168 | #define BM_TVENC_FILTCTRL_SEL_CLPF 0x10000 | ||
169 | #define BF_TVENC_FILTCTRL_SEL_CLPF(v) (((v) << 16) & 0x10000) | ||
170 | #define BP_TVENC_FILTCTRL_SEL_YSHARP 15 | ||
171 | #define BM_TVENC_FILTCTRL_SEL_YSHARP 0x8000 | ||
172 | #define BF_TVENC_FILTCTRL_SEL_YSHARP(v) (((v) << 15) & 0x8000) | ||
173 | #define BP_TVENC_FILTCTRL_YLPF_COEFSEL 14 | ||
174 | #define BM_TVENC_FILTCTRL_YLPF_COEFSEL 0x4000 | ||
175 | #define BF_TVENC_FILTCTRL_YLPF_COEFSEL(v) (((v) << 14) & 0x4000) | ||
176 | #define BP_TVENC_FILTCTRL_COEFSEL_CLPF 13 | ||
177 | #define BM_TVENC_FILTCTRL_COEFSEL_CLPF 0x2000 | ||
178 | #define BF_TVENC_FILTCTRL_COEFSEL_CLPF(v) (((v) << 13) & 0x2000) | ||
179 | #define BP_TVENC_FILTCTRL_YS_GAINSGN 12 | ||
180 | #define BM_TVENC_FILTCTRL_YS_GAINSGN 0x1000 | ||
181 | #define BF_TVENC_FILTCTRL_YS_GAINSGN(v) (((v) << 12) & 0x1000) | ||
182 | #define BP_TVENC_FILTCTRL_YS_GAINSEL 10 | ||
183 | #define BM_TVENC_FILTCTRL_YS_GAINSEL 0xc00 | ||
184 | #define BF_TVENC_FILTCTRL_YS_GAINSEL(v) (((v) << 10) & 0xc00) | ||
185 | #define BP_TVENC_FILTCTRL_RSRVD2 9 | ||
186 | #define BM_TVENC_FILTCTRL_RSRVD2 0x200 | ||
187 | #define BF_TVENC_FILTCTRL_RSRVD2(v) (((v) << 9) & 0x200) | ||
188 | #define BP_TVENC_FILTCTRL_RSRVD3 8 | ||
189 | #define BM_TVENC_FILTCTRL_RSRVD3 0x100 | ||
190 | #define BF_TVENC_FILTCTRL_RSRVD3(v) (((v) << 8) & 0x100) | ||
191 | #define BP_TVENC_FILTCTRL_RSRVD4 0 | ||
192 | #define BM_TVENC_FILTCTRL_RSRVD4 0xff | ||
193 | #define BF_TVENC_FILTCTRL_RSRVD4(v) (((v) << 0) & 0xff) | ||
194 | |||
195 | /** | ||
196 | * Register: HW_TVENC_SYNCOFFSET | ||
197 | * Address: 0x30 | ||
198 | * SCT: yes | ||
199 | */ | ||
200 | #define HW_TVENC_SYNCOFFSET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x0)) | ||
201 | #define HW_TVENC_SYNCOFFSET_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x4)) | ||
202 | #define HW_TVENC_SYNCOFFSET_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x8)) | ||
203 | #define HW_TVENC_SYNCOFFSET_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0xc)) | ||
204 | #define BP_TVENC_SYNCOFFSET_RSRVD1 31 | ||
205 | #define BM_TVENC_SYNCOFFSET_RSRVD1 0x80000000 | ||
206 | #define BF_TVENC_SYNCOFFSET_RSRVD1(v) (((v) << 31) & 0x80000000) | ||
207 | #define BP_TVENC_SYNCOFFSET_HSO 20 | ||
208 | #define BM_TVENC_SYNCOFFSET_HSO 0x7ff00000 | ||
209 | #define BF_TVENC_SYNCOFFSET_HSO(v) (((v) << 20) & 0x7ff00000) | ||
210 | #define BP_TVENC_SYNCOFFSET_VSO 10 | ||
211 | #define BM_TVENC_SYNCOFFSET_VSO 0xffc00 | ||
212 | #define BF_TVENC_SYNCOFFSET_VSO(v) (((v) << 10) & 0xffc00) | ||
213 | #define BP_TVENC_SYNCOFFSET_HLC 0 | ||
214 | #define BM_TVENC_SYNCOFFSET_HLC 0x3ff | ||
215 | #define BF_TVENC_SYNCOFFSET_HLC(v) (((v) << 0) & 0x3ff) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_TVENC_HTIMINGSYNC0 | ||
219 | * Address: 0x40 | ||
220 | * SCT: yes | ||
221 | */ | ||
222 | #define HW_TVENC_HTIMINGSYNC0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x0)) | ||
223 | #define HW_TVENC_HTIMINGSYNC0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x4)) | ||
224 | #define HW_TVENC_HTIMINGSYNC0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x8)) | ||
225 | #define HW_TVENC_HTIMINGSYNC0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0xc)) | ||
226 | #define BP_TVENC_HTIMINGSYNC0_RSRVD2 26 | ||
227 | #define BM_TVENC_HTIMINGSYNC0_RSRVD2 0xfc000000 | ||
228 | #define BF_TVENC_HTIMINGSYNC0_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
229 | #define BP_TVENC_HTIMINGSYNC0_SYNC_END 16 | ||
230 | #define BM_TVENC_HTIMINGSYNC0_SYNC_END 0x3ff0000 | ||
231 | #define BF_TVENC_HTIMINGSYNC0_SYNC_END(v) (((v) << 16) & 0x3ff0000) | ||
232 | #define BP_TVENC_HTIMINGSYNC0_RSRVD1 10 | ||
233 | #define BM_TVENC_HTIMINGSYNC0_RSRVD1 0xfc00 | ||
234 | #define BF_TVENC_HTIMINGSYNC0_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
235 | #define BP_TVENC_HTIMINGSYNC0_SYNC_STRT 0 | ||
236 | #define BM_TVENC_HTIMINGSYNC0_SYNC_STRT 0x3ff | ||
237 | #define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v) (((v) << 0) & 0x3ff) | ||
238 | |||
239 | /** | ||
240 | * Register: HW_TVENC_HTIMINGSYNC1 | ||
241 | * Address: 0x50 | ||
242 | * SCT: yes | ||
243 | */ | ||
244 | #define HW_TVENC_HTIMINGSYNC1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x0)) | ||
245 | #define HW_TVENC_HTIMINGSYNC1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x4)) | ||
246 | #define HW_TVENC_HTIMINGSYNC1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x8)) | ||
247 | #define HW_TVENC_HTIMINGSYNC1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0xc)) | ||
248 | #define BP_TVENC_HTIMINGSYNC1_RSRVD2 26 | ||
249 | #define BM_TVENC_HTIMINGSYNC1_RSRVD2 0xfc000000 | ||
250 | #define BF_TVENC_HTIMINGSYNC1_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
251 | #define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND 16 | ||
252 | #define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND 0x3ff0000 | ||
253 | #define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v) (((v) << 16) & 0x3ff0000) | ||
254 | #define BP_TVENC_HTIMINGSYNC1_RSRVD1 10 | ||
255 | #define BM_TVENC_HTIMINGSYNC1_RSRVD1 0xfc00 | ||
256 | #define BF_TVENC_HTIMINGSYNC1_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
257 | #define BP_TVENC_HTIMINGSYNC1_SYNC_SREND 0 | ||
258 | #define BM_TVENC_HTIMINGSYNC1_SYNC_SREND 0x3ff | ||
259 | #define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v) (((v) << 0) & 0x3ff) | ||
260 | |||
261 | /** | ||
262 | * Register: HW_TVENC_HTIMINGACTIVE | ||
263 | * Address: 0x60 | ||
264 | * SCT: yes | ||
265 | */ | ||
266 | #define HW_TVENC_HTIMINGACTIVE (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x0)) | ||
267 | #define HW_TVENC_HTIMINGACTIVE_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x4)) | ||
268 | #define HW_TVENC_HTIMINGACTIVE_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x8)) | ||
269 | #define HW_TVENC_HTIMINGACTIVE_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0xc)) | ||
270 | #define BP_TVENC_HTIMINGACTIVE_RSRVD2 26 | ||
271 | #define BM_TVENC_HTIMINGACTIVE_RSRVD2 0xfc000000 | ||
272 | #define BF_TVENC_HTIMINGACTIVE_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
273 | #define BP_TVENC_HTIMINGACTIVE_ACTV_END 16 | ||
274 | #define BM_TVENC_HTIMINGACTIVE_ACTV_END 0x3ff0000 | ||
275 | #define BF_TVENC_HTIMINGACTIVE_ACTV_END(v) (((v) << 16) & 0x3ff0000) | ||
276 | #define BP_TVENC_HTIMINGACTIVE_RSRVD1 10 | ||
277 | #define BM_TVENC_HTIMINGACTIVE_RSRVD1 0xfc00 | ||
278 | #define BF_TVENC_HTIMINGACTIVE_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
279 | #define BP_TVENC_HTIMINGACTIVE_ACTV_STRT 0 | ||
280 | #define BM_TVENC_HTIMINGACTIVE_ACTV_STRT 0x3ff | ||
281 | #define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v) (((v) << 0) & 0x3ff) | ||
282 | |||
283 | /** | ||
284 | * Register: HW_TVENC_HTIMINGBURST0 | ||
285 | * Address: 0x70 | ||
286 | * SCT: yes | ||
287 | */ | ||
288 | #define HW_TVENC_HTIMINGBURST0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x0)) | ||
289 | #define HW_TVENC_HTIMINGBURST0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x4)) | ||
290 | #define HW_TVENC_HTIMINGBURST0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x8)) | ||
291 | #define HW_TVENC_HTIMINGBURST0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0xc)) | ||
292 | #define BP_TVENC_HTIMINGBURST0_RSRVD2 26 | ||
293 | #define BM_TVENC_HTIMINGBURST0_RSRVD2 0xfc000000 | ||
294 | #define BF_TVENC_HTIMINGBURST0_RSRVD2(v) (((v) << 26) & 0xfc000000) | ||
295 | #define BP_TVENC_HTIMINGBURST0_WBRST_STRT 16 | ||
296 | #define BM_TVENC_HTIMINGBURST0_WBRST_STRT 0x3ff0000 | ||
297 | #define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v) (((v) << 16) & 0x3ff0000) | ||
298 | #define BP_TVENC_HTIMINGBURST0_RSRVD1 10 | ||
299 | #define BM_TVENC_HTIMINGBURST0_RSRVD1 0xfc00 | ||
300 | #define BF_TVENC_HTIMINGBURST0_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
301 | #define BP_TVENC_HTIMINGBURST0_NBRST_STRT 0 | ||
302 | #define BM_TVENC_HTIMINGBURST0_NBRST_STRT 0x3ff | ||
303 | #define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v) (((v) << 0) & 0x3ff) | ||
304 | |||
305 | /** | ||
306 | * Register: HW_TVENC_HTIMINGBURST1 | ||
307 | * Address: 0x80 | ||
308 | * SCT: yes | ||
309 | */ | ||
310 | #define HW_TVENC_HTIMINGBURST1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x0)) | ||
311 | #define HW_TVENC_HTIMINGBURST1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x4)) | ||
312 | #define HW_TVENC_HTIMINGBURST1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x8)) | ||
313 | #define HW_TVENC_HTIMINGBURST1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0xc)) | ||
314 | #define BP_TVENC_HTIMINGBURST1_RSRVD1 10 | ||
315 | #define BM_TVENC_HTIMINGBURST1_RSRVD1 0xfffffc00 | ||
316 | #define BF_TVENC_HTIMINGBURST1_RSRVD1(v) (((v) << 10) & 0xfffffc00) | ||
317 | #define BP_TVENC_HTIMINGBURST1_BRST_END 0 | ||
318 | #define BM_TVENC_HTIMINGBURST1_BRST_END 0x3ff | ||
319 | #define BF_TVENC_HTIMINGBURST1_BRST_END(v) (((v) << 0) & 0x3ff) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_TVENC_VTIMING0 | ||
323 | * Address: 0x90 | ||
324 | * SCT: yes | ||
325 | */ | ||
326 | #define HW_TVENC_VTIMING0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x0)) | ||
327 | #define HW_TVENC_VTIMING0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x4)) | ||
328 | #define HW_TVENC_VTIMING0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x8)) | ||
329 | #define HW_TVENC_VTIMING0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0xc)) | ||
330 | #define BP_TVENC_VTIMING0_RSRVD3 26 | ||
331 | #define BM_TVENC_VTIMING0_RSRVD3 0xfc000000 | ||
332 | #define BF_TVENC_VTIMING0_RSRVD3(v) (((v) << 26) & 0xfc000000) | ||
333 | #define BP_TVENC_VTIMING0_VSTRT_PREEQ 16 | ||
334 | #define BM_TVENC_VTIMING0_VSTRT_PREEQ 0x3ff0000 | ||
335 | #define BF_TVENC_VTIMING0_VSTRT_PREEQ(v) (((v) << 16) & 0x3ff0000) | ||
336 | #define BP_TVENC_VTIMING0_RSRVD2 14 | ||
337 | #define BM_TVENC_VTIMING0_RSRVD2 0xc000 | ||
338 | #define BF_TVENC_VTIMING0_RSRVD2(v) (((v) << 14) & 0xc000) | ||
339 | #define BP_TVENC_VTIMING0_VSTRT_ACTV 8 | ||
340 | #define BM_TVENC_VTIMING0_VSTRT_ACTV 0x3f00 | ||
341 | #define BF_TVENC_VTIMING0_VSTRT_ACTV(v) (((v) << 8) & 0x3f00) | ||
342 | #define BP_TVENC_VTIMING0_RSRVD1 6 | ||
343 | #define BM_TVENC_VTIMING0_RSRVD1 0xc0 | ||
344 | #define BF_TVENC_VTIMING0_RSRVD1(v) (((v) << 6) & 0xc0) | ||
345 | #define BP_TVENC_VTIMING0_VSTRT_SUBPH 0 | ||
346 | #define BM_TVENC_VTIMING0_VSTRT_SUBPH 0x3f | ||
347 | #define BF_TVENC_VTIMING0_VSTRT_SUBPH(v) (((v) << 0) & 0x3f) | ||
348 | |||
349 | /** | ||
350 | * Register: HW_TVENC_VTIMING1 | ||
351 | * Address: 0xa0 | ||
352 | * SCT: yes | ||
353 | */ | ||
354 | #define HW_TVENC_VTIMING1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x0)) | ||
355 | #define HW_TVENC_VTIMING1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x4)) | ||
356 | #define HW_TVENC_VTIMING1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x8)) | ||
357 | #define HW_TVENC_VTIMING1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0xc)) | ||
358 | #define BP_TVENC_VTIMING1_RSRVD3 30 | ||
359 | #define BM_TVENC_VTIMING1_RSRVD3 0xc0000000 | ||
360 | #define BF_TVENC_VTIMING1_RSRVD3(v) (((v) << 30) & 0xc0000000) | ||
361 | #define BP_TVENC_VTIMING1_VSTRT_POSTEQ 24 | ||
362 | #define BM_TVENC_VTIMING1_VSTRT_POSTEQ 0x3f000000 | ||
363 | #define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v) (((v) << 24) & 0x3f000000) | ||
364 | #define BP_TVENC_VTIMING1_RSRVD2 22 | ||
365 | #define BM_TVENC_VTIMING1_RSRVD2 0xc00000 | ||
366 | #define BF_TVENC_VTIMING1_RSRVD2(v) (((v) << 22) & 0xc00000) | ||
367 | #define BP_TVENC_VTIMING1_VSTRT_SERRA 16 | ||
368 | #define BM_TVENC_VTIMING1_VSTRT_SERRA 0x3f0000 | ||
369 | #define BF_TVENC_VTIMING1_VSTRT_SERRA(v) (((v) << 16) & 0x3f0000) | ||
370 | #define BP_TVENC_VTIMING1_RSRVD1 10 | ||
371 | #define BM_TVENC_VTIMING1_RSRVD1 0xfc00 | ||
372 | #define BF_TVENC_VTIMING1_RSRVD1(v) (((v) << 10) & 0xfc00) | ||
373 | #define BP_TVENC_VTIMING1_LAST_FLD_LN 0 | ||
374 | #define BM_TVENC_VTIMING1_LAST_FLD_LN 0x3ff | ||
375 | #define BF_TVENC_VTIMING1_LAST_FLD_LN(v) (((v) << 0) & 0x3ff) | ||
376 | |||
377 | /** | ||
378 | * Register: HW_TVENC_MISC | ||
379 | * Address: 0xb0 | ||
380 | * SCT: yes | ||
381 | */ | ||
382 | #define HW_TVENC_MISC (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x0)) | ||
383 | #define HW_TVENC_MISC_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x4)) | ||
384 | #define HW_TVENC_MISC_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x8)) | ||
385 | #define HW_TVENC_MISC_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0xc)) | ||
386 | #define BP_TVENC_MISC_RSRVD3 25 | ||
387 | #define BM_TVENC_MISC_RSRVD3 0xfe000000 | ||
388 | #define BF_TVENC_MISC_RSRVD3(v) (((v) << 25) & 0xfe000000) | ||
389 | #define BP_TVENC_MISC_LPF_RST_OFF 16 | ||
390 | #define BM_TVENC_MISC_LPF_RST_OFF 0x1ff0000 | ||
391 | #define BF_TVENC_MISC_LPF_RST_OFF(v) (((v) << 16) & 0x1ff0000) | ||
392 | #define BP_TVENC_MISC_RSRVD2 12 | ||
393 | #define BM_TVENC_MISC_RSRVD2 0xf000 | ||
394 | #define BF_TVENC_MISC_RSRVD2(v) (((v) << 12) & 0xf000) | ||
395 | #define BP_TVENC_MISC_NTSC_LN_CNT 11 | ||
396 | #define BM_TVENC_MISC_NTSC_LN_CNT 0x800 | ||
397 | #define BF_TVENC_MISC_NTSC_LN_CNT(v) (((v) << 11) & 0x800) | ||
398 | #define BP_TVENC_MISC_PAL_FSC_PHASE_ALT 10 | ||
399 | #define BM_TVENC_MISC_PAL_FSC_PHASE_ALT 0x400 | ||
400 | #define BF_TVENC_MISC_PAL_FSC_PHASE_ALT(v) (((v) << 10) & 0x400) | ||
401 | #define BP_TVENC_MISC_FSC_PHASE_RST 8 | ||
402 | #define BM_TVENC_MISC_FSC_PHASE_RST 0x300 | ||
403 | #define BF_TVENC_MISC_FSC_PHASE_RST(v) (((v) << 8) & 0x300) | ||
404 | #define BP_TVENC_MISC_BRUCHB 6 | ||
405 | #define BM_TVENC_MISC_BRUCHB 0xc0 | ||
406 | #define BF_TVENC_MISC_BRUCHB(v) (((v) << 6) & 0xc0) | ||
407 | #define BP_TVENC_MISC_AGC_LVL_CTRL 4 | ||
408 | #define BM_TVENC_MISC_AGC_LVL_CTRL 0x30 | ||
409 | #define BF_TVENC_MISC_AGC_LVL_CTRL(v) (((v) << 4) & 0x30) | ||
410 | #define BP_TVENC_MISC_RSRVD1 3 | ||
411 | #define BM_TVENC_MISC_RSRVD1 0x8 | ||
412 | #define BF_TVENC_MISC_RSRVD1(v) (((v) << 3) & 0x8) | ||
413 | #define BP_TVENC_MISC_CS_INVERT_CTRL 2 | ||
414 | #define BM_TVENC_MISC_CS_INVERT_CTRL 0x4 | ||
415 | #define BF_TVENC_MISC_CS_INVERT_CTRL(v) (((v) << 2) & 0x4) | ||
416 | #define BP_TVENC_MISC_Y_BLANK_CTRL 0 | ||
417 | #define BM_TVENC_MISC_Y_BLANK_CTRL 0x3 | ||
418 | #define BF_TVENC_MISC_Y_BLANK_CTRL(v) (((v) << 0) & 0x3) | ||
419 | |||
420 | /** | ||
421 | * Register: HW_TVENC_COLORSUB0 | ||
422 | * Address: 0xc0 | ||
423 | * SCT: yes | ||
424 | */ | ||
425 | #define HW_TVENC_COLORSUB0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x0)) | ||
426 | #define HW_TVENC_COLORSUB0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x4)) | ||
427 | #define HW_TVENC_COLORSUB0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x8)) | ||
428 | #define HW_TVENC_COLORSUB0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0xc)) | ||
429 | #define BP_TVENC_COLORSUB0_PHASE_INC 0 | ||
430 | #define BM_TVENC_COLORSUB0_PHASE_INC 0xffffffff | ||
431 | #define BF_TVENC_COLORSUB0_PHASE_INC(v) (((v) << 0) & 0xffffffff) | ||
432 | |||
433 | /** | ||
434 | * Register: HW_TVENC_COLORSUB1 | ||
435 | * Address: 0xd0 | ||
436 | * SCT: yes | ||
437 | */ | ||
438 | #define HW_TVENC_COLORSUB1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x0)) | ||
439 | #define HW_TVENC_COLORSUB1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x4)) | ||
440 | #define HW_TVENC_COLORSUB1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x8)) | ||
441 | #define HW_TVENC_COLORSUB1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0xc)) | ||
442 | #define BP_TVENC_COLORSUB1_PHASE_OFFSET 0 | ||
443 | #define BM_TVENC_COLORSUB1_PHASE_OFFSET 0xffffffff | ||
444 | #define BF_TVENC_COLORSUB1_PHASE_OFFSET(v) (((v) << 0) & 0xffffffff) | ||
445 | |||
446 | /** | ||
447 | * Register: HW_TVENC_COPYPROTECT | ||
448 | * Address: 0xe0 | ||
449 | * SCT: yes | ||
450 | */ | ||
451 | #define HW_TVENC_COPYPROTECT (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x0)) | ||
452 | #define HW_TVENC_COPYPROTECT_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x4)) | ||
453 | #define HW_TVENC_COPYPROTECT_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x8)) | ||
454 | #define HW_TVENC_COPYPROTECT_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0xc)) | ||
455 | #define BP_TVENC_COPYPROTECT_RSRVD1 16 | ||
456 | #define BM_TVENC_COPYPROTECT_RSRVD1 0xffff0000 | ||
457 | #define BF_TVENC_COPYPROTECT_RSRVD1(v) (((v) << 16) & 0xffff0000) | ||
458 | #define BP_TVENC_COPYPROTECT_WSS_ENBL 15 | ||
459 | #define BM_TVENC_COPYPROTECT_WSS_ENBL 0x8000 | ||
460 | #define BF_TVENC_COPYPROTECT_WSS_ENBL(v) (((v) << 15) & 0x8000) | ||
461 | #define BP_TVENC_COPYPROTECT_CGMS_ENBL 14 | ||
462 | #define BM_TVENC_COPYPROTECT_CGMS_ENBL 0x4000 | ||
463 | #define BF_TVENC_COPYPROTECT_CGMS_ENBL(v) (((v) << 14) & 0x4000) | ||
464 | #define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA 0 | ||
465 | #define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA 0x3fff | ||
466 | #define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v) (((v) << 0) & 0x3fff) | ||
467 | |||
468 | /** | ||
469 | * Register: HW_TVENC_CLOSEDCAPTION | ||
470 | * Address: 0xf0 | ||
471 | * SCT: yes | ||
472 | */ | ||
473 | #define HW_TVENC_CLOSEDCAPTION (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x0)) | ||
474 | #define HW_TVENC_CLOSEDCAPTION_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x4)) | ||
475 | #define HW_TVENC_CLOSEDCAPTION_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x8)) | ||
476 | #define HW_TVENC_CLOSEDCAPTION_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0xc)) | ||
477 | #define BP_TVENC_CLOSEDCAPTION_RSRVD1 20 | ||
478 | #define BM_TVENC_CLOSEDCAPTION_RSRVD1 0xfff00000 | ||
479 | #define BF_TVENC_CLOSEDCAPTION_RSRVD1(v) (((v) << 20) & 0xfff00000) | ||
480 | #define BP_TVENC_CLOSEDCAPTION_CC_ENBL 18 | ||
481 | #define BM_TVENC_CLOSEDCAPTION_CC_ENBL 0xc0000 | ||
482 | #define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v) (((v) << 18) & 0xc0000) | ||
483 | #define BP_TVENC_CLOSEDCAPTION_CC_FILL 16 | ||
484 | #define BM_TVENC_CLOSEDCAPTION_CC_FILL 0x30000 | ||
485 | #define BF_TVENC_CLOSEDCAPTION_CC_FILL(v) (((v) << 16) & 0x30000) | ||
486 | #define BP_TVENC_CLOSEDCAPTION_CC_DATA 0 | ||
487 | #define BM_TVENC_CLOSEDCAPTION_CC_DATA 0xffff | ||
488 | #define BF_TVENC_CLOSEDCAPTION_CC_DATA(v) (((v) << 0) & 0xffff) | ||
489 | |||
490 | /** | ||
491 | * Register: HW_TVENC_COLORBURST | ||
492 | * Address: 0x140 | ||
493 | * SCT: yes | ||
494 | */ | ||
495 | #define HW_TVENC_COLORBURST (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x0)) | ||
496 | #define HW_TVENC_COLORBURST_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x4)) | ||
497 | #define HW_TVENC_COLORBURST_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x8)) | ||
498 | #define HW_TVENC_COLORBURST_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0xc)) | ||
499 | #define BP_TVENC_COLORBURST_NBA 24 | ||
500 | #define BM_TVENC_COLORBURST_NBA 0xff000000 | ||
501 | #define BF_TVENC_COLORBURST_NBA(v) (((v) << 24) & 0xff000000) | ||
502 | #define BP_TVENC_COLORBURST_PBA 16 | ||
503 | #define BM_TVENC_COLORBURST_PBA 0xff0000 | ||
504 | #define BF_TVENC_COLORBURST_PBA(v) (((v) << 16) & 0xff0000) | ||
505 | #define BP_TVENC_COLORBURST_RSRVD1 12 | ||
506 | #define BM_TVENC_COLORBURST_RSRVD1 0xf000 | ||
507 | #define BF_TVENC_COLORBURST_RSRVD1(v) (((v) << 12) & 0xf000) | ||
508 | #define BP_TVENC_COLORBURST_RSRVD2 0 | ||
509 | #define BM_TVENC_COLORBURST_RSRVD2 0xfff | ||
510 | #define BF_TVENC_COLORBURST_RSRVD2(v) (((v) << 0) & 0xfff) | ||
511 | |||
512 | /** | ||
513 | * Register: HW_TVENC_MACROVISION0 | ||
514 | * Address: 0x150 | ||
515 | * SCT: yes | ||
516 | */ | ||
517 | #define HW_TVENC_MACROVISION0 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x0)) | ||
518 | #define HW_TVENC_MACROVISION0_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x4)) | ||
519 | #define HW_TVENC_MACROVISION0_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x8)) | ||
520 | #define HW_TVENC_MACROVISION0_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0xc)) | ||
521 | #define BP_TVENC_MACROVISION0_DATA 0 | ||
522 | #define BM_TVENC_MACROVISION0_DATA 0xffffffff | ||
523 | #define BF_TVENC_MACROVISION0_DATA(v) (((v) << 0) & 0xffffffff) | ||
524 | |||
525 | /** | ||
526 | * Register: HW_TVENC_MACROVISION1 | ||
527 | * Address: 0x160 | ||
528 | * SCT: yes | ||
529 | */ | ||
530 | #define HW_TVENC_MACROVISION1 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x0)) | ||
531 | #define HW_TVENC_MACROVISION1_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x4)) | ||
532 | #define HW_TVENC_MACROVISION1_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x8)) | ||
533 | #define HW_TVENC_MACROVISION1_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0xc)) | ||
534 | #define BP_TVENC_MACROVISION1_DATA 0 | ||
535 | #define BM_TVENC_MACROVISION1_DATA 0xffffffff | ||
536 | #define BF_TVENC_MACROVISION1_DATA(v) (((v) << 0) & 0xffffffff) | ||
537 | |||
538 | /** | ||
539 | * Register: HW_TVENC_MACROVISION2 | ||
540 | * Address: 0x170 | ||
541 | * SCT: yes | ||
542 | */ | ||
543 | #define HW_TVENC_MACROVISION2 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x0)) | ||
544 | #define HW_TVENC_MACROVISION2_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x4)) | ||
545 | #define HW_TVENC_MACROVISION2_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x8)) | ||
546 | #define HW_TVENC_MACROVISION2_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0xc)) | ||
547 | #define BP_TVENC_MACROVISION2_DATA 0 | ||
548 | #define BM_TVENC_MACROVISION2_DATA 0xffffffff | ||
549 | #define BF_TVENC_MACROVISION2_DATA(v) (((v) << 0) & 0xffffffff) | ||
550 | |||
551 | /** | ||
552 | * Register: HW_TVENC_MACROVISION3 | ||
553 | * Address: 0x180 | ||
554 | * SCT: yes | ||
555 | */ | ||
556 | #define HW_TVENC_MACROVISION3 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x0)) | ||
557 | #define HW_TVENC_MACROVISION3_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x4)) | ||
558 | #define HW_TVENC_MACROVISION3_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x8)) | ||
559 | #define HW_TVENC_MACROVISION3_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0xc)) | ||
560 | #define BP_TVENC_MACROVISION3_DATA 0 | ||
561 | #define BM_TVENC_MACROVISION3_DATA 0xffffffff | ||
562 | #define BF_TVENC_MACROVISION3_DATA(v) (((v) << 0) & 0xffffffff) | ||
563 | |||
564 | /** | ||
565 | * Register: HW_TVENC_MACROVISION4 | ||
566 | * Address: 0x190 | ||
567 | * SCT: yes | ||
568 | */ | ||
569 | #define HW_TVENC_MACROVISION4 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x0)) | ||
570 | #define HW_TVENC_MACROVISION4_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x4)) | ||
571 | #define HW_TVENC_MACROVISION4_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x8)) | ||
572 | #define HW_TVENC_MACROVISION4_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0xc)) | ||
573 | #define BP_TVENC_MACROVISION4_RSRVD2 24 | ||
574 | #define BM_TVENC_MACROVISION4_RSRVD2 0xff000000 | ||
575 | #define BF_TVENC_MACROVISION4_RSRVD2(v) (((v) << 24) & 0xff000000) | ||
576 | #define BP_TVENC_MACROVISION4_MACV_TST 16 | ||
577 | #define BM_TVENC_MACROVISION4_MACV_TST 0xff0000 | ||
578 | #define BF_TVENC_MACROVISION4_MACV_TST(v) (((v) << 16) & 0xff0000) | ||
579 | #define BP_TVENC_MACROVISION4_RSRVD1 11 | ||
580 | #define BM_TVENC_MACROVISION4_RSRVD1 0xf800 | ||
581 | #define BF_TVENC_MACROVISION4_RSRVD1(v) (((v) << 11) & 0xf800) | ||
582 | #define BP_TVENC_MACROVISION4_DATA 0 | ||
583 | #define BM_TVENC_MACROVISION4_DATA 0x7ff | ||
584 | #define BF_TVENC_MACROVISION4_DATA(v) (((v) << 0) & 0x7ff) | ||
585 | |||
586 | /** | ||
587 | * Register: HW_TVENC_DACCTRL | ||
588 | * Address: 0x1a0 | ||
589 | * SCT: yes | ||
590 | */ | ||
591 | #define HW_TVENC_DACCTRL (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x0)) | ||
592 | #define HW_TVENC_DACCTRL_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x4)) | ||
593 | #define HW_TVENC_DACCTRL_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x8)) | ||
594 | #define HW_TVENC_DACCTRL_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0xc)) | ||
595 | #define BP_TVENC_DACCTRL_TEST3 31 | ||
596 | #define BM_TVENC_DACCTRL_TEST3 0x80000000 | ||
597 | #define BF_TVENC_DACCTRL_TEST3(v) (((v) << 31) & 0x80000000) | ||
598 | #define BP_TVENC_DACCTRL_RSRVD1 30 | ||
599 | #define BM_TVENC_DACCTRL_RSRVD1 0x40000000 | ||
600 | #define BF_TVENC_DACCTRL_RSRVD1(v) (((v) << 30) & 0x40000000) | ||
601 | #define BP_TVENC_DACCTRL_RSRVD2 29 | ||
602 | #define BM_TVENC_DACCTRL_RSRVD2 0x20000000 | ||
603 | #define BF_TVENC_DACCTRL_RSRVD2(v) (((v) << 29) & 0x20000000) | ||
604 | #define BP_TVENC_DACCTRL_JACK1_DIS_DET_EN 28 | ||
605 | #define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN 0x10000000 | ||
606 | #define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(v) (((v) << 28) & 0x10000000) | ||
607 | #define BP_TVENC_DACCTRL_TEST2 27 | ||
608 | #define BM_TVENC_DACCTRL_TEST2 0x8000000 | ||
609 | #define BF_TVENC_DACCTRL_TEST2(v) (((v) << 27) & 0x8000000) | ||
610 | #define BP_TVENC_DACCTRL_RSRVD3 26 | ||
611 | #define BM_TVENC_DACCTRL_RSRVD3 0x4000000 | ||
612 | #define BF_TVENC_DACCTRL_RSRVD3(v) (((v) << 26) & 0x4000000) | ||
613 | #define BP_TVENC_DACCTRL_RSRVD4 25 | ||
614 | #define BM_TVENC_DACCTRL_RSRVD4 0x2000000 | ||
615 | #define BF_TVENC_DACCTRL_RSRVD4(v) (((v) << 25) & 0x2000000) | ||
616 | #define BP_TVENC_DACCTRL_JACK1_DET_EN 24 | ||
617 | #define BM_TVENC_DACCTRL_JACK1_DET_EN 0x1000000 | ||
618 | #define BF_TVENC_DACCTRL_JACK1_DET_EN(v) (((v) << 24) & 0x1000000) | ||
619 | #define BP_TVENC_DACCTRL_TEST1 23 | ||
620 | #define BM_TVENC_DACCTRL_TEST1 0x800000 | ||
621 | #define BF_TVENC_DACCTRL_TEST1(v) (((v) << 23) & 0x800000) | ||
622 | #define BP_TVENC_DACCTRL_DISABLE_GND_DETECT 22 | ||
623 | #define BM_TVENC_DACCTRL_DISABLE_GND_DETECT 0x400000 | ||
624 | #define BF_TVENC_DACCTRL_DISABLE_GND_DETECT(v) (((v) << 22) & 0x400000) | ||
625 | #define BP_TVENC_DACCTRL_JACK_DIS_ADJ 20 | ||
626 | #define BM_TVENC_DACCTRL_JACK_DIS_ADJ 0x300000 | ||
627 | #define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v) (((v) << 20) & 0x300000) | ||
628 | #define BP_TVENC_DACCTRL_GAINDN 19 | ||
629 | #define BM_TVENC_DACCTRL_GAINDN 0x80000 | ||
630 | #define BF_TVENC_DACCTRL_GAINDN(v) (((v) << 19) & 0x80000) | ||
631 | #define BP_TVENC_DACCTRL_GAINUP 18 | ||
632 | #define BM_TVENC_DACCTRL_GAINUP 0x40000 | ||
633 | #define BF_TVENC_DACCTRL_GAINUP(v) (((v) << 18) & 0x40000) | ||
634 | #define BP_TVENC_DACCTRL_INVERT_CLK 17 | ||
635 | #define BM_TVENC_DACCTRL_INVERT_CLK 0x20000 | ||
636 | #define BF_TVENC_DACCTRL_INVERT_CLK(v) (((v) << 17) & 0x20000) | ||
637 | #define BP_TVENC_DACCTRL_SELECT_CLK 16 | ||
638 | #define BM_TVENC_DACCTRL_SELECT_CLK 0x10000 | ||
639 | #define BF_TVENC_DACCTRL_SELECT_CLK(v) (((v) << 16) & 0x10000) | ||
640 | #define BP_TVENC_DACCTRL_BYPASS_ACT_CASCODE 15 | ||
641 | #define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE 0x8000 | ||
642 | #define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v) (((v) << 15) & 0x8000) | ||
643 | #define BP_TVENC_DACCTRL_RSRVD5 14 | ||
644 | #define BM_TVENC_DACCTRL_RSRVD5 0x4000 | ||
645 | #define BF_TVENC_DACCTRL_RSRVD5(v) (((v) << 14) & 0x4000) | ||
646 | #define BP_TVENC_DACCTRL_RSRVD6 13 | ||
647 | #define BM_TVENC_DACCTRL_RSRVD6 0x2000 | ||
648 | #define BF_TVENC_DACCTRL_RSRVD6(v) (((v) << 13) & 0x2000) | ||
649 | #define BP_TVENC_DACCTRL_PWRUP1 12 | ||
650 | #define BM_TVENC_DACCTRL_PWRUP1 0x1000 | ||
651 | #define BF_TVENC_DACCTRL_PWRUP1(v) (((v) << 12) & 0x1000) | ||
652 | #define BP_TVENC_DACCTRL_WELL_TOVDD 11 | ||
653 | #define BM_TVENC_DACCTRL_WELL_TOVDD 0x800 | ||
654 | #define BF_TVENC_DACCTRL_WELL_TOVDD(v) (((v) << 11) & 0x800) | ||
655 | #define BP_TVENC_DACCTRL_RSRVD7 10 | ||
656 | #define BM_TVENC_DACCTRL_RSRVD7 0x400 | ||
657 | #define BF_TVENC_DACCTRL_RSRVD7(v) (((v) << 10) & 0x400) | ||
658 | #define BP_TVENC_DACCTRL_RSRVD8 9 | ||
659 | #define BM_TVENC_DACCTRL_RSRVD8 0x200 | ||
660 | #define BF_TVENC_DACCTRL_RSRVD8(v) (((v) << 9) & 0x200) | ||
661 | #define BP_TVENC_DACCTRL_DUMP_TOVDD1 8 | ||
662 | #define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x100 | ||
663 | #define BF_TVENC_DACCTRL_DUMP_TOVDD1(v) (((v) << 8) & 0x100) | ||
664 | #define BP_TVENC_DACCTRL_LOWER_SIGNAL 7 | ||
665 | #define BM_TVENC_DACCTRL_LOWER_SIGNAL 0x80 | ||
666 | #define BF_TVENC_DACCTRL_LOWER_SIGNAL(v) (((v) << 7) & 0x80) | ||
667 | #define BP_TVENC_DACCTRL_RVAL 4 | ||
668 | #define BM_TVENC_DACCTRL_RVAL 0x70 | ||
669 | #define BF_TVENC_DACCTRL_RVAL(v) (((v) << 4) & 0x70) | ||
670 | #define BP_TVENC_DACCTRL_NO_INTERNAL_TERM 3 | ||
671 | #define BM_TVENC_DACCTRL_NO_INTERNAL_TERM 0x8 | ||
672 | #define BF_TVENC_DACCTRL_NO_INTERNAL_TERM(v) (((v) << 3) & 0x8) | ||
673 | #define BP_TVENC_DACCTRL_HALF_CURRENT 2 | ||
674 | #define BM_TVENC_DACCTRL_HALF_CURRENT 0x4 | ||
675 | #define BF_TVENC_DACCTRL_HALF_CURRENT(v) (((v) << 2) & 0x4) | ||
676 | #define BP_TVENC_DACCTRL_CASC_ADJ 0 | ||
677 | #define BM_TVENC_DACCTRL_CASC_ADJ 0x3 | ||
678 | #define BF_TVENC_DACCTRL_CASC_ADJ(v) (((v) << 0) & 0x3) | ||
679 | |||
680 | /** | ||
681 | * Register: HW_TVENC_DACSTATUS | ||
682 | * Address: 0x1b0 | ||
683 | * SCT: yes | ||
684 | */ | ||
685 | #define HW_TVENC_DACSTATUS (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x0)) | ||
686 | #define HW_TVENC_DACSTATUS_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x4)) | ||
687 | #define HW_TVENC_DACSTATUS_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x8)) | ||
688 | #define HW_TVENC_DACSTATUS_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0xc)) | ||
689 | #define BP_TVENC_DACSTATUS_RSRVD1 13 | ||
690 | #define BM_TVENC_DACSTATUS_RSRVD1 0xffffe000 | ||
691 | #define BF_TVENC_DACSTATUS_RSRVD1(v) (((v) << 13) & 0xffffe000) | ||
692 | #define BP_TVENC_DACSTATUS_RSRVD2 12 | ||
693 | #define BM_TVENC_DACSTATUS_RSRVD2 0x1000 | ||
694 | #define BF_TVENC_DACSTATUS_RSRVD2(v) (((v) << 12) & 0x1000) | ||
695 | #define BP_TVENC_DACSTATUS_RSRVD3 11 | ||
696 | #define BM_TVENC_DACSTATUS_RSRVD3 0x800 | ||
697 | #define BF_TVENC_DACSTATUS_RSRVD3(v) (((v) << 11) & 0x800) | ||
698 | #define BP_TVENC_DACSTATUS_JACK1_DET_STATUS 10 | ||
699 | #define BM_TVENC_DACSTATUS_JACK1_DET_STATUS 0x400 | ||
700 | #define BF_TVENC_DACSTATUS_JACK1_DET_STATUS(v) (((v) << 10) & 0x400) | ||
701 | #define BP_TVENC_DACSTATUS_RSRVD4 9 | ||
702 | #define BM_TVENC_DACSTATUS_RSRVD4 0x200 | ||
703 | #define BF_TVENC_DACSTATUS_RSRVD4(v) (((v) << 9) & 0x200) | ||
704 | #define BP_TVENC_DACSTATUS_RSRVD5 8 | ||
705 | #define BM_TVENC_DACSTATUS_RSRVD5 0x100 | ||
706 | #define BF_TVENC_DACSTATUS_RSRVD5(v) (((v) << 8) & 0x100) | ||
707 | #define BP_TVENC_DACSTATUS_JACK1_GROUNDED 7 | ||
708 | #define BM_TVENC_DACSTATUS_JACK1_GROUNDED 0x80 | ||
709 | #define BF_TVENC_DACSTATUS_JACK1_GROUNDED(v) (((v) << 7) & 0x80) | ||
710 | #define BP_TVENC_DACSTATUS_RSRVD6 6 | ||
711 | #define BM_TVENC_DACSTATUS_RSRVD6 0x40 | ||
712 | #define BF_TVENC_DACSTATUS_RSRVD6(v) (((v) << 6) & 0x40) | ||
713 | #define BP_TVENC_DACSTATUS_RSRVD7 5 | ||
714 | #define BM_TVENC_DACSTATUS_RSRVD7 0x20 | ||
715 | #define BF_TVENC_DACSTATUS_RSRVD7(v) (((v) << 5) & 0x20) | ||
716 | #define BP_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ 4 | ||
717 | #define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ 0x10 | ||
718 | #define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v) (((v) << 4) & 0x10) | ||
719 | #define BP_TVENC_DACSTATUS_RSRVD8 3 | ||
720 | #define BM_TVENC_DACSTATUS_RSRVD8 0x8 | ||
721 | #define BF_TVENC_DACSTATUS_RSRVD8(v) (((v) << 3) & 0x8) | ||
722 | #define BP_TVENC_DACSTATUS_RSRVD9 2 | ||
723 | #define BM_TVENC_DACSTATUS_RSRVD9 0x4 | ||
724 | #define BF_TVENC_DACSTATUS_RSRVD9(v) (((v) << 2) & 0x4) | ||
725 | #define BP_TVENC_DACSTATUS_JACK1_DET_IRQ 1 | ||
726 | #define BM_TVENC_DACSTATUS_JACK1_DET_IRQ 0x2 | ||
727 | #define BF_TVENC_DACSTATUS_JACK1_DET_IRQ(v) (((v) << 1) & 0x2) | ||
728 | #define BP_TVENC_DACSTATUS_ENIRQ_JACK 0 | ||
729 | #define BM_TVENC_DACSTATUS_ENIRQ_JACK 0x1 | ||
730 | #define BF_TVENC_DACSTATUS_ENIRQ_JACK(v) (((v) << 0) & 0x1) | ||
731 | |||
732 | /** | ||
733 | * Register: HW_TVENC_VDACTEST | ||
734 | * Address: 0x1c0 | ||
735 | * SCT: yes | ||
736 | */ | ||
737 | #define HW_TVENC_VDACTEST (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x0)) | ||
738 | #define HW_TVENC_VDACTEST_SET (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x4)) | ||
739 | #define HW_TVENC_VDACTEST_CLR (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x8)) | ||
740 | #define HW_TVENC_VDACTEST_TOG (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0xc)) | ||
741 | #define BP_TVENC_VDACTEST_RSRVD1 14 | ||
742 | #define BM_TVENC_VDACTEST_RSRVD1 0xffffc000 | ||
743 | #define BF_TVENC_VDACTEST_RSRVD1(v) (((v) << 14) & 0xffffc000) | ||
744 | #define BP_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN 13 | ||
745 | #define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN 0x2000 | ||
746 | #define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v) (((v) << 13) & 0x2000) | ||
747 | #define BP_TVENC_VDACTEST_BYPASS_PIX_INT 12 | ||
748 | #define BM_TVENC_VDACTEST_BYPASS_PIX_INT 0x1000 | ||
749 | #define BF_TVENC_VDACTEST_BYPASS_PIX_INT(v) (((v) << 12) & 0x1000) | ||
750 | #define BP_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP 11 | ||
751 | #define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP 0x800 | ||
752 | #define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v) (((v) << 11) & 0x800) | ||
753 | #define BP_TVENC_VDACTEST_TEST_FIFO_FULL 10 | ||
754 | #define BM_TVENC_VDACTEST_TEST_FIFO_FULL 0x400 | ||
755 | #define BF_TVENC_VDACTEST_TEST_FIFO_FULL(v) (((v) << 10) & 0x400) | ||
756 | #define BP_TVENC_VDACTEST_DATA 0 | ||
757 | #define BM_TVENC_VDACTEST_DATA 0x3ff | ||
758 | #define BF_TVENC_VDACTEST_DATA(v) (((v) << 0) & 0x3ff) | ||
759 | |||
760 | /** | ||
761 | * Register: HW_TVENC_VERSION | ||
762 | * Address: 0x1d0 | ||
763 | * SCT: no | ||
764 | */ | ||
765 | #define HW_TVENC_VERSION (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1d0)) | ||
766 | #define BP_TVENC_VERSION_MAJOR 24 | ||
767 | #define BM_TVENC_VERSION_MAJOR 0xff000000 | ||
768 | #define BF_TVENC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
769 | #define BP_TVENC_VERSION_MINOR 16 | ||
770 | #define BM_TVENC_VERSION_MINOR 0xff0000 | ||
771 | #define BF_TVENC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
772 | #define BP_TVENC_VERSION_STEP 0 | ||
773 | #define BM_TVENC_VERSION_STEP 0xffff | ||
774 | #define BF_TVENC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
775 | |||
776 | #endif /* __HEADERGEN__IMX233__TVENC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h b/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h new file mode 100644 index 0000000000..11cf8316a6 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h | |||
@@ -0,0 +1,497 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__UARTAPP__H__ | ||
24 | #define __HEADERGEN__IMX233__UARTAPP__H__ | ||
25 | |||
26 | #define REGS_UARTAPP_BASE(i) ((i) == 1 ? 0x8006c000 : 0x8006e000) | ||
27 | |||
28 | #define REGS_UARTAPP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_UARTAPP_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_UARTAPP_CTRL0(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x0)) | ||
36 | #define HW_UARTAPP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x4)) | ||
37 | #define HW_UARTAPP_CTRL0_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x8)) | ||
38 | #define HW_UARTAPP_CTRL0_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0xc)) | ||
39 | #define BP_UARTAPP_CTRL0_SFTRST 31 | ||
40 | #define BM_UARTAPP_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_UARTAPP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_UARTAPP_CTRL0_CLKGATE 30 | ||
43 | #define BM_UARTAPP_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_UARTAPP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_UARTAPP_CTRL0_RUN 29 | ||
46 | #define BM_UARTAPP_CTRL0_RUN 0x20000000 | ||
47 | #define BF_UARTAPP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_UARTAPP_CTRL0_RX_SOURCE 28 | ||
49 | #define BM_UARTAPP_CTRL0_RX_SOURCE 0x10000000 | ||
50 | #define BF_UARTAPP_CTRL0_RX_SOURCE(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_UARTAPP_CTRL0_RXTO_ENABLE 27 | ||
52 | #define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x8000000 | ||
53 | #define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_UARTAPP_CTRL0_RXTIMEOUT 16 | ||
55 | #define BM_UARTAPP_CTRL0_RXTIMEOUT 0x7ff0000 | ||
56 | #define BF_UARTAPP_CTRL0_RXTIMEOUT(v) (((v) << 16) & 0x7ff0000) | ||
57 | #define BP_UARTAPP_CTRL0_XFER_COUNT 0 | ||
58 | #define BM_UARTAPP_CTRL0_XFER_COUNT 0xffff | ||
59 | #define BF_UARTAPP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
60 | |||
61 | /** | ||
62 | * Register: HW_UARTAPP_CTRL1 | ||
63 | * Address: 0x10 | ||
64 | * SCT: yes | ||
65 | */ | ||
66 | #define HW_UARTAPP_CTRL1(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x0)) | ||
67 | #define HW_UARTAPP_CTRL1_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x4)) | ||
68 | #define HW_UARTAPP_CTRL1_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x8)) | ||
69 | #define HW_UARTAPP_CTRL1_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0xc)) | ||
70 | #define BP_UARTAPP_CTRL1_RSVD2 29 | ||
71 | #define BM_UARTAPP_CTRL1_RSVD2 0xe0000000 | ||
72 | #define BF_UARTAPP_CTRL1_RSVD2(v) (((v) << 29) & 0xe0000000) | ||
73 | #define BP_UARTAPP_CTRL1_RUN 28 | ||
74 | #define BM_UARTAPP_CTRL1_RUN 0x10000000 | ||
75 | #define BF_UARTAPP_CTRL1_RUN(v) (((v) << 28) & 0x10000000) | ||
76 | #define BP_UARTAPP_CTRL1_RSVD1 16 | ||
77 | #define BM_UARTAPP_CTRL1_RSVD1 0xfff0000 | ||
78 | #define BF_UARTAPP_CTRL1_RSVD1(v) (((v) << 16) & 0xfff0000) | ||
79 | #define BP_UARTAPP_CTRL1_XFER_COUNT 0 | ||
80 | #define BM_UARTAPP_CTRL1_XFER_COUNT 0xffff | ||
81 | #define BF_UARTAPP_CTRL1_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_UARTAPP_CTRL2 | ||
85 | * Address: 0x20 | ||
86 | * SCT: yes | ||
87 | */ | ||
88 | #define HW_UARTAPP_CTRL2(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x0)) | ||
89 | #define HW_UARTAPP_CTRL2_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x4)) | ||
90 | #define HW_UARTAPP_CTRL2_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x8)) | ||
91 | #define HW_UARTAPP_CTRL2_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0xc)) | ||
92 | #define BP_UARTAPP_CTRL2_INVERT_RTS 31 | ||
93 | #define BM_UARTAPP_CTRL2_INVERT_RTS 0x80000000 | ||
94 | #define BF_UARTAPP_CTRL2_INVERT_RTS(v) (((v) << 31) & 0x80000000) | ||
95 | #define BP_UARTAPP_CTRL2_INVERT_CTS 30 | ||
96 | #define BM_UARTAPP_CTRL2_INVERT_CTS 0x40000000 | ||
97 | #define BF_UARTAPP_CTRL2_INVERT_CTS(v) (((v) << 30) & 0x40000000) | ||
98 | #define BP_UARTAPP_CTRL2_INVERT_TX 29 | ||
99 | #define BM_UARTAPP_CTRL2_INVERT_TX 0x20000000 | ||
100 | #define BF_UARTAPP_CTRL2_INVERT_TX(v) (((v) << 29) & 0x20000000) | ||
101 | #define BP_UARTAPP_CTRL2_INVERT_RX 28 | ||
102 | #define BM_UARTAPP_CTRL2_INVERT_RX 0x10000000 | ||
103 | #define BF_UARTAPP_CTRL2_INVERT_RX(v) (((v) << 28) & 0x10000000) | ||
104 | #define BP_UARTAPP_CTRL2_RTS_SEMAPHORE 27 | ||
105 | #define BM_UARTAPP_CTRL2_RTS_SEMAPHORE 0x8000000 | ||
106 | #define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v) (((v) << 27) & 0x8000000) | ||
107 | #define BP_UARTAPP_CTRL2_DMAONERR 26 | ||
108 | #define BM_UARTAPP_CTRL2_DMAONERR 0x4000000 | ||
109 | #define BF_UARTAPP_CTRL2_DMAONERR(v) (((v) << 26) & 0x4000000) | ||
110 | #define BP_UARTAPP_CTRL2_TXDMAE 25 | ||
111 | #define BM_UARTAPP_CTRL2_TXDMAE 0x2000000 | ||
112 | #define BF_UARTAPP_CTRL2_TXDMAE(v) (((v) << 25) & 0x2000000) | ||
113 | #define BP_UARTAPP_CTRL2_RXDMAE 24 | ||
114 | #define BM_UARTAPP_CTRL2_RXDMAE 0x1000000 | ||
115 | #define BF_UARTAPP_CTRL2_RXDMAE(v) (((v) << 24) & 0x1000000) | ||
116 | #define BP_UARTAPP_CTRL2_RSVD2 23 | ||
117 | #define BM_UARTAPP_CTRL2_RSVD2 0x800000 | ||
118 | #define BF_UARTAPP_CTRL2_RSVD2(v) (((v) << 23) & 0x800000) | ||
119 | #define BP_UARTAPP_CTRL2_RXIFLSEL 20 | ||
120 | #define BM_UARTAPP_CTRL2_RXIFLSEL 0x700000 | ||
121 | #define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 | ||
122 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 | ||
123 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 | ||
124 | #define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 | ||
125 | #define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
126 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 | ||
127 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 | ||
128 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 | ||
129 | #define BF_UARTAPP_CTRL2_RXIFLSEL(v) (((v) << 20) & 0x700000) | ||
130 | #define BF_UARTAPP_CTRL2_RXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000) | ||
131 | #define BP_UARTAPP_CTRL2_RSVD3 19 | ||
132 | #define BM_UARTAPP_CTRL2_RSVD3 0x80000 | ||
133 | #define BF_UARTAPP_CTRL2_RSVD3(v) (((v) << 19) & 0x80000) | ||
134 | #define BP_UARTAPP_CTRL2_TXIFLSEL 16 | ||
135 | #define BM_UARTAPP_CTRL2_TXIFLSEL 0x70000 | ||
136 | #define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 | ||
137 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 | ||
138 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 | ||
139 | #define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 | ||
140 | #define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
141 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 | ||
142 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 | ||
143 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 | ||
144 | #define BF_UARTAPP_CTRL2_TXIFLSEL(v) (((v) << 16) & 0x70000) | ||
145 | #define BF_UARTAPP_CTRL2_TXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000) | ||
146 | #define BP_UARTAPP_CTRL2_CTSEN 15 | ||
147 | #define BM_UARTAPP_CTRL2_CTSEN 0x8000 | ||
148 | #define BF_UARTAPP_CTRL2_CTSEN(v) (((v) << 15) & 0x8000) | ||
149 | #define BP_UARTAPP_CTRL2_RTSEN 14 | ||
150 | #define BM_UARTAPP_CTRL2_RTSEN 0x4000 | ||
151 | #define BF_UARTAPP_CTRL2_RTSEN(v) (((v) << 14) & 0x4000) | ||
152 | #define BP_UARTAPP_CTRL2_OUT2 13 | ||
153 | #define BM_UARTAPP_CTRL2_OUT2 0x2000 | ||
154 | #define BF_UARTAPP_CTRL2_OUT2(v) (((v) << 13) & 0x2000) | ||
155 | #define BP_UARTAPP_CTRL2_OUT1 12 | ||
156 | #define BM_UARTAPP_CTRL2_OUT1 0x1000 | ||
157 | #define BF_UARTAPP_CTRL2_OUT1(v) (((v) << 12) & 0x1000) | ||
158 | #define BP_UARTAPP_CTRL2_RTS 11 | ||
159 | #define BM_UARTAPP_CTRL2_RTS 0x800 | ||
160 | #define BF_UARTAPP_CTRL2_RTS(v) (((v) << 11) & 0x800) | ||
161 | #define BP_UARTAPP_CTRL2_DTR 10 | ||
162 | #define BM_UARTAPP_CTRL2_DTR 0x400 | ||
163 | #define BF_UARTAPP_CTRL2_DTR(v) (((v) << 10) & 0x400) | ||
164 | #define BP_UARTAPP_CTRL2_RXE 9 | ||
165 | #define BM_UARTAPP_CTRL2_RXE 0x200 | ||
166 | #define BF_UARTAPP_CTRL2_RXE(v) (((v) << 9) & 0x200) | ||
167 | #define BP_UARTAPP_CTRL2_TXE 8 | ||
168 | #define BM_UARTAPP_CTRL2_TXE 0x100 | ||
169 | #define BF_UARTAPP_CTRL2_TXE(v) (((v) << 8) & 0x100) | ||
170 | #define BP_UARTAPP_CTRL2_LBE 7 | ||
171 | #define BM_UARTAPP_CTRL2_LBE 0x80 | ||
172 | #define BF_UARTAPP_CTRL2_LBE(v) (((v) << 7) & 0x80) | ||
173 | #define BP_UARTAPP_CTRL2_USE_LCR2 6 | ||
174 | #define BM_UARTAPP_CTRL2_USE_LCR2 0x40 | ||
175 | #define BF_UARTAPP_CTRL2_USE_LCR2(v) (((v) << 6) & 0x40) | ||
176 | #define BP_UARTAPP_CTRL2_RSVD4 3 | ||
177 | #define BM_UARTAPP_CTRL2_RSVD4 0x38 | ||
178 | #define BF_UARTAPP_CTRL2_RSVD4(v) (((v) << 3) & 0x38) | ||
179 | #define BP_UARTAPP_CTRL2_SIRLP 2 | ||
180 | #define BM_UARTAPP_CTRL2_SIRLP 0x4 | ||
181 | #define BF_UARTAPP_CTRL2_SIRLP(v) (((v) << 2) & 0x4) | ||
182 | #define BP_UARTAPP_CTRL2_SIREN 1 | ||
183 | #define BM_UARTAPP_CTRL2_SIREN 0x2 | ||
184 | #define BF_UARTAPP_CTRL2_SIREN(v) (((v) << 1) & 0x2) | ||
185 | #define BP_UARTAPP_CTRL2_UARTEN 0 | ||
186 | #define BM_UARTAPP_CTRL2_UARTEN 0x1 | ||
187 | #define BF_UARTAPP_CTRL2_UARTEN(v) (((v) << 0) & 0x1) | ||
188 | |||
189 | /** | ||
190 | * Register: HW_UARTAPP_LINECTRL | ||
191 | * Address: 0x30 | ||
192 | * SCT: yes | ||
193 | */ | ||
194 | #define HW_UARTAPP_LINECTRL(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x0)) | ||
195 | #define HW_UARTAPP_LINECTRL_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x4)) | ||
196 | #define HW_UARTAPP_LINECTRL_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x8)) | ||
197 | #define HW_UARTAPP_LINECTRL_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0xc)) | ||
198 | #define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 | ||
199 | #define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xffff0000 | ||
200 | #define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
201 | #define BP_UARTAPP_LINECTRL_RSVD 14 | ||
202 | #define BM_UARTAPP_LINECTRL_RSVD 0xc000 | ||
203 | #define BF_UARTAPP_LINECTRL_RSVD(v) (((v) << 14) & 0xc000) | ||
204 | #define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 | ||
205 | #define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x3f00 | ||
206 | #define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
207 | #define BP_UARTAPP_LINECTRL_SPS 7 | ||
208 | #define BM_UARTAPP_LINECTRL_SPS 0x80 | ||
209 | #define BF_UARTAPP_LINECTRL_SPS(v) (((v) << 7) & 0x80) | ||
210 | #define BP_UARTAPP_LINECTRL_WLEN 5 | ||
211 | #define BM_UARTAPP_LINECTRL_WLEN 0x60 | ||
212 | #define BF_UARTAPP_LINECTRL_WLEN(v) (((v) << 5) & 0x60) | ||
213 | #define BP_UARTAPP_LINECTRL_FEN 4 | ||
214 | #define BM_UARTAPP_LINECTRL_FEN 0x10 | ||
215 | #define BF_UARTAPP_LINECTRL_FEN(v) (((v) << 4) & 0x10) | ||
216 | #define BP_UARTAPP_LINECTRL_STP2 3 | ||
217 | #define BM_UARTAPP_LINECTRL_STP2 0x8 | ||
218 | #define BF_UARTAPP_LINECTRL_STP2(v) (((v) << 3) & 0x8) | ||
219 | #define BP_UARTAPP_LINECTRL_EPS 2 | ||
220 | #define BM_UARTAPP_LINECTRL_EPS 0x4 | ||
221 | #define BF_UARTAPP_LINECTRL_EPS(v) (((v) << 2) & 0x4) | ||
222 | #define BP_UARTAPP_LINECTRL_PEN 1 | ||
223 | #define BM_UARTAPP_LINECTRL_PEN 0x2 | ||
224 | #define BF_UARTAPP_LINECTRL_PEN(v) (((v) << 1) & 0x2) | ||
225 | #define BP_UARTAPP_LINECTRL_BRK 0 | ||
226 | #define BM_UARTAPP_LINECTRL_BRK 0x1 | ||
227 | #define BF_UARTAPP_LINECTRL_BRK(v) (((v) << 0) & 0x1) | ||
228 | |||
229 | /** | ||
230 | * Register: HW_UARTAPP_LINECTRL2 | ||
231 | * Address: 0x40 | ||
232 | * SCT: yes | ||
233 | */ | ||
234 | #define HW_UARTAPP_LINECTRL2(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x0)) | ||
235 | #define HW_UARTAPP_LINECTRL2_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x4)) | ||
236 | #define HW_UARTAPP_LINECTRL2_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x8)) | ||
237 | #define HW_UARTAPP_LINECTRL2_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0xc)) | ||
238 | #define BP_UARTAPP_LINECTRL2_BAUD_DIVINT 16 | ||
239 | #define BM_UARTAPP_LINECTRL2_BAUD_DIVINT 0xffff0000 | ||
240 | #define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
241 | #define BP_UARTAPP_LINECTRL2_RSVD 14 | ||
242 | #define BM_UARTAPP_LINECTRL2_RSVD 0xc000 | ||
243 | #define BF_UARTAPP_LINECTRL2_RSVD(v) (((v) << 14) & 0xc000) | ||
244 | #define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC 8 | ||
245 | #define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC 0x3f00 | ||
246 | #define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
247 | #define BP_UARTAPP_LINECTRL2_SPS 7 | ||
248 | #define BM_UARTAPP_LINECTRL2_SPS 0x80 | ||
249 | #define BF_UARTAPP_LINECTRL2_SPS(v) (((v) << 7) & 0x80) | ||
250 | #define BP_UARTAPP_LINECTRL2_WLEN 5 | ||
251 | #define BM_UARTAPP_LINECTRL2_WLEN 0x60 | ||
252 | #define BF_UARTAPP_LINECTRL2_WLEN(v) (((v) << 5) & 0x60) | ||
253 | #define BP_UARTAPP_LINECTRL2_FEN 4 | ||
254 | #define BM_UARTAPP_LINECTRL2_FEN 0x10 | ||
255 | #define BF_UARTAPP_LINECTRL2_FEN(v) (((v) << 4) & 0x10) | ||
256 | #define BP_UARTAPP_LINECTRL2_STP2 3 | ||
257 | #define BM_UARTAPP_LINECTRL2_STP2 0x8 | ||
258 | #define BF_UARTAPP_LINECTRL2_STP2(v) (((v) << 3) & 0x8) | ||
259 | #define BP_UARTAPP_LINECTRL2_EPS 2 | ||
260 | #define BM_UARTAPP_LINECTRL2_EPS 0x4 | ||
261 | #define BF_UARTAPP_LINECTRL2_EPS(v) (((v) << 2) & 0x4) | ||
262 | #define BP_UARTAPP_LINECTRL2_PEN 1 | ||
263 | #define BM_UARTAPP_LINECTRL2_PEN 0x2 | ||
264 | #define BF_UARTAPP_LINECTRL2_PEN(v) (((v) << 1) & 0x2) | ||
265 | #define BP_UARTAPP_LINECTRL2_RSVD1 0 | ||
266 | #define BM_UARTAPP_LINECTRL2_RSVD1 0x1 | ||
267 | #define BF_UARTAPP_LINECTRL2_RSVD1(v) (((v) << 0) & 0x1) | ||
268 | |||
269 | /** | ||
270 | * Register: HW_UARTAPP_INTR | ||
271 | * Address: 0x50 | ||
272 | * SCT: yes | ||
273 | */ | ||
274 | #define HW_UARTAPP_INTR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x0)) | ||
275 | #define HW_UARTAPP_INTR_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x4)) | ||
276 | #define HW_UARTAPP_INTR_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x8)) | ||
277 | #define HW_UARTAPP_INTR_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0xc)) | ||
278 | #define BP_UARTAPP_INTR_RSVD1 27 | ||
279 | #define BM_UARTAPP_INTR_RSVD1 0xf8000000 | ||
280 | #define BF_UARTAPP_INTR_RSVD1(v) (((v) << 27) & 0xf8000000) | ||
281 | #define BP_UARTAPP_INTR_OEIEN 26 | ||
282 | #define BM_UARTAPP_INTR_OEIEN 0x4000000 | ||
283 | #define BF_UARTAPP_INTR_OEIEN(v) (((v) << 26) & 0x4000000) | ||
284 | #define BP_UARTAPP_INTR_BEIEN 25 | ||
285 | #define BM_UARTAPP_INTR_BEIEN 0x2000000 | ||
286 | #define BF_UARTAPP_INTR_BEIEN(v) (((v) << 25) & 0x2000000) | ||
287 | #define BP_UARTAPP_INTR_PEIEN 24 | ||
288 | #define BM_UARTAPP_INTR_PEIEN 0x1000000 | ||
289 | #define BF_UARTAPP_INTR_PEIEN(v) (((v) << 24) & 0x1000000) | ||
290 | #define BP_UARTAPP_INTR_FEIEN 23 | ||
291 | #define BM_UARTAPP_INTR_FEIEN 0x800000 | ||
292 | #define BF_UARTAPP_INTR_FEIEN(v) (((v) << 23) & 0x800000) | ||
293 | #define BP_UARTAPP_INTR_RTIEN 22 | ||
294 | #define BM_UARTAPP_INTR_RTIEN 0x400000 | ||
295 | #define BF_UARTAPP_INTR_RTIEN(v) (((v) << 22) & 0x400000) | ||
296 | #define BP_UARTAPP_INTR_TXIEN 21 | ||
297 | #define BM_UARTAPP_INTR_TXIEN 0x200000 | ||
298 | #define BF_UARTAPP_INTR_TXIEN(v) (((v) << 21) & 0x200000) | ||
299 | #define BP_UARTAPP_INTR_RXIEN 20 | ||
300 | #define BM_UARTAPP_INTR_RXIEN 0x100000 | ||
301 | #define BF_UARTAPP_INTR_RXIEN(v) (((v) << 20) & 0x100000) | ||
302 | #define BP_UARTAPP_INTR_DSRMIEN 19 | ||
303 | #define BM_UARTAPP_INTR_DSRMIEN 0x80000 | ||
304 | #define BF_UARTAPP_INTR_DSRMIEN(v) (((v) << 19) & 0x80000) | ||
305 | #define BP_UARTAPP_INTR_DCDMIEN 18 | ||
306 | #define BM_UARTAPP_INTR_DCDMIEN 0x40000 | ||
307 | #define BF_UARTAPP_INTR_DCDMIEN(v) (((v) << 18) & 0x40000) | ||
308 | #define BP_UARTAPP_INTR_CTSMIEN 17 | ||
309 | #define BM_UARTAPP_INTR_CTSMIEN 0x20000 | ||
310 | #define BF_UARTAPP_INTR_CTSMIEN(v) (((v) << 17) & 0x20000) | ||
311 | #define BP_UARTAPP_INTR_RIMIEN 16 | ||
312 | #define BM_UARTAPP_INTR_RIMIEN 0x10000 | ||
313 | #define BF_UARTAPP_INTR_RIMIEN(v) (((v) << 16) & 0x10000) | ||
314 | #define BP_UARTAPP_INTR_RSVD2 11 | ||
315 | #define BM_UARTAPP_INTR_RSVD2 0xf800 | ||
316 | #define BF_UARTAPP_INTR_RSVD2(v) (((v) << 11) & 0xf800) | ||
317 | #define BP_UARTAPP_INTR_OEIS 10 | ||
318 | #define BM_UARTAPP_INTR_OEIS 0x400 | ||
319 | #define BF_UARTAPP_INTR_OEIS(v) (((v) << 10) & 0x400) | ||
320 | #define BP_UARTAPP_INTR_BEIS 9 | ||
321 | #define BM_UARTAPP_INTR_BEIS 0x200 | ||
322 | #define BF_UARTAPP_INTR_BEIS(v) (((v) << 9) & 0x200) | ||
323 | #define BP_UARTAPP_INTR_PEIS 8 | ||
324 | #define BM_UARTAPP_INTR_PEIS 0x100 | ||
325 | #define BF_UARTAPP_INTR_PEIS(v) (((v) << 8) & 0x100) | ||
326 | #define BP_UARTAPP_INTR_FEIS 7 | ||
327 | #define BM_UARTAPP_INTR_FEIS 0x80 | ||
328 | #define BF_UARTAPP_INTR_FEIS(v) (((v) << 7) & 0x80) | ||
329 | #define BP_UARTAPP_INTR_RTIS 6 | ||
330 | #define BM_UARTAPP_INTR_RTIS 0x40 | ||
331 | #define BF_UARTAPP_INTR_RTIS(v) (((v) << 6) & 0x40) | ||
332 | #define BP_UARTAPP_INTR_TXIS 5 | ||
333 | #define BM_UARTAPP_INTR_TXIS 0x20 | ||
334 | #define BF_UARTAPP_INTR_TXIS(v) (((v) << 5) & 0x20) | ||
335 | #define BP_UARTAPP_INTR_RXIS 4 | ||
336 | #define BM_UARTAPP_INTR_RXIS 0x10 | ||
337 | #define BF_UARTAPP_INTR_RXIS(v) (((v) << 4) & 0x10) | ||
338 | #define BP_UARTAPP_INTR_DSRMIS 3 | ||
339 | #define BM_UARTAPP_INTR_DSRMIS 0x8 | ||
340 | #define BF_UARTAPP_INTR_DSRMIS(v) (((v) << 3) & 0x8) | ||
341 | #define BP_UARTAPP_INTR_DCDMIS 2 | ||
342 | #define BM_UARTAPP_INTR_DCDMIS 0x4 | ||
343 | #define BF_UARTAPP_INTR_DCDMIS(v) (((v) << 2) & 0x4) | ||
344 | #define BP_UARTAPP_INTR_CTSMIS 1 | ||
345 | #define BM_UARTAPP_INTR_CTSMIS 0x2 | ||
346 | #define BF_UARTAPP_INTR_CTSMIS(v) (((v) << 1) & 0x2) | ||
347 | #define BP_UARTAPP_INTR_RIMIS 0 | ||
348 | #define BM_UARTAPP_INTR_RIMIS 0x1 | ||
349 | #define BF_UARTAPP_INTR_RIMIS(v) (((v) << 0) & 0x1) | ||
350 | |||
351 | /** | ||
352 | * Register: HW_UARTAPP_DATA | ||
353 | * Address: 0x60 | ||
354 | * SCT: no | ||
355 | */ | ||
356 | #define HW_UARTAPP_DATA(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x60)) | ||
357 | #define BP_UARTAPP_DATA_DATA 0 | ||
358 | #define BM_UARTAPP_DATA_DATA 0xffffffff | ||
359 | #define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
360 | |||
361 | /** | ||
362 | * Register: HW_UARTAPP_STAT | ||
363 | * Address: 0x70 | ||
364 | * SCT: no | ||
365 | */ | ||
366 | #define HW_UARTAPP_STAT(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x70)) | ||
367 | #define BP_UARTAPP_STAT_PRESENT 31 | ||
368 | #define BM_UARTAPP_STAT_PRESENT 0x80000000 | ||
369 | #define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 | ||
370 | #define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 | ||
371 | #define BF_UARTAPP_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
372 | #define BF_UARTAPP_STAT_PRESENT_V(v) ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000) | ||
373 | #define BP_UARTAPP_STAT_HISPEED 30 | ||
374 | #define BM_UARTAPP_STAT_HISPEED 0x40000000 | ||
375 | #define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 | ||
376 | #define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 | ||
377 | #define BF_UARTAPP_STAT_HISPEED(v) (((v) << 30) & 0x40000000) | ||
378 | #define BF_UARTAPP_STAT_HISPEED_V(v) ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000) | ||
379 | #define BP_UARTAPP_STAT_BUSY 29 | ||
380 | #define BM_UARTAPP_STAT_BUSY 0x20000000 | ||
381 | #define BF_UARTAPP_STAT_BUSY(v) (((v) << 29) & 0x20000000) | ||
382 | #define BP_UARTAPP_STAT_CTS 28 | ||
383 | #define BM_UARTAPP_STAT_CTS 0x10000000 | ||
384 | #define BF_UARTAPP_STAT_CTS(v) (((v) << 28) & 0x10000000) | ||
385 | #define BP_UARTAPP_STAT_TXFE 27 | ||
386 | #define BM_UARTAPP_STAT_TXFE 0x8000000 | ||
387 | #define BF_UARTAPP_STAT_TXFE(v) (((v) << 27) & 0x8000000) | ||
388 | #define BP_UARTAPP_STAT_RXFF 26 | ||
389 | #define BM_UARTAPP_STAT_RXFF 0x4000000 | ||
390 | #define BF_UARTAPP_STAT_RXFF(v) (((v) << 26) & 0x4000000) | ||
391 | #define BP_UARTAPP_STAT_TXFF 25 | ||
392 | #define BM_UARTAPP_STAT_TXFF 0x2000000 | ||
393 | #define BF_UARTAPP_STAT_TXFF(v) (((v) << 25) & 0x2000000) | ||
394 | #define BP_UARTAPP_STAT_RXFE 24 | ||
395 | #define BM_UARTAPP_STAT_RXFE 0x1000000 | ||
396 | #define BF_UARTAPP_STAT_RXFE(v) (((v) << 24) & 0x1000000) | ||
397 | #define BP_UARTAPP_STAT_RXBYTE_INVALID 20 | ||
398 | #define BM_UARTAPP_STAT_RXBYTE_INVALID 0xf00000 | ||
399 | #define BF_UARTAPP_STAT_RXBYTE_INVALID(v) (((v) << 20) & 0xf00000) | ||
400 | #define BP_UARTAPP_STAT_OERR 19 | ||
401 | #define BM_UARTAPP_STAT_OERR 0x80000 | ||
402 | #define BF_UARTAPP_STAT_OERR(v) (((v) << 19) & 0x80000) | ||
403 | #define BP_UARTAPP_STAT_BERR 18 | ||
404 | #define BM_UARTAPP_STAT_BERR 0x40000 | ||
405 | #define BF_UARTAPP_STAT_BERR(v) (((v) << 18) & 0x40000) | ||
406 | #define BP_UARTAPP_STAT_PERR 17 | ||
407 | #define BM_UARTAPP_STAT_PERR 0x20000 | ||
408 | #define BF_UARTAPP_STAT_PERR(v) (((v) << 17) & 0x20000) | ||
409 | #define BP_UARTAPP_STAT_FERR 16 | ||
410 | #define BM_UARTAPP_STAT_FERR 0x10000 | ||
411 | #define BF_UARTAPP_STAT_FERR(v) (((v) << 16) & 0x10000) | ||
412 | #define BP_UARTAPP_STAT_RXCOUNT 0 | ||
413 | #define BM_UARTAPP_STAT_RXCOUNT 0xffff | ||
414 | #define BF_UARTAPP_STAT_RXCOUNT(v) (((v) << 0) & 0xffff) | ||
415 | |||
416 | /** | ||
417 | * Register: HW_UARTAPP_DEBUG | ||
418 | * Address: 0x80 | ||
419 | * SCT: no | ||
420 | */ | ||
421 | #define HW_UARTAPP_DEBUG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x80)) | ||
422 | #define BP_UARTAPP_DEBUG_RXIBAUD_DIV 16 | ||
423 | #define BM_UARTAPP_DEBUG_RXIBAUD_DIV 0xffff0000 | ||
424 | #define BF_UARTAPP_DEBUG_RXIBAUD_DIV(v) (((v) << 16) & 0xffff0000) | ||
425 | #define BP_UARTAPP_DEBUG_RXFBAUD_DIV 10 | ||
426 | #define BM_UARTAPP_DEBUG_RXFBAUD_DIV 0xfc00 | ||
427 | #define BF_UARTAPP_DEBUG_RXFBAUD_DIV(v) (((v) << 10) & 0xfc00) | ||
428 | #define BP_UARTAPP_DEBUG_RSVD1 6 | ||
429 | #define BM_UARTAPP_DEBUG_RSVD1 0x3c0 | ||
430 | #define BF_UARTAPP_DEBUG_RSVD1(v) (((v) << 6) & 0x3c0) | ||
431 | #define BP_UARTAPP_DEBUG_TXDMARUN 5 | ||
432 | #define BM_UARTAPP_DEBUG_TXDMARUN 0x20 | ||
433 | #define BF_UARTAPP_DEBUG_TXDMARUN(v) (((v) << 5) & 0x20) | ||
434 | #define BP_UARTAPP_DEBUG_RXDMARUN 4 | ||
435 | #define BM_UARTAPP_DEBUG_RXDMARUN 0x10 | ||
436 | #define BF_UARTAPP_DEBUG_RXDMARUN(v) (((v) << 4) & 0x10) | ||
437 | #define BP_UARTAPP_DEBUG_TXCMDEND 3 | ||
438 | #define BM_UARTAPP_DEBUG_TXCMDEND 0x8 | ||
439 | #define BF_UARTAPP_DEBUG_TXCMDEND(v) (((v) << 3) & 0x8) | ||
440 | #define BP_UARTAPP_DEBUG_RXCMDEND 2 | ||
441 | #define BM_UARTAPP_DEBUG_RXCMDEND 0x4 | ||
442 | #define BF_UARTAPP_DEBUG_RXCMDEND(v) (((v) << 2) & 0x4) | ||
443 | #define BP_UARTAPP_DEBUG_TXDMARQ 1 | ||
444 | #define BM_UARTAPP_DEBUG_TXDMARQ 0x2 | ||
445 | #define BF_UARTAPP_DEBUG_TXDMARQ(v) (((v) << 1) & 0x2) | ||
446 | #define BP_UARTAPP_DEBUG_RXDMARQ 0 | ||
447 | #define BM_UARTAPP_DEBUG_RXDMARQ 0x1 | ||
448 | #define BF_UARTAPP_DEBUG_RXDMARQ(v) (((v) << 0) & 0x1) | ||
449 | |||
450 | /** | ||
451 | * Register: HW_UARTAPP_VERSION | ||
452 | * Address: 0x90 | ||
453 | * SCT: no | ||
454 | */ | ||
455 | #define HW_UARTAPP_VERSION(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x90)) | ||
456 | #define BP_UARTAPP_VERSION_MAJOR 24 | ||
457 | #define BM_UARTAPP_VERSION_MAJOR 0xff000000 | ||
458 | #define BF_UARTAPP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
459 | #define BP_UARTAPP_VERSION_MINOR 16 | ||
460 | #define BM_UARTAPP_VERSION_MINOR 0xff0000 | ||
461 | #define BF_UARTAPP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
462 | #define BP_UARTAPP_VERSION_STEP 0 | ||
463 | #define BM_UARTAPP_VERSION_STEP 0xffff | ||
464 | #define BF_UARTAPP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
465 | |||
466 | /** | ||
467 | * Register: HW_UARTAPP_AUTOBAUD | ||
468 | * Address: 0xa0 | ||
469 | * SCT: no | ||
470 | */ | ||
471 | #define HW_UARTAPP_AUTOBAUD(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0xa0)) | ||
472 | #define BP_UARTAPP_AUTOBAUD_REFCHAR1 24 | ||
473 | #define BM_UARTAPP_AUTOBAUD_REFCHAR1 0xff000000 | ||
474 | #define BF_UARTAPP_AUTOBAUD_REFCHAR1(v) (((v) << 24) & 0xff000000) | ||
475 | #define BP_UARTAPP_AUTOBAUD_REFCHAR0 16 | ||
476 | #define BM_UARTAPP_AUTOBAUD_REFCHAR0 0xff0000 | ||
477 | #define BF_UARTAPP_AUTOBAUD_REFCHAR0(v) (((v) << 16) & 0xff0000) | ||
478 | #define BP_UARTAPP_AUTOBAUD_RSVD1 5 | ||
479 | #define BM_UARTAPP_AUTOBAUD_RSVD1 0xffe0 | ||
480 | #define BF_UARTAPP_AUTOBAUD_RSVD1(v) (((v) << 5) & 0xffe0) | ||
481 | #define BP_UARTAPP_AUTOBAUD_UPDATE_TX 4 | ||
482 | #define BM_UARTAPP_AUTOBAUD_UPDATE_TX 0x10 | ||
483 | #define BF_UARTAPP_AUTOBAUD_UPDATE_TX(v) (((v) << 4) & 0x10) | ||
484 | #define BP_UARTAPP_AUTOBAUD_TWO_REF_CHARS 3 | ||
485 | #define BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS 0x8 | ||
486 | #define BF_UARTAPP_AUTOBAUD_TWO_REF_CHARS(v) (((v) << 3) & 0x8) | ||
487 | #define BP_UARTAPP_AUTOBAUD_START_WITH_RUNBIT 2 | ||
488 | #define BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT 0x4 | ||
489 | #define BF_UARTAPP_AUTOBAUD_START_WITH_RUNBIT(v) (((v) << 2) & 0x4) | ||
490 | #define BP_UARTAPP_AUTOBAUD_START_BAUD_DETECT 1 | ||
491 | #define BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT 0x2 | ||
492 | #define BF_UARTAPP_AUTOBAUD_START_BAUD_DETECT(v) (((v) << 1) & 0x2) | ||
493 | #define BP_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE 0 | ||
494 | #define BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE 0x1 | ||
495 | #define BF_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE(v) (((v) << 0) & 0x1) | ||
496 | |||
497 | #endif /* __HEADERGEN__IMX233__UARTAPP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h b/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h new file mode 100644 index 0000000000..a92bc288d3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h | |||
@@ -0,0 +1,491 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__UARTDBG__H__ | ||
24 | #define __HEADERGEN__IMX233__UARTDBG__H__ | ||
25 | |||
26 | #define REGS_UARTDBG_BASE (0x80070000) | ||
27 | |||
28 | #define REGS_UARTDBG_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_UARTDBG_DR | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_UARTDBG_DR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0)) | ||
36 | #define BP_UARTDBG_DR_UNAVAILABLE 16 | ||
37 | #define BM_UARTDBG_DR_UNAVAILABLE 0xffff0000 | ||
38 | #define BF_UARTDBG_DR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
39 | #define BP_UARTDBG_DR_RESERVED 12 | ||
40 | #define BM_UARTDBG_DR_RESERVED 0xf000 | ||
41 | #define BF_UARTDBG_DR_RESERVED(v) (((v) << 12) & 0xf000) | ||
42 | #define BP_UARTDBG_DR_OE 11 | ||
43 | #define BM_UARTDBG_DR_OE 0x800 | ||
44 | #define BF_UARTDBG_DR_OE(v) (((v) << 11) & 0x800) | ||
45 | #define BP_UARTDBG_DR_BE 10 | ||
46 | #define BM_UARTDBG_DR_BE 0x400 | ||
47 | #define BF_UARTDBG_DR_BE(v) (((v) << 10) & 0x400) | ||
48 | #define BP_UARTDBG_DR_PE 9 | ||
49 | #define BM_UARTDBG_DR_PE 0x200 | ||
50 | #define BF_UARTDBG_DR_PE(v) (((v) << 9) & 0x200) | ||
51 | #define BP_UARTDBG_DR_FE 8 | ||
52 | #define BM_UARTDBG_DR_FE 0x100 | ||
53 | #define BF_UARTDBG_DR_FE(v) (((v) << 8) & 0x100) | ||
54 | #define BP_UARTDBG_DR_DATA 0 | ||
55 | #define BM_UARTDBG_DR_DATA 0xff | ||
56 | #define BF_UARTDBG_DR_DATA(v) (((v) << 0) & 0xff) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_UARTDBG_RSR_ECR | ||
60 | * Address: 0x4 | ||
61 | * SCT: no | ||
62 | */ | ||
63 | #define HW_UARTDBG_RSR_ECR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4)) | ||
64 | #define BP_UARTDBG_RSR_ECR_UNAVAILABLE 8 | ||
65 | #define BM_UARTDBG_RSR_ECR_UNAVAILABLE 0xffffff00 | ||
66 | #define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
67 | #define BP_UARTDBG_RSR_ECR_EC 4 | ||
68 | #define BM_UARTDBG_RSR_ECR_EC 0xf0 | ||
69 | #define BF_UARTDBG_RSR_ECR_EC(v) (((v) << 4) & 0xf0) | ||
70 | #define BP_UARTDBG_RSR_ECR_OE 3 | ||
71 | #define BM_UARTDBG_RSR_ECR_OE 0x8 | ||
72 | #define BF_UARTDBG_RSR_ECR_OE(v) (((v) << 3) & 0x8) | ||
73 | #define BP_UARTDBG_RSR_ECR_BE 2 | ||
74 | #define BM_UARTDBG_RSR_ECR_BE 0x4 | ||
75 | #define BF_UARTDBG_RSR_ECR_BE(v) (((v) << 2) & 0x4) | ||
76 | #define BP_UARTDBG_RSR_ECR_PE 1 | ||
77 | #define BM_UARTDBG_RSR_ECR_PE 0x2 | ||
78 | #define BF_UARTDBG_RSR_ECR_PE(v) (((v) << 1) & 0x2) | ||
79 | #define BP_UARTDBG_RSR_ECR_FE 0 | ||
80 | #define BM_UARTDBG_RSR_ECR_FE 0x1 | ||
81 | #define BF_UARTDBG_RSR_ECR_FE(v) (((v) << 0) & 0x1) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_UARTDBG_FR | ||
85 | * Address: 0x18 | ||
86 | * SCT: no | ||
87 | */ | ||
88 | #define HW_UARTDBG_FR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18)) | ||
89 | #define BP_UARTDBG_FR_UNAVAILABLE 16 | ||
90 | #define BM_UARTDBG_FR_UNAVAILABLE 0xffff0000 | ||
91 | #define BF_UARTDBG_FR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
92 | #define BP_UARTDBG_FR_RESERVED 9 | ||
93 | #define BM_UARTDBG_FR_RESERVED 0xfe00 | ||
94 | #define BF_UARTDBG_FR_RESERVED(v) (((v) << 9) & 0xfe00) | ||
95 | #define BP_UARTDBG_FR_RI 8 | ||
96 | #define BM_UARTDBG_FR_RI 0x100 | ||
97 | #define BF_UARTDBG_FR_RI(v) (((v) << 8) & 0x100) | ||
98 | #define BP_UARTDBG_FR_TXFE 7 | ||
99 | #define BM_UARTDBG_FR_TXFE 0x80 | ||
100 | #define BF_UARTDBG_FR_TXFE(v) (((v) << 7) & 0x80) | ||
101 | #define BP_UARTDBG_FR_RXFF 6 | ||
102 | #define BM_UARTDBG_FR_RXFF 0x40 | ||
103 | #define BF_UARTDBG_FR_RXFF(v) (((v) << 6) & 0x40) | ||
104 | #define BP_UARTDBG_FR_TXFF 5 | ||
105 | #define BM_UARTDBG_FR_TXFF 0x20 | ||
106 | #define BF_UARTDBG_FR_TXFF(v) (((v) << 5) & 0x20) | ||
107 | #define BP_UARTDBG_FR_RXFE 4 | ||
108 | #define BM_UARTDBG_FR_RXFE 0x10 | ||
109 | #define BF_UARTDBG_FR_RXFE(v) (((v) << 4) & 0x10) | ||
110 | #define BP_UARTDBG_FR_BUSY 3 | ||
111 | #define BM_UARTDBG_FR_BUSY 0x8 | ||
112 | #define BF_UARTDBG_FR_BUSY(v) (((v) << 3) & 0x8) | ||
113 | #define BP_UARTDBG_FR_DCD 2 | ||
114 | #define BM_UARTDBG_FR_DCD 0x4 | ||
115 | #define BF_UARTDBG_FR_DCD(v) (((v) << 2) & 0x4) | ||
116 | #define BP_UARTDBG_FR_DSR 1 | ||
117 | #define BM_UARTDBG_FR_DSR 0x2 | ||
118 | #define BF_UARTDBG_FR_DSR(v) (((v) << 1) & 0x2) | ||
119 | #define BP_UARTDBG_FR_CTS 0 | ||
120 | #define BM_UARTDBG_FR_CTS 0x1 | ||
121 | #define BF_UARTDBG_FR_CTS(v) (((v) << 0) & 0x1) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_UARTDBG_ILPR | ||
125 | * Address: 0x20 | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_UARTDBG_ILPR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20)) | ||
129 | #define BP_UARTDBG_ILPR_UNAVAILABLE 8 | ||
130 | #define BM_UARTDBG_ILPR_UNAVAILABLE 0xffffff00 | ||
131 | #define BF_UARTDBG_ILPR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
132 | #define BP_UARTDBG_ILPR_ILPDVSR 0 | ||
133 | #define BM_UARTDBG_ILPR_ILPDVSR 0xff | ||
134 | #define BF_UARTDBG_ILPR_ILPDVSR(v) (((v) << 0) & 0xff) | ||
135 | |||
136 | /** | ||
137 | * Register: HW_UARTDBG_IBRD | ||
138 | * Address: 0x24 | ||
139 | * SCT: no | ||
140 | */ | ||
141 | #define HW_UARTDBG_IBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24)) | ||
142 | #define BP_UARTDBG_IBRD_UNAVAILABLE 16 | ||
143 | #define BM_UARTDBG_IBRD_UNAVAILABLE 0xffff0000 | ||
144 | #define BF_UARTDBG_IBRD_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
145 | #define BP_UARTDBG_IBRD_BAUD_DIVINT 0 | ||
146 | #define BM_UARTDBG_IBRD_BAUD_DIVINT 0xffff | ||
147 | #define BF_UARTDBG_IBRD_BAUD_DIVINT(v) (((v) << 0) & 0xffff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_UARTDBG_FBRD | ||
151 | * Address: 0x28 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_UARTDBG_FBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28)) | ||
155 | #define BP_UARTDBG_FBRD_UNAVAILABLE 8 | ||
156 | #define BM_UARTDBG_FBRD_UNAVAILABLE 0xffffff00 | ||
157 | #define BF_UARTDBG_FBRD_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
158 | #define BP_UARTDBG_FBRD_RESERVED 6 | ||
159 | #define BM_UARTDBG_FBRD_RESERVED 0xc0 | ||
160 | #define BF_UARTDBG_FBRD_RESERVED(v) (((v) << 6) & 0xc0) | ||
161 | #define BP_UARTDBG_FBRD_BAUD_DIVFRAC 0 | ||
162 | #define BM_UARTDBG_FBRD_BAUD_DIVFRAC 0x3f | ||
163 | #define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_UARTDBG_LCR_H | ||
167 | * Address: 0x2c | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_UARTDBG_LCR_H (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c)) | ||
171 | #define BP_UARTDBG_LCR_H_UNAVAILABLE 16 | ||
172 | #define BM_UARTDBG_LCR_H_UNAVAILABLE 0xffff0000 | ||
173 | #define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
174 | #define BP_UARTDBG_LCR_H_RESERVED 8 | ||
175 | #define BM_UARTDBG_LCR_H_RESERVED 0xff00 | ||
176 | #define BF_UARTDBG_LCR_H_RESERVED(v) (((v) << 8) & 0xff00) | ||
177 | #define BP_UARTDBG_LCR_H_SPS 7 | ||
178 | #define BM_UARTDBG_LCR_H_SPS 0x80 | ||
179 | #define BF_UARTDBG_LCR_H_SPS(v) (((v) << 7) & 0x80) | ||
180 | #define BP_UARTDBG_LCR_H_WLEN 5 | ||
181 | #define BM_UARTDBG_LCR_H_WLEN 0x60 | ||
182 | #define BF_UARTDBG_LCR_H_WLEN(v) (((v) << 5) & 0x60) | ||
183 | #define BP_UARTDBG_LCR_H_FEN 4 | ||
184 | #define BM_UARTDBG_LCR_H_FEN 0x10 | ||
185 | #define BF_UARTDBG_LCR_H_FEN(v) (((v) << 4) & 0x10) | ||
186 | #define BP_UARTDBG_LCR_H_STP2 3 | ||
187 | #define BM_UARTDBG_LCR_H_STP2 0x8 | ||
188 | #define BF_UARTDBG_LCR_H_STP2(v) (((v) << 3) & 0x8) | ||
189 | #define BP_UARTDBG_LCR_H_EPS 2 | ||
190 | #define BM_UARTDBG_LCR_H_EPS 0x4 | ||
191 | #define BF_UARTDBG_LCR_H_EPS(v) (((v) << 2) & 0x4) | ||
192 | #define BP_UARTDBG_LCR_H_PEN 1 | ||
193 | #define BM_UARTDBG_LCR_H_PEN 0x2 | ||
194 | #define BF_UARTDBG_LCR_H_PEN(v) (((v) << 1) & 0x2) | ||
195 | #define BP_UARTDBG_LCR_H_BRK 0 | ||
196 | #define BM_UARTDBG_LCR_H_BRK 0x1 | ||
197 | #define BF_UARTDBG_LCR_H_BRK(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_UARTDBG_CR | ||
201 | * Address: 0x30 | ||
202 | * SCT: no | ||
203 | */ | ||
204 | #define HW_UARTDBG_CR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30)) | ||
205 | #define BP_UARTDBG_CR_UNAVAILABLE 16 | ||
206 | #define BM_UARTDBG_CR_UNAVAILABLE 0xffff0000 | ||
207 | #define BF_UARTDBG_CR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
208 | #define BP_UARTDBG_CR_CTSEN 15 | ||
209 | #define BM_UARTDBG_CR_CTSEN 0x8000 | ||
210 | #define BF_UARTDBG_CR_CTSEN(v) (((v) << 15) & 0x8000) | ||
211 | #define BP_UARTDBG_CR_RTSEN 14 | ||
212 | #define BM_UARTDBG_CR_RTSEN 0x4000 | ||
213 | #define BF_UARTDBG_CR_RTSEN(v) (((v) << 14) & 0x4000) | ||
214 | #define BP_UARTDBG_CR_OUT2 13 | ||
215 | #define BM_UARTDBG_CR_OUT2 0x2000 | ||
216 | #define BF_UARTDBG_CR_OUT2(v) (((v) << 13) & 0x2000) | ||
217 | #define BP_UARTDBG_CR_OUT1 12 | ||
218 | #define BM_UARTDBG_CR_OUT1 0x1000 | ||
219 | #define BF_UARTDBG_CR_OUT1(v) (((v) << 12) & 0x1000) | ||
220 | #define BP_UARTDBG_CR_RTS 11 | ||
221 | #define BM_UARTDBG_CR_RTS 0x800 | ||
222 | #define BF_UARTDBG_CR_RTS(v) (((v) << 11) & 0x800) | ||
223 | #define BP_UARTDBG_CR_DTR 10 | ||
224 | #define BM_UARTDBG_CR_DTR 0x400 | ||
225 | #define BF_UARTDBG_CR_DTR(v) (((v) << 10) & 0x400) | ||
226 | #define BP_UARTDBG_CR_RXE 9 | ||
227 | #define BM_UARTDBG_CR_RXE 0x200 | ||
228 | #define BF_UARTDBG_CR_RXE(v) (((v) << 9) & 0x200) | ||
229 | #define BP_UARTDBG_CR_TXE 8 | ||
230 | #define BM_UARTDBG_CR_TXE 0x100 | ||
231 | #define BF_UARTDBG_CR_TXE(v) (((v) << 8) & 0x100) | ||
232 | #define BP_UARTDBG_CR_LBE 7 | ||
233 | #define BM_UARTDBG_CR_LBE 0x80 | ||
234 | #define BF_UARTDBG_CR_LBE(v) (((v) << 7) & 0x80) | ||
235 | #define BP_UARTDBG_CR_RESERVED 3 | ||
236 | #define BM_UARTDBG_CR_RESERVED 0x78 | ||
237 | #define BF_UARTDBG_CR_RESERVED(v) (((v) << 3) & 0x78) | ||
238 | #define BP_UARTDBG_CR_SIRLP 2 | ||
239 | #define BM_UARTDBG_CR_SIRLP 0x4 | ||
240 | #define BF_UARTDBG_CR_SIRLP(v) (((v) << 2) & 0x4) | ||
241 | #define BP_UARTDBG_CR_SIREN 1 | ||
242 | #define BM_UARTDBG_CR_SIREN 0x2 | ||
243 | #define BF_UARTDBG_CR_SIREN(v) (((v) << 1) & 0x2) | ||
244 | #define BP_UARTDBG_CR_UARTEN 0 | ||
245 | #define BM_UARTDBG_CR_UARTEN 0x1 | ||
246 | #define BF_UARTDBG_CR_UARTEN(v) (((v) << 0) & 0x1) | ||
247 | |||
248 | /** | ||
249 | * Register: HW_UARTDBG_IFLS | ||
250 | * Address: 0x34 | ||
251 | * SCT: no | ||
252 | */ | ||
253 | #define HW_UARTDBG_IFLS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34)) | ||
254 | #define BP_UARTDBG_IFLS_UNAVAILABLE 16 | ||
255 | #define BM_UARTDBG_IFLS_UNAVAILABLE 0xffff0000 | ||
256 | #define BF_UARTDBG_IFLS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
257 | #define BP_UARTDBG_IFLS_RESERVED 6 | ||
258 | #define BM_UARTDBG_IFLS_RESERVED 0xffc0 | ||
259 | #define BF_UARTDBG_IFLS_RESERVED(v) (((v) << 6) & 0xffc0) | ||
260 | #define BP_UARTDBG_IFLS_RXIFLSEL 3 | ||
261 | #define BM_UARTDBG_IFLS_RXIFLSEL 0x38 | ||
262 | #define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY 0x0 | ||
263 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER 0x1 | ||
264 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF 0x2 | ||
265 | #define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS 0x3 | ||
266 | #define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
267 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5 0x5 | ||
268 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6 0x6 | ||
269 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7 0x7 | ||
270 | #define BF_UARTDBG_IFLS_RXIFLSEL(v) (((v) << 3) & 0x38) | ||
271 | #define BF_UARTDBG_IFLS_RXIFLSEL_V(v) ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38) | ||
272 | #define BP_UARTDBG_IFLS_TXIFLSEL 0 | ||
273 | #define BM_UARTDBG_IFLS_TXIFLSEL 0x7 | ||
274 | #define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY 0x0 | ||
275 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER 0x1 | ||
276 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF 0x2 | ||
277 | #define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS 0x3 | ||
278 | #define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
279 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5 0x5 | ||
280 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6 0x6 | ||
281 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7 0x7 | ||
282 | #define BF_UARTDBG_IFLS_TXIFLSEL(v) (((v) << 0) & 0x7) | ||
283 | #define BF_UARTDBG_IFLS_TXIFLSEL_V(v) ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7) | ||
284 | |||
285 | /** | ||
286 | * Register: HW_UARTDBG_IMSC | ||
287 | * Address: 0x38 | ||
288 | * SCT: no | ||
289 | */ | ||
290 | #define HW_UARTDBG_IMSC (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38)) | ||
291 | #define BP_UARTDBG_IMSC_UNAVAILABLE 16 | ||
292 | #define BM_UARTDBG_IMSC_UNAVAILABLE 0xffff0000 | ||
293 | #define BF_UARTDBG_IMSC_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
294 | #define BP_UARTDBG_IMSC_RESERVED 11 | ||
295 | #define BM_UARTDBG_IMSC_RESERVED 0xf800 | ||
296 | #define BF_UARTDBG_IMSC_RESERVED(v) (((v) << 11) & 0xf800) | ||
297 | #define BP_UARTDBG_IMSC_OEIM 10 | ||
298 | #define BM_UARTDBG_IMSC_OEIM 0x400 | ||
299 | #define BF_UARTDBG_IMSC_OEIM(v) (((v) << 10) & 0x400) | ||
300 | #define BP_UARTDBG_IMSC_BEIM 9 | ||
301 | #define BM_UARTDBG_IMSC_BEIM 0x200 | ||
302 | #define BF_UARTDBG_IMSC_BEIM(v) (((v) << 9) & 0x200) | ||
303 | #define BP_UARTDBG_IMSC_PEIM 8 | ||
304 | #define BM_UARTDBG_IMSC_PEIM 0x100 | ||
305 | #define BF_UARTDBG_IMSC_PEIM(v) (((v) << 8) & 0x100) | ||
306 | #define BP_UARTDBG_IMSC_FEIM 7 | ||
307 | #define BM_UARTDBG_IMSC_FEIM 0x80 | ||
308 | #define BF_UARTDBG_IMSC_FEIM(v) (((v) << 7) & 0x80) | ||
309 | #define BP_UARTDBG_IMSC_RTIM 6 | ||
310 | #define BM_UARTDBG_IMSC_RTIM 0x40 | ||
311 | #define BF_UARTDBG_IMSC_RTIM(v) (((v) << 6) & 0x40) | ||
312 | #define BP_UARTDBG_IMSC_TXIM 5 | ||
313 | #define BM_UARTDBG_IMSC_TXIM 0x20 | ||
314 | #define BF_UARTDBG_IMSC_TXIM(v) (((v) << 5) & 0x20) | ||
315 | #define BP_UARTDBG_IMSC_RXIM 4 | ||
316 | #define BM_UARTDBG_IMSC_RXIM 0x10 | ||
317 | #define BF_UARTDBG_IMSC_RXIM(v) (((v) << 4) & 0x10) | ||
318 | #define BP_UARTDBG_IMSC_DSRMIM 3 | ||
319 | #define BM_UARTDBG_IMSC_DSRMIM 0x8 | ||
320 | #define BF_UARTDBG_IMSC_DSRMIM(v) (((v) << 3) & 0x8) | ||
321 | #define BP_UARTDBG_IMSC_DCDMIM 2 | ||
322 | #define BM_UARTDBG_IMSC_DCDMIM 0x4 | ||
323 | #define BF_UARTDBG_IMSC_DCDMIM(v) (((v) << 2) & 0x4) | ||
324 | #define BP_UARTDBG_IMSC_CTSMIM 1 | ||
325 | #define BM_UARTDBG_IMSC_CTSMIM 0x2 | ||
326 | #define BF_UARTDBG_IMSC_CTSMIM(v) (((v) << 1) & 0x2) | ||
327 | #define BP_UARTDBG_IMSC_RIMIM 0 | ||
328 | #define BM_UARTDBG_IMSC_RIMIM 0x1 | ||
329 | #define BF_UARTDBG_IMSC_RIMIM(v) (((v) << 0) & 0x1) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_UARTDBG_RIS | ||
333 | * Address: 0x3c | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_UARTDBG_RIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c)) | ||
337 | #define BP_UARTDBG_RIS_UNAVAILABLE 16 | ||
338 | #define BM_UARTDBG_RIS_UNAVAILABLE 0xffff0000 | ||
339 | #define BF_UARTDBG_RIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
340 | #define BP_UARTDBG_RIS_RESERVED 11 | ||
341 | #define BM_UARTDBG_RIS_RESERVED 0xf800 | ||
342 | #define BF_UARTDBG_RIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
343 | #define BP_UARTDBG_RIS_OERIS 10 | ||
344 | #define BM_UARTDBG_RIS_OERIS 0x400 | ||
345 | #define BF_UARTDBG_RIS_OERIS(v) (((v) << 10) & 0x400) | ||
346 | #define BP_UARTDBG_RIS_BERIS 9 | ||
347 | #define BM_UARTDBG_RIS_BERIS 0x200 | ||
348 | #define BF_UARTDBG_RIS_BERIS(v) (((v) << 9) & 0x200) | ||
349 | #define BP_UARTDBG_RIS_PERIS 8 | ||
350 | #define BM_UARTDBG_RIS_PERIS 0x100 | ||
351 | #define BF_UARTDBG_RIS_PERIS(v) (((v) << 8) & 0x100) | ||
352 | #define BP_UARTDBG_RIS_FERIS 7 | ||
353 | #define BM_UARTDBG_RIS_FERIS 0x80 | ||
354 | #define BF_UARTDBG_RIS_FERIS(v) (((v) << 7) & 0x80) | ||
355 | #define BP_UARTDBG_RIS_RTRIS 6 | ||
356 | #define BM_UARTDBG_RIS_RTRIS 0x40 | ||
357 | #define BF_UARTDBG_RIS_RTRIS(v) (((v) << 6) & 0x40) | ||
358 | #define BP_UARTDBG_RIS_TXRIS 5 | ||
359 | #define BM_UARTDBG_RIS_TXRIS 0x20 | ||
360 | #define BF_UARTDBG_RIS_TXRIS(v) (((v) << 5) & 0x20) | ||
361 | #define BP_UARTDBG_RIS_RXRIS 4 | ||
362 | #define BM_UARTDBG_RIS_RXRIS 0x10 | ||
363 | #define BF_UARTDBG_RIS_RXRIS(v) (((v) << 4) & 0x10) | ||
364 | #define BP_UARTDBG_RIS_DSRRMIS 3 | ||
365 | #define BM_UARTDBG_RIS_DSRRMIS 0x8 | ||
366 | #define BF_UARTDBG_RIS_DSRRMIS(v) (((v) << 3) & 0x8) | ||
367 | #define BP_UARTDBG_RIS_DCDRMIS 2 | ||
368 | #define BM_UARTDBG_RIS_DCDRMIS 0x4 | ||
369 | #define BF_UARTDBG_RIS_DCDRMIS(v) (((v) << 2) & 0x4) | ||
370 | #define BP_UARTDBG_RIS_CTSRMIS 1 | ||
371 | #define BM_UARTDBG_RIS_CTSRMIS 0x2 | ||
372 | #define BF_UARTDBG_RIS_CTSRMIS(v) (((v) << 1) & 0x2) | ||
373 | #define BP_UARTDBG_RIS_RIRMIS 0 | ||
374 | #define BM_UARTDBG_RIS_RIRMIS 0x1 | ||
375 | #define BF_UARTDBG_RIS_RIRMIS(v) (((v) << 0) & 0x1) | ||
376 | |||
377 | /** | ||
378 | * Register: HW_UARTDBG_MIS | ||
379 | * Address: 0x40 | ||
380 | * SCT: no | ||
381 | */ | ||
382 | #define HW_UARTDBG_MIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40)) | ||
383 | #define BP_UARTDBG_MIS_UNAVAILABLE 16 | ||
384 | #define BM_UARTDBG_MIS_UNAVAILABLE 0xffff0000 | ||
385 | #define BF_UARTDBG_MIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
386 | #define BP_UARTDBG_MIS_RESERVED 11 | ||
387 | #define BM_UARTDBG_MIS_RESERVED 0xf800 | ||
388 | #define BF_UARTDBG_MIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
389 | #define BP_UARTDBG_MIS_OEMIS 10 | ||
390 | #define BM_UARTDBG_MIS_OEMIS 0x400 | ||
391 | #define BF_UARTDBG_MIS_OEMIS(v) (((v) << 10) & 0x400) | ||
392 | #define BP_UARTDBG_MIS_BEMIS 9 | ||
393 | #define BM_UARTDBG_MIS_BEMIS 0x200 | ||
394 | #define BF_UARTDBG_MIS_BEMIS(v) (((v) << 9) & 0x200) | ||
395 | #define BP_UARTDBG_MIS_PEMIS 8 | ||
396 | #define BM_UARTDBG_MIS_PEMIS 0x100 | ||
397 | #define BF_UARTDBG_MIS_PEMIS(v) (((v) << 8) & 0x100) | ||
398 | #define BP_UARTDBG_MIS_FEMIS 7 | ||
399 | #define BM_UARTDBG_MIS_FEMIS 0x80 | ||
400 | #define BF_UARTDBG_MIS_FEMIS(v) (((v) << 7) & 0x80) | ||
401 | #define BP_UARTDBG_MIS_RTMIS 6 | ||
402 | #define BM_UARTDBG_MIS_RTMIS 0x40 | ||
403 | #define BF_UARTDBG_MIS_RTMIS(v) (((v) << 6) & 0x40) | ||
404 | #define BP_UARTDBG_MIS_TXMIS 5 | ||
405 | #define BM_UARTDBG_MIS_TXMIS 0x20 | ||
406 | #define BF_UARTDBG_MIS_TXMIS(v) (((v) << 5) & 0x20) | ||
407 | #define BP_UARTDBG_MIS_RXMIS 4 | ||
408 | #define BM_UARTDBG_MIS_RXMIS 0x10 | ||
409 | #define BF_UARTDBG_MIS_RXMIS(v) (((v) << 4) & 0x10) | ||
410 | #define BP_UARTDBG_MIS_DSRMMIS 3 | ||
411 | #define BM_UARTDBG_MIS_DSRMMIS 0x8 | ||
412 | #define BF_UARTDBG_MIS_DSRMMIS(v) (((v) << 3) & 0x8) | ||
413 | #define BP_UARTDBG_MIS_DCDMMIS 2 | ||
414 | #define BM_UARTDBG_MIS_DCDMMIS 0x4 | ||
415 | #define BF_UARTDBG_MIS_DCDMMIS(v) (((v) << 2) & 0x4) | ||
416 | #define BP_UARTDBG_MIS_CTSMMIS 1 | ||
417 | #define BM_UARTDBG_MIS_CTSMMIS 0x2 | ||
418 | #define BF_UARTDBG_MIS_CTSMMIS(v) (((v) << 1) & 0x2) | ||
419 | #define BP_UARTDBG_MIS_RIMMIS 0 | ||
420 | #define BM_UARTDBG_MIS_RIMMIS 0x1 | ||
421 | #define BF_UARTDBG_MIS_RIMMIS(v) (((v) << 0) & 0x1) | ||
422 | |||
423 | /** | ||
424 | * Register: HW_UARTDBG_ICR | ||
425 | * Address: 0x44 | ||
426 | * SCT: no | ||
427 | */ | ||
428 | #define HW_UARTDBG_ICR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44)) | ||
429 | #define BP_UARTDBG_ICR_UNAVAILABLE 16 | ||
430 | #define BM_UARTDBG_ICR_UNAVAILABLE 0xffff0000 | ||
431 | #define BF_UARTDBG_ICR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
432 | #define BP_UARTDBG_ICR_RESERVED 11 | ||
433 | #define BM_UARTDBG_ICR_RESERVED 0xf800 | ||
434 | #define BF_UARTDBG_ICR_RESERVED(v) (((v) << 11) & 0xf800) | ||
435 | #define BP_UARTDBG_ICR_OEIC 10 | ||
436 | #define BM_UARTDBG_ICR_OEIC 0x400 | ||
437 | #define BF_UARTDBG_ICR_OEIC(v) (((v) << 10) & 0x400) | ||
438 | #define BP_UARTDBG_ICR_BEIC 9 | ||
439 | #define BM_UARTDBG_ICR_BEIC 0x200 | ||
440 | #define BF_UARTDBG_ICR_BEIC(v) (((v) << 9) & 0x200) | ||
441 | #define BP_UARTDBG_ICR_PEIC 8 | ||
442 | #define BM_UARTDBG_ICR_PEIC 0x100 | ||
443 | #define BF_UARTDBG_ICR_PEIC(v) (((v) << 8) & 0x100) | ||
444 | #define BP_UARTDBG_ICR_FEIC 7 | ||
445 | #define BM_UARTDBG_ICR_FEIC 0x80 | ||
446 | #define BF_UARTDBG_ICR_FEIC(v) (((v) << 7) & 0x80) | ||
447 | #define BP_UARTDBG_ICR_RTIC 6 | ||
448 | #define BM_UARTDBG_ICR_RTIC 0x40 | ||
449 | #define BF_UARTDBG_ICR_RTIC(v) (((v) << 6) & 0x40) | ||
450 | #define BP_UARTDBG_ICR_TXIC 5 | ||
451 | #define BM_UARTDBG_ICR_TXIC 0x20 | ||
452 | #define BF_UARTDBG_ICR_TXIC(v) (((v) << 5) & 0x20) | ||
453 | #define BP_UARTDBG_ICR_RXIC 4 | ||
454 | #define BM_UARTDBG_ICR_RXIC 0x10 | ||
455 | #define BF_UARTDBG_ICR_RXIC(v) (((v) << 4) & 0x10) | ||
456 | #define BP_UARTDBG_ICR_DSRMIC 3 | ||
457 | #define BM_UARTDBG_ICR_DSRMIC 0x8 | ||
458 | #define BF_UARTDBG_ICR_DSRMIC(v) (((v) << 3) & 0x8) | ||
459 | #define BP_UARTDBG_ICR_DCDMIC 2 | ||
460 | #define BM_UARTDBG_ICR_DCDMIC 0x4 | ||
461 | #define BF_UARTDBG_ICR_DCDMIC(v) (((v) << 2) & 0x4) | ||
462 | #define BP_UARTDBG_ICR_CTSMIC 1 | ||
463 | #define BM_UARTDBG_ICR_CTSMIC 0x2 | ||
464 | #define BF_UARTDBG_ICR_CTSMIC(v) (((v) << 1) & 0x2) | ||
465 | #define BP_UARTDBG_ICR_RIMIC 0 | ||
466 | #define BM_UARTDBG_ICR_RIMIC 0x1 | ||
467 | #define BF_UARTDBG_ICR_RIMIC(v) (((v) << 0) & 0x1) | ||
468 | |||
469 | /** | ||
470 | * Register: HW_UARTDBG_DMACR | ||
471 | * Address: 0x48 | ||
472 | * SCT: no | ||
473 | */ | ||
474 | #define HW_UARTDBG_DMACR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48)) | ||
475 | #define BP_UARTDBG_DMACR_UNAVAILABLE 16 | ||
476 | #define BM_UARTDBG_DMACR_UNAVAILABLE 0xffff0000 | ||
477 | #define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
478 | #define BP_UARTDBG_DMACR_RESERVED 3 | ||
479 | #define BM_UARTDBG_DMACR_RESERVED 0xfff8 | ||
480 | #define BF_UARTDBG_DMACR_RESERVED(v) (((v) << 3) & 0xfff8) | ||
481 | #define BP_UARTDBG_DMACR_DMAONERR 2 | ||
482 | #define BM_UARTDBG_DMACR_DMAONERR 0x4 | ||
483 | #define BF_UARTDBG_DMACR_DMAONERR(v) (((v) << 2) & 0x4) | ||
484 | #define BP_UARTDBG_DMACR_TXDMAE 1 | ||
485 | #define BM_UARTDBG_DMACR_TXDMAE 0x2 | ||
486 | #define BF_UARTDBG_DMACR_TXDMAE(v) (((v) << 1) & 0x2) | ||
487 | #define BP_UARTDBG_DMACR_RXDMAE 0 | ||
488 | #define BM_UARTDBG_DMACR_RXDMAE 0x1 | ||
489 | #define BF_UARTDBG_DMACR_RXDMAE(v) (((v) << 0) & 0x1) | ||
490 | |||
491 | #endif /* __HEADERGEN__IMX233__UARTDBG__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h new file mode 100644 index 0000000000..1e69f3c8bc --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h | |||
@@ -0,0 +1,1234 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__USBCTRL__H__ | ||
24 | #define __HEADERGEN__IMX233__USBCTRL__H__ | ||
25 | |||
26 | #define REGS_USBCTRL_BASE (0x80080000) | ||
27 | |||
28 | #define REGS_USBCTRL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_USBCTRL_ID | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_USBCTRL_ID (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x0)) | ||
36 | #define BP_USBCTRL_ID_CIVERSION 29 | ||
37 | #define BM_USBCTRL_ID_CIVERSION 0xe0000000 | ||
38 | #define BF_USBCTRL_ID_CIVERSION(v) (((v) << 29) & 0xe0000000) | ||
39 | #define BP_USBCTRL_ID_VERSION 25 | ||
40 | #define BM_USBCTRL_ID_VERSION 0x1e000000 | ||
41 | #define BF_USBCTRL_ID_VERSION(v) (((v) << 25) & 0x1e000000) | ||
42 | #define BP_USBCTRL_ID_REVISION 21 | ||
43 | #define BM_USBCTRL_ID_REVISION 0x1e00000 | ||
44 | #define BF_USBCTRL_ID_REVISION(v) (((v) << 21) & 0x1e00000) | ||
45 | #define BP_USBCTRL_ID_TAG 16 | ||
46 | #define BM_USBCTRL_ID_TAG 0x1f0000 | ||
47 | #define BF_USBCTRL_ID_TAG(v) (((v) << 16) & 0x1f0000) | ||
48 | #define BP_USBCTRL_ID_RSVD1 14 | ||
49 | #define BM_USBCTRL_ID_RSVD1 0xc000 | ||
50 | #define BF_USBCTRL_ID_RSVD1(v) (((v) << 14) & 0xc000) | ||
51 | #define BP_USBCTRL_ID_NID 8 | ||
52 | #define BM_USBCTRL_ID_NID 0x3f00 | ||
53 | #define BF_USBCTRL_ID_NID(v) (((v) << 8) & 0x3f00) | ||
54 | #define BP_USBCTRL_ID_RSVD0 6 | ||
55 | #define BM_USBCTRL_ID_RSVD0 0xc0 | ||
56 | #define BF_USBCTRL_ID_RSVD0(v) (((v) << 6) & 0xc0) | ||
57 | #define BP_USBCTRL_ID_ID 0 | ||
58 | #define BM_USBCTRL_ID_ID 0x3f | ||
59 | #define BF_USBCTRL_ID_ID(v) (((v) << 0) & 0x3f) | ||
60 | |||
61 | /** | ||
62 | * Register: HW_USBCTRL_HWGENERAL | ||
63 | * Address: 0x4 | ||
64 | * SCT: no | ||
65 | */ | ||
66 | #define HW_USBCTRL_HWGENERAL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x4)) | ||
67 | #define BP_USBCTRL_HWGENERAL_RSVD 11 | ||
68 | #define BM_USBCTRL_HWGENERAL_RSVD 0xfffff800 | ||
69 | #define BF_USBCTRL_HWGENERAL_RSVD(v) (((v) << 11) & 0xfffff800) | ||
70 | #define BP_USBCTRL_HWGENERAL_SM 9 | ||
71 | #define BM_USBCTRL_HWGENERAL_SM 0x600 | ||
72 | #define BF_USBCTRL_HWGENERAL_SM(v) (((v) << 9) & 0x600) | ||
73 | #define BP_USBCTRL_HWGENERAL_PHYM 6 | ||
74 | #define BM_USBCTRL_HWGENERAL_PHYM 0x1c0 | ||
75 | #define BF_USBCTRL_HWGENERAL_PHYM(v) (((v) << 6) & 0x1c0) | ||
76 | #define BP_USBCTRL_HWGENERAL_PHYW 4 | ||
77 | #define BM_USBCTRL_HWGENERAL_PHYW 0x30 | ||
78 | #define BF_USBCTRL_HWGENERAL_PHYW(v) (((v) << 4) & 0x30) | ||
79 | #define BP_USBCTRL_HWGENERAL_BWT 3 | ||
80 | #define BM_USBCTRL_HWGENERAL_BWT 0x8 | ||
81 | #define BF_USBCTRL_HWGENERAL_BWT(v) (((v) << 3) & 0x8) | ||
82 | #define BP_USBCTRL_HWGENERAL_CLKC 1 | ||
83 | #define BM_USBCTRL_HWGENERAL_CLKC 0x6 | ||
84 | #define BF_USBCTRL_HWGENERAL_CLKC(v) (((v) << 1) & 0x6) | ||
85 | #define BP_USBCTRL_HWGENERAL_RT 0 | ||
86 | #define BM_USBCTRL_HWGENERAL_RT 0x1 | ||
87 | #define BF_USBCTRL_HWGENERAL_RT(v) (((v) << 0) & 0x1) | ||
88 | |||
89 | /** | ||
90 | * Register: HW_USBCTRL_HWHOST | ||
91 | * Address: 0x8 | ||
92 | * SCT: no | ||
93 | */ | ||
94 | #define HW_USBCTRL_HWHOST (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8)) | ||
95 | #define BP_USBCTRL_HWHOST_TTPER 24 | ||
96 | #define BM_USBCTRL_HWHOST_TTPER 0xff000000 | ||
97 | #define BF_USBCTRL_HWHOST_TTPER(v) (((v) << 24) & 0xff000000) | ||
98 | #define BP_USBCTRL_HWHOST_TTASY 16 | ||
99 | #define BM_USBCTRL_HWHOST_TTASY 0xff0000 | ||
100 | #define BF_USBCTRL_HWHOST_TTASY(v) (((v) << 16) & 0xff0000) | ||
101 | #define BP_USBCTRL_HWHOST_RSVD 4 | ||
102 | #define BM_USBCTRL_HWHOST_RSVD 0xfff0 | ||
103 | #define BF_USBCTRL_HWHOST_RSVD(v) (((v) << 4) & 0xfff0) | ||
104 | #define BP_USBCTRL_HWHOST_NPORT 1 | ||
105 | #define BM_USBCTRL_HWHOST_NPORT 0xe | ||
106 | #define BF_USBCTRL_HWHOST_NPORT(v) (((v) << 1) & 0xe) | ||
107 | #define BP_USBCTRL_HWHOST_HC 0 | ||
108 | #define BM_USBCTRL_HWHOST_HC 0x1 | ||
109 | #define BF_USBCTRL_HWHOST_HC(v) (((v) << 0) & 0x1) | ||
110 | |||
111 | /** | ||
112 | * Register: HW_USBCTRL_HWDEVICE | ||
113 | * Address: 0xc | ||
114 | * SCT: no | ||
115 | */ | ||
116 | #define HW_USBCTRL_HWDEVICE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0xc)) | ||
117 | #define BP_USBCTRL_HWDEVICE_RSVD 6 | ||
118 | #define BM_USBCTRL_HWDEVICE_RSVD 0xffffffc0 | ||
119 | #define BF_USBCTRL_HWDEVICE_RSVD(v) (((v) << 6) & 0xffffffc0) | ||
120 | #define BP_USBCTRL_HWDEVICE_DEVEP 1 | ||
121 | #define BM_USBCTRL_HWDEVICE_DEVEP 0x3e | ||
122 | #define BF_USBCTRL_HWDEVICE_DEVEP(v) (((v) << 1) & 0x3e) | ||
123 | #define BP_USBCTRL_HWDEVICE_DC 0 | ||
124 | #define BM_USBCTRL_HWDEVICE_DC 0x1 | ||
125 | #define BF_USBCTRL_HWDEVICE_DC(v) (((v) << 0) & 0x1) | ||
126 | |||
127 | /** | ||
128 | * Register: HW_USBCTRL_HWTXBUF | ||
129 | * Address: 0x10 | ||
130 | * SCT: no | ||
131 | */ | ||
132 | #define HW_USBCTRL_HWTXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x10)) | ||
133 | #define BP_USBCTRL_HWTXBUF_TXLCR 31 | ||
134 | #define BM_USBCTRL_HWTXBUF_TXLCR 0x80000000 | ||
135 | #define BF_USBCTRL_HWTXBUF_TXLCR(v) (((v) << 31) & 0x80000000) | ||
136 | #define BP_USBCTRL_HWTXBUF_RSVD 24 | ||
137 | #define BM_USBCTRL_HWTXBUF_RSVD 0x7f000000 | ||
138 | #define BF_USBCTRL_HWTXBUF_RSVD(v) (((v) << 24) & 0x7f000000) | ||
139 | #define BP_USBCTRL_HWTXBUF_TXCHANADD 16 | ||
140 | #define BM_USBCTRL_HWTXBUF_TXCHANADD 0xff0000 | ||
141 | #define BF_USBCTRL_HWTXBUF_TXCHANADD(v) (((v) << 16) & 0xff0000) | ||
142 | #define BP_USBCTRL_HWTXBUF_TXADD 8 | ||
143 | #define BM_USBCTRL_HWTXBUF_TXADD 0xff00 | ||
144 | #define BF_USBCTRL_HWTXBUF_TXADD(v) (((v) << 8) & 0xff00) | ||
145 | #define BP_USBCTRL_HWTXBUF_TXBURST 0 | ||
146 | #define BM_USBCTRL_HWTXBUF_TXBURST 0xff | ||
147 | #define BF_USBCTRL_HWTXBUF_TXBURST(v) (((v) << 0) & 0xff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_USBCTRL_HWRXBUF | ||
151 | * Address: 0x14 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_USBCTRL_HWRXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14)) | ||
155 | #define BP_USBCTRL_HWRXBUF_RSVD 16 | ||
156 | #define BM_USBCTRL_HWRXBUF_RSVD 0xffff0000 | ||
157 | #define BF_USBCTRL_HWRXBUF_RSVD(v) (((v) << 16) & 0xffff0000) | ||
158 | #define BP_USBCTRL_HWRXBUF_RXADD 8 | ||
159 | #define BM_USBCTRL_HWRXBUF_RXADD 0xff00 | ||
160 | #define BF_USBCTRL_HWRXBUF_RXADD(v) (((v) << 8) & 0xff00) | ||
161 | #define BP_USBCTRL_HWRXBUF_RXBURST 0 | ||
162 | #define BM_USBCTRL_HWRXBUF_RXBURST 0xff | ||
163 | #define BF_USBCTRL_HWRXBUF_RXBURST(v) (((v) << 0) & 0xff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_USBCTRL_GPTIMER0LD | ||
167 | * Address: 0x80 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_USBCTRL_GPTIMER0LD (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x80)) | ||
171 | #define BP_USBCTRL_GPTIMER0LD_RSVD0 24 | ||
172 | #define BM_USBCTRL_GPTIMER0LD_RSVD0 0xff000000 | ||
173 | #define BF_USBCTRL_GPTIMER0LD_RSVD0(v) (((v) << 24) & 0xff000000) | ||
174 | #define BP_USBCTRL_GPTIMER0LD_GPTLD 0 | ||
175 | #define BM_USBCTRL_GPTIMER0LD_GPTLD 0xffffff | ||
176 | #define BF_USBCTRL_GPTIMER0LD_GPTLD(v) (((v) << 0) & 0xffffff) | ||
177 | |||
178 | /** | ||
179 | * Register: HW_USBCTRL_GPTIMER0CTRL | ||
180 | * Address: 0x84 | ||
181 | * SCT: no | ||
182 | */ | ||
183 | #define HW_USBCTRL_GPTIMER0CTRL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x84)) | ||
184 | #define BP_USBCTRL_GPTIMER0CTRL_GPTRUN 31 | ||
185 | #define BM_USBCTRL_GPTIMER0CTRL_GPTRUN 0x80000000 | ||
186 | #define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__STOP 0x0 | ||
187 | #define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__RUN 0x1 | ||
188 | #define BF_USBCTRL_GPTIMER0CTRL_GPTRUN(v) (((v) << 31) & 0x80000000) | ||
189 | #define BF_USBCTRL_GPTIMER0CTRL_GPTRUN_V(v) ((BV_USBCTRL_GPTIMER0CTRL_GPTRUN__##v << 31) & 0x80000000) | ||
190 | #define BP_USBCTRL_GPTIMER0CTRL_GPTRST 30 | ||
191 | #define BM_USBCTRL_GPTIMER0CTRL_GPTRST 0x40000000 | ||
192 | #define BV_USBCTRL_GPTIMER0CTRL_GPTRST__NOACTION 0x0 | ||
193 | #define BV_USBCTRL_GPTIMER0CTRL_GPTRST__LOADCOUNTER 0x1 | ||
194 | #define BF_USBCTRL_GPTIMER0CTRL_GPTRST(v) (((v) << 30) & 0x40000000) | ||
195 | #define BF_USBCTRL_GPTIMER0CTRL_GPTRST_V(v) ((BV_USBCTRL_GPTIMER0CTRL_GPTRST__##v << 30) & 0x40000000) | ||
196 | #define BP_USBCTRL_GPTIMER0CTRL_RSVD0 25 | ||
197 | #define BM_USBCTRL_GPTIMER0CTRL_RSVD0 0x3e000000 | ||
198 | #define BF_USBCTRL_GPTIMER0CTRL_RSVD0(v) (((v) << 25) & 0x3e000000) | ||
199 | #define BP_USBCTRL_GPTIMER0CTRL_GPTMODE 24 | ||
200 | #define BM_USBCTRL_GPTIMER0CTRL_GPTMODE 0x1000000 | ||
201 | #define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__ONESHOT 0x0 | ||
202 | #define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__REPEAT 0x1 | ||
203 | #define BF_USBCTRL_GPTIMER0CTRL_GPTMODE(v) (((v) << 24) & 0x1000000) | ||
204 | #define BF_USBCTRL_GPTIMER0CTRL_GPTMODE_V(v) ((BV_USBCTRL_GPTIMER0CTRL_GPTMODE__##v << 24) & 0x1000000) | ||
205 | #define BP_USBCTRL_GPTIMER0CTRL_GPTCNT 0 | ||
206 | #define BM_USBCTRL_GPTIMER0CTRL_GPTCNT 0xffffff | ||
207 | #define BF_USBCTRL_GPTIMER0CTRL_GPTCNT(v) (((v) << 0) & 0xffffff) | ||
208 | |||
209 | /** | ||
210 | * Register: HW_USBCTRL_GPTIMER1LD | ||
211 | * Address: 0x88 | ||
212 | * SCT: no | ||
213 | */ | ||
214 | #define HW_USBCTRL_GPTIMER1LD (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x88)) | ||
215 | #define BP_USBCTRL_GPTIMER1LD_RSVD0 24 | ||
216 | #define BM_USBCTRL_GPTIMER1LD_RSVD0 0xff000000 | ||
217 | #define BF_USBCTRL_GPTIMER1LD_RSVD0(v) (((v) << 24) & 0xff000000) | ||
218 | #define BP_USBCTRL_GPTIMER1LD_GPTLD 0 | ||
219 | #define BM_USBCTRL_GPTIMER1LD_GPTLD 0xffffff | ||
220 | #define BF_USBCTRL_GPTIMER1LD_GPTLD(v) (((v) << 0) & 0xffffff) | ||
221 | |||
222 | /** | ||
223 | * Register: HW_USBCTRL_GPTIMER1CTRL | ||
224 | * Address: 0x8c | ||
225 | * SCT: no | ||
226 | */ | ||
227 | #define HW_USBCTRL_GPTIMER1CTRL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8c)) | ||
228 | #define BP_USBCTRL_GPTIMER1CTRL_GPTRUN 31 | ||
229 | #define BM_USBCTRL_GPTIMER1CTRL_GPTRUN 0x80000000 | ||
230 | #define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__STOP 0x0 | ||
231 | #define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__RUN 0x1 | ||
232 | #define BF_USBCTRL_GPTIMER1CTRL_GPTRUN(v) (((v) << 31) & 0x80000000) | ||
233 | #define BF_USBCTRL_GPTIMER1CTRL_GPTRUN_V(v) ((BV_USBCTRL_GPTIMER1CTRL_GPTRUN__##v << 31) & 0x80000000) | ||
234 | #define BP_USBCTRL_GPTIMER1CTRL_GPTRST 30 | ||
235 | #define BM_USBCTRL_GPTIMER1CTRL_GPTRST 0x40000000 | ||
236 | #define BV_USBCTRL_GPTIMER1CTRL_GPTRST__NOACTION 0x0 | ||
237 | #define BV_USBCTRL_GPTIMER1CTRL_GPTRST__LOADCOUNTER 0x1 | ||
238 | #define BF_USBCTRL_GPTIMER1CTRL_GPTRST(v) (((v) << 30) & 0x40000000) | ||
239 | #define BF_USBCTRL_GPTIMER1CTRL_GPTRST_V(v) ((BV_USBCTRL_GPTIMER1CTRL_GPTRST__##v << 30) & 0x40000000) | ||
240 | #define BP_USBCTRL_GPTIMER1CTRL_RSVD0 25 | ||
241 | #define BM_USBCTRL_GPTIMER1CTRL_RSVD0 0x3e000000 | ||
242 | #define BF_USBCTRL_GPTIMER1CTRL_RSVD0(v) (((v) << 25) & 0x3e000000) | ||
243 | #define BP_USBCTRL_GPTIMER1CTRL_GPTMODE 24 | ||
244 | #define BM_USBCTRL_GPTIMER1CTRL_GPTMODE 0x1000000 | ||
245 | #define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__ONESHOT 0x0 | ||
246 | #define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__REPEAT 0x1 | ||
247 | #define BF_USBCTRL_GPTIMER1CTRL_GPTMODE(v) (((v) << 24) & 0x1000000) | ||
248 | #define BF_USBCTRL_GPTIMER1CTRL_GPTMODE_V(v) ((BV_USBCTRL_GPTIMER1CTRL_GPTMODE__##v << 24) & 0x1000000) | ||
249 | #define BP_USBCTRL_GPTIMER1CTRL_GPTCNT 0 | ||
250 | #define BM_USBCTRL_GPTIMER1CTRL_GPTCNT 0xffffff | ||
251 | #define BF_USBCTRL_GPTIMER1CTRL_GPTCNT(v) (((v) << 0) & 0xffffff) | ||
252 | |||
253 | /** | ||
254 | * Register: HW_USBCTRL_SBUSCFG | ||
255 | * Address: 0x90 | ||
256 | * SCT: no | ||
257 | */ | ||
258 | #define HW_USBCTRL_SBUSCFG (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x90)) | ||
259 | #define BP_USBCTRL_SBUSCFG_RSVD 3 | ||
260 | #define BM_USBCTRL_SBUSCFG_RSVD 0xfffffff8 | ||
261 | #define BF_USBCTRL_SBUSCFG_RSVD(v) (((v) << 3) & 0xfffffff8) | ||
262 | #define BP_USBCTRL_SBUSCFG_AHBBRST 0 | ||
263 | #define BM_USBCTRL_SBUSCFG_AHBBRST 0x7 | ||
264 | #define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR 0x0 | ||
265 | #define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR4 0x1 | ||
266 | #define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR8 0x2 | ||
267 | #define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR16 0x3 | ||
268 | #define BV_USBCTRL_SBUSCFG_AHBBRST__RESERVED 0x4 | ||
269 | #define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR4 0x5 | ||
270 | #define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR8 0x6 | ||
271 | #define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR16 0x7 | ||
272 | #define BF_USBCTRL_SBUSCFG_AHBBRST(v) (((v) << 0) & 0x7) | ||
273 | #define BF_USBCTRL_SBUSCFG_AHBBRST_V(v) ((BV_USBCTRL_SBUSCFG_AHBBRST__##v << 0) & 0x7) | ||
274 | |||
275 | /** | ||
276 | * Register: HW_USBCTRL_CAPLENGTH | ||
277 | * Address: 0x100 | ||
278 | * SCT: no | ||
279 | */ | ||
280 | #define HW_USBCTRL_CAPLENGTH (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x100)) | ||
281 | #define BP_USBCTRL_CAPLENGTH_HCIVERSION 16 | ||
282 | #define BM_USBCTRL_CAPLENGTH_HCIVERSION 0xffff0000 | ||
283 | #define BF_USBCTRL_CAPLENGTH_HCIVERSION(v) (((v) << 16) & 0xffff0000) | ||
284 | #define BP_USBCTRL_CAPLENGTH_RSVD 8 | ||
285 | #define BM_USBCTRL_CAPLENGTH_RSVD 0xff00 | ||
286 | #define BF_USBCTRL_CAPLENGTH_RSVD(v) (((v) << 8) & 0xff00) | ||
287 | #define BP_USBCTRL_CAPLENGTH_CAPLENGTH 0 | ||
288 | #define BM_USBCTRL_CAPLENGTH_CAPLENGTH 0xff | ||
289 | #define BF_USBCTRL_CAPLENGTH_CAPLENGTH(v) (((v) << 0) & 0xff) | ||
290 | |||
291 | /** | ||
292 | * Register: HW_USBCTRL_HCSPARAMS | ||
293 | * Address: 0x104 | ||
294 | * SCT: no | ||
295 | */ | ||
296 | #define HW_USBCTRL_HCSPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x104)) | ||
297 | #define BP_USBCTRL_HCSPARAMS_RSVD2 28 | ||
298 | #define BM_USBCTRL_HCSPARAMS_RSVD2 0xf0000000 | ||
299 | #define BF_USBCTRL_HCSPARAMS_RSVD2(v) (((v) << 28) & 0xf0000000) | ||
300 | #define BP_USBCTRL_HCSPARAMS_N_TT 24 | ||
301 | #define BM_USBCTRL_HCSPARAMS_N_TT 0xf000000 | ||
302 | #define BF_USBCTRL_HCSPARAMS_N_TT(v) (((v) << 24) & 0xf000000) | ||
303 | #define BP_USBCTRL_HCSPARAMS_N_PTT 20 | ||
304 | #define BM_USBCTRL_HCSPARAMS_N_PTT 0xf00000 | ||
305 | #define BF_USBCTRL_HCSPARAMS_N_PTT(v) (((v) << 20) & 0xf00000) | ||
306 | #define BP_USBCTRL_HCSPARAMS_RSVD1 17 | ||
307 | #define BM_USBCTRL_HCSPARAMS_RSVD1 0xe0000 | ||
308 | #define BF_USBCTRL_HCSPARAMS_RSVD1(v) (((v) << 17) & 0xe0000) | ||
309 | #define BP_USBCTRL_HCSPARAMS_PI 16 | ||
310 | #define BM_USBCTRL_HCSPARAMS_PI 0x10000 | ||
311 | #define BF_USBCTRL_HCSPARAMS_PI(v) (((v) << 16) & 0x10000) | ||
312 | #define BP_USBCTRL_HCSPARAMS_N_CC 12 | ||
313 | #define BM_USBCTRL_HCSPARAMS_N_CC 0xf000 | ||
314 | #define BF_USBCTRL_HCSPARAMS_N_CC(v) (((v) << 12) & 0xf000) | ||
315 | #define BP_USBCTRL_HCSPARAMS_N_PCC 8 | ||
316 | #define BM_USBCTRL_HCSPARAMS_N_PCC 0xf00 | ||
317 | #define BF_USBCTRL_HCSPARAMS_N_PCC(v) (((v) << 8) & 0xf00) | ||
318 | #define BP_USBCTRL_HCSPARAMS_RSVD0 5 | ||
319 | #define BM_USBCTRL_HCSPARAMS_RSVD0 0xe0 | ||
320 | #define BF_USBCTRL_HCSPARAMS_RSVD0(v) (((v) << 5) & 0xe0) | ||
321 | #define BP_USBCTRL_HCSPARAMS_PPC 4 | ||
322 | #define BM_USBCTRL_HCSPARAMS_PPC 0x10 | ||
323 | #define BF_USBCTRL_HCSPARAMS_PPC(v) (((v) << 4) & 0x10) | ||
324 | #define BP_USBCTRL_HCSPARAMS_N_PORTS 0 | ||
325 | #define BM_USBCTRL_HCSPARAMS_N_PORTS 0xf | ||
326 | #define BF_USBCTRL_HCSPARAMS_N_PORTS(v) (((v) << 0) & 0xf) | ||
327 | |||
328 | /** | ||
329 | * Register: HW_USBCTRL_HCCPARAMS | ||
330 | * Address: 0x108 | ||
331 | * SCT: no | ||
332 | */ | ||
333 | #define HW_USBCTRL_HCCPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x108)) | ||
334 | #define BP_USBCTRL_HCCPARAMS_RSVD2 16 | ||
335 | #define BM_USBCTRL_HCCPARAMS_RSVD2 0xffff0000 | ||
336 | #define BF_USBCTRL_HCCPARAMS_RSVD2(v) (((v) << 16) & 0xffff0000) | ||
337 | #define BP_USBCTRL_HCCPARAMS_EECP 8 | ||
338 | #define BM_USBCTRL_HCCPARAMS_EECP 0xff00 | ||
339 | #define BF_USBCTRL_HCCPARAMS_EECP(v) (((v) << 8) & 0xff00) | ||
340 | #define BP_USBCTRL_HCCPARAMS_IST 4 | ||
341 | #define BM_USBCTRL_HCCPARAMS_IST 0xf0 | ||
342 | #define BF_USBCTRL_HCCPARAMS_IST(v) (((v) << 4) & 0xf0) | ||
343 | #define BP_USBCTRL_HCCPARAMS_RSVD0 3 | ||
344 | #define BM_USBCTRL_HCCPARAMS_RSVD0 0x8 | ||
345 | #define BF_USBCTRL_HCCPARAMS_RSVD0(v) (((v) << 3) & 0x8) | ||
346 | #define BP_USBCTRL_HCCPARAMS_ASP 2 | ||
347 | #define BM_USBCTRL_HCCPARAMS_ASP 0x4 | ||
348 | #define BF_USBCTRL_HCCPARAMS_ASP(v) (((v) << 2) & 0x4) | ||
349 | #define BP_USBCTRL_HCCPARAMS_PFL 1 | ||
350 | #define BM_USBCTRL_HCCPARAMS_PFL 0x2 | ||
351 | #define BF_USBCTRL_HCCPARAMS_PFL(v) (((v) << 1) & 0x2) | ||
352 | #define BP_USBCTRL_HCCPARAMS_ADC 0 | ||
353 | #define BM_USBCTRL_HCCPARAMS_ADC 0x1 | ||
354 | #define BF_USBCTRL_HCCPARAMS_ADC(v) (((v) << 0) & 0x1) | ||
355 | |||
356 | /** | ||
357 | * Register: HW_USBCTRL_DCIVERSION | ||
358 | * Address: 0x120 | ||
359 | * SCT: no | ||
360 | */ | ||
361 | #define HW_USBCTRL_DCIVERSION (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x120)) | ||
362 | #define BP_USBCTRL_DCIVERSION_RSVD 16 | ||
363 | #define BM_USBCTRL_DCIVERSION_RSVD 0xffff0000 | ||
364 | #define BF_USBCTRL_DCIVERSION_RSVD(v) (((v) << 16) & 0xffff0000) | ||
365 | #define BP_USBCTRL_DCIVERSION_DCIVERSION 0 | ||
366 | #define BM_USBCTRL_DCIVERSION_DCIVERSION 0xffff | ||
367 | #define BF_USBCTRL_DCIVERSION_DCIVERSION(v) (((v) << 0) & 0xffff) | ||
368 | |||
369 | /** | ||
370 | * Register: HW_USBCTRL_DCCPARAMS | ||
371 | * Address: 0x124 | ||
372 | * SCT: no | ||
373 | */ | ||
374 | #define HW_USBCTRL_DCCPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x124)) | ||
375 | #define BP_USBCTRL_DCCPARAMS_RSVD1 9 | ||
376 | #define BM_USBCTRL_DCCPARAMS_RSVD1 0xfffffe00 | ||
377 | #define BF_USBCTRL_DCCPARAMS_RSVD1(v) (((v) << 9) & 0xfffffe00) | ||
378 | #define BP_USBCTRL_DCCPARAMS_HC 8 | ||
379 | #define BM_USBCTRL_DCCPARAMS_HC 0x100 | ||
380 | #define BF_USBCTRL_DCCPARAMS_HC(v) (((v) << 8) & 0x100) | ||
381 | #define BP_USBCTRL_DCCPARAMS_DC 7 | ||
382 | #define BM_USBCTRL_DCCPARAMS_DC 0x80 | ||
383 | #define BF_USBCTRL_DCCPARAMS_DC(v) (((v) << 7) & 0x80) | ||
384 | #define BP_USBCTRL_DCCPARAMS_RSVD2 5 | ||
385 | #define BM_USBCTRL_DCCPARAMS_RSVD2 0x60 | ||
386 | #define BF_USBCTRL_DCCPARAMS_RSVD2(v) (((v) << 5) & 0x60) | ||
387 | #define BP_USBCTRL_DCCPARAMS_DEN 0 | ||
388 | #define BM_USBCTRL_DCCPARAMS_DEN 0x1f | ||
389 | #define BF_USBCTRL_DCCPARAMS_DEN(v) (((v) << 0) & 0x1f) | ||
390 | |||
391 | /** | ||
392 | * Register: HW_USBCTRL_USBCMD | ||
393 | * Address: 0x140 | ||
394 | * SCT: no | ||
395 | */ | ||
396 | #define HW_USBCTRL_USBCMD (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x140)) | ||
397 | #define BP_USBCTRL_USBCMD_RSVD3 24 | ||
398 | #define BM_USBCTRL_USBCMD_RSVD3 0xff000000 | ||
399 | #define BF_USBCTRL_USBCMD_RSVD3(v) (((v) << 24) & 0xff000000) | ||
400 | #define BP_USBCTRL_USBCMD_ITC 16 | ||
401 | #define BM_USBCTRL_USBCMD_ITC 0xff0000 | ||
402 | #define BV_USBCTRL_USBCMD_ITC__IMM 0x0 | ||
403 | #define BV_USBCTRL_USBCMD_ITC__1_MICROFRAME 0x1 | ||
404 | #define BV_USBCTRL_USBCMD_ITC__2_MICROFRAME 0x2 | ||
405 | #define BV_USBCTRL_USBCMD_ITC__4_MICROFRAME 0x4 | ||
406 | #define BV_USBCTRL_USBCMD_ITC__8_MICROFRAME 0x8 | ||
407 | #define BV_USBCTRL_USBCMD_ITC__16_MICROFRAME 0x10 | ||
408 | #define BV_USBCTRL_USBCMD_ITC__32_MICROFRAME 0x20 | ||
409 | #define BV_USBCTRL_USBCMD_ITC__64_MICROFRAME 0x40 | ||
410 | #define BF_USBCTRL_USBCMD_ITC(v) (((v) << 16) & 0xff0000) | ||
411 | #define BF_USBCTRL_USBCMD_ITC_V(v) ((BV_USBCTRL_USBCMD_ITC__##v << 16) & 0xff0000) | ||
412 | #define BP_USBCTRL_USBCMD_FS2 15 | ||
413 | #define BM_USBCTRL_USBCMD_FS2 0x8000 | ||
414 | #define BF_USBCTRL_USBCMD_FS2(v) (((v) << 15) & 0x8000) | ||
415 | #define BP_USBCTRL_USBCMD_ATDTW 14 | ||
416 | #define BM_USBCTRL_USBCMD_ATDTW 0x4000 | ||
417 | #define BF_USBCTRL_USBCMD_ATDTW(v) (((v) << 14) & 0x4000) | ||
418 | #define BP_USBCTRL_USBCMD_SUTW 13 | ||
419 | #define BM_USBCTRL_USBCMD_SUTW 0x2000 | ||
420 | #define BF_USBCTRL_USBCMD_SUTW(v) (((v) << 13) & 0x2000) | ||
421 | #define BP_USBCTRL_USBCMD_RSVD2 12 | ||
422 | #define BM_USBCTRL_USBCMD_RSVD2 0x1000 | ||
423 | #define BF_USBCTRL_USBCMD_RSVD2(v) (((v) << 12) & 0x1000) | ||
424 | #define BP_USBCTRL_USBCMD_ASPE 11 | ||
425 | #define BM_USBCTRL_USBCMD_ASPE 0x800 | ||
426 | #define BF_USBCTRL_USBCMD_ASPE(v) (((v) << 11) & 0x800) | ||
427 | #define BP_USBCTRL_USBCMD_RSVD1 10 | ||
428 | #define BM_USBCTRL_USBCMD_RSVD1 0x400 | ||
429 | #define BF_USBCTRL_USBCMD_RSVD1(v) (((v) << 10) & 0x400) | ||
430 | #define BP_USBCTRL_USBCMD_ASP 8 | ||
431 | #define BM_USBCTRL_USBCMD_ASP 0x300 | ||
432 | #define BF_USBCTRL_USBCMD_ASP(v) (((v) << 8) & 0x300) | ||
433 | #define BP_USBCTRL_USBCMD_LR 7 | ||
434 | #define BM_USBCTRL_USBCMD_LR 0x80 | ||
435 | #define BF_USBCTRL_USBCMD_LR(v) (((v) << 7) & 0x80) | ||
436 | #define BP_USBCTRL_USBCMD_IAA 6 | ||
437 | #define BM_USBCTRL_USBCMD_IAA 0x40 | ||
438 | #define BF_USBCTRL_USBCMD_IAA(v) (((v) << 6) & 0x40) | ||
439 | #define BP_USBCTRL_USBCMD_ASE 5 | ||
440 | #define BM_USBCTRL_USBCMD_ASE 0x20 | ||
441 | #define BF_USBCTRL_USBCMD_ASE(v) (((v) << 5) & 0x20) | ||
442 | #define BP_USBCTRL_USBCMD_PSE 4 | ||
443 | #define BM_USBCTRL_USBCMD_PSE 0x10 | ||
444 | #define BF_USBCTRL_USBCMD_PSE(v) (((v) << 4) & 0x10) | ||
445 | #define BP_USBCTRL_USBCMD_FS1 3 | ||
446 | #define BM_USBCTRL_USBCMD_FS1 0x8 | ||
447 | #define BF_USBCTRL_USBCMD_FS1(v) (((v) << 3) & 0x8) | ||
448 | #define BP_USBCTRL_USBCMD_FS0 2 | ||
449 | #define BM_USBCTRL_USBCMD_FS0 0x4 | ||
450 | #define BF_USBCTRL_USBCMD_FS0(v) (((v) << 2) & 0x4) | ||
451 | #define BP_USBCTRL_USBCMD_RST 1 | ||
452 | #define BM_USBCTRL_USBCMD_RST 0x2 | ||
453 | #define BF_USBCTRL_USBCMD_RST(v) (((v) << 1) & 0x2) | ||
454 | #define BP_USBCTRL_USBCMD_RS 0 | ||
455 | #define BM_USBCTRL_USBCMD_RS 0x1 | ||
456 | #define BF_USBCTRL_USBCMD_RS(v) (((v) << 0) & 0x1) | ||
457 | |||
458 | /** | ||
459 | * Register: HW_USBCTRL_USBSTS | ||
460 | * Address: 0x144 | ||
461 | * SCT: no | ||
462 | */ | ||
463 | #define HW_USBCTRL_USBSTS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x144)) | ||
464 | #define BP_USBCTRL_USBSTS_RSVD5 26 | ||
465 | #define BM_USBCTRL_USBSTS_RSVD5 0xfc000000 | ||
466 | #define BF_USBCTRL_USBSTS_RSVD5(v) (((v) << 26) & 0xfc000000) | ||
467 | #define BP_USBCTRL_USBSTS_TI1 25 | ||
468 | #define BM_USBCTRL_USBSTS_TI1 0x2000000 | ||
469 | #define BF_USBCTRL_USBSTS_TI1(v) (((v) << 25) & 0x2000000) | ||
470 | #define BP_USBCTRL_USBSTS_TI0 24 | ||
471 | #define BM_USBCTRL_USBSTS_TI0 0x1000000 | ||
472 | #define BF_USBCTRL_USBSTS_TI0(v) (((v) << 24) & 0x1000000) | ||
473 | #define BP_USBCTRL_USBSTS_RSVD4 20 | ||
474 | #define BM_USBCTRL_USBSTS_RSVD4 0xf00000 | ||
475 | #define BF_USBCTRL_USBSTS_RSVD4(v) (((v) << 20) & 0xf00000) | ||
476 | #define BP_USBCTRL_USBSTS_UPI 19 | ||
477 | #define BM_USBCTRL_USBSTS_UPI 0x80000 | ||
478 | #define BF_USBCTRL_USBSTS_UPI(v) (((v) << 19) & 0x80000) | ||
479 | #define BP_USBCTRL_USBSTS_UAI 18 | ||
480 | #define BM_USBCTRL_USBSTS_UAI 0x40000 | ||
481 | #define BF_USBCTRL_USBSTS_UAI(v) (((v) << 18) & 0x40000) | ||
482 | #define BP_USBCTRL_USBSTS_RSVD3 17 | ||
483 | #define BM_USBCTRL_USBSTS_RSVD3 0x20000 | ||
484 | #define BF_USBCTRL_USBSTS_RSVD3(v) (((v) << 17) & 0x20000) | ||
485 | #define BP_USBCTRL_USBSTS_NAKI 16 | ||
486 | #define BM_USBCTRL_USBSTS_NAKI 0x10000 | ||
487 | #define BF_USBCTRL_USBSTS_NAKI(v) (((v) << 16) & 0x10000) | ||
488 | #define BP_USBCTRL_USBSTS_AS 15 | ||
489 | #define BM_USBCTRL_USBSTS_AS 0x8000 | ||
490 | #define BF_USBCTRL_USBSTS_AS(v) (((v) << 15) & 0x8000) | ||
491 | #define BP_USBCTRL_USBSTS_PS 14 | ||
492 | #define BM_USBCTRL_USBSTS_PS 0x4000 | ||
493 | #define BF_USBCTRL_USBSTS_PS(v) (((v) << 14) & 0x4000) | ||
494 | #define BP_USBCTRL_USBSTS_RCL 13 | ||
495 | #define BM_USBCTRL_USBSTS_RCL 0x2000 | ||
496 | #define BF_USBCTRL_USBSTS_RCL(v) (((v) << 13) & 0x2000) | ||
497 | #define BP_USBCTRL_USBSTS_HCH 12 | ||
498 | #define BM_USBCTRL_USBSTS_HCH 0x1000 | ||
499 | #define BF_USBCTRL_USBSTS_HCH(v) (((v) << 12) & 0x1000) | ||
500 | #define BP_USBCTRL_USBSTS_RSVD2 11 | ||
501 | #define BM_USBCTRL_USBSTS_RSVD2 0x800 | ||
502 | #define BF_USBCTRL_USBSTS_RSVD2(v) (((v) << 11) & 0x800) | ||
503 | #define BP_USBCTRL_USBSTS_ULPII 10 | ||
504 | #define BM_USBCTRL_USBSTS_ULPII 0x400 | ||
505 | #define BF_USBCTRL_USBSTS_ULPII(v) (((v) << 10) & 0x400) | ||
506 | #define BP_USBCTRL_USBSTS_RSVD1 9 | ||
507 | #define BM_USBCTRL_USBSTS_RSVD1 0x200 | ||
508 | #define BF_USBCTRL_USBSTS_RSVD1(v) (((v) << 9) & 0x200) | ||
509 | #define BP_USBCTRL_USBSTS_SLI 8 | ||
510 | #define BM_USBCTRL_USBSTS_SLI 0x100 | ||
511 | #define BF_USBCTRL_USBSTS_SLI(v) (((v) << 8) & 0x100) | ||
512 | #define BP_USBCTRL_USBSTS_SRI 7 | ||
513 | #define BM_USBCTRL_USBSTS_SRI 0x80 | ||
514 | #define BF_USBCTRL_USBSTS_SRI(v) (((v) << 7) & 0x80) | ||
515 | #define BP_USBCTRL_USBSTS_URI 6 | ||
516 | #define BM_USBCTRL_USBSTS_URI 0x40 | ||
517 | #define BF_USBCTRL_USBSTS_URI(v) (((v) << 6) & 0x40) | ||
518 | #define BP_USBCTRL_USBSTS_AAI 5 | ||
519 | #define BM_USBCTRL_USBSTS_AAI 0x20 | ||
520 | #define BF_USBCTRL_USBSTS_AAI(v) (((v) << 5) & 0x20) | ||
521 | #define BP_USBCTRL_USBSTS_SEI 4 | ||
522 | #define BM_USBCTRL_USBSTS_SEI 0x10 | ||
523 | #define BF_USBCTRL_USBSTS_SEI(v) (((v) << 4) & 0x10) | ||
524 | #define BP_USBCTRL_USBSTS_FRI 3 | ||
525 | #define BM_USBCTRL_USBSTS_FRI 0x8 | ||
526 | #define BF_USBCTRL_USBSTS_FRI(v) (((v) << 3) & 0x8) | ||
527 | #define BP_USBCTRL_USBSTS_PCI 2 | ||
528 | #define BM_USBCTRL_USBSTS_PCI 0x4 | ||
529 | #define BF_USBCTRL_USBSTS_PCI(v) (((v) << 2) & 0x4) | ||
530 | #define BP_USBCTRL_USBSTS_UEI 1 | ||
531 | #define BM_USBCTRL_USBSTS_UEI 0x2 | ||
532 | #define BF_USBCTRL_USBSTS_UEI(v) (((v) << 1) & 0x2) | ||
533 | #define BP_USBCTRL_USBSTS_UI 0 | ||
534 | #define BM_USBCTRL_USBSTS_UI 0x1 | ||
535 | #define BF_USBCTRL_USBSTS_UI(v) (((v) << 0) & 0x1) | ||
536 | |||
537 | /** | ||
538 | * Register: HW_USBCTRL_USBINTR | ||
539 | * Address: 0x148 | ||
540 | * SCT: no | ||
541 | */ | ||
542 | #define HW_USBCTRL_USBINTR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x148)) | ||
543 | #define BP_USBCTRL_USBINTR_RSVD5 26 | ||
544 | #define BM_USBCTRL_USBINTR_RSVD5 0xfc000000 | ||
545 | #define BF_USBCTRL_USBINTR_RSVD5(v) (((v) << 26) & 0xfc000000) | ||
546 | #define BP_USBCTRL_USBINTR_TIE1 25 | ||
547 | #define BM_USBCTRL_USBINTR_TIE1 0x2000000 | ||
548 | #define BF_USBCTRL_USBINTR_TIE1(v) (((v) << 25) & 0x2000000) | ||
549 | #define BP_USBCTRL_USBINTR_TIE0 24 | ||
550 | #define BM_USBCTRL_USBINTR_TIE0 0x1000000 | ||
551 | #define BF_USBCTRL_USBINTR_TIE0(v) (((v) << 24) & 0x1000000) | ||
552 | #define BP_USBCTRL_USBINTR_RSVD4 20 | ||
553 | #define BM_USBCTRL_USBINTR_RSVD4 0xf00000 | ||
554 | #define BF_USBCTRL_USBINTR_RSVD4(v) (((v) << 20) & 0xf00000) | ||
555 | #define BP_USBCTRL_USBINTR_UPIE 19 | ||
556 | #define BM_USBCTRL_USBINTR_UPIE 0x80000 | ||
557 | #define BF_USBCTRL_USBINTR_UPIE(v) (((v) << 19) & 0x80000) | ||
558 | #define BP_USBCTRL_USBINTR_UAIE 18 | ||
559 | #define BM_USBCTRL_USBINTR_UAIE 0x40000 | ||
560 | #define BF_USBCTRL_USBINTR_UAIE(v) (((v) << 18) & 0x40000) | ||
561 | #define BP_USBCTRL_USBINTR_RSVD3 17 | ||
562 | #define BM_USBCTRL_USBINTR_RSVD3 0x20000 | ||
563 | #define BF_USBCTRL_USBINTR_RSVD3(v) (((v) << 17) & 0x20000) | ||
564 | #define BP_USBCTRL_USBINTR_NAKE 16 | ||
565 | #define BM_USBCTRL_USBINTR_NAKE 0x10000 | ||
566 | #define BF_USBCTRL_USBINTR_NAKE(v) (((v) << 16) & 0x10000) | ||
567 | #define BP_USBCTRL_USBINTR_RSVD2 11 | ||
568 | #define BM_USBCTRL_USBINTR_RSVD2 0xf800 | ||
569 | #define BF_USBCTRL_USBINTR_RSVD2(v) (((v) << 11) & 0xf800) | ||
570 | #define BP_USBCTRL_USBINTR_ULPIE 10 | ||
571 | #define BM_USBCTRL_USBINTR_ULPIE 0x400 | ||
572 | #define BF_USBCTRL_USBINTR_ULPIE(v) (((v) << 10) & 0x400) | ||
573 | #define BP_USBCTRL_USBINTR_RSVD1 9 | ||
574 | #define BM_USBCTRL_USBINTR_RSVD1 0x200 | ||
575 | #define BF_USBCTRL_USBINTR_RSVD1(v) (((v) << 9) & 0x200) | ||
576 | #define BP_USBCTRL_USBINTR_SLE 8 | ||
577 | #define BM_USBCTRL_USBINTR_SLE 0x100 | ||
578 | #define BF_USBCTRL_USBINTR_SLE(v) (((v) << 8) & 0x100) | ||
579 | #define BP_USBCTRL_USBINTR_SRE 7 | ||
580 | #define BM_USBCTRL_USBINTR_SRE 0x80 | ||
581 | #define BF_USBCTRL_USBINTR_SRE(v) (((v) << 7) & 0x80) | ||
582 | #define BP_USBCTRL_USBINTR_URE 6 | ||
583 | #define BM_USBCTRL_USBINTR_URE 0x40 | ||
584 | #define BF_USBCTRL_USBINTR_URE(v) (((v) << 6) & 0x40) | ||
585 | #define BP_USBCTRL_USBINTR_AAE 5 | ||
586 | #define BM_USBCTRL_USBINTR_AAE 0x20 | ||
587 | #define BF_USBCTRL_USBINTR_AAE(v) (((v) << 5) & 0x20) | ||
588 | #define BP_USBCTRL_USBINTR_SEE 4 | ||
589 | #define BM_USBCTRL_USBINTR_SEE 0x10 | ||
590 | #define BF_USBCTRL_USBINTR_SEE(v) (((v) << 4) & 0x10) | ||
591 | #define BP_USBCTRL_USBINTR_FRE 3 | ||
592 | #define BM_USBCTRL_USBINTR_FRE 0x8 | ||
593 | #define BF_USBCTRL_USBINTR_FRE(v) (((v) << 3) & 0x8) | ||
594 | #define BP_USBCTRL_USBINTR_PCE 2 | ||
595 | #define BM_USBCTRL_USBINTR_PCE 0x4 | ||
596 | #define BF_USBCTRL_USBINTR_PCE(v) (((v) << 2) & 0x4) | ||
597 | #define BP_USBCTRL_USBINTR_UEE 1 | ||
598 | #define BM_USBCTRL_USBINTR_UEE 0x2 | ||
599 | #define BF_USBCTRL_USBINTR_UEE(v) (((v) << 1) & 0x2) | ||
600 | #define BP_USBCTRL_USBINTR_UE 0 | ||
601 | #define BM_USBCTRL_USBINTR_UE 0x1 | ||
602 | #define BF_USBCTRL_USBINTR_UE(v) (((v) << 0) & 0x1) | ||
603 | |||
604 | /** | ||
605 | * Register: HW_USBCTRL_FRINDEX | ||
606 | * Address: 0x14c | ||
607 | * SCT: no | ||
608 | */ | ||
609 | #define HW_USBCTRL_FRINDEX (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14c)) | ||
610 | #define BP_USBCTRL_FRINDEX_RSVD 14 | ||
611 | #define BM_USBCTRL_FRINDEX_RSVD 0xffffc000 | ||
612 | #define BF_USBCTRL_FRINDEX_RSVD(v) (((v) << 14) & 0xffffc000) | ||
613 | #define BP_USBCTRL_FRINDEX_FRINDEX 3 | ||
614 | #define BM_USBCTRL_FRINDEX_FRINDEX 0x3ff8 | ||
615 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_12 0xc | ||
616 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_11 0xb | ||
617 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_10 0xa | ||
618 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_9 0x9 | ||
619 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_8 0x8 | ||
620 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_7 0x7 | ||
621 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_6 0x6 | ||
622 | #define BV_USBCTRL_FRINDEX_FRINDEX__N_5 0x5 | ||
623 | #define BF_USBCTRL_FRINDEX_FRINDEX(v) (((v) << 3) & 0x3ff8) | ||
624 | #define BF_USBCTRL_FRINDEX_FRINDEX_V(v) ((BV_USBCTRL_FRINDEX_FRINDEX__##v << 3) & 0x3ff8) | ||
625 | #define BP_USBCTRL_FRINDEX_UINDEX 0 | ||
626 | #define BM_USBCTRL_FRINDEX_UINDEX 0x7 | ||
627 | #define BF_USBCTRL_FRINDEX_UINDEX(v) (((v) << 0) & 0x7) | ||
628 | |||
629 | /** | ||
630 | * Register: HW_USBCTRL_PERIODICLISTBASE | ||
631 | * Address: 0x154 | ||
632 | * SCT: no | ||
633 | */ | ||
634 | #define HW_USBCTRL_PERIODICLISTBASE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154)) | ||
635 | #define BP_USBCTRL_PERIODICLISTBASE_PERBASE 12 | ||
636 | #define BM_USBCTRL_PERIODICLISTBASE_PERBASE 0xfffff000 | ||
637 | #define BF_USBCTRL_PERIODICLISTBASE_PERBASE(v) (((v) << 12) & 0xfffff000) | ||
638 | #define BP_USBCTRL_PERIODICLISTBASE_RSVD 0 | ||
639 | #define BM_USBCTRL_PERIODICLISTBASE_RSVD 0xfff | ||
640 | #define BF_USBCTRL_PERIODICLISTBASE_RSVD(v) (((v) << 0) & 0xfff) | ||
641 | |||
642 | /** | ||
643 | * Register: HW_USBCTRL_DEVICEADDR | ||
644 | * Address: 0x154 | ||
645 | * SCT: no | ||
646 | */ | ||
647 | #define HW_USBCTRL_DEVICEADDR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154)) | ||
648 | #define BP_USBCTRL_DEVICEADDR_USBADR 25 | ||
649 | #define BM_USBCTRL_DEVICEADDR_USBADR 0xfe000000 | ||
650 | #define BF_USBCTRL_DEVICEADDR_USBADR(v) (((v) << 25) & 0xfe000000) | ||
651 | #define BP_USBCTRL_DEVICEADDR_USBADRA 24 | ||
652 | #define BM_USBCTRL_DEVICEADDR_USBADRA 0x1000000 | ||
653 | #define BF_USBCTRL_DEVICEADDR_USBADRA(v) (((v) << 24) & 0x1000000) | ||
654 | #define BP_USBCTRL_DEVICEADDR_RSVD 0 | ||
655 | #define BM_USBCTRL_DEVICEADDR_RSVD 0xffffff | ||
656 | #define BF_USBCTRL_DEVICEADDR_RSVD(v) (((v) << 0) & 0xffffff) | ||
657 | |||
658 | /** | ||
659 | * Register: HW_USBCTRL_ASYNCLISTADDR | ||
660 | * Address: 0x158 | ||
661 | * SCT: no | ||
662 | */ | ||
663 | #define HW_USBCTRL_ASYNCLISTADDR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158)) | ||
664 | #define BP_USBCTRL_ASYNCLISTADDR_ASYBASE 5 | ||
665 | #define BM_USBCTRL_ASYNCLISTADDR_ASYBASE 0xffffffe0 | ||
666 | #define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) (((v) << 5) & 0xffffffe0) | ||
667 | #define BP_USBCTRL_ASYNCLISTADDR_RSVD 0 | ||
668 | #define BM_USBCTRL_ASYNCLISTADDR_RSVD 0x1f | ||
669 | #define BF_USBCTRL_ASYNCLISTADDR_RSVD(v) (((v) << 0) & 0x1f) | ||
670 | |||
671 | /** | ||
672 | * Register: HW_USBCTRL_ENDPOINTLISTADDR | ||
673 | * Address: 0x158 | ||
674 | * SCT: no | ||
675 | */ | ||
676 | #define HW_USBCTRL_ENDPOINTLISTADDR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158)) | ||
677 | #define BP_USBCTRL_ENDPOINTLISTADDR_EPBASE 11 | ||
678 | #define BM_USBCTRL_ENDPOINTLISTADDR_EPBASE 0xfffff800 | ||
679 | #define BF_USBCTRL_ENDPOINTLISTADDR_EPBASE(v) (((v) << 11) & 0xfffff800) | ||
680 | #define BP_USBCTRL_ENDPOINTLISTADDR_RSVD 0 | ||
681 | #define BM_USBCTRL_ENDPOINTLISTADDR_RSVD 0x7ff | ||
682 | #define BF_USBCTRL_ENDPOINTLISTADDR_RSVD(v) (((v) << 0) & 0x7ff) | ||
683 | |||
684 | /** | ||
685 | * Register: HW_USBCTRL_TTCTRL | ||
686 | * Address: 0x15c | ||
687 | * SCT: no | ||
688 | */ | ||
689 | #define HW_USBCTRL_TTCTRL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x15c)) | ||
690 | #define BP_USBCTRL_TTCTRL_RSVD1 31 | ||
691 | #define BM_USBCTRL_TTCTRL_RSVD1 0x80000000 | ||
692 | #define BF_USBCTRL_TTCTRL_RSVD1(v) (((v) << 31) & 0x80000000) | ||
693 | #define BP_USBCTRL_TTCTRL_TTHA 24 | ||
694 | #define BM_USBCTRL_TTCTRL_TTHA 0x7f000000 | ||
695 | #define BF_USBCTRL_TTCTRL_TTHA(v) (((v) << 24) & 0x7f000000) | ||
696 | #define BP_USBCTRL_TTCTRL_RSVD2 0 | ||
697 | #define BM_USBCTRL_TTCTRL_RSVD2 0xffffff | ||
698 | #define BF_USBCTRL_TTCTRL_RSVD2(v) (((v) << 0) & 0xffffff) | ||
699 | |||
700 | /** | ||
701 | * Register: HW_USBCTRL_BURSTSIZE | ||
702 | * Address: 0x160 | ||
703 | * SCT: no | ||
704 | */ | ||
705 | #define HW_USBCTRL_BURSTSIZE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x160)) | ||
706 | #define BP_USBCTRL_BURSTSIZE_RSVD 16 | ||
707 | #define BM_USBCTRL_BURSTSIZE_RSVD 0xffff0000 | ||
708 | #define BF_USBCTRL_BURSTSIZE_RSVD(v) (((v) << 16) & 0xffff0000) | ||
709 | #define BP_USBCTRL_BURSTSIZE_TXPBURST 8 | ||
710 | #define BM_USBCTRL_BURSTSIZE_TXPBURST 0xff00 | ||
711 | #define BF_USBCTRL_BURSTSIZE_TXPBURST(v) (((v) << 8) & 0xff00) | ||
712 | #define BP_USBCTRL_BURSTSIZE_RXPBURST 0 | ||
713 | #define BM_USBCTRL_BURSTSIZE_RXPBURST 0xff | ||
714 | #define BF_USBCTRL_BURSTSIZE_RXPBURST(v) (((v) << 0) & 0xff) | ||
715 | |||
716 | /** | ||
717 | * Register: HW_USBCTRL_TXFILLTUNING | ||
718 | * Address: 0x164 | ||
719 | * SCT: no | ||
720 | */ | ||
721 | #define HW_USBCTRL_TXFILLTUNING (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x164)) | ||
722 | #define BP_USBCTRL_TXFILLTUNING_RSVD2 22 | ||
723 | #define BM_USBCTRL_TXFILLTUNING_RSVD2 0xffc00000 | ||
724 | #define BF_USBCTRL_TXFILLTUNING_RSVD2(v) (((v) << 22) & 0xffc00000) | ||
725 | #define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES 16 | ||
726 | #define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES 0x3f0000 | ||
727 | #define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v) (((v) << 16) & 0x3f0000) | ||
728 | #define BP_USBCTRL_TXFILLTUNING_RSVD1 13 | ||
729 | #define BM_USBCTRL_TXFILLTUNING_RSVD1 0xe000 | ||
730 | #define BF_USBCTRL_TXFILLTUNING_RSVD1(v) (((v) << 13) & 0xe000) | ||
731 | #define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH 8 | ||
732 | #define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH 0x1f00 | ||
733 | #define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v) (((v) << 8) & 0x1f00) | ||
734 | #define BP_USBCTRL_TXFILLTUNING_RSVD0 7 | ||
735 | #define BM_USBCTRL_TXFILLTUNING_RSVD0 0x80 | ||
736 | #define BF_USBCTRL_TXFILLTUNING_RSVD0(v) (((v) << 7) & 0x80) | ||
737 | #define BP_USBCTRL_TXFILLTUNING_TXSCHOH 0 | ||
738 | #define BM_USBCTRL_TXFILLTUNING_TXSCHOH 0x7f | ||
739 | #define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v) (((v) << 0) & 0x7f) | ||
740 | |||
741 | /** | ||
742 | * Register: HW_USBCTRL_IC_USB | ||
743 | * Address: 0x16c | ||
744 | * SCT: no | ||
745 | */ | ||
746 | #define HW_USBCTRL_IC_USB (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x16c)) | ||
747 | #define BP_USBCTRL_IC_USB_RSVD 4 | ||
748 | #define BM_USBCTRL_IC_USB_RSVD 0xfffffff0 | ||
749 | #define BF_USBCTRL_IC_USB_RSVD(v) (((v) << 4) & 0xfffffff0) | ||
750 | #define BP_USBCTRL_IC_USB_IC_ENABLE 3 | ||
751 | #define BM_USBCTRL_IC_USB_IC_ENABLE 0x8 | ||
752 | #define BF_USBCTRL_IC_USB_IC_ENABLE(v) (((v) << 3) & 0x8) | ||
753 | #define BP_USBCTRL_IC_USB_IC_VDD 0 | ||
754 | #define BM_USBCTRL_IC_USB_IC_VDD 0x7 | ||
755 | #define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_NONE 0x0 | ||
756 | #define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_0 0x1 | ||
757 | #define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_2 0x2 | ||
758 | #define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_5 0x3 | ||
759 | #define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_8 0x4 | ||
760 | #define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_3_0 0x5 | ||
761 | #define BV_USBCTRL_IC_USB_IC_VDD__RESERVED0 0x6 | ||
762 | #define BV_USBCTRL_IC_USB_IC_VDD__RESERVED1 0x7 | ||
763 | #define BF_USBCTRL_IC_USB_IC_VDD(v) (((v) << 0) & 0x7) | ||
764 | #define BF_USBCTRL_IC_USB_IC_VDD_V(v) ((BV_USBCTRL_IC_USB_IC_VDD__##v << 0) & 0x7) | ||
765 | |||
766 | /** | ||
767 | * Register: HW_USBCTRL_ULPI | ||
768 | * Address: 0x170 | ||
769 | * SCT: no | ||
770 | */ | ||
771 | #define HW_USBCTRL_ULPI (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x170)) | ||
772 | #define BP_USBCTRL_ULPI_ULPIWU 31 | ||
773 | #define BM_USBCTRL_ULPI_ULPIWU 0x80000000 | ||
774 | #define BF_USBCTRL_ULPI_ULPIWU(v) (((v) << 31) & 0x80000000) | ||
775 | #define BP_USBCTRL_ULPI_ULPIRUN 30 | ||
776 | #define BM_USBCTRL_ULPI_ULPIRUN 0x40000000 | ||
777 | #define BF_USBCTRL_ULPI_ULPIRUN(v) (((v) << 30) & 0x40000000) | ||
778 | #define BP_USBCTRL_ULPI_ULPIRW 29 | ||
779 | #define BM_USBCTRL_ULPI_ULPIRW 0x20000000 | ||
780 | #define BF_USBCTRL_ULPI_ULPIRW(v) (((v) << 29) & 0x20000000) | ||
781 | #define BP_USBCTRL_ULPI_RSVD0 28 | ||
782 | #define BM_USBCTRL_ULPI_RSVD0 0x10000000 | ||
783 | #define BF_USBCTRL_ULPI_RSVD0(v) (((v) << 28) & 0x10000000) | ||
784 | #define BP_USBCTRL_ULPI_ULPISS 27 | ||
785 | #define BM_USBCTRL_ULPI_ULPISS 0x8000000 | ||
786 | #define BF_USBCTRL_ULPI_ULPISS(v) (((v) << 27) & 0x8000000) | ||
787 | #define BP_USBCTRL_ULPI_ULPIPORT 24 | ||
788 | #define BM_USBCTRL_ULPI_ULPIPORT 0x7000000 | ||
789 | #define BF_USBCTRL_ULPI_ULPIPORT(v) (((v) << 24) & 0x7000000) | ||
790 | #define BP_USBCTRL_ULPI_ULPIADDR 16 | ||
791 | #define BM_USBCTRL_ULPI_ULPIADDR 0xff0000 | ||
792 | #define BF_USBCTRL_ULPI_ULPIADDR(v) (((v) << 16) & 0xff0000) | ||
793 | #define BP_USBCTRL_ULPI_ULPIDATRD 8 | ||
794 | #define BM_USBCTRL_ULPI_ULPIDATRD 0xff00 | ||
795 | #define BF_USBCTRL_ULPI_ULPIDATRD(v) (((v) << 8) & 0xff00) | ||
796 | #define BP_USBCTRL_ULPI_ULPIDATWR 0 | ||
797 | #define BM_USBCTRL_ULPI_ULPIDATWR 0xff | ||
798 | #define BF_USBCTRL_ULPI_ULPIDATWR(v) (((v) << 0) & 0xff) | ||
799 | |||
800 | /** | ||
801 | * Register: HW_USBCTRL_ENDPTNAK | ||
802 | * Address: 0x178 | ||
803 | * SCT: no | ||
804 | */ | ||
805 | #define HW_USBCTRL_ENDPTNAK (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x178)) | ||
806 | #define BP_USBCTRL_ENDPTNAK_RSVD1 21 | ||
807 | #define BM_USBCTRL_ENDPTNAK_RSVD1 0xffe00000 | ||
808 | #define BF_USBCTRL_ENDPTNAK_RSVD1(v) (((v) << 21) & 0xffe00000) | ||
809 | #define BP_USBCTRL_ENDPTNAK_EPTN 16 | ||
810 | #define BM_USBCTRL_ENDPTNAK_EPTN 0x1f0000 | ||
811 | #define BF_USBCTRL_ENDPTNAK_EPTN(v) (((v) << 16) & 0x1f0000) | ||
812 | #define BP_USBCTRL_ENDPTNAK_RSVD0 5 | ||
813 | #define BM_USBCTRL_ENDPTNAK_RSVD0 0xffe0 | ||
814 | #define BF_USBCTRL_ENDPTNAK_RSVD0(v) (((v) << 5) & 0xffe0) | ||
815 | #define BP_USBCTRL_ENDPTNAK_EPRN 0 | ||
816 | #define BM_USBCTRL_ENDPTNAK_EPRN 0x1f | ||
817 | #define BF_USBCTRL_ENDPTNAK_EPRN(v) (((v) << 0) & 0x1f) | ||
818 | |||
819 | /** | ||
820 | * Register: HW_USBCTRL_ENDPTNAKEN | ||
821 | * Address: 0x17c | ||
822 | * SCT: no | ||
823 | */ | ||
824 | #define HW_USBCTRL_ENDPTNAKEN (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x17c)) | ||
825 | #define BP_USBCTRL_ENDPTNAKEN_RSVD1 21 | ||
826 | #define BM_USBCTRL_ENDPTNAKEN_RSVD1 0xffe00000 | ||
827 | #define BF_USBCTRL_ENDPTNAKEN_RSVD1(v) (((v) << 21) & 0xffe00000) | ||
828 | #define BP_USBCTRL_ENDPTNAKEN_EPTNE 16 | ||
829 | #define BM_USBCTRL_ENDPTNAKEN_EPTNE 0x1f0000 | ||
830 | #define BF_USBCTRL_ENDPTNAKEN_EPTNE(v) (((v) << 16) & 0x1f0000) | ||
831 | #define BP_USBCTRL_ENDPTNAKEN_RSVD0 5 | ||
832 | #define BM_USBCTRL_ENDPTNAKEN_RSVD0 0xffe0 | ||
833 | #define BF_USBCTRL_ENDPTNAKEN_RSVD0(v) (((v) << 5) & 0xffe0) | ||
834 | #define BP_USBCTRL_ENDPTNAKEN_EPRNE 0 | ||
835 | #define BM_USBCTRL_ENDPTNAKEN_EPRNE 0x1f | ||
836 | #define BF_USBCTRL_ENDPTNAKEN_EPRNE(v) (((v) << 0) & 0x1f) | ||
837 | |||
838 | /** | ||
839 | * Register: HW_USBCTRL_PORTSC1 | ||
840 | * Address: 0x184 | ||
841 | * SCT: no | ||
842 | */ | ||
843 | #define HW_USBCTRL_PORTSC1 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x184)) | ||
844 | #define BP_USBCTRL_PORTSC1_PTS 30 | ||
845 | #define BM_USBCTRL_PORTSC1_PTS 0xc0000000 | ||
846 | #define BV_USBCTRL_PORTSC1_PTS__UTMI 0x0 | ||
847 | #define BV_USBCTRL_PORTSC1_PTS__PHIL 0x1 | ||
848 | #define BV_USBCTRL_PORTSC1_PTS__ULPI 0x2 | ||
849 | #define BV_USBCTRL_PORTSC1_PTS__SERIAL 0x3 | ||
850 | #define BF_USBCTRL_PORTSC1_PTS(v) (((v) << 30) & 0xc0000000) | ||
851 | #define BF_USBCTRL_PORTSC1_PTS_V(v) ((BV_USBCTRL_PORTSC1_PTS__##v << 30) & 0xc0000000) | ||
852 | #define BP_USBCTRL_PORTSC1_STS 29 | ||
853 | #define BM_USBCTRL_PORTSC1_STS 0x20000000 | ||
854 | #define BF_USBCTRL_PORTSC1_STS(v) (((v) << 29) & 0x20000000) | ||
855 | #define BP_USBCTRL_PORTSC1_PTW 28 | ||
856 | #define BM_USBCTRL_PORTSC1_PTW 0x10000000 | ||
857 | #define BF_USBCTRL_PORTSC1_PTW(v) (((v) << 28) & 0x10000000) | ||
858 | #define BP_USBCTRL_PORTSC1_PSPD 26 | ||
859 | #define BM_USBCTRL_PORTSC1_PSPD 0xc000000 | ||
860 | #define BV_USBCTRL_PORTSC1_PSPD__FULL 0x0 | ||
861 | #define BV_USBCTRL_PORTSC1_PSPD__LOW 0x1 | ||
862 | #define BV_USBCTRL_PORTSC1_PSPD__HIGH 0x2 | ||
863 | #define BF_USBCTRL_PORTSC1_PSPD(v) (((v) << 26) & 0xc000000) | ||
864 | #define BF_USBCTRL_PORTSC1_PSPD_V(v) ((BV_USBCTRL_PORTSC1_PSPD__##v << 26) & 0xc000000) | ||
865 | #define BP_USBCTRL_PORTSC1_SRT 25 | ||
866 | #define BM_USBCTRL_PORTSC1_SRT 0x2000000 | ||
867 | #define BF_USBCTRL_PORTSC1_SRT(v) (((v) << 25) & 0x2000000) | ||
868 | #define BP_USBCTRL_PORTSC1_PFSC 24 | ||
869 | #define BM_USBCTRL_PORTSC1_PFSC 0x1000000 | ||
870 | #define BF_USBCTRL_PORTSC1_PFSC(v) (((v) << 24) & 0x1000000) | ||
871 | #define BP_USBCTRL_PORTSC1_PHCD 23 | ||
872 | #define BM_USBCTRL_PORTSC1_PHCD 0x800000 | ||
873 | #define BF_USBCTRL_PORTSC1_PHCD(v) (((v) << 23) & 0x800000) | ||
874 | #define BP_USBCTRL_PORTSC1_WKOC 22 | ||
875 | #define BM_USBCTRL_PORTSC1_WKOC 0x400000 | ||
876 | #define BF_USBCTRL_PORTSC1_WKOC(v) (((v) << 22) & 0x400000) | ||
877 | #define BP_USBCTRL_PORTSC1_WKDS 21 | ||
878 | #define BM_USBCTRL_PORTSC1_WKDS 0x200000 | ||
879 | #define BF_USBCTRL_PORTSC1_WKDS(v) (((v) << 21) & 0x200000) | ||
880 | #define BP_USBCTRL_PORTSC1_WKCN 20 | ||
881 | #define BM_USBCTRL_PORTSC1_WKCN 0x100000 | ||
882 | #define BF_USBCTRL_PORTSC1_WKCN(v) (((v) << 20) & 0x100000) | ||
883 | #define BP_USBCTRL_PORTSC1_PTC 16 | ||
884 | #define BM_USBCTRL_PORTSC1_PTC 0xf0000 | ||
885 | #define BV_USBCTRL_PORTSC1_PTC__TEST_DISABLE 0x0 | ||
886 | #define BV_USBCTRL_PORTSC1_PTC__TEST_J_STATE 0x1 | ||
887 | #define BV_USBCTRL_PORTSC1_PTC__TEST_K_STATE 0x2 | ||
888 | #define BV_USBCTRL_PORTSC1_PTC__TEST_J_SE0_NAK 0x3 | ||
889 | #define BV_USBCTRL_PORTSC1_PTC__TEST_PACKET 0x4 | ||
890 | #define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_HS 0x5 | ||
891 | #define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_FS 0x6 | ||
892 | #define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_LS 0x7 | ||
893 | #define BF_USBCTRL_PORTSC1_PTC(v) (((v) << 16) & 0xf0000) | ||
894 | #define BF_USBCTRL_PORTSC1_PTC_V(v) ((BV_USBCTRL_PORTSC1_PTC__##v << 16) & 0xf0000) | ||
895 | #define BP_USBCTRL_PORTSC1_PIC 14 | ||
896 | #define BM_USBCTRL_PORTSC1_PIC 0xc000 | ||
897 | #define BV_USBCTRL_PORTSC1_PIC__OFF 0x0 | ||
898 | #define BV_USBCTRL_PORTSC1_PIC__AMBER 0x1 | ||
899 | #define BV_USBCTRL_PORTSC1_PIC__GREEN 0x2 | ||
900 | #define BV_USBCTRL_PORTSC1_PIC__UNDEF 0x3 | ||
901 | #define BF_USBCTRL_PORTSC1_PIC(v) (((v) << 14) & 0xc000) | ||
902 | #define BF_USBCTRL_PORTSC1_PIC_V(v) ((BV_USBCTRL_PORTSC1_PIC__##v << 14) & 0xc000) | ||
903 | #define BP_USBCTRL_PORTSC1_PO 13 | ||
904 | #define BM_USBCTRL_PORTSC1_PO 0x2000 | ||
905 | #define BF_USBCTRL_PORTSC1_PO(v) (((v) << 13) & 0x2000) | ||
906 | #define BP_USBCTRL_PORTSC1_PP 12 | ||
907 | #define BM_USBCTRL_PORTSC1_PP 0x1000 | ||
908 | #define BF_USBCTRL_PORTSC1_PP(v) (((v) << 12) & 0x1000) | ||
909 | #define BP_USBCTRL_PORTSC1_LS 10 | ||
910 | #define BM_USBCTRL_PORTSC1_LS 0xc00 | ||
911 | #define BV_USBCTRL_PORTSC1_LS__SE0 0x0 | ||
912 | #define BV_USBCTRL_PORTSC1_LS__K_STATE 0x1 | ||
913 | #define BV_USBCTRL_PORTSC1_LS__J_STATE 0x2 | ||
914 | #define BV_USBCTRL_PORTSC1_LS__UNDEF 0x3 | ||
915 | #define BF_USBCTRL_PORTSC1_LS(v) (((v) << 10) & 0xc00) | ||
916 | #define BF_USBCTRL_PORTSC1_LS_V(v) ((BV_USBCTRL_PORTSC1_LS__##v << 10) & 0xc00) | ||
917 | #define BP_USBCTRL_PORTSC1_HSP 9 | ||
918 | #define BM_USBCTRL_PORTSC1_HSP 0x200 | ||
919 | #define BF_USBCTRL_PORTSC1_HSP(v) (((v) << 9) & 0x200) | ||
920 | #define BP_USBCTRL_PORTSC1_PR 8 | ||
921 | #define BM_USBCTRL_PORTSC1_PR 0x100 | ||
922 | #define BF_USBCTRL_PORTSC1_PR(v) (((v) << 8) & 0x100) | ||
923 | #define BP_USBCTRL_PORTSC1_SUSP 7 | ||
924 | #define BM_USBCTRL_PORTSC1_SUSP 0x80 | ||
925 | #define BF_USBCTRL_PORTSC1_SUSP(v) (((v) << 7) & 0x80) | ||
926 | #define BP_USBCTRL_PORTSC1_FPR 6 | ||
927 | #define BM_USBCTRL_PORTSC1_FPR 0x40 | ||
928 | #define BF_USBCTRL_PORTSC1_FPR(v) (((v) << 6) & 0x40) | ||
929 | #define BP_USBCTRL_PORTSC1_OCC 5 | ||
930 | #define BM_USBCTRL_PORTSC1_OCC 0x20 | ||
931 | #define BF_USBCTRL_PORTSC1_OCC(v) (((v) << 5) & 0x20) | ||
932 | #define BP_USBCTRL_PORTSC1_OCA 4 | ||
933 | #define BM_USBCTRL_PORTSC1_OCA 0x10 | ||
934 | #define BF_USBCTRL_PORTSC1_OCA(v) (((v) << 4) & 0x10) | ||
935 | #define BP_USBCTRL_PORTSC1_PEC 3 | ||
936 | #define BM_USBCTRL_PORTSC1_PEC 0x8 | ||
937 | #define BF_USBCTRL_PORTSC1_PEC(v) (((v) << 3) & 0x8) | ||
938 | #define BP_USBCTRL_PORTSC1_PE 2 | ||
939 | #define BM_USBCTRL_PORTSC1_PE 0x4 | ||
940 | #define BF_USBCTRL_PORTSC1_PE(v) (((v) << 2) & 0x4) | ||
941 | #define BP_USBCTRL_PORTSC1_CSC 1 | ||
942 | #define BM_USBCTRL_PORTSC1_CSC 0x2 | ||
943 | #define BF_USBCTRL_PORTSC1_CSC(v) (((v) << 1) & 0x2) | ||
944 | #define BP_USBCTRL_PORTSC1_CCS 0 | ||
945 | #define BM_USBCTRL_PORTSC1_CCS 0x1 | ||
946 | #define BF_USBCTRL_PORTSC1_CCS(v) (((v) << 0) & 0x1) | ||
947 | |||
948 | /** | ||
949 | * Register: HW_USBCTRL_OTGSC | ||
950 | * Address: 0x1a4 | ||
951 | * SCT: no | ||
952 | */ | ||
953 | #define HW_USBCTRL_OTGSC (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a4)) | ||
954 | #define BP_USBCTRL_OTGSC_RSVD2 31 | ||
955 | #define BM_USBCTRL_OTGSC_RSVD2 0x80000000 | ||
956 | #define BF_USBCTRL_OTGSC_RSVD2(v) (((v) << 31) & 0x80000000) | ||
957 | #define BP_USBCTRL_OTGSC_DPIE 30 | ||
958 | #define BM_USBCTRL_OTGSC_DPIE 0x40000000 | ||
959 | #define BF_USBCTRL_OTGSC_DPIE(v) (((v) << 30) & 0x40000000) | ||
960 | #define BP_USBCTRL_OTGSC_ONEMSE 29 | ||
961 | #define BM_USBCTRL_OTGSC_ONEMSE 0x20000000 | ||
962 | #define BF_USBCTRL_OTGSC_ONEMSE(v) (((v) << 29) & 0x20000000) | ||
963 | #define BP_USBCTRL_OTGSC_BSEIE 28 | ||
964 | #define BM_USBCTRL_OTGSC_BSEIE 0x10000000 | ||
965 | #define BF_USBCTRL_OTGSC_BSEIE(v) (((v) << 28) & 0x10000000) | ||
966 | #define BP_USBCTRL_OTGSC_BSVIE 27 | ||
967 | #define BM_USBCTRL_OTGSC_BSVIE 0x8000000 | ||
968 | #define BF_USBCTRL_OTGSC_BSVIE(v) (((v) << 27) & 0x8000000) | ||
969 | #define BP_USBCTRL_OTGSC_ASVIE 26 | ||
970 | #define BM_USBCTRL_OTGSC_ASVIE 0x4000000 | ||
971 | #define BF_USBCTRL_OTGSC_ASVIE(v) (((v) << 26) & 0x4000000) | ||
972 | #define BP_USBCTRL_OTGSC_AVVIE 25 | ||
973 | #define BM_USBCTRL_OTGSC_AVVIE 0x2000000 | ||
974 | #define BF_USBCTRL_OTGSC_AVVIE(v) (((v) << 25) & 0x2000000) | ||
975 | #define BP_USBCTRL_OTGSC_IDIE 24 | ||
976 | #define BM_USBCTRL_OTGSC_IDIE 0x1000000 | ||
977 | #define BF_USBCTRL_OTGSC_IDIE(v) (((v) << 24) & 0x1000000) | ||
978 | #define BP_USBCTRL_OTGSC_RSVD1 23 | ||
979 | #define BM_USBCTRL_OTGSC_RSVD1 0x800000 | ||
980 | #define BF_USBCTRL_OTGSC_RSVD1(v) (((v) << 23) & 0x800000) | ||
981 | #define BP_USBCTRL_OTGSC_DPIS 22 | ||
982 | #define BM_USBCTRL_OTGSC_DPIS 0x400000 | ||
983 | #define BF_USBCTRL_OTGSC_DPIS(v) (((v) << 22) & 0x400000) | ||
984 | #define BP_USBCTRL_OTGSC_ONEMSS 21 | ||
985 | #define BM_USBCTRL_OTGSC_ONEMSS 0x200000 | ||
986 | #define BF_USBCTRL_OTGSC_ONEMSS(v) (((v) << 21) & 0x200000) | ||
987 | #define BP_USBCTRL_OTGSC_BSEIS 20 | ||
988 | #define BM_USBCTRL_OTGSC_BSEIS 0x100000 | ||
989 | #define BF_USBCTRL_OTGSC_BSEIS(v) (((v) << 20) & 0x100000) | ||
990 | #define BP_USBCTRL_OTGSC_BSVIS 19 | ||
991 | #define BM_USBCTRL_OTGSC_BSVIS 0x80000 | ||
992 | #define BF_USBCTRL_OTGSC_BSVIS(v) (((v) << 19) & 0x80000) | ||
993 | #define BP_USBCTRL_OTGSC_ASVIS 18 | ||
994 | #define BM_USBCTRL_OTGSC_ASVIS 0x40000 | ||
995 | #define BF_USBCTRL_OTGSC_ASVIS(v) (((v) << 18) & 0x40000) | ||
996 | #define BP_USBCTRL_OTGSC_AVVIS 17 | ||
997 | #define BM_USBCTRL_OTGSC_AVVIS 0x20000 | ||
998 | #define BF_USBCTRL_OTGSC_AVVIS(v) (((v) << 17) & 0x20000) | ||
999 | #define BP_USBCTRL_OTGSC_IDIS 16 | ||
1000 | #define BM_USBCTRL_OTGSC_IDIS 0x10000 | ||
1001 | #define BF_USBCTRL_OTGSC_IDIS(v) (((v) << 16) & 0x10000) | ||
1002 | #define BP_USBCTRL_OTGSC_RSVD0 15 | ||
1003 | #define BM_USBCTRL_OTGSC_RSVD0 0x8000 | ||
1004 | #define BF_USBCTRL_OTGSC_RSVD0(v) (((v) << 15) & 0x8000) | ||
1005 | #define BP_USBCTRL_OTGSC_DPS 14 | ||
1006 | #define BM_USBCTRL_OTGSC_DPS 0x4000 | ||
1007 | #define BF_USBCTRL_OTGSC_DPS(v) (((v) << 14) & 0x4000) | ||
1008 | #define BP_USBCTRL_OTGSC_ONEMST 13 | ||
1009 | #define BM_USBCTRL_OTGSC_ONEMST 0x2000 | ||
1010 | #define BF_USBCTRL_OTGSC_ONEMST(v) (((v) << 13) & 0x2000) | ||
1011 | #define BP_USBCTRL_OTGSC_BSE 12 | ||
1012 | #define BM_USBCTRL_OTGSC_BSE 0x1000 | ||
1013 | #define BF_USBCTRL_OTGSC_BSE(v) (((v) << 12) & 0x1000) | ||
1014 | #define BP_USBCTRL_OTGSC_BSV 11 | ||
1015 | #define BM_USBCTRL_OTGSC_BSV 0x800 | ||
1016 | #define BF_USBCTRL_OTGSC_BSV(v) (((v) << 11) & 0x800) | ||
1017 | #define BP_USBCTRL_OTGSC_ASV 10 | ||
1018 | #define BM_USBCTRL_OTGSC_ASV 0x400 | ||
1019 | #define BF_USBCTRL_OTGSC_ASV(v) (((v) << 10) & 0x400) | ||
1020 | #define BP_USBCTRL_OTGSC_AVV 9 | ||
1021 | #define BM_USBCTRL_OTGSC_AVV 0x200 | ||
1022 | #define BF_USBCTRL_OTGSC_AVV(v) (((v) << 9) & 0x200) | ||
1023 | #define BP_USBCTRL_OTGSC_ID 8 | ||
1024 | #define BM_USBCTRL_OTGSC_ID 0x100 | ||
1025 | #define BF_USBCTRL_OTGSC_ID(v) (((v) << 8) & 0x100) | ||
1026 | #define BP_USBCTRL_OTGSC_HABA 7 | ||
1027 | #define BM_USBCTRL_OTGSC_HABA 0x80 | ||
1028 | #define BF_USBCTRL_OTGSC_HABA(v) (((v) << 7) & 0x80) | ||
1029 | #define BP_USBCTRL_OTGSC_HADP 6 | ||
1030 | #define BM_USBCTRL_OTGSC_HADP 0x40 | ||
1031 | #define BF_USBCTRL_OTGSC_HADP(v) (((v) << 6) & 0x40) | ||
1032 | #define BP_USBCTRL_OTGSC_IDPU 5 | ||
1033 | #define BM_USBCTRL_OTGSC_IDPU 0x20 | ||
1034 | #define BF_USBCTRL_OTGSC_IDPU(v) (((v) << 5) & 0x20) | ||
1035 | #define BP_USBCTRL_OTGSC_DP 4 | ||
1036 | #define BM_USBCTRL_OTGSC_DP 0x10 | ||
1037 | #define BF_USBCTRL_OTGSC_DP(v) (((v) << 4) & 0x10) | ||
1038 | #define BP_USBCTRL_OTGSC_OT 3 | ||
1039 | #define BM_USBCTRL_OTGSC_OT 0x8 | ||
1040 | #define BF_USBCTRL_OTGSC_OT(v) (((v) << 3) & 0x8) | ||
1041 | #define BP_USBCTRL_OTGSC_HAAR 2 | ||
1042 | #define BM_USBCTRL_OTGSC_HAAR 0x4 | ||
1043 | #define BF_USBCTRL_OTGSC_HAAR(v) (((v) << 2) & 0x4) | ||
1044 | #define BP_USBCTRL_OTGSC_VC 1 | ||
1045 | #define BM_USBCTRL_OTGSC_VC 0x2 | ||
1046 | #define BF_USBCTRL_OTGSC_VC(v) (((v) << 1) & 0x2) | ||
1047 | #define BP_USBCTRL_OTGSC_VD 0 | ||
1048 | #define BM_USBCTRL_OTGSC_VD 0x1 | ||
1049 | #define BF_USBCTRL_OTGSC_VD(v) (((v) << 0) & 0x1) | ||
1050 | |||
1051 | /** | ||
1052 | * Register: HW_USBCTRL_USBMODE | ||
1053 | * Address: 0x1a8 | ||
1054 | * SCT: no | ||
1055 | */ | ||
1056 | #define HW_USBCTRL_USBMODE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a8)) | ||
1057 | #define BP_USBCTRL_USBMODE_RSVD 6 | ||
1058 | #define BM_USBCTRL_USBMODE_RSVD 0xffffffc0 | ||
1059 | #define BF_USBCTRL_USBMODE_RSVD(v) (((v) << 6) & 0xffffffc0) | ||
1060 | #define BP_USBCTRL_USBMODE_VBPS 5 | ||
1061 | #define BM_USBCTRL_USBMODE_VBPS 0x20 | ||
1062 | #define BF_USBCTRL_USBMODE_VBPS(v) (((v) << 5) & 0x20) | ||
1063 | #define BP_USBCTRL_USBMODE_SDIS 4 | ||
1064 | #define BM_USBCTRL_USBMODE_SDIS 0x10 | ||
1065 | #define BF_USBCTRL_USBMODE_SDIS(v) (((v) << 4) & 0x10) | ||
1066 | #define BP_USBCTRL_USBMODE_SLOM 3 | ||
1067 | #define BM_USBCTRL_USBMODE_SLOM 0x8 | ||
1068 | #define BF_USBCTRL_USBMODE_SLOM(v) (((v) << 3) & 0x8) | ||
1069 | #define BP_USBCTRL_USBMODE_ES 2 | ||
1070 | #define BM_USBCTRL_USBMODE_ES 0x4 | ||
1071 | #define BF_USBCTRL_USBMODE_ES(v) (((v) << 2) & 0x4) | ||
1072 | #define BP_USBCTRL_USBMODE_CM 0 | ||
1073 | #define BM_USBCTRL_USBMODE_CM 0x3 | ||
1074 | #define BV_USBCTRL_USBMODE_CM__IDLE 0x0 | ||
1075 | #define BV_USBCTRL_USBMODE_CM__DEVICE 0x2 | ||
1076 | #define BV_USBCTRL_USBMODE_CM__HOST 0x3 | ||
1077 | #define BF_USBCTRL_USBMODE_CM(v) (((v) << 0) & 0x3) | ||
1078 | #define BF_USBCTRL_USBMODE_CM_V(v) ((BV_USBCTRL_USBMODE_CM__##v << 0) & 0x3) | ||
1079 | |||
1080 | /** | ||
1081 | * Register: HW_USBCTRL_ENDPTSETUPSTAT | ||
1082 | * Address: 0x1ac | ||
1083 | * SCT: no | ||
1084 | */ | ||
1085 | #define HW_USBCTRL_ENDPTSETUPSTAT (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1ac)) | ||
1086 | #define BP_USBCTRL_ENDPTSETUPSTAT_RSVD 5 | ||
1087 | #define BM_USBCTRL_ENDPTSETUPSTAT_RSVD 0xffffffe0 | ||
1088 | #define BF_USBCTRL_ENDPTSETUPSTAT_RSVD(v) (((v) << 5) & 0xffffffe0) | ||
1089 | #define BP_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT 0 | ||
1090 | #define BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT 0x1f | ||
1091 | #define BF_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT(v) (((v) << 0) & 0x1f) | ||
1092 | |||
1093 | /** | ||
1094 | * Register: HW_USBCTRL_ENDPTPRIME | ||
1095 | * Address: 0x1b0 | ||
1096 | * SCT: no | ||
1097 | */ | ||
1098 | #define HW_USBCTRL_ENDPTPRIME (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b0)) | ||
1099 | #define BP_USBCTRL_ENDPTPRIME_RSVD1 21 | ||
1100 | #define BM_USBCTRL_ENDPTPRIME_RSVD1 0xffe00000 | ||
1101 | #define BF_USBCTRL_ENDPTPRIME_RSVD1(v) (((v) << 21) & 0xffe00000) | ||
1102 | #define BP_USBCTRL_ENDPTPRIME_PETB 16 | ||
1103 | #define BM_USBCTRL_ENDPTPRIME_PETB 0x1f0000 | ||
1104 | #define BF_USBCTRL_ENDPTPRIME_PETB(v) (((v) << 16) & 0x1f0000) | ||
1105 | #define BP_USBCTRL_ENDPTPRIME_RSVD0 5 | ||
1106 | #define BM_USBCTRL_ENDPTPRIME_RSVD0 0xffe0 | ||
1107 | #define BF_USBCTRL_ENDPTPRIME_RSVD0(v) (((v) << 5) & 0xffe0) | ||
1108 | #define BP_USBCTRL_ENDPTPRIME_PERB 0 | ||
1109 | #define BM_USBCTRL_ENDPTPRIME_PERB 0x1f | ||
1110 | #define BF_USBCTRL_ENDPTPRIME_PERB(v) (((v) << 0) & 0x1f) | ||
1111 | |||
1112 | /** | ||
1113 | * Register: HW_USBCTRL_ENDPTFLUSH | ||
1114 | * Address: 0x1b4 | ||
1115 | * SCT: no | ||
1116 | */ | ||
1117 | #define HW_USBCTRL_ENDPTFLUSH (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b4)) | ||
1118 | #define BP_USBCTRL_ENDPTFLUSH_RSVD1 21 | ||
1119 | #define BM_USBCTRL_ENDPTFLUSH_RSVD1 0xffe00000 | ||
1120 | #define BF_USBCTRL_ENDPTFLUSH_RSVD1(v) (((v) << 21) & 0xffe00000) | ||
1121 | #define BP_USBCTRL_ENDPTFLUSH_FETB 16 | ||
1122 | #define BM_USBCTRL_ENDPTFLUSH_FETB 0x1f0000 | ||
1123 | #define BF_USBCTRL_ENDPTFLUSH_FETB(v) (((v) << 16) & 0x1f0000) | ||
1124 | #define BP_USBCTRL_ENDPTFLUSH_RSVD0 5 | ||
1125 | #define BM_USBCTRL_ENDPTFLUSH_RSVD0 0xffe0 | ||
1126 | #define BF_USBCTRL_ENDPTFLUSH_RSVD0(v) (((v) << 5) & 0xffe0) | ||
1127 | #define BP_USBCTRL_ENDPTFLUSH_FERB 0 | ||
1128 | #define BM_USBCTRL_ENDPTFLUSH_FERB 0x1f | ||
1129 | #define BF_USBCTRL_ENDPTFLUSH_FERB(v) (((v) << 0) & 0x1f) | ||
1130 | |||
1131 | /** | ||
1132 | * Register: HW_USBCTRL_ENDPTSTAT | ||
1133 | * Address: 0x1b8 | ||
1134 | * SCT: no | ||
1135 | */ | ||
1136 | #define HW_USBCTRL_ENDPTSTAT (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b8)) | ||
1137 | #define BP_USBCTRL_ENDPTSTAT_RSVD1 21 | ||
1138 | #define BM_USBCTRL_ENDPTSTAT_RSVD1 0xffe00000 | ||
1139 | #define BF_USBCTRL_ENDPTSTAT_RSVD1(v) (((v) << 21) & 0xffe00000) | ||
1140 | #define BP_USBCTRL_ENDPTSTAT_ETBR 16 | ||
1141 | #define BM_USBCTRL_ENDPTSTAT_ETBR 0x1f0000 | ||
1142 | #define BF_USBCTRL_ENDPTSTAT_ETBR(v) (((v) << 16) & 0x1f0000) | ||
1143 | #define BP_USBCTRL_ENDPTSTAT_RSVD0 5 | ||
1144 | #define BM_USBCTRL_ENDPTSTAT_RSVD0 0xffe0 | ||
1145 | #define BF_USBCTRL_ENDPTSTAT_RSVD0(v) (((v) << 5) & 0xffe0) | ||
1146 | #define BP_USBCTRL_ENDPTSTAT_ERBR 0 | ||
1147 | #define BM_USBCTRL_ENDPTSTAT_ERBR 0x1f | ||
1148 | #define BF_USBCTRL_ENDPTSTAT_ERBR(v) (((v) << 0) & 0x1f) | ||
1149 | |||
1150 | /** | ||
1151 | * Register: HW_USBCTRL_ENDPTCOMPLETE | ||
1152 | * Address: 0x1bc | ||
1153 | * SCT: no | ||
1154 | */ | ||
1155 | #define HW_USBCTRL_ENDPTCOMPLETE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1bc)) | ||
1156 | #define BP_USBCTRL_ENDPTCOMPLETE_RSVD1 21 | ||
1157 | #define BM_USBCTRL_ENDPTCOMPLETE_RSVD1 0xffe00000 | ||
1158 | #define BF_USBCTRL_ENDPTCOMPLETE_RSVD1(v) (((v) << 21) & 0xffe00000) | ||
1159 | #define BP_USBCTRL_ENDPTCOMPLETE_ETCE 16 | ||
1160 | #define BM_USBCTRL_ENDPTCOMPLETE_ETCE 0x1f0000 | ||
1161 | #define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v) (((v) << 16) & 0x1f0000) | ||
1162 | #define BP_USBCTRL_ENDPTCOMPLETE_RSVD0 5 | ||
1163 | #define BM_USBCTRL_ENDPTCOMPLETE_RSVD0 0xffe0 | ||
1164 | #define BF_USBCTRL_ENDPTCOMPLETE_RSVD0(v) (((v) << 5) & 0xffe0) | ||
1165 | #define BP_USBCTRL_ENDPTCOMPLETE_ERCE 0 | ||
1166 | #define BM_USBCTRL_ENDPTCOMPLETE_ERCE 0x1f | ||
1167 | #define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v) (((v) << 0) & 0x1f) | ||
1168 | |||
1169 | /** | ||
1170 | * Register: HW_USBCTRL_ENDPTCTRLn | ||
1171 | * Address: 0x1c0+n*0x4 | ||
1172 | * SCT: no | ||
1173 | */ | ||
1174 | #define HW_USBCTRL_ENDPTCTRLn(n) (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c0+(n)*0x4)) | ||
1175 | #define BP_USBCTRL_ENDPTCTRLn_RSVD6 24 | ||
1176 | #define BM_USBCTRL_ENDPTCTRLn_RSVD6 0xff000000 | ||
1177 | #define BF_USBCTRL_ENDPTCTRLn_RSVD6(v) (((v) << 24) & 0xff000000) | ||
1178 | #define BP_USBCTRL_ENDPTCTRLn_TXE 23 | ||
1179 | #define BM_USBCTRL_ENDPTCTRLn_TXE 0x800000 | ||
1180 | #define BF_USBCTRL_ENDPTCTRLn_TXE(v) (((v) << 23) & 0x800000) | ||
1181 | #define BP_USBCTRL_ENDPTCTRLn_TXR 22 | ||
1182 | #define BM_USBCTRL_ENDPTCTRLn_TXR 0x400000 | ||
1183 | #define BF_USBCTRL_ENDPTCTRLn_TXR(v) (((v) << 22) & 0x400000) | ||
1184 | #define BP_USBCTRL_ENDPTCTRLn_TXI 21 | ||
1185 | #define BM_USBCTRL_ENDPTCTRLn_TXI 0x200000 | ||
1186 | #define BF_USBCTRL_ENDPTCTRLn_TXI(v) (((v) << 21) & 0x200000) | ||
1187 | #define BP_USBCTRL_ENDPTCTRLn_RSVD5 20 | ||
1188 | #define BM_USBCTRL_ENDPTCTRLn_RSVD5 0x100000 | ||
1189 | #define BF_USBCTRL_ENDPTCTRLn_RSVD5(v) (((v) << 20) & 0x100000) | ||
1190 | #define BP_USBCTRL_ENDPTCTRLn_TXT 18 | ||
1191 | #define BM_USBCTRL_ENDPTCTRLn_TXT 0xc0000 | ||
1192 | #define BV_USBCTRL_ENDPTCTRLn_TXT__CONTROL 0x0 | ||
1193 | #define BV_USBCTRL_ENDPTCTRLn_TXT__ISO 0x1 | ||
1194 | #define BV_USBCTRL_ENDPTCTRLn_TXT__BULK 0x2 | ||
1195 | #define BV_USBCTRL_ENDPTCTRLn_TXT__INT 0x3 | ||
1196 | #define BF_USBCTRL_ENDPTCTRLn_TXT(v) (((v) << 18) & 0xc0000) | ||
1197 | #define BF_USBCTRL_ENDPTCTRLn_TXT_V(v) ((BV_USBCTRL_ENDPTCTRLn_TXT__##v << 18) & 0xc0000) | ||
1198 | #define BP_USBCTRL_ENDPTCTRLn_TXD 17 | ||
1199 | #define BM_USBCTRL_ENDPTCTRLn_TXD 0x20000 | ||
1200 | #define BF_USBCTRL_ENDPTCTRLn_TXD(v) (((v) << 17) & 0x20000) | ||
1201 | #define BP_USBCTRL_ENDPTCTRLn_TXS 16 | ||
1202 | #define BM_USBCTRL_ENDPTCTRLn_TXS 0x10000 | ||
1203 | #define BF_USBCTRL_ENDPTCTRLn_TXS(v) (((v) << 16) & 0x10000) | ||
1204 | #define BP_USBCTRL_ENDPTCTRLn_RSVD3 8 | ||
1205 | #define BM_USBCTRL_ENDPTCTRLn_RSVD3 0xff00 | ||
1206 | #define BF_USBCTRL_ENDPTCTRLn_RSVD3(v) (((v) << 8) & 0xff00) | ||
1207 | #define BP_USBCTRL_ENDPTCTRLn_RXE 7 | ||
1208 | #define BM_USBCTRL_ENDPTCTRLn_RXE 0x80 | ||
1209 | #define BF_USBCTRL_ENDPTCTRLn_RXE(v) (((v) << 7) & 0x80) | ||
1210 | #define BP_USBCTRL_ENDPTCTRLn_RXR 6 | ||
1211 | #define BM_USBCTRL_ENDPTCTRLn_RXR 0x40 | ||
1212 | #define BF_USBCTRL_ENDPTCTRLn_RXR(v) (((v) << 6) & 0x40) | ||
1213 | #define BP_USBCTRL_ENDPTCTRLn_RXI 5 | ||
1214 | #define BM_USBCTRL_ENDPTCTRLn_RXI 0x20 | ||
1215 | #define BF_USBCTRL_ENDPTCTRLn_RXI(v) (((v) << 5) & 0x20) | ||
1216 | #define BP_USBCTRL_ENDPTCTRLn_RSVD2 4 | ||
1217 | #define BM_USBCTRL_ENDPTCTRLn_RSVD2 0x10 | ||
1218 | #define BF_USBCTRL_ENDPTCTRLn_RSVD2(v) (((v) << 4) & 0x10) | ||
1219 | #define BP_USBCTRL_ENDPTCTRLn_RXT 2 | ||
1220 | #define BM_USBCTRL_ENDPTCTRLn_RXT 0xc | ||
1221 | #define BV_USBCTRL_ENDPTCTRLn_RXT__CONTROL 0x0 | ||
1222 | #define BV_USBCTRL_ENDPTCTRLn_RXT__ISO 0x1 | ||
1223 | #define BV_USBCTRL_ENDPTCTRLn_RXT__BULK 0x2 | ||
1224 | #define BV_USBCTRL_ENDPTCTRLn_RXT__INT 0x3 | ||
1225 | #define BF_USBCTRL_ENDPTCTRLn_RXT(v) (((v) << 2) & 0xc) | ||
1226 | #define BF_USBCTRL_ENDPTCTRLn_RXT_V(v) ((BV_USBCTRL_ENDPTCTRLn_RXT__##v << 2) & 0xc) | ||
1227 | #define BP_USBCTRL_ENDPTCTRLn_RXD 1 | ||
1228 | #define BM_USBCTRL_ENDPTCTRLn_RXD 0x2 | ||
1229 | #define BF_USBCTRL_ENDPTCTRLn_RXD(v) (((v) << 1) & 0x2) | ||
1230 | #define BP_USBCTRL_ENDPTCTRLn_RXS 0 | ||
1231 | #define BM_USBCTRL_ENDPTCTRLn_RXS 0x1 | ||
1232 | #define BF_USBCTRL_ENDPTCTRLn_RXS(v) (((v) << 0) & 0x1) | ||
1233 | |||
1234 | #endif /* __HEADERGEN__IMX233__USBCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h b/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h new file mode 100644 index 0000000000..e20871b0df --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h | |||
@@ -0,0 +1,421 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__USBPHY__H__ | ||
24 | #define __HEADERGEN__IMX233__USBPHY__H__ | ||
25 | |||
26 | #define REGS_USBPHY_BASE (0x8007c000) | ||
27 | |||
28 | #define REGS_USBPHY_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_USBPHY_PWD | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_USBPHY_PWD (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0)) | ||
36 | #define HW_USBPHY_PWD_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4)) | ||
37 | #define HW_USBPHY_PWD_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8)) | ||
38 | #define HW_USBPHY_PWD_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc)) | ||
39 | #define BP_USBPHY_PWD_RSVD2 21 | ||
40 | #define BM_USBPHY_PWD_RSVD2 0xffe00000 | ||
41 | #define BF_USBPHY_PWD_RSVD2(v) (((v) << 21) & 0xffe00000) | ||
42 | #define BP_USBPHY_PWD_RXPWDRX 20 | ||
43 | #define BM_USBPHY_PWD_RXPWDRX 0x100000 | ||
44 | #define BF_USBPHY_PWD_RXPWDRX(v) (((v) << 20) & 0x100000) | ||
45 | #define BP_USBPHY_PWD_RXPWDDIFF 19 | ||
46 | #define BM_USBPHY_PWD_RXPWDDIFF 0x80000 | ||
47 | #define BF_USBPHY_PWD_RXPWDDIFF(v) (((v) << 19) & 0x80000) | ||
48 | #define BP_USBPHY_PWD_RXPWD1PT1 18 | ||
49 | #define BM_USBPHY_PWD_RXPWD1PT1 0x40000 | ||
50 | #define BF_USBPHY_PWD_RXPWD1PT1(v) (((v) << 18) & 0x40000) | ||
51 | #define BP_USBPHY_PWD_RXPWDENV 17 | ||
52 | #define BM_USBPHY_PWD_RXPWDENV 0x20000 | ||
53 | #define BF_USBPHY_PWD_RXPWDENV(v) (((v) << 17) & 0x20000) | ||
54 | #define BP_USBPHY_PWD_RSVD1 13 | ||
55 | #define BM_USBPHY_PWD_RSVD1 0x1e000 | ||
56 | #define BF_USBPHY_PWD_RSVD1(v) (((v) << 13) & 0x1e000) | ||
57 | #define BP_USBPHY_PWD_TXPWDV2I 12 | ||
58 | #define BM_USBPHY_PWD_TXPWDV2I 0x1000 | ||
59 | #define BF_USBPHY_PWD_TXPWDV2I(v) (((v) << 12) & 0x1000) | ||
60 | #define BP_USBPHY_PWD_TXPWDIBIAS 11 | ||
61 | #define BM_USBPHY_PWD_TXPWDIBIAS 0x800 | ||
62 | #define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800) | ||
63 | #define BP_USBPHY_PWD_TXPWDFS 10 | ||
64 | #define BM_USBPHY_PWD_TXPWDFS 0x400 | ||
65 | #define BF_USBPHY_PWD_TXPWDFS(v) (((v) << 10) & 0x400) | ||
66 | #define BP_USBPHY_PWD_RSVD0 0 | ||
67 | #define BM_USBPHY_PWD_RSVD0 0x3ff | ||
68 | #define BF_USBPHY_PWD_RSVD0(v) (((v) << 0) & 0x3ff) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_USBPHY_TX | ||
72 | * Address: 0x10 | ||
73 | * SCT: yes | ||
74 | */ | ||
75 | #define HW_USBPHY_TX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0)) | ||
76 | #define HW_USBPHY_TX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4)) | ||
77 | #define HW_USBPHY_TX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8)) | ||
78 | #define HW_USBPHY_TX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc)) | ||
79 | #define BP_USBPHY_TX_RSVD5 29 | ||
80 | #define BM_USBPHY_TX_RSVD5 0xe0000000 | ||
81 | #define BF_USBPHY_TX_RSVD5(v) (((v) << 29) & 0xe0000000) | ||
82 | #define BP_USBPHY_TX_USBPHY_TX_EDGECTRL 26 | ||
83 | #define BM_USBPHY_TX_USBPHY_TX_EDGECTRL 0x1c000000 | ||
84 | #define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v) (((v) << 26) & 0x1c000000) | ||
85 | #define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT 25 | ||
86 | #define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT 0x2000000 | ||
87 | #define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v) (((v) << 25) & 0x2000000) | ||
88 | #define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX 24 | ||
89 | #define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX 0x1000000 | ||
90 | #define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v) (((v) << 24) & 0x1000000) | ||
91 | #define BP_USBPHY_TX_RSVD4 22 | ||
92 | #define BM_USBPHY_TX_RSVD4 0xc00000 | ||
93 | #define BF_USBPHY_TX_RSVD4(v) (((v) << 22) & 0xc00000) | ||
94 | #define BP_USBPHY_TX_TXENCAL45DP 21 | ||
95 | #define BM_USBPHY_TX_TXENCAL45DP 0x200000 | ||
96 | #define BF_USBPHY_TX_TXENCAL45DP(v) (((v) << 21) & 0x200000) | ||
97 | #define BP_USBPHY_TX_RSVD3 20 | ||
98 | #define BM_USBPHY_TX_RSVD3 0x100000 | ||
99 | #define BF_USBPHY_TX_RSVD3(v) (((v) << 20) & 0x100000) | ||
100 | #define BP_USBPHY_TX_TXCAL45DP 16 | ||
101 | #define BM_USBPHY_TX_TXCAL45DP 0xf0000 | ||
102 | #define BF_USBPHY_TX_TXCAL45DP(v) (((v) << 16) & 0xf0000) | ||
103 | #define BP_USBPHY_TX_RSVD2 14 | ||
104 | #define BM_USBPHY_TX_RSVD2 0xc000 | ||
105 | #define BF_USBPHY_TX_RSVD2(v) (((v) << 14) & 0xc000) | ||
106 | #define BP_USBPHY_TX_TXENCAL45DN 13 | ||
107 | #define BM_USBPHY_TX_TXENCAL45DN 0x2000 | ||
108 | #define BF_USBPHY_TX_TXENCAL45DN(v) (((v) << 13) & 0x2000) | ||
109 | #define BP_USBPHY_TX_RSVD1 12 | ||
110 | #define BM_USBPHY_TX_RSVD1 0x1000 | ||
111 | #define BF_USBPHY_TX_RSVD1(v) (((v) << 12) & 0x1000) | ||
112 | #define BP_USBPHY_TX_TXCAL45DN 8 | ||
113 | #define BM_USBPHY_TX_TXCAL45DN 0xf00 | ||
114 | #define BF_USBPHY_TX_TXCAL45DN(v) (((v) << 8) & 0xf00) | ||
115 | #define BP_USBPHY_TX_RSVD0 4 | ||
116 | #define BM_USBPHY_TX_RSVD0 0xf0 | ||
117 | #define BF_USBPHY_TX_RSVD0(v) (((v) << 4) & 0xf0) | ||
118 | #define BP_USBPHY_TX_D_CAL 0 | ||
119 | #define BM_USBPHY_TX_D_CAL 0xf | ||
120 | #define BF_USBPHY_TX_D_CAL(v) (((v) << 0) & 0xf) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_USBPHY_RX | ||
124 | * Address: 0x20 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_USBPHY_RX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0)) | ||
128 | #define HW_USBPHY_RX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4)) | ||
129 | #define HW_USBPHY_RX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8)) | ||
130 | #define HW_USBPHY_RX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc)) | ||
131 | #define BP_USBPHY_RX_RSVD2 23 | ||
132 | #define BM_USBPHY_RX_RSVD2 0xff800000 | ||
133 | #define BF_USBPHY_RX_RSVD2(v) (((v) << 23) & 0xff800000) | ||
134 | #define BP_USBPHY_RX_RXDBYPASS 22 | ||
135 | #define BM_USBPHY_RX_RXDBYPASS 0x400000 | ||
136 | #define BF_USBPHY_RX_RXDBYPASS(v) (((v) << 22) & 0x400000) | ||
137 | #define BP_USBPHY_RX_RSVD1 7 | ||
138 | #define BM_USBPHY_RX_RSVD1 0x3fff80 | ||
139 | #define BF_USBPHY_RX_RSVD1(v) (((v) << 7) & 0x3fff80) | ||
140 | #define BP_USBPHY_RX_DISCONADJ 4 | ||
141 | #define BM_USBPHY_RX_DISCONADJ 0x70 | ||
142 | #define BF_USBPHY_RX_DISCONADJ(v) (((v) << 4) & 0x70) | ||
143 | #define BP_USBPHY_RX_RSVD0 3 | ||
144 | #define BM_USBPHY_RX_RSVD0 0x8 | ||
145 | #define BF_USBPHY_RX_RSVD0(v) (((v) << 3) & 0x8) | ||
146 | #define BP_USBPHY_RX_ENVADJ 0 | ||
147 | #define BM_USBPHY_RX_ENVADJ 0x7 | ||
148 | #define BF_USBPHY_RX_ENVADJ(v) (((v) << 0) & 0x7) | ||
149 | |||
150 | /** | ||
151 | * Register: HW_USBPHY_CTRL | ||
152 | * Address: 0x30 | ||
153 | * SCT: yes | ||
154 | */ | ||
155 | #define HW_USBPHY_CTRL (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0)) | ||
156 | #define HW_USBPHY_CTRL_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4)) | ||
157 | #define HW_USBPHY_CTRL_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8)) | ||
158 | #define HW_USBPHY_CTRL_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc)) | ||
159 | #define BP_USBPHY_CTRL_SFTRST 31 | ||
160 | #define BM_USBPHY_CTRL_SFTRST 0x80000000 | ||
161 | #define BF_USBPHY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
162 | #define BP_USBPHY_CTRL_CLKGATE 30 | ||
163 | #define BM_USBPHY_CTRL_CLKGATE 0x40000000 | ||
164 | #define BF_USBPHY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
165 | #define BP_USBPHY_CTRL_UTMI_SUSPENDM 29 | ||
166 | #define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 | ||
167 | #define BF_USBPHY_CTRL_UTMI_SUSPENDM(v) (((v) << 29) & 0x20000000) | ||
168 | #define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0 28 | ||
169 | #define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 0x10000000 | ||
170 | #define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v) (((v) << 28) & 0x10000000) | ||
171 | #define BP_USBPHY_CTRL_RSVD3 14 | ||
172 | #define BM_USBPHY_CTRL_RSVD3 0xfffc000 | ||
173 | #define BF_USBPHY_CTRL_RSVD3(v) (((v) << 14) & 0xfffc000) | ||
174 | #define BP_USBPHY_CTRL_DATA_ON_LRADC 13 | ||
175 | #define BM_USBPHY_CTRL_DATA_ON_LRADC 0x2000 | ||
176 | #define BF_USBPHY_CTRL_DATA_ON_LRADC(v) (((v) << 13) & 0x2000) | ||
177 | #define BP_USBPHY_CTRL_DEVPLUGIN_IRQ 12 | ||
178 | #define BM_USBPHY_CTRL_DEVPLUGIN_IRQ 0x1000 | ||
179 | #define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v) (((v) << 12) & 0x1000) | ||
180 | #define BP_USBPHY_CTRL_ENIRQDEVPLUGIN 11 | ||
181 | #define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x800 | ||
182 | #define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v) (((v) << 11) & 0x800) | ||
183 | #define BP_USBPHY_CTRL_RESUME_IRQ 10 | ||
184 | #define BM_USBPHY_CTRL_RESUME_IRQ 0x400 | ||
185 | #define BF_USBPHY_CTRL_RESUME_IRQ(v) (((v) << 10) & 0x400) | ||
186 | #define BP_USBPHY_CTRL_ENIRQRESUMEDETECT 9 | ||
187 | #define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x200 | ||
188 | #define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v) (((v) << 9) & 0x200) | ||
189 | #define BP_USBPHY_CTRL_RSVD2 8 | ||
190 | #define BM_USBPHY_CTRL_RSVD2 0x100 | ||
191 | #define BF_USBPHY_CTRL_RSVD2(v) (((v) << 8) & 0x100) | ||
192 | #define BP_USBPHY_CTRL_ENOTGIDDETECT 7 | ||
193 | #define BM_USBPHY_CTRL_ENOTGIDDETECT 0x80 | ||
194 | #define BF_USBPHY_CTRL_ENOTGIDDETECT(v) (((v) << 7) & 0x80) | ||
195 | #define BP_USBPHY_CTRL_RSVD1 6 | ||
196 | #define BM_USBPHY_CTRL_RSVD1 0x40 | ||
197 | #define BF_USBPHY_CTRL_RSVD1(v) (((v) << 6) & 0x40) | ||
198 | #define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY 5 | ||
199 | #define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY 0x20 | ||
200 | #define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v) (((v) << 5) & 0x20) | ||
201 | #define BP_USBPHY_CTRL_ENDEVPLUGINDETECT 4 | ||
202 | #define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x10 | ||
203 | #define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v) (((v) << 4) & 0x10) | ||
204 | #define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 3 | ||
205 | #define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x8 | ||
206 | #define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v) (((v) << 3) & 0x8) | ||
207 | #define BP_USBPHY_CTRL_ENIRQHOSTDISCON 2 | ||
208 | #define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x4 | ||
209 | #define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v) (((v) << 2) & 0x4) | ||
210 | #define BP_USBPHY_CTRL_ENHOSTDISCONDETECT 1 | ||
211 | #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x2 | ||
212 | #define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v) (((v) << 1) & 0x2) | ||
213 | #define BP_USBPHY_CTRL_RSVD0 0 | ||
214 | #define BM_USBPHY_CTRL_RSVD0 0x1 | ||
215 | #define BF_USBPHY_CTRL_RSVD0(v) (((v) << 0) & 0x1) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_USBPHY_STATUS | ||
219 | * Address: 0x40 | ||
220 | * SCT: no | ||
221 | */ | ||
222 | #define HW_USBPHY_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40)) | ||
223 | #define BP_USBPHY_STATUS_RSVD4 11 | ||
224 | #define BM_USBPHY_STATUS_RSVD4 0xfffff800 | ||
225 | #define BF_USBPHY_STATUS_RSVD4(v) (((v) << 11) & 0xfffff800) | ||
226 | #define BP_USBPHY_STATUS_RESUME_STATUS 10 | ||
227 | #define BM_USBPHY_STATUS_RESUME_STATUS 0x400 | ||
228 | #define BF_USBPHY_STATUS_RESUME_STATUS(v) (((v) << 10) & 0x400) | ||
229 | #define BP_USBPHY_STATUS_RSVD3 9 | ||
230 | #define BM_USBPHY_STATUS_RSVD3 0x200 | ||
231 | #define BF_USBPHY_STATUS_RSVD3(v) (((v) << 9) & 0x200) | ||
232 | #define BP_USBPHY_STATUS_OTGID_STATUS 8 | ||
233 | #define BM_USBPHY_STATUS_OTGID_STATUS 0x100 | ||
234 | #define BF_USBPHY_STATUS_OTGID_STATUS(v) (((v) << 8) & 0x100) | ||
235 | #define BP_USBPHY_STATUS_RSVD2 7 | ||
236 | #define BM_USBPHY_STATUS_RSVD2 0x80 | ||
237 | #define BF_USBPHY_STATUS_RSVD2(v) (((v) << 7) & 0x80) | ||
238 | #define BP_USBPHY_STATUS_DEVPLUGIN_STATUS 6 | ||
239 | #define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x40 | ||
240 | #define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v) (((v) << 6) & 0x40) | ||
241 | #define BP_USBPHY_STATUS_RSVD1 4 | ||
242 | #define BM_USBPHY_STATUS_RSVD1 0x30 | ||
243 | #define BF_USBPHY_STATUS_RSVD1(v) (((v) << 4) & 0x30) | ||
244 | #define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 3 | ||
245 | #define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x8 | ||
246 | #define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8) | ||
247 | #define BP_USBPHY_STATUS_RSVD0 0 | ||
248 | #define BM_USBPHY_STATUS_RSVD0 0x7 | ||
249 | #define BF_USBPHY_STATUS_RSVD0(v) (((v) << 0) & 0x7) | ||
250 | |||
251 | /** | ||
252 | * Register: HW_USBPHY_DEBUG | ||
253 | * Address: 0x50 | ||
254 | * SCT: yes | ||
255 | */ | ||
256 | #define HW_USBPHY_DEBUG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0)) | ||
257 | #define HW_USBPHY_DEBUG_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4)) | ||
258 | #define HW_USBPHY_DEBUG_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8)) | ||
259 | #define HW_USBPHY_DEBUG_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc)) | ||
260 | #define BP_USBPHY_DEBUG_RSVD3 31 | ||
261 | #define BM_USBPHY_DEBUG_RSVD3 0x80000000 | ||
262 | #define BF_USBPHY_DEBUG_RSVD3(v) (((v) << 31) & 0x80000000) | ||
263 | #define BP_USBPHY_DEBUG_CLKGATE 30 | ||
264 | #define BM_USBPHY_DEBUG_CLKGATE 0x40000000 | ||
265 | #define BF_USBPHY_DEBUG_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
266 | #define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG 29 | ||
267 | #define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG 0x20000000 | ||
268 | #define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v) (((v) << 29) & 0x20000000) | ||
269 | #define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 | ||
270 | #define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1e000000 | ||
271 | #define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) (((v) << 25) & 0x1e000000) | ||
272 | #define BP_USBPHY_DEBUG_ENSQUELCHRESET 24 | ||
273 | #define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x1000000 | ||
274 | #define BF_USBPHY_DEBUG_ENSQUELCHRESET(v) (((v) << 24) & 0x1000000) | ||
275 | #define BP_USBPHY_DEBUG_RSVD2 21 | ||
276 | #define BM_USBPHY_DEBUG_RSVD2 0xe00000 | ||
277 | #define BF_USBPHY_DEBUG_RSVD2(v) (((v) << 21) & 0xe00000) | ||
278 | #define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 | ||
279 | #define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x1f0000 | ||
280 | #define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) (((v) << 16) & 0x1f0000) | ||
281 | #define BP_USBPHY_DEBUG_RSVD1 13 | ||
282 | #define BM_USBPHY_DEBUG_RSVD1 0xe000 | ||
283 | #define BF_USBPHY_DEBUG_RSVD1(v) (((v) << 13) & 0xe000) | ||
284 | #define BP_USBPHY_DEBUG_ENTX2RXCOUNT 12 | ||
285 | #define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x1000 | ||
286 | #define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v) (((v) << 12) & 0x1000) | ||
287 | #define BP_USBPHY_DEBUG_TX2RXCOUNT 8 | ||
288 | #define BM_USBPHY_DEBUG_TX2RXCOUNT 0xf00 | ||
289 | #define BF_USBPHY_DEBUG_TX2RXCOUNT(v) (((v) << 8) & 0xf00) | ||
290 | #define BP_USBPHY_DEBUG_RSVD0 6 | ||
291 | #define BM_USBPHY_DEBUG_RSVD0 0xc0 | ||
292 | #define BF_USBPHY_DEBUG_RSVD0(v) (((v) << 6) & 0xc0) | ||
293 | #define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 | ||
294 | #define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x30 | ||
295 | #define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) (((v) << 4) & 0x30) | ||
296 | #define BP_USBPHY_DEBUG_HSTPULLDOWN 2 | ||
297 | #define BM_USBPHY_DEBUG_HSTPULLDOWN 0xc | ||
298 | #define BF_USBPHY_DEBUG_HSTPULLDOWN(v) (((v) << 2) & 0xc) | ||
299 | #define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 1 | ||
300 | #define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x2 | ||
301 | #define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2) | ||
302 | #define BP_USBPHY_DEBUG_OTGIDPIOLOCK 0 | ||
303 | #define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x1 | ||
304 | #define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v) (((v) << 0) & 0x1) | ||
305 | |||
306 | /** | ||
307 | * Register: HW_USBPHY_DEBUG0_STATUS | ||
308 | * Address: 0x60 | ||
309 | * SCT: no | ||
310 | */ | ||
311 | #define HW_USBPHY_DEBUG0_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60)) | ||
312 | #define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 | ||
313 | #define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xfc000000 | ||
314 | #define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) (((v) << 26) & 0xfc000000) | ||
315 | #define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 | ||
316 | #define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x3ff0000 | ||
317 | #define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
318 | #define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 | ||
319 | #define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0xffff | ||
320 | #define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) (((v) << 0) & 0xffff) | ||
321 | |||
322 | /** | ||
323 | * Register: HW_USBPHY_DEBUG1 | ||
324 | * Address: 0x70 | ||
325 | * SCT: yes | ||
326 | */ | ||
327 | #define HW_USBPHY_DEBUG1 (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x0)) | ||
328 | #define HW_USBPHY_DEBUG1_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x4)) | ||
329 | #define HW_USBPHY_DEBUG1_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x8)) | ||
330 | #define HW_USBPHY_DEBUG1_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0xc)) | ||
331 | #define BP_USBPHY_DEBUG1_RSVD1 15 | ||
332 | #define BM_USBPHY_DEBUG1_RSVD1 0xffff8000 | ||
333 | #define BF_USBPHY_DEBUG1_RSVD1(v) (((v) << 15) & 0xffff8000) | ||
334 | #define BP_USBPHY_DEBUG1_ENTAILADJVD 13 | ||
335 | #define BM_USBPHY_DEBUG1_ENTAILADJVD 0x6000 | ||
336 | #define BF_USBPHY_DEBUG1_ENTAILADJVD(v) (((v) << 13) & 0x6000) | ||
337 | #define BP_USBPHY_DEBUG1_ENTX2TX 12 | ||
338 | #define BM_USBPHY_DEBUG1_ENTX2TX 0x1000 | ||
339 | #define BF_USBPHY_DEBUG1_ENTX2TX(v) (((v) << 12) & 0x1000) | ||
340 | #define BP_USBPHY_DEBUG1_RSVD0 4 | ||
341 | #define BM_USBPHY_DEBUG1_RSVD0 0xff0 | ||
342 | #define BF_USBPHY_DEBUG1_RSVD0(v) (((v) << 4) & 0xff0) | ||
343 | #define BP_USBPHY_DEBUG1_DBG_ADDRESS 0 | ||
344 | #define BM_USBPHY_DEBUG1_DBG_ADDRESS 0xf | ||
345 | #define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) (((v) << 0) & 0xf) | ||
346 | |||
347 | /** | ||
348 | * Register: HW_USBPHY_VERSION | ||
349 | * Address: 0x80 | ||
350 | * SCT: no | ||
351 | */ | ||
352 | #define HW_USBPHY_VERSION (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80)) | ||
353 | #define BP_USBPHY_VERSION_MAJOR 24 | ||
354 | #define BM_USBPHY_VERSION_MAJOR 0xff000000 | ||
355 | #define BF_USBPHY_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
356 | #define BP_USBPHY_VERSION_MINOR 16 | ||
357 | #define BM_USBPHY_VERSION_MINOR 0xff0000 | ||
358 | #define BF_USBPHY_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
359 | #define BP_USBPHY_VERSION_STEP 0 | ||
360 | #define BM_USBPHY_VERSION_STEP 0xffff | ||
361 | #define BF_USBPHY_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
362 | |||
363 | /** | ||
364 | * Register: HW_USBPHY_IP | ||
365 | * Address: 0x90 | ||
366 | * SCT: yes | ||
367 | */ | ||
368 | #define HW_USBPHY_IP (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x0)) | ||
369 | #define HW_USBPHY_IP_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x4)) | ||
370 | #define HW_USBPHY_IP_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x8)) | ||
371 | #define HW_USBPHY_IP_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0xc)) | ||
372 | #define BP_USBPHY_IP_RSVD1 25 | ||
373 | #define BM_USBPHY_IP_RSVD1 0xfe000000 | ||
374 | #define BF_USBPHY_IP_RSVD1(v) (((v) << 25) & 0xfe000000) | ||
375 | #define BP_USBPHY_IP_DIV_SEL 23 | ||
376 | #define BM_USBPHY_IP_DIV_SEL 0x1800000 | ||
377 | #define BV_USBPHY_IP_DIV_SEL__DEFAULT 0x0 | ||
378 | #define BV_USBPHY_IP_DIV_SEL__LOWER 0x1 | ||
379 | #define BV_USBPHY_IP_DIV_SEL__LOWEST 0x2 | ||
380 | #define BV_USBPHY_IP_DIV_SEL__UNDEFINED 0x3 | ||
381 | #define BF_USBPHY_IP_DIV_SEL(v) (((v) << 23) & 0x1800000) | ||
382 | #define BF_USBPHY_IP_DIV_SEL_V(v) ((BV_USBPHY_IP_DIV_SEL__##v << 23) & 0x1800000) | ||
383 | #define BP_USBPHY_IP_LFR_SEL 21 | ||
384 | #define BM_USBPHY_IP_LFR_SEL 0x600000 | ||
385 | #define BV_USBPHY_IP_LFR_SEL__DEFAULT 0x0 | ||
386 | #define BV_USBPHY_IP_LFR_SEL__TIMES_2 0x1 | ||
387 | #define BV_USBPHY_IP_LFR_SEL__TIMES_05 0x2 | ||
388 | #define BV_USBPHY_IP_LFR_SEL__UNDEFINED 0x3 | ||
389 | #define BF_USBPHY_IP_LFR_SEL(v) (((v) << 21) & 0x600000) | ||
390 | #define BF_USBPHY_IP_LFR_SEL_V(v) ((BV_USBPHY_IP_LFR_SEL__##v << 21) & 0x600000) | ||
391 | #define BP_USBPHY_IP_CP_SEL 19 | ||
392 | #define BM_USBPHY_IP_CP_SEL 0x180000 | ||
393 | #define BV_USBPHY_IP_CP_SEL__DEFAULT 0x0 | ||
394 | #define BV_USBPHY_IP_CP_SEL__TIMES_2 0x1 | ||
395 | #define BV_USBPHY_IP_CP_SEL__TIMES_05 0x2 | ||
396 | #define BV_USBPHY_IP_CP_SEL__UNDEFINED 0x3 | ||
397 | #define BF_USBPHY_IP_CP_SEL(v) (((v) << 19) & 0x180000) | ||
398 | #define BF_USBPHY_IP_CP_SEL_V(v) ((BV_USBPHY_IP_CP_SEL__##v << 19) & 0x180000) | ||
399 | #define BP_USBPHY_IP_TSTI_TX_DP 18 | ||
400 | #define BM_USBPHY_IP_TSTI_TX_DP 0x40000 | ||
401 | #define BF_USBPHY_IP_TSTI_TX_DP(v) (((v) << 18) & 0x40000) | ||
402 | #define BP_USBPHY_IP_TSTI_TX_DM 17 | ||
403 | #define BM_USBPHY_IP_TSTI_TX_DM 0x20000 | ||
404 | #define BF_USBPHY_IP_TSTI_TX_DM(v) (((v) << 17) & 0x20000) | ||
405 | #define BP_USBPHY_IP_ANALOG_TESTMODE 16 | ||
406 | #define BM_USBPHY_IP_ANALOG_TESTMODE 0x10000 | ||
407 | #define BF_USBPHY_IP_ANALOG_TESTMODE(v) (((v) << 16) & 0x10000) | ||
408 | #define BP_USBPHY_IP_RSVD0 3 | ||
409 | #define BM_USBPHY_IP_RSVD0 0xfff8 | ||
410 | #define BF_USBPHY_IP_RSVD0(v) (((v) << 3) & 0xfff8) | ||
411 | #define BP_USBPHY_IP_EN_USB_CLKS 2 | ||
412 | #define BM_USBPHY_IP_EN_USB_CLKS 0x4 | ||
413 | #define BF_USBPHY_IP_EN_USB_CLKS(v) (((v) << 2) & 0x4) | ||
414 | #define BP_USBPHY_IP_PLL_LOCKED 1 | ||
415 | #define BM_USBPHY_IP_PLL_LOCKED 0x2 | ||
416 | #define BF_USBPHY_IP_PLL_LOCKED(v) (((v) << 1) & 0x2) | ||
417 | #define BP_USBPHY_IP_PLL_POWER 0 | ||
418 | #define BM_USBPHY_IP_PLL_POWER 0x1 | ||
419 | #define BF_USBPHY_IP_PLL_POWER(v) (((v) << 0) & 0x1) | ||
420 | |||
421 | #endif /* __HEADERGEN__IMX233__USBPHY__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-anatop.h b/firmware/target/arm/imx233/regs/regs-anatop.h new file mode 100644 index 0000000000..760500cf16 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-anatop.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__ANATOP__H__ | ||
24 | #define __SELECT__ANATOP__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-anatop.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3600_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__ANATOP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-apbh.h b/firmware/target/arm/imx233/regs/regs-apbh.h new file mode 100644 index 0000000000..91d2976bdc --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-apbh.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__APBH__H__ | ||
24 | #define __SELECT__APBH__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-apbh.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-apbh.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-apbh.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__APBH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-apbx.h b/firmware/target/arm/imx233/regs/regs-apbx.h new file mode 100644 index 0000000000..19923e5c5d --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-apbx.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.1 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__APBX__H__ | ||
24 | #define __SELECT__APBX__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-apbx.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-apbx.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-apbx.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__APBX__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-arc.h b/firmware/target/arm/imx233/regs/regs-arc.h new file mode 100644 index 0000000000..d9050e398f --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-arc.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__ARC__H__ | ||
24 | #define __SELECT__ARC__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-arc.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3600_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__ARC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-audioin.h b/firmware/target/arm/imx233/regs/regs-audioin.h new file mode 100644 index 0000000000..c3dcfd13d8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-audioin.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.5.0 stmp3700:3.4.0 imx233:3.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__AUDIOIN__H__ | ||
24 | #define __SELECT__AUDIOIN__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-audioin.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-audioin.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-audioin.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__AUDIOIN__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-audioout.h b/firmware/target/arm/imx233/regs/regs-audioout.h new file mode 100644 index 0000000000..e9fc4adaa0 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-audioout.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__AUDIOOUT__H__ | ||
24 | #define __SELECT__AUDIOOUT__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-audioout.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-audioout.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-audioout.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__AUDIOOUT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-bch.h b/firmware/target/arm/imx233/regs/regs-bch.h new file mode 100644 index 0000000000..2bbd3d2eca --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-bch.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__BCH__H__ | ||
24 | #define __SELECT__BCH__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define IMX233_INCLUDE "imx233/regs-bch.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef IMX233_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__BCH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-brazoiocsr.h b/firmware/target/arm/imx233/regs/regs-brazoiocsr.h new file mode 100644 index 0000000000..723e13e27b --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-brazoiocsr.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__BRAZOIOCSR__H__ | ||
24 | #define __SELECT__BRAZOIOCSR__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-brazoiocsr.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3600_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__BRAZOIOCSR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-clkctrl.h b/firmware/target/arm/imx233/regs/regs-clkctrl.h new file mode 100644 index 0000000000..dbb2765e73 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-clkctrl.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__CLKCTRL__H__ | ||
24 | #define __SELECT__CLKCTRL__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-clkctrl.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-clkctrl.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-clkctrl.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__CLKCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-dacdma.h b/firmware/target/arm/imx233/regs/regs-dacdma.h new file mode 100644 index 0000000000..dc00b63b8a --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-dacdma.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__DACDMA__H__ | ||
24 | #define __SELECT__DACDMA__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-dacdma.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3600_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__DACDMA__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-dcp.h b/firmware/target/arm/imx233/regs/regs-dcp.h new file mode 100644 index 0000000000..7603751040 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-dcp.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__DCP__H__ | ||
24 | #define __SELECT__DCP__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-dcp.h" | ||
28 | #define IMX233_INCLUDE "imx233/regs-dcp.h" | ||
29 | |||
30 | #include "regs-select.h" | ||
31 | |||
32 | #undef STMP3700_INCLUDE | ||
33 | #undef IMX233_INCLUDE | ||
34 | |||
35 | #endif /* __SELECT__DCP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-digctl.h b/firmware/target/arm/imx233/regs/regs-digctl.h new file mode 100644 index 0000000000..900884a532 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-digctl.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__DIGCTL__H__ | ||
24 | #define __SELECT__DIGCTL__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-digctl.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-digctl.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-digctl.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__DIGCTL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-dram.h b/firmware/target/arm/imx233/regs/regs-dram.h new file mode 100644 index 0000000000..4ebd0a7157 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-dram.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__DRAM__H__ | ||
24 | #define __SELECT__DRAM__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-dram.h" | ||
28 | #define IMX233_INCLUDE "imx233/regs-dram.h" | ||
29 | |||
30 | #include "regs-select.h" | ||
31 | |||
32 | #undef STMP3700_INCLUDE | ||
33 | #undef IMX233_INCLUDE | ||
34 | |||
35 | #endif /* __SELECT__DRAM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-dri.h b/firmware/target/arm/imx233/regs/regs-dri.h new file mode 100644 index 0000000000..7d481c029c --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-dri.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__DRI__H__ | ||
24 | #define __SELECT__DRI__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-dri.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-dri.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-dri.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__DRI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-ecc8.h b/firmware/target/arm/imx233/regs/regs-ecc8.h new file mode 100644 index 0000000000..776d92e87d --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-ecc8.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__ECC8__H__ | ||
24 | #define __SELECT__ECC8__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-ecc8.h" | ||
28 | #define IMX233_INCLUDE "imx233/regs-ecc8.h" | ||
29 | |||
30 | #include "regs-select.h" | ||
31 | |||
32 | #undef STMP3700_INCLUDE | ||
33 | #undef IMX233_INCLUDE | ||
34 | |||
35 | #endif /* __SELECT__ECC8__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-emi.h b/firmware/target/arm/imx233/regs/regs-emi.h new file mode 100644 index 0000000000..3f8a16ffbe --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-emi.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__EMI__H__ | ||
24 | #define __SELECT__EMI__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-emi.h" | ||
28 | #define IMX233_INCLUDE "imx233/regs-emi.h" | ||
29 | |||
30 | #include "regs-select.h" | ||
31 | |||
32 | #undef STMP3700_INCLUDE | ||
33 | #undef IMX233_INCLUDE | ||
34 | |||
35 | #endif /* __SELECT__EMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-emictrl.h b/firmware/target/arm/imx233/regs/regs-emictrl.h new file mode 100644 index 0000000000..f7fceb8710 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-emictrl.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__EMICTRL__H__ | ||
24 | #define __SELECT__EMICTRL__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-emictrl.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3600_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__EMICTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-gpiomon.h b/firmware/target/arm/imx233/regs/regs-gpiomon.h new file mode 100644 index 0000000000..bfd2c875e7 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-gpiomon.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__GPIOMON__H__ | ||
24 | #define __SELECT__GPIOMON__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-gpiomon.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3700_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__GPIOMON__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-gpmi.h b/firmware/target/arm/imx233/regs/regs-gpmi.h new file mode 100644 index 0000000000..7dba72387b --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-gpmi.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__GPMI__H__ | ||
24 | #define __SELECT__GPMI__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-gpmi.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-gpmi.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-gpmi.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__GPMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-hwecc.h b/firmware/target/arm/imx233/regs/regs-hwecc.h new file mode 100644 index 0000000000..16609045f8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-hwecc.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__HWECC__H__ | ||
24 | #define __SELECT__HWECC__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-hwecc.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3600_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__HWECC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-i2c.h b/firmware/target/arm/imx233/regs/regs-i2c.h new file mode 100644 index 0000000000..28c6c04f95 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-i2c.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__I2C__H__ | ||
24 | #define __SELECT__I2C__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-i2c.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-i2c.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-i2c.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__I2C__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-icoll.h b/firmware/target/arm/imx233/regs/regs-icoll.h new file mode 100644 index 0000000000..c89f3d478f --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-icoll.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__ICOLL__H__ | ||
24 | #define __SELECT__ICOLL__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-icoll.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-icoll.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-icoll.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__ICOLL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-ir.h b/firmware/target/arm/imx233/regs/regs-ir.h new file mode 100644 index 0000000000..ebb51e4f1e --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-ir.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__IR__H__ | ||
24 | #define __SELECT__IR__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-ir.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-ir.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-ir.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__IR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-lcdif.h b/firmware/target/arm/imx233/regs/regs-lcdif.h new file mode 100644 index 0000000000..79e6554d58 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-lcdif.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__LCDIF__H__ | ||
24 | #define __SELECT__LCDIF__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-lcdif.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-lcdif.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-lcdif.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__LCDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-lradc.h b/firmware/target/arm/imx233/regs/regs-lradc.h new file mode 100644 index 0000000000..2b4701bb8c --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-lradc.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__LRADC__H__ | ||
24 | #define __SELECT__LRADC__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-lradc.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-lradc.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-lradc.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__LRADC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-macro.h b/firmware/target/arm/imx233/regs/regs-macro.h new file mode 100644 index 0000000000..c53bc8609b --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-macro.h | |||
@@ -0,0 +1,496 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * | ||
11 | * Copyright (C) 2013 by Amaury Pouly | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or | ||
14 | * modify it under the terms of the GNU General Public License | ||
15 | * as published by the Free Software Foundation; either version 2 | ||
16 | * of the License, or (at your option) any later version. | ||
17 | * | ||
18 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
19 | * KIND, either express or implied. | ||
20 | * | ||
21 | ****************************************************************************/ | ||
22 | #ifndef __REGS__MACRO__H__ | ||
23 | #define __REGS__MACRO__H__ | ||
24 | |||
25 | #ifndef REG_WRITE | ||
26 | #define REG_WRITE(var,value) ((var) = (value)) | ||
27 | #endif /* REG_WRITE */ | ||
28 | |||
29 | #ifndef REG_READ | ||
30 | #define REG_READ(var) (var) | ||
31 | #endif /* REG_READ */ | ||
32 | |||
33 | #define BF_SET(reg, field) REG_WRITE(HW_##reg##_SET, BM_##reg##_##field) | ||
34 | #define BF_CLR(reg, field) REG_WRITE(HW_##reg##_CLR, BM_##reg##_##field) | ||
35 | #define BF_TOG(reg, field) REG_WRITE(HW_##reg##_TOG, BM_##reg##_##field) | ||
36 | |||
37 | #define BF_SETV(reg, field, v) REG_WRITE(HW_##reg##_SET, BF_##reg##_##field(v)) | ||
38 | #define BF_CLRV(reg, field, v) REG_WRITE(HW_##reg##_CLR, BF_##reg##_##field(v)) | ||
39 | #define BF_TOGV(reg, field, v) REG_WRITE(HW_##reg##_TOG, BF_##reg##_##field(v)) | ||
40 | |||
41 | #define BF_RDX(val, reg, field) ((REG_READ(val) & BM_##reg##_##field) >> BP_##reg##_##field) | ||
42 | #define BF_RD(reg, field) BF_RDX(REG_READ(HW_##reg), reg, field) | ||
43 | #define BF_WRX(val, reg, field, v) REG_WRITE(val, (REG_READ(val) & ~BM_##reg##_##field) | (((v) << BP_##reg##_##field) & BM_##reg##_##field)) | ||
44 | #define BF_WR(reg, field, v) BF_WRX(HW_##reg, reg, field, v) | ||
45 | #define BF_WR_V(reg, field, sy) BF_WR(reg, field, BV_##reg##_##field##__##sy) | ||
46 | #define BF_WR_VX(val, reg, field, sy) BF_WRX(val, reg, field, BV_##reg##_##field##__##sy) | ||
47 | |||
48 | #define BF_SETn(reg, n, field) REG_WRITE(HW_##reg##_SET(n), BM_##reg##_##field) | ||
49 | #define BF_CLRn(reg, n, field) REG_WRITE(HW_##reg##_CLR(n), BM_##reg##_##field) | ||
50 | #define BF_TOGn(reg, n, field) REG_WRITE(HW_##reg##_TOG(n), BM_##reg##_##field) | ||
51 | |||
52 | #define BF_SETVn(reg, n, field, v) REG_WRITE(HW_##reg##_SET(n), BF_##reg##_##field(v)) | ||
53 | #define BF_CLRVn(reg, n, field, v) REG_WRITE(HW_##reg##_CLR(n), BF_##reg##_##field(v)) | ||
54 | #define BF_TOGVn(reg, n, field, v) REG_WRITE(HW_##reg##_TOG(n), BF_##reg##_##field(v)) | ||
55 | |||
56 | #define BF_RDn(reg, n, field) BF_RDX(HW_##reg(n), reg, field) | ||
57 | #define BF_WRn(reg, n, field, v) BF_WRX(HW_##reg(n), reg, field, v) | ||
58 | #define BF_WRn_V(reg, n, field, sy) BF_WRn(reg, n, field, BV_##reg##_##field##__##sy) | ||
59 | |||
60 | #define BM_OR1(reg, f01) \ | ||
61 | (BM_##reg##_##f01) | ||
62 | #define BM_OR2(reg, f01, f02) \ | ||
63 | (BM_##reg##_##f01 | BM_##reg##_##f02) | ||
64 | #define BM_OR3(reg, f01, f02, f03) \ | ||
65 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03) | ||
66 | #define BM_OR4(reg, f01, f02, f03, f04) \ | ||
67 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04) | ||
68 | #define BM_OR5(reg, f01, f02, f03, f04, f05) \ | ||
69 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
70 | BM_##reg##_##f05) | ||
71 | #define BM_OR6(reg, f01, f02, f03, f04, f05, f06) \ | ||
72 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
73 | BM_##reg##_##f05 | BM_##reg##_##f06) | ||
74 | #define BM_OR7(reg, f01, f02, f03, f04, f05, f06, f07) \ | ||
75 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
76 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07) | ||
77 | #define BM_OR8(reg, f01, f02, f03, f04, f05, f06, f07, f08) \ | ||
78 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
79 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08) | ||
80 | #define BM_OR9(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09) \ | ||
81 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
82 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
83 | BM_##reg##_##f09) | ||
84 | #define BM_OR10(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10) \ | ||
85 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
86 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
87 | BM_##reg##_##f09 | BM_##reg##_##f10) | ||
88 | #define BM_OR11(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
89 | f11) \ | ||
90 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
91 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
92 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11) | ||
93 | #define BM_OR12(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
94 | f11, f12) \ | ||
95 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
96 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
97 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12) | ||
98 | #define BM_OR13(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
99 | f11, f12, f13) \ | ||
100 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
101 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
102 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
103 | BM_##reg##_##f13) | ||
104 | #define BM_OR14(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
105 | f11, f12, f13, f14) \ | ||
106 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
107 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
108 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
109 | BM_##reg##_##f13 | BM_##reg##_##f14) | ||
110 | #define BM_OR15(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
111 | f11, f12, f13, f14, f15) \ | ||
112 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
113 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
114 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
115 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15) | ||
116 | #define BM_OR16(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
117 | f11, f12, f13, f14, f15, f16) \ | ||
118 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
119 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
120 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
121 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16) | ||
122 | #define BM_OR17(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
123 | f11, f12, f13, f14, f15, f16, f17) \ | ||
124 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
125 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
126 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
127 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
128 | BM_##reg##_##f17) | ||
129 | #define BM_OR18(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
130 | f11, f12, f13, f14, f15, f16, f17, f18) \ | ||
131 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
132 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
133 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
134 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
135 | BM_##reg##_##f17 | BM_##reg##_##f18) | ||
136 | #define BM_OR19(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
137 | f11, f12, f13, f14, f15, f16, f17, f18, f19) \ | ||
138 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
139 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
140 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
141 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
142 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19) | ||
143 | #define BM_OR20(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
144 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20) \ | ||
145 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
146 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
147 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
148 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
149 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20) | ||
150 | #define BM_OR21(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
151 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
152 | f21) \ | ||
153 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
154 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
155 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
156 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
157 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
158 | BM_##reg##_##f21) | ||
159 | #define BM_OR22(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
160 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
161 | f21, f22) \ | ||
162 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
163 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
164 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
165 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
166 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
167 | BM_##reg##_##f21 | BM_##reg##_##f22) | ||
168 | #define BM_OR23(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
169 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
170 | f21, f22, f23) \ | ||
171 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
172 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
173 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
174 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
175 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
176 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23) | ||
177 | #define BM_OR24(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
178 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
179 | f21, f22, f23, f24) \ | ||
180 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
181 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
182 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
183 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
184 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
185 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24) | ||
186 | #define BM_OR25(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
187 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
188 | f21, f22, f23, f24, f25) \ | ||
189 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
190 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
191 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
192 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
193 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
194 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
195 | BM_##reg##_##f25) | ||
196 | #define BM_OR26(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
197 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
198 | f21, f22, f23, f24, f25, f26) \ | ||
199 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
200 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
201 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
202 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
203 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
204 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
205 | BM_##reg##_##f25 | BM_##reg##_##f26) | ||
206 | #define BM_OR27(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
207 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
208 | f21, f22, f23, f24, f25, f26, f27) \ | ||
209 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
210 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
211 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
212 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
213 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
214 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
215 | BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27) | ||
216 | #define BM_OR28(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
217 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
218 | f21, f22, f23, f24, f25, f26, f27, f28) \ | ||
219 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
220 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
221 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
222 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
223 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
224 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
225 | BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28) | ||
226 | #define BM_OR29(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
227 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
228 | f21, f22, f23, f24, f25, f26, f27, f28, f29) \ | ||
229 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
230 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
231 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
232 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
233 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
234 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
235 | BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \ | ||
236 | BM_##reg##_##f29) | ||
237 | #define BM_OR30(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
238 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
239 | f21, f22, f23, f24, f25, f26, f27, f28, f29, f30) \ | ||
240 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
241 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
242 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
243 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
244 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
245 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
246 | BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \ | ||
247 | BM_##reg##_##f29 | BM_##reg##_##f30) | ||
248 | #define BM_OR31(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
249 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
250 | f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \ | ||
251 | f31) \ | ||
252 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
253 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
254 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
255 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
256 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
257 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
258 | BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \ | ||
259 | BM_##reg##_##f29 | BM_##reg##_##f30 | BM_##reg##_##f31) | ||
260 | #define BM_OR32(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
261 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
262 | f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \ | ||
263 | f31, f32) \ | ||
264 | (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \ | ||
265 | BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \ | ||
266 | BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \ | ||
267 | BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \ | ||
268 | BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \ | ||
269 | BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \ | ||
270 | BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \ | ||
271 | BM_##reg##_##f29 | BM_##reg##_##f30 | BM_##reg##_##f31 | BM_##reg##_##f32) | ||
272 | |||
273 | #define BF_OR1(reg, f01) \ | ||
274 | (BF_##reg##_##f01) | ||
275 | #define BF_OR2(reg, f01, f02) \ | ||
276 | (BF_##reg##_##f01 | BF_##reg##_##f02) | ||
277 | #define BF_OR3(reg, f01, f02, f03) \ | ||
278 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03) | ||
279 | #define BF_OR4(reg, f01, f02, f03, f04) \ | ||
280 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04) | ||
281 | #define BF_OR5(reg, f01, f02, f03, f04, f05) \ | ||
282 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
283 | BF_##reg##_##f05) | ||
284 | #define BF_OR6(reg, f01, f02, f03, f04, f05, f06) \ | ||
285 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
286 | BF_##reg##_##f05 | BF_##reg##_##f06) | ||
287 | #define BF_OR7(reg, f01, f02, f03, f04, f05, f06, f07) \ | ||
288 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
289 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07) | ||
290 | #define BF_OR8(reg, f01, f02, f03, f04, f05, f06, f07, f08) \ | ||
291 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
292 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08) | ||
293 | #define BF_OR9(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09) \ | ||
294 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
295 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
296 | BF_##reg##_##f09) | ||
297 | #define BF_OR10(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10) \ | ||
298 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
299 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
300 | BF_##reg##_##f09 | BF_##reg##_##f10) | ||
301 | #define BF_OR11(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
302 | f11) \ | ||
303 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
304 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
305 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11) | ||
306 | #define BF_OR12(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
307 | f11, f12) \ | ||
308 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
309 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
310 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12) | ||
311 | #define BF_OR13(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
312 | f11, f12, f13) \ | ||
313 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
314 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
315 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
316 | BF_##reg##_##f13) | ||
317 | #define BF_OR14(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
318 | f11, f12, f13, f14) \ | ||
319 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
320 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
321 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
322 | BF_##reg##_##f13 | BF_##reg##_##f14) | ||
323 | #define BF_OR15(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
324 | f11, f12, f13, f14, f15) \ | ||
325 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
326 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
327 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
328 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15) | ||
329 | #define BF_OR16(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
330 | f11, f12, f13, f14, f15, f16) \ | ||
331 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
332 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
333 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
334 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16) | ||
335 | #define BF_OR17(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
336 | f11, f12, f13, f14, f15, f16, f17) \ | ||
337 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
338 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
339 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
340 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
341 | BF_##reg##_##f17) | ||
342 | #define BF_OR18(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
343 | f11, f12, f13, f14, f15, f16, f17, f18) \ | ||
344 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
345 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
346 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
347 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
348 | BF_##reg##_##f17 | BF_##reg##_##f18) | ||
349 | #define BF_OR19(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
350 | f11, f12, f13, f14, f15, f16, f17, f18, f19) \ | ||
351 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
352 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
353 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
354 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
355 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19) | ||
356 | #define BF_OR20(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
357 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20) \ | ||
358 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
359 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
360 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
361 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
362 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20) | ||
363 | #define BF_OR21(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
364 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
365 | f21) \ | ||
366 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
367 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
368 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
369 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
370 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
371 | BF_##reg##_##f21) | ||
372 | #define BF_OR22(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
373 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
374 | f21, f22) \ | ||
375 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
376 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
377 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
378 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
379 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
380 | BF_##reg##_##f21 | BF_##reg##_##f22) | ||
381 | #define BF_OR23(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
382 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
383 | f21, f22, f23) \ | ||
384 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
385 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
386 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
387 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
388 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
389 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23) | ||
390 | #define BF_OR24(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
391 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
392 | f21, f22, f23, f24) \ | ||
393 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
394 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
395 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
396 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
397 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
398 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24) | ||
399 | #define BF_OR25(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
400 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
401 | f21, f22, f23, f24, f25) \ | ||
402 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
403 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
404 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
405 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
406 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
407 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
408 | BF_##reg##_##f25) | ||
409 | #define BF_OR26(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
410 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
411 | f21, f22, f23, f24, f25, f26) \ | ||
412 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
413 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
414 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
415 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
416 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
417 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
418 | BF_##reg##_##f25 | BF_##reg##_##f26) | ||
419 | #define BF_OR27(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
420 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
421 | f21, f22, f23, f24, f25, f26, f27) \ | ||
422 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
423 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
424 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
425 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
426 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
427 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
428 | BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27) | ||
429 | #define BF_OR28(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
430 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
431 | f21, f22, f23, f24, f25, f26, f27, f28) \ | ||
432 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
433 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
434 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
435 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
436 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
437 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
438 | BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28) | ||
439 | #define BF_OR29(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
440 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
441 | f21, f22, f23, f24, f25, f26, f27, f28, f29) \ | ||
442 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
443 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
444 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
445 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
446 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
447 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
448 | BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \ | ||
449 | BF_##reg##_##f29) | ||
450 | #define BF_OR30(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
451 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
452 | f21, f22, f23, f24, f25, f26, f27, f28, f29, f30) \ | ||
453 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
454 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
455 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
456 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
457 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
458 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
459 | BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \ | ||
460 | BF_##reg##_##f29 | BF_##reg##_##f30) | ||
461 | #define BF_OR31(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
462 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
463 | f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \ | ||
464 | f31) \ | ||
465 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
466 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
467 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
468 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
469 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
470 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
471 | BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \ | ||
472 | BF_##reg##_##f29 | BF_##reg##_##f30 | BF_##reg##_##f31) | ||
473 | #define BF_OR32(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \ | ||
474 | f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \ | ||
475 | f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \ | ||
476 | f31, f32) \ | ||
477 | (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \ | ||
478 | BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \ | ||
479 | BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \ | ||
480 | BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \ | ||
481 | BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \ | ||
482 | BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \ | ||
483 | BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \ | ||
484 | BF_##reg##_##f29 | BF_##reg##_##f30 | BF_##reg##_##f31 | BF_##reg##_##f32) | ||
485 | |||
486 | #define REG_NARG(...) REG_NARGS_(__VA_ARGS__, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1) | ||
487 | #define REG_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, N, ...) N | ||
488 | |||
489 | #define REG_VARIADIC(macro, reg, ...) REG_VARIADIC_(macro, NARG(__VA_ARGS__), reg, __VA_ARGS__) | ||
490 | #define REG_VARIADIC_(macro, cnt, reg, ...) REG_VARIADIC__(macro, cnt, reg, __VA_ARGS__) | ||
491 | #define REG_VARIADIC__(macro, cnt, reg, ...) REG_VARIADIC___(macro##cnt, reg, ...) | ||
492 | #define REG_VARIADIC___(macro, reg, ...) macro(reg, __VA_ARGS__) | ||
493 | |||
494 | #define BM_OR(reg, ...) REG_VARIADIC(BM_OR, reg, __VA_ARGS__) | ||
495 | #define BF_OR(reg, ...) REG_VARIADIC(BF_OR, reg, __VA_ARGS__) | ||
496 | #endif /* __REGS__MACRO__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-memcpy.h b/firmware/target/arm/imx233/regs/regs-memcpy.h new file mode 100644 index 0000000000..5abcf10e96 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-memcpy.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__MEMCPY__H__ | ||
24 | #define __SELECT__MEMCPY__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-memcpy.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef STMP3600_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__MEMCPY__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-ocotp.h b/firmware/target/arm/imx233/regs/regs-ocotp.h new file mode 100644 index 0000000000..6ddf92e05d --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-ocotp.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__OCOTP__H__ | ||
24 | #define __SELECT__OCOTP__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-ocotp.h" | ||
28 | #define IMX233_INCLUDE "imx233/regs-ocotp.h" | ||
29 | |||
30 | #include "regs-select.h" | ||
31 | |||
32 | #undef STMP3700_INCLUDE | ||
33 | #undef IMX233_INCLUDE | ||
34 | |||
35 | #endif /* __SELECT__OCOTP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-pinctrl.h b/firmware/target/arm/imx233/regs/regs-pinctrl.h new file mode 100644 index 0000000000..c1736976f7 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-pinctrl.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__PINCTRL__H__ | ||
24 | #define __SELECT__PINCTRL__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-pinctrl.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-pinctrl.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-pinctrl.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__PINCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-power.h b/firmware/target/arm/imx233/regs/regs-power.h new file mode 100644 index 0000000000..ebf1e4796f --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-power.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__POWER__H__ | ||
24 | #define __SELECT__POWER__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-power.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-power.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-power.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__POWER__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-pwm.h b/firmware/target/arm/imx233/regs/regs-pwm.h new file mode 100644 index 0000000000..ce782620be --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-pwm.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__PWM__H__ | ||
24 | #define __SELECT__PWM__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-pwm.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-pwm.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-pwm.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__PWM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-pxp.h b/firmware/target/arm/imx233/regs/regs-pxp.h new file mode 100644 index 0000000000..5c5d4cffeb --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-pxp.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__PXP__H__ | ||
24 | #define __SELECT__PXP__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define IMX233_INCLUDE "imx233/regs-pxp.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef IMX233_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__PXP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-rtc.h b/firmware/target/arm/imx233/regs/regs-rtc.h new file mode 100644 index 0000000000..c9acbdfbaa --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-rtc.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__RTC__H__ | ||
24 | #define __SELECT__RTC__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-rtc.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-rtc.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-rtc.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__RTC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-saif.h b/firmware/target/arm/imx233/regs/regs-saif.h new file mode 100644 index 0000000000..234b6ed204 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-saif.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__SAIF__H__ | ||
24 | #define __SELECT__SAIF__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-saif.h" | ||
28 | #define IMX233_INCLUDE "imx233/regs-saif.h" | ||
29 | |||
30 | #include "regs-select.h" | ||
31 | |||
32 | #undef STMP3700_INCLUDE | ||
33 | #undef IMX233_INCLUDE | ||
34 | |||
35 | #endif /* __SELECT__SAIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-spdif.h b/firmware/target/arm/imx233/regs/regs-spdif.h new file mode 100644 index 0000000000..c5108a780b --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-spdif.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__SPDIF__H__ | ||
24 | #define __SELECT__SPDIF__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-spdif.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-spdif.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-spdif.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__SPDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-ssp.h b/firmware/target/arm/imx233/regs/regs-ssp.h new file mode 100644 index 0000000000..0c44e8cc3c --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-ssp.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__SSP__H__ | ||
24 | #define __SELECT__SSP__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-ssp.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-ssp.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-ssp.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__SSP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-sydma.h b/firmware/target/arm/imx233/regs/regs-sydma.h new file mode 100644 index 0000000000..e1480959bd --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-sydma.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__SYDMA__H__ | ||
24 | #define __SELECT__SYDMA__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define IMX233_INCLUDE "imx233/regs-sydma.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef IMX233_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__SYDMA__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-timrot.h b/firmware/target/arm/imx233/regs/regs-timrot.h new file mode 100644 index 0000000000..32edf163ea --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-timrot.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__TIMROT__H__ | ||
24 | #define __SELECT__TIMROT__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-timrot.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-timrot.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-timrot.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__TIMROT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-tvenc.h b/firmware/target/arm/imx233/regs/regs-tvenc.h new file mode 100644 index 0000000000..5497c48766 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-tvenc.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__TVENC__H__ | ||
24 | #define __SELECT__TVENC__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define IMX233_INCLUDE "imx233/regs-tvenc.h" | ||
28 | |||
29 | #include "regs-select.h" | ||
30 | |||
31 | #undef IMX233_INCLUDE | ||
32 | |||
33 | #endif /* __SELECT__TVENC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-uartapp.h b/firmware/target/arm/imx233/regs/regs-uartapp.h new file mode 100644 index 0000000000..08f48348a4 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-uartapp.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__UARTAPP__H__ | ||
24 | #define __SELECT__UARTAPP__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-uartapp.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-uartapp.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-uartapp.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__UARTAPP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-uartdbg.h b/firmware/target/arm/imx233/regs/regs-uartdbg.h new file mode 100644 index 0000000000..b4080be163 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-uartdbg.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__UARTDBG__H__ | ||
24 | #define __SELECT__UARTDBG__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-uartdbg.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-uartdbg.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-uartdbg.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__UARTDBG__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-usbctrl.h b/firmware/target/arm/imx233/regs/regs-usbctrl.h new file mode 100644 index 0000000000..c0552bb5eb --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-usbctrl.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__USBCTRL__H__ | ||
24 | #define __SELECT__USBCTRL__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3700_INCLUDE "stmp3700/regs-usbctrl.h" | ||
28 | #define IMX233_INCLUDE "imx233/regs-usbctrl.h" | ||
29 | |||
30 | #include "regs-select.h" | ||
31 | |||
32 | #undef STMP3700_INCLUDE | ||
33 | #undef IMX233_INCLUDE | ||
34 | |||
35 | #endif /* __SELECT__USBCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/regs-usbphy.h b/firmware/target/arm/imx233/regs/regs-usbphy.h new file mode 100644 index 0000000000..08fc272a40 --- /dev/null +++ b/firmware/target/arm/imx233/regs/regs-usbphy.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __SELECT__USBPHY__H__ | ||
24 | #define __SELECT__USBPHY__H__ | ||
25 | #include "regs-macro.h" | ||
26 | |||
27 | #define STMP3600_INCLUDE "stmp3600/regs-usbphy.h" | ||
28 | #define STMP3700_INCLUDE "stmp3700/regs-usbphy.h" | ||
29 | #define IMX233_INCLUDE "imx233/regs-usbphy.h" | ||
30 | |||
31 | #include "regs-select.h" | ||
32 | |||
33 | #undef STMP3600_INCLUDE | ||
34 | #undef STMP3700_INCLUDE | ||
35 | #undef IMX233_INCLUDE | ||
36 | |||
37 | #endif /* __SELECT__USBPHY__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h b/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h new file mode 100644 index 0000000000..d18835f044 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h | |||
@@ -0,0 +1,82 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__ANATOP__H__ | ||
24 | #define __HEADERGEN__STMP3600__ANATOP__H__ | ||
25 | |||
26 | #define REGS_ANATOP_BASE (0x8003c200) | ||
27 | |||
28 | #define REGS_ANATOP_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ANATOP_PROBE_OUTPUT_SELECT | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_ANATOP_PROBE_OUTPUT_SELECT (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_ANATOP_PROBE_OUTPUT_SELECT_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_ANATOP_PROBE_OUTPUT_SELECT_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_ANATOP_PROBE_OUTPUT_SELECT_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT 0 | ||
40 | #define BM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT 0xffffffff | ||
41 | #define BF_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT(v) (((v) << 0) & 0xffffffff) | ||
42 | |||
43 | /** | ||
44 | * Register: HW_ANATOP_PROBE_INPUT_SELECT | ||
45 | * Address: 0x10 | ||
46 | * SCT: yes | ||
47 | */ | ||
48 | #define HW_ANATOP_PROBE_INPUT_SELECT (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x0)) | ||
49 | #define HW_ANATOP_PROBE_INPUT_SELECT_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x4)) | ||
50 | #define HW_ANATOP_PROBE_INPUT_SELECT_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x8)) | ||
51 | #define HW_ANATOP_PROBE_INPUT_SELECT_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0xc)) | ||
52 | #define BP_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT 0 | ||
53 | #define BM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT 0xffffffff | ||
54 | #define BF_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT(v) (((v) << 0) & 0xffffffff) | ||
55 | |||
56 | /** | ||
57 | * Register: HW_ANATOP_PROBE_DATA | ||
58 | * Address: 0x20 | ||
59 | * SCT: yes | ||
60 | */ | ||
61 | #define HW_ANATOP_PROBE_DATA (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x0)) | ||
62 | #define HW_ANATOP_PROBE_DATA_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x4)) | ||
63 | #define HW_ANATOP_PROBE_DATA_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x8)) | ||
64 | #define HW_ANATOP_PROBE_DATA_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0xc)) | ||
65 | #define BP_ANATOP_PROBE_DATA_DATA 0 | ||
66 | #define BM_ANATOP_PROBE_DATA_DATA 0xffffffff | ||
67 | #define BF_ANATOP_PROBE_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
68 | |||
69 | /** | ||
70 | * Register: HW_ANATOP_PROBE_DIGTOP_SELECT | ||
71 | * Address: 0x30 | ||
72 | * SCT: yes | ||
73 | */ | ||
74 | #define HW_ANATOP_PROBE_DIGTOP_SELECT (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x0)) | ||
75 | #define HW_ANATOP_PROBE_DIGTOP_SELECT_SET (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x4)) | ||
76 | #define HW_ANATOP_PROBE_DIGTOP_SELECT_CLR (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x8)) | ||
77 | #define HW_ANATOP_PROBE_DIGTOP_SELECT_TOG (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0xc)) | ||
78 | #define BP_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT 0 | ||
79 | #define BM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT 0xffffffff | ||
80 | #define BF_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT(v) (((v) << 0) & 0xffffffff) | ||
81 | |||
82 | #endif /* __HEADERGEN__STMP3600__ANATOP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h new file mode 100644 index 0000000000..ab8d9e6deb --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h | |||
@@ -0,0 +1,288 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__APBH__H__ | ||
24 | #define __HEADERGEN__STMP3600__APBH__H__ | ||
25 | |||
26 | #define REGS_APBH_BASE (0x80004000) | ||
27 | |||
28 | #define REGS_APBH_VERSION "2.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_APBH_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_APBH_CTRL0 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0)) | ||
36 | #define HW_APBH_CTRL0_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4)) | ||
37 | #define HW_APBH_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8)) | ||
38 | #define HW_APBH_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc)) | ||
39 | #define BP_APBH_CTRL0_SFTRST 31 | ||
40 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_APBH_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_APBH_CTRL0_CLKGATE 30 | ||
43 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_APBH_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
46 | #define BM_APBH_CTRL0_RESET_CHANNEL 0xff0000 | ||
47 | #define BV_APBH_CTRL0_RESET_CHANNEL__HWECC 0x1 | ||
48 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP 0x2 | ||
49 | #define BV_APBH_CTRL0_RESET_CHANNEL__SRC 0x4 | ||
50 | #define BV_APBH_CTRL0_RESET_CHANNEL__DEST 0x8 | ||
51 | #define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 | ||
52 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 | ||
53 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 | ||
54 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x30 | ||
55 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x40 | ||
56 | #define BF_APBH_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
57 | #define BF_APBH_CTRL0_RESET_CHANNEL_V(v) ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
58 | #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 | ||
59 | #define BM_APBH_CTRL0_CLKGATE_CHANNEL 0xff00 | ||
60 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__HWECC 0x1 | ||
61 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP 0x2 | ||
62 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SRC 0x4 | ||
63 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__DEST 0x8 | ||
64 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 | ||
65 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 | ||
66 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 | ||
67 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x30 | ||
68 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x40 | ||
69 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) << 8) & 0xff00) | ||
70 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v) ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00) | ||
71 | #define BP_APBH_CTRL0_FREEZE_CHANNEL 0 | ||
72 | #define BM_APBH_CTRL0_FREEZE_CHANNEL 0xff | ||
73 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__HWECC 0x1 | ||
74 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP 0x2 | ||
75 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SRC 0x4 | ||
76 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__DEST 0x8 | ||
77 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 | ||
78 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 | ||
79 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 | ||
80 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x30 | ||
81 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x40 | ||
82 | #define BF_APBH_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
83 | #define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
84 | |||
85 | /** | ||
86 | * Register: HW_APBH_CTRL1 | ||
87 | * Address: 0x10 | ||
88 | * SCT: yes | ||
89 | */ | ||
90 | #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0)) | ||
91 | #define HW_APBH_CTRL1_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4)) | ||
92 | #define HW_APBH_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8)) | ||
93 | #define HW_APBH_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc)) | ||
94 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 16 | ||
95 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff0000 | ||
96 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000) | ||
97 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
98 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
99 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
100 | |||
101 | /** | ||
102 | * Register: HW_APBH_DEVSEL | ||
103 | * Address: 0x20 | ||
104 | * SCT: no | ||
105 | */ | ||
106 | #define HW_APBH_DEVSEL (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20)) | ||
107 | #define BP_APBH_DEVSEL_CH7 28 | ||
108 | #define BM_APBH_DEVSEL_CH7 0xf0000000 | ||
109 | #define BF_APBH_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
110 | #define BP_APBH_DEVSEL_CH6 24 | ||
111 | #define BM_APBH_DEVSEL_CH6 0xf000000 | ||
112 | #define BF_APBH_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
113 | #define BP_APBH_DEVSEL_CH5 20 | ||
114 | #define BM_APBH_DEVSEL_CH5 0xf00000 | ||
115 | #define BF_APBH_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
116 | #define BP_APBH_DEVSEL_CH4 16 | ||
117 | #define BM_APBH_DEVSEL_CH4 0xf0000 | ||
118 | #define BF_APBH_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
119 | #define BP_APBH_DEVSEL_CH3 12 | ||
120 | #define BM_APBH_DEVSEL_CH3 0xf000 | ||
121 | #define BF_APBH_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
122 | #define BP_APBH_DEVSEL_CH2 8 | ||
123 | #define BM_APBH_DEVSEL_CH2 0xf00 | ||
124 | #define BF_APBH_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
125 | #define BP_APBH_DEVSEL_CH1 4 | ||
126 | #define BM_APBH_DEVSEL_CH1 0xf0 | ||
127 | #define BF_APBH_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
128 | #define BP_APBH_DEVSEL_CH0 0 | ||
129 | #define BM_APBH_DEVSEL_CH0 0xf | ||
130 | #define BF_APBH_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
131 | |||
132 | /** | ||
133 | * Register: HW_APBH_CHn_DEBUG2 | ||
134 | * Address: 0x90+n*0x70 | ||
135 | * SCT: no | ||
136 | */ | ||
137 | #define HW_APBH_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70)) | ||
138 | #define BP_APBH_CHn_DEBUG2_APB_BYTES 16 | ||
139 | #define BM_APBH_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
140 | #define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
141 | #define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 | ||
142 | #define BM_APBH_CHn_DEBUG2_AHB_BYTES 0xffff | ||
143 | #define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
144 | |||
145 | /** | ||
146 | * Register: HW_APBH_CHn_CURCMDAR | ||
147 | * Address: 0x30+n*0x70 | ||
148 | * SCT: no | ||
149 | */ | ||
150 | #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30+(n)*0x70)) | ||
151 | #define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 | ||
152 | #define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
153 | #define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
154 | |||
155 | /** | ||
156 | * Register: HW_APBH_CHn_BAR | ||
157 | * Address: 0x60+n*0x70 | ||
158 | * SCT: no | ||
159 | */ | ||
160 | #define HW_APBH_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70)) | ||
161 | #define BP_APBH_CHn_BAR_ADDRESS 0 | ||
162 | #define BM_APBH_CHn_BAR_ADDRESS 0xffffffff | ||
163 | #define BF_APBH_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_APBH_CHn_CMD | ||
167 | * Address: 0x50+n*0x70 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_APBH_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70)) | ||
171 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
172 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xffff0000 | ||
173 | #define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
174 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
175 | #define BM_APBH_CHn_CMD_CMDWORDS 0xf000 | ||
176 | #define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
177 | #define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 | ||
178 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x80 | ||
179 | #define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
180 | #define BP_APBH_CHn_CMD_SEMAPHORE 6 | ||
181 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x40 | ||
182 | #define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
183 | #define BP_APBH_CHn_CMD_NANDWAIT4READY 5 | ||
184 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x20 | ||
185 | #define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & 0x20) | ||
186 | #define BP_APBH_CHn_CMD_NANDLOCK 4 | ||
187 | #define BM_APBH_CHn_CMD_NANDLOCK 0x10 | ||
188 | #define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & 0x10) | ||
189 | #define BP_APBH_CHn_CMD_IRQONCMPLT 3 | ||
190 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x8 | ||
191 | #define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
192 | #define BP_APBH_CHn_CMD_CHAIN 2 | ||
193 | #define BM_APBH_CHn_CMD_CHAIN 0x4 | ||
194 | #define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
195 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
196 | #define BM_APBH_CHn_CMD_COMMAND 0x3 | ||
197 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
198 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
199 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
200 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 | ||
201 | #define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
202 | #define BF_APBH_CHn_CMD_COMMAND_V(v) ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
203 | |||
204 | /** | ||
205 | * Register: HW_APBH_CHn_NXTCMDAR | ||
206 | * Address: 0x40+n*0x70 | ||
207 | * SCT: no | ||
208 | */ | ||
209 | #define HW_APBH_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70)) | ||
210 | #define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 | ||
211 | #define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
212 | #define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
213 | |||
214 | /** | ||
215 | * Register: HW_APBH_CHn_SEMA | ||
216 | * Address: 0x70+n*0x70 | ||
217 | * SCT: no | ||
218 | */ | ||
219 | #define HW_APBH_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70)) | ||
220 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
221 | #define BM_APBH_CHn_SEMA_PHORE 0xff0000 | ||
222 | #define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
223 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
224 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0xff | ||
225 | #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
226 | |||
227 | /** | ||
228 | * Register: HW_APBH_CHn_DEBUG1 | ||
229 | * Address: 0x80+n*0x70 | ||
230 | * SCT: no | ||
231 | */ | ||
232 | #define HW_APBH_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70)) | ||
233 | #define BP_APBH_CHn_DEBUG1_REQ 31 | ||
234 | #define BM_APBH_CHn_DEBUG1_REQ 0x80000000 | ||
235 | #define BF_APBH_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
236 | #define BP_APBH_CHn_DEBUG1_BURST 30 | ||
237 | #define BM_APBH_CHn_DEBUG1_BURST 0x40000000 | ||
238 | #define BF_APBH_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
239 | #define BP_APBH_CHn_DEBUG1_KICK 29 | ||
240 | #define BM_APBH_CHn_DEBUG1_KICK 0x20000000 | ||
241 | #define BF_APBH_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
242 | #define BP_APBH_CHn_DEBUG1_END 28 | ||
243 | #define BM_APBH_CHn_DEBUG1_END 0x10000000 | ||
244 | #define BF_APBH_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
245 | #define BP_APBH_CHn_DEBUG1_RSVD2 25 | ||
246 | #define BM_APBH_CHn_DEBUG1_RSVD2 0xe000000 | ||
247 | #define BF_APBH_CHn_DEBUG1_RSVD2(v) (((v) << 25) & 0xe000000) | ||
248 | #define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
249 | #define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
250 | #define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
251 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
252 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
253 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
254 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
255 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
256 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
257 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
258 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
259 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
260 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
261 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
262 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
263 | #define BP_APBH_CHn_DEBUG1_RSVD1 5 | ||
264 | #define BM_APBH_CHn_DEBUG1_RSVD1 0xfffe0 | ||
265 | #define BF_APBH_CHn_DEBUG1_RSVD1(v) (((v) << 5) & 0xfffe0) | ||
266 | #define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 | ||
267 | #define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x1f | ||
268 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
269 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
270 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
271 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
272 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
273 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
274 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
275 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
276 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
277 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
278 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
279 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
280 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
281 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
282 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
283 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
284 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
285 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
286 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
287 | |||
288 | #endif /* __HEADERGEN__STMP3600__APBH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h new file mode 100644 index 0000000000..fcb9949616 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h | |||
@@ -0,0 +1,276 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__APBX__H__ | ||
24 | #define __HEADERGEN__STMP3600__APBX__H__ | ||
25 | |||
26 | #define REGS_APBX_BASE (0x80024000) | ||
27 | |||
28 | #define REGS_APBX_VERSION "2.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_APBX_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_APBX_CTRL0 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0)) | ||
36 | #define HW_APBX_CTRL0_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4)) | ||
37 | #define HW_APBX_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8)) | ||
38 | #define HW_APBX_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc)) | ||
39 | #define BP_APBX_CTRL0_SFTRST 31 | ||
40 | #define BM_APBX_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_APBX_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_APBX_CTRL0_CLKGATE 30 | ||
43 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_APBX_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_APBX_CTRL0_RESET_CHANNEL 16 | ||
46 | #define BM_APBX_CTRL0_RESET_CHANNEL 0xff0000 | ||
47 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN 0x1 | ||
48 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT 0x2 | ||
49 | #define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX 0x4 | ||
50 | #define BV_APBX_CTRL0_RESET_CHANNEL__I2C 0x8 | ||
51 | #define BV_APBX_CTRL0_RESET_CHANNEL__LCDIF 0x10 | ||
52 | #define BV_APBX_CTRL0_RESET_CHANNEL__DRI 0x20 | ||
53 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX 0x30 | ||
54 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX 0x30 | ||
55 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX 0x40 | ||
56 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX 0x40 | ||
57 | #define BF_APBX_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
58 | #define BF_APBX_CTRL0_RESET_CHANNEL_V(v) ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
59 | #define BP_APBX_CTRL0_FREEZE_CHANNEL 0 | ||
60 | #define BM_APBX_CTRL0_FREEZE_CHANNEL 0xff | ||
61 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN 0x1 | ||
62 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT 0x2 | ||
63 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX 0x4 | ||
64 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C 0x8 | ||
65 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__LCDIF 0x10 | ||
66 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI 0x20 | ||
67 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX 0x30 | ||
68 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX 0x30 | ||
69 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX 0x40 | ||
70 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX 0x40 | ||
71 | #define BF_APBX_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
72 | #define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
73 | |||
74 | /** | ||
75 | * Register: HW_APBX_CTRL1 | ||
76 | * Address: 0x10 | ||
77 | * SCT: yes | ||
78 | */ | ||
79 | #define HW_APBX_CTRL1 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0)) | ||
80 | #define HW_APBX_CTRL1_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4)) | ||
81 | #define HW_APBX_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8)) | ||
82 | #define HW_APBX_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc)) | ||
83 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 16 | ||
84 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff0000 | ||
85 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000) | ||
86 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
87 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
88 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
89 | |||
90 | /** | ||
91 | * Register: HW_APBX_DEVSEL | ||
92 | * Address: 0x20 | ||
93 | * SCT: no | ||
94 | */ | ||
95 | #define HW_APBX_DEVSEL (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20)) | ||
96 | #define BP_APBX_DEVSEL_CH7 28 | ||
97 | #define BM_APBX_DEVSEL_CH7 0xf0000000 | ||
98 | #define BV_APBX_DEVSEL_CH7__USE_UART 0x0 | ||
99 | #define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 | ||
100 | #define BF_APBX_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
101 | #define BF_APBX_DEVSEL_CH7_V(v) ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000) | ||
102 | #define BP_APBX_DEVSEL_CH6 24 | ||
103 | #define BM_APBX_DEVSEL_CH6 0xf000000 | ||
104 | #define BV_APBX_DEVSEL_CH6__USE_UART 0x0 | ||
105 | #define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 | ||
106 | #define BF_APBX_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
107 | #define BF_APBX_DEVSEL_CH6_V(v) ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000) | ||
108 | #define BP_APBX_DEVSEL_CH5 20 | ||
109 | #define BM_APBX_DEVSEL_CH5 0xf00000 | ||
110 | #define BF_APBX_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
111 | #define BP_APBX_DEVSEL_CH4 16 | ||
112 | #define BM_APBX_DEVSEL_CH4 0xf0000 | ||
113 | #define BF_APBX_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
114 | #define BP_APBX_DEVSEL_CH3 12 | ||
115 | #define BM_APBX_DEVSEL_CH3 0xf000 | ||
116 | #define BF_APBX_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
117 | #define BP_APBX_DEVSEL_CH2 8 | ||
118 | #define BM_APBX_DEVSEL_CH2 0xf00 | ||
119 | #define BF_APBX_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
120 | #define BP_APBX_DEVSEL_CH1 4 | ||
121 | #define BM_APBX_DEVSEL_CH1 0xf0 | ||
122 | #define BF_APBX_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
123 | #define BP_APBX_DEVSEL_CH0 0 | ||
124 | #define BM_APBX_DEVSEL_CH0 0xf | ||
125 | #define BF_APBX_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
126 | |||
127 | /** | ||
128 | * Register: HW_APBX_CHn_NXTCMDAR | ||
129 | * Address: 0x40+n*0x70 | ||
130 | * SCT: no | ||
131 | */ | ||
132 | #define HW_APBX_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70)) | ||
133 | #define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 | ||
134 | #define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
135 | #define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
136 | |||
137 | /** | ||
138 | * Register: HW_APBX_CHn_DEBUG2 | ||
139 | * Address: 0x90+n*0x70 | ||
140 | * SCT: no | ||
141 | */ | ||
142 | #define HW_APBX_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70)) | ||
143 | #define BP_APBX_CHn_DEBUG2_APB_BYTES 16 | ||
144 | #define BM_APBX_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
145 | #define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
146 | #define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 | ||
147 | #define BM_APBX_CHn_DEBUG2_AHB_BYTES 0xffff | ||
148 | #define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
149 | |||
150 | /** | ||
151 | * Register: HW_APBX_CHn_BAR | ||
152 | * Address: 0x60+n*0x70 | ||
153 | * SCT: no | ||
154 | */ | ||
155 | #define HW_APBX_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70)) | ||
156 | #define BP_APBX_CHn_BAR_ADDRESS 0 | ||
157 | #define BM_APBX_CHn_BAR_ADDRESS 0xffffffff | ||
158 | #define BF_APBX_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
159 | |||
160 | /** | ||
161 | * Register: HW_APBX_CHn_CMD | ||
162 | * Address: 0x50+n*0x70 | ||
163 | * SCT: no | ||
164 | */ | ||
165 | #define HW_APBX_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70)) | ||
166 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 | ||
167 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xffff0000 | ||
168 | #define BF_APBX_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
169 | #define BP_APBX_CHn_CMD_CMDWORDS 12 | ||
170 | #define BM_APBX_CHn_CMD_CMDWORDS 0xf000 | ||
171 | #define BF_APBX_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
172 | #define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 | ||
173 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x80 | ||
174 | #define BF_APBX_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
175 | #define BP_APBX_CHn_CMD_SEMAPHORE 6 | ||
176 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x40 | ||
177 | #define BF_APBX_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
178 | #define BP_APBX_CHn_CMD_IRQONCMPLT 3 | ||
179 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x8 | ||
180 | #define BF_APBX_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
181 | #define BP_APBX_CHn_CMD_CHAIN 2 | ||
182 | #define BM_APBX_CHn_CMD_CHAIN 0x4 | ||
183 | #define BF_APBX_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
184 | #define BP_APBX_CHn_CMD_COMMAND 0 | ||
185 | #define BM_APBX_CHn_CMD_COMMAND 0x3 | ||
186 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
187 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
188 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
189 | #define BF_APBX_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
190 | #define BF_APBX_CHn_CMD_COMMAND_V(v) ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
191 | |||
192 | /** | ||
193 | * Register: HW_APBX_CHn_DEBUG1 | ||
194 | * Address: 0x80+n*0x70 | ||
195 | * SCT: no | ||
196 | */ | ||
197 | #define HW_APBX_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70)) | ||
198 | #define BP_APBX_CHn_DEBUG1_REQ 31 | ||
199 | #define BM_APBX_CHn_DEBUG1_REQ 0x80000000 | ||
200 | #define BF_APBX_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
201 | #define BP_APBX_CHn_DEBUG1_BURST 30 | ||
202 | #define BM_APBX_CHn_DEBUG1_BURST 0x40000000 | ||
203 | #define BF_APBX_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
204 | #define BP_APBX_CHn_DEBUG1_KICK 29 | ||
205 | #define BM_APBX_CHn_DEBUG1_KICK 0x20000000 | ||
206 | #define BF_APBX_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
207 | #define BP_APBX_CHn_DEBUG1_END 28 | ||
208 | #define BM_APBX_CHn_DEBUG1_END 0x10000000 | ||
209 | #define BF_APBX_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
210 | #define BP_APBX_CHn_DEBUG1_RSVD2 25 | ||
211 | #define BM_APBX_CHn_DEBUG1_RSVD2 0xe000000 | ||
212 | #define BF_APBX_CHn_DEBUG1_RSVD2(v) (((v) << 25) & 0xe000000) | ||
213 | #define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
214 | #define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
215 | #define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
216 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
217 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
218 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
219 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
220 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
221 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
222 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
223 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
224 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
225 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
226 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
227 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
228 | #define BP_APBX_CHn_DEBUG1_RSVD1 5 | ||
229 | #define BM_APBX_CHn_DEBUG1_RSVD1 0xfffe0 | ||
230 | #define BF_APBX_CHn_DEBUG1_RSVD1(v) (((v) << 5) & 0xfffe0) | ||
231 | #define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 | ||
232 | #define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x1f | ||
233 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
234 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
235 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
236 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
237 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
238 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
239 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
240 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
241 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
242 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
243 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
244 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
245 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
246 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
247 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
248 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
249 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
250 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
251 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
252 | |||
253 | /** | ||
254 | * Register: HW_APBX_CHn_SEMA | ||
255 | * Address: 0x70+n*0x70 | ||
256 | * SCT: no | ||
257 | */ | ||
258 | #define HW_APBX_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70)) | ||
259 | #define BP_APBX_CHn_SEMA_PHORE 16 | ||
260 | #define BM_APBX_CHn_SEMA_PHORE 0xff0000 | ||
261 | #define BF_APBX_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
262 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 | ||
263 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0xff | ||
264 | #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
265 | |||
266 | /** | ||
267 | * Register: HW_APBX_CHn_CURCMDAR | ||
268 | * Address: 0x30+n*0x70 | ||
269 | * SCT: no | ||
270 | */ | ||
271 | #define HW_APBX_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30+(n)*0x70)) | ||
272 | #define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 | ||
273 | #define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
274 | #define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
275 | |||
276 | #endif /* __HEADERGEN__STMP3600__APBX__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h new file mode 100644 index 0000000000..af64d3a4ef --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h | |||
@@ -0,0 +1,268 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__ARC__H__ | ||
24 | #define __HEADERGEN__STMP3600__ARC__H__ | ||
25 | |||
26 | #define REGS_ARC_BASE (0x80080000) | ||
27 | |||
28 | #define REGS_ARC_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ARC_BASE | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_ARC_BASE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0)) | ||
36 | |||
37 | /** | ||
38 | * Register: HW_ARC_ID | ||
39 | * Address: 0 | ||
40 | * SCT: no | ||
41 | */ | ||
42 | #define HW_ARC_ID (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0)) | ||
43 | |||
44 | /** | ||
45 | * Register: HW_ARC_HCSPARAMS | ||
46 | * Address: 0x104 | ||
47 | * SCT: no | ||
48 | */ | ||
49 | #define HW_ARC_HCSPARAMS (*(volatile unsigned long *)(REGS_ARC_BASE + 0x104)) | ||
50 | |||
51 | /** | ||
52 | * Register: HW_ARC_USBCMD | ||
53 | * Address: 0x140 | ||
54 | * SCT: no | ||
55 | */ | ||
56 | #define HW_ARC_USBCMD (*(volatile unsigned long *)(REGS_ARC_BASE + 0x140)) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_ARC_USBSTS | ||
60 | * Address: 0x144 | ||
61 | * SCT: no | ||
62 | */ | ||
63 | #define HW_ARC_USBSTS (*(volatile unsigned long *)(REGS_ARC_BASE + 0x144)) | ||
64 | |||
65 | /** | ||
66 | * Register: HW_ARC_USBINTR | ||
67 | * Address: 0x148 | ||
68 | * SCT: no | ||
69 | */ | ||
70 | #define HW_ARC_USBINTR (*(volatile unsigned long *)(REGS_ARC_BASE + 0x148)) | ||
71 | |||
72 | /** | ||
73 | * Register: HW_ARC_FRINDEX | ||
74 | * Address: 0x14c | ||
75 | * SCT: no | ||
76 | */ | ||
77 | #define HW_ARC_FRINDEX (*(volatile unsigned long *)(REGS_ARC_BASE + 0x14c)) | ||
78 | |||
79 | /** | ||
80 | * Register: HW_ARC_DEVADDR | ||
81 | * Address: 0x154 | ||
82 | * SCT: no | ||
83 | */ | ||
84 | #define HW_ARC_DEVADDR (*(volatile unsigned long *)(REGS_ARC_BASE + 0x154)) | ||
85 | |||
86 | /** | ||
87 | * Register: HW_ARC_ENDPTLISTADDR | ||
88 | * Address: 0x158 | ||
89 | * SCT: no | ||
90 | */ | ||
91 | #define HW_ARC_ENDPTLISTADDR (*(volatile unsigned long *)(REGS_ARC_BASE + 0x158)) | ||
92 | |||
93 | /** | ||
94 | * Register: HW_ARC_PORTSC1 | ||
95 | * Address: 0x184 | ||
96 | * SCT: no | ||
97 | */ | ||
98 | #define HW_ARC_PORTSC1 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x184)) | ||
99 | |||
100 | /** | ||
101 | * Register: HW_ARC_OTGSC | ||
102 | * Address: 0x1a4 | ||
103 | * SCT: no | ||
104 | */ | ||
105 | #define HW_ARC_OTGSC (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a4)) | ||
106 | |||
107 | /** | ||
108 | * Register: HW_ARC_USBMODE | ||
109 | * Address: 0x1a8 | ||
110 | * SCT: no | ||
111 | */ | ||
112 | #define HW_ARC_USBMODE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a8)) | ||
113 | |||
114 | /** | ||
115 | * Register: HW_ARC_ENDPTSETUPSTAT | ||
116 | * Address: 0x1ac | ||
117 | * SCT: no | ||
118 | */ | ||
119 | #define HW_ARC_ENDPTSETUPSTAT (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ac)) | ||
120 | |||
121 | /** | ||
122 | * Register: HW_ARC_ENDPTPRIME | ||
123 | * Address: 0x1b0 | ||
124 | * SCT: no | ||
125 | */ | ||
126 | #define HW_ARC_ENDPTPRIME (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b0)) | ||
127 | |||
128 | /** | ||
129 | * Register: HW_ARC_ENDPTFLUSH | ||
130 | * Address: 0x1b4 | ||
131 | * SCT: no | ||
132 | */ | ||
133 | #define HW_ARC_ENDPTFLUSH (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b4)) | ||
134 | |||
135 | /** | ||
136 | * Register: HW_ARC_ENDPTSTATUS | ||
137 | * Address: 0x1b8 | ||
138 | * SCT: no | ||
139 | */ | ||
140 | #define HW_ARC_ENDPTSTATUS (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b8)) | ||
141 | |||
142 | /** | ||
143 | * Register: HW_ARC_ENDPTCOMPLETE | ||
144 | * Address: 0x1bc | ||
145 | * SCT: no | ||
146 | */ | ||
147 | #define HW_ARC_ENDPTCOMPLETE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1bc)) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_ARC_ENDPTCTRL0 | ||
151 | * Address: 0x1c0 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_ARC_ENDPTCTRL0 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0)) | ||
155 | |||
156 | /** | ||
157 | * Register: HW_ARC_ENDPTCTRL1 | ||
158 | * Address: 0x1c4 | ||
159 | * SCT: no | ||
160 | */ | ||
161 | #define HW_ARC_ENDPTCTRL1 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c4)) | ||
162 | |||
163 | /** | ||
164 | * Register: HW_ARC_ENDPTCTRL2 | ||
165 | * Address: 0x1c8 | ||
166 | * SCT: no | ||
167 | */ | ||
168 | #define HW_ARC_ENDPTCTRL2 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c8)) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_ARC_ENDPTCTRL3 | ||
172 | * Address: 0x1cc | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_ARC_ENDPTCTRL3 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1cc)) | ||
176 | |||
177 | /** | ||
178 | * Register: HW_ARC_ENDPTCTRL4 | ||
179 | * Address: 0x1d0 | ||
180 | * SCT: no | ||
181 | */ | ||
182 | #define HW_ARC_ENDPTCTRL4 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d0)) | ||
183 | |||
184 | /** | ||
185 | * Register: HW_ARC_ENDPTCTRL5 | ||
186 | * Address: 0x1d4 | ||
187 | * SCT: no | ||
188 | */ | ||
189 | #define HW_ARC_ENDPTCTRL5 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d4)) | ||
190 | |||
191 | /** | ||
192 | * Register: HW_ARC_ENDPTCTRL6 | ||
193 | * Address: 0x1d8 | ||
194 | * SCT: no | ||
195 | */ | ||
196 | #define HW_ARC_ENDPTCTRL6 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d8)) | ||
197 | |||
198 | /** | ||
199 | * Register: HW_ARC_ENDPTCTRL7 | ||
200 | * Address: 0x1dc | ||
201 | * SCT: no | ||
202 | */ | ||
203 | #define HW_ARC_ENDPTCTRL7 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1dc)) | ||
204 | |||
205 | /** | ||
206 | * Register: HW_ARC_ENDPTCTRL8 | ||
207 | * Address: 0x1e0 | ||
208 | * SCT: no | ||
209 | */ | ||
210 | #define HW_ARC_ENDPTCTRL8 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e0)) | ||
211 | |||
212 | /** | ||
213 | * Register: HW_ARC_ENDPTCTRL9 | ||
214 | * Address: 0x1e4 | ||
215 | * SCT: no | ||
216 | */ | ||
217 | #define HW_ARC_ENDPTCTRL9 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e4)) | ||
218 | |||
219 | /** | ||
220 | * Register: HW_ARC_ENDPTCTRL10 | ||
221 | * Address: 0x1e8 | ||
222 | * SCT: no | ||
223 | */ | ||
224 | #define HW_ARC_ENDPTCTRL10 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e8)) | ||
225 | |||
226 | /** | ||
227 | * Register: HW_ARC_ENDPTCTRL11 | ||
228 | * Address: 0x1ec | ||
229 | * SCT: no | ||
230 | */ | ||
231 | #define HW_ARC_ENDPTCTRL11 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ec)) | ||
232 | |||
233 | /** | ||
234 | * Register: HW_ARC_ENDPTCTRL12 | ||
235 | * Address: 0x1f0 | ||
236 | * SCT: no | ||
237 | */ | ||
238 | #define HW_ARC_ENDPTCTRL12 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f0)) | ||
239 | |||
240 | /** | ||
241 | * Register: HW_ARC_ENDPTCTRL13 | ||
242 | * Address: 0x1f4 | ||
243 | * SCT: no | ||
244 | */ | ||
245 | #define HW_ARC_ENDPTCTRL13 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f4)) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_ARC_ENDPTCTRL14 | ||
249 | * Address: 0x1f8 | ||
250 | * SCT: no | ||
251 | */ | ||
252 | #define HW_ARC_ENDPTCTRL14 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f8)) | ||
253 | |||
254 | /** | ||
255 | * Register: HW_ARC_ENDPTCTRL15 | ||
256 | * Address: 0x1fc | ||
257 | * SCT: no | ||
258 | */ | ||
259 | #define HW_ARC_ENDPTCTRL15 (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1fc)) | ||
260 | |||
261 | /** | ||
262 | * Register: HW_ARC_ENDPTCTRLn | ||
263 | * Address: 0x1c0+n*0x4 | ||
264 | * SCT: no | ||
265 | */ | ||
266 | #define HW_ARC_ENDPTCTRLn(n) (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0+(n)*0x4)) | ||
267 | |||
268 | #endif /* __HEADERGEN__STMP3600__ARC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h new file mode 100644 index 0000000000..8b5fbac6ea --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h | |||
@@ -0,0 +1,281 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.5.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__AUDIOIN__H__ | ||
24 | #define __HEADERGEN__STMP3600__AUDIOIN__H__ | ||
25 | |||
26 | #define REGS_AUDIOIN_BASE (0x8004c000) | ||
27 | |||
28 | #define REGS_AUDIOIN_VERSION "2.5.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_AUDIOIN_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_AUDIOIN_CTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0)) | ||
36 | #define HW_AUDIOIN_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4)) | ||
37 | #define HW_AUDIOIN_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8)) | ||
38 | #define HW_AUDIOIN_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc)) | ||
39 | #define BP_AUDIOIN_CTRL_SFTRST 31 | ||
40 | #define BM_AUDIOIN_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_AUDIOIN_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_AUDIOIN_CTRL_CLKGATE 30 | ||
43 | #define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_AUDIOIN_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 | ||
46 | #define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
47 | #define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
48 | #define BP_AUDIOIN_CTRL_LR_SWAP 10 | ||
49 | #define BM_AUDIOIN_CTRL_LR_SWAP 0x400 | ||
50 | #define BF_AUDIOIN_CTRL_LR_SWAP(v) (((v) << 10) & 0x400) | ||
51 | #define BP_AUDIOIN_CTRL_EDGE_SYNC 9 | ||
52 | #define BM_AUDIOIN_CTRL_EDGE_SYNC 0x200 | ||
53 | #define BF_AUDIOIN_CTRL_EDGE_SYNC(v) (((v) << 9) & 0x200) | ||
54 | #define BP_AUDIOIN_CTRL_INVERT_1BIT 8 | ||
55 | #define BM_AUDIOIN_CTRL_INVERT_1BIT 0x100 | ||
56 | #define BF_AUDIOIN_CTRL_INVERT_1BIT(v) (((v) << 8) & 0x100) | ||
57 | #define BP_AUDIOIN_CTRL_OFFSET_ENABLE 7 | ||
58 | #define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x80 | ||
59 | #define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v) (((v) << 7) & 0x80) | ||
60 | #define BP_AUDIOIN_CTRL_HPF_ENABLE 6 | ||
61 | #define BM_AUDIOIN_CTRL_HPF_ENABLE 0x40 | ||
62 | #define BF_AUDIOIN_CTRL_HPF_ENABLE(v) (((v) << 6) & 0x40) | ||
63 | #define BP_AUDIOIN_CTRL_WORD_LENGTH 5 | ||
64 | #define BM_AUDIOIN_CTRL_WORD_LENGTH 0x20 | ||
65 | #define BF_AUDIOIN_CTRL_WORD_LENGTH(v) (((v) << 5) & 0x20) | ||
66 | #define BP_AUDIOIN_CTRL_LOOPBACK 4 | ||
67 | #define BM_AUDIOIN_CTRL_LOOPBACK 0x10 | ||
68 | #define BF_AUDIOIN_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
69 | #define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
70 | #define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
71 | #define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
72 | #define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
73 | #define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
74 | #define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
75 | #define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
76 | #define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
77 | #define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
78 | #define BP_AUDIOIN_CTRL_RUN 0 | ||
79 | #define BM_AUDIOIN_CTRL_RUN 0x1 | ||
80 | #define BF_AUDIOIN_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
81 | |||
82 | /** | ||
83 | * Register: HW_AUDIOIN_STAT | ||
84 | * Address: 0x10 | ||
85 | * SCT: no | ||
86 | */ | ||
87 | #define HW_AUDIOIN_STAT (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10)) | ||
88 | #define BP_AUDIOIN_STAT_ADC_PRESENT 31 | ||
89 | #define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 | ||
90 | #define BF_AUDIOIN_STAT_ADC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_AUDIOIN_ADCSRR | ||
94 | * Address: 0x20 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_AUDIOIN_ADCSRR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0)) | ||
98 | #define HW_AUDIOIN_ADCSRR_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4)) | ||
99 | #define HW_AUDIOIN_ADCSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8)) | ||
100 | #define HW_AUDIOIN_ADCSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc)) | ||
101 | #define BP_AUDIOIN_ADCSRR_OSR 31 | ||
102 | #define BM_AUDIOIN_ADCSRR_OSR 0x80000000 | ||
103 | #define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 | ||
104 | #define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 | ||
105 | #define BF_AUDIOIN_ADCSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
106 | #define BF_AUDIOIN_ADCSRR_OSR_V(v) ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000) | ||
107 | #define BP_AUDIOIN_ADCSRR_BASEMULT 28 | ||
108 | #define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 | ||
109 | #define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 | ||
110 | #define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
111 | #define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 | ||
112 | #define BF_AUDIOIN_ADCSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
113 | #define BF_AUDIOIN_ADCSRR_BASEMULT_V(v) ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000) | ||
114 | #define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 | ||
115 | #define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x7000000 | ||
116 | #define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
117 | #define BP_AUDIOIN_ADCSRR_SRC_INT 16 | ||
118 | #define BM_AUDIOIN_ADCSRR_SRC_INT 0x1f0000 | ||
119 | #define BF_AUDIOIN_ADCSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
120 | #define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 | ||
121 | #define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x1fff | ||
122 | #define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
123 | |||
124 | /** | ||
125 | * Register: HW_AUDIOIN_ADCVOLUME | ||
126 | * Address: 0x30 | ||
127 | * SCT: yes | ||
128 | */ | ||
129 | #define HW_AUDIOIN_ADCVOLUME (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0)) | ||
130 | #define HW_AUDIOIN_ADCVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4)) | ||
131 | #define HW_AUDIOIN_ADCVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8)) | ||
132 | #define HW_AUDIOIN_ADCVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc)) | ||
133 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 28 | ||
134 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
135 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
136 | #define BP_AUDIOIN_ADCVOLUME_EN_ZCD 25 | ||
137 | #define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x2000000 | ||
138 | #define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
139 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 | ||
140 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0xff0000 | ||
141 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
142 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
143 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
144 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
145 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 | ||
146 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0xff | ||
147 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_AUDIOIN_ADCDEBUG | ||
151 | * Address: 0x40 | ||
152 | * SCT: yes | ||
153 | */ | ||
154 | #define HW_AUDIOIN_ADCDEBUG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0)) | ||
155 | #define HW_AUDIOIN_ADCDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4)) | ||
156 | #define HW_AUDIOIN_ADCDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8)) | ||
157 | #define HW_AUDIOIN_ADCDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc)) | ||
158 | #define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 31 | ||
159 | #define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 | ||
160 | #define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v) (((v) << 31) & 0x80000000) | ||
161 | #define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 3 | ||
162 | #define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x8 | ||
163 | #define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8) | ||
164 | #define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 2 | ||
165 | #define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x4 | ||
166 | #define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
167 | #define BP_AUDIOIN_ADCDEBUG_DMA_PREQ 1 | ||
168 | #define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x2 | ||
169 | #define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
170 | #define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS 0 | ||
171 | #define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x1 | ||
172 | #define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_AUDIOIN_ADCVOL | ||
176 | * Address: 0x50 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_AUDIOIN_ADCVOL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0)) | ||
180 | #define HW_AUDIOIN_ADCVOL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4)) | ||
181 | #define HW_AUDIOIN_ADCVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8)) | ||
182 | #define HW_AUDIOIN_ADCVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc)) | ||
183 | #define BP_AUDIOIN_ADCVOL_SELECT_LEFT 28 | ||
184 | #define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x30000000 | ||
185 | #define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) (((v) << 28) & 0x30000000) | ||
186 | #define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 24 | ||
187 | #define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x3000000 | ||
188 | #define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) (((v) << 24) & 0x3000000) | ||
189 | #define BP_AUDIOIN_ADCVOL_MUTE 8 | ||
190 | #define BM_AUDIOIN_ADCVOL_MUTE 0x100 | ||
191 | #define BF_AUDIOIN_ADCVOL_MUTE(v) (((v) << 8) & 0x100) | ||
192 | #define BP_AUDIOIN_ADCVOL_GAIN_LEFT 4 | ||
193 | #define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0xf0 | ||
194 | #define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) (((v) << 4) & 0xf0) | ||
195 | #define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 | ||
196 | #define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0xf | ||
197 | #define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) (((v) << 0) & 0xf) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_AUDIOIN_MICLINE | ||
201 | * Address: 0x60 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_AUDIOIN_MICLINE (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0)) | ||
205 | #define HW_AUDIOIN_MICLINE_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4)) | ||
206 | #define HW_AUDIOIN_MICLINE_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8)) | ||
207 | #define HW_AUDIOIN_MICLINE_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc)) | ||
208 | #define BP_AUDIOIN_MICLINE_ATTEN_LINE 30 | ||
209 | #define BM_AUDIOIN_MICLINE_ATTEN_LINE 0x40000000 | ||
210 | #define BF_AUDIOIN_MICLINE_ATTEN_LINE(v) (((v) << 30) & 0x40000000) | ||
211 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE1 29 | ||
212 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 | ||
213 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v) (((v) << 29) & 0x20000000) | ||
214 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE2 28 | ||
215 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 | ||
216 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v) (((v) << 28) & 0x10000000) | ||
217 | #define BP_AUDIOIN_MICLINE_MIC_SELECT 24 | ||
218 | #define BM_AUDIOIN_MICLINE_MIC_SELECT 0x1000000 | ||
219 | #define BF_AUDIOIN_MICLINE_MIC_SELECT(v) (((v) << 24) & 0x1000000) | ||
220 | #define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 | ||
221 | #define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x300000 | ||
222 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off 0x0 | ||
223 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm 0x1 | ||
224 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm 0x2 | ||
225 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm 0x3 | ||
226 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) (((v) << 20) & 0x300000) | ||
227 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v) ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000) | ||
228 | #define BP_AUDIOIN_MICLINE_MIC_BIAS 16 | ||
229 | #define BM_AUDIOIN_MICLINE_MIC_BIAS 0x70000 | ||
230 | #define BF_AUDIOIN_MICLINE_MIC_BIAS(v) (((v) << 16) & 0x70000) | ||
231 | #define BP_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP 8 | ||
232 | #define BM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP 0x100 | ||
233 | #define BF_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP(v) (((v) << 8) & 0x100) | ||
234 | #define BP_AUDIOIN_MICLINE_MIC_GAIN 0 | ||
235 | #define BM_AUDIOIN_MICLINE_MIC_GAIN 0x3 | ||
236 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB 0x0 | ||
237 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB 0x1 | ||
238 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB 0x2 | ||
239 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB 0x3 | ||
240 | #define BF_AUDIOIN_MICLINE_MIC_GAIN(v) (((v) << 0) & 0x3) | ||
241 | #define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v) ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3) | ||
242 | |||
243 | /** | ||
244 | * Register: HW_AUDIOIN_ANACLKCTRL | ||
245 | * Address: 0x70 | ||
246 | * SCT: yes | ||
247 | */ | ||
248 | #define HW_AUDIOIN_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0)) | ||
249 | #define HW_AUDIOIN_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4)) | ||
250 | #define HW_AUDIOIN_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8)) | ||
251 | #define HW_AUDIOIN_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc)) | ||
252 | #define BP_AUDIOIN_ANACLKCTRL_CLKGATE 31 | ||
253 | #define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 | ||
254 | #define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
255 | #define BP_AUDIOIN_ANACLKCTRL_DITHER_ENABLE 6 | ||
256 | #define BM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE 0x40 | ||
257 | #define BF_AUDIOIN_ANACLKCTRL_DITHER_ENABLE(v) (((v) << 6) & 0x40) | ||
258 | #define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER 5 | ||
259 | #define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x20 | ||
260 | #define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v) (((v) << 5) & 0x20) | ||
261 | #define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 4 | ||
262 | #define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x10 | ||
263 | #define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v) (((v) << 4) & 0x10) | ||
264 | #define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 | ||
265 | #define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x7 | ||
266 | #define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) (((v) << 0) & 0x7) | ||
267 | |||
268 | /** | ||
269 | * Register: HW_AUDIOIN_DATA | ||
270 | * Address: 0x80 | ||
271 | * SCT: no | ||
272 | */ | ||
273 | #define HW_AUDIOIN_DATA (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80)) | ||
274 | #define BP_AUDIOIN_DATA_HIGH 16 | ||
275 | #define BM_AUDIOIN_DATA_HIGH 0xffff0000 | ||
276 | #define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
277 | #define BP_AUDIOIN_DATA_LOW 0 | ||
278 | #define BM_AUDIOIN_DATA_LOW 0xffff | ||
279 | #define BF_AUDIOIN_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
280 | |||
281 | #endif /* __HEADERGEN__STMP3600__AUDIOIN__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h new file mode 100644 index 0000000000..20e639c6dd --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h | |||
@@ -0,0 +1,473 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__AUDIOOUT__H__ | ||
24 | #define __HEADERGEN__STMP3600__AUDIOOUT__H__ | ||
25 | |||
26 | #define REGS_AUDIOOUT_BASE (0x80048000) | ||
27 | |||
28 | #define REGS_AUDIOOUT_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_AUDIOOUT_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_AUDIOOUT_CTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0)) | ||
36 | #define HW_AUDIOOUT_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4)) | ||
37 | #define HW_AUDIOOUT_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8)) | ||
38 | #define HW_AUDIOOUT_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc)) | ||
39 | #define BP_AUDIOOUT_CTRL_SFTRST 31 | ||
40 | #define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_AUDIOOUT_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_AUDIOOUT_CTRL_CLKGATE 30 | ||
43 | #define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_AUDIOOUT_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 | ||
46 | #define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
47 | #define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
48 | #define BP_AUDIOOUT_CTRL_LR_SWAP 14 | ||
49 | #define BM_AUDIOOUT_CTRL_LR_SWAP 0x4000 | ||
50 | #define BF_AUDIOOUT_CTRL_LR_SWAP(v) (((v) << 14) & 0x4000) | ||
51 | #define BP_AUDIOOUT_CTRL_EDGE_SYNC 13 | ||
52 | #define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x2000 | ||
53 | #define BF_AUDIOOUT_CTRL_EDGE_SYNC(v) (((v) << 13) & 0x2000) | ||
54 | #define BP_AUDIOOUT_CTRL_INVERT_1BIT 12 | ||
55 | #define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x1000 | ||
56 | #define BF_AUDIOOUT_CTRL_INVERT_1BIT(v) (((v) << 12) & 0x1000) | ||
57 | #define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 | ||
58 | #define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x300 | ||
59 | #define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) (((v) << 8) & 0x300) | ||
60 | #define BP_AUDIOOUT_CTRL_WORD_LENGTH 6 | ||
61 | #define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x40 | ||
62 | #define BF_AUDIOOUT_CTRL_WORD_LENGTH(v) (((v) << 6) & 0x40) | ||
63 | #define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 5 | ||
64 | #define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x20 | ||
65 | #define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v) (((v) << 5) & 0x20) | ||
66 | #define BP_AUDIOOUT_CTRL_LOOPBACK 4 | ||
67 | #define BM_AUDIOOUT_CTRL_LOOPBACK 0x10 | ||
68 | #define BF_AUDIOOUT_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
69 | #define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
70 | #define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
71 | #define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
72 | #define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
73 | #define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
74 | #define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
75 | #define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
76 | #define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
77 | #define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
78 | #define BP_AUDIOOUT_CTRL_RUN 0 | ||
79 | #define BM_AUDIOOUT_CTRL_RUN 0x1 | ||
80 | #define BF_AUDIOOUT_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
81 | |||
82 | /** | ||
83 | * Register: HW_AUDIOOUT_STAT | ||
84 | * Address: 0x10 | ||
85 | * SCT: no | ||
86 | */ | ||
87 | #define HW_AUDIOOUT_STAT (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10)) | ||
88 | #define BP_AUDIOOUT_STAT_DAC_PRESENT 31 | ||
89 | #define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 | ||
90 | #define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_AUDIOOUT_DACSRR | ||
94 | * Address: 0x20 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_AUDIOOUT_DACSRR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0)) | ||
98 | #define HW_AUDIOOUT_DACSRR_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4)) | ||
99 | #define HW_AUDIOOUT_DACSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8)) | ||
100 | #define HW_AUDIOOUT_DACSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc)) | ||
101 | #define BP_AUDIOOUT_DACSRR_OSR 31 | ||
102 | #define BM_AUDIOOUT_DACSRR_OSR 0x80000000 | ||
103 | #define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 | ||
104 | #define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 | ||
105 | #define BF_AUDIOOUT_DACSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
106 | #define BF_AUDIOOUT_DACSRR_OSR_V(v) ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000) | ||
107 | #define BP_AUDIOOUT_DACSRR_BASEMULT 28 | ||
108 | #define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 | ||
109 | #define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 | ||
110 | #define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
111 | #define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 | ||
112 | #define BF_AUDIOOUT_DACSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
113 | #define BF_AUDIOOUT_DACSRR_BASEMULT_V(v) ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000) | ||
114 | #define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 | ||
115 | #define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x7000000 | ||
116 | #define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
117 | #define BP_AUDIOOUT_DACSRR_SRC_INT 16 | ||
118 | #define BM_AUDIOOUT_DACSRR_SRC_INT 0x1f0000 | ||
119 | #define BF_AUDIOOUT_DACSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
120 | #define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 | ||
121 | #define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x1fff | ||
122 | #define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
123 | |||
124 | /** | ||
125 | * Register: HW_AUDIOOUT_DACVOLUME | ||
126 | * Address: 0x30 | ||
127 | * SCT: yes | ||
128 | */ | ||
129 | #define HW_AUDIOOUT_DACVOLUME (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0)) | ||
130 | #define HW_AUDIOOUT_DACVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4)) | ||
131 | #define HW_AUDIOOUT_DACVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8)) | ||
132 | #define HW_AUDIOOUT_DACVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc)) | ||
133 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 28 | ||
134 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
135 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
136 | #define BP_AUDIOOUT_DACVOLUME_EN_ZCD 25 | ||
137 | #define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x2000000 | ||
138 | #define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
139 | #define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT 24 | ||
140 | #define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x1000000 | ||
141 | #define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v) (((v) << 24) & 0x1000000) | ||
142 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 | ||
143 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0xff0000 | ||
144 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
145 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
146 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
147 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
148 | #define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT 8 | ||
149 | #define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x100 | ||
150 | #define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v) (((v) << 8) & 0x100) | ||
151 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 | ||
152 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0xff | ||
153 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
154 | |||
155 | /** | ||
156 | * Register: HW_AUDIOOUT_DACDEBUG | ||
157 | * Address: 0x40 | ||
158 | * SCT: yes | ||
159 | */ | ||
160 | #define HW_AUDIOOUT_DACDEBUG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0)) | ||
161 | #define HW_AUDIOOUT_DACDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4)) | ||
162 | #define HW_AUDIOOUT_DACDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8)) | ||
163 | #define HW_AUDIOOUT_DACDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc)) | ||
164 | #define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 31 | ||
165 | #define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 | ||
166 | #define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v) (((v) << 31) & 0x80000000) | ||
167 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 5 | ||
168 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x20 | ||
169 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v) (((v) << 5) & 0x20) | ||
170 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 4 | ||
171 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x10 | ||
172 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v) (((v) << 4) & 0x10) | ||
173 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 3 | ||
174 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x8 | ||
175 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v) (((v) << 3) & 0x8) | ||
176 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 2 | ||
177 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x4 | ||
178 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
179 | #define BP_AUDIOOUT_DACDEBUG_DMA_PREQ 1 | ||
180 | #define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x2 | ||
181 | #define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
182 | #define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS 0 | ||
183 | #define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x1 | ||
184 | #define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
185 | |||
186 | /** | ||
187 | * Register: HW_AUDIOOUT_HPVOL | ||
188 | * Address: 0x50 | ||
189 | * SCT: yes | ||
190 | */ | ||
191 | #define HW_AUDIOOUT_HPVOL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0)) | ||
192 | #define HW_AUDIOOUT_HPVOL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4)) | ||
193 | #define HW_AUDIOOUT_HPVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8)) | ||
194 | #define HW_AUDIOOUT_HPVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc)) | ||
195 | #define BP_AUDIOOUT_HPVOL_SELECT 24 | ||
196 | #define BM_AUDIOOUT_HPVOL_SELECT 0x3000000 | ||
197 | #define BF_AUDIOOUT_HPVOL_SELECT(v) (((v) << 24) & 0x3000000) | ||
198 | #define BP_AUDIOOUT_HPVOL_MUTE 16 | ||
199 | #define BM_AUDIOOUT_HPVOL_MUTE 0x10000 | ||
200 | #define BF_AUDIOOUT_HPVOL_MUTE(v) (((v) << 16) & 0x10000) | ||
201 | #define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 | ||
202 | #define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x1f00 | ||
203 | #define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) (((v) << 8) & 0x1f00) | ||
204 | #define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 | ||
205 | #define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x1f | ||
206 | #define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) (((v) << 0) & 0x1f) | ||
207 | |||
208 | /** | ||
209 | * Register: HW_AUDIOOUT_SPKRVOL | ||
210 | * Address: 0x60 | ||
211 | * SCT: yes | ||
212 | */ | ||
213 | #define HW_AUDIOOUT_SPKRVOL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x0)) | ||
214 | #define HW_AUDIOOUT_SPKRVOL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x4)) | ||
215 | #define HW_AUDIOOUT_SPKRVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x8)) | ||
216 | #define HW_AUDIOOUT_SPKRVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0xc)) | ||
217 | #define BP_AUDIOOUT_SPKRVOL_MUTE 16 | ||
218 | #define BM_AUDIOOUT_SPKRVOL_MUTE 0x10000 | ||
219 | #define BF_AUDIOOUT_SPKRVOL_MUTE(v) (((v) << 16) & 0x10000) | ||
220 | #define BP_AUDIOOUT_SPKRVOL_VOL 0 | ||
221 | #define BM_AUDIOOUT_SPKRVOL_VOL 0xf | ||
222 | #define BF_AUDIOOUT_SPKRVOL_VOL(v) (((v) << 0) & 0xf) | ||
223 | |||
224 | /** | ||
225 | * Register: HW_AUDIOOUT_PWRDN | ||
226 | * Address: 0x70 | ||
227 | * SCT: yes | ||
228 | */ | ||
229 | #define HW_AUDIOOUT_PWRDN (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0)) | ||
230 | #define HW_AUDIOOUT_PWRDN_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4)) | ||
231 | #define HW_AUDIOOUT_PWRDN_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8)) | ||
232 | #define HW_AUDIOOUT_PWRDN_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc)) | ||
233 | #define BP_AUDIOOUT_PWRDN_SPEAKER 24 | ||
234 | #define BM_AUDIOOUT_PWRDN_SPEAKER 0x1000000 | ||
235 | #define BF_AUDIOOUT_PWRDN_SPEAKER(v) (((v) << 24) & 0x1000000) | ||
236 | #define BP_AUDIOOUT_PWRDN_SELFBIAS 20 | ||
237 | #define BM_AUDIOOUT_PWRDN_SELFBIAS 0x100000 | ||
238 | #define BF_AUDIOOUT_PWRDN_SELFBIAS(v) (((v) << 20) & 0x100000) | ||
239 | #define BP_AUDIOOUT_PWRDN_RIGHT_ADC 16 | ||
240 | #define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x10000 | ||
241 | #define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v) (((v) << 16) & 0x10000) | ||
242 | #define BP_AUDIOOUT_PWRDN_DAC 12 | ||
243 | #define BM_AUDIOOUT_PWRDN_DAC 0x1000 | ||
244 | #define BF_AUDIOOUT_PWRDN_DAC(v) (((v) << 12) & 0x1000) | ||
245 | #define BP_AUDIOOUT_PWRDN_ADC 8 | ||
246 | #define BM_AUDIOOUT_PWRDN_ADC 0x100 | ||
247 | #define BF_AUDIOOUT_PWRDN_ADC(v) (((v) << 8) & 0x100) | ||
248 | #define BP_AUDIOOUT_PWRDN_CAPLESS 4 | ||
249 | #define BM_AUDIOOUT_PWRDN_CAPLESS 0x10 | ||
250 | #define BF_AUDIOOUT_PWRDN_CAPLESS(v) (((v) << 4) & 0x10) | ||
251 | #define BP_AUDIOOUT_PWRDN_HEADPHONE 0 | ||
252 | #define BM_AUDIOOUT_PWRDN_HEADPHONE 0x1 | ||
253 | #define BF_AUDIOOUT_PWRDN_HEADPHONE(v) (((v) << 0) & 0x1) | ||
254 | |||
255 | /** | ||
256 | * Register: HW_AUDIOOUT_REFCTRL | ||
257 | * Address: 0x80 | ||
258 | * SCT: yes | ||
259 | */ | ||
260 | #define HW_AUDIOOUT_REFCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0)) | ||
261 | #define HW_AUDIOOUT_REFCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4)) | ||
262 | #define HW_AUDIOOUT_REFCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8)) | ||
263 | #define HW_AUDIOOUT_REFCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc)) | ||
264 | #define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 24 | ||
265 | #define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x1000000 | ||
266 | #define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v) (((v) << 24) & 0x1000000) | ||
267 | #define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 | ||
268 | #define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x700000 | ||
269 | #define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) (((v) << 20) & 0x700000) | ||
270 | #define BP_AUDIOOUT_REFCTRL_LOW_PWR 19 | ||
271 | #define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x80000 | ||
272 | #define BF_AUDIOOUT_REFCTRL_LOW_PWR(v) (((v) << 19) & 0x80000) | ||
273 | #define BP_AUDIOOUT_REFCTRL_LW_REF 18 | ||
274 | #define BM_AUDIOOUT_REFCTRL_LW_REF 0x40000 | ||
275 | #define BF_AUDIOOUT_REFCTRL_LW_REF(v) (((v) << 18) & 0x40000) | ||
276 | #define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 | ||
277 | #define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x30000 | ||
278 | #define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) (((v) << 16) & 0x30000) | ||
279 | #define BP_AUDIOOUT_REFCTRL_ADJ_ADC 13 | ||
280 | #define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x2000 | ||
281 | #define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v) (((v) << 13) & 0x2000) | ||
282 | #define BP_AUDIOOUT_REFCTRL_ADJ_VAG 12 | ||
283 | #define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x1000 | ||
284 | #define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v) (((v) << 12) & 0x1000) | ||
285 | #define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 | ||
286 | #define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0xf00 | ||
287 | #define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) (((v) << 8) & 0xf00) | ||
288 | #define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 | ||
289 | #define BM_AUDIOOUT_REFCTRL_VAG_VAL 0xf0 | ||
290 | #define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) (((v) << 4) & 0xf0) | ||
291 | #define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 | ||
292 | #define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x7 | ||
293 | #define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) (((v) << 0) & 0x7) | ||
294 | |||
295 | /** | ||
296 | * Register: HW_AUDIOOUT_ANACTRL | ||
297 | * Address: 0x90 | ||
298 | * SCT: yes | ||
299 | */ | ||
300 | #define HW_AUDIOOUT_ANACTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0)) | ||
301 | #define HW_AUDIOOUT_ANACTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4)) | ||
302 | #define HW_AUDIOOUT_ANACTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8)) | ||
303 | #define HW_AUDIOOUT_ANACTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc)) | ||
304 | #define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS 28 | ||
305 | #define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 | ||
306 | #define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v) (((v) << 28) & 0x10000000) | ||
307 | #define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS 24 | ||
308 | #define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x1000000 | ||
309 | #define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v) (((v) << 24) & 0x1000000) | ||
310 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 | ||
311 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x300000 | ||
312 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) (((v) << 20) & 0x300000) | ||
313 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 | ||
314 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x60000 | ||
315 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) (((v) << 17) & 0x60000) | ||
316 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 | ||
317 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x7000 | ||
318 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) (((v) << 12) & 0x7000) | ||
319 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 | ||
320 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x700 | ||
321 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) (((v) << 8) & 0x700) | ||
322 | #define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND 5 | ||
323 | #define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x20 | ||
324 | #define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v) (((v) << 5) & 0x20) | ||
325 | #define BP_AUDIOOUT_ANACTRL_HP_CLASSAB 4 | ||
326 | #define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x10 | ||
327 | #define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v) (((v) << 4) & 0x10) | ||
328 | #define BP_AUDIOOUT_ANACTRL_EN_SPKR_ZCD 2 | ||
329 | #define BM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD 0x4 | ||
330 | #define BF_AUDIOOUT_ANACTRL_EN_SPKR_ZCD(v) (((v) << 2) & 0x4) | ||
331 | #define BP_AUDIOOUT_ANACTRL_ZCD_SELECTADC 1 | ||
332 | #define BM_AUDIOOUT_ANACTRL_ZCD_SELECTADC 0x2 | ||
333 | #define BF_AUDIOOUT_ANACTRL_ZCD_SELECTADC(v) (((v) << 1) & 0x2) | ||
334 | #define BP_AUDIOOUT_ANACTRL_EN_ZCD 0 | ||
335 | #define BM_AUDIOOUT_ANACTRL_EN_ZCD 0x1 | ||
336 | #define BF_AUDIOOUT_ANACTRL_EN_ZCD(v) (((v) << 0) & 0x1) | ||
337 | |||
338 | /** | ||
339 | * Register: HW_AUDIOOUT_TEST | ||
340 | * Address: 0xa0 | ||
341 | * SCT: yes | ||
342 | */ | ||
343 | #define HW_AUDIOOUT_TEST (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0)) | ||
344 | #define HW_AUDIOOUT_TEST_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4)) | ||
345 | #define HW_AUDIOOUT_TEST_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8)) | ||
346 | #define HW_AUDIOOUT_TEST_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc)) | ||
347 | #define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 | ||
348 | #define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 | ||
349 | #define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) (((v) << 28) & 0x70000000) | ||
350 | #define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP 26 | ||
351 | #define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x4000000 | ||
352 | #define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v) (((v) << 26) & 0x4000000) | ||
353 | #define BP_AUDIOOUT_TEST_TM_SPEAKER 25 | ||
354 | #define BM_AUDIOOUT_TEST_TM_SPEAKER 0x2000000 | ||
355 | #define BF_AUDIOOUT_TEST_TM_SPEAKER(v) (((v) << 25) & 0x2000000) | ||
356 | #define BP_AUDIOOUT_TEST_TM_HPCOMMON 24 | ||
357 | #define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x1000000 | ||
358 | #define BF_AUDIOOUT_TEST_TM_HPCOMMON(v) (((v) << 24) & 0x1000000) | ||
359 | #define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 | ||
360 | #define BM_AUDIOOUT_TEST_HP_I1_ADJ 0xc00000 | ||
361 | #define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) (((v) << 22) & 0xc00000) | ||
362 | #define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 | ||
363 | #define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x300000 | ||
364 | #define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) (((v) << 20) & 0x300000) | ||
365 | #define BP_AUDIOOUT_TEST_SPKR_I1_ADJ 18 | ||
366 | #define BM_AUDIOOUT_TEST_SPKR_I1_ADJ 0xc0000 | ||
367 | #define BF_AUDIOOUT_TEST_SPKR_I1_ADJ(v) (((v) << 18) & 0xc0000) | ||
368 | #define BP_AUDIOOUT_TEST_SPKR_IALL_ADJ 16 | ||
369 | #define BM_AUDIOOUT_TEST_SPKR_IALL_ADJ 0x30000 | ||
370 | #define BF_AUDIOOUT_TEST_SPKR_IALL_ADJ(v) (((v) << 16) & 0x30000) | ||
371 | #define BP_AUDIOOUT_TEST_VAG_CLASSA 13 | ||
372 | #define BM_AUDIOOUT_TEST_VAG_CLASSA 0x2000 | ||
373 | #define BF_AUDIOOUT_TEST_VAG_CLASSA(v) (((v) << 13) & 0x2000) | ||
374 | #define BP_AUDIOOUT_TEST_VAG_DOUBLE_I 12 | ||
375 | #define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x1000 | ||
376 | #define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v) (((v) << 12) & 0x1000) | ||
377 | #define BP_AUDIOOUT_TEST_HP_CHOPCLK 8 | ||
378 | #define BM_AUDIOOUT_TEST_HP_CHOPCLK 0x300 | ||
379 | #define BF_AUDIOOUT_TEST_HP_CHOPCLK(v) (((v) << 8) & 0x300) | ||
380 | #define BP_AUDIOOUT_TEST_DAC_CHOPCLK 4 | ||
381 | #define BM_AUDIOOUT_TEST_DAC_CHOPCLK 0x30 | ||
382 | #define BF_AUDIOOUT_TEST_DAC_CHOPCLK(v) (((v) << 4) & 0x30) | ||
383 | #define BP_AUDIOOUT_TEST_DAC_CLASSA 2 | ||
384 | #define BM_AUDIOOUT_TEST_DAC_CLASSA 0x4 | ||
385 | #define BF_AUDIOOUT_TEST_DAC_CLASSA(v) (((v) << 2) & 0x4) | ||
386 | #define BP_AUDIOOUT_TEST_DAC_DOUBLE_I 1 | ||
387 | #define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x2 | ||
388 | #define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v) (((v) << 1) & 0x2) | ||
389 | #define BP_AUDIOOUT_TEST_DAC_DIS_RTZ 0 | ||
390 | #define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x1 | ||
391 | #define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v) (((v) << 0) & 0x1) | ||
392 | |||
393 | /** | ||
394 | * Register: HW_AUDIOOUT_BISTCTRL | ||
395 | * Address: 0xb0 | ||
396 | * SCT: yes | ||
397 | */ | ||
398 | #define HW_AUDIOOUT_BISTCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0)) | ||
399 | #define HW_AUDIOOUT_BISTCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4)) | ||
400 | #define HW_AUDIOOUT_BISTCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8)) | ||
401 | #define HW_AUDIOOUT_BISTCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc)) | ||
402 | #define BP_AUDIOOUT_BISTCTRL_FAIL 3 | ||
403 | #define BM_AUDIOOUT_BISTCTRL_FAIL 0x8 | ||
404 | #define BF_AUDIOOUT_BISTCTRL_FAIL(v) (((v) << 3) & 0x8) | ||
405 | #define BP_AUDIOOUT_BISTCTRL_PASS 2 | ||
406 | #define BM_AUDIOOUT_BISTCTRL_PASS 0x4 | ||
407 | #define BF_AUDIOOUT_BISTCTRL_PASS(v) (((v) << 2) & 0x4) | ||
408 | #define BP_AUDIOOUT_BISTCTRL_DONE 1 | ||
409 | #define BM_AUDIOOUT_BISTCTRL_DONE 0x2 | ||
410 | #define BF_AUDIOOUT_BISTCTRL_DONE(v) (((v) << 1) & 0x2) | ||
411 | #define BP_AUDIOOUT_BISTCTRL_START 0 | ||
412 | #define BM_AUDIOOUT_BISTCTRL_START 0x1 | ||
413 | #define BF_AUDIOOUT_BISTCTRL_START(v) (((v) << 0) & 0x1) | ||
414 | |||
415 | /** | ||
416 | * Register: HW_AUDIOOUT_BISTSTAT0 | ||
417 | * Address: 0xc0 | ||
418 | * SCT: no | ||
419 | */ | ||
420 | #define HW_AUDIOOUT_BISTSTAT0 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0)) | ||
421 | #define BP_AUDIOOUT_BISTSTAT0_DATA 0 | ||
422 | #define BM_AUDIOOUT_BISTSTAT0_DATA 0xffffff | ||
423 | #define BF_AUDIOOUT_BISTSTAT0_DATA(v) (((v) << 0) & 0xffffff) | ||
424 | |||
425 | /** | ||
426 | * Register: HW_AUDIOOUT_BISTSTAT1 | ||
427 | * Address: 0xd0 | ||
428 | * SCT: no | ||
429 | */ | ||
430 | #define HW_AUDIOOUT_BISTSTAT1 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0)) | ||
431 | #define BP_AUDIOOUT_BISTSTAT1_STATE 24 | ||
432 | #define BM_AUDIOOUT_BISTSTAT1_STATE 0x1f000000 | ||
433 | #define BF_AUDIOOUT_BISTSTAT1_STATE(v) (((v) << 24) & 0x1f000000) | ||
434 | #define BP_AUDIOOUT_BISTSTAT1_ADDR 0 | ||
435 | #define BM_AUDIOOUT_BISTSTAT1_ADDR 0xff | ||
436 | #define BF_AUDIOOUT_BISTSTAT1_ADDR(v) (((v) << 0) & 0xff) | ||
437 | |||
438 | /** | ||
439 | * Register: HW_AUDIOOUT_ANACLKCTRL | ||
440 | * Address: 0xe0 | ||
441 | * SCT: yes | ||
442 | */ | ||
443 | #define HW_AUDIOOUT_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0)) | ||
444 | #define HW_AUDIOOUT_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4)) | ||
445 | #define HW_AUDIOOUT_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8)) | ||
446 | #define HW_AUDIOOUT_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc)) | ||
447 | #define BP_AUDIOOUT_ANACLKCTRL_CLKGATE 31 | ||
448 | #define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 | ||
449 | #define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
450 | #define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 4 | ||
451 | #define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x10 | ||
452 | #define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10) | ||
453 | #define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 | ||
454 | #define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x7 | ||
455 | #define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) (((v) << 0) & 0x7) | ||
456 | |||
457 | /** | ||
458 | * Register: HW_AUDIOOUT_DATA | ||
459 | * Address: 0xf0 | ||
460 | * SCT: yes | ||
461 | */ | ||
462 | #define HW_AUDIOOUT_DATA (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0)) | ||
463 | #define HW_AUDIOOUT_DATA_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4)) | ||
464 | #define HW_AUDIOOUT_DATA_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8)) | ||
465 | #define HW_AUDIOOUT_DATA_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc)) | ||
466 | #define BP_AUDIOOUT_DATA_HIGH 16 | ||
467 | #define BM_AUDIOOUT_DATA_HIGH 0xffff0000 | ||
468 | #define BF_AUDIOOUT_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
469 | #define BP_AUDIOOUT_DATA_LOW 0 | ||
470 | #define BM_AUDIOOUT_DATA_LOW 0xffff | ||
471 | #define BF_AUDIOOUT_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
472 | |||
473 | #endif /* __HEADERGEN__STMP3600__AUDIOOUT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h b/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h new file mode 100644 index 0000000000..903cf09878 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__BRAZOIOCSR__H__ | ||
24 | #define __HEADERGEN__STMP3600__BRAZOIOCSR__H__ | ||
25 | |||
26 | #define REGS_BRAZOIOCSR_BASE (0x80038000) | ||
27 | |||
28 | #define REGS_BRAZOIOCSR_VERSION "2.3.0" | ||
29 | |||
30 | #endif /* __HEADERGEN__STMP3600__BRAZOIOCSR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h new file mode 100644 index 0000000000..218298b69d --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h | |||
@@ -0,0 +1,344 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__CLKCTRL__H__ | ||
24 | #define __HEADERGEN__STMP3600__CLKCTRL__H__ | ||
25 | |||
26 | #define REGS_CLKCTRL_BASE (0x80040000) | ||
27 | |||
28 | #define REGS_CLKCTRL_VERSION "2.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_CLKCTRL_PLLCTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_CLKCTRL_PLLCTRL0_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_CLKCTRL_PLLCTRL0_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_CLKCTRL_PLLCTRL0_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_CLKCTRL_PLLCTRL0_PLLVCOKSTART 30 | ||
40 | #define BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART 0x40000000 | ||
41 | #define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v) (((v) << 30) & 0x40000000) | ||
42 | #define BP_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 29 | ||
43 | #define BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 0x20000000 | ||
44 | #define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v) (((v) << 29) & 0x20000000) | ||
45 | #define BP_CLKCTRL_PLLCTRL0_PLLCPDBLIP 28 | ||
46 | #define BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP 0x10000000 | ||
47 | #define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v) (((v) << 28) & 0x10000000) | ||
48 | #define BP_CLKCTRL_PLLCTRL0_PLLCPNSEL 24 | ||
49 | #define BM_CLKCTRL_PLLCTRL0_PLLCPNSEL 0x7000000 | ||
50 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__DEFAULT 0x0 | ||
51 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_15 0x2 | ||
52 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_075 0x3 | ||
53 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_05 0x4 | ||
54 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_04 0x7 | ||
55 | #define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(v) (((v) << 24) & 0x7000000) | ||
56 | #define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(v) ((BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__##v << 24) & 0x7000000) | ||
57 | #define BP_CLKCTRL_PLLCTRL0_PLLV2ISEL 20 | ||
58 | #define BM_CLKCTRL_PLLCTRL0_PLLV2ISEL 0x300000 | ||
59 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__NORMAL 0x0 | ||
60 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWER 0x1 | ||
61 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWEST 0x2 | ||
62 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__HIGHEST 0x3 | ||
63 | #define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(v) (((v) << 20) & 0x300000) | ||
64 | #define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(v) ((BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__##v << 20) & 0x300000) | ||
65 | #define BP_CLKCTRL_PLLCTRL0_FORCE_FREQ 19 | ||
66 | #define BM_CLKCTRL_PLLCTRL0_FORCE_FREQ 0x80000 | ||
67 | #define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__FORCE_SAME_FREQ 0x1 | ||
68 | #define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__HONOR_SAME_FREQ_RULE 0x0 | ||
69 | #define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(v) (((v) << 19) & 0x80000) | ||
70 | #define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(v) ((BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__##v << 19) & 0x80000) | ||
71 | #define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 | ||
72 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 | ||
73 | #define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) << 18) & 0x40000) | ||
74 | #define BP_CLKCTRL_PLLCTRL0_BYPASS 17 | ||
75 | #define BM_CLKCTRL_PLLCTRL0_BYPASS 0x20000 | ||
76 | #define BF_CLKCTRL_PLLCTRL0_BYPASS(v) (((v) << 17) & 0x20000) | ||
77 | #define BP_CLKCTRL_PLLCTRL0_POWER 16 | ||
78 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 | ||
79 | #define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) << 16) & 0x10000) | ||
80 | #define BP_CLKCTRL_PLLCTRL0_FREQ 0 | ||
81 | #define BM_CLKCTRL_PLLCTRL0_FREQ 0x1ff | ||
82 | #define BF_CLKCTRL_PLLCTRL0_FREQ(v) (((v) << 0) & 0x1ff) | ||
83 | |||
84 | /** | ||
85 | * Register: HW_CLKCTRL_PLLCTRL1 | ||
86 | * Address: 0x10 | ||
87 | * SCT: yes | ||
88 | */ | ||
89 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x0)) | ||
90 | #define HW_CLKCTRL_PLLCTRL1_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x4)) | ||
91 | #define HW_CLKCTRL_PLLCTRL1_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x8)) | ||
92 | #define HW_CLKCTRL_PLLCTRL1_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0xc)) | ||
93 | #define BP_CLKCTRL_PLLCTRL1_LOCK 31 | ||
94 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
95 | #define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) << 31) & 0x80000000) | ||
96 | #define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 | ||
97 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
98 | #define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) << 30) & 0x40000000) | ||
99 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
100 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff | ||
101 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) << 0) & 0xffff) | ||
102 | |||
103 | /** | ||
104 | * Register: HW_CLKCTRL_CPU | ||
105 | * Address: 0x20 | ||
106 | * SCT: no | ||
107 | */ | ||
108 | #define HW_CLKCTRL_CPU (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20)) | ||
109 | #define BP_CLKCTRL_CPU_WAIT_PLL_LOCK 30 | ||
110 | #define BM_CLKCTRL_CPU_WAIT_PLL_LOCK 0x40000000 | ||
111 | #define BF_CLKCTRL_CPU_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
112 | #define BP_CLKCTRL_CPU_BUSY 29 | ||
113 | #define BM_CLKCTRL_CPU_BUSY 0x20000000 | ||
114 | #define BF_CLKCTRL_CPU_BUSY(v) (((v) << 29) & 0x20000000) | ||
115 | #define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 | ||
116 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 | ||
117 | #define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) << 12) & 0x1000) | ||
118 | #define BP_CLKCTRL_CPU_DIV 0 | ||
119 | #define BM_CLKCTRL_CPU_DIV 0x3ff | ||
120 | #define BF_CLKCTRL_CPU_DIV(v) (((v) << 0) & 0x3ff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_CLKCTRL_HBUS | ||
124 | * Address: 0x30 | ||
125 | * SCT: no | ||
126 | */ | ||
127 | #define HW_CLKCTRL_HBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30)) | ||
128 | #define BP_CLKCTRL_HBUS_WAIT_PLL_LOCK 30 | ||
129 | #define BM_CLKCTRL_HBUS_WAIT_PLL_LOCK 0x40000000 | ||
130 | #define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
131 | #define BP_CLKCTRL_HBUS_BUSY 29 | ||
132 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
133 | #define BF_CLKCTRL_HBUS_BUSY(v) (((v) << 29) & 0x20000000) | ||
134 | #define BP_CLKCTRL_HBUS_EMI_BUSY_FAST 27 | ||
135 | #define BM_CLKCTRL_HBUS_EMI_BUSY_FAST 0x8000000 | ||
136 | #define BF_CLKCTRL_HBUS_EMI_BUSY_FAST(v) (((v) << 27) & 0x8000000) | ||
137 | #define BP_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 26 | ||
138 | #define BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 0x4000000 | ||
139 | #define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v) (((v) << 26) & 0x4000000) | ||
140 | #define BP_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 25 | ||
141 | #define BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 0x2000000 | ||
142 | #define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v) (((v) << 25) & 0x2000000) | ||
143 | #define BP_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 24 | ||
144 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 0x1000000 | ||
145 | #define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v) (((v) << 24) & 0x1000000) | ||
146 | #define BP_CLKCTRL_HBUS_TRAFFIC_FAST 23 | ||
147 | #define BM_CLKCTRL_HBUS_TRAFFIC_FAST 0x800000 | ||
148 | #define BF_CLKCTRL_HBUS_TRAFFIC_FAST(v) (((v) << 23) & 0x800000) | ||
149 | #define BP_CLKCTRL_HBUS_CPU_DATA_FAST 22 | ||
150 | #define BM_CLKCTRL_HBUS_CPU_DATA_FAST 0x400000 | ||
151 | #define BF_CLKCTRL_HBUS_CPU_DATA_FAST(v) (((v) << 22) & 0x400000) | ||
152 | #define BP_CLKCTRL_HBUS_CPU_INSTR_FAST 21 | ||
153 | #define BM_CLKCTRL_HBUS_CPU_INSTR_FAST 0x200000 | ||
154 | #define BF_CLKCTRL_HBUS_CPU_INSTR_FAST(v) (((v) << 21) & 0x200000) | ||
155 | #define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 | ||
156 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 | ||
157 | #define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) << 20) & 0x100000) | ||
158 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
159 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x30000 | ||
160 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
161 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
162 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
163 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
164 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) << 16) & 0x30000) | ||
165 | #define BF_CLKCTRL_HBUS_SLOW_DIV_V(v) ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x30000) | ||
166 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
167 | #define BM_CLKCTRL_HBUS_DIV 0x1f | ||
168 | #define BF_CLKCTRL_HBUS_DIV(v) (((v) << 0) & 0x1f) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_CLKCTRL_XBUS | ||
172 | * Address: 0x40 | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_CLKCTRL_XBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40)) | ||
176 | #define BP_CLKCTRL_XBUS_BUSY 31 | ||
177 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
178 | #define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000) | ||
179 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
180 | #define BM_CLKCTRL_XBUS_DIV 0x3ff | ||
181 | #define BF_CLKCTRL_XBUS_DIV(v) (((v) << 0) & 0x3ff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_CLKCTRL_XTAL | ||
185 | * Address: 0x50 | ||
186 | * SCT: no | ||
187 | */ | ||
188 | #define HW_CLKCTRL_XTAL (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50)) | ||
189 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
190 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
191 | #define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) << 31) & 0x80000000) | ||
192 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
193 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
194 | #define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) << 30) & 0x40000000) | ||
195 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
196 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
197 | #define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) << 29) & 0x20000000) | ||
198 | #define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 | ||
199 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
200 | #define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) << 28) & 0x10000000) | ||
201 | #define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 | ||
202 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 | ||
203 | #define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) << 27) & 0x8000000) | ||
204 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
205 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 | ||
206 | #define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) << 26) & 0x4000000) | ||
207 | #define BP_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 25 | ||
208 | #define BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 0x2000000 | ||
209 | #define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v) (((v) << 25) & 0x2000000) | ||
210 | #define BP_CLKCTRL_XTAL_LRADC_CLK2K_GATE 24 | ||
211 | #define BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE 0x1000000 | ||
212 | #define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v) (((v) << 24) & 0x1000000) | ||
213 | |||
214 | /** | ||
215 | * Register: HW_CLKCTRL_OCRAM | ||
216 | * Address: 0x60 | ||
217 | * SCT: no | ||
218 | */ | ||
219 | #define HW_CLKCTRL_OCRAM (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60)) | ||
220 | #define BP_CLKCTRL_OCRAM_CLKGATE 31 | ||
221 | #define BM_CLKCTRL_OCRAM_CLKGATE 0x80000000 | ||
222 | #define BF_CLKCTRL_OCRAM_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
223 | #define BP_CLKCTRL_OCRAM_BUSY 30 | ||
224 | #define BM_CLKCTRL_OCRAM_BUSY 0x40000000 | ||
225 | #define BF_CLKCTRL_OCRAM_BUSY(v) (((v) << 30) & 0x40000000) | ||
226 | #define BP_CLKCTRL_OCRAM_DIV 0 | ||
227 | #define BM_CLKCTRL_OCRAM_DIV 0x3ff | ||
228 | #define BF_CLKCTRL_OCRAM_DIV(v) (((v) << 0) & 0x3ff) | ||
229 | |||
230 | /** | ||
231 | * Register: HW_CLKCTRL_UTMI | ||
232 | * Address: 0x70 | ||
233 | * SCT: no | ||
234 | */ | ||
235 | #define HW_CLKCTRL_UTMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70)) | ||
236 | #define BP_CLKCTRL_UTMI_UTMI_CLK120M_GATE 31 | ||
237 | #define BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE 0x80000000 | ||
238 | #define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v) (((v) << 31) & 0x80000000) | ||
239 | #define BP_CLKCTRL_UTMI_UTMI_CLK30M_GATE 30 | ||
240 | #define BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE 0x40000000 | ||
241 | #define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v) (((v) << 30) & 0x40000000) | ||
242 | |||
243 | /** | ||
244 | * Register: HW_CLKCTRL_SSP | ||
245 | * Address: 0x80 | ||
246 | * SCT: no | ||
247 | */ | ||
248 | #define HW_CLKCTRL_SSP (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80)) | ||
249 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
250 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
251 | #define BF_CLKCTRL_SSP_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
252 | #define BP_CLKCTRL_SSP_WAIT_PLL_LOCK 30 | ||
253 | #define BM_CLKCTRL_SSP_WAIT_PLL_LOCK 0x40000000 | ||
254 | #define BF_CLKCTRL_SSP_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
255 | #define BP_CLKCTRL_SSP_BUSY 29 | ||
256 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
257 | #define BF_CLKCTRL_SSP_BUSY(v) (((v) << 29) & 0x20000000) | ||
258 | #define BP_CLKCTRL_SSP_DIV 0 | ||
259 | #define BM_CLKCTRL_SSP_DIV 0x1ff | ||
260 | #define BF_CLKCTRL_SSP_DIV(v) (((v) << 0) & 0x1ff) | ||
261 | |||
262 | /** | ||
263 | * Register: HW_CLKCTRL_GPMI | ||
264 | * Address: 0x90 | ||
265 | * SCT: no | ||
266 | */ | ||
267 | #define HW_CLKCTRL_GPMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90)) | ||
268 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
269 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
270 | #define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
271 | #define BP_CLKCTRL_GPMI_WAIT_PLL_LOCK 30 | ||
272 | #define BM_CLKCTRL_GPMI_WAIT_PLL_LOCK 0x40000000 | ||
273 | #define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
274 | #define BP_CLKCTRL_GPMI_BUSY 29 | ||
275 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
276 | #define BF_CLKCTRL_GPMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
277 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
278 | #define BM_CLKCTRL_GPMI_DIV 0x3ff | ||
279 | #define BF_CLKCTRL_GPMI_DIV(v) (((v) << 0) & 0x3ff) | ||
280 | |||
281 | /** | ||
282 | * Register: HW_CLKCTRL_SPDIF | ||
283 | * Address: 0xa0 | ||
284 | * SCT: no | ||
285 | */ | ||
286 | #define HW_CLKCTRL_SPDIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0)) | ||
287 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
288 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
289 | #define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
290 | #define BP_CLKCTRL_SPDIF_BUSY 30 | ||
291 | #define BM_CLKCTRL_SPDIF_BUSY 0x40000000 | ||
292 | #define BF_CLKCTRL_SPDIF_BUSY(v) (((v) << 30) & 0x40000000) | ||
293 | #define BP_CLKCTRL_SPDIF_DIV 0 | ||
294 | #define BM_CLKCTRL_SPDIF_DIV 0x7 | ||
295 | #define BF_CLKCTRL_SPDIF_DIV(v) (((v) << 0) & 0x7) | ||
296 | |||
297 | /** | ||
298 | * Register: HW_CLKCTRL_EMI | ||
299 | * Address: 0xb0 | ||
300 | * SCT: no | ||
301 | */ | ||
302 | #define HW_CLKCTRL_EMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0)) | ||
303 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
304 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
305 | #define BF_CLKCTRL_EMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
306 | #define BP_CLKCTRL_EMI_WAIT_PLL_LOCK 30 | ||
307 | #define BM_CLKCTRL_EMI_WAIT_PLL_LOCK 0x40000000 | ||
308 | #define BF_CLKCTRL_EMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
309 | #define BP_CLKCTRL_EMI_BUSY 29 | ||
310 | #define BM_CLKCTRL_EMI_BUSY 0x20000000 | ||
311 | #define BF_CLKCTRL_EMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
312 | #define BP_CLKCTRL_EMI_DIV 0 | ||
313 | #define BM_CLKCTRL_EMI_DIV 0x7 | ||
314 | #define BF_CLKCTRL_EMI_DIV(v) (((v) << 0) & 0x7) | ||
315 | |||
316 | /** | ||
317 | * Register: HW_CLKCTRL_IR | ||
318 | * Address: 0xc0 | ||
319 | * SCT: no | ||
320 | */ | ||
321 | #define HW_CLKCTRL_IR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0)) | ||
322 | #define BP_CLKCTRL_IR_CLKGATE 31 | ||
323 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
324 | #define BF_CLKCTRL_IR_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
325 | #define BP_CLKCTRL_IR_WAIT_PLL_LOCK 30 | ||
326 | #define BM_CLKCTRL_IR_WAIT_PLL_LOCK 0x40000000 | ||
327 | #define BF_CLKCTRL_IR_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
328 | #define BP_CLKCTRL_IR_AUTO_DIV 29 | ||
329 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
330 | #define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) << 29) & 0x20000000) | ||
331 | #define BP_CLKCTRL_IR_IR_BUSY 28 | ||
332 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
333 | #define BF_CLKCTRL_IR_IR_BUSY(v) (((v) << 28) & 0x10000000) | ||
334 | #define BP_CLKCTRL_IR_IROV_BUSY 27 | ||
335 | #define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 | ||
336 | #define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) << 27) & 0x8000000) | ||
337 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
338 | #define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 | ||
339 | #define BF_CLKCTRL_IR_IROV_DIV(v) (((v) << 16) & 0x1ff0000) | ||
340 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
341 | #define BM_CLKCTRL_IR_IR_DIV 0x3ff | ||
342 | #define BF_CLKCTRL_IR_IR_DIV(v) (((v) << 0) & 0x3ff) | ||
343 | |||
344 | #endif /* __HEADERGEN__STMP3600__CLKCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h new file mode 100644 index 0000000000..5d2fe44fb1 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__DACDMA__H__ | ||
24 | #define __HEADERGEN__STMP3600__DACDMA__H__ | ||
25 | |||
26 | #define REGS_DACDMA_BASE (0x8004c000) | ||
27 | |||
28 | #define REGS_DACDMA_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DACDMA_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DACDMA_CTRL (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DACDMA_CTRL_SET (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DACDMA_CTRL_CLR (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DACDMA_CTRL_TOG (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DACDMA_CTRL_SFTRST 31 | ||
40 | #define BM_DACDMA_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_DACDMA_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_DACDMA_CTRL_CLKGATE 30 | ||
43 | #define BM_DACDMA_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_DACDMA_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_DACDMA_CTRL_RUN 0 | ||
46 | #define BM_DACDMA_CTRL_RUN 0x1 | ||
47 | #define BF_DACDMA_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
48 | |||
49 | /** | ||
50 | * Register: HW_DACDMA_DATA | ||
51 | * Address: 0x80 | ||
52 | * SCT: no | ||
53 | */ | ||
54 | #define HW_DACDMA_DATA (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x80)) | ||
55 | #define BP_DACDMA_DATA_HIGH 16 | ||
56 | #define BM_DACDMA_DATA_HIGH 0xffff0000 | ||
57 | #define BF_DACDMA_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
58 | #define BP_DACDMA_DATA_LOW 0 | ||
59 | #define BM_DACDMA_DATA_LOW 0xffff | ||
60 | #define BF_DACDMA_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
61 | |||
62 | #endif /* __HEADERGEN__STMP3600__DACDMA__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h new file mode 100644 index 0000000000..a7b45a7ca9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h | |||
@@ -0,0 +1,595 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__DIGCTL__H__ | ||
24 | #define __HEADERGEN__STMP3600__DIGCTL__H__ | ||
25 | |||
26 | #define REGS_DIGCTL_BASE (0x8001c000) | ||
27 | |||
28 | #define REGS_DIGCTL_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DIGCTL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DIGCTL_CTRL_MASTER_SELECT 24 | ||
40 | #define BM_DIGCTL_CTRL_MASTER_SELECT 0x1f000000 | ||
41 | #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I 0x1 | ||
42 | #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D 0x2 | ||
43 | #define BV_DIGCTL_CTRL_MASTER_SELECT__USB 0x4 | ||
44 | #define BV_DIGCTL_CTRL_MASTER_SELECT__APBH 0x8 | ||
45 | #define BV_DIGCTL_CTRL_MASTER_SELECT__APBX 0x10 | ||
46 | #define BF_DIGCTL_CTRL_MASTER_SELECT(v) (((v) << 24) & 0x1f000000) | ||
47 | #define BF_DIGCTL_CTRL_MASTER_SELECT_V(v) ((BV_DIGCTL_CTRL_MASTER_SELECT__##v << 24) & 0x1f000000) | ||
48 | #define BP_DIGCTL_CTRL_USB_TESTMODE 20 | ||
49 | #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 | ||
50 | #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) | ||
51 | #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 | ||
52 | #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 | ||
53 | #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) | ||
54 | #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 | ||
55 | #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 | ||
56 | #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) | ||
57 | #define BP_DIGCTL_CTRL_UTMI_TESTMODE 17 | ||
58 | #define BM_DIGCTL_CTRL_UTMI_TESTMODE 0x20000 | ||
59 | #define BF_DIGCTL_CTRL_UTMI_TESTMODE(v) (((v) << 17) & 0x20000) | ||
60 | #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 | ||
61 | #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 | ||
62 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 | ||
63 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 | ||
64 | #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) | ||
65 | #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) | ||
66 | #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 | ||
67 | #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 | ||
68 | #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) | ||
69 | #define BP_DIGCTL_CTRL_USB_CLKGATE 2 | ||
70 | #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 | ||
71 | #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 | ||
72 | #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 | ||
73 | #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) | ||
74 | #define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) | ||
75 | #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 | ||
76 | #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 | ||
77 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 | ||
78 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 | ||
79 | #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) | ||
80 | #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) | ||
81 | #define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0 | ||
82 | #define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0x1 | ||
83 | #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE 0x0 | ||
84 | #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE 0x1 | ||
85 | #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) (((v) << 0) & 0x1) | ||
86 | #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v) ((BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##v << 0) & 0x1) | ||
87 | |||
88 | /** | ||
89 | * Register: HW_DIGCTL_STATUS | ||
90 | * Address: 0x10 | ||
91 | * SCT: no | ||
92 | */ | ||
93 | #define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10)) | ||
94 | #define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT 31 | ||
95 | #define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT 0x80000000 | ||
96 | #define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
97 | #define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 6 | ||
98 | #define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 0x40 | ||
99 | #define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) << 6) & 0x40) | ||
100 | #define BP_DIGCTL_STATUS_ROM_SHIELDED 5 | ||
101 | #define BM_DIGCTL_STATUS_ROM_SHIELDED 0x20 | ||
102 | #define BF_DIGCTL_STATUS_ROM_SHIELDED(v) (((v) << 5) & 0x20) | ||
103 | #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 | ||
104 | #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 | ||
105 | #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) | ||
106 | #define BP_DIGCTL_STATUS_PSWITCH 2 | ||
107 | #define BM_DIGCTL_STATUS_PSWITCH 0xc | ||
108 | #define BF_DIGCTL_STATUS_PSWITCH(v) (((v) << 2) & 0xc) | ||
109 | #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 | ||
110 | #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x2 | ||
111 | #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0x2) | ||
112 | #define BP_DIGCTL_STATUS_WRITTEN 0 | ||
113 | #define BM_DIGCTL_STATUS_WRITTEN 0x1 | ||
114 | #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) | ||
115 | |||
116 | /** | ||
117 | * Register: HW_DIGCTL_HCLKCOUNT | ||
118 | * Address: 0x20 | ||
119 | * SCT: no | ||
120 | */ | ||
121 | #define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20)) | ||
122 | #define BP_DIGCTL_HCLKCOUNT_COUNT 0 | ||
123 | #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff | ||
124 | #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) | ||
125 | |||
126 | /** | ||
127 | * Register: HW_DIGCTL_RAMCTRL | ||
128 | * Address: 0x30 | ||
129 | * SCT: yes | ||
130 | */ | ||
131 | #define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) | ||
132 | #define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) | ||
133 | #define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) | ||
134 | #define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) | ||
135 | #define BP_DIGCTL_RAMCTRL_TEST_MARGIN 28 | ||
136 | #define BM_DIGCTL_RAMCTRL_TEST_MARGIN 0x70000000 | ||
137 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL 0x0 | ||
138 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1 0x1 | ||
139 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2 0x2 | ||
140 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3 0x3 | ||
141 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4 0x4 | ||
142 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5 0x5 | ||
143 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6 0x6 | ||
144 | #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7 0x7 | ||
145 | #define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v) (((v) << 28) & 0x70000000) | ||
146 | #define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(v) ((BV_DIGCTL_RAMCTRL_TEST_MARGIN__##v << 28) & 0x70000000) | ||
147 | #define BP_DIGCTL_RAMCTRL_PWDN_BANKS 24 | ||
148 | #define BM_DIGCTL_RAMCTRL_PWDN_BANKS 0xf000000 | ||
149 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3 0x8 | ||
150 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2 0x4 | ||
151 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1 0x2 | ||
152 | #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0 0x1 | ||
153 | #define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v) (((v) << 24) & 0xf000000) | ||
154 | #define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(v) ((BV_DIGCTL_RAMCTRL_PWDN_BANKS__##v << 24) & 0xf000000) | ||
155 | #define BP_DIGCTL_RAMCTRL_TEMP_SENSOR 20 | ||
156 | #define BM_DIGCTL_RAMCTRL_TEMP_SENSOR 0x700000 | ||
157 | #define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v) (((v) << 20) & 0x700000) | ||
158 | #define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP 16 | ||
159 | #define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP 0x70000 | ||
160 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP 0x1 | ||
161 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A 0x2 | ||
162 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B 0x3 | ||
163 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C 0x4 | ||
164 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D 0x5 | ||
165 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E 0x6 | ||
166 | #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F 0x7 | ||
167 | #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) (((v) << 16) & 0x70000) | ||
168 | #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v) ((BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##v << 16) & 0x70000) | ||
169 | #define BP_DIGCTL_RAMCTRL_SHIFT_COUNT 8 | ||
170 | #define BM_DIGCTL_RAMCTRL_SHIFT_COUNT 0x7f00 | ||
171 | #define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v) (((v) << 8) & 0x7f00) | ||
172 | #define BP_DIGCTL_RAMCTRL_FLIP_CLK 7 | ||
173 | #define BM_DIGCTL_RAMCTRL_FLIP_CLK 0x80 | ||
174 | #define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL 0x0 | ||
175 | #define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT 0x1 | ||
176 | #define BF_DIGCTL_RAMCTRL_FLIP_CLK(v) (((v) << 7) & 0x80) | ||
177 | #define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(v) ((BV_DIGCTL_RAMCTRL_FLIP_CLK__##v << 7) & 0x80) | ||
178 | #define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 3 | ||
179 | #define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 0x8 | ||
180 | #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL 0x0 | ||
181 | #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1 | ||
182 | #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) (((v) << 3) & 0x8) | ||
183 | #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v) ((BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##v << 3) & 0x8) | ||
184 | #define BP_DIGCTL_RAMCTRL_REF_CLK_GATE 2 | ||
185 | #define BM_DIGCTL_RAMCTRL_REF_CLK_GATE 0x4 | ||
186 | #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL 0x0 | ||
187 | #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF 0x1 | ||
188 | #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v) (((v) << 2) & 0x4) | ||
189 | #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v) ((BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##v << 2) & 0x4) | ||
190 | #define BP_DIGCTL_RAMCTRL_REPAIR_STATUS 1 | ||
191 | #define BM_DIGCTL_RAMCTRL_REPAIR_STATUS 0x2 | ||
192 | #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE 0x0 | ||
193 | #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY 0x1 | ||
194 | #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v) (((v) << 1) & 0x2) | ||
195 | #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##v << 1) & 0x2) | ||
196 | #define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0 | ||
197 | #define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0x1 | ||
198 | #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE 0x0 | ||
199 | #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND 0x1 | ||
200 | #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) (((v) << 0) & 0x1) | ||
201 | #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v) ((BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##v << 0) & 0x1) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_DIGCTL_RAMREPAIR0 | ||
205 | * Address: 0x40 | ||
206 | * SCT: yes | ||
207 | */ | ||
208 | #define HW_DIGCTL_RAMREPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) | ||
209 | #define HW_DIGCTL_RAMREPAIR0_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) | ||
210 | #define HW_DIGCTL_RAMREPAIR0_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) | ||
211 | #define HW_DIGCTL_RAMREPAIR0_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) | ||
212 | #define BP_DIGCTL_RAMREPAIR0_EFUSE3 24 | ||
213 | #define BM_DIGCTL_RAMREPAIR0_EFUSE3 0x7f000000 | ||
214 | #define BF_DIGCTL_RAMREPAIR0_EFUSE3(v) (((v) << 24) & 0x7f000000) | ||
215 | #define BP_DIGCTL_RAMREPAIR0_EFUSE2 16 | ||
216 | #define BM_DIGCTL_RAMREPAIR0_EFUSE2 0x7f0000 | ||
217 | #define BF_DIGCTL_RAMREPAIR0_EFUSE2(v) (((v) << 16) & 0x7f0000) | ||
218 | #define BP_DIGCTL_RAMREPAIR0_EFUSE1 8 | ||
219 | #define BM_DIGCTL_RAMREPAIR0_EFUSE1 0x7f00 | ||
220 | #define BF_DIGCTL_RAMREPAIR0_EFUSE1(v) (((v) << 8) & 0x7f00) | ||
221 | #define BP_DIGCTL_RAMREPAIR0_EFUSE0 0 | ||
222 | #define BM_DIGCTL_RAMREPAIR0_EFUSE0 0x7f | ||
223 | #define BF_DIGCTL_RAMREPAIR0_EFUSE0(v) (((v) << 0) & 0x7f) | ||
224 | |||
225 | /** | ||
226 | * Register: HW_DIGCTL_RAMREPAIR1 | ||
227 | * Address: 0x50 | ||
228 | * SCT: yes | ||
229 | */ | ||
230 | #define HW_DIGCTL_RAMREPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) | ||
231 | #define HW_DIGCTL_RAMREPAIR1_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) | ||
232 | #define HW_DIGCTL_RAMREPAIR1_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) | ||
233 | #define HW_DIGCTL_RAMREPAIR1_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) | ||
234 | #define BP_DIGCTL_RAMREPAIR1_EFUSE3 24 | ||
235 | #define BM_DIGCTL_RAMREPAIR1_EFUSE3 0x7f000000 | ||
236 | #define BF_DIGCTL_RAMREPAIR1_EFUSE3(v) (((v) << 24) & 0x7f000000) | ||
237 | #define BP_DIGCTL_RAMREPAIR1_EFUSE2 16 | ||
238 | #define BM_DIGCTL_RAMREPAIR1_EFUSE2 0x7f0000 | ||
239 | #define BF_DIGCTL_RAMREPAIR1_EFUSE2(v) (((v) << 16) & 0x7f0000) | ||
240 | #define BP_DIGCTL_RAMREPAIR1_EFUSE1 8 | ||
241 | #define BM_DIGCTL_RAMREPAIR1_EFUSE1 0x7f00 | ||
242 | #define BF_DIGCTL_RAMREPAIR1_EFUSE1(v) (((v) << 8) & 0x7f00) | ||
243 | #define BP_DIGCTL_RAMREPAIR1_EFUSE0 0 | ||
244 | #define BM_DIGCTL_RAMREPAIR1_EFUSE0 0x7f | ||
245 | #define BF_DIGCTL_RAMREPAIR1_EFUSE0(v) (((v) << 0) & 0x7f) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_DIGCTL_WRITEONCE | ||
249 | * Address: 0x60 | ||
250 | * SCT: no | ||
251 | */ | ||
252 | #define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) | ||
253 | #define BP_DIGCTL_WRITEONCE_BITS 0 | ||
254 | #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff | ||
255 | #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) | ||
256 | |||
257 | /** | ||
258 | * Register: HW_DIGCTL_AHBCYCLES | ||
259 | * Address: 0x70 | ||
260 | * SCT: no | ||
261 | */ | ||
262 | #define HW_DIGCTL_AHBCYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x70)) | ||
263 | #define BP_DIGCTL_AHBCYCLES_COUNT 0 | ||
264 | #define BM_DIGCTL_AHBCYCLES_COUNT 0xffffffff | ||
265 | #define BF_DIGCTL_AHBCYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
266 | |||
267 | /** | ||
268 | * Register: HW_DIGCTL_AHBSTALLED | ||
269 | * Address: 0x80 | ||
270 | * SCT: no | ||
271 | */ | ||
272 | #define HW_DIGCTL_AHBSTALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x80)) | ||
273 | #define BP_DIGCTL_AHBSTALLED_COUNT 0 | ||
274 | #define BM_DIGCTL_AHBSTALLED_COUNT 0xffffffff | ||
275 | #define BF_DIGCTL_AHBSTALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
276 | |||
277 | /** | ||
278 | * Register: HW_DIGCTL_ENTROPY | ||
279 | * Address: 0x90 | ||
280 | * SCT: no | ||
281 | */ | ||
282 | #define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) | ||
283 | #define BP_DIGCTL_ENTROPY_VALUE 0 | ||
284 | #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff | ||
285 | #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) | ||
286 | |||
287 | /** | ||
288 | * Register: HW_DIGCTL_ROMSHIELD | ||
289 | * Address: 0xa0 | ||
290 | * SCT: no | ||
291 | */ | ||
292 | #define HW_DIGCTL_ROMSHIELD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) | ||
293 | #define BP_DIGCTL_ROMSHIELD_WRITE_ONCE 0 | ||
294 | #define BM_DIGCTL_ROMSHIELD_WRITE_ONCE 0x1 | ||
295 | #define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v) (((v) << 0) & 0x1) | ||
296 | |||
297 | /** | ||
298 | * Register: HW_DIGCTL_MICROSECONDS | ||
299 | * Address: 0xb0 | ||
300 | * SCT: yes | ||
301 | */ | ||
302 | #define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) | ||
303 | #define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) | ||
304 | #define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) | ||
305 | #define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) | ||
306 | #define BP_DIGCTL_MICROSECONDS_VALUE 0 | ||
307 | #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff | ||
308 | #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) | ||
309 | |||
310 | /** | ||
311 | * Register: HW_DIGCTL_DBGRD | ||
312 | * Address: 0xc0 | ||
313 | * SCT: no | ||
314 | */ | ||
315 | #define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0)) | ||
316 | #define BP_DIGCTL_DBGRD_COMPLEMENT 0 | ||
317 | #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff | ||
318 | #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) | ||
319 | |||
320 | /** | ||
321 | * Register: HW_DIGCTL_DBG | ||
322 | * Address: 0xd0 | ||
323 | * SCT: no | ||
324 | */ | ||
325 | #define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) | ||
326 | #define BP_DIGCTL_DBG_VALUE 0 | ||
327 | #define BM_DIGCTL_DBG_VALUE 0xffffffff | ||
328 | #define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) | ||
329 | |||
330 | /** | ||
331 | * Register: HW_DIGCTL_1TRAM_BIST_CSR | ||
332 | * Address: 0xe0 | ||
333 | * SCT: yes | ||
334 | */ | ||
335 | #define HW_DIGCTL_1TRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x0)) | ||
336 | #define HW_DIGCTL_1TRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x4)) | ||
337 | #define HW_DIGCTL_1TRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x8)) | ||
338 | #define HW_DIGCTL_1TRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0xc)) | ||
339 | #define BP_DIGCTL_1TRAM_BIST_CSR_FAIL 3 | ||
340 | #define BM_DIGCTL_1TRAM_BIST_CSR_FAIL 0x8 | ||
341 | #define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) | ||
342 | #define BP_DIGCTL_1TRAM_BIST_CSR_PASS 2 | ||
343 | #define BM_DIGCTL_1TRAM_BIST_CSR_PASS 0x4 | ||
344 | #define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) | ||
345 | #define BP_DIGCTL_1TRAM_BIST_CSR_DONE 1 | ||
346 | #define BM_DIGCTL_1TRAM_BIST_CSR_DONE 0x2 | ||
347 | #define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) | ||
348 | #define BP_DIGCTL_1TRAM_BIST_CSR_START 0 | ||
349 | #define BM_DIGCTL_1TRAM_BIST_CSR_START 0x1 | ||
350 | #define BF_DIGCTL_1TRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) | ||
351 | |||
352 | /** | ||
353 | * Register: HW_DIGCTL_1TRAM_BIST_REPAIR0 | ||
354 | * Address: 0xf0 | ||
355 | * SCT: no | ||
356 | */ | ||
357 | #define HW_DIGCTL_1TRAM_BIST_REPAIR0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0)) | ||
358 | |||
359 | /** | ||
360 | * Register: HW_DIGCTL_1TRAM_BIST_REPAIR1 | ||
361 | * Address: 0x100 | ||
362 | * SCT: no | ||
363 | */ | ||
364 | #define HW_DIGCTL_1TRAM_BIST_REPAIR1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x100)) | ||
365 | |||
366 | /** | ||
367 | * Register: HW_DIGCTL_1TRAM_STATUS0 | ||
368 | * Address: 0x110 | ||
369 | * SCT: no | ||
370 | */ | ||
371 | #define HW_DIGCTL_1TRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110)) | ||
372 | #define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00 0 | ||
373 | #define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 0xffffffff | ||
374 | #define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) | ||
375 | |||
376 | /** | ||
377 | * Register: HW_DIGCTL_1TRAM_STATUS1 | ||
378 | * Address: 0x120 | ||
379 | * SCT: no | ||
380 | */ | ||
381 | #define HW_DIGCTL_1TRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120)) | ||
382 | #define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01 0 | ||
383 | #define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 0xffffffff | ||
384 | #define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) | ||
385 | |||
386 | /** | ||
387 | * Register: HW_DIGCTL_1TRAM_STATUS2 | ||
388 | * Address: 0x130 | ||
389 | * SCT: no | ||
390 | */ | ||
391 | #define HW_DIGCTL_1TRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130)) | ||
392 | #define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10 0 | ||
393 | #define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 0xffffffff | ||
394 | #define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) | ||
395 | |||
396 | /** | ||
397 | * Register: HW_DIGCTL_1TRAM_STATUS3 | ||
398 | * Address: 0x140 | ||
399 | * SCT: no | ||
400 | */ | ||
401 | #define HW_DIGCTL_1TRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140)) | ||
402 | #define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11 0 | ||
403 | #define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 0xffffffff | ||
404 | #define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) | ||
405 | |||
406 | /** | ||
407 | * Register: HW_DIGCTL_1TRAM_STATUS4 | ||
408 | * Address: 0x150 | ||
409 | * SCT: no | ||
410 | */ | ||
411 | #define HW_DIGCTL_1TRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150)) | ||
412 | #define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20 0 | ||
413 | #define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 0xffffffff | ||
414 | #define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) | ||
415 | |||
416 | /** | ||
417 | * Register: HW_DIGCTL_1TRAM_STATUS5 | ||
418 | * Address: 0x160 | ||
419 | * SCT: no | ||
420 | */ | ||
421 | #define HW_DIGCTL_1TRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160)) | ||
422 | #define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21 0 | ||
423 | #define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 0xffffffff | ||
424 | #define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) | ||
425 | |||
426 | /** | ||
427 | * Register: HW_DIGCTL_1TRAM_STATUS6 | ||
428 | * Address: 0x170 | ||
429 | * SCT: no | ||
430 | */ | ||
431 | #define HW_DIGCTL_1TRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170)) | ||
432 | #define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30 0 | ||
433 | #define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 0xffffffff | ||
434 | #define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) | ||
435 | |||
436 | /** | ||
437 | * Register: HW_DIGCTL_1TRAM_STATUS7 | ||
438 | * Address: 0x180 | ||
439 | * SCT: no | ||
440 | */ | ||
441 | #define HW_DIGCTL_1TRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180)) | ||
442 | #define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31 0 | ||
443 | #define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 0xffffffff | ||
444 | #define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) | ||
445 | |||
446 | /** | ||
447 | * Register: HW_DIGCTL_1TRAM_STATUS8 | ||
448 | * Address: 0x190 | ||
449 | * SCT: no | ||
450 | */ | ||
451 | #define HW_DIGCTL_1TRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190)) | ||
452 | #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01 16 | ||
453 | #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 0xffff0000 | ||
454 | #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0xffff0000) | ||
455 | #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00 0 | ||
456 | #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 0xffff | ||
457 | #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0xffff) | ||
458 | |||
459 | /** | ||
460 | * Register: HW_DIGCTL_1TRAM_STATUS9 | ||
461 | * Address: 0x1a0 | ||
462 | * SCT: no | ||
463 | */ | ||
464 | #define HW_DIGCTL_1TRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0)) | ||
465 | #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11 16 | ||
466 | #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 0xffff0000 | ||
467 | #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0xffff0000) | ||
468 | #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10 0 | ||
469 | #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 0xffff | ||
470 | #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0xffff) | ||
471 | |||
472 | /** | ||
473 | * Register: HW_DIGCTL_1TRAM_STATUS10 | ||
474 | * Address: 0x1b0 | ||
475 | * SCT: no | ||
476 | */ | ||
477 | #define HW_DIGCTL_1TRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0)) | ||
478 | #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21 16 | ||
479 | #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 0xffff0000 | ||
480 | #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0xffff0000) | ||
481 | #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20 0 | ||
482 | #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 0xffff | ||
483 | #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0xffff) | ||
484 | |||
485 | /** | ||
486 | * Register: HW_DIGCTL_1TRAM_STATUS11 | ||
487 | * Address: 0x1c0 | ||
488 | * SCT: no | ||
489 | */ | ||
490 | #define HW_DIGCTL_1TRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0)) | ||
491 | #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31 16 | ||
492 | #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 0xffff0000 | ||
493 | #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0xffff0000) | ||
494 | #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30 0 | ||
495 | #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 0xffff | ||
496 | #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0xffff) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_DIGCTL_1TRAM_STATUS12 | ||
500 | * Address: 0x1d0 | ||
501 | * SCT: no | ||
502 | */ | ||
503 | #define HW_DIGCTL_1TRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0)) | ||
504 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11 24 | ||
505 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 0x1f000000 | ||
506 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000) | ||
507 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10 16 | ||
508 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 0x1f0000 | ||
509 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000) | ||
510 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01 8 | ||
511 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 0x1f00 | ||
512 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00) | ||
513 | #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0 | ||
514 | #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0x1f | ||
515 | #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f) | ||
516 | |||
517 | /** | ||
518 | * Register: HW_DIGCTL_1TRAM_STATUS13 | ||
519 | * Address: 0x1e0 | ||
520 | * SCT: no | ||
521 | */ | ||
522 | #define HW_DIGCTL_1TRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0)) | ||
523 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31 24 | ||
524 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 0x1f000000 | ||
525 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000) | ||
526 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30 16 | ||
527 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 0x1f0000 | ||
528 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000) | ||
529 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21 8 | ||
530 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 0x1f00 | ||
531 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00) | ||
532 | #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0 | ||
533 | #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0x1f | ||
534 | #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f) | ||
535 | |||
536 | /** | ||
537 | * Register: HW_DIGCTL_SCRATCH0 | ||
538 | * Address: 0x290 | ||
539 | * SCT: no | ||
540 | */ | ||
541 | #define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) | ||
542 | #define BP_DIGCTL_SCRATCH0_PTR 0 | ||
543 | #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff | ||
544 | #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) | ||
545 | |||
546 | /** | ||
547 | * Register: HW_DIGCTL_SCRATCH1 | ||
548 | * Address: 0x2a0 | ||
549 | * SCT: no | ||
550 | */ | ||
551 | #define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) | ||
552 | #define BP_DIGCTL_SCRATCH1_PTR 0 | ||
553 | #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff | ||
554 | #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) | ||
555 | |||
556 | /** | ||
557 | * Register: HW_DIGCTL_ARMCACHE | ||
558 | * Address: 0x2b0 | ||
559 | * SCT: no | ||
560 | */ | ||
561 | #define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) | ||
562 | #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 | ||
563 | #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 | ||
564 | #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) | ||
565 | #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 | ||
566 | #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 | ||
567 | #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) | ||
568 | #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 | ||
569 | #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 | ||
570 | #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) | ||
571 | |||
572 | /** | ||
573 | * Register: HW_DIGCTL_SGTL | ||
574 | * Address: 0x300 | ||
575 | * SCT: no | ||
576 | */ | ||
577 | #define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) | ||
578 | #define BP_DIGCTL_SGTL_COPYRIGHT 0 | ||
579 | #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff | ||
580 | #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) | ||
581 | |||
582 | /** | ||
583 | * Register: HW_DIGCTL_CHIPID | ||
584 | * Address: 0x310 | ||
585 | * SCT: no | ||
586 | */ | ||
587 | #define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) | ||
588 | #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 | ||
589 | #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 | ||
590 | #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) | ||
591 | #define BP_DIGCTL_CHIPID_REVISION 0 | ||
592 | #define BM_DIGCTL_CHIPID_REVISION 0xff | ||
593 | #define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) | ||
594 | |||
595 | #endif /* __HEADERGEN__STMP3600__DIGCTL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h new file mode 100644 index 0000000000..2d2624a953 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h | |||
@@ -0,0 +1,258 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__DRI__H__ | ||
24 | #define __HEADERGEN__STMP3600__DRI__H__ | ||
25 | |||
26 | #define REGS_DRI_BASE (0x80074000) | ||
27 | |||
28 | #define REGS_DRI_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DRI_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DRI_CTRL_SFTRST 31 | ||
40 | #define BM_DRI_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_DRI_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_DRI_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_DRI_CTRL_CLKGATE 30 | ||
46 | #define BM_DRI_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_DRI_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_DRI_CTRL_ENABLE_INPUTS 29 | ||
52 | #define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 | ||
53 | #define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0 | ||
54 | #define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1 | ||
55 | #define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000) | ||
57 | #define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26 | ||
58 | #define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000 | ||
59 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0 | ||
60 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1 | ||
61 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000) | ||
62 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000) | ||
63 | #define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25 | ||
64 | #define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000 | ||
65 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0 | ||
66 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1 | ||
67 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000) | ||
68 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000) | ||
69 | #define BP_DRI_CTRL_DMA_DELAY_COUNT 16 | ||
70 | #define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000 | ||
71 | #define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000) | ||
72 | #define BP_DRI_CTRL_REACQUIRE_PHASE 15 | ||
73 | #define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000 | ||
74 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0 | ||
75 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1 | ||
76 | #define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000) | ||
77 | #define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000) | ||
78 | #define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11 | ||
79 | #define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800 | ||
80 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0 | ||
81 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1 | ||
82 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800) | ||
83 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800) | ||
84 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10 | ||
85 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400 | ||
86 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0 | ||
87 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1 | ||
88 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
89 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
90 | #define BP_DRI_CTRL_ATTENTION_IRQ_EN 9 | ||
91 | #define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200 | ||
92 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0 | ||
93 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1 | ||
94 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200) | ||
95 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200) | ||
96 | #define BP_DRI_CTRL_OVERFLOW_IRQ 3 | ||
97 | #define BM_DRI_CTRL_OVERFLOW_IRQ 0x8 | ||
98 | #define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
99 | #define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1 | ||
100 | #define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
101 | #define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8) | ||
102 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2 | ||
103 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4 | ||
104 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0 | ||
105 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1 | ||
106 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
107 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4) | ||
108 | #define BP_DRI_CTRL_ATTENTION_IRQ 1 | ||
109 | #define BM_DRI_CTRL_ATTENTION_IRQ 0x2 | ||
110 | #define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0 | ||
111 | #define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1 | ||
112 | #define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2) | ||
113 | #define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2) | ||
114 | #define BP_DRI_CTRL_RUN 0 | ||
115 | #define BM_DRI_CTRL_RUN 0x1 | ||
116 | #define BV_DRI_CTRL_RUN__HALT 0x0 | ||
117 | #define BV_DRI_CTRL_RUN__RUN 0x1 | ||
118 | #define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
119 | #define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1) | ||
120 | |||
121 | /** | ||
122 | * Register: HW_DRI_TIMING | ||
123 | * Address: 0x10 | ||
124 | * SCT: no | ||
125 | */ | ||
126 | #define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10)) | ||
127 | #define BP_DRI_TIMING_PILOT_REP_RATE 16 | ||
128 | #define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000 | ||
129 | #define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000) | ||
130 | #define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 | ||
131 | #define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff | ||
132 | #define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff) | ||
133 | |||
134 | /** | ||
135 | * Register: HW_DRI_STAT | ||
136 | * Address: 0x20 | ||
137 | * SCT: no | ||
138 | */ | ||
139 | #define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20)) | ||
140 | #define BP_DRI_STAT_DRI_PRESENT 31 | ||
141 | #define BM_DRI_STAT_DRI_PRESENT 0x80000000 | ||
142 | #define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0 | ||
143 | #define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1 | ||
144 | #define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000) | ||
145 | #define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000) | ||
146 | #define BP_DRI_STAT_PILOT_PHASE 16 | ||
147 | #define BM_DRI_STAT_PILOT_PHASE 0xf0000 | ||
148 | #define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000) | ||
149 | #define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3 | ||
150 | #define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8 | ||
151 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
152 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1 | ||
153 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
154 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8) | ||
155 | #define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2 | ||
156 | #define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4 | ||
157 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
158 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
159 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
160 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
161 | #define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1 | ||
162 | #define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2 | ||
163 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
164 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1 | ||
165 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
166 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2) | ||
167 | |||
168 | /** | ||
169 | * Register: HW_DRI_DATA | ||
170 | * Address: 0x30 | ||
171 | * SCT: no | ||
172 | */ | ||
173 | #define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30)) | ||
174 | #define BP_DRI_DATA_DATA 0 | ||
175 | #define BM_DRI_DATA_DATA 0xffffffff | ||
176 | #define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
177 | |||
178 | /** | ||
179 | * Register: HW_DRI_DEBUG0 | ||
180 | * Address: 0x40 | ||
181 | * SCT: yes | ||
182 | */ | ||
183 | #define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0)) | ||
184 | #define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4)) | ||
185 | #define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8)) | ||
186 | #define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc)) | ||
187 | #define BP_DRI_DEBUG0_DMAREQ 31 | ||
188 | #define BM_DRI_DEBUG0_DMAREQ 0x80000000 | ||
189 | #define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
190 | #define BP_DRI_DEBUG0_DMACMDKICK 30 | ||
191 | #define BM_DRI_DEBUG0_DMACMDKICK 0x40000000 | ||
192 | #define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000) | ||
193 | #define BP_DRI_DEBUG0_DRI_CLK_INPUT 29 | ||
194 | #define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000 | ||
195 | #define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000) | ||
196 | #define BP_DRI_DEBUG0_DRI_DATA_INPUT 28 | ||
197 | #define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000 | ||
198 | #define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000) | ||
199 | #define BP_DRI_DEBUG0_TEST_MODE 27 | ||
200 | #define BM_DRI_DEBUG0_TEST_MODE 0x8000000 | ||
201 | #define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000) | ||
202 | #define BP_DRI_DEBUG0_PILOT_REP_RATE 26 | ||
203 | #define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000 | ||
204 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0 | ||
205 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1 | ||
206 | #define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000) | ||
207 | #define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000) | ||
208 | #define BP_DRI_DEBUG0_SPARE 18 | ||
209 | #define BM_DRI_DEBUG0_SPARE 0x3fc0000 | ||
210 | #define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000) | ||
211 | #define BP_DRI_DEBUG0_FRAME 0 | ||
212 | #define BM_DRI_DEBUG0_FRAME 0x3ffff | ||
213 | #define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff) | ||
214 | |||
215 | /** | ||
216 | * Register: HW_DRI_DEBUG1 | ||
217 | * Address: 0x50 | ||
218 | * SCT: yes | ||
219 | */ | ||
220 | #define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0)) | ||
221 | #define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4)) | ||
222 | #define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8)) | ||
223 | #define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc)) | ||
224 | #define BP_DRI_DEBUG1_INVERT_PILOT 31 | ||
225 | #define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000 | ||
226 | #define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0 | ||
227 | #define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1 | ||
228 | #define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000) | ||
229 | #define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000) | ||
230 | #define BP_DRI_DEBUG1_INVERT_ATTENTION 30 | ||
231 | #define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000 | ||
232 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0 | ||
233 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1 | ||
234 | #define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000) | ||
235 | #define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000) | ||
236 | #define BP_DRI_DEBUG1_INVERT_DRI_DATA 29 | ||
237 | #define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000 | ||
238 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0 | ||
239 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1 | ||
240 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000) | ||
241 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000) | ||
242 | #define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28 | ||
243 | #define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000 | ||
244 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0 | ||
245 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1 | ||
246 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000) | ||
247 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000) | ||
248 | #define BP_DRI_DEBUG1_REVERSE_FRAME 27 | ||
249 | #define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000 | ||
250 | #define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0 | ||
251 | #define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1 | ||
252 | #define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000) | ||
253 | #define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000) | ||
254 | #define BP_DRI_DEBUG1_SWIZZLED_FRAME 0 | ||
255 | #define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff | ||
256 | #define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff) | ||
257 | |||
258 | #endif /* __HEADERGEN__STMP3600__DRI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h new file mode 100644 index 0000000000..88a94f977b --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__EMICTRL__H__ | ||
24 | #define __HEADERGEN__STMP3600__EMICTRL__H__ | ||
25 | |||
26 | #define REGS_EMICTRL_BASE (0x80020000) | ||
27 | |||
28 | #define REGS_EMICTRL_VERSION "2.3.0" | ||
29 | |||
30 | #endif /* __HEADERGEN__STMP3600__EMICTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h new file mode 100644 index 0000000000..bdf52c9308 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h | |||
@@ -0,0 +1,372 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__GPMI__H__ | ||
24 | #define __HEADERGEN__STMP3600__GPMI__H__ | ||
25 | |||
26 | #define REGS_GPMI_BASE (0x8000c000) | ||
27 | |||
28 | #define REGS_GPMI_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_GPMI_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_GPMI_CTRL0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_GPMI_CTRL0_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_GPMI_CTRL0_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_GPMI_CTRL0_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_GPMI_CTRL0_SFTRST 31 | ||
40 | #define BM_GPMI_CTRL0_SFTRST 0x80000000 | ||
41 | #define BV_GPMI_CTRL0_SFTRST__RUN 0x0 | ||
42 | #define BV_GPMI_CTRL0_SFTRST__RESET 0x1 | ||
43 | #define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_GPMI_CTRL0_SFTRST_V(v) ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_GPMI_CTRL0_CLKGATE 30 | ||
46 | #define BM_GPMI_CTRL0_CLKGATE 0x40000000 | ||
47 | #define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 | ||
48 | #define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_GPMI_CTRL0_CLKGATE_V(v) ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_GPMI_CTRL0_RUN 29 | ||
52 | #define BM_GPMI_CTRL0_RUN 0x20000000 | ||
53 | #define BV_GPMI_CTRL0_RUN__IDLE 0x0 | ||
54 | #define BV_GPMI_CTRL0_RUN__BUSY 0x1 | ||
55 | #define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_GPMI_CTRL0_RUN_V(v) ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000) | ||
57 | #define BP_GPMI_CTRL0_DEV_IRQ_EN 28 | ||
58 | #define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 | ||
59 | #define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
60 | #define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27 | ||
61 | #define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x8000000 | ||
62 | #define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & 0x8000000) | ||
63 | #define BP_GPMI_CTRL0_UDMA 26 | ||
64 | #define BM_GPMI_CTRL0_UDMA 0x4000000 | ||
65 | #define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 | ||
66 | #define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 | ||
67 | #define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & 0x4000000) | ||
68 | #define BF_GPMI_CTRL0_UDMA_V(v) ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000) | ||
69 | #define BP_GPMI_CTRL0_COMMAND_MODE 24 | ||
70 | #define BM_GPMI_CTRL0_COMMAND_MODE 0x3000000 | ||
71 | #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 | ||
72 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 | ||
73 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 | ||
74 | #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 | ||
75 | #define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & 0x3000000) | ||
76 | #define BF_GPMI_CTRL0_COMMAND_MODE_V(v) ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000) | ||
77 | #define BP_GPMI_CTRL0_WORD_LENGTH 23 | ||
78 | #define BM_GPMI_CTRL0_WORD_LENGTH 0x800000 | ||
79 | #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 | ||
80 | #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 | ||
81 | #define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & 0x800000) | ||
82 | #define BF_GPMI_CTRL0_WORD_LENGTH_V(v) ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000) | ||
83 | #define BP_GPMI_CTRL0_LOCK_CS 22 | ||
84 | #define BM_GPMI_CTRL0_LOCK_CS 0x400000 | ||
85 | #define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 | ||
86 | #define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 | ||
87 | #define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & 0x400000) | ||
88 | #define BF_GPMI_CTRL0_LOCK_CS_V(v) ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000) | ||
89 | #define BP_GPMI_CTRL0_CS 20 | ||
90 | #define BM_GPMI_CTRL0_CS 0x300000 | ||
91 | #define BF_GPMI_CTRL0_CS(v) (((v) << 20) & 0x300000) | ||
92 | #define BP_GPMI_CTRL0_ADDRESS 17 | ||
93 | #define BM_GPMI_CTRL0_ADDRESS 0xe0000 | ||
94 | #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 | ||
95 | #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 | ||
96 | #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 | ||
97 | #define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & 0xe0000) | ||
98 | #define BF_GPMI_CTRL0_ADDRESS_V(v) ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000) | ||
99 | #define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 | ||
100 | #define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x10000 | ||
101 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 | ||
102 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 | ||
103 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & 0x10000) | ||
104 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000) | ||
105 | #define BP_GPMI_CTRL0_XFER_COUNT 0 | ||
106 | #define BM_GPMI_CTRL0_XFER_COUNT 0xffff | ||
107 | #define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_GPMI_COMPARE | ||
111 | * Address: 0x10 | ||
112 | * SCT: no | ||
113 | */ | ||
114 | #define HW_GPMI_COMPARE (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10)) | ||
115 | #define BP_GPMI_COMPARE_MASK 16 | ||
116 | #define BM_GPMI_COMPARE_MASK 0xffff0000 | ||
117 | #define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & 0xffff0000) | ||
118 | #define BP_GPMI_COMPARE_REFERENCE 0 | ||
119 | #define BM_GPMI_COMPARE_REFERENCE 0xffff | ||
120 | #define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & 0xffff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_GPMI_CTRL1 | ||
124 | * Address: 0x20 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_GPMI_CTRL1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0)) | ||
128 | #define HW_GPMI_CTRL1_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4)) | ||
129 | #define HW_GPMI_CTRL1_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8)) | ||
130 | #define HW_GPMI_CTRL1_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc)) | ||
131 | #define BP_GPMI_CTRL1_DSAMPLE_TIME 12 | ||
132 | #define BM_GPMI_CTRL1_DSAMPLE_TIME 0x3000 | ||
133 | #define BF_GPMI_CTRL1_DSAMPLE_TIME(v) (((v) << 12) & 0x3000) | ||
134 | #define BP_GPMI_CTRL1_DEV_IRQ 10 | ||
135 | #define BM_GPMI_CTRL1_DEV_IRQ 0x400 | ||
136 | #define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & 0x400) | ||
137 | #define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 | ||
138 | #define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x200 | ||
139 | #define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & 0x200) | ||
140 | #define BP_GPMI_CTRL1_BURST_EN 8 | ||
141 | #define BM_GPMI_CTRL1_BURST_EN 0x100 | ||
142 | #define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & 0x100) | ||
143 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7 | ||
144 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x80 | ||
145 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & 0x80) | ||
146 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6 | ||
147 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x40 | ||
148 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & 0x40) | ||
149 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5 | ||
150 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x20 | ||
151 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & 0x20) | ||
152 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4 | ||
153 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x10 | ||
154 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & 0x10) | ||
155 | #define BP_GPMI_CTRL1_DEV_RESET 3 | ||
156 | #define BM_GPMI_CTRL1_DEV_RESET 0x8 | ||
157 | #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 | ||
158 | #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 | ||
159 | #define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & 0x8) | ||
160 | #define BF_GPMI_CTRL1_DEV_RESET_V(v) ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8) | ||
161 | #define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 | ||
162 | #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x4 | ||
163 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 | ||
164 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 | ||
165 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & 0x4) | ||
166 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v) ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4) | ||
167 | #define BP_GPMI_CTRL1_CAMERA_MODE 1 | ||
168 | #define BM_GPMI_CTRL1_CAMERA_MODE 0x2 | ||
169 | #define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & 0x2) | ||
170 | #define BP_GPMI_CTRL1_GPMI_MODE 0 | ||
171 | #define BM_GPMI_CTRL1_GPMI_MODE 0x1 | ||
172 | #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 | ||
173 | #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 | ||
174 | #define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & 0x1) | ||
175 | #define BF_GPMI_CTRL1_GPMI_MODE_V(v) ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1) | ||
176 | |||
177 | /** | ||
178 | * Register: HW_GPMI_TIMING0 | ||
179 | * Address: 0x30 | ||
180 | * SCT: no | ||
181 | */ | ||
182 | #define HW_GPMI_TIMING0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30)) | ||
183 | #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 | ||
184 | #define BM_GPMI_TIMING0_ADDRESS_SETUP 0xff0000 | ||
185 | #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & 0xff0000) | ||
186 | #define BP_GPMI_TIMING0_DATA_HOLD 8 | ||
187 | #define BM_GPMI_TIMING0_DATA_HOLD 0xff00 | ||
188 | #define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
189 | #define BP_GPMI_TIMING0_DATA_SETUP 0 | ||
190 | #define BM_GPMI_TIMING0_DATA_SETUP 0xff | ||
191 | #define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
192 | |||
193 | /** | ||
194 | * Register: HW_GPMI_TIMING1 | ||
195 | * Address: 0x40 | ||
196 | * SCT: no | ||
197 | */ | ||
198 | #define HW_GPMI_TIMING1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40)) | ||
199 | #define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 | ||
200 | #define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xffff0000 | ||
201 | #define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
202 | #define BP_GPMI_TIMING1_ATA_READY_TIMEOUT 0 | ||
203 | #define BM_GPMI_TIMING1_ATA_READY_TIMEOUT 0xffff | ||
204 | #define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v) (((v) << 0) & 0xffff) | ||
205 | |||
206 | /** | ||
207 | * Register: HW_GPMI_TIMING2 | ||
208 | * Address: 0x50 | ||
209 | * SCT: no | ||
210 | */ | ||
211 | #define HW_GPMI_TIMING2 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50)) | ||
212 | #define BP_GPMI_TIMING2_UDMA_TRP 24 | ||
213 | #define BM_GPMI_TIMING2_UDMA_TRP 0xff000000 | ||
214 | #define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & 0xff000000) | ||
215 | #define BP_GPMI_TIMING2_UDMA_ENV 16 | ||
216 | #define BM_GPMI_TIMING2_UDMA_ENV 0xff0000 | ||
217 | #define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & 0xff0000) | ||
218 | #define BP_GPMI_TIMING2_UDMA_HOLD 8 | ||
219 | #define BM_GPMI_TIMING2_UDMA_HOLD 0xff00 | ||
220 | #define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & 0xff00) | ||
221 | #define BP_GPMI_TIMING2_UDMA_SETUP 0 | ||
222 | #define BM_GPMI_TIMING2_UDMA_SETUP 0xff | ||
223 | #define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & 0xff) | ||
224 | |||
225 | /** | ||
226 | * Register: HW_GPMI_DATA | ||
227 | * Address: 0x60 | ||
228 | * SCT: no | ||
229 | */ | ||
230 | #define HW_GPMI_DATA (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60)) | ||
231 | #define BP_GPMI_DATA_DATA 0 | ||
232 | #define BM_GPMI_DATA_DATA 0xffffffff | ||
233 | #define BF_GPMI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
234 | |||
235 | /** | ||
236 | * Register: HW_GPMI_STAT | ||
237 | * Address: 0x70 | ||
238 | * SCT: no | ||
239 | */ | ||
240 | #define HW_GPMI_STAT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70)) | ||
241 | #define BP_GPMI_STAT_PRESENT 31 | ||
242 | #define BM_GPMI_STAT_PRESENT 0x80000000 | ||
243 | #define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 | ||
244 | #define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 | ||
245 | #define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
246 | #define BF_GPMI_STAT_PRESENT_V(v) ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000) | ||
247 | #define BP_GPMI_STAT_RDY_TIMEOUT 8 | ||
248 | #define BM_GPMI_STAT_RDY_TIMEOUT 0xf00 | ||
249 | #define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & 0xf00) | ||
250 | #define BP_GPMI_STAT_ATA_IRQ 7 | ||
251 | #define BM_GPMI_STAT_ATA_IRQ 0x80 | ||
252 | #define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & 0x80) | ||
253 | #define BP_GPMI_STAT_FIFO_EMPTY 5 | ||
254 | #define BM_GPMI_STAT_FIFO_EMPTY 0x20 | ||
255 | #define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 | ||
256 | #define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 | ||
257 | #define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
258 | #define BF_GPMI_STAT_FIFO_EMPTY_V(v) ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20) | ||
259 | #define BP_GPMI_STAT_FIFO_FULL 4 | ||
260 | #define BM_GPMI_STAT_FIFO_FULL 0x10 | ||
261 | #define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 | ||
262 | #define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 | ||
263 | #define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & 0x10) | ||
264 | #define BF_GPMI_STAT_FIFO_FULL_V(v) ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10) | ||
265 | #define BP_GPMI_STAT_DEV3_ERROR 3 | ||
266 | #define BM_GPMI_STAT_DEV3_ERROR 0x8 | ||
267 | #define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & 0x8) | ||
268 | #define BP_GPMI_STAT_DEV2_ERROR 2 | ||
269 | #define BM_GPMI_STAT_DEV2_ERROR 0x4 | ||
270 | #define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & 0x4) | ||
271 | #define BP_GPMI_STAT_DEV1_ERROR 1 | ||
272 | #define BM_GPMI_STAT_DEV1_ERROR 0x2 | ||
273 | #define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & 0x2) | ||
274 | #define BP_GPMI_STAT_DEV0_ERROR 0 | ||
275 | #define BM_GPMI_STAT_DEV0_ERROR 0x1 | ||
276 | #define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & 0x1) | ||
277 | |||
278 | /** | ||
279 | * Register: HW_GPMI_DEBUG | ||
280 | * Address: 0x80 | ||
281 | * SCT: no | ||
282 | */ | ||
283 | #define HW_GPMI_DEBUG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80)) | ||
284 | #define BP_GPMI_DEBUG_READY3 31 | ||
285 | #define BM_GPMI_DEBUG_READY3 0x80000000 | ||
286 | #define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & 0x80000000) | ||
287 | #define BP_GPMI_DEBUG_READY2 30 | ||
288 | #define BM_GPMI_DEBUG_READY2 0x40000000 | ||
289 | #define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & 0x40000000) | ||
290 | #define BP_GPMI_DEBUG_READY1 29 | ||
291 | #define BM_GPMI_DEBUG_READY1 0x20000000 | ||
292 | #define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & 0x20000000) | ||
293 | #define BP_GPMI_DEBUG_READY0 28 | ||
294 | #define BM_GPMI_DEBUG_READY0 0x10000000 | ||
295 | #define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & 0x10000000) | ||
296 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27 | ||
297 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x8000000 | ||
298 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & 0x8000000) | ||
299 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26 | ||
300 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x4000000 | ||
301 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & 0x4000000) | ||
302 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25 | ||
303 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x2000000 | ||
304 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & 0x2000000) | ||
305 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24 | ||
306 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x1000000 | ||
307 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & 0x1000000) | ||
308 | #define BP_GPMI_DEBUG_SENSE3 23 | ||
309 | #define BM_GPMI_DEBUG_SENSE3 0x800000 | ||
310 | #define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & 0x800000) | ||
311 | #define BP_GPMI_DEBUG_SENSE2 22 | ||
312 | #define BM_GPMI_DEBUG_SENSE2 0x400000 | ||
313 | #define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & 0x400000) | ||
314 | #define BP_GPMI_DEBUG_SENSE1 21 | ||
315 | #define BM_GPMI_DEBUG_SENSE1 0x200000 | ||
316 | #define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & 0x200000) | ||
317 | #define BP_GPMI_DEBUG_SENSE0 20 | ||
318 | #define BM_GPMI_DEBUG_SENSE0 0x100000 | ||
319 | #define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & 0x100000) | ||
320 | #define BP_GPMI_DEBUG_DMAREQ3 19 | ||
321 | #define BM_GPMI_DEBUG_DMAREQ3 0x80000 | ||
322 | #define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & 0x80000) | ||
323 | #define BP_GPMI_DEBUG_DMAREQ2 18 | ||
324 | #define BM_GPMI_DEBUG_DMAREQ2 0x40000 | ||
325 | #define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & 0x40000) | ||
326 | #define BP_GPMI_DEBUG_DMAREQ1 17 | ||
327 | #define BM_GPMI_DEBUG_DMAREQ1 0x20000 | ||
328 | #define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & 0x20000) | ||
329 | #define BP_GPMI_DEBUG_DMAREQ0 16 | ||
330 | #define BM_GPMI_DEBUG_DMAREQ0 0x10000 | ||
331 | #define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & 0x10000) | ||
332 | #define BP_GPMI_DEBUG_CMD_END 12 | ||
333 | #define BM_GPMI_DEBUG_CMD_END 0xf000 | ||
334 | #define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & 0xf000) | ||
335 | #define BP_GPMI_DEBUG_UDMA_STATE 8 | ||
336 | #define BM_GPMI_DEBUG_UDMA_STATE 0xf00 | ||
337 | #define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & 0xf00) | ||
338 | #define BP_GPMI_DEBUG_BUSY 7 | ||
339 | #define BM_GPMI_DEBUG_BUSY 0x80 | ||
340 | #define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 | ||
341 | #define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 | ||
342 | #define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & 0x80) | ||
343 | #define BF_GPMI_DEBUG_BUSY_V(v) ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80) | ||
344 | #define BP_GPMI_DEBUG_PIN_STATE 4 | ||
345 | #define BM_GPMI_DEBUG_PIN_STATE 0x70 | ||
346 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 | ||
347 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 | ||
348 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 | ||
349 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 | ||
350 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 | ||
351 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 | ||
352 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 | ||
353 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 | ||
354 | #define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & 0x70) | ||
355 | #define BF_GPMI_DEBUG_PIN_STATE_V(v) ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70) | ||
356 | #define BP_GPMI_DEBUG_MAIN_STATE 0 | ||
357 | #define BM_GPMI_DEBUG_MAIN_STATE 0xf | ||
358 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 | ||
359 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 | ||
360 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 | ||
361 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 | ||
362 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 | ||
363 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 | ||
364 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 | ||
365 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 | ||
366 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 | ||
367 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 | ||
368 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xa | ||
369 | #define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & 0xf) | ||
370 | #define BF_GPMI_DEBUG_MAIN_STATE_V(v) ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf) | ||
371 | |||
372 | #endif /* __HEADERGEN__STMP3600__GPMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h new file mode 100644 index 0000000000..b6e5ead2ba --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h | |||
@@ -0,0 +1,223 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__HWECC__H__ | ||
24 | #define __HEADERGEN__STMP3600__HWECC__H__ | ||
25 | |||
26 | #define REGS_HWECC_BASE (0x80008000) | ||
27 | |||
28 | #define REGS_HWECC_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_HWECC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_HWECC_CTRL (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_HWECC_CTRL_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_HWECC_CTRL_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_HWECC_CTRL_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_HWECC_CTRL_SFTRST 31 | ||
40 | #define BM_HWECC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_HWECC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_HWECC_CTRL_CLKGATE 30 | ||
43 | #define BM_HWECC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_HWECC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_HWECC_CTRL_NUM_SYMBOLS 16 | ||
46 | #define BM_HWECC_CTRL_NUM_SYMBOLS 0x1ff0000 | ||
47 | #define BF_HWECC_CTRL_NUM_SYMBOLS(v) (((v) << 16) & 0x1ff0000) | ||
48 | #define BP_HWECC_CTRL_DMAWAIT_COUNT 8 | ||
49 | #define BM_HWECC_CTRL_DMAWAIT_COUNT 0x1f00 | ||
50 | #define BF_HWECC_CTRL_DMAWAIT_COUNT(v) (((v) << 8) & 0x1f00) | ||
51 | #define BP_HWECC_CTRL_BYTE_ENABLE 6 | ||
52 | #define BM_HWECC_CTRL_BYTE_ENABLE 0x40 | ||
53 | #define BF_HWECC_CTRL_BYTE_ENABLE(v) (((v) << 6) & 0x40) | ||
54 | #define BP_HWECC_CTRL_ECC_SEL 5 | ||
55 | #define BM_HWECC_CTRL_ECC_SEL 0x20 | ||
56 | #define BF_HWECC_CTRL_ECC_SEL(v) (((v) << 5) & 0x20) | ||
57 | #define BP_HWECC_CTRL_ENC_SEL 4 | ||
58 | #define BM_HWECC_CTRL_ENC_SEL 0x10 | ||
59 | #define BF_HWECC_CTRL_ENC_SEL(v) (((v) << 4) & 0x10) | ||
60 | #define BP_HWECC_CTRL_UNCORR_IRQ 2 | ||
61 | #define BM_HWECC_CTRL_UNCORR_IRQ 0x4 | ||
62 | #define BF_HWECC_CTRL_UNCORR_IRQ(v) (((v) << 2) & 0x4) | ||
63 | #define BP_HWECC_CTRL_UNCORR_IRQ_EN 1 | ||
64 | #define BM_HWECC_CTRL_UNCORR_IRQ_EN 0x2 | ||
65 | #define BF_HWECC_CTRL_UNCORR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
66 | #define BP_HWECC_CTRL_RUN 0 | ||
67 | #define BM_HWECC_CTRL_RUN 0x1 | ||
68 | #define BF_HWECC_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_HWECC_STAT | ||
72 | * Address: 0x10 | ||
73 | * SCT: no | ||
74 | */ | ||
75 | #define HW_HWECC_STAT (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x10)) | ||
76 | #define BP_HWECC_STAT_RSDEC_PRESENT 31 | ||
77 | #define BM_HWECC_STAT_RSDEC_PRESENT 0x80000000 | ||
78 | #define BF_HWECC_STAT_RSDEC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
79 | #define BP_HWECC_STAT_RSENC_PRESENT 30 | ||
80 | #define BM_HWECC_STAT_RSENC_PRESENT 0x40000000 | ||
81 | #define BF_HWECC_STAT_RSENC_PRESENT(v) (((v) << 30) & 0x40000000) | ||
82 | #define BP_HWECC_STAT_SSDEC_PRESENT 29 | ||
83 | #define BM_HWECC_STAT_SSDEC_PRESENT 0x20000000 | ||
84 | #define BF_HWECC_STAT_SSDEC_PRESENT(v) (((v) << 29) & 0x20000000) | ||
85 | #define BP_HWECC_STAT_SSENC_PRESENT 28 | ||
86 | #define BM_HWECC_STAT_SSENC_PRESENT 0x10000000 | ||
87 | #define BF_HWECC_STAT_SSENC_PRESENT(v) (((v) << 28) & 0x10000000) | ||
88 | |||
89 | /** | ||
90 | * Register: HW_HWECC_DEBUG0 | ||
91 | * Address: 0x20 | ||
92 | * SCT: no | ||
93 | */ | ||
94 | #define HW_HWECC_DEBUG0 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x20)) | ||
95 | #define BP_HWECC_DEBUG0_DMA_PENDCMD 29 | ||
96 | #define BM_HWECC_DEBUG0_DMA_PENDCMD 0x20000000 | ||
97 | #define BF_HWECC_DEBUG0_DMA_PENDCMD(v) (((v) << 29) & 0x20000000) | ||
98 | #define BP_HWECC_DEBUG0_DMA_PREQ 28 | ||
99 | #define BM_HWECC_DEBUG0_DMA_PREQ 0x10000000 | ||
100 | #define BF_HWECC_DEBUG0_DMA_PREQ(v) (((v) << 28) & 0x10000000) | ||
101 | #define BP_HWECC_DEBUG0_SYMBOL_STATE 24 | ||
102 | #define BM_HWECC_DEBUG0_SYMBOL_STATE 0xf000000 | ||
103 | #define BF_HWECC_DEBUG0_SYMBOL_STATE(v) (((v) << 24) & 0xf000000) | ||
104 | #define BP_HWECC_DEBUG0_CTRL_STATE 16 | ||
105 | #define BM_HWECC_DEBUG0_CTRL_STATE 0x3f0000 | ||
106 | #define BF_HWECC_DEBUG0_CTRL_STATE(v) (((v) << 16) & 0x3f0000) | ||
107 | #define BP_HWECC_DEBUG0_ECC_EXCEPTION 12 | ||
108 | #define BM_HWECC_DEBUG0_ECC_EXCEPTION 0xf000 | ||
109 | #define BF_HWECC_DEBUG0_ECC_EXCEPTION(v) (((v) << 12) & 0xf000) | ||
110 | #define BP_HWECC_DEBUG0_NUM_BIT_ERRORS 4 | ||
111 | #define BM_HWECC_DEBUG0_NUM_BIT_ERRORS 0x3f0 | ||
112 | #define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v) (((v) << 4) & 0x3f0) | ||
113 | #define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0 | ||
114 | #define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS 0x7 | ||
115 | #define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v) (((v) << 0) & 0x7) | ||
116 | |||
117 | /** | ||
118 | * Register: HW_HWECC_DEBUG1 | ||
119 | * Address: 0x30 | ||
120 | * SCT: no | ||
121 | */ | ||
122 | #define HW_HWECC_DEBUG1 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x30)) | ||
123 | #define BP_HWECC_DEBUG1_SYNDROME2 18 | ||
124 | #define BM_HWECC_DEBUG1_SYNDROME2 0x7fc0000 | ||
125 | #define BF_HWECC_DEBUG1_SYNDROME2(v) (((v) << 18) & 0x7fc0000) | ||
126 | #define BP_HWECC_DEBUG1_SYNDROME1 9 | ||
127 | #define BM_HWECC_DEBUG1_SYNDROME1 0x3fe00 | ||
128 | #define BF_HWECC_DEBUG1_SYNDROME1(v) (((v) << 9) & 0x3fe00) | ||
129 | #define BP_HWECC_DEBUG1_SYNDROME0 0 | ||
130 | #define BM_HWECC_DEBUG1_SYNDROME0 0x1ff | ||
131 | #define BF_HWECC_DEBUG1_SYNDROME0(v) (((v) << 0) & 0x1ff) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_HWECC_DEBUG2 | ||
135 | * Address: 0x40 | ||
136 | * SCT: no | ||
137 | */ | ||
138 | #define HW_HWECC_DEBUG2 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x40)) | ||
139 | #define BP_HWECC_DEBUG2_SYNDROME5 18 | ||
140 | #define BM_HWECC_DEBUG2_SYNDROME5 0x7fc0000 | ||
141 | #define BF_HWECC_DEBUG2_SYNDROME5(v) (((v) << 18) & 0x7fc0000) | ||
142 | #define BP_HWECC_DEBUG2_SYNDROME4 9 | ||
143 | #define BM_HWECC_DEBUG2_SYNDROME4 0x3fe00 | ||
144 | #define BF_HWECC_DEBUG2_SYNDROME4(v) (((v) << 9) & 0x3fe00) | ||
145 | #define BP_HWECC_DEBUG2_SYNDROME3 0 | ||
146 | #define BM_HWECC_DEBUG2_SYNDROME3 0x1ff | ||
147 | #define BF_HWECC_DEBUG2_SYNDROME3(v) (((v) << 0) & 0x1ff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_HWECC_DEBUG3 | ||
151 | * Address: 0x50 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_HWECC_DEBUG3 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x50)) | ||
155 | #define BP_HWECC_DEBUG3_OMEGA0 18 | ||
156 | #define BM_HWECC_DEBUG3_OMEGA0 0x7fc0000 | ||
157 | #define BF_HWECC_DEBUG3_OMEGA0(v) (((v) << 18) & 0x7fc0000) | ||
158 | #define BP_HWECC_DEBUG3_SYNDROME7 9 | ||
159 | #define BM_HWECC_DEBUG3_SYNDROME7 0x3fe00 | ||
160 | #define BF_HWECC_DEBUG3_SYNDROME7(v) (((v) << 9) & 0x3fe00) | ||
161 | #define BP_HWECC_DEBUG3_SYNDROME6 0 | ||
162 | #define BM_HWECC_DEBUG3_SYNDROME6 0x1ff | ||
163 | #define BF_HWECC_DEBUG3_SYNDROME6(v) (((v) << 0) & 0x1ff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_HWECC_DEBUG4 | ||
167 | * Address: 0x60 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_HWECC_DEBUG4 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x60)) | ||
171 | #define BP_HWECC_DEBUG4_OMEGA3 18 | ||
172 | #define BM_HWECC_DEBUG4_OMEGA3 0x7fc0000 | ||
173 | #define BF_HWECC_DEBUG4_OMEGA3(v) (((v) << 18) & 0x7fc0000) | ||
174 | #define BP_HWECC_DEBUG4_OMEGA2 9 | ||
175 | #define BM_HWECC_DEBUG4_OMEGA2 0x3fe00 | ||
176 | #define BF_HWECC_DEBUG4_OMEGA2(v) (((v) << 9) & 0x3fe00) | ||
177 | #define BP_HWECC_DEBUG4_OMEGA1 0 | ||
178 | #define BM_HWECC_DEBUG4_OMEGA1 0x1ff | ||
179 | #define BF_HWECC_DEBUG4_OMEGA1(v) (((v) << 0) & 0x1ff) | ||
180 | |||
181 | /** | ||
182 | * Register: HW_HWECC_DEBUG5 | ||
183 | * Address: 0x70 | ||
184 | * SCT: no | ||
185 | */ | ||
186 | #define HW_HWECC_DEBUG5 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x70)) | ||
187 | #define BP_HWECC_DEBUG5_LAMBDA2 18 | ||
188 | #define BM_HWECC_DEBUG5_LAMBDA2 0x7fc0000 | ||
189 | #define BF_HWECC_DEBUG5_LAMBDA2(v) (((v) << 18) & 0x7fc0000) | ||
190 | #define BP_HWECC_DEBUG5_LAMBDA1 9 | ||
191 | #define BM_HWECC_DEBUG5_LAMBDA1 0x3fe00 | ||
192 | #define BF_HWECC_DEBUG5_LAMBDA1(v) (((v) << 9) & 0x3fe00) | ||
193 | #define BP_HWECC_DEBUG5_LAMBDA0 0 | ||
194 | #define BM_HWECC_DEBUG5_LAMBDA0 0x1ff | ||
195 | #define BF_HWECC_DEBUG5_LAMBDA0(v) (((v) << 0) & 0x1ff) | ||
196 | |||
197 | /** | ||
198 | * Register: HW_HWECC_DEBUG6 | ||
199 | * Address: 0x80 | ||
200 | * SCT: no | ||
201 | */ | ||
202 | #define HW_HWECC_DEBUG6 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x80)) | ||
203 | #define BP_HWECC_DEBUG6_LAMBDA4 9 | ||
204 | #define BM_HWECC_DEBUG6_LAMBDA4 0x3fe00 | ||
205 | #define BF_HWECC_DEBUG6_LAMBDA4(v) (((v) << 9) & 0x3fe00) | ||
206 | #define BP_HWECC_DEBUG6_LAMBDA3 0 | ||
207 | #define BM_HWECC_DEBUG6_LAMBDA3 0x1ff | ||
208 | #define BF_HWECC_DEBUG6_LAMBDA3(v) (((v) << 0) & 0x1ff) | ||
209 | |||
210 | /** | ||
211 | * Register: HW_HWECC_DATA | ||
212 | * Address: 0x90 | ||
213 | * SCT: yes | ||
214 | */ | ||
215 | #define HW_HWECC_DATA (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x0)) | ||
216 | #define HW_HWECC_DATA_SET (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x4)) | ||
217 | #define HW_HWECC_DATA_CLR (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x8)) | ||
218 | #define HW_HWECC_DATA_TOG (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0xc)) | ||
219 | #define BP_HWECC_DATA_DATA 0 | ||
220 | #define BM_HWECC_DATA_DATA 0xffffffff | ||
221 | #define BF_HWECC_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
222 | |||
223 | #endif /* __HEADERGEN__STMP3600__HWECC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h new file mode 100644 index 0000000000..0b3317c231 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h | |||
@@ -0,0 +1,521 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__I2C__H__ | ||
24 | #define __HEADERGEN__STMP3600__I2C__H__ | ||
25 | |||
26 | #define REGS_I2C_BASE (0x80058000) | ||
27 | |||
28 | #define REGS_I2C_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_I2C_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_I2C_CTRL0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0)) | ||
36 | #define HW_I2C_CTRL0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4)) | ||
37 | #define HW_I2C_CTRL0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8)) | ||
38 | #define HW_I2C_CTRL0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc)) | ||
39 | #define BP_I2C_CTRL0_SFTRST 31 | ||
40 | #define BM_I2C_CTRL0_SFTRST 0x80000000 | ||
41 | #define BV_I2C_CTRL0_SFTRST__RUN 0x0 | ||
42 | #define BV_I2C_CTRL0_SFTRST__RESET 0x1 | ||
43 | #define BF_I2C_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_I2C_CTRL0_SFTRST_V(v) ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_I2C_CTRL0_CLKGATE 30 | ||
46 | #define BM_I2C_CTRL0_CLKGATE 0x40000000 | ||
47 | #define BV_I2C_CTRL0_CLKGATE__RUN 0x0 | ||
48 | #define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_I2C_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_I2C_CTRL0_CLKGATE_V(v) ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_I2C_CTRL0_RUN 29 | ||
52 | #define BM_I2C_CTRL0_RUN 0x20000000 | ||
53 | #define BV_I2C_CTRL0_RUN__HALT 0x0 | ||
54 | #define BV_I2C_CTRL0_RUN__RUN 0x1 | ||
55 | #define BF_I2C_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_I2C_CTRL0_RUN_V(v) ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000) | ||
57 | #define BP_I2C_CTRL0_PRE_ACK 27 | ||
58 | #define BM_I2C_CTRL0_PRE_ACK 0x8000000 | ||
59 | #define BF_I2C_CTRL0_PRE_ACK(v) (((v) << 27) & 0x8000000) | ||
60 | #define BP_I2C_CTRL0_ACKNOWLEDGE 26 | ||
61 | #define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000 | ||
62 | #define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 | ||
63 | #define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 | ||
64 | #define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) << 26) & 0x4000000) | ||
65 | #define BF_I2C_CTRL0_ACKNOWLEDGE_V(v) ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000) | ||
66 | #define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25 | ||
67 | #define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000 | ||
68 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 | ||
69 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 | ||
70 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) << 25) & 0x2000000) | ||
71 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000) | ||
72 | #define BP_I2C_CTRL0_PIO_MODE 24 | ||
73 | #define BM_I2C_CTRL0_PIO_MODE 0x1000000 | ||
74 | #define BF_I2C_CTRL0_PIO_MODE(v) (((v) << 24) & 0x1000000) | ||
75 | #define BP_I2C_CTRL0_MULTI_MASTER 23 | ||
76 | #define BM_I2C_CTRL0_MULTI_MASTER 0x800000 | ||
77 | #define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 | ||
78 | #define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 | ||
79 | #define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) << 23) & 0x800000) | ||
80 | #define BF_I2C_CTRL0_MULTI_MASTER_V(v) ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000) | ||
81 | #define BP_I2C_CTRL0_CLOCK_HELD 22 | ||
82 | #define BM_I2C_CTRL0_CLOCK_HELD 0x400000 | ||
83 | #define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 | ||
84 | #define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 | ||
85 | #define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) << 22) & 0x400000) | ||
86 | #define BF_I2C_CTRL0_CLOCK_HELD_V(v) ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000) | ||
87 | #define BP_I2C_CTRL0_RETAIN_CLOCK 21 | ||
88 | #define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000 | ||
89 | #define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 | ||
90 | #define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 | ||
91 | #define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) << 21) & 0x200000) | ||
92 | #define BF_I2C_CTRL0_RETAIN_CLOCK_V(v) ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000) | ||
93 | #define BP_I2C_CTRL0_POST_SEND_STOP 20 | ||
94 | #define BM_I2C_CTRL0_POST_SEND_STOP 0x100000 | ||
95 | #define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 | ||
96 | #define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 | ||
97 | #define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) << 20) & 0x100000) | ||
98 | #define BF_I2C_CTRL0_POST_SEND_STOP_V(v) ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000) | ||
99 | #define BP_I2C_CTRL0_PRE_SEND_START 19 | ||
100 | #define BM_I2C_CTRL0_PRE_SEND_START 0x80000 | ||
101 | #define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 | ||
102 | #define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 | ||
103 | #define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) << 19) & 0x80000) | ||
104 | #define BF_I2C_CTRL0_PRE_SEND_START_V(v) ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000) | ||
105 | #define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18 | ||
106 | #define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000 | ||
107 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 | ||
108 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 | ||
109 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) << 18) & 0x40000) | ||
110 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000) | ||
111 | #define BP_I2C_CTRL0_MASTER_MODE 17 | ||
112 | #define BM_I2C_CTRL0_MASTER_MODE 0x20000 | ||
113 | #define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 | ||
114 | #define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 | ||
115 | #define BF_I2C_CTRL0_MASTER_MODE(v) (((v) << 17) & 0x20000) | ||
116 | #define BF_I2C_CTRL0_MASTER_MODE_V(v) ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000) | ||
117 | #define BP_I2C_CTRL0_DIRECTION 16 | ||
118 | #define BM_I2C_CTRL0_DIRECTION 0x10000 | ||
119 | #define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 | ||
120 | #define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 | ||
121 | #define BF_I2C_CTRL0_DIRECTION(v) (((v) << 16) & 0x10000) | ||
122 | #define BF_I2C_CTRL0_DIRECTION_V(v) ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000) | ||
123 | #define BP_I2C_CTRL0_XFER_COUNT 0 | ||
124 | #define BM_I2C_CTRL0_XFER_COUNT 0xffff | ||
125 | #define BF_I2C_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
126 | |||
127 | /** | ||
128 | * Register: HW_I2C_TIMING0 | ||
129 | * Address: 0x10 | ||
130 | * SCT: yes | ||
131 | */ | ||
132 | #define HW_I2C_TIMING0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0)) | ||
133 | #define HW_I2C_TIMING0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4)) | ||
134 | #define HW_I2C_TIMING0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8)) | ||
135 | #define HW_I2C_TIMING0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc)) | ||
136 | #define BP_I2C_TIMING0_HIGH_COUNT 16 | ||
137 | #define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000 | ||
138 | #define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
139 | #define BP_I2C_TIMING0_RCV_COUNT 0 | ||
140 | #define BM_I2C_TIMING0_RCV_COUNT 0x3ff | ||
141 | #define BF_I2C_TIMING0_RCV_COUNT(v) (((v) << 0) & 0x3ff) | ||
142 | |||
143 | /** | ||
144 | * Register: HW_I2C_TIMING1 | ||
145 | * Address: 0x20 | ||
146 | * SCT: yes | ||
147 | */ | ||
148 | #define HW_I2C_TIMING1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0)) | ||
149 | #define HW_I2C_TIMING1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4)) | ||
150 | #define HW_I2C_TIMING1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8)) | ||
151 | #define HW_I2C_TIMING1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc)) | ||
152 | #define BP_I2C_TIMING1_LOW_COUNT 16 | ||
153 | #define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000 | ||
154 | #define BF_I2C_TIMING1_LOW_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
155 | #define BP_I2C_TIMING1_XMIT_COUNT 0 | ||
156 | #define BM_I2C_TIMING1_XMIT_COUNT 0x3ff | ||
157 | #define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) << 0) & 0x3ff) | ||
158 | |||
159 | /** | ||
160 | * Register: HW_I2C_TIMING2 | ||
161 | * Address: 0x30 | ||
162 | * SCT: yes | ||
163 | */ | ||
164 | #define HW_I2C_TIMING2 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0)) | ||
165 | #define HW_I2C_TIMING2_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4)) | ||
166 | #define HW_I2C_TIMING2_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8)) | ||
167 | #define HW_I2C_TIMING2_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc)) | ||
168 | #define BP_I2C_TIMING2_BUS_FREE 16 | ||
169 | #define BM_I2C_TIMING2_BUS_FREE 0x3ff0000 | ||
170 | #define BF_I2C_TIMING2_BUS_FREE(v) (((v) << 16) & 0x3ff0000) | ||
171 | #define BP_I2C_TIMING2_LEADIN_COUNT 0 | ||
172 | #define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff | ||
173 | #define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) << 0) & 0x3ff) | ||
174 | |||
175 | /** | ||
176 | * Register: HW_I2C_CTRL1 | ||
177 | * Address: 0x40 | ||
178 | * SCT: yes | ||
179 | */ | ||
180 | #define HW_I2C_CTRL1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0)) | ||
181 | #define HW_I2C_CTRL1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4)) | ||
182 | #define HW_I2C_CTRL1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8)) | ||
183 | #define HW_I2C_CTRL1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc)) | ||
184 | #define BP_I2C_CTRL1_BCAST_SLAVE_EN 24 | ||
185 | #define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000 | ||
186 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 | ||
187 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 | ||
188 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) << 24) & 0x1000000) | ||
189 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v) ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000) | ||
190 | #define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 | ||
191 | #define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000 | ||
192 | #define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) << 16) & 0xff0000) | ||
193 | #define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15 | ||
194 | #define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000 | ||
195 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 | ||
196 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 | ||
197 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
198 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000) | ||
199 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14 | ||
200 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000 | ||
201 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 | ||
202 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 | ||
203 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
204 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000) | ||
205 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13 | ||
206 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000 | ||
207 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 | ||
208 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 | ||
209 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
210 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000) | ||
211 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12 | ||
212 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000 | ||
213 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 | ||
214 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 | ||
215 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
216 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000) | ||
217 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11 | ||
218 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800 | ||
219 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 | ||
220 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 | ||
221 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) << 11) & 0x800) | ||
222 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800) | ||
223 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10 | ||
224 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400 | ||
225 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 | ||
226 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 | ||
227 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
228 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
229 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9 | ||
230 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200 | ||
231 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 | ||
232 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 | ||
233 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) << 9) & 0x200) | ||
234 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200) | ||
235 | #define BP_I2C_CTRL1_SLAVE_IRQ_EN 8 | ||
236 | #define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100 | ||
237 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 | ||
238 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 | ||
239 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
240 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100) | ||
241 | #define BP_I2C_CTRL1_BUS_FREE_IRQ 7 | ||
242 | #define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80 | ||
243 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 | ||
244 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 | ||
245 | #define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) << 7) & 0x80) | ||
246 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80) | ||
247 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6 | ||
248 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | ||
249 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 | ||
250 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 | ||
251 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) << 6) & 0x40) | ||
252 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40) | ||
253 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5 | ||
254 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | ||
255 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 | ||
256 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 | ||
257 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) << 5) & 0x20) | ||
258 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20) | ||
259 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4 | ||
260 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | ||
261 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 | ||
262 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 | ||
263 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) << 4) & 0x10) | ||
264 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10) | ||
265 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ 3 | ||
266 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8 | ||
267 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 | ||
268 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 | ||
269 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) << 3) & 0x8) | ||
270 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8) | ||
271 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2 | ||
272 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4 | ||
273 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 | ||
274 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 | ||
275 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
276 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4) | ||
277 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1 | ||
278 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2 | ||
279 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 | ||
280 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 | ||
281 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) << 1) & 0x2) | ||
282 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2) | ||
283 | #define BP_I2C_CTRL1_SLAVE_IRQ 0 | ||
284 | #define BM_I2C_CTRL1_SLAVE_IRQ 0x1 | ||
285 | #define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 | ||
286 | #define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 | ||
287 | #define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) << 0) & 0x1) | ||
288 | #define BF_I2C_CTRL1_SLAVE_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1) | ||
289 | |||
290 | /** | ||
291 | * Register: HW_I2C_STAT | ||
292 | * Address: 0x50 | ||
293 | * SCT: no | ||
294 | */ | ||
295 | #define HW_I2C_STAT (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50)) | ||
296 | #define BP_I2C_STAT_MASTER_PRESENT 31 | ||
297 | #define BM_I2C_STAT_MASTER_PRESENT 0x80000000 | ||
298 | #define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 | ||
299 | #define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 | ||
300 | #define BF_I2C_STAT_MASTER_PRESENT(v) (((v) << 31) & 0x80000000) | ||
301 | #define BF_I2C_STAT_MASTER_PRESENT_V(v) ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000) | ||
302 | #define BP_I2C_STAT_SLAVE_PRESENT 30 | ||
303 | #define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 | ||
304 | #define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 | ||
305 | #define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 | ||
306 | #define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) << 30) & 0x40000000) | ||
307 | #define BF_I2C_STAT_SLAVE_PRESENT_V(v) ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000) | ||
308 | #define BP_I2C_STAT_ANY_ENABLED_IRQ 29 | ||
309 | #define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 | ||
310 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 | ||
311 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 | ||
312 | #define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) << 29) & 0x20000000) | ||
313 | #define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v) ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000) | ||
314 | #define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 | ||
315 | #define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000 | ||
316 | #define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) << 16) & 0xff0000) | ||
317 | #define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15 | ||
318 | #define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000 | ||
319 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 | ||
320 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 | ||
321 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) << 15) & 0x8000) | ||
322 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000) | ||
323 | #define BP_I2C_STAT_SLAVE_FOUND 14 | ||
324 | #define BM_I2C_STAT_SLAVE_FOUND 0x4000 | ||
325 | #define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 | ||
326 | #define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 | ||
327 | #define BF_I2C_STAT_SLAVE_FOUND(v) (((v) << 14) & 0x4000) | ||
328 | #define BF_I2C_STAT_SLAVE_FOUND_V(v) ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000) | ||
329 | #define BP_I2C_STAT_SLAVE_SEARCHING 13 | ||
330 | #define BM_I2C_STAT_SLAVE_SEARCHING 0x2000 | ||
331 | #define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 | ||
332 | #define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 | ||
333 | #define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) << 13) & 0x2000) | ||
334 | #define BF_I2C_STAT_SLAVE_SEARCHING_V(v) ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000) | ||
335 | #define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12 | ||
336 | #define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000 | ||
337 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 | ||
338 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 | ||
339 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) << 12) & 0x1000) | ||
340 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000) | ||
341 | #define BP_I2C_STAT_BUS_BUSY 11 | ||
342 | #define BM_I2C_STAT_BUS_BUSY 0x800 | ||
343 | #define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 | ||
344 | #define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 | ||
345 | #define BF_I2C_STAT_BUS_BUSY(v) (((v) << 11) & 0x800) | ||
346 | #define BF_I2C_STAT_BUS_BUSY_V(v) ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800) | ||
347 | #define BP_I2C_STAT_CLK_GEN_BUSY 10 | ||
348 | #define BM_I2C_STAT_CLK_GEN_BUSY 0x400 | ||
349 | #define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 | ||
350 | #define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 | ||
351 | #define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) << 10) & 0x400) | ||
352 | #define BF_I2C_STAT_CLK_GEN_BUSY_V(v) ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400) | ||
353 | #define BP_I2C_STAT_DATA_ENGINE_BUSY 9 | ||
354 | #define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200 | ||
355 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 | ||
356 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 | ||
357 | #define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) << 9) & 0x200) | ||
358 | #define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v) ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200) | ||
359 | #define BP_I2C_STAT_SLAVE_BUSY 8 | ||
360 | #define BM_I2C_STAT_SLAVE_BUSY 0x100 | ||
361 | #define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 | ||
362 | #define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 | ||
363 | #define BF_I2C_STAT_SLAVE_BUSY(v) (((v) << 8) & 0x100) | ||
364 | #define BF_I2C_STAT_SLAVE_BUSY_V(v) ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100) | ||
365 | #define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7 | ||
366 | #define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80 | ||
367 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
368 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 | ||
369 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) << 7) & 0x80) | ||
370 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80) | ||
371 | #define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6 | ||
372 | #define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40 | ||
373 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
374 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 | ||
375 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) << 6) & 0x40) | ||
376 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40) | ||
377 | #define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5 | ||
378 | #define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20 | ||
379 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
380 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 | ||
381 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) << 5) & 0x20) | ||
382 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20) | ||
383 | #define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4 | ||
384 | #define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10 | ||
385 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
386 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
387 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) << 4) & 0x10) | ||
388 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10) | ||
389 | #define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3 | ||
390 | #define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8 | ||
391 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
392 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
393 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
394 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8) | ||
395 | #define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2 | ||
396 | #define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4 | ||
397 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
398 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
399 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
400 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
401 | #define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1 | ||
402 | #define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2 | ||
403 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
404 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 | ||
405 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
406 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2) | ||
407 | #define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0 | ||
408 | #define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1 | ||
409 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
410 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 | ||
411 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) << 0) & 0x1) | ||
412 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1) | ||
413 | |||
414 | /** | ||
415 | * Register: HW_I2C_DATA | ||
416 | * Address: 0x60 | ||
417 | * SCT: no | ||
418 | */ | ||
419 | #define HW_I2C_DATA (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60)) | ||
420 | #define BP_I2C_DATA_DATA 0 | ||
421 | #define BM_I2C_DATA_DATA 0xffffffff | ||
422 | #define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
423 | |||
424 | /** | ||
425 | * Register: HW_I2C_DEBUG0 | ||
426 | * Address: 0x70 | ||
427 | * SCT: yes | ||
428 | */ | ||
429 | #define HW_I2C_DEBUG0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0)) | ||
430 | #define HW_I2C_DEBUG0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4)) | ||
431 | #define HW_I2C_DEBUG0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8)) | ||
432 | #define HW_I2C_DEBUG0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc)) | ||
433 | #define BP_I2C_DEBUG0_DMAREQ 31 | ||
434 | #define BM_I2C_DEBUG0_DMAREQ 0x80000000 | ||
435 | #define BF_I2C_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
436 | #define BP_I2C_DEBUG0_DMAENDCMD 30 | ||
437 | #define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 | ||
438 | #define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) << 30) & 0x40000000) | ||
439 | #define BP_I2C_DEBUG0_DMAKICK 29 | ||
440 | #define BM_I2C_DEBUG0_DMAKICK 0x20000000 | ||
441 | #define BF_I2C_DEBUG0_DMAKICK(v) (((v) << 29) & 0x20000000) | ||
442 | #define BP_I2C_DEBUG0_TBD 26 | ||
443 | #define BM_I2C_DEBUG0_TBD 0x1c000000 | ||
444 | #define BF_I2C_DEBUG0_TBD(v) (((v) << 26) & 0x1c000000) | ||
445 | #define BP_I2C_DEBUG0_DMA_STATE 16 | ||
446 | #define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000 | ||
447 | #define BF_I2C_DEBUG0_DMA_STATE(v) (((v) << 16) & 0x3ff0000) | ||
448 | #define BP_I2C_DEBUG0_START_TOGGLE 15 | ||
449 | #define BM_I2C_DEBUG0_START_TOGGLE 0x8000 | ||
450 | #define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) << 15) & 0x8000) | ||
451 | #define BP_I2C_DEBUG0_STOP_TOGGLE 14 | ||
452 | #define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000 | ||
453 | #define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) << 14) & 0x4000) | ||
454 | #define BP_I2C_DEBUG0_GRAB_TOGGLE 13 | ||
455 | #define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000 | ||
456 | #define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) << 13) & 0x2000) | ||
457 | #define BP_I2C_DEBUG0_CHANGE_TOGGLE 12 | ||
458 | #define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000 | ||
459 | #define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) << 12) & 0x1000) | ||
460 | #define BP_I2C_DEBUG0_TESTMODE 11 | ||
461 | #define BM_I2C_DEBUG0_TESTMODE 0x800 | ||
462 | #define BF_I2C_DEBUG0_TESTMODE(v) (((v) << 11) & 0x800) | ||
463 | #define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10 | ||
464 | #define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400 | ||
465 | #define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400) | ||
466 | #define BP_I2C_DEBUG0_SLAVE_STATE 0 | ||
467 | #define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff | ||
468 | #define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) << 0) & 0x3ff) | ||
469 | |||
470 | /** | ||
471 | * Register: HW_I2C_DEBUG1 | ||
472 | * Address: 0x80 | ||
473 | * SCT: yes | ||
474 | */ | ||
475 | #define HW_I2C_DEBUG1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0)) | ||
476 | #define HW_I2C_DEBUG1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4)) | ||
477 | #define HW_I2C_DEBUG1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8)) | ||
478 | #define HW_I2C_DEBUG1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc)) | ||
479 | #define BP_I2C_DEBUG1_I2C_CLK_IN 31 | ||
480 | #define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 | ||
481 | #define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) << 31) & 0x80000000) | ||
482 | #define BP_I2C_DEBUG1_I2C_DATA_IN 30 | ||
483 | #define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 | ||
484 | #define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) << 30) & 0x40000000) | ||
485 | #define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 | ||
486 | #define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000 | ||
487 | #define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) << 24) & 0xf000000) | ||
488 | #define BP_I2C_DEBUG1_CLK_GEN_STATE 16 | ||
489 | #define BM_I2C_DEBUG1_CLK_GEN_STATE 0x7f0000 | ||
490 | #define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) << 16) & 0x7f0000) | ||
491 | #define BP_I2C_DEBUG1_LST_MODE 9 | ||
492 | #define BM_I2C_DEBUG1_LST_MODE 0x600 | ||
493 | #define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 | ||
494 | #define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 | ||
495 | #define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 | ||
496 | #define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 | ||
497 | #define BF_I2C_DEBUG1_LST_MODE(v) (((v) << 9) & 0x600) | ||
498 | #define BF_I2C_DEBUG1_LST_MODE_V(v) ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600) | ||
499 | #define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8 | ||
500 | #define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100 | ||
501 | #define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) << 8) & 0x100) | ||
502 | #define BP_I2C_DEBUG1_FORCE_CLK_ON 5 | ||
503 | #define BM_I2C_DEBUG1_FORCE_CLK_ON 0x20 | ||
504 | #define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) << 5) & 0x20) | ||
505 | #define BP_I2C_DEBUG1_FORCE_CLK_IDLE 4 | ||
506 | #define BM_I2C_DEBUG1_FORCE_CLK_IDLE 0x10 | ||
507 | #define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v) (((v) << 4) & 0x10) | ||
508 | #define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3 | ||
509 | #define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8 | ||
510 | #define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) << 3) & 0x8) | ||
511 | #define BP_I2C_DEBUG1_FORCE_RCV_ACK 2 | ||
512 | #define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4 | ||
513 | #define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) << 2) & 0x4) | ||
514 | #define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1 | ||
515 | #define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2 | ||
516 | #define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) << 1) & 0x2) | ||
517 | #define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0 | ||
518 | #define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1 | ||
519 | #define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) << 0) & 0x1) | ||
520 | |||
521 | #endif /* __HEADERGEN__STMP3600__I2C__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h new file mode 100644 index 0000000000..130ab2ca17 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h | |||
@@ -0,0 +1,348 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__ICOLL__H__ | ||
24 | #define __HEADERGEN__STMP3600__ICOLL__H__ | ||
25 | |||
26 | #define REGS_ICOLL_BASE (0x80000000) | ||
27 | |||
28 | #define REGS_ICOLL_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ICOLL_VECTOR | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_ICOLL_VECTOR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_ICOLL_VECTOR_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_ICOLL_VECTOR_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_ICOLL_VECTOR_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_ICOLL_VECTOR_IRQVECTOR 2 | ||
40 | #define BM_ICOLL_VECTOR_IRQVECTOR 0xfffffffc | ||
41 | #define BF_ICOLL_VECTOR_IRQVECTOR(v) (((v) << 2) & 0xfffffffc) | ||
42 | |||
43 | /** | ||
44 | * Register: HW_ICOLL_LEVELACK | ||
45 | * Address: 0x10 | ||
46 | * SCT: no | ||
47 | */ | ||
48 | #define HW_ICOLL_LEVELACK (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10)) | ||
49 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 | ||
50 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0xf | ||
51 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | ||
52 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 | ||
53 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 | ||
54 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 | ||
55 | #define BF_ICOLL_LEVELACK_IRQLEVELACK(v) (((v) << 0) & 0xf) | ||
56 | #define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v) ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_ICOLL_CTRL | ||
60 | * Address: 0x20 | ||
61 | * SCT: yes | ||
62 | */ | ||
63 | #define HW_ICOLL_CTRL (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0)) | ||
64 | #define HW_ICOLL_CTRL_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4)) | ||
65 | #define HW_ICOLL_CTRL_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8)) | ||
66 | #define HW_ICOLL_CTRL_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc)) | ||
67 | #define BP_ICOLL_CTRL_SFTRST 31 | ||
68 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 | ||
69 | #define BV_ICOLL_CTRL_SFTRST__RUN 0x0 | ||
70 | #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 | ||
71 | #define BF_ICOLL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
72 | #define BF_ICOLL_CTRL_SFTRST_V(v) ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
73 | #define BP_ICOLL_CTRL_CLKGATE 30 | ||
74 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 | ||
75 | #define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 | ||
76 | #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 | ||
77 | #define BF_ICOLL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
78 | #define BF_ICOLL_CTRL_CLKGATE_V(v) ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
79 | #define BP_ICOLL_CTRL_ENABLE2FIQ35 27 | ||
80 | #define BM_ICOLL_CTRL_ENABLE2FIQ35 0x8000000 | ||
81 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE 0x0 | ||
82 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE 0x1 | ||
83 | #define BF_ICOLL_CTRL_ENABLE2FIQ35(v) (((v) << 27) & 0x8000000) | ||
84 | #define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 27) & 0x8000000) | ||
85 | #define BP_ICOLL_CTRL_ENABLE2FIQ34 26 | ||
86 | #define BM_ICOLL_CTRL_ENABLE2FIQ34 0x4000000 | ||
87 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE 0x0 | ||
88 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE 0x1 | ||
89 | #define BF_ICOLL_CTRL_ENABLE2FIQ34(v) (((v) << 26) & 0x4000000) | ||
90 | #define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 26) & 0x4000000) | ||
91 | #define BP_ICOLL_CTRL_ENABLE2FIQ33 25 | ||
92 | #define BM_ICOLL_CTRL_ENABLE2FIQ33 0x2000000 | ||
93 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE 0x0 | ||
94 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE 0x1 | ||
95 | #define BF_ICOLL_CTRL_ENABLE2FIQ33(v) (((v) << 25) & 0x2000000) | ||
96 | #define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 25) & 0x2000000) | ||
97 | #define BP_ICOLL_CTRL_ENABLE2FIQ32 24 | ||
98 | #define BM_ICOLL_CTRL_ENABLE2FIQ32 0x1000000 | ||
99 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE 0x0 | ||
100 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE 0x1 | ||
101 | #define BF_ICOLL_CTRL_ENABLE2FIQ32(v) (((v) << 24) & 0x1000000) | ||
102 | #define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 24) & 0x1000000) | ||
103 | #define BP_ICOLL_CTRL_BYPASS_FSM 20 | ||
104 | #define BM_ICOLL_CTRL_BYPASS_FSM 0x100000 | ||
105 | #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 | ||
106 | #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 | ||
107 | #define BF_ICOLL_CTRL_BYPASS_FSM(v) (((v) << 20) & 0x100000) | ||
108 | #define BF_ICOLL_CTRL_BYPASS_FSM_V(v) ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000) | ||
109 | #define BP_ICOLL_CTRL_NO_NESTING 19 | ||
110 | #define BM_ICOLL_CTRL_NO_NESTING 0x80000 | ||
111 | #define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 | ||
112 | #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 | ||
113 | #define BF_ICOLL_CTRL_NO_NESTING(v) (((v) << 19) & 0x80000) | ||
114 | #define BF_ICOLL_CTRL_NO_NESTING_V(v) ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000) | ||
115 | #define BP_ICOLL_CTRL_ARM_RSE_MODE 18 | ||
116 | #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x40000 | ||
117 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE 0x0 | ||
118 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT 0x1 | ||
119 | #define BF_ICOLL_CTRL_ARM_RSE_MODE(v) (((v) << 18) & 0x40000) | ||
120 | #define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v) ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000) | ||
121 | #define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE 17 | ||
122 | #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x20000 | ||
123 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 | ||
124 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 | ||
125 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v) (((v) << 17) & 0x20000) | ||
126 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000) | ||
127 | #define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE 16 | ||
128 | #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x10000 | ||
129 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 | ||
130 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 | ||
131 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v) (((v) << 16) & 0x10000) | ||
132 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000) | ||
133 | |||
134 | /** | ||
135 | * Register: HW_ICOLL_STAT | ||
136 | * Address: 0x30 | ||
137 | * SCT: no | ||
138 | */ | ||
139 | #define HW_ICOLL_STAT (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30)) | ||
140 | #define BP_ICOLL_STAT_VECTOR_NUMBER 0 | ||
141 | #define BM_ICOLL_STAT_VECTOR_NUMBER 0x3f | ||
142 | #define BF_ICOLL_STAT_VECTOR_NUMBER(v) (((v) << 0) & 0x3f) | ||
143 | |||
144 | /** | ||
145 | * Register: HW_ICOLL_VBASE | ||
146 | * Address: 0x160 | ||
147 | * SCT: yes | ||
148 | */ | ||
149 | #define HW_ICOLL_VBASE (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0)) | ||
150 | #define HW_ICOLL_VBASE_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4)) | ||
151 | #define HW_ICOLL_VBASE_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8)) | ||
152 | #define HW_ICOLL_VBASE_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc)) | ||
153 | #define BP_ICOLL_VBASE_TABLE_ADDRESS 2 | ||
154 | #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xfffffffc | ||
155 | #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
156 | |||
157 | /** | ||
158 | * Register: HW_ICOLL_DEBUG | ||
159 | * Address: 0x170 | ||
160 | * SCT: no | ||
161 | */ | ||
162 | #define HW_ICOLL_DEBUG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170)) | ||
163 | #define BP_ICOLL_DEBUG_INSERVICE 28 | ||
164 | #define BM_ICOLL_DEBUG_INSERVICE 0xf0000000 | ||
165 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 | ||
166 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 | ||
167 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 | ||
168 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 | ||
169 | #define BF_ICOLL_DEBUG_INSERVICE(v) (((v) << 28) & 0xf0000000) | ||
170 | #define BF_ICOLL_DEBUG_INSERVICE_V(v) ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000) | ||
171 | #define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 | ||
172 | #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0xf000000 | ||
173 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 | ||
174 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 | ||
175 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 | ||
176 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 | ||
177 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) (((v) << 24) & 0xf000000) | ||
178 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v) ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000) | ||
179 | #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 | ||
180 | #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0xf00000 | ||
181 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 | ||
182 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 | ||
183 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 | ||
184 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 | ||
185 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) (((v) << 20) & 0xf00000) | ||
186 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v) ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000) | ||
187 | #define BP_ICOLL_DEBUG_FIQ 17 | ||
188 | #define BM_ICOLL_DEBUG_FIQ 0x20000 | ||
189 | #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 | ||
190 | #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 | ||
191 | #define BF_ICOLL_DEBUG_FIQ(v) (((v) << 17) & 0x20000) | ||
192 | #define BF_ICOLL_DEBUG_FIQ_V(v) ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000) | ||
193 | #define BP_ICOLL_DEBUG_IRQ 16 | ||
194 | #define BM_ICOLL_DEBUG_IRQ 0x10000 | ||
195 | #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 | ||
196 | #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 | ||
197 | #define BF_ICOLL_DEBUG_IRQ(v) (((v) << 16) & 0x10000) | ||
198 | #define BF_ICOLL_DEBUG_IRQ_V(v) ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000) | ||
199 | #define BP_ICOLL_DEBUG_VECTOR_FSM 0 | ||
200 | #define BM_ICOLL_DEBUG_VECTOR_FSM 0x3ff | ||
201 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x0 | ||
202 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x1 | ||
203 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x2 | ||
204 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x4 | ||
205 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x8 | ||
206 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x10 | ||
207 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20 | ||
208 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40 | ||
209 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80 | ||
210 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 | ||
211 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 | ||
212 | #define BF_ICOLL_DEBUG_VECTOR_FSM(v) (((v) << 0) & 0x3ff) | ||
213 | #define BF_ICOLL_DEBUG_VECTOR_FSM_V(v) ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff) | ||
214 | |||
215 | /** | ||
216 | * Register: HW_ICOLL_DBGFLAG | ||
217 | * Address: 0x1a0 | ||
218 | * SCT: yes | ||
219 | */ | ||
220 | #define HW_ICOLL_DBGFLAG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0)) | ||
221 | #define HW_ICOLL_DBGFLAG_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4)) | ||
222 | #define HW_ICOLL_DBGFLAG_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8)) | ||
223 | #define HW_ICOLL_DBGFLAG_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc)) | ||
224 | #define BP_ICOLL_DBGFLAG_FLAG 0 | ||
225 | #define BM_ICOLL_DBGFLAG_FLAG 0xffff | ||
226 | #define BF_ICOLL_DBGFLAG_FLAG(v) (((v) << 0) & 0xffff) | ||
227 | |||
228 | /** | ||
229 | * Register: HW_ICOLL_DBGREQUESTn | ||
230 | * Address: 0x1b0+n*0x10 | ||
231 | * SCT: no | ||
232 | */ | ||
233 | #define HW_ICOLL_DBGREQUESTn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10)) | ||
234 | #define BP_ICOLL_DBGREQUESTn_BITS 0 | ||
235 | #define BM_ICOLL_DBGREQUESTn_BITS 0xffffffff | ||
236 | #define BF_ICOLL_DBGREQUESTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
237 | |||
238 | /** | ||
239 | * Register: HW_ICOLL_RAWn | ||
240 | * Address: 0x40+n*0x10 | ||
241 | * SCT: no | ||
242 | */ | ||
243 | #define HW_ICOLL_RAWn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10)) | ||
244 | #define BP_ICOLL_RAWn_RAW_IRQS 0 | ||
245 | #define BM_ICOLL_RAWn_RAW_IRQS 0xffffffff | ||
246 | #define BF_ICOLL_RAWn_RAW_IRQS(v) (((v) << 0) & 0xffffffff) | ||
247 | |||
248 | /** | ||
249 | * Register: HW_ICOLL_DBGREADn | ||
250 | * Address: 0x180+n*0x10 | ||
251 | * SCT: no | ||
252 | */ | ||
253 | #define HW_ICOLL_DBGREADn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180+(n)*0x10)) | ||
254 | #define BP_ICOLL_DBGREADn_VALUE 0 | ||
255 | #define BM_ICOLL_DBGREADn_VALUE 0xffffffff | ||
256 | #define BF_ICOLL_DBGREADn_VALUE(v) (((v) << 0) & 0xffffffff) | ||
257 | |||
258 | /** | ||
259 | * Register: HW_ICOLL_PRIORITYn | ||
260 | * Address: 0x60+n*0x10 | ||
261 | * SCT: yes | ||
262 | */ | ||
263 | #define HW_ICOLL_PRIORITYn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0)) | ||
264 | #define HW_ICOLL_PRIORITYn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4)) | ||
265 | #define HW_ICOLL_PRIORITYn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8)) | ||
266 | #define HW_ICOLL_PRIORITYn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc)) | ||
267 | #define BP_ICOLL_PRIORITYn_SOFTIRQ3 27 | ||
268 | #define BM_ICOLL_PRIORITYn_SOFTIRQ3 0x8000000 | ||
269 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT 0x0 | ||
270 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT 0x1 | ||
271 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3(v) (((v) << 27) & 0x8000000) | ||
272 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000) | ||
273 | #define BP_ICOLL_PRIORITYn_ENABLE3 26 | ||
274 | #define BM_ICOLL_PRIORITYn_ENABLE3 0x4000000 | ||
275 | #define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE 0x0 | ||
276 | #define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE 0x1 | ||
277 | #define BF_ICOLL_PRIORITYn_ENABLE3(v) (((v) << 26) & 0x4000000) | ||
278 | #define BF_ICOLL_PRIORITYn_ENABLE3_V(v) ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000) | ||
279 | #define BP_ICOLL_PRIORITYn_PRIORITY3 24 | ||
280 | #define BM_ICOLL_PRIORITYn_PRIORITY3 0x3000000 | ||
281 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0 0x0 | ||
282 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1 0x1 | ||
283 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2 0x2 | ||
284 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3 0x3 | ||
285 | #define BF_ICOLL_PRIORITYn_PRIORITY3(v) (((v) << 24) & 0x3000000) | ||
286 | #define BF_ICOLL_PRIORITYn_PRIORITY3_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000) | ||
287 | #define BP_ICOLL_PRIORITYn_SOFTIRQ2 19 | ||
288 | #define BM_ICOLL_PRIORITYn_SOFTIRQ2 0x80000 | ||
289 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT 0x0 | ||
290 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT 0x1 | ||
291 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2(v) (((v) << 19) & 0x80000) | ||
292 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000) | ||
293 | #define BP_ICOLL_PRIORITYn_ENABLE2 18 | ||
294 | #define BM_ICOLL_PRIORITYn_ENABLE2 0x40000 | ||
295 | #define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE 0x0 | ||
296 | #define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE 0x1 | ||
297 | #define BF_ICOLL_PRIORITYn_ENABLE2(v) (((v) << 18) & 0x40000) | ||
298 | #define BF_ICOLL_PRIORITYn_ENABLE2_V(v) ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000) | ||
299 | #define BP_ICOLL_PRIORITYn_PRIORITY2 16 | ||
300 | #define BM_ICOLL_PRIORITYn_PRIORITY2 0x30000 | ||
301 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0 0x0 | ||
302 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1 0x1 | ||
303 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2 0x2 | ||
304 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3 0x3 | ||
305 | #define BF_ICOLL_PRIORITYn_PRIORITY2(v) (((v) << 16) & 0x30000) | ||
306 | #define BF_ICOLL_PRIORITYn_PRIORITY2_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000) | ||
307 | #define BP_ICOLL_PRIORITYn_SOFTIRQ1 11 | ||
308 | #define BM_ICOLL_PRIORITYn_SOFTIRQ1 0x800 | ||
309 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT 0x0 | ||
310 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT 0x1 | ||
311 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1(v) (((v) << 11) & 0x800) | ||
312 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800) | ||
313 | #define BP_ICOLL_PRIORITYn_ENABLE1 10 | ||
314 | #define BM_ICOLL_PRIORITYn_ENABLE1 0x400 | ||
315 | #define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE 0x0 | ||
316 | #define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE 0x1 | ||
317 | #define BF_ICOLL_PRIORITYn_ENABLE1(v) (((v) << 10) & 0x400) | ||
318 | #define BF_ICOLL_PRIORITYn_ENABLE1_V(v) ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400) | ||
319 | #define BP_ICOLL_PRIORITYn_PRIORITY1 8 | ||
320 | #define BM_ICOLL_PRIORITYn_PRIORITY1 0x300 | ||
321 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0 0x0 | ||
322 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1 0x1 | ||
323 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2 0x2 | ||
324 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3 0x3 | ||
325 | #define BF_ICOLL_PRIORITYn_PRIORITY1(v) (((v) << 8) & 0x300) | ||
326 | #define BF_ICOLL_PRIORITYn_PRIORITY1_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300) | ||
327 | #define BP_ICOLL_PRIORITYn_SOFTIRQ0 3 | ||
328 | #define BM_ICOLL_PRIORITYn_SOFTIRQ0 0x8 | ||
329 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT 0x0 | ||
330 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT 0x1 | ||
331 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0(v) (((v) << 3) & 0x8) | ||
332 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8) | ||
333 | #define BP_ICOLL_PRIORITYn_ENABLE0 2 | ||
334 | #define BM_ICOLL_PRIORITYn_ENABLE0 0x4 | ||
335 | #define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE 0x0 | ||
336 | #define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE 0x1 | ||
337 | #define BF_ICOLL_PRIORITYn_ENABLE0(v) (((v) << 2) & 0x4) | ||
338 | #define BF_ICOLL_PRIORITYn_ENABLE0_V(v) ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4) | ||
339 | #define BP_ICOLL_PRIORITYn_PRIORITY0 0 | ||
340 | #define BM_ICOLL_PRIORITYn_PRIORITY0 0x3 | ||
341 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0 0x0 | ||
342 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1 0x1 | ||
343 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2 0x2 | ||
344 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3 0x3 | ||
345 | #define BF_ICOLL_PRIORITYn_PRIORITY0(v) (((v) << 0) & 0x3) | ||
346 | #define BF_ICOLL_PRIORITYn_PRIORITY0_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3) | ||
347 | |||
348 | #endif /* __HEADERGEN__STMP3600__ICOLL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h new file mode 100644 index 0000000000..56eeabaaa3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h | |||
@@ -0,0 +1,477 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__IR__H__ | ||
24 | #define __HEADERGEN__STMP3600__IR__H__ | ||
25 | |||
26 | #define REGS_IR_BASE (0x80078000) | ||
27 | |||
28 | #define REGS_IR_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_IR_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_IR_CTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0)) | ||
36 | #define HW_IR_CTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4)) | ||
37 | #define HW_IR_CTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8)) | ||
38 | #define HW_IR_CTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc)) | ||
39 | #define BP_IR_CTRL_SFTRST 31 | ||
40 | #define BM_IR_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_IR_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_IR_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_IR_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_IR_CTRL_SFTRST_V(v) ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_IR_CTRL_CLKGATE 30 | ||
46 | #define BM_IR_CTRL_CLKGATE 0x40000000 | ||
47 | #define BF_IR_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
48 | #define BP_IR_CTRL_MTA 24 | ||
49 | #define BM_IR_CTRL_MTA 0x7000000 | ||
50 | #define BV_IR_CTRL_MTA__MTA_10MS 0x0 | ||
51 | #define BV_IR_CTRL_MTA__MTA_5MS 0x1 | ||
52 | #define BV_IR_CTRL_MTA__MTA_1MS 0x2 | ||
53 | #define BV_IR_CTRL_MTA__MTA_500US 0x3 | ||
54 | #define BV_IR_CTRL_MTA__MTA_100US 0x4 | ||
55 | #define BV_IR_CTRL_MTA__MTA_50US 0x5 | ||
56 | #define BV_IR_CTRL_MTA__MTA_10US 0x6 | ||
57 | #define BV_IR_CTRL_MTA__MTA_0 0x7 | ||
58 | #define BF_IR_CTRL_MTA(v) (((v) << 24) & 0x7000000) | ||
59 | #define BF_IR_CTRL_MTA_V(v) ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000) | ||
60 | #define BP_IR_CTRL_MODE 22 | ||
61 | #define BM_IR_CTRL_MODE 0xc00000 | ||
62 | #define BV_IR_CTRL_MODE__SIR 0x0 | ||
63 | #define BV_IR_CTRL_MODE__MIR 0x1 | ||
64 | #define BV_IR_CTRL_MODE__FIR 0x2 | ||
65 | #define BV_IR_CTRL_MODE__VFIR 0x3 | ||
66 | #define BF_IR_CTRL_MODE(v) (((v) << 22) & 0xc00000) | ||
67 | #define BF_IR_CTRL_MODE_V(v) ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000) | ||
68 | #define BP_IR_CTRL_SPEED 19 | ||
69 | #define BM_IR_CTRL_SPEED 0x380000 | ||
70 | #define BV_IR_CTRL_SPEED__SPD000 0x0 | ||
71 | #define BV_IR_CTRL_SPEED__SPD001 0x1 | ||
72 | #define BV_IR_CTRL_SPEED__SPD010 0x2 | ||
73 | #define BV_IR_CTRL_SPEED__SPD011 0x3 | ||
74 | #define BV_IR_CTRL_SPEED__SPD100 0x4 | ||
75 | #define BV_IR_CTRL_SPEED__SPD101 0x5 | ||
76 | #define BF_IR_CTRL_SPEED(v) (((v) << 19) & 0x380000) | ||
77 | #define BF_IR_CTRL_SPEED_V(v) ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000) | ||
78 | #define BP_IR_CTRL_TC_TIME_DIV 8 | ||
79 | #define BM_IR_CTRL_TC_TIME_DIV 0x3f00 | ||
80 | #define BF_IR_CTRL_TC_TIME_DIV(v) (((v) << 8) & 0x3f00) | ||
81 | #define BP_IR_CTRL_TC_TYPE 7 | ||
82 | #define BM_IR_CTRL_TC_TYPE 0x80 | ||
83 | #define BF_IR_CTRL_TC_TYPE(v) (((v) << 7) & 0x80) | ||
84 | #define BP_IR_CTRL_SIR_GAP 4 | ||
85 | #define BM_IR_CTRL_SIR_GAP 0x70 | ||
86 | #define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0 | ||
87 | #define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1 | ||
88 | #define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2 | ||
89 | #define BV_IR_CTRL_SIR_GAP__GAP_500 0x3 | ||
90 | #define BV_IR_CTRL_SIR_GAP__GAP_100 0x4 | ||
91 | #define BV_IR_CTRL_SIR_GAP__GAP_50 0x5 | ||
92 | #define BV_IR_CTRL_SIR_GAP__GAP_10 0x6 | ||
93 | #define BV_IR_CTRL_SIR_GAP__GAP_0 0x7 | ||
94 | #define BF_IR_CTRL_SIR_GAP(v) (((v) << 4) & 0x70) | ||
95 | #define BF_IR_CTRL_SIR_GAP_V(v) ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70) | ||
96 | #define BP_IR_CTRL_SIPEN 3 | ||
97 | #define BM_IR_CTRL_SIPEN 0x8 | ||
98 | #define BF_IR_CTRL_SIPEN(v) (((v) << 3) & 0x8) | ||
99 | #define BP_IR_CTRL_TCEN 2 | ||
100 | #define BM_IR_CTRL_TCEN 0x4 | ||
101 | #define BF_IR_CTRL_TCEN(v) (((v) << 2) & 0x4) | ||
102 | #define BP_IR_CTRL_TXEN 1 | ||
103 | #define BM_IR_CTRL_TXEN 0x2 | ||
104 | #define BF_IR_CTRL_TXEN(v) (((v) << 1) & 0x2) | ||
105 | #define BP_IR_CTRL_RXEN 0 | ||
106 | #define BM_IR_CTRL_RXEN 0x1 | ||
107 | #define BF_IR_CTRL_RXEN(v) (((v) << 0) & 0x1) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_IR_TXDMA | ||
111 | * Address: 0x10 | ||
112 | * SCT: yes | ||
113 | */ | ||
114 | #define HW_IR_TXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0)) | ||
115 | #define HW_IR_TXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4)) | ||
116 | #define HW_IR_TXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8)) | ||
117 | #define HW_IR_TXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc)) | ||
118 | #define BP_IR_TXDMA_RUN 31 | ||
119 | #define BM_IR_TXDMA_RUN 0x80000000 | ||
120 | #define BF_IR_TXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
121 | #define BP_IR_TXDMA_EMPTY 29 | ||
122 | #define BM_IR_TXDMA_EMPTY 0x20000000 | ||
123 | #define BF_IR_TXDMA_EMPTY(v) (((v) << 29) & 0x20000000) | ||
124 | #define BP_IR_TXDMA_INT 28 | ||
125 | #define BM_IR_TXDMA_INT 0x10000000 | ||
126 | #define BF_IR_TXDMA_INT(v) (((v) << 28) & 0x10000000) | ||
127 | #define BP_IR_TXDMA_CHANGE 27 | ||
128 | #define BM_IR_TXDMA_CHANGE 0x8000000 | ||
129 | #define BF_IR_TXDMA_CHANGE(v) (((v) << 27) & 0x8000000) | ||
130 | #define BP_IR_TXDMA_NEW_MTA 24 | ||
131 | #define BM_IR_TXDMA_NEW_MTA 0x7000000 | ||
132 | #define BF_IR_TXDMA_NEW_MTA(v) (((v) << 24) & 0x7000000) | ||
133 | #define BP_IR_TXDMA_NEW_MODE 22 | ||
134 | #define BM_IR_TXDMA_NEW_MODE 0xc00000 | ||
135 | #define BF_IR_TXDMA_NEW_MODE(v) (((v) << 22) & 0xc00000) | ||
136 | #define BP_IR_TXDMA_NEW_SPEED 19 | ||
137 | #define BM_IR_TXDMA_NEW_SPEED 0x380000 | ||
138 | #define BF_IR_TXDMA_NEW_SPEED(v) (((v) << 19) & 0x380000) | ||
139 | #define BP_IR_TXDMA_BOF_TYPE 18 | ||
140 | #define BM_IR_TXDMA_BOF_TYPE 0x40000 | ||
141 | #define BF_IR_TXDMA_BOF_TYPE(v) (((v) << 18) & 0x40000) | ||
142 | #define BP_IR_TXDMA_XBOFS 12 | ||
143 | #define BM_IR_TXDMA_XBOFS 0x3f000 | ||
144 | #define BF_IR_TXDMA_XBOFS(v) (((v) << 12) & 0x3f000) | ||
145 | #define BP_IR_TXDMA_XFER_COUNT 0 | ||
146 | #define BM_IR_TXDMA_XFER_COUNT 0xfff | ||
147 | #define BF_IR_TXDMA_XFER_COUNT(v) (((v) << 0) & 0xfff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_IR_RXDMA | ||
151 | * Address: 0x20 | ||
152 | * SCT: yes | ||
153 | */ | ||
154 | #define HW_IR_RXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0)) | ||
155 | #define HW_IR_RXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4)) | ||
156 | #define HW_IR_RXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8)) | ||
157 | #define HW_IR_RXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc)) | ||
158 | #define BP_IR_RXDMA_RUN 31 | ||
159 | #define BM_IR_RXDMA_RUN 0x80000000 | ||
160 | #define BF_IR_RXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
161 | #define BP_IR_RXDMA_XFER_COUNT 0 | ||
162 | #define BM_IR_RXDMA_XFER_COUNT 0x3ff | ||
163 | #define BF_IR_RXDMA_XFER_COUNT(v) (((v) << 0) & 0x3ff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_IR_DBGCTRL | ||
167 | * Address: 0x30 | ||
168 | * SCT: yes | ||
169 | */ | ||
170 | #define HW_IR_DBGCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0)) | ||
171 | #define HW_IR_DBGCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4)) | ||
172 | #define HW_IR_DBGCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8)) | ||
173 | #define HW_IR_DBGCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc)) | ||
174 | #define BP_IR_DBGCTRL_VFIRSWZ 12 | ||
175 | #define BM_IR_DBGCTRL_VFIRSWZ 0x1000 | ||
176 | #define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0 | ||
177 | #define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1 | ||
178 | #define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) << 12) & 0x1000) | ||
179 | #define BF_IR_DBGCTRL_VFIRSWZ_V(v) ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000) | ||
180 | #define BP_IR_DBGCTRL_RXFRMOFF 11 | ||
181 | #define BM_IR_DBGCTRL_RXFRMOFF 0x800 | ||
182 | #define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) << 11) & 0x800) | ||
183 | #define BP_IR_DBGCTRL_RXCRCOFF 10 | ||
184 | #define BM_IR_DBGCTRL_RXCRCOFF 0x400 | ||
185 | #define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) << 10) & 0x400) | ||
186 | #define BP_IR_DBGCTRL_RXINVERT 9 | ||
187 | #define BM_IR_DBGCTRL_RXINVERT 0x200 | ||
188 | #define BF_IR_DBGCTRL_RXINVERT(v) (((v) << 9) & 0x200) | ||
189 | #define BP_IR_DBGCTRL_TXFRMOFF 8 | ||
190 | #define BM_IR_DBGCTRL_TXFRMOFF 0x100 | ||
191 | #define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) << 8) & 0x100) | ||
192 | #define BP_IR_DBGCTRL_TXCRCOFF 7 | ||
193 | #define BM_IR_DBGCTRL_TXCRCOFF 0x80 | ||
194 | #define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) << 7) & 0x80) | ||
195 | #define BP_IR_DBGCTRL_TXINVERT 6 | ||
196 | #define BM_IR_DBGCTRL_TXINVERT 0x40 | ||
197 | #define BF_IR_DBGCTRL_TXINVERT(v) (((v) << 6) & 0x40) | ||
198 | #define BP_IR_DBGCTRL_INTLOOPBACK 5 | ||
199 | #define BM_IR_DBGCTRL_INTLOOPBACK 0x20 | ||
200 | #define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) << 5) & 0x20) | ||
201 | #define BP_IR_DBGCTRL_DUPLEX 4 | ||
202 | #define BM_IR_DBGCTRL_DUPLEX 0x10 | ||
203 | #define BF_IR_DBGCTRL_DUPLEX(v) (((v) << 4) & 0x10) | ||
204 | #define BP_IR_DBGCTRL_MIO_RX 3 | ||
205 | #define BM_IR_DBGCTRL_MIO_RX 0x8 | ||
206 | #define BF_IR_DBGCTRL_MIO_RX(v) (((v) << 3) & 0x8) | ||
207 | #define BP_IR_DBGCTRL_MIO_TX 2 | ||
208 | #define BM_IR_DBGCTRL_MIO_TX 0x4 | ||
209 | #define BF_IR_DBGCTRL_MIO_TX(v) (((v) << 2) & 0x4) | ||
210 | #define BP_IR_DBGCTRL_MIO_SCLK 1 | ||
211 | #define BM_IR_DBGCTRL_MIO_SCLK 0x2 | ||
212 | #define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) << 1) & 0x2) | ||
213 | #define BP_IR_DBGCTRL_MIO_EN 0 | ||
214 | #define BM_IR_DBGCTRL_MIO_EN 0x1 | ||
215 | #define BF_IR_DBGCTRL_MIO_EN(v) (((v) << 0) & 0x1) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_IR_INTR | ||
219 | * Address: 0x40 | ||
220 | * SCT: yes | ||
221 | */ | ||
222 | #define HW_IR_INTR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0)) | ||
223 | #define HW_IR_INTR_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4)) | ||
224 | #define HW_IR_INTR_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8)) | ||
225 | #define HW_IR_INTR_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc)) | ||
226 | #define BP_IR_INTR_RXABORT_IRQ_EN 22 | ||
227 | #define BM_IR_INTR_RXABORT_IRQ_EN 0x400000 | ||
228 | #define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0 | ||
229 | #define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1 | ||
230 | #define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
231 | #define BF_IR_INTR_RXABORT_IRQ_EN_V(v) ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000) | ||
232 | #define BP_IR_INTR_SPEED_IRQ_EN 21 | ||
233 | #define BM_IR_INTR_SPEED_IRQ_EN 0x200000 | ||
234 | #define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0 | ||
235 | #define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1 | ||
236 | #define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
237 | #define BF_IR_INTR_SPEED_IRQ_EN_V(v) ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000) | ||
238 | #define BP_IR_INTR_RXOF_IRQ_EN 20 | ||
239 | #define BM_IR_INTR_RXOF_IRQ_EN 0x100000 | ||
240 | #define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0 | ||
241 | #define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1 | ||
242 | #define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
243 | #define BF_IR_INTR_RXOF_IRQ_EN_V(v) ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000) | ||
244 | #define BP_IR_INTR_TXUF_IRQ_EN 19 | ||
245 | #define BM_IR_INTR_TXUF_IRQ_EN 0x80000 | ||
246 | #define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0 | ||
247 | #define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1 | ||
248 | #define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
249 | #define BF_IR_INTR_TXUF_IRQ_EN_V(v) ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000) | ||
250 | #define BP_IR_INTR_TC_IRQ_EN 18 | ||
251 | #define BM_IR_INTR_TC_IRQ_EN 0x40000 | ||
252 | #define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0 | ||
253 | #define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1 | ||
254 | #define BF_IR_INTR_TC_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
255 | #define BF_IR_INTR_TC_IRQ_EN_V(v) ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000) | ||
256 | #define BP_IR_INTR_RX_IRQ_EN 17 | ||
257 | #define BM_IR_INTR_RX_IRQ_EN 0x20000 | ||
258 | #define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0 | ||
259 | #define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1 | ||
260 | #define BF_IR_INTR_RX_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
261 | #define BF_IR_INTR_RX_IRQ_EN_V(v) ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000) | ||
262 | #define BP_IR_INTR_TX_IRQ_EN 16 | ||
263 | #define BM_IR_INTR_TX_IRQ_EN 0x10000 | ||
264 | #define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0 | ||
265 | #define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1 | ||
266 | #define BF_IR_INTR_TX_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
267 | #define BF_IR_INTR_TX_IRQ_EN_V(v) ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000) | ||
268 | #define BP_IR_INTR_RXABORT_IRQ 6 | ||
269 | #define BM_IR_INTR_RXABORT_IRQ 0x40 | ||
270 | #define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0 | ||
271 | #define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1 | ||
272 | #define BF_IR_INTR_RXABORT_IRQ(v) (((v) << 6) & 0x40) | ||
273 | #define BF_IR_INTR_RXABORT_IRQ_V(v) ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40) | ||
274 | #define BP_IR_INTR_SPEED_IRQ 5 | ||
275 | #define BM_IR_INTR_SPEED_IRQ 0x20 | ||
276 | #define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0 | ||
277 | #define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1 | ||
278 | #define BF_IR_INTR_SPEED_IRQ(v) (((v) << 5) & 0x20) | ||
279 | #define BF_IR_INTR_SPEED_IRQ_V(v) ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20) | ||
280 | #define BP_IR_INTR_RXOF_IRQ 4 | ||
281 | #define BM_IR_INTR_RXOF_IRQ 0x10 | ||
282 | #define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0 | ||
283 | #define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1 | ||
284 | #define BF_IR_INTR_RXOF_IRQ(v) (((v) << 4) & 0x10) | ||
285 | #define BF_IR_INTR_RXOF_IRQ_V(v) ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10) | ||
286 | #define BP_IR_INTR_TXUF_IRQ 3 | ||
287 | #define BM_IR_INTR_TXUF_IRQ 0x8 | ||
288 | #define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0 | ||
289 | #define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1 | ||
290 | #define BF_IR_INTR_TXUF_IRQ(v) (((v) << 3) & 0x8) | ||
291 | #define BF_IR_INTR_TXUF_IRQ_V(v) ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8) | ||
292 | #define BP_IR_INTR_TC_IRQ 2 | ||
293 | #define BM_IR_INTR_TC_IRQ 0x4 | ||
294 | #define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0 | ||
295 | #define BV_IR_INTR_TC_IRQ__REQUEST 0x1 | ||
296 | #define BF_IR_INTR_TC_IRQ(v) (((v) << 2) & 0x4) | ||
297 | #define BF_IR_INTR_TC_IRQ_V(v) ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4) | ||
298 | #define BP_IR_INTR_RX_IRQ 1 | ||
299 | #define BM_IR_INTR_RX_IRQ 0x2 | ||
300 | #define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0 | ||
301 | #define BV_IR_INTR_RX_IRQ__REQUEST 0x1 | ||
302 | #define BF_IR_INTR_RX_IRQ(v) (((v) << 1) & 0x2) | ||
303 | #define BF_IR_INTR_RX_IRQ_V(v) ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2) | ||
304 | #define BP_IR_INTR_TX_IRQ 0 | ||
305 | #define BM_IR_INTR_TX_IRQ 0x1 | ||
306 | #define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0 | ||
307 | #define BV_IR_INTR_TX_IRQ__REQUEST 0x1 | ||
308 | #define BF_IR_INTR_TX_IRQ(v) (((v) << 0) & 0x1) | ||
309 | #define BF_IR_INTR_TX_IRQ_V(v) ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1) | ||
310 | |||
311 | /** | ||
312 | * Register: HW_IR_DATA | ||
313 | * Address: 0x50 | ||
314 | * SCT: no | ||
315 | */ | ||
316 | #define HW_IR_DATA (*(volatile unsigned long *)(REGS_IR_BASE + 0x50)) | ||
317 | #define BP_IR_DATA_DATA 0 | ||
318 | #define BM_IR_DATA_DATA 0xffffffff | ||
319 | #define BF_IR_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_IR_STAT | ||
323 | * Address: 0x60 | ||
324 | * SCT: no | ||
325 | */ | ||
326 | #define HW_IR_STAT (*(volatile unsigned long *)(REGS_IR_BASE + 0x60)) | ||
327 | #define BP_IR_STAT_PRESENT 31 | ||
328 | #define BM_IR_STAT_PRESENT 0x80000000 | ||
329 | #define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0 | ||
330 | #define BV_IR_STAT_PRESENT__AVAILABLE 0x1 | ||
331 | #define BF_IR_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
332 | #define BF_IR_STAT_PRESENT_V(v) ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000) | ||
333 | #define BP_IR_STAT_MODE_ALLOWED 29 | ||
334 | #define BM_IR_STAT_MODE_ALLOWED 0x60000000 | ||
335 | #define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0 | ||
336 | #define BV_IR_STAT_MODE_ALLOWED__FIR 0x1 | ||
337 | #define BV_IR_STAT_MODE_ALLOWED__MIR 0x2 | ||
338 | #define BV_IR_STAT_MODE_ALLOWED__SIR 0x3 | ||
339 | #define BF_IR_STAT_MODE_ALLOWED(v) (((v) << 29) & 0x60000000) | ||
340 | #define BF_IR_STAT_MODE_ALLOWED_V(v) ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000) | ||
341 | #define BP_IR_STAT_ANY_IRQ 28 | ||
342 | #define BM_IR_STAT_ANY_IRQ 0x10000000 | ||
343 | #define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0 | ||
344 | #define BV_IR_STAT_ANY_IRQ__REQUEST 0x1 | ||
345 | #define BF_IR_STAT_ANY_IRQ(v) (((v) << 28) & 0x10000000) | ||
346 | #define BF_IR_STAT_ANY_IRQ_V(v) ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000) | ||
347 | #define BP_IR_STAT_RXABORT_SUMMARY 22 | ||
348 | #define BM_IR_STAT_RXABORT_SUMMARY 0x400000 | ||
349 | #define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0 | ||
350 | #define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1 | ||
351 | #define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) << 22) & 0x400000) | ||
352 | #define BF_IR_STAT_RXABORT_SUMMARY_V(v) ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000) | ||
353 | #define BP_IR_STAT_SPEED_SUMMARY 21 | ||
354 | #define BM_IR_STAT_SPEED_SUMMARY 0x200000 | ||
355 | #define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0 | ||
356 | #define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1 | ||
357 | #define BF_IR_STAT_SPEED_SUMMARY(v) (((v) << 21) & 0x200000) | ||
358 | #define BF_IR_STAT_SPEED_SUMMARY_V(v) ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000) | ||
359 | #define BP_IR_STAT_RXOF_SUMMARY 20 | ||
360 | #define BM_IR_STAT_RXOF_SUMMARY 0x100000 | ||
361 | #define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0 | ||
362 | #define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1 | ||
363 | #define BF_IR_STAT_RXOF_SUMMARY(v) (((v) << 20) & 0x100000) | ||
364 | #define BF_IR_STAT_RXOF_SUMMARY_V(v) ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000) | ||
365 | #define BP_IR_STAT_TXUF_SUMMARY 19 | ||
366 | #define BM_IR_STAT_TXUF_SUMMARY 0x80000 | ||
367 | #define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0 | ||
368 | #define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1 | ||
369 | #define BF_IR_STAT_TXUF_SUMMARY(v) (((v) << 19) & 0x80000) | ||
370 | #define BF_IR_STAT_TXUF_SUMMARY_V(v) ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000) | ||
371 | #define BP_IR_STAT_TC_SUMMARY 18 | ||
372 | #define BM_IR_STAT_TC_SUMMARY 0x40000 | ||
373 | #define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0 | ||
374 | #define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1 | ||
375 | #define BF_IR_STAT_TC_SUMMARY(v) (((v) << 18) & 0x40000) | ||
376 | #define BF_IR_STAT_TC_SUMMARY_V(v) ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000) | ||
377 | #define BP_IR_STAT_RX_SUMMARY 17 | ||
378 | #define BM_IR_STAT_RX_SUMMARY 0x20000 | ||
379 | #define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0 | ||
380 | #define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1 | ||
381 | #define BF_IR_STAT_RX_SUMMARY(v) (((v) << 17) & 0x20000) | ||
382 | #define BF_IR_STAT_RX_SUMMARY_V(v) ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000) | ||
383 | #define BP_IR_STAT_TX_SUMMARY 16 | ||
384 | #define BM_IR_STAT_TX_SUMMARY 0x10000 | ||
385 | #define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0 | ||
386 | #define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1 | ||
387 | #define BF_IR_STAT_TX_SUMMARY(v) (((v) << 16) & 0x10000) | ||
388 | #define BF_IR_STAT_TX_SUMMARY_V(v) ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000) | ||
389 | #define BP_IR_STAT_MEDIA_BUSY 2 | ||
390 | #define BM_IR_STAT_MEDIA_BUSY 0x4 | ||
391 | #define BF_IR_STAT_MEDIA_BUSY(v) (((v) << 2) & 0x4) | ||
392 | #define BP_IR_STAT_RX_ACTIVE 1 | ||
393 | #define BM_IR_STAT_RX_ACTIVE 0x2 | ||
394 | #define BF_IR_STAT_RX_ACTIVE(v) (((v) << 1) & 0x2) | ||
395 | #define BP_IR_STAT_TX_ACTIVE 0 | ||
396 | #define BM_IR_STAT_TX_ACTIVE 0x1 | ||
397 | #define BF_IR_STAT_TX_ACTIVE(v) (((v) << 0) & 0x1) | ||
398 | |||
399 | /** | ||
400 | * Register: HW_IR_TCCTRL | ||
401 | * Address: 0x70 | ||
402 | * SCT: yes | ||
403 | */ | ||
404 | #define HW_IR_TCCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0)) | ||
405 | #define HW_IR_TCCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4)) | ||
406 | #define HW_IR_TCCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8)) | ||
407 | #define HW_IR_TCCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc)) | ||
408 | #define BP_IR_TCCTRL_INIT 31 | ||
409 | #define BM_IR_TCCTRL_INIT 0x80000000 | ||
410 | #define BF_IR_TCCTRL_INIT(v) (((v) << 31) & 0x80000000) | ||
411 | #define BP_IR_TCCTRL_GO 30 | ||
412 | #define BM_IR_TCCTRL_GO 0x40000000 | ||
413 | #define BF_IR_TCCTRL_GO(v) (((v) << 30) & 0x40000000) | ||
414 | #define BP_IR_TCCTRL_BUSY 29 | ||
415 | #define BM_IR_TCCTRL_BUSY 0x20000000 | ||
416 | #define BF_IR_TCCTRL_BUSY(v) (((v) << 29) & 0x20000000) | ||
417 | #define BP_IR_TCCTRL_TEMIC 24 | ||
418 | #define BM_IR_TCCTRL_TEMIC 0x1000000 | ||
419 | #define BV_IR_TCCTRL_TEMIC__LOW 0x0 | ||
420 | #define BV_IR_TCCTRL_TEMIC__HIGH 0x1 | ||
421 | #define BF_IR_TCCTRL_TEMIC(v) (((v) << 24) & 0x1000000) | ||
422 | #define BF_IR_TCCTRL_TEMIC_V(v) ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000) | ||
423 | #define BP_IR_TCCTRL_EXT_DATA 16 | ||
424 | #define BM_IR_TCCTRL_EXT_DATA 0xff0000 | ||
425 | #define BF_IR_TCCTRL_EXT_DATA(v) (((v) << 16) & 0xff0000) | ||
426 | #define BP_IR_TCCTRL_DATA 8 | ||
427 | #define BM_IR_TCCTRL_DATA 0xff00 | ||
428 | #define BF_IR_TCCTRL_DATA(v) (((v) << 8) & 0xff00) | ||
429 | #define BP_IR_TCCTRL_ADDR 5 | ||
430 | #define BM_IR_TCCTRL_ADDR 0xe0 | ||
431 | #define BF_IR_TCCTRL_ADDR(v) (((v) << 5) & 0xe0) | ||
432 | #define BP_IR_TCCTRL_INDX 1 | ||
433 | #define BM_IR_TCCTRL_INDX 0x1e | ||
434 | #define BF_IR_TCCTRL_INDX(v) (((v) << 1) & 0x1e) | ||
435 | #define BP_IR_TCCTRL_C 0 | ||
436 | #define BM_IR_TCCTRL_C 0x1 | ||
437 | #define BF_IR_TCCTRL_C(v) (((v) << 0) & 0x1) | ||
438 | |||
439 | /** | ||
440 | * Register: HW_IR_SI_READ | ||
441 | * Address: 0x80 | ||
442 | * SCT: no | ||
443 | */ | ||
444 | #define HW_IR_SI_READ (*(volatile unsigned long *)(REGS_IR_BASE + 0x80)) | ||
445 | #define BP_IR_SI_READ_ABORT 8 | ||
446 | #define BM_IR_SI_READ_ABORT 0x100 | ||
447 | #define BF_IR_SI_READ_ABORT(v) (((v) << 8) & 0x100) | ||
448 | #define BP_IR_SI_READ_DATA 0 | ||
449 | #define BM_IR_SI_READ_DATA 0xff | ||
450 | #define BF_IR_SI_READ_DATA(v) (((v) << 0) & 0xff) | ||
451 | |||
452 | /** | ||
453 | * Register: HW_IR_DEBUG | ||
454 | * Address: 0x90 | ||
455 | * SCT: no | ||
456 | */ | ||
457 | #define HW_IR_DEBUG (*(volatile unsigned long *)(REGS_IR_BASE + 0x90)) | ||
458 | #define BP_IR_DEBUG_TXDMAKICK 5 | ||
459 | #define BM_IR_DEBUG_TXDMAKICK 0x20 | ||
460 | #define BF_IR_DEBUG_TXDMAKICK(v) (((v) << 5) & 0x20) | ||
461 | #define BP_IR_DEBUG_RXDMAKICK 4 | ||
462 | #define BM_IR_DEBUG_RXDMAKICK 0x10 | ||
463 | #define BF_IR_DEBUG_RXDMAKICK(v) (((v) << 4) & 0x10) | ||
464 | #define BP_IR_DEBUG_TXDMAEND 3 | ||
465 | #define BM_IR_DEBUG_TXDMAEND 0x8 | ||
466 | #define BF_IR_DEBUG_TXDMAEND(v) (((v) << 3) & 0x8) | ||
467 | #define BP_IR_DEBUG_RXDMAEND 2 | ||
468 | #define BM_IR_DEBUG_RXDMAEND 0x4 | ||
469 | #define BF_IR_DEBUG_RXDMAEND(v) (((v) << 2) & 0x4) | ||
470 | #define BP_IR_DEBUG_TXDMAREQ 1 | ||
471 | #define BM_IR_DEBUG_TXDMAREQ 0x2 | ||
472 | #define BF_IR_DEBUG_TXDMAREQ(v) (((v) << 1) & 0x2) | ||
473 | #define BP_IR_DEBUG_RXDMAREQ 0 | ||
474 | #define BM_IR_DEBUG_RXDMAREQ 0x1 | ||
475 | #define BF_IR_DEBUG_RXDMAREQ(v) (((v) << 0) & 0x1) | ||
476 | |||
477 | #endif /* __HEADERGEN__STMP3600__IR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h new file mode 100644 index 0000000000..24b17d5905 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h | |||
@@ -0,0 +1,167 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__LCDIF__H__ | ||
24 | #define __HEADERGEN__STMP3600__LCDIF__H__ | ||
25 | |||
26 | #define REGS_LCDIF_BASE (0x80060000) | ||
27 | |||
28 | #define REGS_LCDIF_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_LCDIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_LCDIF_CTRL (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0)) | ||
36 | #define HW_LCDIF_CTRL_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4)) | ||
37 | #define HW_LCDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8)) | ||
38 | #define HW_LCDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc)) | ||
39 | #define BP_LCDIF_CTRL_SFTRST 31 | ||
40 | #define BM_LCDIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_LCDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_LCDIF_CTRL_CLKGATE 30 | ||
43 | #define BM_LCDIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_LCDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_LCDIF_CTRL_PRESENT 29 | ||
46 | #define BM_LCDIF_CTRL_PRESENT 0x20000000 | ||
47 | #define BF_LCDIF_CTRL_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_LCDIF_CTRL_BUSY_ENABLE 25 | ||
49 | #define BM_LCDIF_CTRL_BUSY_ENABLE 0x2000000 | ||
50 | #define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_DISABLED 0x0 | ||
51 | #define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_ENABLED 0x1 | ||
52 | #define BF_LCDIF_CTRL_BUSY_ENABLE(v) (((v) << 25) & 0x2000000) | ||
53 | #define BF_LCDIF_CTRL_BUSY_ENABLE_V(v) ((BV_LCDIF_CTRL_BUSY_ENABLE__##v << 25) & 0x2000000) | ||
54 | #define BP_LCDIF_CTRL_FIFO_STATUS 24 | ||
55 | #define BM_LCDIF_CTRL_FIFO_STATUS 0x1000000 | ||
56 | #define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_FULL 0x0 | ||
57 | #define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_OK 0x1 | ||
58 | #define BF_LCDIF_CTRL_FIFO_STATUS(v) (((v) << 24) & 0x1000000) | ||
59 | #define BF_LCDIF_CTRL_FIFO_STATUS_V(v) ((BV_LCDIF_CTRL_FIFO_STATUS__##v << 24) & 0x1000000) | ||
60 | #define BP_LCDIF_CTRL_DMA_REQ 23 | ||
61 | #define BM_LCDIF_CTRL_DMA_REQ 0x800000 | ||
62 | #define BF_LCDIF_CTRL_DMA_REQ(v) (((v) << 23) & 0x800000) | ||
63 | #define BP_LCDIF_CTRL_DATA_SWIZZLE 21 | ||
64 | #define BM_LCDIF_CTRL_DATA_SWIZZLE 0x600000 | ||
65 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP 0x0 | ||
66 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 | ||
67 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 | ||
68 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 | ||
69 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP 0x2 | ||
70 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 | ||
71 | #define BF_LCDIF_CTRL_DATA_SWIZZLE(v) (((v) << 21) & 0x600000) | ||
72 | #define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v) ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000) | ||
73 | #define BP_LCDIF_CTRL_RESET 20 | ||
74 | #define BM_LCDIF_CTRL_RESET 0x100000 | ||
75 | #define BV_LCDIF_CTRL_RESET__LCDRESET_LOW 0x0 | ||
76 | #define BV_LCDIF_CTRL_RESET__LCDRESET_HIGH 0x1 | ||
77 | #define BF_LCDIF_CTRL_RESET(v) (((v) << 20) & 0x100000) | ||
78 | #define BF_LCDIF_CTRL_RESET_V(v) ((BV_LCDIF_CTRL_RESET__##v << 20) & 0x100000) | ||
79 | #define BP_LCDIF_CTRL_MODE86 19 | ||
80 | #define BM_LCDIF_CTRL_MODE86 0x80000 | ||
81 | #define BV_LCDIF_CTRL_MODE86__8080_MODE 0x0 | ||
82 | #define BV_LCDIF_CTRL_MODE86__6800_MODE 0x1 | ||
83 | #define BF_LCDIF_CTRL_MODE86(v) (((v) << 19) & 0x80000) | ||
84 | #define BF_LCDIF_CTRL_MODE86_V(v) ((BV_LCDIF_CTRL_MODE86__##v << 19) & 0x80000) | ||
85 | #define BP_LCDIF_CTRL_DATA_SELECT 18 | ||
86 | #define BM_LCDIF_CTRL_DATA_SELECT 0x40000 | ||
87 | #define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 | ||
88 | #define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 | ||
89 | #define BF_LCDIF_CTRL_DATA_SELECT(v) (((v) << 18) & 0x40000) | ||
90 | #define BF_LCDIF_CTRL_DATA_SELECT_V(v) ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000) | ||
91 | #define BP_LCDIF_CTRL_WORD_LENGTH 17 | ||
92 | #define BM_LCDIF_CTRL_WORD_LENGTH 0x20000 | ||
93 | #define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 | ||
94 | #define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 | ||
95 | #define BF_LCDIF_CTRL_WORD_LENGTH(v) (((v) << 17) & 0x20000) | ||
96 | #define BF_LCDIF_CTRL_WORD_LENGTH_V(v) ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000) | ||
97 | #define BP_LCDIF_CTRL_RUN 16 | ||
98 | #define BM_LCDIF_CTRL_RUN 0x10000 | ||
99 | #define BF_LCDIF_CTRL_RUN(v) (((v) << 16) & 0x10000) | ||
100 | #define BP_LCDIF_CTRL_COUNT 0 | ||
101 | #define BM_LCDIF_CTRL_COUNT 0xffff | ||
102 | #define BF_LCDIF_CTRL_COUNT(v) (((v) << 0) & 0xffff) | ||
103 | |||
104 | /** | ||
105 | * Register: HW_LCDIF_TIMING | ||
106 | * Address: 0x10 | ||
107 | * SCT: no | ||
108 | */ | ||
109 | #define HW_LCDIF_TIMING (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10)) | ||
110 | #define BP_LCDIF_TIMING_CMD_HOLD 24 | ||
111 | #define BM_LCDIF_TIMING_CMD_HOLD 0xff000000 | ||
112 | #define BF_LCDIF_TIMING_CMD_HOLD(v) (((v) << 24) & 0xff000000) | ||
113 | #define BP_LCDIF_TIMING_CMD_SETUP 16 | ||
114 | #define BM_LCDIF_TIMING_CMD_SETUP 0xff0000 | ||
115 | #define BF_LCDIF_TIMING_CMD_SETUP(v) (((v) << 16) & 0xff0000) | ||
116 | #define BP_LCDIF_TIMING_DATA_HOLD 8 | ||
117 | #define BM_LCDIF_TIMING_DATA_HOLD 0xff00 | ||
118 | #define BF_LCDIF_TIMING_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
119 | #define BP_LCDIF_TIMING_DATA_SETUP 0 | ||
120 | #define BM_LCDIF_TIMING_DATA_SETUP 0xff | ||
121 | #define BF_LCDIF_TIMING_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_LCDIF_DATA | ||
125 | * Address: 0x20 | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_LCDIF_DATA (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20)) | ||
129 | #define BP_LCDIF_DATA_DATA_THREE 24 | ||
130 | #define BM_LCDIF_DATA_DATA_THREE 0xff000000 | ||
131 | #define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000) | ||
132 | #define BP_LCDIF_DATA_DATA_TWO 16 | ||
133 | #define BM_LCDIF_DATA_DATA_TWO 0xff0000 | ||
134 | #define BF_LCDIF_DATA_DATA_TWO(v) (((v) << 16) & 0xff0000) | ||
135 | #define BP_LCDIF_DATA_DATA_ONE 8 | ||
136 | #define BM_LCDIF_DATA_DATA_ONE 0xff00 | ||
137 | #define BF_LCDIF_DATA_DATA_ONE(v) (((v) << 8) & 0xff00) | ||
138 | #define BP_LCDIF_DATA_DATA_ZERO 0 | ||
139 | #define BM_LCDIF_DATA_DATA_ZERO 0xff | ||
140 | #define BF_LCDIF_DATA_DATA_ZERO(v) (((v) << 0) & 0xff) | ||
141 | |||
142 | /** | ||
143 | * Register: HW_LCDIF_DEBUG | ||
144 | * Address: 0x30 | ||
145 | * SCT: no | ||
146 | */ | ||
147 | #define HW_LCDIF_DEBUG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30)) | ||
148 | #define BP_LCDIF_DEBUG_BUSY 27 | ||
149 | #define BM_LCDIF_DEBUG_BUSY 0x8000000 | ||
150 | #define BF_LCDIF_DEBUG_BUSY(v) (((v) << 27) & 0x8000000) | ||
151 | #define BP_LCDIF_DEBUG_LAST_SUBWORD 26 | ||
152 | #define BM_LCDIF_DEBUG_LAST_SUBWORD 0x4000000 | ||
153 | #define BF_LCDIF_DEBUG_LAST_SUBWORD(v) (((v) << 26) & 0x4000000) | ||
154 | #define BP_LCDIF_DEBUG_SUBWORD_POSITION 24 | ||
155 | #define BM_LCDIF_DEBUG_SUBWORD_POSITION 0x3000000 | ||
156 | #define BF_LCDIF_DEBUG_SUBWORD_POSITION(v) (((v) << 24) & 0x3000000) | ||
157 | #define BP_LCDIF_DEBUG_EMPTY_WORD 23 | ||
158 | #define BM_LCDIF_DEBUG_EMPTY_WORD 0x800000 | ||
159 | #define BF_LCDIF_DEBUG_EMPTY_WORD(v) (((v) << 23) & 0x800000) | ||
160 | #define BP_LCDIF_DEBUG_STATE 16 | ||
161 | #define BM_LCDIF_DEBUG_STATE 0x7f0000 | ||
162 | #define BF_LCDIF_DEBUG_STATE(v) (((v) << 16) & 0x7f0000) | ||
163 | #define BP_LCDIF_DEBUG_DATA_COUNT 0 | ||
164 | #define BM_LCDIF_DEBUG_DATA_COUNT 0xffff | ||
165 | #define BF_LCDIF_DEBUG_DATA_COUNT(v) (((v) << 0) & 0xffff) | ||
166 | |||
167 | #endif /* __HEADERGEN__STMP3600__LCDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h new file mode 100644 index 0000000000..c799635306 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h | |||
@@ -0,0 +1,572 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__LRADC__H__ | ||
24 | #define __HEADERGEN__STMP3600__LRADC__H__ | ||
25 | |||
26 | #define REGS_LRADC_BASE (0x80050000) | ||
27 | |||
28 | #define REGS_LRADC_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_LRADC_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_LRADC_CTRL0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_LRADC_CTRL0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_LRADC_CTRL0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_LRADC_CTRL0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_LRADC_CTRL0_SFTRST 31 | ||
40 | #define BM_LRADC_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_LRADC_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_LRADC_CTRL0_CLKGATE 30 | ||
43 | #define BM_LRADC_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_LRADC_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21 | ||
46 | #define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000 | ||
47 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 | ||
48 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 | ||
49 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) << 21) & 0x200000) | ||
50 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000) | ||
51 | #define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20 | ||
52 | #define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000 | ||
53 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 | ||
54 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 | ||
55 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) << 20) & 0x100000) | ||
56 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000) | ||
57 | #define BP_LRADC_CTRL0_YMINUS_ENABLE 19 | ||
58 | #define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000 | ||
59 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 | ||
60 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 | ||
61 | #define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) << 19) & 0x80000) | ||
62 | #define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000) | ||
63 | #define BP_LRADC_CTRL0_XMINUS_ENABLE 18 | ||
64 | #define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000 | ||
65 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 | ||
66 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 | ||
67 | #define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) << 18) & 0x40000) | ||
68 | #define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000) | ||
69 | #define BP_LRADC_CTRL0_YPLUS_ENABLE 17 | ||
70 | #define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000 | ||
71 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 | ||
72 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 | ||
73 | #define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) << 17) & 0x20000) | ||
74 | #define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000) | ||
75 | #define BP_LRADC_CTRL0_XPLUS_ENABLE 16 | ||
76 | #define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000 | ||
77 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 | ||
78 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 | ||
79 | #define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) << 16) & 0x10000) | ||
80 | #define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000) | ||
81 | #define BP_LRADC_CTRL0_SCHEDULE 0 | ||
82 | #define BM_LRADC_CTRL0_SCHEDULE 0xff | ||
83 | #define BF_LRADC_CTRL0_SCHEDULE(v) (((v) << 0) & 0xff) | ||
84 | |||
85 | /** | ||
86 | * Register: HW_LRADC_CTRL1 | ||
87 | * Address: 0x10 | ||
88 | * SCT: yes | ||
89 | */ | ||
90 | #define HW_LRADC_CTRL1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0)) | ||
91 | #define HW_LRADC_CTRL1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4)) | ||
92 | #define HW_LRADC_CTRL1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8)) | ||
93 | #define HW_LRADC_CTRL1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc)) | ||
94 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24 | ||
95 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000 | ||
96 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 | ||
97 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 | ||
98 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
99 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000) | ||
100 | #define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23 | ||
101 | #define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000 | ||
102 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 | ||
103 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 | ||
104 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) << 23) & 0x800000) | ||
105 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000) | ||
106 | #define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22 | ||
107 | #define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000 | ||
108 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 | ||
109 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 | ||
110 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
111 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000) | ||
112 | #define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21 | ||
113 | #define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000 | ||
114 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 | ||
115 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 | ||
116 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
117 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000) | ||
118 | #define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20 | ||
119 | #define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000 | ||
120 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 | ||
121 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 | ||
122 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
123 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000) | ||
124 | #define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19 | ||
125 | #define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000 | ||
126 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 | ||
127 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 | ||
128 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
129 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000) | ||
130 | #define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18 | ||
131 | #define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000 | ||
132 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 | ||
133 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 | ||
134 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
135 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000) | ||
136 | #define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17 | ||
137 | #define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000 | ||
138 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 | ||
139 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 | ||
140 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
141 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000) | ||
142 | #define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16 | ||
143 | #define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000 | ||
144 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 | ||
145 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 | ||
146 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
147 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000) | ||
148 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8 | ||
149 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100 | ||
150 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 | ||
151 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 | ||
152 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) << 8) & 0x100) | ||
153 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100) | ||
154 | #define BP_LRADC_CTRL1_LRADC7_IRQ 7 | ||
155 | #define BM_LRADC_CTRL1_LRADC7_IRQ 0x80 | ||
156 | #define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 | ||
157 | #define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 | ||
158 | #define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) << 7) & 0x80) | ||
159 | #define BF_LRADC_CTRL1_LRADC7_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80) | ||
160 | #define BP_LRADC_CTRL1_LRADC6_IRQ 6 | ||
161 | #define BM_LRADC_CTRL1_LRADC6_IRQ 0x40 | ||
162 | #define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 | ||
163 | #define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 | ||
164 | #define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) << 6) & 0x40) | ||
165 | #define BF_LRADC_CTRL1_LRADC6_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40) | ||
166 | #define BP_LRADC_CTRL1_LRADC5_IRQ 5 | ||
167 | #define BM_LRADC_CTRL1_LRADC5_IRQ 0x20 | ||
168 | #define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 | ||
169 | #define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 | ||
170 | #define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) << 5) & 0x20) | ||
171 | #define BF_LRADC_CTRL1_LRADC5_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20) | ||
172 | #define BP_LRADC_CTRL1_LRADC4_IRQ 4 | ||
173 | #define BM_LRADC_CTRL1_LRADC4_IRQ 0x10 | ||
174 | #define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 | ||
175 | #define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 | ||
176 | #define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) << 4) & 0x10) | ||
177 | #define BF_LRADC_CTRL1_LRADC4_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10) | ||
178 | #define BP_LRADC_CTRL1_LRADC3_IRQ 3 | ||
179 | #define BM_LRADC_CTRL1_LRADC3_IRQ 0x8 | ||
180 | #define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 | ||
181 | #define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 | ||
182 | #define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) << 3) & 0x8) | ||
183 | #define BF_LRADC_CTRL1_LRADC3_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8) | ||
184 | #define BP_LRADC_CTRL1_LRADC2_IRQ 2 | ||
185 | #define BM_LRADC_CTRL1_LRADC2_IRQ 0x4 | ||
186 | #define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 | ||
187 | #define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 | ||
188 | #define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) << 2) & 0x4) | ||
189 | #define BF_LRADC_CTRL1_LRADC2_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4) | ||
190 | #define BP_LRADC_CTRL1_LRADC1_IRQ 1 | ||
191 | #define BM_LRADC_CTRL1_LRADC1_IRQ 0x2 | ||
192 | #define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 | ||
193 | #define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 | ||
194 | #define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) << 1) & 0x2) | ||
195 | #define BF_LRADC_CTRL1_LRADC1_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2) | ||
196 | #define BP_LRADC_CTRL1_LRADC0_IRQ 0 | ||
197 | #define BM_LRADC_CTRL1_LRADC0_IRQ 0x1 | ||
198 | #define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 | ||
199 | #define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 | ||
200 | #define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) << 0) & 0x1) | ||
201 | #define BF_LRADC_CTRL1_LRADC0_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_LRADC_CTRL2 | ||
205 | * Address: 0x20 | ||
206 | * SCT: yes | ||
207 | */ | ||
208 | #define HW_LRADC_CTRL2 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0)) | ||
209 | #define HW_LRADC_CTRL2_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4)) | ||
210 | #define HW_LRADC_CTRL2_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8)) | ||
211 | #define HW_LRADC_CTRL2_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc)) | ||
212 | #define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 | ||
213 | #define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000 | ||
214 | #define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) << 24) & 0xff000000) | ||
215 | #define BP_LRADC_CTRL2_LRADC6SELECT 20 | ||
216 | #define BM_LRADC_CTRL2_LRADC6SELECT 0xf00000 | ||
217 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL0 0x0 | ||
218 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL1 0x1 | ||
219 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL2 0x2 | ||
220 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL3 0x3 | ||
221 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL4 0x4 | ||
222 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL5 0x5 | ||
223 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL6 0x6 | ||
224 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL7 0x7 | ||
225 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL8 0x8 | ||
226 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL9 0x9 | ||
227 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL10 0xa | ||
228 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL11 0xb | ||
229 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL12 0xc | ||
230 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL13 0xd | ||
231 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL14 0xe | ||
232 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL15 0xf | ||
233 | #define BF_LRADC_CTRL2_LRADC6SELECT(v) (((v) << 20) & 0xf00000) | ||
234 | #define BF_LRADC_CTRL2_LRADC6SELECT_V(v) ((BV_LRADC_CTRL2_LRADC6SELECT__##v << 20) & 0xf00000) | ||
235 | #define BP_LRADC_CTRL2_LRADC7SELECT 16 | ||
236 | #define BM_LRADC_CTRL2_LRADC7SELECT 0xf0000 | ||
237 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL0 0x0 | ||
238 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL1 0x1 | ||
239 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL2 0x2 | ||
240 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL3 0x3 | ||
241 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL4 0x4 | ||
242 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL5 0x5 | ||
243 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL6 0x6 | ||
244 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL7 0x7 | ||
245 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL8 0x8 | ||
246 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL9 0x9 | ||
247 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL10 0xa | ||
248 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL11 0xb | ||
249 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL12 0xc | ||
250 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL13 0xd | ||
251 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL14 0xe | ||
252 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL15 0xf | ||
253 | #define BF_LRADC_CTRL2_LRADC7SELECT(v) (((v) << 16) & 0xf0000) | ||
254 | #define BF_LRADC_CTRL2_LRADC7SELECT_V(v) ((BV_LRADC_CTRL2_LRADC7SELECT__##v << 16) & 0xf0000) | ||
255 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9 | ||
256 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200 | ||
257 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 | ||
258 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 | ||
259 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) << 9) & 0x200) | ||
260 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200) | ||
261 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8 | ||
262 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100 | ||
263 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 | ||
264 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 | ||
265 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) << 8) & 0x100) | ||
266 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100) | ||
267 | #define BP_LRADC_CTRL2_TEMP_ISRC1 4 | ||
268 | #define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0 | ||
269 | #define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf | ||
270 | #define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe | ||
271 | #define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd | ||
272 | #define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc | ||
273 | #define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb | ||
274 | #define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa | ||
275 | #define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 | ||
276 | #define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 | ||
277 | #define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 | ||
278 | #define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 | ||
279 | #define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 | ||
280 | #define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 | ||
281 | #define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 | ||
282 | #define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 | ||
283 | #define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 | ||
284 | #define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 | ||
285 | #define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) << 4) & 0xf0) | ||
286 | #define BF_LRADC_CTRL2_TEMP_ISRC1_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0) | ||
287 | #define BP_LRADC_CTRL2_TEMP_ISRC0 0 | ||
288 | #define BM_LRADC_CTRL2_TEMP_ISRC0 0xf | ||
289 | #define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf | ||
290 | #define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe | ||
291 | #define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd | ||
292 | #define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc | ||
293 | #define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb | ||
294 | #define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa | ||
295 | #define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 | ||
296 | #define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 | ||
297 | #define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 | ||
298 | #define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 | ||
299 | #define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 | ||
300 | #define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 | ||
301 | #define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 | ||
302 | #define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 | ||
303 | #define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 | ||
304 | #define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 | ||
305 | #define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) << 0) & 0xf) | ||
306 | #define BF_LRADC_CTRL2_TEMP_ISRC0_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf) | ||
307 | |||
308 | /** | ||
309 | * Register: HW_LRADC_CTRL3 | ||
310 | * Address: 0x30 | ||
311 | * SCT: yes | ||
312 | */ | ||
313 | #define HW_LRADC_CTRL3 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0)) | ||
314 | #define HW_LRADC_CTRL3_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4)) | ||
315 | #define HW_LRADC_CTRL3_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8)) | ||
316 | #define HW_LRADC_CTRL3_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc)) | ||
317 | #define BP_LRADC_CTRL3_DISCARD 24 | ||
318 | #define BM_LRADC_CTRL3_DISCARD 0x3000000 | ||
319 | #define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 | ||
320 | #define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 | ||
321 | #define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 | ||
322 | #define BF_LRADC_CTRL3_DISCARD(v) (((v) << 24) & 0x3000000) | ||
323 | #define BF_LRADC_CTRL3_DISCARD_V(v) ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000) | ||
324 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23 | ||
325 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000 | ||
326 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 | ||
327 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 | ||
328 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) << 23) & 0x800000) | ||
329 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000) | ||
330 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22 | ||
331 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000 | ||
332 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 | ||
333 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 | ||
334 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) << 22) & 0x400000) | ||
335 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000) | ||
336 | #define BP_LRADC_CTRL3_FORCE_PWD40UA_PWUP 21 | ||
337 | #define BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP 0x200000 | ||
338 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__OFF 0x0 | ||
339 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__ON 0x1 | ||
340 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v) (((v) << 21) & 0x200000) | ||
341 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__##v << 21) & 0x200000) | ||
342 | #define BP_LRADC_CTRL3_FORCE_PWD40UA_PWDN 20 | ||
343 | #define BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN 0x100000 | ||
344 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__ON 0x0 | ||
345 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__OFF 0x1 | ||
346 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v) (((v) << 20) & 0x100000) | ||
347 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__##v << 20) & 0x100000) | ||
348 | #define BP_LRADC_CTRL3_VDD_FILTER 16 | ||
349 | #define BM_LRADC_CTRL3_VDD_FILTER 0x30000 | ||
350 | #define BV_LRADC_CTRL3_VDD_FILTER__0OHMS 0x0 | ||
351 | #define BV_LRADC_CTRL3_VDD_FILTER__100OHMS 0x1 | ||
352 | #define BV_LRADC_CTRL3_VDD_FILTER__250OHMS 0x2 | ||
353 | #define BV_LRADC_CTRL3_VDD_FILTER__5000OHMS 0x3 | ||
354 | #define BF_LRADC_CTRL3_VDD_FILTER(v) (((v) << 16) & 0x30000) | ||
355 | #define BF_LRADC_CTRL3_VDD_FILTER_V(v) ((BV_LRADC_CTRL3_VDD_FILTER__##v << 16) & 0x30000) | ||
356 | #define BP_LRADC_CTRL3_ADD_CAP2INPUTS 12 | ||
357 | #define BM_LRADC_CTRL3_ADD_CAP2INPUTS 0x3000 | ||
358 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0PF 0x0 | ||
359 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0_5PF 0x1 | ||
360 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__1_0PF 0x2 | ||
361 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__2_5PF 0x3 | ||
362 | #define BF_LRADC_CTRL3_ADD_CAP2INPUTS(v) (((v) << 12) & 0x3000) | ||
363 | #define BF_LRADC_CTRL3_ADD_CAP2INPUTS_V(v) ((BV_LRADC_CTRL3_ADD_CAP2INPUTS__##v << 12) & 0x3000) | ||
364 | #define BP_LRADC_CTRL3_CYCLE_TIME 8 | ||
365 | #define BM_LRADC_CTRL3_CYCLE_TIME 0x300 | ||
366 | #define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 | ||
367 | #define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 | ||
368 | #define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 | ||
369 | #define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 | ||
370 | #define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) << 8) & 0x300) | ||
371 | #define BF_LRADC_CTRL3_CYCLE_TIME_V(v) ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300) | ||
372 | #define BP_LRADC_CTRL3_HIGH_TIME 4 | ||
373 | #define BM_LRADC_CTRL3_HIGH_TIME 0x30 | ||
374 | #define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 | ||
375 | #define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 | ||
376 | #define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 | ||
377 | #define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 | ||
378 | #define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) << 4) & 0x30) | ||
379 | #define BF_LRADC_CTRL3_HIGH_TIME_V(v) ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30) | ||
380 | #define BP_LRADC_CTRL3_REMOVE_CFILT 3 | ||
381 | #define BM_LRADC_CTRL3_REMOVE_CFILT 0x8 | ||
382 | #define BV_LRADC_CTRL3_REMOVE_CFILT__OFF 0x0 | ||
383 | #define BV_LRADC_CTRL3_REMOVE_CFILT__ON 0x1 | ||
384 | #define BF_LRADC_CTRL3_REMOVE_CFILT(v) (((v) << 3) & 0x8) | ||
385 | #define BF_LRADC_CTRL3_REMOVE_CFILT_V(v) ((BV_LRADC_CTRL3_REMOVE_CFILT__##v << 3) & 0x8) | ||
386 | #define BP_LRADC_CTRL3_SHORT_RFILT 2 | ||
387 | #define BM_LRADC_CTRL3_SHORT_RFILT 0x4 | ||
388 | #define BV_LRADC_CTRL3_SHORT_RFILT__OFF 0x0 | ||
389 | #define BV_LRADC_CTRL3_SHORT_RFILT__ON 0x1 | ||
390 | #define BF_LRADC_CTRL3_SHORT_RFILT(v) (((v) << 2) & 0x4) | ||
391 | #define BF_LRADC_CTRL3_SHORT_RFILT_V(v) ((BV_LRADC_CTRL3_SHORT_RFILT__##v << 2) & 0x4) | ||
392 | #define BP_LRADC_CTRL3_DELAY_CLOCK 1 | ||
393 | #define BM_LRADC_CTRL3_DELAY_CLOCK 0x2 | ||
394 | #define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 | ||
395 | #define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 | ||
396 | #define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) << 1) & 0x2) | ||
397 | #define BF_LRADC_CTRL3_DELAY_CLOCK_V(v) ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2) | ||
398 | #define BP_LRADC_CTRL3_INVERT_CLOCK 0 | ||
399 | #define BM_LRADC_CTRL3_INVERT_CLOCK 0x1 | ||
400 | #define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 | ||
401 | #define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 | ||
402 | #define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) << 0) & 0x1) | ||
403 | #define BF_LRADC_CTRL3_INVERT_CLOCK_V(v) ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1) | ||
404 | |||
405 | /** | ||
406 | * Register: HW_LRADC_STATUS | ||
407 | * Address: 0x40 | ||
408 | * SCT: no | ||
409 | */ | ||
410 | #define HW_LRADC_STATUS (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40)) | ||
411 | #define BP_LRADC_STATUS_TEMP1_PRESENT 26 | ||
412 | #define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000 | ||
413 | #define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
414 | #define BP_LRADC_STATUS_TEMP0_PRESENT 25 | ||
415 | #define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000 | ||
416 | #define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
417 | #define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24 | ||
418 | #define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000 | ||
419 | #define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) << 24) & 0x1000000) | ||
420 | #define BP_LRADC_STATUS_CHANNEL7_PRESENT 23 | ||
421 | #define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000 | ||
422 | #define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) << 23) & 0x800000) | ||
423 | #define BP_LRADC_STATUS_CHANNEL6_PRESENT 22 | ||
424 | #define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000 | ||
425 | #define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) << 22) & 0x400000) | ||
426 | #define BP_LRADC_STATUS_CHANNEL5_PRESENT 21 | ||
427 | #define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000 | ||
428 | #define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) << 21) & 0x200000) | ||
429 | #define BP_LRADC_STATUS_CHANNEL4_PRESENT 20 | ||
430 | #define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000 | ||
431 | #define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) << 20) & 0x100000) | ||
432 | #define BP_LRADC_STATUS_CHANNEL3_PRESENT 19 | ||
433 | #define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000 | ||
434 | #define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) << 19) & 0x80000) | ||
435 | #define BP_LRADC_STATUS_CHANNEL2_PRESENT 18 | ||
436 | #define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000 | ||
437 | #define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) << 18) & 0x40000) | ||
438 | #define BP_LRADC_STATUS_CHANNEL1_PRESENT 17 | ||
439 | #define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000 | ||
440 | #define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) << 17) & 0x20000) | ||
441 | #define BP_LRADC_STATUS_CHANNEL0_PRESENT 16 | ||
442 | #define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000 | ||
443 | #define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) << 16) & 0x10000) | ||
444 | #define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 | ||
445 | #define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1 | ||
446 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 | ||
447 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 | ||
448 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) << 0) & 0x1) | ||
449 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1) | ||
450 | |||
451 | /** | ||
452 | * Register: HW_LRADC_DEBUG0 | ||
453 | * Address: 0x110 | ||
454 | * SCT: no | ||
455 | */ | ||
456 | #define HW_LRADC_DEBUG0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110)) | ||
457 | #define BP_LRADC_DEBUG0_READONLY 16 | ||
458 | #define BM_LRADC_DEBUG0_READONLY 0xffff0000 | ||
459 | #define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000) | ||
460 | #define BP_LRADC_DEBUG0_STATE 0 | ||
461 | #define BM_LRADC_DEBUG0_STATE 0xfff | ||
462 | #define BF_LRADC_DEBUG0_STATE(v) (((v) << 0) & 0xfff) | ||
463 | |||
464 | /** | ||
465 | * Register: HW_LRADC_DEBUG1 | ||
466 | * Address: 0x120 | ||
467 | * SCT: yes | ||
468 | */ | ||
469 | #define HW_LRADC_DEBUG1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0)) | ||
470 | #define HW_LRADC_DEBUG1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4)) | ||
471 | #define HW_LRADC_DEBUG1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8)) | ||
472 | #define HW_LRADC_DEBUG1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc)) | ||
473 | #define BP_LRADC_DEBUG1_REQUEST 16 | ||
474 | #define BM_LRADC_DEBUG1_REQUEST 0xff0000 | ||
475 | #define BF_LRADC_DEBUG1_REQUEST(v) (((v) << 16) & 0xff0000) | ||
476 | #define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 | ||
477 | #define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00 | ||
478 | #define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) << 8) & 0x1f00) | ||
479 | #define BP_LRADC_DEBUG1_TESTMODE6 2 | ||
480 | #define BM_LRADC_DEBUG1_TESTMODE6 0x4 | ||
481 | #define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 | ||
482 | #define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 | ||
483 | #define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) << 2) & 0x4) | ||
484 | #define BF_LRADC_DEBUG1_TESTMODE6_V(v) ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4) | ||
485 | #define BP_LRADC_DEBUG1_TESTMODE5 1 | ||
486 | #define BM_LRADC_DEBUG1_TESTMODE5 0x2 | ||
487 | #define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 | ||
488 | #define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 | ||
489 | #define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) << 1) & 0x2) | ||
490 | #define BF_LRADC_DEBUG1_TESTMODE5_V(v) ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2) | ||
491 | #define BP_LRADC_DEBUG1_TESTMODE 0 | ||
492 | #define BM_LRADC_DEBUG1_TESTMODE 0x1 | ||
493 | #define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 | ||
494 | #define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 | ||
495 | #define BF_LRADC_DEBUG1_TESTMODE(v) (((v) << 0) & 0x1) | ||
496 | #define BF_LRADC_DEBUG1_TESTMODE_V(v) ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_LRADC_CONVERSION | ||
500 | * Address: 0x130 | ||
501 | * SCT: yes | ||
502 | */ | ||
503 | #define HW_LRADC_CONVERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0)) | ||
504 | #define HW_LRADC_CONVERSION_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4)) | ||
505 | #define HW_LRADC_CONVERSION_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8)) | ||
506 | #define HW_LRADC_CONVERSION_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc)) | ||
507 | #define BP_LRADC_CONVERSION_AUTOMATIC 20 | ||
508 | #define BM_LRADC_CONVERSION_AUTOMATIC 0x100000 | ||
509 | #define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 | ||
510 | #define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 | ||
511 | #define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) << 20) & 0x100000) | ||
512 | #define BF_LRADC_CONVERSION_AUTOMATIC_V(v) ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000) | ||
513 | #define BP_LRADC_CONVERSION_SCALE_FACTOR 16 | ||
514 | #define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000 | ||
515 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 | ||
516 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 | ||
517 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 | ||
518 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 | ||
519 | #define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) << 16) & 0x30000) | ||
520 | #define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v) ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000) | ||
521 | #define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 | ||
522 | #define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff | ||
523 | #define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) << 0) & 0x3ff) | ||
524 | |||
525 | /** | ||
526 | * Register: HW_LRADC_DELAYn | ||
527 | * Address: 0xd0+n*0x10 | ||
528 | * SCT: yes | ||
529 | */ | ||
530 | #define HW_LRADC_DELAYn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0)) | ||
531 | #define HW_LRADC_DELAYn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4)) | ||
532 | #define HW_LRADC_DELAYn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8)) | ||
533 | #define HW_LRADC_DELAYn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc)) | ||
534 | #define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 | ||
535 | #define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000 | ||
536 | #define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) << 24) & 0xff000000) | ||
537 | #define BP_LRADC_DELAYn_KICK 20 | ||
538 | #define BM_LRADC_DELAYn_KICK 0x100000 | ||
539 | #define BF_LRADC_DELAYn_KICK(v) (((v) << 20) & 0x100000) | ||
540 | #define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 | ||
541 | #define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000 | ||
542 | #define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) << 16) & 0xf0000) | ||
543 | #define BP_LRADC_DELAYn_LOOP_COUNT 11 | ||
544 | #define BM_LRADC_DELAYn_LOOP_COUNT 0xf800 | ||
545 | #define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) << 11) & 0xf800) | ||
546 | #define BP_LRADC_DELAYn_DELAY 0 | ||
547 | #define BM_LRADC_DELAYn_DELAY 0x7ff | ||
548 | #define BF_LRADC_DELAYn_DELAY(v) (((v) << 0) & 0x7ff) | ||
549 | |||
550 | /** | ||
551 | * Register: HW_LRADC_CHn | ||
552 | * Address: 0x50+n*0x10 | ||
553 | * SCT: yes | ||
554 | */ | ||
555 | #define HW_LRADC_CHn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0)) | ||
556 | #define HW_LRADC_CHn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4)) | ||
557 | #define HW_LRADC_CHn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8)) | ||
558 | #define HW_LRADC_CHn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc)) | ||
559 | #define BP_LRADC_CHn_TOGGLE 31 | ||
560 | #define BM_LRADC_CHn_TOGGLE 0x80000000 | ||
561 | #define BF_LRADC_CHn_TOGGLE(v) (((v) << 31) & 0x80000000) | ||
562 | #define BP_LRADC_CHn_ACCUMULATE 29 | ||
563 | #define BM_LRADC_CHn_ACCUMULATE 0x20000000 | ||
564 | #define BF_LRADC_CHn_ACCUMULATE(v) (((v) << 29) & 0x20000000) | ||
565 | #define BP_LRADC_CHn_NUM_SAMPLES 24 | ||
566 | #define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000 | ||
567 | #define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000) | ||
568 | #define BP_LRADC_CHn_VALUE 0 | ||
569 | #define BM_LRADC_CHn_VALUE 0x3ffff | ||
570 | #define BF_LRADC_CHn_VALUE(v) (((v) << 0) & 0x3ffff) | ||
571 | |||
572 | #endif /* __HEADERGEN__STMP3600__LRADC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h new file mode 100644 index 0000000000..3ba723eab3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__MEMCPY__H__ | ||
24 | #define __HEADERGEN__STMP3600__MEMCPY__H__ | ||
25 | |||
26 | #define REGS_MEMCPY_BASE (0x80014000) | ||
27 | |||
28 | #define REGS_MEMCPY_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_MEMCPY_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_MEMCPY_CTRL (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x0)) | ||
36 | #define HW_MEMCPY_CTRL_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x4)) | ||
37 | #define HW_MEMCPY_CTRL_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x8)) | ||
38 | #define HW_MEMCPY_CTRL_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0xc)) | ||
39 | #define BP_MEMCPY_CTRL_SFTRST 31 | ||
40 | #define BM_MEMCPY_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_MEMCPY_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_MEMCPY_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_MEMCPY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_MEMCPY_CTRL_SFTRST_V(v) ((BV_MEMCPY_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_MEMCPY_CTRL_CLKGATE 30 | ||
46 | #define BM_MEMCPY_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_MEMCPY_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_MEMCPY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_MEMCPY_CTRL_CLKGATE_V(v) ((BV_MEMCPY_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_MEMCPY_CTRL_PRESENT 29 | ||
52 | #define BM_MEMCPY_CTRL_PRESENT 0x20000000 | ||
53 | #define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0 | ||
54 | #define BV_MEMCPY_CTRL_PRESENT__AVAILABLE 0x1 | ||
55 | #define BF_MEMCPY_CTRL_PRESENT(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_MEMCPY_CTRL_PRESENT_V(v) ((BV_MEMCPY_CTRL_PRESENT__##v << 29) & 0x20000000) | ||
57 | #define BP_MEMCPY_CTRL_BURST 16 | ||
58 | #define BM_MEMCPY_CTRL_BURST 0x10000 | ||
59 | #define BF_MEMCPY_CTRL_BURST(v) (((v) << 16) & 0x10000) | ||
60 | #define BP_MEMCPY_CTRL_XFER_SIZE 0 | ||
61 | #define BM_MEMCPY_CTRL_XFER_SIZE 0xffff | ||
62 | #define BF_MEMCPY_CTRL_XFER_SIZE(v) (((v) << 0) & 0xffff) | ||
63 | |||
64 | /** | ||
65 | * Register: HW_MEMCPY_DATA | ||
66 | * Address: 0x10 | ||
67 | * SCT: yes | ||
68 | */ | ||
69 | #define HW_MEMCPY_DATA (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x0)) | ||
70 | #define HW_MEMCPY_DATA_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x4)) | ||
71 | #define HW_MEMCPY_DATA_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x8)) | ||
72 | #define HW_MEMCPY_DATA_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0xc)) | ||
73 | #define BP_MEMCPY_DATA_DATA 0 | ||
74 | #define BM_MEMCPY_DATA_DATA 0xffffffff | ||
75 | #define BF_MEMCPY_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
76 | |||
77 | /** | ||
78 | * Register: HW_MEMCPY_DEBUG | ||
79 | * Address: 0x20 | ||
80 | * SCT: no | ||
81 | */ | ||
82 | #define HW_MEMCPY_DEBUG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x20)) | ||
83 | #define BP_MEMCPY_DEBUG_DST_END_CMD 30 | ||
84 | #define BM_MEMCPY_DEBUG_DST_END_CMD 0x40000000 | ||
85 | #define BF_MEMCPY_DEBUG_DST_END_CMD(v) (((v) << 30) & 0x40000000) | ||
86 | #define BP_MEMCPY_DEBUG_DST_KICK 29 | ||
87 | #define BM_MEMCPY_DEBUG_DST_KICK 0x20000000 | ||
88 | #define BF_MEMCPY_DEBUG_DST_KICK(v) (((v) << 29) & 0x20000000) | ||
89 | #define BP_MEMCPY_DEBUG_DST_DMA_REQ 28 | ||
90 | #define BM_MEMCPY_DEBUG_DST_DMA_REQ 0x10000000 | ||
91 | #define BF_MEMCPY_DEBUG_DST_DMA_REQ(v) (((v) << 28) & 0x10000000) | ||
92 | #define BP_MEMCPY_DEBUG_SRC_KICK 25 | ||
93 | #define BM_MEMCPY_DEBUG_SRC_KICK 0x2000000 | ||
94 | #define BF_MEMCPY_DEBUG_SRC_KICK(v) (((v) << 25) & 0x2000000) | ||
95 | #define BP_MEMCPY_DEBUG_SRC_DMA_REQ 24 | ||
96 | #define BM_MEMCPY_DEBUG_SRC_DMA_REQ 0x1000000 | ||
97 | #define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v) (((v) << 24) & 0x1000000) | ||
98 | #define BP_MEMCPY_DEBUG_WRITE_STATE 2 | ||
99 | #define BM_MEMCPY_DEBUG_WRITE_STATE 0xc | ||
100 | #define BF_MEMCPY_DEBUG_WRITE_STATE(v) (((v) << 2) & 0xc) | ||
101 | #define BP_MEMCPY_DEBUG_READ_STATE 0 | ||
102 | #define BM_MEMCPY_DEBUG_READ_STATE 0x3 | ||
103 | #define BF_MEMCPY_DEBUG_READ_STATE(v) (((v) << 0) & 0x3) | ||
104 | |||
105 | #endif /* __HEADERGEN__STMP3600__MEMCPY__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h new file mode 100644 index 0000000000..14b6069060 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h | |||
@@ -0,0 +1,213 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__PINCTRL__H__ | ||
24 | #define __HEADERGEN__STMP3600__PINCTRL__H__ | ||
25 | |||
26 | #define REGS_PINCTRL_BASE (0x80018000) | ||
27 | |||
28 | #define REGS_PINCTRL_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_PINCTRL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_PINCTRL_CTRL_SFTRST 31 | ||
40 | #define BM_PINCTRL_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_PINCTRL_CTRL_CLKGATE 30 | ||
43 | #define BM_PINCTRL_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_PINCTRL_CTRL_PRESENT3 29 | ||
46 | #define BM_PINCTRL_CTRL_PRESENT3 0x20000000 | ||
47 | #define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_PINCTRL_CTRL_PRESENT2 28 | ||
49 | #define BM_PINCTRL_CTRL_PRESENT2 0x10000000 | ||
50 | #define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_PINCTRL_CTRL_PRESENT1 27 | ||
52 | #define BM_PINCTRL_CTRL_PRESENT1 0x8000000 | ||
53 | #define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_PINCTRL_CTRL_PRESENT0 26 | ||
55 | #define BM_PINCTRL_CTRL_PRESENT0 0x4000000 | ||
56 | #define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_PINCTRL_CTRL_IRQOUT3 3 | ||
58 | #define BM_PINCTRL_CTRL_IRQOUT3 0x8 | ||
59 | #define BF_PINCTRL_CTRL_IRQOUT3(v) (((v) << 3) & 0x8) | ||
60 | #define BP_PINCTRL_CTRL_IRQOUT2 2 | ||
61 | #define BM_PINCTRL_CTRL_IRQOUT2 0x4 | ||
62 | #define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4) | ||
63 | #define BP_PINCTRL_CTRL_IRQOUT1 1 | ||
64 | #define BM_PINCTRL_CTRL_IRQOUT1 0x2 | ||
65 | #define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2) | ||
66 | #define BP_PINCTRL_CTRL_IRQOUT0 0 | ||
67 | #define BM_PINCTRL_CTRL_IRQOUT0 0x1 | ||
68 | #define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_PINCTRL_MUXSELLn | ||
72 | * Address: 0x10+n*0x100 | ||
73 | * SCT: yes | ||
74 | */ | ||
75 | #define HW_PINCTRL_MUXSELLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x0)) | ||
76 | #define HW_PINCTRL_MUXSELLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x4)) | ||
77 | #define HW_PINCTRL_MUXSELLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x8)) | ||
78 | #define HW_PINCTRL_MUXSELLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0xc)) | ||
79 | #define BP_PINCTRL_MUXSELLn_BITS 0 | ||
80 | #define BM_PINCTRL_MUXSELLn_BITS 0xffffffff | ||
81 | #define BF_PINCTRL_MUXSELLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_PINCTRL_MUXSELHn | ||
85 | * Address: 0x20+n*0x100 | ||
86 | * SCT: yes | ||
87 | */ | ||
88 | #define HW_PINCTRL_MUXSELHn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x0)) | ||
89 | #define HW_PINCTRL_MUXSELHn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x4)) | ||
90 | #define HW_PINCTRL_MUXSELHn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x8)) | ||
91 | #define HW_PINCTRL_MUXSELHn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0xc)) | ||
92 | #define BP_PINCTRL_MUXSELHn_BITS 0 | ||
93 | #define BM_PINCTRL_MUXSELHn_BITS 0xffffffff | ||
94 | #define BF_PINCTRL_MUXSELHn_BITS(v) (((v) << 0) & 0xffffffff) | ||
95 | |||
96 | /** | ||
97 | * Register: HW_PINCTRL_DRIVEn | ||
98 | * Address: 0x30+n*0x100 | ||
99 | * SCT: yes | ||
100 | */ | ||
101 | #define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x0)) | ||
102 | #define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x4)) | ||
103 | #define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x8)) | ||
104 | #define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0xc)) | ||
105 | #define BP_PINCTRL_DRIVEn_BITS 0 | ||
106 | #define BM_PINCTRL_DRIVEn_BITS 0xffffffff | ||
107 | #define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_PINCTRL_DOUTn | ||
111 | * Address: 0x50+n*0x100 | ||
112 | * SCT: yes | ||
113 | */ | ||
114 | #define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x0)) | ||
115 | #define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x4)) | ||
116 | #define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x8)) | ||
117 | #define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0xc)) | ||
118 | #define BP_PINCTRL_DOUTn_BITS 0 | ||
119 | #define BM_PINCTRL_DOUTn_BITS 0xffffffff | ||
120 | #define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_PINCTRL_DINn | ||
124 | * Address: 0x60+n*0x100 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x0)) | ||
128 | #define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x4)) | ||
129 | #define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x8)) | ||
130 | #define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0xc)) | ||
131 | #define BP_PINCTRL_DINn_BITS 0 | ||
132 | #define BM_PINCTRL_DINn_BITS 0xffffffff | ||
133 | #define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff) | ||
134 | |||
135 | /** | ||
136 | * Register: HW_PINCTRL_DOEn | ||
137 | * Address: 0x70+n*0x100 | ||
138 | * SCT: yes | ||
139 | */ | ||
140 | #define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x0)) | ||
141 | #define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x4)) | ||
142 | #define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x8)) | ||
143 | #define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0xc)) | ||
144 | #define BP_PINCTRL_DOEn_BITS 0 | ||
145 | #define BM_PINCTRL_DOEn_BITS 0xffffffff | ||
146 | #define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
147 | |||
148 | /** | ||
149 | * Register: HW_PINCTRL_PIN2IRQn | ||
150 | * Address: 0x80+n*0x100 | ||
151 | * SCT: yes | ||
152 | */ | ||
153 | #define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x0)) | ||
154 | #define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x4)) | ||
155 | #define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x8)) | ||
156 | #define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0xc)) | ||
157 | #define BP_PINCTRL_PIN2IRQn_BITS 0 | ||
158 | #define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff | ||
159 | #define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff) | ||
160 | |||
161 | /** | ||
162 | * Register: HW_PINCTRL_IRQENn | ||
163 | * Address: 0x90+n*0x100 | ||
164 | * SCT: yes | ||
165 | */ | ||
166 | #define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x0)) | ||
167 | #define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x4)) | ||
168 | #define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x8)) | ||
169 | #define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0xc)) | ||
170 | #define BP_PINCTRL_IRQENn_BITS 0 | ||
171 | #define BM_PINCTRL_IRQENn_BITS 0xffffffff | ||
172 | #define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_PINCTRL_IRQLEVELn | ||
176 | * Address: 0xa0+n*0x100 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x0)) | ||
180 | #define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x4)) | ||
181 | #define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x8)) | ||
182 | #define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0xc)) | ||
183 | #define BP_PINCTRL_IRQLEVELn_BITS 0 | ||
184 | #define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff | ||
185 | #define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
186 | |||
187 | /** | ||
188 | * Register: HW_PINCTRL_IRQPOLn | ||
189 | * Address: 0xb0+n*0x100 | ||
190 | * SCT: yes | ||
191 | */ | ||
192 | #define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x0)) | ||
193 | #define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x4)) | ||
194 | #define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x8)) | ||
195 | #define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0xc)) | ||
196 | #define BP_PINCTRL_IRQPOLn_BITS 0 | ||
197 | #define BM_PINCTRL_IRQPOLn_BITS 0xffffffff | ||
198 | #define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
199 | |||
200 | /** | ||
201 | * Register: HW_PINCTRL_IRQSTATn | ||
202 | * Address: 0xc0+n*0x100 | ||
203 | * SCT: yes | ||
204 | */ | ||
205 | #define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x0)) | ||
206 | #define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x4)) | ||
207 | #define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x8)) | ||
208 | #define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0xc)) | ||
209 | #define BP_PINCTRL_IRQSTATn_BITS 0 | ||
210 | #define BM_PINCTRL_IRQSTATn_BITS 0xffffffff | ||
211 | #define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff) | ||
212 | |||
213 | #endif /* __HEADERGEN__STMP3600__PINCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-power.h b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h new file mode 100644 index 0000000000..577a1c6415 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h | |||
@@ -0,0 +1,484 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__POWER__H__ | ||
24 | #define __HEADERGEN__STMP3600__POWER__H__ | ||
25 | |||
26 | #define REGS_POWER_BASE (0x80044000) | ||
27 | |||
28 | #define REGS_POWER_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_POWER_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_POWER_CTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0)) | ||
36 | #define HW_POWER_CTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4)) | ||
37 | #define HW_POWER_CTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8)) | ||
38 | #define HW_POWER_CTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc)) | ||
39 | #define BP_POWER_CTRL_CLKGATE 30 | ||
40 | #define BM_POWER_CTRL_CLKGATE 0x40000000 | ||
41 | #define BF_POWER_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
42 | #define BP_POWER_CTRL_BATT_BO_IRQ 8 | ||
43 | #define BM_POWER_CTRL_BATT_BO_IRQ 0x100 | ||
44 | #define BF_POWER_CTRL_BATT_BO_IRQ(v) (((v) << 8) & 0x100) | ||
45 | #define BP_POWER_CTRL_ENIRQBATT_BO 7 | ||
46 | #define BM_POWER_CTRL_ENIRQBATT_BO 0x80 | ||
47 | #define BF_POWER_CTRL_ENIRQBATT_BO(v) (((v) << 7) & 0x80) | ||
48 | #define BP_POWER_CTRL_VDDIO_BO_IRQ 6 | ||
49 | #define BM_POWER_CTRL_VDDIO_BO_IRQ 0x40 | ||
50 | #define BF_POWER_CTRL_VDDIO_BO_IRQ(v) (((v) << 6) & 0x40) | ||
51 | #define BP_POWER_CTRL_ENIRQVDDIO_BO 5 | ||
52 | #define BM_POWER_CTRL_ENIRQVDDIO_BO 0x20 | ||
53 | #define BF_POWER_CTRL_ENIRQVDDIO_BO(v) (((v) << 5) & 0x20) | ||
54 | #define BP_POWER_CTRL_VDDD_BO_IRQ 4 | ||
55 | #define BM_POWER_CTRL_VDDD_BO_IRQ 0x10 | ||
56 | #define BF_POWER_CTRL_VDDD_BO_IRQ(v) (((v) << 4) & 0x10) | ||
57 | #define BP_POWER_CTRL_ENIRQVDDD_BO 3 | ||
58 | #define BM_POWER_CTRL_ENIRQVDDD_BO 0x8 | ||
59 | #define BF_POWER_CTRL_ENIRQVDDD_BO(v) (((v) << 3) & 0x8) | ||
60 | #define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 2 | ||
61 | #define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x4 | ||
62 | #define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v) (((v) << 2) & 0x4) | ||
63 | #define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 1 | ||
64 | #define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x2 | ||
65 | #define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v) (((v) << 1) & 0x2) | ||
66 | #define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 | ||
67 | #define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x1 | ||
68 | #define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v) (((v) << 0) & 0x1) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_POWER_5VCTRL | ||
72 | * Address: 0x10 | ||
73 | * SCT: yes | ||
74 | */ | ||
75 | #define HW_POWER_5VCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0)) | ||
76 | #define HW_POWER_5VCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4)) | ||
77 | #define HW_POWER_5VCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8)) | ||
78 | #define HW_POWER_5VCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc)) | ||
79 | #define BP_POWER_5VCTRL_PWDN_5VBRNOUT 21 | ||
80 | #define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x200000 | ||
81 | #define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v) (((v) << 21) & 0x200000) | ||
82 | #define BP_POWER_5VCTRL_PWDN_IOBRNOUT 20 | ||
83 | #define BM_POWER_5VCTRL_PWDN_IOBRNOUT 0x100000 | ||
84 | #define BF_POWER_5VCTRL_PWDN_IOBRNOUT(v) (((v) << 20) & 0x100000) | ||
85 | #define BP_POWER_5VCTRL_DISABLE_ILIMIT 19 | ||
86 | #define BM_POWER_5VCTRL_DISABLE_ILIMIT 0x80000 | ||
87 | #define BF_POWER_5VCTRL_DISABLE_ILIMIT(v) (((v) << 19) & 0x80000) | ||
88 | #define BP_POWER_5VCTRL_DCDC_XFER 18 | ||
89 | #define BM_POWER_5VCTRL_DCDC_XFER 0x40000 | ||
90 | #define BF_POWER_5VCTRL_DCDC_XFER(v) (((v) << 18) & 0x40000) | ||
91 | #define BP_POWER_5VCTRL_EN_BATT_PULLDN 17 | ||
92 | #define BM_POWER_5VCTRL_EN_BATT_PULLDN 0x20000 | ||
93 | #define BF_POWER_5VCTRL_EN_BATT_PULLDN(v) (((v) << 17) & 0x20000) | ||
94 | #define BP_POWER_5VCTRL_VBUSVALID_5VDETECT 16 | ||
95 | #define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x10000 | ||
96 | #define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v) (((v) << 16) & 0x10000) | ||
97 | #define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 | ||
98 | #define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x300 | ||
99 | #define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) (((v) << 8) & 0x300) | ||
100 | #define BP_POWER_5VCTRL_USB_SUSPEND_I 7 | ||
101 | #define BM_POWER_5VCTRL_USB_SUSPEND_I 0x80 | ||
102 | #define BF_POWER_5VCTRL_USB_SUSPEND_I(v) (((v) << 7) & 0x80) | ||
103 | #define BP_POWER_5VCTRL_VBUSVALID_TO_B 6 | ||
104 | #define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x40 | ||
105 | #define BF_POWER_5VCTRL_VBUSVALID_TO_B(v) (((v) << 6) & 0x40) | ||
106 | #define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO 5 | ||
107 | #define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x20 | ||
108 | #define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v) (((v) << 5) & 0x20) | ||
109 | #define BP_POWER_5VCTRL_OTG_PWRUP_CMPS 4 | ||
110 | #define BM_POWER_5VCTRL_OTG_PWRUP_CMPS 0x10 | ||
111 | #define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v) (((v) << 4) & 0x10) | ||
112 | #define BP_POWER_5VCTRL_EN_DCDC2 3 | ||
113 | #define BM_POWER_5VCTRL_EN_DCDC2 0x8 | ||
114 | #define BF_POWER_5VCTRL_EN_DCDC2(v) (((v) << 3) & 0x8) | ||
115 | #define BP_POWER_5VCTRL_PWD_VDDD_LINREG 2 | ||
116 | #define BM_POWER_5VCTRL_PWD_VDDD_LINREG 0x4 | ||
117 | #define BF_POWER_5VCTRL_PWD_VDDD_LINREG(v) (((v) << 2) & 0x4) | ||
118 | #define BP_POWER_5VCTRL_EN_DCDC1 1 | ||
119 | #define BM_POWER_5VCTRL_EN_DCDC1 0x2 | ||
120 | #define BF_POWER_5VCTRL_EN_DCDC1(v) (((v) << 1) & 0x2) | ||
121 | #define BP_POWER_5VCTRL_LINREG_OFFSET 0 | ||
122 | #define BM_POWER_5VCTRL_LINREG_OFFSET 0x1 | ||
123 | #define BF_POWER_5VCTRL_LINREG_OFFSET(v) (((v) << 0) & 0x1) | ||
124 | |||
125 | /** | ||
126 | * Register: HW_POWER_MINPWR | ||
127 | * Address: 0x20 | ||
128 | * SCT: yes | ||
129 | */ | ||
130 | #define HW_POWER_MINPWR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0)) | ||
131 | #define HW_POWER_MINPWR_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4)) | ||
132 | #define HW_POWER_MINPWR_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8)) | ||
133 | #define HW_POWER_MINPWR_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc)) | ||
134 | #define BP_POWER_MINPWR_TEST_DISCHRG_VBUS 23 | ||
135 | #define BM_POWER_MINPWR_TEST_DISCHRG_VBUS 0x800000 | ||
136 | #define BF_POWER_MINPWR_TEST_DISCHRG_VBUS(v) (((v) << 23) & 0x800000) | ||
137 | #define BP_POWER_MINPWR_TEST_CHRG_VBUS 22 | ||
138 | #define BM_POWER_MINPWR_TEST_CHRG_VBUS 0x400000 | ||
139 | #define BF_POWER_MINPWR_TEST_CHRG_VBUS(v) (((v) << 22) & 0x400000) | ||
140 | #define BP_POWER_MINPWR_DC2_TST 21 | ||
141 | #define BM_POWER_MINPWR_DC2_TST 0x200000 | ||
142 | #define BF_POWER_MINPWR_DC2_TST(v) (((v) << 21) & 0x200000) | ||
143 | #define BP_POWER_MINPWR_DC1_TST 20 | ||
144 | #define BM_POWER_MINPWR_DC1_TST 0x100000 | ||
145 | #define BF_POWER_MINPWR_DC1_TST(v) (((v) << 20) & 0x100000) | ||
146 | #define BP_POWER_MINPWR_PERIPHERALSWOFF 19 | ||
147 | #define BM_POWER_MINPWR_PERIPHERALSWOFF 0x80000 | ||
148 | #define BF_POWER_MINPWR_PERIPHERALSWOFF(v) (((v) << 19) & 0x80000) | ||
149 | #define BP_POWER_MINPWR_TOGGLE_DIF 18 | ||
150 | #define BM_POWER_MINPWR_TOGGLE_DIF 0x40000 | ||
151 | #define BF_POWER_MINPWR_TOGGLE_DIF(v) (((v) << 18) & 0x40000) | ||
152 | #define BP_POWER_MINPWR_DISABLE_VDDIOSTEP 17 | ||
153 | #define BM_POWER_MINPWR_DISABLE_VDDIOSTEP 0x20000 | ||
154 | #define BF_POWER_MINPWR_DISABLE_VDDIOSTEP(v) (((v) << 17) & 0x20000) | ||
155 | #define BP_POWER_MINPWR_DISABLE_VDDSTEP 16 | ||
156 | #define BM_POWER_MINPWR_DISABLE_VDDSTEP 0x10000 | ||
157 | #define BF_POWER_MINPWR_DISABLE_VDDSTEP(v) (((v) << 16) & 0x10000) | ||
158 | #define BP_POWER_MINPWR_SEL_PLLDIV16CLK 9 | ||
159 | #define BM_POWER_MINPWR_SEL_PLLDIV16CLK 0x200 | ||
160 | #define BF_POWER_MINPWR_SEL_PLLDIV16CLK(v) (((v) << 9) & 0x200) | ||
161 | #define BP_POWER_MINPWR_PWD_VDDIOBO 8 | ||
162 | #define BM_POWER_MINPWR_PWD_VDDIOBO 0x100 | ||
163 | #define BF_POWER_MINPWR_PWD_VDDIOBO(v) (((v) << 8) & 0x100) | ||
164 | #define BP_POWER_MINPWR_LESSANA_I 7 | ||
165 | #define BM_POWER_MINPWR_LESSANA_I 0x80 | ||
166 | #define BF_POWER_MINPWR_LESSANA_I(v) (((v) << 7) & 0x80) | ||
167 | #define BP_POWER_MINPWR_DC1_HALFFETS 6 | ||
168 | #define BM_POWER_MINPWR_DC1_HALFFETS 0x40 | ||
169 | #define BF_POWER_MINPWR_DC1_HALFFETS(v) (((v) << 6) & 0x40) | ||
170 | #define BP_POWER_MINPWR_DC2_STOPCLK 5 | ||
171 | #define BM_POWER_MINPWR_DC2_STOPCLK 0x20 | ||
172 | #define BF_POWER_MINPWR_DC2_STOPCLK(v) (((v) << 5) & 0x20) | ||
173 | #define BP_POWER_MINPWR_DC1_STOPCLK 4 | ||
174 | #define BM_POWER_MINPWR_DC1_STOPCLK 0x10 | ||
175 | #define BF_POWER_MINPWR_DC1_STOPCLK(v) (((v) << 4) & 0x10) | ||
176 | #define BP_POWER_MINPWR_EN_DC2_PFM 3 | ||
177 | #define BM_POWER_MINPWR_EN_DC2_PFM 0x8 | ||
178 | #define BF_POWER_MINPWR_EN_DC2_PFM(v) (((v) << 3) & 0x8) | ||
179 | #define BP_POWER_MINPWR_EN_DC1_PFM 2 | ||
180 | #define BM_POWER_MINPWR_EN_DC1_PFM 0x4 | ||
181 | #define BF_POWER_MINPWR_EN_DC1_PFM(v) (((v) << 2) & 0x4) | ||
182 | #define BP_POWER_MINPWR_DC2_HALFCLK 1 | ||
183 | #define BM_POWER_MINPWR_DC2_HALFCLK 0x2 | ||
184 | #define BF_POWER_MINPWR_DC2_HALFCLK(v) (((v) << 1) & 0x2) | ||
185 | #define BP_POWER_MINPWR_DC1_HALFCLK 0 | ||
186 | #define BM_POWER_MINPWR_DC1_HALFCLK 0x1 | ||
187 | #define BF_POWER_MINPWR_DC1_HALFCLK(v) (((v) << 0) & 0x1) | ||
188 | |||
189 | /** | ||
190 | * Register: HW_POWER_BATTCHRG | ||
191 | * Address: 0x30 | ||
192 | * SCT: yes | ||
193 | */ | ||
194 | #define HW_POWER_BATTCHRG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0)) | ||
195 | #define HW_POWER_BATTCHRG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4)) | ||
196 | #define HW_POWER_BATTCHRG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8)) | ||
197 | #define HW_POWER_BATTCHRG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc)) | ||
198 | #define BP_POWER_BATTCHRG_CHRG_STS_OFF 19 | ||
199 | #define BM_POWER_BATTCHRG_CHRG_STS_OFF 0x80000 | ||
200 | #define BF_POWER_BATTCHRG_CHRG_STS_OFF(v) (((v) << 19) & 0x80000) | ||
201 | #define BP_POWER_BATTCHRG_LIION_4P1 18 | ||
202 | #define BM_POWER_BATTCHRG_LIION_4P1 0x40000 | ||
203 | #define BF_POWER_BATTCHRG_LIION_4P1(v) (((v) << 18) & 0x40000) | ||
204 | #define BP_POWER_BATTCHRG_USE_EXTERN_R 17 | ||
205 | #define BM_POWER_BATTCHRG_USE_EXTERN_R 0x20000 | ||
206 | #define BF_POWER_BATTCHRG_USE_EXTERN_R(v) (((v) << 17) & 0x20000) | ||
207 | #define BP_POWER_BATTCHRG_PWD_BATTCHRG 16 | ||
208 | #define BM_POWER_BATTCHRG_PWD_BATTCHRG 0x10000 | ||
209 | #define BF_POWER_BATTCHRG_PWD_BATTCHRG(v) (((v) << 16) & 0x10000) | ||
210 | #define BP_POWER_BATTCHRG_STOP_ILIMIT 8 | ||
211 | #define BM_POWER_BATTCHRG_STOP_ILIMIT 0xf00 | ||
212 | #define BF_POWER_BATTCHRG_STOP_ILIMIT(v) (((v) << 8) & 0xf00) | ||
213 | #define BP_POWER_BATTCHRG_BATTCHRG_I 0 | ||
214 | #define BM_POWER_BATTCHRG_BATTCHRG_I 0x3f | ||
215 | #define BF_POWER_BATTCHRG_BATTCHRG_I(v) (((v) << 0) & 0x3f) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_POWER_VDDCTRL | ||
219 | * Address: 0x40 | ||
220 | * SCT: no | ||
221 | */ | ||
222 | #define HW_POWER_VDDCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40)) | ||
223 | #define BP_POWER_VDDCTRL_VDDIO_BO 24 | ||
224 | #define BM_POWER_VDDCTRL_VDDIO_BO 0x1f000000 | ||
225 | #define BF_POWER_VDDCTRL_VDDIO_BO(v) (((v) << 24) & 0x1f000000) | ||
226 | #define BP_POWER_VDDCTRL_VDDIO_TRG 16 | ||
227 | #define BM_POWER_VDDCTRL_VDDIO_TRG 0x1f0000 | ||
228 | #define BF_POWER_VDDCTRL_VDDIO_TRG(v) (((v) << 16) & 0x1f0000) | ||
229 | #define BP_POWER_VDDCTRL_VDDD_BO 8 | ||
230 | #define BM_POWER_VDDCTRL_VDDD_BO 0x1f00 | ||
231 | #define BF_POWER_VDDCTRL_VDDD_BO(v) (((v) << 8) & 0x1f00) | ||
232 | #define BP_POWER_VDDCTRL_VDDD_TRG 0 | ||
233 | #define BM_POWER_VDDCTRL_VDDD_TRG 0x1f | ||
234 | #define BF_POWER_VDDCTRL_VDDD_TRG(v) (((v) << 0) & 0x1f) | ||
235 | |||
236 | /** | ||
237 | * Register: HW_POWER_DC1MULTOUT | ||
238 | * Address: 0x50 | ||
239 | * SCT: no | ||
240 | */ | ||
241 | #define HW_POWER_DC1MULTOUT (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50)) | ||
242 | #define BP_POWER_DC1MULTOUT_FUNCV 16 | ||
243 | #define BM_POWER_DC1MULTOUT_FUNCV 0x1ff0000 | ||
244 | #define BF_POWER_DC1MULTOUT_FUNCV(v) (((v) << 16) & 0x1ff0000) | ||
245 | #define BP_POWER_DC1MULTOUT_EN_BATADJ 8 | ||
246 | #define BM_POWER_DC1MULTOUT_EN_BATADJ 0x100 | ||
247 | #define BF_POWER_DC1MULTOUT_EN_BATADJ(v) (((v) << 8) & 0x100) | ||
248 | #define BP_POWER_DC1MULTOUT_ADJTN 0 | ||
249 | #define BM_POWER_DC1MULTOUT_ADJTN 0xf | ||
250 | #define BF_POWER_DC1MULTOUT_ADJTN(v) (((v) << 0) & 0xf) | ||
251 | |||
252 | /** | ||
253 | * Register: HW_POWER_DC1LIMITS | ||
254 | * Address: 0x60 | ||
255 | * SCT: no | ||
256 | */ | ||
257 | #define HW_POWER_DC1LIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60)) | ||
258 | #define BP_POWER_DC1LIMITS_EN_PFETOFF 24 | ||
259 | #define BM_POWER_DC1LIMITS_EN_PFETOFF 0x1000000 | ||
260 | #define BF_POWER_DC1LIMITS_EN_PFETOFF(v) (((v) << 24) & 0x1000000) | ||
261 | #define BP_POWER_DC1LIMITS_POSLIMIT_BOOST 16 | ||
262 | #define BM_POWER_DC1LIMITS_POSLIMIT_BOOST 0x7f0000 | ||
263 | #define BF_POWER_DC1LIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) | ||
264 | #define BP_POWER_DC1LIMITS_POSLIMIT_BUCK 8 | ||
265 | #define BM_POWER_DC1LIMITS_POSLIMIT_BUCK 0x7f00 | ||
266 | #define BF_POWER_DC1LIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
267 | #define BP_POWER_DC1LIMITS_NEGLIMIT 0 | ||
268 | #define BM_POWER_DC1LIMITS_NEGLIMIT 0x7f | ||
269 | #define BF_POWER_DC1LIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
270 | |||
271 | /** | ||
272 | * Register: HW_POWER_DC2LIMITS | ||
273 | * Address: 0x70 | ||
274 | * SCT: no | ||
275 | */ | ||
276 | #define HW_POWER_DC2LIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70)) | ||
277 | #define BP_POWER_DC2LIMITS_EN_BOOST 24 | ||
278 | #define BM_POWER_DC2LIMITS_EN_BOOST 0x1000000 | ||
279 | #define BF_POWER_DC2LIMITS_EN_BOOST(v) (((v) << 24) & 0x1000000) | ||
280 | #define BP_POWER_DC2LIMITS_POSLIMIT_BOOST 16 | ||
281 | #define BM_POWER_DC2LIMITS_POSLIMIT_BOOST 0x7f0000 | ||
282 | #define BF_POWER_DC2LIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) | ||
283 | #define BP_POWER_DC2LIMITS_POSLIMIT_BUCK 8 | ||
284 | #define BM_POWER_DC2LIMITS_POSLIMIT_BUCK 0x7f00 | ||
285 | #define BF_POWER_DC2LIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
286 | #define BP_POWER_DC2LIMITS_NEGLIMIT 0 | ||
287 | #define BM_POWER_DC2LIMITS_NEGLIMIT 0x7f | ||
288 | #define BF_POWER_DC2LIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
289 | |||
290 | /** | ||
291 | * Register: HW_POWER_LOOPCTRL | ||
292 | * Address: 0x80 | ||
293 | * SCT: yes | ||
294 | */ | ||
295 | #define HW_POWER_LOOPCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x0)) | ||
296 | #define HW_POWER_LOOPCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x4)) | ||
297 | #define HW_POWER_LOOPCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x8)) | ||
298 | #define HW_POWER_LOOPCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0xc)) | ||
299 | #define BP_POWER_LOOPCTRL_TRAN_NOHYST 30 | ||
300 | #define BM_POWER_LOOPCTRL_TRAN_NOHYST 0x40000000 | ||
301 | #define BF_POWER_LOOPCTRL_TRAN_NOHYST(v) (((v) << 30) & 0x40000000) | ||
302 | #define BP_POWER_LOOPCTRL_HYST_SIGN 29 | ||
303 | #define BM_POWER_LOOPCTRL_HYST_SIGN 0x20000000 | ||
304 | #define BF_POWER_LOOPCTRL_HYST_SIGN(v) (((v) << 29) & 0x20000000) | ||
305 | #define BP_POWER_LOOPCTRL_EN_CMP_HYST 28 | ||
306 | #define BM_POWER_LOOPCTRL_EN_CMP_HYST 0x10000000 | ||
307 | #define BF_POWER_LOOPCTRL_EN_CMP_HYST(v) (((v) << 28) & 0x10000000) | ||
308 | #define BP_POWER_LOOPCTRL_EN_DC2_RCSCALE 27 | ||
309 | #define BM_POWER_LOOPCTRL_EN_DC2_RCSCALE 0x8000000 | ||
310 | #define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(v) (((v) << 27) & 0x8000000) | ||
311 | #define BP_POWER_LOOPCTRL_EN_DC1_RCSCALE 26 | ||
312 | #define BM_POWER_LOOPCTRL_EN_DC1_RCSCALE 0x4000000 | ||
313 | #define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(v) (((v) << 26) & 0x4000000) | ||
314 | #define BP_POWER_LOOPCTRL_RC_SIGN 25 | ||
315 | #define BM_POWER_LOOPCTRL_RC_SIGN 0x2000000 | ||
316 | #define BF_POWER_LOOPCTRL_RC_SIGN(v) (((v) << 25) & 0x2000000) | ||
317 | #define BP_POWER_LOOPCTRL_EN_RCSCALE 24 | ||
318 | #define BM_POWER_LOOPCTRL_EN_RCSCALE 0x1000000 | ||
319 | #define BF_POWER_LOOPCTRL_EN_RCSCALE(v) (((v) << 24) & 0x1000000) | ||
320 | #define BP_POWER_LOOPCTRL_DC2_FF 20 | ||
321 | #define BM_POWER_LOOPCTRL_DC2_FF 0x700000 | ||
322 | #define BF_POWER_LOOPCTRL_DC2_FF(v) (((v) << 20) & 0x700000) | ||
323 | #define BP_POWER_LOOPCTRL_DC2_R 16 | ||
324 | #define BM_POWER_LOOPCTRL_DC2_R 0xf0000 | ||
325 | #define BF_POWER_LOOPCTRL_DC2_R(v) (((v) << 16) & 0xf0000) | ||
326 | #define BP_POWER_LOOPCTRL_DC2_C 12 | ||
327 | #define BM_POWER_LOOPCTRL_DC2_C 0x3000 | ||
328 | #define BF_POWER_LOOPCTRL_DC2_C(v) (((v) << 12) & 0x3000) | ||
329 | #define BP_POWER_LOOPCTRL_DC1_FF 8 | ||
330 | #define BM_POWER_LOOPCTRL_DC1_FF 0x700 | ||
331 | #define BF_POWER_LOOPCTRL_DC1_FF(v) (((v) << 8) & 0x700) | ||
332 | #define BP_POWER_LOOPCTRL_DC1_R 4 | ||
333 | #define BM_POWER_LOOPCTRL_DC1_R 0xf0 | ||
334 | #define BF_POWER_LOOPCTRL_DC1_R(v) (((v) << 4) & 0xf0) | ||
335 | #define BP_POWER_LOOPCTRL_DC1_C 0 | ||
336 | #define BM_POWER_LOOPCTRL_DC1_C 0x3 | ||
337 | #define BF_POWER_LOOPCTRL_DC1_C(v) (((v) << 0) & 0x3) | ||
338 | |||
339 | /** | ||
340 | * Register: HW_POWER_STS | ||
341 | * Address: 0x90 | ||
342 | * SCT: no | ||
343 | */ | ||
344 | #define HW_POWER_STS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90)) | ||
345 | #define BP_POWER_STS_BATT_CHRG_PRESENT 31 | ||
346 | #define BM_POWER_STS_BATT_CHRG_PRESENT 0x80000000 | ||
347 | #define BF_POWER_STS_BATT_CHRG_PRESENT(v) (((v) << 31) & 0x80000000) | ||
348 | #define BP_POWER_STS_MODE 20 | ||
349 | #define BM_POWER_STS_MODE 0x300000 | ||
350 | #define BF_POWER_STS_MODE(v) (((v) << 20) & 0x300000) | ||
351 | #define BP_POWER_STS_BATT_BO 16 | ||
352 | #define BM_POWER_STS_BATT_BO 0x10000 | ||
353 | #define BF_POWER_STS_BATT_BO(v) (((v) << 16) & 0x10000) | ||
354 | #define BP_POWER_STS_CHRGSTS 14 | ||
355 | #define BM_POWER_STS_CHRGSTS 0x4000 | ||
356 | #define BF_POWER_STS_CHRGSTS(v) (((v) << 14) & 0x4000) | ||
357 | #define BP_POWER_STS_DC2_OK 13 | ||
358 | #define BM_POWER_STS_DC2_OK 0x2000 | ||
359 | #define BF_POWER_STS_DC2_OK(v) (((v) << 13) & 0x2000) | ||
360 | #define BP_POWER_STS_DC1_OK 12 | ||
361 | #define BM_POWER_STS_DC1_OK 0x1000 | ||
362 | #define BF_POWER_STS_DC1_OK(v) (((v) << 12) & 0x1000) | ||
363 | #define BP_POWER_STS_VDDIO_BO 9 | ||
364 | #define BM_POWER_STS_VDDIO_BO 0x200 | ||
365 | #define BF_POWER_STS_VDDIO_BO(v) (((v) << 9) & 0x200) | ||
366 | #define BP_POWER_STS_VDDD_BO 8 | ||
367 | #define BM_POWER_STS_VDDD_BO 0x100 | ||
368 | #define BF_POWER_STS_VDDD_BO(v) (((v) << 8) & 0x100) | ||
369 | #define BP_POWER_STS_VDD5V_GT_VDDIO 4 | ||
370 | #define BM_POWER_STS_VDD5V_GT_VDDIO 0x10 | ||
371 | #define BF_POWER_STS_VDD5V_GT_VDDIO(v) (((v) << 4) & 0x10) | ||
372 | #define BP_POWER_STS_AVALID 3 | ||
373 | #define BM_POWER_STS_AVALID 0x8 | ||
374 | #define BF_POWER_STS_AVALID(v) (((v) << 3) & 0x8) | ||
375 | #define BP_POWER_STS_BVALID 2 | ||
376 | #define BM_POWER_STS_BVALID 0x4 | ||
377 | #define BF_POWER_STS_BVALID(v) (((v) << 2) & 0x4) | ||
378 | #define BP_POWER_STS_VBUSVALID 1 | ||
379 | #define BM_POWER_STS_VBUSVALID 0x2 | ||
380 | #define BF_POWER_STS_VBUSVALID(v) (((v) << 1) & 0x2) | ||
381 | #define BP_POWER_STS_SESSEND 0 | ||
382 | #define BM_POWER_STS_SESSEND 0x1 | ||
383 | #define BF_POWER_STS_SESSEND(v) (((v) << 0) & 0x1) | ||
384 | |||
385 | /** | ||
386 | * Register: HW_POWER_SPEEDTEMP | ||
387 | * Address: 0xa0 | ||
388 | * SCT: yes | ||
389 | */ | ||
390 | #define HW_POWER_SPEEDTEMP (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0)) | ||
391 | #define HW_POWER_SPEEDTEMP_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4)) | ||
392 | #define HW_POWER_SPEEDTEMP_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8)) | ||
393 | #define HW_POWER_SPEEDTEMP_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc)) | ||
394 | #define BP_POWER_SPEEDTEMP_SPEED_STS1 24 | ||
395 | #define BM_POWER_SPEEDTEMP_SPEED_STS1 0xff000000 | ||
396 | #define BF_POWER_SPEEDTEMP_SPEED_STS1(v) (((v) << 24) & 0xff000000) | ||
397 | #define BP_POWER_SPEEDTEMP_SPEED_STS2 16 | ||
398 | #define BM_POWER_SPEEDTEMP_SPEED_STS2 0xff0000 | ||
399 | #define BF_POWER_SPEEDTEMP_SPEED_STS2(v) (((v) << 16) & 0xff0000) | ||
400 | #define BP_POWER_SPEEDTEMP_TEMP_STS 8 | ||
401 | #define BM_POWER_SPEEDTEMP_TEMP_STS 0xf00 | ||
402 | #define BF_POWER_SPEEDTEMP_TEMP_STS(v) (((v) << 8) & 0xf00) | ||
403 | #define BP_POWER_SPEEDTEMP_SPEED_CTRL 4 | ||
404 | #define BM_POWER_SPEEDTEMP_SPEED_CTRL 0x30 | ||
405 | #define BF_POWER_SPEEDTEMP_SPEED_CTRL(v) (((v) << 4) & 0x30) | ||
406 | #define BP_POWER_SPEEDTEMP_TEMP_CTRL 0 | ||
407 | #define BM_POWER_SPEEDTEMP_TEMP_CTRL 0xf | ||
408 | #define BF_POWER_SPEEDTEMP_TEMP_CTRL(v) (((v) << 0) & 0xf) | ||
409 | |||
410 | /** | ||
411 | * Register: HW_POWER_BATTMONITOR | ||
412 | * Address: 0xb0 | ||
413 | * SCT: no | ||
414 | */ | ||
415 | #define HW_POWER_BATTMONITOR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0)) | ||
416 | #define BP_POWER_BATTMONITOR_BATT_VAL 16 | ||
417 | #define BM_POWER_BATTMONITOR_BATT_VAL 0x3ff0000 | ||
418 | #define BF_POWER_BATTMONITOR_BATT_VAL(v) (((v) << 16) & 0x3ff0000) | ||
419 | #define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT 9 | ||
420 | #define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x200 | ||
421 | #define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200) | ||
422 | #define BP_POWER_BATTMONITOR_BRWNOUT_PWD 8 | ||
423 | #define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x100 | ||
424 | #define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v) (((v) << 8) & 0x100) | ||
425 | #define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 | ||
426 | #define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0xf | ||
427 | #define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) (((v) << 0) & 0xf) | ||
428 | |||
429 | /** | ||
430 | * Register: HW_POWER_RESET | ||
431 | * Address: 0xc0 | ||
432 | * SCT: yes | ||
433 | */ | ||
434 | #define HW_POWER_RESET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0)) | ||
435 | #define HW_POWER_RESET_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4)) | ||
436 | #define HW_POWER_RESET_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8)) | ||
437 | #define HW_POWER_RESET_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc)) | ||
438 | #define BP_POWER_RESET_UNLOCK 16 | ||
439 | #define BM_POWER_RESET_UNLOCK 0xffff0000 | ||
440 | #define BV_POWER_RESET_UNLOCK__KEY 0x3e77 | ||
441 | #define BF_POWER_RESET_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
442 | #define BF_POWER_RESET_UNLOCK_V(v) ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000) | ||
443 | #define BP_POWER_RESET_PWD_OFF 4 | ||
444 | #define BM_POWER_RESET_PWD_OFF 0x10 | ||
445 | #define BF_POWER_RESET_PWD_OFF(v) (((v) << 4) & 0x10) | ||
446 | #define BP_POWER_RESET_POR 3 | ||
447 | #define BM_POWER_RESET_POR 0x8 | ||
448 | #define BF_POWER_RESET_POR(v) (((v) << 3) & 0x8) | ||
449 | #define BP_POWER_RESET_PWD 2 | ||
450 | #define BM_POWER_RESET_PWD 0x4 | ||
451 | #define BF_POWER_RESET_PWD(v) (((v) << 2) & 0x4) | ||
452 | #define BP_POWER_RESET_RST_DIG 1 | ||
453 | #define BM_POWER_RESET_RST_DIG 0x2 | ||
454 | #define BF_POWER_RESET_RST_DIG(v) (((v) << 1) & 0x2) | ||
455 | #define BP_POWER_RESET_RST_ALL 0 | ||
456 | #define BM_POWER_RESET_RST_ALL 0x1 | ||
457 | #define BF_POWER_RESET_RST_ALL(v) (((v) << 0) & 0x1) | ||
458 | |||
459 | /** | ||
460 | * Register: HW_POWER_DEBUG | ||
461 | * Address: 0xd0 | ||
462 | * SCT: yes | ||
463 | */ | ||
464 | #define HW_POWER_DEBUG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0)) | ||
465 | #define HW_POWER_DEBUG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4)) | ||
466 | #define HW_POWER_DEBUG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8)) | ||
467 | #define HW_POWER_DEBUG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc)) | ||
468 | #define BP_POWER_DEBUG_ENCTRLVBUS 4 | ||
469 | #define BM_POWER_DEBUG_ENCTRLVBUS 0x10 | ||
470 | #define BF_POWER_DEBUG_ENCTRLVBUS(v) (((v) << 4) & 0x10) | ||
471 | #define BP_POWER_DEBUG_VBUSVALIDPIOLOCK 3 | ||
472 | #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x8 | ||
473 | #define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v) (((v) << 3) & 0x8) | ||
474 | #define BP_POWER_DEBUG_AVALIDPIOLOCK 2 | ||
475 | #define BM_POWER_DEBUG_AVALIDPIOLOCK 0x4 | ||
476 | #define BF_POWER_DEBUG_AVALIDPIOLOCK(v) (((v) << 2) & 0x4) | ||
477 | #define BP_POWER_DEBUG_BVALIDPIOLOCK 1 | ||
478 | #define BM_POWER_DEBUG_BVALIDPIOLOCK 0x2 | ||
479 | #define BF_POWER_DEBUG_BVALIDPIOLOCK(v) (((v) << 1) & 0x2) | ||
480 | #define BP_POWER_DEBUG_SESSENDPIOLOCK 0 | ||
481 | #define BM_POWER_DEBUG_SESSENDPIOLOCK 0x1 | ||
482 | #define BF_POWER_DEBUG_SESSENDPIOLOCK(v) (((v) << 0) & 0x1) | ||
483 | |||
484 | #endif /* __HEADERGEN__STMP3600__POWER__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h new file mode 100644 index 0000000000..72d456fd10 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h | |||
@@ -0,0 +1,134 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__PWM__H__ | ||
24 | #define __HEADERGEN__STMP3600__PWM__H__ | ||
25 | |||
26 | #define REGS_PWM_BASE (0x80064000) | ||
27 | |||
28 | #define REGS_PWM_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_PWM_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_PWM_CTRL (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0)) | ||
36 | #define HW_PWM_CTRL_SET (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4)) | ||
37 | #define HW_PWM_CTRL_CLR (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8)) | ||
38 | #define HW_PWM_CTRL_TOG (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc)) | ||
39 | #define BP_PWM_CTRL_SFTRST 31 | ||
40 | #define BM_PWM_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_PWM_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_PWM_CTRL_CLKGATE 30 | ||
43 | #define BM_PWM_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_PWM_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_PWM_CTRL_PWM4_PRESENT 29 | ||
46 | #define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 | ||
47 | #define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_PWM_CTRL_PWM3_PRESENT 28 | ||
49 | #define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 | ||
50 | #define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_PWM_CTRL_PWM2_PRESENT 27 | ||
52 | #define BM_PWM_CTRL_PWM2_PRESENT 0x8000000 | ||
53 | #define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_PWM_CTRL_PWM1_PRESENT 26 | ||
55 | #define BM_PWM_CTRL_PWM1_PRESENT 0x4000000 | ||
56 | #define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_PWM_CTRL_PWM0_PRESENT 25 | ||
58 | #define BM_PWM_CTRL_PWM0_PRESENT 0x2000000 | ||
59 | #define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_PWM_CTRL_PWM4_ENABLE 4 | ||
61 | #define BM_PWM_CTRL_PWM4_ENABLE 0x10 | ||
62 | #define BF_PWM_CTRL_PWM4_ENABLE(v) (((v) << 4) & 0x10) | ||
63 | #define BP_PWM_CTRL_PWM3_ENABLE 3 | ||
64 | #define BM_PWM_CTRL_PWM3_ENABLE 0x8 | ||
65 | #define BF_PWM_CTRL_PWM3_ENABLE(v) (((v) << 3) & 0x8) | ||
66 | #define BP_PWM_CTRL_PWM2_ENABLE 2 | ||
67 | #define BM_PWM_CTRL_PWM2_ENABLE 0x4 | ||
68 | #define BF_PWM_CTRL_PWM2_ENABLE(v) (((v) << 2) & 0x4) | ||
69 | #define BP_PWM_CTRL_PWM1_ENABLE 1 | ||
70 | #define BM_PWM_CTRL_PWM1_ENABLE 0x2 | ||
71 | #define BF_PWM_CTRL_PWM1_ENABLE(v) (((v) << 1) & 0x2) | ||
72 | #define BP_PWM_CTRL_PWM0_ENABLE 0 | ||
73 | #define BM_PWM_CTRL_PWM0_ENABLE 0x1 | ||
74 | #define BF_PWM_CTRL_PWM0_ENABLE(v) (((v) << 0) & 0x1) | ||
75 | |||
76 | /** | ||
77 | * Register: HW_PWM_ACTIVEn | ||
78 | * Address: 0x10+n*0x20 | ||
79 | * SCT: yes | ||
80 | */ | ||
81 | #define HW_PWM_ACTIVEn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0)) | ||
82 | #define HW_PWM_ACTIVEn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4)) | ||
83 | #define HW_PWM_ACTIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8)) | ||
84 | #define HW_PWM_ACTIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc)) | ||
85 | #define BP_PWM_ACTIVEn_INACTIVE 16 | ||
86 | #define BM_PWM_ACTIVEn_INACTIVE 0xffff0000 | ||
87 | #define BF_PWM_ACTIVEn_INACTIVE(v) (((v) << 16) & 0xffff0000) | ||
88 | #define BP_PWM_ACTIVEn_ACTIVE 0 | ||
89 | #define BM_PWM_ACTIVEn_ACTIVE 0xffff | ||
90 | #define BF_PWM_ACTIVEn_ACTIVE(v) (((v) << 0) & 0xffff) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_PWM_PERIODn | ||
94 | * Address: 0x20+n*0x20 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_PWM_PERIODn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0)) | ||
98 | #define HW_PWM_PERIODn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4)) | ||
99 | #define HW_PWM_PERIODn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8)) | ||
100 | #define HW_PWM_PERIODn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc)) | ||
101 | #define BP_PWM_PERIODn_MATT 23 | ||
102 | #define BM_PWM_PERIODn_MATT 0x800000 | ||
103 | #define BF_PWM_PERIODn_MATT(v) (((v) << 23) & 0x800000) | ||
104 | #define BP_PWM_PERIODn_CDIV 20 | ||
105 | #define BM_PWM_PERIODn_CDIV 0x700000 | ||
106 | #define BV_PWM_PERIODn_CDIV__DIV_1 0x0 | ||
107 | #define BV_PWM_PERIODn_CDIV__DIV_2 0x1 | ||
108 | #define BV_PWM_PERIODn_CDIV__DIV_4 0x2 | ||
109 | #define BV_PWM_PERIODn_CDIV__DIV_8 0x3 | ||
110 | #define BV_PWM_PERIODn_CDIV__DIV_16 0x4 | ||
111 | #define BV_PWM_PERIODn_CDIV__DIV_64 0x5 | ||
112 | #define BV_PWM_PERIODn_CDIV__DIV_256 0x6 | ||
113 | #define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 | ||
114 | #define BF_PWM_PERIODn_CDIV(v) (((v) << 20) & 0x700000) | ||
115 | #define BF_PWM_PERIODn_CDIV_V(v) ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000) | ||
116 | #define BP_PWM_PERIODn_INACTIVE_STATE 18 | ||
117 | #define BM_PWM_PERIODn_INACTIVE_STATE 0xc0000 | ||
118 | #define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 | ||
119 | #define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 | ||
120 | #define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 | ||
121 | #define BF_PWM_PERIODn_INACTIVE_STATE(v) (((v) << 18) & 0xc0000) | ||
122 | #define BF_PWM_PERIODn_INACTIVE_STATE_V(v) ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000) | ||
123 | #define BP_PWM_PERIODn_ACTIVE_STATE 16 | ||
124 | #define BM_PWM_PERIODn_ACTIVE_STATE 0x30000 | ||
125 | #define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 | ||
126 | #define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 | ||
127 | #define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 | ||
128 | #define BF_PWM_PERIODn_ACTIVE_STATE(v) (((v) << 16) & 0x30000) | ||
129 | #define BF_PWM_PERIODn_ACTIVE_STATE_V(v) ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000) | ||
130 | #define BP_PWM_PERIODn_PERIOD 0 | ||
131 | #define BM_PWM_PERIODn_PERIOD 0xffff | ||
132 | #define BF_PWM_PERIODn_PERIOD(v) (((v) << 0) & 0xffff) | ||
133 | |||
134 | #endif /* __HEADERGEN__STMP3600__PWM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h new file mode 100644 index 0000000000..8661e75706 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h | |||
@@ -0,0 +1,304 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__RTC__H__ | ||
24 | #define __HEADERGEN__STMP3600__RTC__H__ | ||
25 | |||
26 | #define REGS_RTC_BASE (0x8005c000) | ||
27 | |||
28 | #define REGS_RTC_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_RTC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_RTC_CTRL (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_RTC_CTRL_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_RTC_CTRL_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_RTC_CTRL_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_RTC_CTRL_SFTRST 31 | ||
40 | #define BM_RTC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_RTC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_RTC_CTRL_CLKGATE 30 | ||
43 | #define BM_RTC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_RTC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_RTC_CTRL_CLKDIV 24 | ||
46 | #define BM_RTC_CTRL_CLKDIV 0xf000000 | ||
47 | #define BF_RTC_CTRL_CLKDIV(v) (((v) << 24) & 0xf000000) | ||
48 | #define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG 6 | ||
49 | #define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x40 | ||
50 | #define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NORMAL 0x0 | ||
51 | #define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NO_COPY 0x1 | ||
52 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40) | ||
53 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v) ((BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##v << 6) & 0x40) | ||
54 | #define BP_RTC_CTRL_FORCE_UPDATE 5 | ||
55 | #define BM_RTC_CTRL_FORCE_UPDATE 0x20 | ||
56 | #define BV_RTC_CTRL_FORCE_UPDATE__NORMAL 0x0 | ||
57 | #define BV_RTC_CTRL_FORCE_UPDATE__FORCE_COPY 0x1 | ||
58 | #define BF_RTC_CTRL_FORCE_UPDATE(v) (((v) << 5) & 0x20) | ||
59 | #define BF_RTC_CTRL_FORCE_UPDATE_V(v) ((BV_RTC_CTRL_FORCE_UPDATE__##v << 5) & 0x20) | ||
60 | #define BP_RTC_CTRL_WATCHDOGEN 4 | ||
61 | #define BM_RTC_CTRL_WATCHDOGEN 0x10 | ||
62 | #define BF_RTC_CTRL_WATCHDOGEN(v) (((v) << 4) & 0x10) | ||
63 | #define BP_RTC_CTRL_ONEMSEC_IRQ 3 | ||
64 | #define BM_RTC_CTRL_ONEMSEC_IRQ 0x8 | ||
65 | #define BF_RTC_CTRL_ONEMSEC_IRQ(v) (((v) << 3) & 0x8) | ||
66 | #define BP_RTC_CTRL_ALARM_IRQ 2 | ||
67 | #define BM_RTC_CTRL_ALARM_IRQ 0x4 | ||
68 | #define BF_RTC_CTRL_ALARM_IRQ(v) (((v) << 2) & 0x4) | ||
69 | #define BP_RTC_CTRL_ONEMSEC_IRQ_EN 1 | ||
70 | #define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x2 | ||
71 | #define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v) (((v) << 1) & 0x2) | ||
72 | #define BP_RTC_CTRL_ALARM_IRQ_EN 0 | ||
73 | #define BM_RTC_CTRL_ALARM_IRQ_EN 0x1 | ||
74 | #define BF_RTC_CTRL_ALARM_IRQ_EN(v) (((v) << 0) & 0x1) | ||
75 | |||
76 | /** | ||
77 | * Register: HW_RTC_STAT | ||
78 | * Address: 0x10 | ||
79 | * SCT: no | ||
80 | */ | ||
81 | #define HW_RTC_STAT (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10)) | ||
82 | #define BP_RTC_STAT_RTC_PRESENT 31 | ||
83 | #define BM_RTC_STAT_RTC_PRESENT 0x80000000 | ||
84 | #define BF_RTC_STAT_RTC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
85 | #define BP_RTC_STAT_ALARM_PRESENT 30 | ||
86 | #define BM_RTC_STAT_ALARM_PRESENT 0x40000000 | ||
87 | #define BF_RTC_STAT_ALARM_PRESENT(v) (((v) << 30) & 0x40000000) | ||
88 | #define BP_RTC_STAT_WATCHDOG_PRESENT 29 | ||
89 | #define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 | ||
90 | #define BF_RTC_STAT_WATCHDOG_PRESENT(v) (((v) << 29) & 0x20000000) | ||
91 | #define BP_RTC_STAT_XTAL32768_PRESENT 28 | ||
92 | #define BM_RTC_STAT_XTAL32768_PRESENT 0x10000000 | ||
93 | #define BF_RTC_STAT_XTAL32768_PRESENT(v) (((v) << 28) & 0x10000000) | ||
94 | #define BP_RTC_STAT_STALE_REGS 16 | ||
95 | #define BM_RTC_STAT_STALE_REGS 0x3f0000 | ||
96 | #define BF_RTC_STAT_STALE_REGS(v) (((v) << 16) & 0x3f0000) | ||
97 | #define BP_RTC_STAT_NEW_REGS 8 | ||
98 | #define BM_RTC_STAT_NEW_REGS 0x3f00 | ||
99 | #define BF_RTC_STAT_NEW_REGS(v) (((v) << 8) & 0x3f00) | ||
100 | #define BP_RTC_STAT_FUSE_UNLOCK 1 | ||
101 | #define BM_RTC_STAT_FUSE_UNLOCK 0x2 | ||
102 | #define BF_RTC_STAT_FUSE_UNLOCK(v) (((v) << 1) & 0x2) | ||
103 | #define BP_RTC_STAT_FUSE_DONE 0 | ||
104 | #define BM_RTC_STAT_FUSE_DONE 0x1 | ||
105 | #define BF_RTC_STAT_FUSE_DONE(v) (((v) << 0) & 0x1) | ||
106 | |||
107 | /** | ||
108 | * Register: HW_RTC_MILLISECONDS | ||
109 | * Address: 0x20 | ||
110 | * SCT: yes | ||
111 | */ | ||
112 | #define HW_RTC_MILLISECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0)) | ||
113 | #define HW_RTC_MILLISECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4)) | ||
114 | #define HW_RTC_MILLISECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8)) | ||
115 | #define HW_RTC_MILLISECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc)) | ||
116 | #define BP_RTC_MILLISECONDS_COUNT 0 | ||
117 | #define BM_RTC_MILLISECONDS_COUNT 0xffffffff | ||
118 | #define BF_RTC_MILLISECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
119 | |||
120 | /** | ||
121 | * Register: HW_RTC_SECONDS | ||
122 | * Address: 0x30 | ||
123 | * SCT: yes | ||
124 | */ | ||
125 | #define HW_RTC_SECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0)) | ||
126 | #define HW_RTC_SECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4)) | ||
127 | #define HW_RTC_SECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8)) | ||
128 | #define HW_RTC_SECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc)) | ||
129 | #define BP_RTC_SECONDS_COUNT 0 | ||
130 | #define BM_RTC_SECONDS_COUNT 0xffffffff | ||
131 | #define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_RTC_ALARM | ||
135 | * Address: 0x40 | ||
136 | * SCT: yes | ||
137 | */ | ||
138 | #define HW_RTC_ALARM (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0)) | ||
139 | #define HW_RTC_ALARM_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4)) | ||
140 | #define HW_RTC_ALARM_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8)) | ||
141 | #define HW_RTC_ALARM_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc)) | ||
142 | #define BP_RTC_ALARM_VALUE 0 | ||
143 | #define BM_RTC_ALARM_VALUE 0xffffffff | ||
144 | #define BF_RTC_ALARM_VALUE(v) (((v) << 0) & 0xffffffff) | ||
145 | |||
146 | /** | ||
147 | * Register: HW_RTC_WATCHDOG | ||
148 | * Address: 0x50 | ||
149 | * SCT: yes | ||
150 | */ | ||
151 | #define HW_RTC_WATCHDOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0)) | ||
152 | #define HW_RTC_WATCHDOG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4)) | ||
153 | #define HW_RTC_WATCHDOG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8)) | ||
154 | #define HW_RTC_WATCHDOG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc)) | ||
155 | #define BP_RTC_WATCHDOG_COUNT 0 | ||
156 | #define BM_RTC_WATCHDOG_COUNT 0xffffffff | ||
157 | #define BF_RTC_WATCHDOG_COUNT(v) (((v) << 0) & 0xffffffff) | ||
158 | |||
159 | /** | ||
160 | * Register: HW_RTC_PERSISTENT0 | ||
161 | * Address: 0x60 | ||
162 | * SCT: yes | ||
163 | */ | ||
164 | #define HW_RTC_PERSISTENT0 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0)) | ||
165 | #define HW_RTC_PERSISTENT0_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4)) | ||
166 | #define HW_RTC_PERSISTENT0_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8)) | ||
167 | #define HW_RTC_PERSISTENT0_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc)) | ||
168 | #define BP_RTC_PERSISTENT0_GENERAL 16 | ||
169 | #define BM_RTC_PERSISTENT0_GENERAL 0xffff0000 | ||
170 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_BOOT 0x8000 | ||
171 | #define BV_RTC_PERSISTENT0_GENERAL__ENUMERATE_500MA_TWICE 0x4000 | ||
172 | #define BV_RTC_PERSISTENT0_GENERAL__USB_BOOT_PLAYER_MODE 0x2000 | ||
173 | #define BV_RTC_PERSISTENT0_GENERAL__SKIP_CHECKDISK 0x1000 | ||
174 | #define BV_RTC_PERSISTENT0_GENERAL__USB_LOW_POWER_MODE 0x800 | ||
175 | #define BV_RTC_PERSISTENT0_GENERAL__OTG_HNP_BIT 0x400 | ||
176 | #define BV_RTC_PERSISTENT0_GENERAL__OTG_ATL_ROLE_BIT 0x200 | ||
177 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_HI 0x100 | ||
178 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_LO 0x80 | ||
179 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_3 0x40 | ||
180 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_2 0x20 | ||
181 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_1 0x10 | ||
182 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_0 0x8 | ||
183 | #define BV_RTC_PERSISTENT0_GENERAL__ETM_ENABLE 0x4 | ||
184 | #define BF_RTC_PERSISTENT0_GENERAL(v) (((v) << 16) & 0xffff0000) | ||
185 | #define BF_RTC_PERSISTENT0_GENERAL_V(v) ((BV_RTC_PERSISTENT0_GENERAL__##v << 16) & 0xffff0000) | ||
186 | #define BP_RTC_PERSISTENT0_DCDC_CTRL 6 | ||
187 | #define BM_RTC_PERSISTENT0_DCDC_CTRL 0xffc0 | ||
188 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SD_PRESENT 0x200 | ||
189 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__LOWBAT_3P0 0x100 | ||
190 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SELFBIAS_PWRUP 0x80 | ||
191 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__AUTO_RESTART 0x40 | ||
192 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DETECT_LOWBAT 0x20 | ||
193 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS1 0x10 | ||
194 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS2 0x8 | ||
195 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE 0x4 | ||
196 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DISABLE_XTALSTOP 0x2 | ||
197 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE2 0x1 | ||
198 | #define BF_RTC_PERSISTENT0_DCDC_CTRL(v) (((v) << 6) & 0xffc0) | ||
199 | #define BF_RTC_PERSISTENT0_DCDC_CTRL_V(v) ((BV_RTC_PERSISTENT0_DCDC_CTRL__##v << 6) & 0xffc0) | ||
200 | #define BP_RTC_PERSISTENT0_XTAL32_PDOWN 5 | ||
201 | #define BM_RTC_PERSISTENT0_XTAL32_PDOWN 0x20 | ||
202 | #define BF_RTC_PERSISTENT0_XTAL32_PDOWN(v) (((v) << 5) & 0x20) | ||
203 | #define BP_RTC_PERSISTENT0_XTAL24_PDOWN 4 | ||
204 | #define BM_RTC_PERSISTENT0_XTAL24_PDOWN 0x10 | ||
205 | #define BF_RTC_PERSISTENT0_XTAL24_PDOWN(v) (((v) << 4) & 0x10) | ||
206 | #define BP_RTC_PERSISTENT0_ALARM_WAKE_EN 3 | ||
207 | #define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x8 | ||
208 | #define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v) (((v) << 3) & 0x8) | ||
209 | #define BP_RTC_PERSISTENT0_ALARM_EN 2 | ||
210 | #define BM_RTC_PERSISTENT0_ALARM_EN 0x4 | ||
211 | #define BF_RTC_PERSISTENT0_ALARM_EN(v) (((v) << 2) & 0x4) | ||
212 | #define BP_RTC_PERSISTENT0_ALARM_WAKE 1 | ||
213 | #define BM_RTC_PERSISTENT0_ALARM_WAKE 0x2 | ||
214 | #define BF_RTC_PERSISTENT0_ALARM_WAKE(v) (((v) << 1) & 0x2) | ||
215 | #define BP_RTC_PERSISTENT0_CLOCKSOURCE 0 | ||
216 | #define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x1 | ||
217 | #define BF_RTC_PERSISTENT0_CLOCKSOURCE(v) (((v) << 0) & 0x1) | ||
218 | |||
219 | /** | ||
220 | * Register: HW_RTC_PERSISTENT1 | ||
221 | * Address: 0x70 | ||
222 | * SCT: yes | ||
223 | */ | ||
224 | #define HW_RTC_PERSISTENT1 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0)) | ||
225 | #define HW_RTC_PERSISTENT1_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4)) | ||
226 | #define HW_RTC_PERSISTENT1_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8)) | ||
227 | #define HW_RTC_PERSISTENT1_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc)) | ||
228 | #define BP_RTC_PERSISTENT1_GENERAL 0 | ||
229 | #define BM_RTC_PERSISTENT1_GENERAL 0xffffffff | ||
230 | #define BF_RTC_PERSISTENT1_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
231 | |||
232 | /** | ||
233 | * Register: HW_RTC_PERSISTENT2 | ||
234 | * Address: 0x80 | ||
235 | * SCT: yes | ||
236 | */ | ||
237 | #define HW_RTC_PERSISTENT2 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0)) | ||
238 | #define HW_RTC_PERSISTENT2_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4)) | ||
239 | #define HW_RTC_PERSISTENT2_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8)) | ||
240 | #define HW_RTC_PERSISTENT2_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc)) | ||
241 | #define BP_RTC_PERSISTENT2_SRAM_LO 0 | ||
242 | #define BM_RTC_PERSISTENT2_SRAM_LO 0xffffffff | ||
243 | #define BV_RTC_PERSISTENT2_SRAM_LO__WARM_BOOT 0x80000000 | ||
244 | #define BF_RTC_PERSISTENT2_SRAM_LO(v) (((v) << 0) & 0xffffffff) | ||
245 | #define BF_RTC_PERSISTENT2_SRAM_LO_V(v) ((BV_RTC_PERSISTENT2_SRAM_LO__##v << 0) & 0xffffffff) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_RTC_PERSISTENT3 | ||
249 | * Address: 0x90 | ||
250 | * SCT: yes | ||
251 | */ | ||
252 | #define HW_RTC_PERSISTENT3 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0)) | ||
253 | #define HW_RTC_PERSISTENT3_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4)) | ||
254 | #define HW_RTC_PERSISTENT3_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8)) | ||
255 | #define HW_RTC_PERSISTENT3_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc)) | ||
256 | #define BP_RTC_PERSISTENT3_SRAM_HI 0 | ||
257 | #define BM_RTC_PERSISTENT3_SRAM_HI 0xffffffff | ||
258 | #define BF_RTC_PERSISTENT3_SRAM_HI(v) (((v) << 0) & 0xffffffff) | ||
259 | |||
260 | /** | ||
261 | * Register: HW_RTC_DEBUG | ||
262 | * Address: 0xa0 | ||
263 | * SCT: yes | ||
264 | */ | ||
265 | #define HW_RTC_DEBUG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0)) | ||
266 | #define HW_RTC_DEBUG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4)) | ||
267 | #define HW_RTC_DEBUG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8)) | ||
268 | #define HW_RTC_DEBUG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc)) | ||
269 | #define BP_RTC_DEBUG_WATCHDOG_RESET_MASK 1 | ||
270 | #define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x2 | ||
271 | #define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2) | ||
272 | #define BP_RTC_DEBUG_WATCHDOG_RESET 0 | ||
273 | #define BM_RTC_DEBUG_WATCHDOG_RESET 0x1 | ||
274 | #define BF_RTC_DEBUG_WATCHDOG_RESET(v) (((v) << 0) & 0x1) | ||
275 | |||
276 | /** | ||
277 | * Register: HW_RTC_UNLOCK | ||
278 | * Address: 0x200 | ||
279 | * SCT: yes | ||
280 | */ | ||
281 | #define HW_RTC_UNLOCK (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x0)) | ||
282 | #define HW_RTC_UNLOCK_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x4)) | ||
283 | #define HW_RTC_UNLOCK_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x8)) | ||
284 | #define HW_RTC_UNLOCK_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0xc)) | ||
285 | #define BP_RTC_UNLOCK_KEY 0 | ||
286 | #define BM_RTC_UNLOCK_KEY 0xffffffff | ||
287 | #define BV_RTC_UNLOCK_KEY__VAL 0xc6a83957 | ||
288 | #define BF_RTC_UNLOCK_KEY(v) (((v) << 0) & 0xffffffff) | ||
289 | #define BF_RTC_UNLOCK_KEY_V(v) ((BV_RTC_UNLOCK_KEY__##v << 0) & 0xffffffff) | ||
290 | |||
291 | /** | ||
292 | * Register: HW_RTC_LASERFUSEn | ||
293 | * Address: 0x300+n*0x10 | ||
294 | * SCT: yes | ||
295 | */ | ||
296 | #define HW_RTC_LASERFUSEn(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x0)) | ||
297 | #define HW_RTC_LASERFUSEn_SET(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x4)) | ||
298 | #define HW_RTC_LASERFUSEn_CLR(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x8)) | ||
299 | #define HW_RTC_LASERFUSEn_TOG(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0xc)) | ||
300 | #define BP_RTC_LASERFUSEn_BITS 0 | ||
301 | #define BM_RTC_LASERFUSEn_BITS 0xffffffff | ||
302 | #define BF_RTC_LASERFUSEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
303 | |||
304 | #endif /* __HEADERGEN__STMP3600__RTC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h new file mode 100644 index 0000000000..32e88b37cd --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h | |||
@@ -0,0 +1,165 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__SPDIF__H__ | ||
24 | #define __HEADERGEN__STMP3600__SPDIF__H__ | ||
25 | |||
26 | #define REGS_SPDIF_BASE (0x80054000) | ||
27 | |||
28 | #define REGS_SPDIF_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SPDIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SPDIF_CTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0)) | ||
36 | #define HW_SPDIF_CTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4)) | ||
37 | #define HW_SPDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8)) | ||
38 | #define HW_SPDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc)) | ||
39 | #define BP_SPDIF_CTRL_SFTRST 31 | ||
40 | #define BM_SPDIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_SPDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SPDIF_CTRL_CLKGATE 30 | ||
43 | #define BM_SPDIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_SPDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 | ||
46 | #define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
47 | #define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
48 | #define BP_SPDIF_CTRL_WAIT_END_XFER 5 | ||
49 | #define BM_SPDIF_CTRL_WAIT_END_XFER 0x20 | ||
50 | #define BF_SPDIF_CTRL_WAIT_END_XFER(v) (((v) << 5) & 0x20) | ||
51 | #define BP_SPDIF_CTRL_WORD_LENGTH 4 | ||
52 | #define BM_SPDIF_CTRL_WORD_LENGTH 0x10 | ||
53 | #define BF_SPDIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0x10) | ||
54 | #define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
55 | #define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
56 | #define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
57 | #define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
58 | #define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
59 | #define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
60 | #define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
61 | #define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
62 | #define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
63 | #define BP_SPDIF_CTRL_RUN 0 | ||
64 | #define BM_SPDIF_CTRL_RUN 0x1 | ||
65 | #define BF_SPDIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
66 | |||
67 | /** | ||
68 | * Register: HW_SPDIF_STAT | ||
69 | * Address: 0x10 | ||
70 | * SCT: no | ||
71 | */ | ||
72 | #define HW_SPDIF_STAT (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10)) | ||
73 | #define BP_SPDIF_STAT_PRESENT 31 | ||
74 | #define BM_SPDIF_STAT_PRESENT 0x80000000 | ||
75 | #define BF_SPDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
76 | #define BP_SPDIF_STAT_END_XFER 0 | ||
77 | #define BM_SPDIF_STAT_END_XFER 0x1 | ||
78 | #define BF_SPDIF_STAT_END_XFER(v) (((v) << 0) & 0x1) | ||
79 | |||
80 | /** | ||
81 | * Register: HW_SPDIF_FRAMECTRL | ||
82 | * Address: 0x20 | ||
83 | * SCT: yes | ||
84 | */ | ||
85 | #define HW_SPDIF_FRAMECTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0)) | ||
86 | #define HW_SPDIF_FRAMECTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4)) | ||
87 | #define HW_SPDIF_FRAMECTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8)) | ||
88 | #define HW_SPDIF_FRAMECTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc)) | ||
89 | #define BP_SPDIF_FRAMECTRL_V_CONFIG 17 | ||
90 | #define BM_SPDIF_FRAMECTRL_V_CONFIG 0x20000 | ||
91 | #define BF_SPDIF_FRAMECTRL_V_CONFIG(v) (((v) << 17) & 0x20000) | ||
92 | #define BP_SPDIF_FRAMECTRL_AUTO_MUTE 16 | ||
93 | #define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x10000 | ||
94 | #define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000) | ||
95 | #define BP_SPDIF_FRAMECTRL_USER_DATA 14 | ||
96 | #define BM_SPDIF_FRAMECTRL_USER_DATA 0x4000 | ||
97 | #define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000) | ||
98 | #define BP_SPDIF_FRAMECTRL_V 13 | ||
99 | #define BM_SPDIF_FRAMECTRL_V 0x2000 | ||
100 | #define BF_SPDIF_FRAMECTRL_V(v) (((v) << 13) & 0x2000) | ||
101 | #define BP_SPDIF_FRAMECTRL_L 12 | ||
102 | #define BM_SPDIF_FRAMECTRL_L 0x1000 | ||
103 | #define BF_SPDIF_FRAMECTRL_L(v) (((v) << 12) & 0x1000) | ||
104 | #define BP_SPDIF_FRAMECTRL_CC 4 | ||
105 | #define BM_SPDIF_FRAMECTRL_CC 0x7f0 | ||
106 | #define BF_SPDIF_FRAMECTRL_CC(v) (((v) << 4) & 0x7f0) | ||
107 | #define BP_SPDIF_FRAMECTRL_PRE 3 | ||
108 | #define BM_SPDIF_FRAMECTRL_PRE 0x8 | ||
109 | #define BF_SPDIF_FRAMECTRL_PRE(v) (((v) << 3) & 0x8) | ||
110 | #define BP_SPDIF_FRAMECTRL_COPY 2 | ||
111 | #define BM_SPDIF_FRAMECTRL_COPY 0x4 | ||
112 | #define BF_SPDIF_FRAMECTRL_COPY(v) (((v) << 2) & 0x4) | ||
113 | #define BP_SPDIF_FRAMECTRL_AUDIO 1 | ||
114 | #define BM_SPDIF_FRAMECTRL_AUDIO 0x2 | ||
115 | #define BF_SPDIF_FRAMECTRL_AUDIO(v) (((v) << 1) & 0x2) | ||
116 | #define BP_SPDIF_FRAMECTRL_PRO 0 | ||
117 | #define BM_SPDIF_FRAMECTRL_PRO 0x1 | ||
118 | #define BF_SPDIF_FRAMECTRL_PRO(v) (((v) << 0) & 0x1) | ||
119 | |||
120 | /** | ||
121 | * Register: HW_SPDIF_SRR | ||
122 | * Address: 0x30 | ||
123 | * SCT: yes | ||
124 | */ | ||
125 | #define HW_SPDIF_SRR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0)) | ||
126 | #define HW_SPDIF_SRR_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4)) | ||
127 | #define HW_SPDIF_SRR_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8)) | ||
128 | #define HW_SPDIF_SRR_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc)) | ||
129 | #define BP_SPDIF_SRR_BASEMULT 28 | ||
130 | #define BM_SPDIF_SRR_BASEMULT 0x70000000 | ||
131 | #define BF_SPDIF_SRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
132 | #define BP_SPDIF_SRR_RATE 0 | ||
133 | #define BM_SPDIF_SRR_RATE 0xfffff | ||
134 | #define BF_SPDIF_SRR_RATE(v) (((v) << 0) & 0xfffff) | ||
135 | |||
136 | /** | ||
137 | * Register: HW_SPDIF_DEBUG | ||
138 | * Address: 0x40 | ||
139 | * SCT: no | ||
140 | */ | ||
141 | #define HW_SPDIF_DEBUG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40)) | ||
142 | #define BP_SPDIF_DEBUG_DMA_PREQ 1 | ||
143 | #define BM_SPDIF_DEBUG_DMA_PREQ 0x2 | ||
144 | #define BF_SPDIF_DEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
145 | #define BP_SPDIF_DEBUG_FIFO_STATUS 0 | ||
146 | #define BM_SPDIF_DEBUG_FIFO_STATUS 0x1 | ||
147 | #define BF_SPDIF_DEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_SPDIF_DATA | ||
151 | * Address: 0x50 | ||
152 | * SCT: yes | ||
153 | */ | ||
154 | #define HW_SPDIF_DATA (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0)) | ||
155 | #define HW_SPDIF_DATA_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4)) | ||
156 | #define HW_SPDIF_DATA_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8)) | ||
157 | #define HW_SPDIF_DATA_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc)) | ||
158 | #define BP_SPDIF_DATA_HIGH 16 | ||
159 | #define BM_SPDIF_DATA_HIGH 0xffff0000 | ||
160 | #define BF_SPDIF_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
161 | #define BP_SPDIF_DATA_LOW 0 | ||
162 | #define BM_SPDIF_DATA_LOW 0xffff | ||
163 | #define BF_SPDIF_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
164 | |||
165 | #endif /* __HEADERGEN__STMP3600__SPDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h new file mode 100644 index 0000000000..2c589f5256 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h | |||
@@ -0,0 +1,541 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__SSP__H__ | ||
24 | #define __HEADERGEN__STMP3600__SSP__H__ | ||
25 | |||
26 | #define REGS_SSP_BASE (0x80010000) | ||
27 | |||
28 | #define REGS_SSP_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SSP_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SSP_CTRL0 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_SSP_CTRL0_SET (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_SSP_CTRL0_CLR (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_SSP_CTRL0_TOG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_SSP_CTRL0_SFTRST 31 | ||
40 | #define BM_SSP_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_SSP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SSP_CTRL0_CLKGATE 30 | ||
43 | #define BM_SSP_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_SSP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SSP_CTRL0_RUN 29 | ||
46 | #define BM_SSP_CTRL0_RUN 0x20000000 | ||
47 | #define BF_SSP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_SSP_CTRL0_HALF_DUPLEX 28 | ||
49 | #define BM_SSP_CTRL0_HALF_DUPLEX 0x10000000 | ||
50 | #define BF_SSP_CTRL0_HALF_DUPLEX(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_SSP_CTRL0_LOCK_CS 27 | ||
52 | #define BM_SSP_CTRL0_LOCK_CS 0x8000000 | ||
53 | #define BF_SSP_CTRL0_LOCK_CS(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_SSP_CTRL0_IGNORE_CRC 26 | ||
55 | #define BM_SSP_CTRL0_IGNORE_CRC 0x4000000 | ||
56 | #define BF_SSP_CTRL0_IGNORE_CRC(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_SSP_CTRL0_READ 25 | ||
58 | #define BM_SSP_CTRL0_READ 0x2000000 | ||
59 | #define BF_SSP_CTRL0_READ(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_SSP_CTRL0_DATA_XFER 24 | ||
61 | #define BM_SSP_CTRL0_DATA_XFER 0x1000000 | ||
62 | #define BF_SSP_CTRL0_DATA_XFER(v) (((v) << 24) & 0x1000000) | ||
63 | #define BP_SSP_CTRL0_SDIO_IRQ 23 | ||
64 | #define BM_SSP_CTRL0_SDIO_IRQ 0x800000 | ||
65 | #define BF_SSP_CTRL0_SDIO_IRQ(v) (((v) << 23) & 0x800000) | ||
66 | #define BP_SSP_CTRL0_BUS_WIDTH 22 | ||
67 | #define BM_SSP_CTRL0_BUS_WIDTH 0x400000 | ||
68 | #define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 | ||
69 | #define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 | ||
70 | #define BF_SSP_CTRL0_BUS_WIDTH(v) (((v) << 22) & 0x400000) | ||
71 | #define BF_SSP_CTRL0_BUS_WIDTH_V(v) ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0x400000) | ||
72 | #define BP_SSP_CTRL0_WAIT_FOR_IRQ 21 | ||
73 | #define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x200000 | ||
74 | #define BF_SSP_CTRL0_WAIT_FOR_IRQ(v) (((v) << 21) & 0x200000) | ||
75 | #define BP_SSP_CTRL0_WAIT_FOR_CMD 20 | ||
76 | #define BM_SSP_CTRL0_WAIT_FOR_CMD 0x100000 | ||
77 | #define BF_SSP_CTRL0_WAIT_FOR_CMD(v) (((v) << 20) & 0x100000) | ||
78 | #define BP_SSP_CTRL0_LONG_RESP 19 | ||
79 | #define BM_SSP_CTRL0_LONG_RESP 0x80000 | ||
80 | #define BF_SSP_CTRL0_LONG_RESP(v) (((v) << 19) & 0x80000) | ||
81 | #define BP_SSP_CTRL0_CHECK_RESP 18 | ||
82 | #define BM_SSP_CTRL0_CHECK_RESP 0x40000 | ||
83 | #define BF_SSP_CTRL0_CHECK_RESP(v) (((v) << 18) & 0x40000) | ||
84 | #define BP_SSP_CTRL0_GET_RESP 17 | ||
85 | #define BM_SSP_CTRL0_GET_RESP 0x20000 | ||
86 | #define BF_SSP_CTRL0_GET_RESP(v) (((v) << 17) & 0x20000) | ||
87 | #define BP_SSP_CTRL0_ENABLE 16 | ||
88 | #define BM_SSP_CTRL0_ENABLE 0x10000 | ||
89 | #define BF_SSP_CTRL0_ENABLE(v) (((v) << 16) & 0x10000) | ||
90 | #define BP_SSP_CTRL0_XFER_COUNT 0 | ||
91 | #define BM_SSP_CTRL0_XFER_COUNT 0xffff | ||
92 | #define BF_SSP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
93 | |||
94 | /** | ||
95 | * Register: HW_SSP_CMD0 | ||
96 | * Address: 0x10 | ||
97 | * SCT: yes | ||
98 | */ | ||
99 | #define HW_SSP_CMD0 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x0)) | ||
100 | #define HW_SSP_CMD0_SET (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x4)) | ||
101 | #define HW_SSP_CMD0_CLR (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x8)) | ||
102 | #define HW_SSP_CMD0_TOG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0xc)) | ||
103 | #define BP_SSP_CMD0_CMD 0 | ||
104 | #define BM_SSP_CMD0_CMD 0xff | ||
105 | #define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x0 | ||
106 | #define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x1 | ||
107 | #define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x2 | ||
108 | #define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x3 | ||
109 | #define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x4 | ||
110 | #define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x5 | ||
111 | #define BV_SSP_CMD0_CMD__MMC_SWITCH 0x6 | ||
112 | #define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x7 | ||
113 | #define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x8 | ||
114 | #define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x9 | ||
115 | #define BV_SSP_CMD0_CMD__MMC_SEND_CID 0xa | ||
116 | #define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0xb | ||
117 | #define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0xc | ||
118 | #define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0xd | ||
119 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0xe | ||
120 | #define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0xf | ||
121 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 | ||
122 | #define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 | ||
123 | #define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 | ||
124 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 | ||
125 | #define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 | ||
126 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 | ||
127 | #define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 | ||
128 | #define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 | ||
129 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1a | ||
130 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1b | ||
131 | #define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1c | ||
132 | #define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1d | ||
133 | #define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1e | ||
134 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 | ||
135 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 | ||
136 | #define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 | ||
137 | #define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 | ||
138 | #define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 | ||
139 | #define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2a | ||
140 | #define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 | ||
141 | #define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 | ||
142 | #define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x0 | ||
143 | #define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x2 | ||
144 | #define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x3 | ||
145 | #define BV_SSP_CMD0_CMD__SD_SET_DSR 0x4 | ||
146 | #define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x5 | ||
147 | #define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x7 | ||
148 | #define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x9 | ||
149 | #define BV_SSP_CMD0_CMD__SD_SEND_CID 0xa | ||
150 | #define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0xc | ||
151 | #define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0xd | ||
152 | #define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0xf | ||
153 | #define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 | ||
154 | #define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 | ||
155 | #define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 | ||
156 | #define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 | ||
157 | #define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 | ||
158 | #define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1b | ||
159 | #define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1c | ||
160 | #define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1d | ||
161 | #define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1e | ||
162 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 | ||
163 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 | ||
164 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 | ||
165 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 | ||
166 | #define BV_SSP_CMD0_CMD__SD_ERASE 0x26 | ||
167 | #define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2a | ||
168 | #define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 | ||
169 | #define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 | ||
170 | #define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 | ||
171 | #define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 | ||
172 | #define BF_SSP_CMD0_CMD(v) (((v) << 0) & 0xff) | ||
173 | #define BF_SSP_CMD0_CMD_V(v) ((BV_SSP_CMD0_CMD__##v << 0) & 0xff) | ||
174 | |||
175 | /** | ||
176 | * Register: HW_SSP_CMD1 | ||
177 | * Address: 0x20 | ||
178 | * SCT: no | ||
179 | */ | ||
180 | #define HW_SSP_CMD1 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x20)) | ||
181 | #define BP_SSP_CMD1_CMD_ARG 0 | ||
182 | #define BM_SSP_CMD1_CMD_ARG 0xffffffff | ||
183 | #define BF_SSP_CMD1_CMD_ARG(v) (((v) << 0) & 0xffffffff) | ||
184 | |||
185 | /** | ||
186 | * Register: HW_SSP_COMPREF | ||
187 | * Address: 0x30 | ||
188 | * SCT: no | ||
189 | */ | ||
190 | #define HW_SSP_COMPREF (*(volatile unsigned long *)(REGS_SSP_BASE + 0x30)) | ||
191 | #define BP_SSP_COMPREF_REFERENCE 0 | ||
192 | #define BM_SSP_COMPREF_REFERENCE 0xffffffff | ||
193 | #define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff) | ||
194 | |||
195 | /** | ||
196 | * Register: HW_SSP_COMPMASK | ||
197 | * Address: 0x40 | ||
198 | * SCT: no | ||
199 | */ | ||
200 | #define HW_SSP_COMPMASK (*(volatile unsigned long *)(REGS_SSP_BASE + 0x40)) | ||
201 | #define BP_SSP_COMPMASK_MASK 0 | ||
202 | #define BM_SSP_COMPMASK_MASK 0xffffffff | ||
203 | #define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff) | ||
204 | |||
205 | /** | ||
206 | * Register: HW_SSP_TIMING | ||
207 | * Address: 0x50 | ||
208 | * SCT: no | ||
209 | */ | ||
210 | #define HW_SSP_TIMING (*(volatile unsigned long *)(REGS_SSP_BASE + 0x50)) | ||
211 | #define BP_SSP_TIMING_TIMEOUT 16 | ||
212 | #define BM_SSP_TIMING_TIMEOUT 0xffff0000 | ||
213 | #define BF_SSP_TIMING_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
214 | #define BP_SSP_TIMING_CLOCK_DIVIDE 8 | ||
215 | #define BM_SSP_TIMING_CLOCK_DIVIDE 0xff00 | ||
216 | #define BF_SSP_TIMING_CLOCK_DIVIDE(v) (((v) << 8) & 0xff00) | ||
217 | #define BP_SSP_TIMING_CLOCK_RATE 0 | ||
218 | #define BM_SSP_TIMING_CLOCK_RATE 0xff | ||
219 | #define BF_SSP_TIMING_CLOCK_RATE(v) (((v) << 0) & 0xff) | ||
220 | |||
221 | /** | ||
222 | * Register: HW_SSP_CTRL1 | ||
223 | * Address: 0x60 | ||
224 | * SCT: yes | ||
225 | */ | ||
226 | #define HW_SSP_CTRL1 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x0)) | ||
227 | #define HW_SSP_CTRL1_SET (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x4)) | ||
228 | #define HW_SSP_CTRL1_CLR (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x8)) | ||
229 | #define HW_SSP_CTRL1_TOG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0xc)) | ||
230 | #define BP_SSP_CTRL1_SDIO_IRQ 31 | ||
231 | #define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 | ||
232 | #define BF_SSP_CTRL1_SDIO_IRQ(v) (((v) << 31) & 0x80000000) | ||
233 | #define BP_SSP_CTRL1_SDIO_IRQ_EN 30 | ||
234 | #define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 | ||
235 | #define BF_SSP_CTRL1_SDIO_IRQ_EN(v) (((v) << 30) & 0x40000000) | ||
236 | #define BP_SSP_CTRL1_RESP_ERR_IRQ 29 | ||
237 | #define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 | ||
238 | #define BF_SSP_CTRL1_RESP_ERR_IRQ(v) (((v) << 29) & 0x20000000) | ||
239 | #define BP_SSP_CTRL1_RESP_ERR_IRQ_EN 28 | ||
240 | #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 | ||
241 | #define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
242 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ 27 | ||
243 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x8000000 | ||
244 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v) (((v) << 27) & 0x8000000) | ||
245 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 26 | ||
246 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x4000000 | ||
247 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v) (((v) << 26) & 0x4000000) | ||
248 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ 25 | ||
249 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x2000000 | ||
250 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v) (((v) << 25) & 0x2000000) | ||
251 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 24 | ||
252 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x1000000 | ||
253 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
254 | #define BP_SSP_CTRL1_DATA_CRC_IRQ 23 | ||
255 | #define BM_SSP_CTRL1_DATA_CRC_IRQ 0x800000 | ||
256 | #define BF_SSP_CTRL1_DATA_CRC_IRQ(v) (((v) << 23) & 0x800000) | ||
257 | #define BP_SSP_CTRL1_DATA_CRC_IRQ_EN 22 | ||
258 | #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x400000 | ||
259 | #define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
260 | #define BP_SSP_CTRL1_XMIT_IRQ 21 | ||
261 | #define BM_SSP_CTRL1_XMIT_IRQ 0x200000 | ||
262 | #define BF_SSP_CTRL1_XMIT_IRQ(v) (((v) << 21) & 0x200000) | ||
263 | #define BP_SSP_CTRL1_XMIT_IRQ_EN 20 | ||
264 | #define BM_SSP_CTRL1_XMIT_IRQ_EN 0x100000 | ||
265 | #define BF_SSP_CTRL1_XMIT_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
266 | #define BP_SSP_CTRL1_RECV_IRQ 19 | ||
267 | #define BM_SSP_CTRL1_RECV_IRQ 0x80000 | ||
268 | #define BF_SSP_CTRL1_RECV_IRQ(v) (((v) << 19) & 0x80000) | ||
269 | #define BP_SSP_CTRL1_RECV_IRQ_EN 18 | ||
270 | #define BM_SSP_CTRL1_RECV_IRQ_EN 0x40000 | ||
271 | #define BF_SSP_CTRL1_RECV_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
272 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ 17 | ||
273 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x20000 | ||
274 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v) (((v) << 17) & 0x20000) | ||
275 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 16 | ||
276 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x10000 | ||
277 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
278 | #define BP_SSP_CTRL1_RECV_OVRFLW_IRQ 15 | ||
279 | #define BM_SSP_CTRL1_RECV_OVRFLW_IRQ 0x8000 | ||
280 | #define BF_SSP_CTRL1_RECV_OVRFLW_IRQ(v) (((v) << 15) & 0x8000) | ||
281 | #define BP_SSP_CTRL1_RECV_OVRFLW_IRQ_EN 14 | ||
282 | #define BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN 0x4000 | ||
283 | #define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
284 | #define BP_SSP_CTRL1_DMA_ENABLE 13 | ||
285 | #define BM_SSP_CTRL1_DMA_ENABLE 0x2000 | ||
286 | #define BF_SSP_CTRL1_DMA_ENABLE(v) (((v) << 13) & 0x2000) | ||
287 | #define BP_SSP_CTRL1_LOOPBACK 12 | ||
288 | #define BM_SSP_CTRL1_LOOPBACK 0x1000 | ||
289 | #define BF_SSP_CTRL1_LOOPBACK(v) (((v) << 12) & 0x1000) | ||
290 | #define BP_SSP_CTRL1_SLAVE_OUT_DISABLE 11 | ||
291 | #define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x800 | ||
292 | #define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v) (((v) << 11) & 0x800) | ||
293 | #define BP_SSP_CTRL1_PHASE 10 | ||
294 | #define BM_SSP_CTRL1_PHASE 0x400 | ||
295 | #define BF_SSP_CTRL1_PHASE(v) (((v) << 10) & 0x400) | ||
296 | #define BP_SSP_CTRL1_POLARITY 9 | ||
297 | #define BM_SSP_CTRL1_POLARITY 0x200 | ||
298 | #define BF_SSP_CTRL1_POLARITY(v) (((v) << 9) & 0x200) | ||
299 | #define BP_SSP_CTRL1_SLAVE_MODE 8 | ||
300 | #define BM_SSP_CTRL1_SLAVE_MODE 0x100 | ||
301 | #define BF_SSP_CTRL1_SLAVE_MODE(v) (((v) << 8) & 0x100) | ||
302 | #define BP_SSP_CTRL1_WORD_LENGTH 4 | ||
303 | #define BM_SSP_CTRL1_WORD_LENGTH 0xf0 | ||
304 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 | ||
305 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 | ||
306 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 | ||
307 | #define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 | ||
308 | #define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 | ||
309 | #define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xf | ||
310 | #define BF_SSP_CTRL1_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
311 | #define BF_SSP_CTRL1_WORD_LENGTH_V(v) ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0) | ||
312 | #define BP_SSP_CTRL1_SSP_MODE 0 | ||
313 | #define BM_SSP_CTRL1_SSP_MODE 0xf | ||
314 | #define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 | ||
315 | #define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 | ||
316 | #define BV_SSP_CTRL1_SSP_MODE__MICROWIRE 0x2 | ||
317 | #define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 | ||
318 | #define BV_SSP_CTRL1_SSP_MODE__MS 0x4 | ||
319 | #define BF_SSP_CTRL1_SSP_MODE(v) (((v) << 0) & 0xf) | ||
320 | #define BF_SSP_CTRL1_SSP_MODE_V(v) ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf) | ||
321 | |||
322 | /** | ||
323 | * Register: HW_SSP_DATA | ||
324 | * Address: 0x70 | ||
325 | * SCT: no | ||
326 | */ | ||
327 | #define HW_SSP_DATA (*(volatile unsigned long *)(REGS_SSP_BASE + 0x70)) | ||
328 | #define BP_SSP_DATA_DATA 0 | ||
329 | #define BM_SSP_DATA_DATA 0xffffffff | ||
330 | #define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
331 | |||
332 | /** | ||
333 | * Register: HW_SSP_SDRESP0 | ||
334 | * Address: 0x80 | ||
335 | * SCT: no | ||
336 | */ | ||
337 | #define HW_SSP_SDRESP0 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x80)) | ||
338 | #define BP_SSP_SDRESP0_RESP0 0 | ||
339 | #define BM_SSP_SDRESP0_RESP0 0xffffffff | ||
340 | #define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff) | ||
341 | |||
342 | /** | ||
343 | * Register: HW_SSP_SDRESP1 | ||
344 | * Address: 0x90 | ||
345 | * SCT: no | ||
346 | */ | ||
347 | #define HW_SSP_SDRESP1 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x90)) | ||
348 | #define BP_SSP_SDRESP1_RESP1 0 | ||
349 | #define BM_SSP_SDRESP1_RESP1 0xffffffff | ||
350 | #define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff) | ||
351 | |||
352 | /** | ||
353 | * Register: HW_SSP_SDRESP2 | ||
354 | * Address: 0xa0 | ||
355 | * SCT: no | ||
356 | */ | ||
357 | #define HW_SSP_SDRESP2 (*(volatile unsigned long *)(REGS_SSP_BASE + 0xa0)) | ||
358 | #define BP_SSP_SDRESP2_RESP2 0 | ||
359 | #define BM_SSP_SDRESP2_RESP2 0xffffffff | ||
360 | #define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff) | ||
361 | |||
362 | /** | ||
363 | * Register: HW_SSP_SDRESP3 | ||
364 | * Address: 0xb0 | ||
365 | * SCT: no | ||
366 | */ | ||
367 | #define HW_SSP_SDRESP3 (*(volatile unsigned long *)(REGS_SSP_BASE + 0xb0)) | ||
368 | #define BP_SSP_SDRESP3_RESP3 0 | ||
369 | #define BM_SSP_SDRESP3_RESP3 0xffffffff | ||
370 | #define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff) | ||
371 | |||
372 | /** | ||
373 | * Register: HW_SSP_STATUS | ||
374 | * Address: 0xc0 | ||
375 | * SCT: no | ||
376 | */ | ||
377 | #define HW_SSP_STATUS (*(volatile unsigned long *)(REGS_SSP_BASE + 0xc0)) | ||
378 | #define BP_SSP_STATUS_PRESENT 31 | ||
379 | #define BM_SSP_STATUS_PRESENT 0x80000000 | ||
380 | #define BF_SSP_STATUS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
381 | #define BP_SSP_STATUS_MS_PRESENT 30 | ||
382 | #define BM_SSP_STATUS_MS_PRESENT 0x40000000 | ||
383 | #define BF_SSP_STATUS_MS_PRESENT(v) (((v) << 30) & 0x40000000) | ||
384 | #define BP_SSP_STATUS_SD_PRESENT 29 | ||
385 | #define BM_SSP_STATUS_SD_PRESENT 0x20000000 | ||
386 | #define BF_SSP_STATUS_SD_PRESENT(v) (((v) << 29) & 0x20000000) | ||
387 | #define BP_SSP_STATUS_CARD_DETECT 28 | ||
388 | #define BM_SSP_STATUS_CARD_DETECT 0x10000000 | ||
389 | #define BF_SSP_STATUS_CARD_DETECT(v) (((v) << 28) & 0x10000000) | ||
390 | #define BP_SSP_STATUS_RECV_COUNT 24 | ||
391 | #define BM_SSP_STATUS_RECV_COUNT 0xf000000 | ||
392 | #define BF_SSP_STATUS_RECV_COUNT(v) (((v) << 24) & 0xf000000) | ||
393 | #define BP_SSP_STATUS_XMIT_COUNT 20 | ||
394 | #define BM_SSP_STATUS_XMIT_COUNT 0xf00000 | ||
395 | #define BF_SSP_STATUS_XMIT_COUNT(v) (((v) << 20) & 0xf00000) | ||
396 | #define BP_SSP_STATUS_DMAREQ 19 | ||
397 | #define BM_SSP_STATUS_DMAREQ 0x80000 | ||
398 | #define BF_SSP_STATUS_DMAREQ(v) (((v) << 19) & 0x80000) | ||
399 | #define BP_SSP_STATUS_DMAEND 18 | ||
400 | #define BM_SSP_STATUS_DMAEND 0x40000 | ||
401 | #define BF_SSP_STATUS_DMAEND(v) (((v) << 18) & 0x40000) | ||
402 | #define BP_SSP_STATUS_SDIO_IRQ 17 | ||
403 | #define BM_SSP_STATUS_SDIO_IRQ 0x20000 | ||
404 | #define BF_SSP_STATUS_SDIO_IRQ(v) (((v) << 17) & 0x20000) | ||
405 | #define BP_SSP_STATUS_RESP_CRC_ERR 16 | ||
406 | #define BM_SSP_STATUS_RESP_CRC_ERR 0x10000 | ||
407 | #define BF_SSP_STATUS_RESP_CRC_ERR(v) (((v) << 16) & 0x10000) | ||
408 | #define BP_SSP_STATUS_RESP_ERR 15 | ||
409 | #define BM_SSP_STATUS_RESP_ERR 0x8000 | ||
410 | #define BF_SSP_STATUS_RESP_ERR(v) (((v) << 15) & 0x8000) | ||
411 | #define BP_SSP_STATUS_RESP_TIMEOUT 14 | ||
412 | #define BM_SSP_STATUS_RESP_TIMEOUT 0x4000 | ||
413 | #define BF_SSP_STATUS_RESP_TIMEOUT(v) (((v) << 14) & 0x4000) | ||
414 | #define BP_SSP_STATUS_DATA_CRC_ERR 13 | ||
415 | #define BM_SSP_STATUS_DATA_CRC_ERR 0x2000 | ||
416 | #define BF_SSP_STATUS_DATA_CRC_ERR(v) (((v) << 13) & 0x2000) | ||
417 | #define BP_SSP_STATUS_TIMEOUT 12 | ||
418 | #define BM_SSP_STATUS_TIMEOUT 0x1000 | ||
419 | #define BF_SSP_STATUS_TIMEOUT(v) (((v) << 12) & 0x1000) | ||
420 | #define BP_SSP_STATUS_RECV_TIMEOUT_STAT 11 | ||
421 | #define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x800 | ||
422 | #define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v) (((v) << 11) & 0x800) | ||
423 | #define BP_SSP_STATUS_RECV_DATA_STAT 10 | ||
424 | #define BM_SSP_STATUS_RECV_DATA_STAT 0x400 | ||
425 | #define BF_SSP_STATUS_RECV_DATA_STAT(v) (((v) << 10) & 0x400) | ||
426 | #define BP_SSP_STATUS_RECV_OVRFLW 9 | ||
427 | #define BM_SSP_STATUS_RECV_OVRFLW 0x200 | ||
428 | #define BF_SSP_STATUS_RECV_OVRFLW(v) (((v) << 9) & 0x200) | ||
429 | #define BP_SSP_STATUS_RECV_FULL 8 | ||
430 | #define BM_SSP_STATUS_RECV_FULL 0x100 | ||
431 | #define BF_SSP_STATUS_RECV_FULL(v) (((v) << 8) & 0x100) | ||
432 | #define BP_SSP_STATUS_RECV_NOT_EMPTY 7 | ||
433 | #define BM_SSP_STATUS_RECV_NOT_EMPTY 0x80 | ||
434 | #define BF_SSP_STATUS_RECV_NOT_EMPTY(v) (((v) << 7) & 0x80) | ||
435 | #define BP_SSP_STATUS_XMIT_NOT_FULL 6 | ||
436 | #define BM_SSP_STATUS_XMIT_NOT_FULL 0x40 | ||
437 | #define BF_SSP_STATUS_XMIT_NOT_FULL(v) (((v) << 6) & 0x40) | ||
438 | #define BP_SSP_STATUS_XMIT_EMPTY 5 | ||
439 | #define BM_SSP_STATUS_XMIT_EMPTY 0x20 | ||
440 | #define BF_SSP_STATUS_XMIT_EMPTY(v) (((v) << 5) & 0x20) | ||
441 | #define BP_SSP_STATUS_XMIT_UNDRFLW 4 | ||
442 | #define BM_SSP_STATUS_XMIT_UNDRFLW 0x10 | ||
443 | #define BF_SSP_STATUS_XMIT_UNDRFLW(v) (((v) << 4) & 0x10) | ||
444 | #define BP_SSP_STATUS_CMD_BUSY 3 | ||
445 | #define BM_SSP_STATUS_CMD_BUSY 0x8 | ||
446 | #define BF_SSP_STATUS_CMD_BUSY(v) (((v) << 3) & 0x8) | ||
447 | #define BP_SSP_STATUS_DATA_BUSY 2 | ||
448 | #define BM_SSP_STATUS_DATA_BUSY 0x4 | ||
449 | #define BF_SSP_STATUS_DATA_BUSY(v) (((v) << 2) & 0x4) | ||
450 | #define BP_SSP_STATUS_DATA_XFER 1 | ||
451 | #define BM_SSP_STATUS_DATA_XFER 0x2 | ||
452 | #define BF_SSP_STATUS_DATA_XFER(v) (((v) << 1) & 0x2) | ||
453 | #define BP_SSP_STATUS_BUSY 0 | ||
454 | #define BM_SSP_STATUS_BUSY 0x1 | ||
455 | #define BF_SSP_STATUS_BUSY(v) (((v) << 0) & 0x1) | ||
456 | |||
457 | /** | ||
458 | * Register: HW_SSP_DEBUG | ||
459 | * Address: 0x100 | ||
460 | * SCT: no | ||
461 | */ | ||
462 | #define HW_SSP_DEBUG (*(volatile unsigned long *)(REGS_SSP_BASE + 0x100)) | ||
463 | #define BP_SSP_DEBUG_DATACRC_ERR 28 | ||
464 | #define BM_SSP_DEBUG_DATACRC_ERR 0xf0000000 | ||
465 | #define BF_SSP_DEBUG_DATACRC_ERR(v) (((v) << 28) & 0xf0000000) | ||
466 | #define BP_SSP_DEBUG_DATA_STALL 27 | ||
467 | #define BM_SSP_DEBUG_DATA_STALL 0x8000000 | ||
468 | #define BF_SSP_DEBUG_DATA_STALL(v) (((v) << 27) & 0x8000000) | ||
469 | #define BP_SSP_DEBUG_DAT_SM 24 | ||
470 | #define BM_SSP_DEBUG_DAT_SM 0x7000000 | ||
471 | #define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 | ||
472 | #define BV_SSP_DEBUG_DAT_SM__DSM_START 0x1 | ||
473 | #define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 | ||
474 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 | ||
475 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 | ||
476 | #define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 | ||
477 | #define BV_SSP_DEBUG_DAT_SM__DSM_RXDLY 0x6 | ||
478 | #define BF_SSP_DEBUG_DAT_SM(v) (((v) << 24) & 0x7000000) | ||
479 | #define BF_SSP_DEBUG_DAT_SM_V(v) ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000) | ||
480 | #define BP_SSP_DEBUG_MSTK_SM 20 | ||
481 | #define BM_SSP_DEBUG_MSTK_SM 0xf00000 | ||
482 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 | ||
483 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 | ||
484 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 | ||
485 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 | ||
486 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 | ||
487 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 | ||
488 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 | ||
489 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 | ||
490 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 | ||
491 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 | ||
492 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xa | ||
493 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xb | ||
494 | #define BF_SSP_DEBUG_MSTK_SM(v) (((v) << 20) & 0xf00000) | ||
495 | #define BF_SSP_DEBUG_MSTK_SM_V(v) ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000) | ||
496 | #define BP_SSP_DEBUG_CMD_OE 19 | ||
497 | #define BM_SSP_DEBUG_CMD_OE 0x80000 | ||
498 | #define BF_SSP_DEBUG_CMD_OE(v) (((v) << 19) & 0x80000) | ||
499 | #define BP_SSP_DEBUG_CMD_SM 16 | ||
500 | #define BM_SSP_DEBUG_CMD_SM 0x70000 | ||
501 | #define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 | ||
502 | #define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 | ||
503 | #define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 | ||
504 | #define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 | ||
505 | #define BF_SSP_DEBUG_CMD_SM(v) (((v) << 16) & 0x70000) | ||
506 | #define BF_SSP_DEBUG_CMD_SM_V(v) ((BV_SSP_DEBUG_CMD_SM__##v << 16) & 0x70000) | ||
507 | #define BP_SSP_DEBUG_CLK_OE 15 | ||
508 | #define BM_SSP_DEBUG_CLK_OE 0x8000 | ||
509 | #define BF_SSP_DEBUG_CLK_OE(v) (((v) << 15) & 0x8000) | ||
510 | #define BP_SSP_DEBUG_MMC_SM 12 | ||
511 | #define BM_SSP_DEBUG_MMC_SM 0x7000 | ||
512 | #define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 | ||
513 | #define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 | ||
514 | #define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 | ||
515 | #define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 | ||
516 | #define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 | ||
517 | #define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 | ||
518 | #define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 | ||
519 | #define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 | ||
520 | #define BF_SSP_DEBUG_MMC_SM(v) (((v) << 12) & 0x7000) | ||
521 | #define BF_SSP_DEBUG_MMC_SM_V(v) ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0x7000) | ||
522 | #define BP_SSP_DEBUG_DAT0_OE 11 | ||
523 | #define BM_SSP_DEBUG_DAT0_OE 0x800 | ||
524 | #define BF_SSP_DEBUG_DAT0_OE(v) (((v) << 11) & 0x800) | ||
525 | #define BP_SSP_DEBUG_DAT321_OE 10 | ||
526 | #define BM_SSP_DEBUG_DAT321_OE 0x400 | ||
527 | #define BF_SSP_DEBUG_DAT321_OE(v) (((v) << 10) & 0x400) | ||
528 | #define BP_SSP_DEBUG_SSP_CMD 9 | ||
529 | #define BM_SSP_DEBUG_SSP_CMD 0x200 | ||
530 | #define BF_SSP_DEBUG_SSP_CMD(v) (((v) << 9) & 0x200) | ||
531 | #define BP_SSP_DEBUG_SSP_RESP 8 | ||
532 | #define BM_SSP_DEBUG_SSP_RESP 0x100 | ||
533 | #define BF_SSP_DEBUG_SSP_RESP(v) (((v) << 8) & 0x100) | ||
534 | #define BP_SSP_DEBUG_SSP_TXD 4 | ||
535 | #define BM_SSP_DEBUG_SSP_TXD 0xf0 | ||
536 | #define BF_SSP_DEBUG_SSP_TXD(v) (((v) << 4) & 0xf0) | ||
537 | #define BP_SSP_DEBUG_SSP_RXD 0 | ||
538 | #define BM_SSP_DEBUG_SSP_RXD 0xf | ||
539 | #define BF_SSP_DEBUG_SSP_RXD(v) (((v) << 0) & 0xf) | ||
540 | |||
541 | #endif /* __HEADERGEN__STMP3600__SSP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h new file mode 100644 index 0000000000..a726662ac8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h | |||
@@ -0,0 +1,267 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__TIMROT__H__ | ||
24 | #define __HEADERGEN__STMP3600__TIMROT__H__ | ||
25 | |||
26 | #define REGS_TIMROT_BASE (0x80068000) | ||
27 | |||
28 | #define REGS_TIMROT_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_TIMROT_ROTCTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_TIMROT_ROTCTRL (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0)) | ||
36 | #define HW_TIMROT_ROTCTRL_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4)) | ||
37 | #define HW_TIMROT_ROTCTRL_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8)) | ||
38 | #define HW_TIMROT_ROTCTRL_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc)) | ||
39 | #define BP_TIMROT_ROTCTRL_SFTRST 31 | ||
40 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | ||
41 | #define BF_TIMROT_ROTCTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_TIMROT_ROTCTRL_CLKGATE 30 | ||
43 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | ||
44 | #define BF_TIMROT_ROTCTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_TIMROT_ROTCTRL_ROTARY_PRESENT 29 | ||
46 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | ||
47 | #define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_TIMROT_ROTCTRL_TIM3_PRESENT 28 | ||
49 | #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 | ||
50 | #define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_TIMROT_ROTCTRL_TIM2_PRESENT 27 | ||
52 | #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x8000000 | ||
53 | #define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_TIMROT_ROTCTRL_TIM1_PRESENT 26 | ||
55 | #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x4000000 | ||
56 | #define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_TIMROT_ROTCTRL_TIM0_PRESENT 25 | ||
58 | #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x2000000 | ||
59 | #define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_TIMROT_ROTCTRL_STATE 22 | ||
61 | #define BM_TIMROT_ROTCTRL_STATE 0x1c00000 | ||
62 | #define BF_TIMROT_ROTCTRL_STATE(v) (((v) << 22) & 0x1c00000) | ||
63 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | ||
64 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x3f0000 | ||
65 | #define BF_TIMROT_ROTCTRL_DIVIDER(v) (((v) << 16) & 0x3f0000) | ||
66 | #define BP_TIMROT_ROTCTRL_RELATIVE 12 | ||
67 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x1000 | ||
68 | #define BF_TIMROT_ROTCTRL_RELATIVE(v) (((v) << 12) & 0x1000) | ||
69 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | ||
70 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0xc00 | ||
71 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 | ||
72 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 | ||
73 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 | ||
74 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 | ||
75 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) (((v) << 10) & 0xc00) | ||
76 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v) ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00) | ||
77 | #define BP_TIMROT_ROTCTRL_POLARITY_B 9 | ||
78 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x200 | ||
79 | #define BF_TIMROT_ROTCTRL_POLARITY_B(v) (((v) << 9) & 0x200) | ||
80 | #define BP_TIMROT_ROTCTRL_POLARITY_A 8 | ||
81 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x100 | ||
82 | #define BF_TIMROT_ROTCTRL_POLARITY_A(v) (((v) << 8) & 0x100) | ||
83 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
84 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x70 | ||
85 | #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 | ||
86 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 | ||
87 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 | ||
88 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 | ||
89 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 | ||
90 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 | ||
91 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 | ||
92 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 | ||
93 | #define BF_TIMROT_ROTCTRL_SELECT_B(v) (((v) << 4) & 0x70) | ||
94 | #define BF_TIMROT_ROTCTRL_SELECT_B_V(v) ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70) | ||
95 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
96 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x7 | ||
97 | #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 | ||
98 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 | ||
99 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 | ||
100 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 | ||
101 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 | ||
102 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 | ||
103 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 | ||
104 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 | ||
105 | #define BF_TIMROT_ROTCTRL_SELECT_A(v) (((v) << 0) & 0x7) | ||
106 | #define BF_TIMROT_ROTCTRL_SELECT_A_V(v) ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7) | ||
107 | |||
108 | /** | ||
109 | * Register: HW_TIMROT_ROTCOUNT | ||
110 | * Address: 0x10 | ||
111 | * SCT: no | ||
112 | */ | ||
113 | #define HW_TIMROT_ROTCOUNT (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10)) | ||
114 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 | ||
115 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0xffff | ||
116 | #define BF_TIMROT_ROTCOUNT_UPDOWN(v) (((v) << 0) & 0xffff) | ||
117 | |||
118 | /** | ||
119 | * Register: HW_TIMROT_TIMCTRL3 | ||
120 | * Address: 0x80 | ||
121 | * SCT: yes | ||
122 | */ | ||
123 | #define HW_TIMROT_TIMCTRL3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0)) | ||
124 | #define HW_TIMROT_TIMCTRL3_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4)) | ||
125 | #define HW_TIMROT_TIMCTRL3_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8)) | ||
126 | #define HW_TIMROT_TIMCTRL3_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc)) | ||
127 | #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 | ||
128 | #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0xf0000 | ||
129 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 | ||
130 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 | ||
131 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 | ||
132 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 | ||
133 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 | ||
134 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 | ||
135 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 | ||
136 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 | ||
137 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 | ||
138 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 | ||
139 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xa | ||
140 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xb | ||
141 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc | ||
142 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) (((v) << 16) & 0xf0000) | ||
143 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v) ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000) | ||
144 | #define BP_TIMROT_TIMCTRL3_IRQ 15 | ||
145 | #define BM_TIMROT_TIMCTRL3_IRQ 0x8000 | ||
146 | #define BF_TIMROT_TIMCTRL3_IRQ(v) (((v) << 15) & 0x8000) | ||
147 | #define BP_TIMROT_TIMCTRL3_IRQ_EN 14 | ||
148 | #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x4000 | ||
149 | #define BF_TIMROT_TIMCTRL3_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
150 | #define BP_TIMROT_TIMCTRL3_DUTY_VALID 10 | ||
151 | #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x400 | ||
152 | #define BF_TIMROT_TIMCTRL3_DUTY_VALID(v) (((v) << 10) & 0x400) | ||
153 | #define BP_TIMROT_TIMCTRL3_DUTY_CYCLE 9 | ||
154 | #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x200 | ||
155 | #define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v) (((v) << 9) & 0x200) | ||
156 | #define BP_TIMROT_TIMCTRL3_POLARITY 8 | ||
157 | #define BM_TIMROT_TIMCTRL3_POLARITY 0x100 | ||
158 | #define BF_TIMROT_TIMCTRL3_POLARITY(v) (((v) << 8) & 0x100) | ||
159 | #define BP_TIMROT_TIMCTRL3_UPDATE 7 | ||
160 | #define BM_TIMROT_TIMCTRL3_UPDATE 0x80 | ||
161 | #define BF_TIMROT_TIMCTRL3_UPDATE(v) (((v) << 7) & 0x80) | ||
162 | #define BP_TIMROT_TIMCTRL3_RELOAD 6 | ||
163 | #define BM_TIMROT_TIMCTRL3_RELOAD 0x40 | ||
164 | #define BF_TIMROT_TIMCTRL3_RELOAD(v) (((v) << 6) & 0x40) | ||
165 | #define BP_TIMROT_TIMCTRL3_PRESCALE 4 | ||
166 | #define BM_TIMROT_TIMCTRL3_PRESCALE 0x30 | ||
167 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 | ||
168 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 | ||
169 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 | ||
170 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 | ||
171 | #define BF_TIMROT_TIMCTRL3_PRESCALE(v) (((v) << 4) & 0x30) | ||
172 | #define BF_TIMROT_TIMCTRL3_PRESCALE_V(v) ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30) | ||
173 | #define BP_TIMROT_TIMCTRL3_SELECT 0 | ||
174 | #define BM_TIMROT_TIMCTRL3_SELECT 0xf | ||
175 | #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 | ||
176 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 | ||
177 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 | ||
178 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 | ||
179 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 | ||
180 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 | ||
181 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 | ||
182 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 | ||
183 | #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 | ||
184 | #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 | ||
185 | #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xa | ||
186 | #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xb | ||
187 | #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xc | ||
188 | #define BF_TIMROT_TIMCTRL3_SELECT(v) (((v) << 0) & 0xf) | ||
189 | #define BF_TIMROT_TIMCTRL3_SELECT_V(v) ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf) | ||
190 | |||
191 | /** | ||
192 | * Register: HW_TIMROT_TIMCOUNT3 | ||
193 | * Address: 0x90 | ||
194 | * SCT: no | ||
195 | */ | ||
196 | #define HW_TIMROT_TIMCOUNT3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90)) | ||
197 | #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 | ||
198 | #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xffff0000 | ||
199 | #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
200 | #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 | ||
201 | #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0xffff | ||
202 | #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
203 | |||
204 | /** | ||
205 | * Register: HW_TIMROT_TIMCOUNTn | ||
206 | * Address: 0x30+n*0x20 | ||
207 | * SCT: no | ||
208 | */ | ||
209 | #define HW_TIMROT_TIMCOUNTn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20)) | ||
210 | #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 | ||
211 | #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xffff0000 | ||
212 | #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
213 | #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 | ||
214 | #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0xffff | ||
215 | #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_TIMROT_TIMCTRLn | ||
219 | * Address: 0x20+n*0x20 | ||
220 | * SCT: yes | ||
221 | */ | ||
222 | #define HW_TIMROT_TIMCTRLn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0)) | ||
223 | #define HW_TIMROT_TIMCTRLn_SET(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4)) | ||
224 | #define HW_TIMROT_TIMCTRLn_CLR(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8)) | ||
225 | #define HW_TIMROT_TIMCTRLn_TOG(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc)) | ||
226 | #define BP_TIMROT_TIMCTRLn_IRQ 15 | ||
227 | #define BM_TIMROT_TIMCTRLn_IRQ 0x8000 | ||
228 | #define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & 0x8000) | ||
229 | #define BP_TIMROT_TIMCTRLn_IRQ_EN 14 | ||
230 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x4000 | ||
231 | #define BF_TIMROT_TIMCTRLn_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
232 | #define BP_TIMROT_TIMCTRLn_POLARITY 8 | ||
233 | #define BM_TIMROT_TIMCTRLn_POLARITY 0x100 | ||
234 | #define BF_TIMROT_TIMCTRLn_POLARITY(v) (((v) << 8) & 0x100) | ||
235 | #define BP_TIMROT_TIMCTRLn_UPDATE 7 | ||
236 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x80 | ||
237 | #define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & 0x80) | ||
238 | #define BP_TIMROT_TIMCTRLn_RELOAD 6 | ||
239 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x40 | ||
240 | #define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & 0x40) | ||
241 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 | ||
242 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x30 | ||
243 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 | ||
244 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 | ||
245 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 | ||
246 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 | ||
247 | #define BF_TIMROT_TIMCTRLn_PRESCALE(v) (((v) << 4) & 0x30) | ||
248 | #define BF_TIMROT_TIMCTRLn_PRESCALE_V(v) ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30) | ||
249 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
250 | #define BM_TIMROT_TIMCTRLn_SELECT 0xf | ||
251 | #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 | ||
252 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 | ||
253 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 | ||
254 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 | ||
255 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 | ||
256 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 | ||
257 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 | ||
258 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 | ||
259 | #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
260 | #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 | ||
261 | #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xa | ||
262 | #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xb | ||
263 | #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xc | ||
264 | #define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & 0xf) | ||
265 | #define BF_TIMROT_TIMCTRLn_SELECT_V(v) ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf) | ||
266 | |||
267 | #endif /* __HEADERGEN__STMP3600__TIMROT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h new file mode 100644 index 0000000000..62442f3ef3 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h | |||
@@ -0,0 +1,371 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__UARTAPP__H__ | ||
24 | #define __HEADERGEN__STMP3600__UARTAPP__H__ | ||
25 | |||
26 | #define REGS_UARTAPP_BASE (0x8006c000) | ||
27 | |||
28 | #define REGS_UARTAPP_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_UARTAPP_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_UARTAPP_CTRL0 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_UARTAPP_CTRL0_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_UARTAPP_CTRL0_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_UARTAPP_CTRL0_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_UARTAPP_CTRL0_SFTRST 31 | ||
40 | #define BM_UARTAPP_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_UARTAPP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_UARTAPP_CTRL0_CLKGATE 30 | ||
43 | #define BM_UARTAPP_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_UARTAPP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_UARTAPP_CTRL0_RUN 28 | ||
46 | #define BM_UARTAPP_CTRL0_RUN 0x10000000 | ||
47 | #define BF_UARTAPP_CTRL0_RUN(v) (((v) << 28) & 0x10000000) | ||
48 | #define BP_UARTAPP_CTRL0_RX_SOURCE 25 | ||
49 | #define BM_UARTAPP_CTRL0_RX_SOURCE 0x2000000 | ||
50 | #define BF_UARTAPP_CTRL0_RX_SOURCE(v) (((v) << 25) & 0x2000000) | ||
51 | #define BP_UARTAPP_CTRL0_RXTO_ENABLE 24 | ||
52 | #define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x1000000 | ||
53 | #define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 24) & 0x1000000) | ||
54 | #define BP_UARTAPP_CTRL0_RXTIMEOUT 16 | ||
55 | #define BM_UARTAPP_CTRL0_RXTIMEOUT 0xff0000 | ||
56 | #define BF_UARTAPP_CTRL0_RXTIMEOUT(v) (((v) << 16) & 0xff0000) | ||
57 | #define BP_UARTAPP_CTRL0_XFER_COUNT 0 | ||
58 | #define BM_UARTAPP_CTRL0_XFER_COUNT 0xffff | ||
59 | #define BF_UARTAPP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
60 | |||
61 | /** | ||
62 | * Register: HW_UARTAPP_CTRL1 | ||
63 | * Address: 0x10 | ||
64 | * SCT: yes | ||
65 | */ | ||
66 | #define HW_UARTAPP_CTRL1 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x0)) | ||
67 | #define HW_UARTAPP_CTRL1_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x4)) | ||
68 | #define HW_UARTAPP_CTRL1_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x8)) | ||
69 | #define HW_UARTAPP_CTRL1_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0xc)) | ||
70 | #define BP_UARTAPP_CTRL1_RUN 28 | ||
71 | #define BM_UARTAPP_CTRL1_RUN 0x10000000 | ||
72 | #define BF_UARTAPP_CTRL1_RUN(v) (((v) << 28) & 0x10000000) | ||
73 | #define BP_UARTAPP_CTRL1_XFER_COUNT 0 | ||
74 | #define BM_UARTAPP_CTRL1_XFER_COUNT 0xffff | ||
75 | #define BF_UARTAPP_CTRL1_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
76 | |||
77 | /** | ||
78 | * Register: HW_UARTAPP_CTRL2 | ||
79 | * Address: 0x20 | ||
80 | * SCT: yes | ||
81 | */ | ||
82 | #define HW_UARTAPP_CTRL2 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x0)) | ||
83 | #define HW_UARTAPP_CTRL2_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x4)) | ||
84 | #define HW_UARTAPP_CTRL2_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x8)) | ||
85 | #define HW_UARTAPP_CTRL2_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0xc)) | ||
86 | #define BP_UARTAPP_CTRL2_INVERT_RTS 31 | ||
87 | #define BM_UARTAPP_CTRL2_INVERT_RTS 0x80000000 | ||
88 | #define BF_UARTAPP_CTRL2_INVERT_RTS(v) (((v) << 31) & 0x80000000) | ||
89 | #define BP_UARTAPP_CTRL2_INVERT_CTS 30 | ||
90 | #define BM_UARTAPP_CTRL2_INVERT_CTS 0x40000000 | ||
91 | #define BF_UARTAPP_CTRL2_INVERT_CTS(v) (((v) << 30) & 0x40000000) | ||
92 | #define BP_UARTAPP_CTRL2_INVERT_TX 29 | ||
93 | #define BM_UARTAPP_CTRL2_INVERT_TX 0x20000000 | ||
94 | #define BF_UARTAPP_CTRL2_INVERT_TX(v) (((v) << 29) & 0x20000000) | ||
95 | #define BP_UARTAPP_CTRL2_INVERT_RX 28 | ||
96 | #define BM_UARTAPP_CTRL2_INVERT_RX 0x10000000 | ||
97 | #define BF_UARTAPP_CTRL2_INVERT_RX(v) (((v) << 28) & 0x10000000) | ||
98 | #define BP_UARTAPP_CTRL2_DMAONERR 26 | ||
99 | #define BM_UARTAPP_CTRL2_DMAONERR 0x4000000 | ||
100 | #define BF_UARTAPP_CTRL2_DMAONERR(v) (((v) << 26) & 0x4000000) | ||
101 | #define BP_UARTAPP_CTRL2_TXDMAE 25 | ||
102 | #define BM_UARTAPP_CTRL2_TXDMAE 0x2000000 | ||
103 | #define BF_UARTAPP_CTRL2_TXDMAE(v) (((v) << 25) & 0x2000000) | ||
104 | #define BP_UARTAPP_CTRL2_RXDMAE 24 | ||
105 | #define BM_UARTAPP_CTRL2_RXDMAE 0x1000000 | ||
106 | #define BF_UARTAPP_CTRL2_RXDMAE(v) (((v) << 24) & 0x1000000) | ||
107 | #define BP_UARTAPP_CTRL2_RXIFLSEL 20 | ||
108 | #define BM_UARTAPP_CTRL2_RXIFLSEL 0x700000 | ||
109 | #define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 | ||
110 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 | ||
111 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 | ||
112 | #define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 | ||
113 | #define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
114 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 | ||
115 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 | ||
116 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 | ||
117 | #define BF_UARTAPP_CTRL2_RXIFLSEL(v) (((v) << 20) & 0x700000) | ||
118 | #define BF_UARTAPP_CTRL2_RXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000) | ||
119 | #define BP_UARTAPP_CTRL2_TXIFLSEL 16 | ||
120 | #define BM_UARTAPP_CTRL2_TXIFLSEL 0x70000 | ||
121 | #define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 | ||
122 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 | ||
123 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 | ||
124 | #define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 | ||
125 | #define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
126 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 | ||
127 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 | ||
128 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 | ||
129 | #define BF_UARTAPP_CTRL2_TXIFLSEL(v) (((v) << 16) & 0x70000) | ||
130 | #define BF_UARTAPP_CTRL2_TXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000) | ||
131 | #define BP_UARTAPP_CTRL2_CTSEN 15 | ||
132 | #define BM_UARTAPP_CTRL2_CTSEN 0x8000 | ||
133 | #define BF_UARTAPP_CTRL2_CTSEN(v) (((v) << 15) & 0x8000) | ||
134 | #define BP_UARTAPP_CTRL2_RTSEN 14 | ||
135 | #define BM_UARTAPP_CTRL2_RTSEN 0x4000 | ||
136 | #define BF_UARTAPP_CTRL2_RTSEN(v) (((v) << 14) & 0x4000) | ||
137 | #define BP_UARTAPP_CTRL2_OUT2 13 | ||
138 | #define BM_UARTAPP_CTRL2_OUT2 0x2000 | ||
139 | #define BF_UARTAPP_CTRL2_OUT2(v) (((v) << 13) & 0x2000) | ||
140 | #define BP_UARTAPP_CTRL2_OUT1 12 | ||
141 | #define BM_UARTAPP_CTRL2_OUT1 0x1000 | ||
142 | #define BF_UARTAPP_CTRL2_OUT1(v) (((v) << 12) & 0x1000) | ||
143 | #define BP_UARTAPP_CTRL2_RTS 11 | ||
144 | #define BM_UARTAPP_CTRL2_RTS 0x800 | ||
145 | #define BF_UARTAPP_CTRL2_RTS(v) (((v) << 11) & 0x800) | ||
146 | #define BP_UARTAPP_CTRL2_DTR 10 | ||
147 | #define BM_UARTAPP_CTRL2_DTR 0x400 | ||
148 | #define BF_UARTAPP_CTRL2_DTR(v) (((v) << 10) & 0x400) | ||
149 | #define BP_UARTAPP_CTRL2_RXE 9 | ||
150 | #define BM_UARTAPP_CTRL2_RXE 0x200 | ||
151 | #define BF_UARTAPP_CTRL2_RXE(v) (((v) << 9) & 0x200) | ||
152 | #define BP_UARTAPP_CTRL2_TXE 8 | ||
153 | #define BM_UARTAPP_CTRL2_TXE 0x100 | ||
154 | #define BF_UARTAPP_CTRL2_TXE(v) (((v) << 8) & 0x100) | ||
155 | #define BP_UARTAPP_CTRL2_LBE 7 | ||
156 | #define BM_UARTAPP_CTRL2_LBE 0x80 | ||
157 | #define BF_UARTAPP_CTRL2_LBE(v) (((v) << 7) & 0x80) | ||
158 | #define BP_UARTAPP_CTRL2_SIRLP 2 | ||
159 | #define BM_UARTAPP_CTRL2_SIRLP 0x4 | ||
160 | #define BF_UARTAPP_CTRL2_SIRLP(v) (((v) << 2) & 0x4) | ||
161 | #define BP_UARTAPP_CTRL2_SIREN 1 | ||
162 | #define BM_UARTAPP_CTRL2_SIREN 0x2 | ||
163 | #define BF_UARTAPP_CTRL2_SIREN(v) (((v) << 1) & 0x2) | ||
164 | #define BP_UARTAPP_CTRL2_UARTEN 0 | ||
165 | #define BM_UARTAPP_CTRL2_UARTEN 0x1 | ||
166 | #define BF_UARTAPP_CTRL2_UARTEN(v) (((v) << 0) & 0x1) | ||
167 | |||
168 | /** | ||
169 | * Register: HW_UARTAPP_LINECTRL | ||
170 | * Address: 0x30 | ||
171 | * SCT: yes | ||
172 | */ | ||
173 | #define HW_UARTAPP_LINECTRL (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x0)) | ||
174 | #define HW_UARTAPP_LINECTRL_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x4)) | ||
175 | #define HW_UARTAPP_LINECTRL_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x8)) | ||
176 | #define HW_UARTAPP_LINECTRL_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0xc)) | ||
177 | #define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 | ||
178 | #define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xffff0000 | ||
179 | #define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
180 | #define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 | ||
181 | #define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x3f00 | ||
182 | #define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
183 | #define BP_UARTAPP_LINECTRL_SPS 7 | ||
184 | #define BM_UARTAPP_LINECTRL_SPS 0x80 | ||
185 | #define BF_UARTAPP_LINECTRL_SPS(v) (((v) << 7) & 0x80) | ||
186 | #define BP_UARTAPP_LINECTRL_WLEN 5 | ||
187 | #define BM_UARTAPP_LINECTRL_WLEN 0x60 | ||
188 | #define BF_UARTAPP_LINECTRL_WLEN(v) (((v) << 5) & 0x60) | ||
189 | #define BP_UARTAPP_LINECTRL_FEN 4 | ||
190 | #define BM_UARTAPP_LINECTRL_FEN 0x10 | ||
191 | #define BF_UARTAPP_LINECTRL_FEN(v) (((v) << 4) & 0x10) | ||
192 | #define BP_UARTAPP_LINECTRL_STP2 3 | ||
193 | #define BM_UARTAPP_LINECTRL_STP2 0x8 | ||
194 | #define BF_UARTAPP_LINECTRL_STP2(v) (((v) << 3) & 0x8) | ||
195 | #define BP_UARTAPP_LINECTRL_EPS 2 | ||
196 | #define BM_UARTAPP_LINECTRL_EPS 0x4 | ||
197 | #define BF_UARTAPP_LINECTRL_EPS(v) (((v) << 2) & 0x4) | ||
198 | #define BP_UARTAPP_LINECTRL_PEN 1 | ||
199 | #define BM_UARTAPP_LINECTRL_PEN 0x2 | ||
200 | #define BF_UARTAPP_LINECTRL_PEN(v) (((v) << 1) & 0x2) | ||
201 | #define BP_UARTAPP_LINECTRL_BRK 0 | ||
202 | #define BM_UARTAPP_LINECTRL_BRK 0x1 | ||
203 | #define BF_UARTAPP_LINECTRL_BRK(v) (((v) << 0) & 0x1) | ||
204 | |||
205 | /** | ||
206 | * Register: HW_UARTAPP_INTR | ||
207 | * Address: 0x40 | ||
208 | * SCT: yes | ||
209 | */ | ||
210 | #define HW_UARTAPP_INTR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x0)) | ||
211 | #define HW_UARTAPP_INTR_SET (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x4)) | ||
212 | #define HW_UARTAPP_INTR_CLR (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x8)) | ||
213 | #define HW_UARTAPP_INTR_TOG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0xc)) | ||
214 | #define BP_UARTAPP_INTR_OEIEN 26 | ||
215 | #define BM_UARTAPP_INTR_OEIEN 0x4000000 | ||
216 | #define BF_UARTAPP_INTR_OEIEN(v) (((v) << 26) & 0x4000000) | ||
217 | #define BP_UARTAPP_INTR_BEIEN 25 | ||
218 | #define BM_UARTAPP_INTR_BEIEN 0x2000000 | ||
219 | #define BF_UARTAPP_INTR_BEIEN(v) (((v) << 25) & 0x2000000) | ||
220 | #define BP_UARTAPP_INTR_PEIEN 24 | ||
221 | #define BM_UARTAPP_INTR_PEIEN 0x1000000 | ||
222 | #define BF_UARTAPP_INTR_PEIEN(v) (((v) << 24) & 0x1000000) | ||
223 | #define BP_UARTAPP_INTR_FEIEN 23 | ||
224 | #define BM_UARTAPP_INTR_FEIEN 0x800000 | ||
225 | #define BF_UARTAPP_INTR_FEIEN(v) (((v) << 23) & 0x800000) | ||
226 | #define BP_UARTAPP_INTR_RTIEN 22 | ||
227 | #define BM_UARTAPP_INTR_RTIEN 0x400000 | ||
228 | #define BF_UARTAPP_INTR_RTIEN(v) (((v) << 22) & 0x400000) | ||
229 | #define BP_UARTAPP_INTR_TXIEN 21 | ||
230 | #define BM_UARTAPP_INTR_TXIEN 0x200000 | ||
231 | #define BF_UARTAPP_INTR_TXIEN(v) (((v) << 21) & 0x200000) | ||
232 | #define BP_UARTAPP_INTR_RXIEN 20 | ||
233 | #define BM_UARTAPP_INTR_RXIEN 0x100000 | ||
234 | #define BF_UARTAPP_INTR_RXIEN(v) (((v) << 20) & 0x100000) | ||
235 | #define BP_UARTAPP_INTR_DSRMIEN 19 | ||
236 | #define BM_UARTAPP_INTR_DSRMIEN 0x80000 | ||
237 | #define BF_UARTAPP_INTR_DSRMIEN(v) (((v) << 19) & 0x80000) | ||
238 | #define BP_UARTAPP_INTR_DCDMIEN 18 | ||
239 | #define BM_UARTAPP_INTR_DCDMIEN 0x40000 | ||
240 | #define BF_UARTAPP_INTR_DCDMIEN(v) (((v) << 18) & 0x40000) | ||
241 | #define BP_UARTAPP_INTR_CTSMIEN 17 | ||
242 | #define BM_UARTAPP_INTR_CTSMIEN 0x20000 | ||
243 | #define BF_UARTAPP_INTR_CTSMIEN(v) (((v) << 17) & 0x20000) | ||
244 | #define BP_UARTAPP_INTR_RIMIEN 16 | ||
245 | #define BM_UARTAPP_INTR_RIMIEN 0x10000 | ||
246 | #define BF_UARTAPP_INTR_RIMIEN(v) (((v) << 16) & 0x10000) | ||
247 | #define BP_UARTAPP_INTR_OEIS 10 | ||
248 | #define BM_UARTAPP_INTR_OEIS 0x400 | ||
249 | #define BF_UARTAPP_INTR_OEIS(v) (((v) << 10) & 0x400) | ||
250 | #define BP_UARTAPP_INTR_BEIS 9 | ||
251 | #define BM_UARTAPP_INTR_BEIS 0x200 | ||
252 | #define BF_UARTAPP_INTR_BEIS(v) (((v) << 9) & 0x200) | ||
253 | #define BP_UARTAPP_INTR_PEIS 8 | ||
254 | #define BM_UARTAPP_INTR_PEIS 0x100 | ||
255 | #define BF_UARTAPP_INTR_PEIS(v) (((v) << 8) & 0x100) | ||
256 | #define BP_UARTAPP_INTR_FEIS 7 | ||
257 | #define BM_UARTAPP_INTR_FEIS 0x80 | ||
258 | #define BF_UARTAPP_INTR_FEIS(v) (((v) << 7) & 0x80) | ||
259 | #define BP_UARTAPP_INTR_RTIS 6 | ||
260 | #define BM_UARTAPP_INTR_RTIS 0x40 | ||
261 | #define BF_UARTAPP_INTR_RTIS(v) (((v) << 6) & 0x40) | ||
262 | #define BP_UARTAPP_INTR_TXIS 5 | ||
263 | #define BM_UARTAPP_INTR_TXIS 0x20 | ||
264 | #define BF_UARTAPP_INTR_TXIS(v) (((v) << 5) & 0x20) | ||
265 | #define BP_UARTAPP_INTR_RXIS 4 | ||
266 | #define BM_UARTAPP_INTR_RXIS 0x10 | ||
267 | #define BF_UARTAPP_INTR_RXIS(v) (((v) << 4) & 0x10) | ||
268 | #define BP_UARTAPP_INTR_DSRMIS 3 | ||
269 | #define BM_UARTAPP_INTR_DSRMIS 0x8 | ||
270 | #define BF_UARTAPP_INTR_DSRMIS(v) (((v) << 3) & 0x8) | ||
271 | #define BP_UARTAPP_INTR_DCDMIS 2 | ||
272 | #define BM_UARTAPP_INTR_DCDMIS 0x4 | ||
273 | #define BF_UARTAPP_INTR_DCDMIS(v) (((v) << 2) & 0x4) | ||
274 | #define BP_UARTAPP_INTR_CTSMIS 1 | ||
275 | #define BM_UARTAPP_INTR_CTSMIS 0x2 | ||
276 | #define BF_UARTAPP_INTR_CTSMIS(v) (((v) << 1) & 0x2) | ||
277 | #define BP_UARTAPP_INTR_RIMIS 0 | ||
278 | #define BM_UARTAPP_INTR_RIMIS 0x1 | ||
279 | #define BF_UARTAPP_INTR_RIMIS(v) (((v) << 0) & 0x1) | ||
280 | |||
281 | /** | ||
282 | * Register: HW_UARTAPP_DATA | ||
283 | * Address: 0x50 | ||
284 | * SCT: no | ||
285 | */ | ||
286 | #define HW_UARTAPP_DATA (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x50)) | ||
287 | #define BP_UARTAPP_DATA_DATA 0 | ||
288 | #define BM_UARTAPP_DATA_DATA 0xffffffff | ||
289 | #define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
290 | |||
291 | /** | ||
292 | * Register: HW_UARTAPP_STAT | ||
293 | * Address: 0x60 | ||
294 | * SCT: no | ||
295 | */ | ||
296 | #define HW_UARTAPP_STAT (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x60)) | ||
297 | #define BP_UARTAPP_STAT_PRESENT 31 | ||
298 | #define BM_UARTAPP_STAT_PRESENT 0x80000000 | ||
299 | #define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 | ||
300 | #define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 | ||
301 | #define BF_UARTAPP_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
302 | #define BF_UARTAPP_STAT_PRESENT_V(v) ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000) | ||
303 | #define BP_UARTAPP_STAT_HISPEED 30 | ||
304 | #define BM_UARTAPP_STAT_HISPEED 0x40000000 | ||
305 | #define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 | ||
306 | #define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 | ||
307 | #define BF_UARTAPP_STAT_HISPEED(v) (((v) << 30) & 0x40000000) | ||
308 | #define BF_UARTAPP_STAT_HISPEED_V(v) ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000) | ||
309 | #define BP_UARTAPP_STAT_BUSY 29 | ||
310 | #define BM_UARTAPP_STAT_BUSY 0x20000000 | ||
311 | #define BF_UARTAPP_STAT_BUSY(v) (((v) << 29) & 0x20000000) | ||
312 | #define BP_UARTAPP_STAT_CTS 28 | ||
313 | #define BM_UARTAPP_STAT_CTS 0x10000000 | ||
314 | #define BF_UARTAPP_STAT_CTS(v) (((v) << 28) & 0x10000000) | ||
315 | #define BP_UARTAPP_STAT_TXFE 27 | ||
316 | #define BM_UARTAPP_STAT_TXFE 0x8000000 | ||
317 | #define BF_UARTAPP_STAT_TXFE(v) (((v) << 27) & 0x8000000) | ||
318 | #define BP_UARTAPP_STAT_RXFF 26 | ||
319 | #define BM_UARTAPP_STAT_RXFF 0x4000000 | ||
320 | #define BF_UARTAPP_STAT_RXFF(v) (((v) << 26) & 0x4000000) | ||
321 | #define BP_UARTAPP_STAT_TXFF 25 | ||
322 | #define BM_UARTAPP_STAT_TXFF 0x2000000 | ||
323 | #define BF_UARTAPP_STAT_TXFF(v) (((v) << 25) & 0x2000000) | ||
324 | #define BP_UARTAPP_STAT_RXFE 24 | ||
325 | #define BM_UARTAPP_STAT_RXFE 0x1000000 | ||
326 | #define BF_UARTAPP_STAT_RXFE(v) (((v) << 24) & 0x1000000) | ||
327 | #define BP_UARTAPP_STAT_RXBYTE_INVALID 20 | ||
328 | #define BM_UARTAPP_STAT_RXBYTE_INVALID 0xf00000 | ||
329 | #define BF_UARTAPP_STAT_RXBYTE_INVALID(v) (((v) << 20) & 0xf00000) | ||
330 | #define BP_UARTAPP_STAT_OERR 19 | ||
331 | #define BM_UARTAPP_STAT_OERR 0x80000 | ||
332 | #define BF_UARTAPP_STAT_OERR(v) (((v) << 19) & 0x80000) | ||
333 | #define BP_UARTAPP_STAT_BERR 18 | ||
334 | #define BM_UARTAPP_STAT_BERR 0x40000 | ||
335 | #define BF_UARTAPP_STAT_BERR(v) (((v) << 18) & 0x40000) | ||
336 | #define BP_UARTAPP_STAT_PERR 17 | ||
337 | #define BM_UARTAPP_STAT_PERR 0x20000 | ||
338 | #define BF_UARTAPP_STAT_PERR(v) (((v) << 17) & 0x20000) | ||
339 | #define BP_UARTAPP_STAT_FERR 16 | ||
340 | #define BM_UARTAPP_STAT_FERR 0x10000 | ||
341 | #define BF_UARTAPP_STAT_FERR(v) (((v) << 16) & 0x10000) | ||
342 | #define BP_UARTAPP_STAT_RXCOUNT 0 | ||
343 | #define BM_UARTAPP_STAT_RXCOUNT 0xffff | ||
344 | #define BF_UARTAPP_STAT_RXCOUNT(v) (((v) << 0) & 0xffff) | ||
345 | |||
346 | /** | ||
347 | * Register: HW_UARTAPP_DEBUG | ||
348 | * Address: 0x70 | ||
349 | * SCT: no | ||
350 | */ | ||
351 | #define HW_UARTAPP_DEBUG (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x70)) | ||
352 | #define BP_UARTAPP_DEBUG_TXDMARUN 5 | ||
353 | #define BM_UARTAPP_DEBUG_TXDMARUN 0x20 | ||
354 | #define BF_UARTAPP_DEBUG_TXDMARUN(v) (((v) << 5) & 0x20) | ||
355 | #define BP_UARTAPP_DEBUG_RXDMARUN 4 | ||
356 | #define BM_UARTAPP_DEBUG_RXDMARUN 0x10 | ||
357 | #define BF_UARTAPP_DEBUG_RXDMARUN(v) (((v) << 4) & 0x10) | ||
358 | #define BP_UARTAPP_DEBUG_TXCMDEND 3 | ||
359 | #define BM_UARTAPP_DEBUG_TXCMDEND 0x8 | ||
360 | #define BF_UARTAPP_DEBUG_TXCMDEND(v) (((v) << 3) & 0x8) | ||
361 | #define BP_UARTAPP_DEBUG_RXCMDEND 2 | ||
362 | #define BM_UARTAPP_DEBUG_RXCMDEND 0x4 | ||
363 | #define BF_UARTAPP_DEBUG_RXCMDEND(v) (((v) << 2) & 0x4) | ||
364 | #define BP_UARTAPP_DEBUG_TXDMARQ 1 | ||
365 | #define BM_UARTAPP_DEBUG_TXDMARQ 0x2 | ||
366 | #define BF_UARTAPP_DEBUG_TXDMARQ(v) (((v) << 1) & 0x2) | ||
367 | #define BP_UARTAPP_DEBUG_RXDMARQ 0 | ||
368 | #define BM_UARTAPP_DEBUG_RXDMARQ 0x1 | ||
369 | #define BF_UARTAPP_DEBUG_RXDMARQ(v) (((v) << 0) & 0x1) | ||
370 | |||
371 | #endif /* __HEADERGEN__STMP3600__UARTAPP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h new file mode 100644 index 0000000000..9750330d9d --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h | |||
@@ -0,0 +1,491 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__UARTDBG__H__ | ||
24 | #define __HEADERGEN__STMP3600__UARTDBG__H__ | ||
25 | |||
26 | #define REGS_UARTDBG_BASE (0x80070000) | ||
27 | |||
28 | #define REGS_UARTDBG_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_UARTDBG_DR | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_UARTDBG_DR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0)) | ||
36 | #define BP_UARTDBG_DR_UNAVAILABLE 16 | ||
37 | #define BM_UARTDBG_DR_UNAVAILABLE 0xffff0000 | ||
38 | #define BF_UARTDBG_DR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
39 | #define BP_UARTDBG_DR_RESERVED 12 | ||
40 | #define BM_UARTDBG_DR_RESERVED 0xf000 | ||
41 | #define BF_UARTDBG_DR_RESERVED(v) (((v) << 12) & 0xf000) | ||
42 | #define BP_UARTDBG_DR_OE 11 | ||
43 | #define BM_UARTDBG_DR_OE 0x800 | ||
44 | #define BF_UARTDBG_DR_OE(v) (((v) << 11) & 0x800) | ||
45 | #define BP_UARTDBG_DR_BE 10 | ||
46 | #define BM_UARTDBG_DR_BE 0x400 | ||
47 | #define BF_UARTDBG_DR_BE(v) (((v) << 10) & 0x400) | ||
48 | #define BP_UARTDBG_DR_PE 9 | ||
49 | #define BM_UARTDBG_DR_PE 0x200 | ||
50 | #define BF_UARTDBG_DR_PE(v) (((v) << 9) & 0x200) | ||
51 | #define BP_UARTDBG_DR_FE 8 | ||
52 | #define BM_UARTDBG_DR_FE 0x100 | ||
53 | #define BF_UARTDBG_DR_FE(v) (((v) << 8) & 0x100) | ||
54 | #define BP_UARTDBG_DR_DATA 0 | ||
55 | #define BM_UARTDBG_DR_DATA 0xff | ||
56 | #define BF_UARTDBG_DR_DATA(v) (((v) << 0) & 0xff) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_UARTDBG_RSR_ECR | ||
60 | * Address: 0x4 | ||
61 | * SCT: no | ||
62 | */ | ||
63 | #define HW_UARTDBG_RSR_ECR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4)) | ||
64 | #define BP_UARTDBG_RSR_ECR_UNAVAILABLE 8 | ||
65 | #define BM_UARTDBG_RSR_ECR_UNAVAILABLE 0xffffff00 | ||
66 | #define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
67 | #define BP_UARTDBG_RSR_ECR_EC 4 | ||
68 | #define BM_UARTDBG_RSR_ECR_EC 0xf0 | ||
69 | #define BF_UARTDBG_RSR_ECR_EC(v) (((v) << 4) & 0xf0) | ||
70 | #define BP_UARTDBG_RSR_ECR_OE 3 | ||
71 | #define BM_UARTDBG_RSR_ECR_OE 0x8 | ||
72 | #define BF_UARTDBG_RSR_ECR_OE(v) (((v) << 3) & 0x8) | ||
73 | #define BP_UARTDBG_RSR_ECR_BE 2 | ||
74 | #define BM_UARTDBG_RSR_ECR_BE 0x4 | ||
75 | #define BF_UARTDBG_RSR_ECR_BE(v) (((v) << 2) & 0x4) | ||
76 | #define BP_UARTDBG_RSR_ECR_PE 1 | ||
77 | #define BM_UARTDBG_RSR_ECR_PE 0x2 | ||
78 | #define BF_UARTDBG_RSR_ECR_PE(v) (((v) << 1) & 0x2) | ||
79 | #define BP_UARTDBG_RSR_ECR_FE 0 | ||
80 | #define BM_UARTDBG_RSR_ECR_FE 0x1 | ||
81 | #define BF_UARTDBG_RSR_ECR_FE(v) (((v) << 0) & 0x1) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_UARTDBG_FR | ||
85 | * Address: 0x18 | ||
86 | * SCT: no | ||
87 | */ | ||
88 | #define HW_UARTDBG_FR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18)) | ||
89 | #define BP_UARTDBG_FR_UNAVAILABLE 16 | ||
90 | #define BM_UARTDBG_FR_UNAVAILABLE 0xffff0000 | ||
91 | #define BF_UARTDBG_FR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
92 | #define BP_UARTDBG_FR_RESERVED 9 | ||
93 | #define BM_UARTDBG_FR_RESERVED 0xfe00 | ||
94 | #define BF_UARTDBG_FR_RESERVED(v) (((v) << 9) & 0xfe00) | ||
95 | #define BP_UARTDBG_FR_RI 8 | ||
96 | #define BM_UARTDBG_FR_RI 0x100 | ||
97 | #define BF_UARTDBG_FR_RI(v) (((v) << 8) & 0x100) | ||
98 | #define BP_UARTDBG_FR_TXFE 7 | ||
99 | #define BM_UARTDBG_FR_TXFE 0x80 | ||
100 | #define BF_UARTDBG_FR_TXFE(v) (((v) << 7) & 0x80) | ||
101 | #define BP_UARTDBG_FR_RXFF 6 | ||
102 | #define BM_UARTDBG_FR_RXFF 0x40 | ||
103 | #define BF_UARTDBG_FR_RXFF(v) (((v) << 6) & 0x40) | ||
104 | #define BP_UARTDBG_FR_TXFF 5 | ||
105 | #define BM_UARTDBG_FR_TXFF 0x20 | ||
106 | #define BF_UARTDBG_FR_TXFF(v) (((v) << 5) & 0x20) | ||
107 | #define BP_UARTDBG_FR_RXFE 4 | ||
108 | #define BM_UARTDBG_FR_RXFE 0x10 | ||
109 | #define BF_UARTDBG_FR_RXFE(v) (((v) << 4) & 0x10) | ||
110 | #define BP_UARTDBG_FR_BUSY 3 | ||
111 | #define BM_UARTDBG_FR_BUSY 0x8 | ||
112 | #define BF_UARTDBG_FR_BUSY(v) (((v) << 3) & 0x8) | ||
113 | #define BP_UARTDBG_FR_DCD 2 | ||
114 | #define BM_UARTDBG_FR_DCD 0x4 | ||
115 | #define BF_UARTDBG_FR_DCD(v) (((v) << 2) & 0x4) | ||
116 | #define BP_UARTDBG_FR_DSR 1 | ||
117 | #define BM_UARTDBG_FR_DSR 0x2 | ||
118 | #define BF_UARTDBG_FR_DSR(v) (((v) << 1) & 0x2) | ||
119 | #define BP_UARTDBG_FR_CTS 0 | ||
120 | #define BM_UARTDBG_FR_CTS 0x1 | ||
121 | #define BF_UARTDBG_FR_CTS(v) (((v) << 0) & 0x1) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_UARTDBG_ILPR | ||
125 | * Address: 0x20 | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_UARTDBG_ILPR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20)) | ||
129 | #define BP_UARTDBG_ILPR_UNAVAILABLE 8 | ||
130 | #define BM_UARTDBG_ILPR_UNAVAILABLE 0xffffff00 | ||
131 | #define BF_UARTDBG_ILPR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
132 | #define BP_UARTDBG_ILPR_ILPDVSR 0 | ||
133 | #define BM_UARTDBG_ILPR_ILPDVSR 0xff | ||
134 | #define BF_UARTDBG_ILPR_ILPDVSR(v) (((v) << 0) & 0xff) | ||
135 | |||
136 | /** | ||
137 | * Register: HW_UARTDBG_IBRD | ||
138 | * Address: 0x24 | ||
139 | * SCT: no | ||
140 | */ | ||
141 | #define HW_UARTDBG_IBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24)) | ||
142 | #define BP_UARTDBG_IBRD_UNAVAILABLE 16 | ||
143 | #define BM_UARTDBG_IBRD_UNAVAILABLE 0xffff0000 | ||
144 | #define BF_UARTDBG_IBRD_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
145 | #define BP_UARTDBG_IBRD_BAUD_DIVINT 0 | ||
146 | #define BM_UARTDBG_IBRD_BAUD_DIVINT 0xffff | ||
147 | #define BF_UARTDBG_IBRD_BAUD_DIVINT(v) (((v) << 0) & 0xffff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_UARTDBG_FBRD | ||
151 | * Address: 0x28 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_UARTDBG_FBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28)) | ||
155 | #define BP_UARTDBG_FBRD_UNAVAILABLE 8 | ||
156 | #define BM_UARTDBG_FBRD_UNAVAILABLE 0xffffff00 | ||
157 | #define BF_UARTDBG_FBRD_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
158 | #define BP_UARTDBG_FBRD_RESERVED 6 | ||
159 | #define BM_UARTDBG_FBRD_RESERVED 0xc0 | ||
160 | #define BF_UARTDBG_FBRD_RESERVED(v) (((v) << 6) & 0xc0) | ||
161 | #define BP_UARTDBG_FBRD_BAUD_DIVFRAC 0 | ||
162 | #define BM_UARTDBG_FBRD_BAUD_DIVFRAC 0x3f | ||
163 | #define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_UARTDBG_LCR_H | ||
167 | * Address: 0x2c | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_UARTDBG_LCR_H (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c)) | ||
171 | #define BP_UARTDBG_LCR_H_UNAVAILABLE 16 | ||
172 | #define BM_UARTDBG_LCR_H_UNAVAILABLE 0xffff0000 | ||
173 | #define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
174 | #define BP_UARTDBG_LCR_H_RESERVED 8 | ||
175 | #define BM_UARTDBG_LCR_H_RESERVED 0xff00 | ||
176 | #define BF_UARTDBG_LCR_H_RESERVED(v) (((v) << 8) & 0xff00) | ||
177 | #define BP_UARTDBG_LCR_H_SPS 7 | ||
178 | #define BM_UARTDBG_LCR_H_SPS 0x80 | ||
179 | #define BF_UARTDBG_LCR_H_SPS(v) (((v) << 7) & 0x80) | ||
180 | #define BP_UARTDBG_LCR_H_WLEN 5 | ||
181 | #define BM_UARTDBG_LCR_H_WLEN 0x60 | ||
182 | #define BF_UARTDBG_LCR_H_WLEN(v) (((v) << 5) & 0x60) | ||
183 | #define BP_UARTDBG_LCR_H_FEN 4 | ||
184 | #define BM_UARTDBG_LCR_H_FEN 0x10 | ||
185 | #define BF_UARTDBG_LCR_H_FEN(v) (((v) << 4) & 0x10) | ||
186 | #define BP_UARTDBG_LCR_H_STP2 3 | ||
187 | #define BM_UARTDBG_LCR_H_STP2 0x8 | ||
188 | #define BF_UARTDBG_LCR_H_STP2(v) (((v) << 3) & 0x8) | ||
189 | #define BP_UARTDBG_LCR_H_EPS 2 | ||
190 | #define BM_UARTDBG_LCR_H_EPS 0x4 | ||
191 | #define BF_UARTDBG_LCR_H_EPS(v) (((v) << 2) & 0x4) | ||
192 | #define BP_UARTDBG_LCR_H_PEN 1 | ||
193 | #define BM_UARTDBG_LCR_H_PEN 0x2 | ||
194 | #define BF_UARTDBG_LCR_H_PEN(v) (((v) << 1) & 0x2) | ||
195 | #define BP_UARTDBG_LCR_H_BRK 0 | ||
196 | #define BM_UARTDBG_LCR_H_BRK 0x1 | ||
197 | #define BF_UARTDBG_LCR_H_BRK(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_UARTDBG_CR | ||
201 | * Address: 0x30 | ||
202 | * SCT: no | ||
203 | */ | ||
204 | #define HW_UARTDBG_CR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30)) | ||
205 | #define BP_UARTDBG_CR_UNAVAILABLE 16 | ||
206 | #define BM_UARTDBG_CR_UNAVAILABLE 0xffff0000 | ||
207 | #define BF_UARTDBG_CR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
208 | #define BP_UARTDBG_CR_CTSEN 15 | ||
209 | #define BM_UARTDBG_CR_CTSEN 0x8000 | ||
210 | #define BF_UARTDBG_CR_CTSEN(v) (((v) << 15) & 0x8000) | ||
211 | #define BP_UARTDBG_CR_RTSEN 14 | ||
212 | #define BM_UARTDBG_CR_RTSEN 0x4000 | ||
213 | #define BF_UARTDBG_CR_RTSEN(v) (((v) << 14) & 0x4000) | ||
214 | #define BP_UARTDBG_CR_OUT2 13 | ||
215 | #define BM_UARTDBG_CR_OUT2 0x2000 | ||
216 | #define BF_UARTDBG_CR_OUT2(v) (((v) << 13) & 0x2000) | ||
217 | #define BP_UARTDBG_CR_OUT1 12 | ||
218 | #define BM_UARTDBG_CR_OUT1 0x1000 | ||
219 | #define BF_UARTDBG_CR_OUT1(v) (((v) << 12) & 0x1000) | ||
220 | #define BP_UARTDBG_CR_RTS 11 | ||
221 | #define BM_UARTDBG_CR_RTS 0x800 | ||
222 | #define BF_UARTDBG_CR_RTS(v) (((v) << 11) & 0x800) | ||
223 | #define BP_UARTDBG_CR_DTR 10 | ||
224 | #define BM_UARTDBG_CR_DTR 0x400 | ||
225 | #define BF_UARTDBG_CR_DTR(v) (((v) << 10) & 0x400) | ||
226 | #define BP_UARTDBG_CR_RXE 9 | ||
227 | #define BM_UARTDBG_CR_RXE 0x200 | ||
228 | #define BF_UARTDBG_CR_RXE(v) (((v) << 9) & 0x200) | ||
229 | #define BP_UARTDBG_CR_TXE 8 | ||
230 | #define BM_UARTDBG_CR_TXE 0x100 | ||
231 | #define BF_UARTDBG_CR_TXE(v) (((v) << 8) & 0x100) | ||
232 | #define BP_UARTDBG_CR_LBE 7 | ||
233 | #define BM_UARTDBG_CR_LBE 0x80 | ||
234 | #define BF_UARTDBG_CR_LBE(v) (((v) << 7) & 0x80) | ||
235 | #define BP_UARTDBG_CR_RESERVED 3 | ||
236 | #define BM_UARTDBG_CR_RESERVED 0x78 | ||
237 | #define BF_UARTDBG_CR_RESERVED(v) (((v) << 3) & 0x78) | ||
238 | #define BP_UARTDBG_CR_SIRLP 2 | ||
239 | #define BM_UARTDBG_CR_SIRLP 0x4 | ||
240 | #define BF_UARTDBG_CR_SIRLP(v) (((v) << 2) & 0x4) | ||
241 | #define BP_UARTDBG_CR_SIREN 1 | ||
242 | #define BM_UARTDBG_CR_SIREN 0x2 | ||
243 | #define BF_UARTDBG_CR_SIREN(v) (((v) << 1) & 0x2) | ||
244 | #define BP_UARTDBG_CR_UARTEN 0 | ||
245 | #define BM_UARTDBG_CR_UARTEN 0x1 | ||
246 | #define BF_UARTDBG_CR_UARTEN(v) (((v) << 0) & 0x1) | ||
247 | |||
248 | /** | ||
249 | * Register: HW_UARTDBG_IFLS | ||
250 | * Address: 0x34 | ||
251 | * SCT: no | ||
252 | */ | ||
253 | #define HW_UARTDBG_IFLS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34)) | ||
254 | #define BP_UARTDBG_IFLS_UNAVAILABLE 16 | ||
255 | #define BM_UARTDBG_IFLS_UNAVAILABLE 0xffff0000 | ||
256 | #define BF_UARTDBG_IFLS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
257 | #define BP_UARTDBG_IFLS_RESERVED 6 | ||
258 | #define BM_UARTDBG_IFLS_RESERVED 0xffc0 | ||
259 | #define BF_UARTDBG_IFLS_RESERVED(v) (((v) << 6) & 0xffc0) | ||
260 | #define BP_UARTDBG_IFLS_RXIFLSEL 3 | ||
261 | #define BM_UARTDBG_IFLS_RXIFLSEL 0x38 | ||
262 | #define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY 0x0 | ||
263 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER 0x1 | ||
264 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF 0x2 | ||
265 | #define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS 0x3 | ||
266 | #define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
267 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5 0x5 | ||
268 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6 0x6 | ||
269 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7 0x7 | ||
270 | #define BF_UARTDBG_IFLS_RXIFLSEL(v) (((v) << 3) & 0x38) | ||
271 | #define BF_UARTDBG_IFLS_RXIFLSEL_V(v) ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38) | ||
272 | #define BP_UARTDBG_IFLS_TXIFLSEL 0 | ||
273 | #define BM_UARTDBG_IFLS_TXIFLSEL 0x7 | ||
274 | #define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY 0x0 | ||
275 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER 0x1 | ||
276 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF 0x2 | ||
277 | #define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS 0x3 | ||
278 | #define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
279 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5 0x5 | ||
280 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6 0x6 | ||
281 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7 0x7 | ||
282 | #define BF_UARTDBG_IFLS_TXIFLSEL(v) (((v) << 0) & 0x7) | ||
283 | #define BF_UARTDBG_IFLS_TXIFLSEL_V(v) ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7) | ||
284 | |||
285 | /** | ||
286 | * Register: HW_UARTDBG_IMSC | ||
287 | * Address: 0x38 | ||
288 | * SCT: no | ||
289 | */ | ||
290 | #define HW_UARTDBG_IMSC (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38)) | ||
291 | #define BP_UARTDBG_IMSC_UNAVAILABLE 16 | ||
292 | #define BM_UARTDBG_IMSC_UNAVAILABLE 0xffff0000 | ||
293 | #define BF_UARTDBG_IMSC_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
294 | #define BP_UARTDBG_IMSC_RESERVED 11 | ||
295 | #define BM_UARTDBG_IMSC_RESERVED 0xf800 | ||
296 | #define BF_UARTDBG_IMSC_RESERVED(v) (((v) << 11) & 0xf800) | ||
297 | #define BP_UARTDBG_IMSC_OEIM 10 | ||
298 | #define BM_UARTDBG_IMSC_OEIM 0x400 | ||
299 | #define BF_UARTDBG_IMSC_OEIM(v) (((v) << 10) & 0x400) | ||
300 | #define BP_UARTDBG_IMSC_BEIM 9 | ||
301 | #define BM_UARTDBG_IMSC_BEIM 0x200 | ||
302 | #define BF_UARTDBG_IMSC_BEIM(v) (((v) << 9) & 0x200) | ||
303 | #define BP_UARTDBG_IMSC_PEIM 8 | ||
304 | #define BM_UARTDBG_IMSC_PEIM 0x100 | ||
305 | #define BF_UARTDBG_IMSC_PEIM(v) (((v) << 8) & 0x100) | ||
306 | #define BP_UARTDBG_IMSC_FEIM 7 | ||
307 | #define BM_UARTDBG_IMSC_FEIM 0x80 | ||
308 | #define BF_UARTDBG_IMSC_FEIM(v) (((v) << 7) & 0x80) | ||
309 | #define BP_UARTDBG_IMSC_RTIM 6 | ||
310 | #define BM_UARTDBG_IMSC_RTIM 0x40 | ||
311 | #define BF_UARTDBG_IMSC_RTIM(v) (((v) << 6) & 0x40) | ||
312 | #define BP_UARTDBG_IMSC_TXIM 5 | ||
313 | #define BM_UARTDBG_IMSC_TXIM 0x20 | ||
314 | #define BF_UARTDBG_IMSC_TXIM(v) (((v) << 5) & 0x20) | ||
315 | #define BP_UARTDBG_IMSC_RXIM 4 | ||
316 | #define BM_UARTDBG_IMSC_RXIM 0x10 | ||
317 | #define BF_UARTDBG_IMSC_RXIM(v) (((v) << 4) & 0x10) | ||
318 | #define BP_UARTDBG_IMSC_DSRMIM 3 | ||
319 | #define BM_UARTDBG_IMSC_DSRMIM 0x8 | ||
320 | #define BF_UARTDBG_IMSC_DSRMIM(v) (((v) << 3) & 0x8) | ||
321 | #define BP_UARTDBG_IMSC_DCDMIM 2 | ||
322 | #define BM_UARTDBG_IMSC_DCDMIM 0x4 | ||
323 | #define BF_UARTDBG_IMSC_DCDMIM(v) (((v) << 2) & 0x4) | ||
324 | #define BP_UARTDBG_IMSC_CTSMIM 1 | ||
325 | #define BM_UARTDBG_IMSC_CTSMIM 0x2 | ||
326 | #define BF_UARTDBG_IMSC_CTSMIM(v) (((v) << 1) & 0x2) | ||
327 | #define BP_UARTDBG_IMSC_RIMIM 0 | ||
328 | #define BM_UARTDBG_IMSC_RIMIM 0x1 | ||
329 | #define BF_UARTDBG_IMSC_RIMIM(v) (((v) << 0) & 0x1) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_UARTDBG_RIS | ||
333 | * Address: 0x3c | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_UARTDBG_RIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c)) | ||
337 | #define BP_UARTDBG_RIS_UNAVAILABLE 16 | ||
338 | #define BM_UARTDBG_RIS_UNAVAILABLE 0xffff0000 | ||
339 | #define BF_UARTDBG_RIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
340 | #define BP_UARTDBG_RIS_RESERVED 11 | ||
341 | #define BM_UARTDBG_RIS_RESERVED 0xf800 | ||
342 | #define BF_UARTDBG_RIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
343 | #define BP_UARTDBG_RIS_OERIS 10 | ||
344 | #define BM_UARTDBG_RIS_OERIS 0x400 | ||
345 | #define BF_UARTDBG_RIS_OERIS(v) (((v) << 10) & 0x400) | ||
346 | #define BP_UARTDBG_RIS_BERIS 9 | ||
347 | #define BM_UARTDBG_RIS_BERIS 0x200 | ||
348 | #define BF_UARTDBG_RIS_BERIS(v) (((v) << 9) & 0x200) | ||
349 | #define BP_UARTDBG_RIS_PERIS 8 | ||
350 | #define BM_UARTDBG_RIS_PERIS 0x100 | ||
351 | #define BF_UARTDBG_RIS_PERIS(v) (((v) << 8) & 0x100) | ||
352 | #define BP_UARTDBG_RIS_FERIS 7 | ||
353 | #define BM_UARTDBG_RIS_FERIS 0x80 | ||
354 | #define BF_UARTDBG_RIS_FERIS(v) (((v) << 7) & 0x80) | ||
355 | #define BP_UARTDBG_RIS_RTRIS 6 | ||
356 | #define BM_UARTDBG_RIS_RTRIS 0x40 | ||
357 | #define BF_UARTDBG_RIS_RTRIS(v) (((v) << 6) & 0x40) | ||
358 | #define BP_UARTDBG_RIS_TXRIS 5 | ||
359 | #define BM_UARTDBG_RIS_TXRIS 0x20 | ||
360 | #define BF_UARTDBG_RIS_TXRIS(v) (((v) << 5) & 0x20) | ||
361 | #define BP_UARTDBG_RIS_RXRIS 4 | ||
362 | #define BM_UARTDBG_RIS_RXRIS 0x10 | ||
363 | #define BF_UARTDBG_RIS_RXRIS(v) (((v) << 4) & 0x10) | ||
364 | #define BP_UARTDBG_RIS_DSRRMIS 3 | ||
365 | #define BM_UARTDBG_RIS_DSRRMIS 0x8 | ||
366 | #define BF_UARTDBG_RIS_DSRRMIS(v) (((v) << 3) & 0x8) | ||
367 | #define BP_UARTDBG_RIS_DCDRMIS 2 | ||
368 | #define BM_UARTDBG_RIS_DCDRMIS 0x4 | ||
369 | #define BF_UARTDBG_RIS_DCDRMIS(v) (((v) << 2) & 0x4) | ||
370 | #define BP_UARTDBG_RIS_CTSRMIS 1 | ||
371 | #define BM_UARTDBG_RIS_CTSRMIS 0x2 | ||
372 | #define BF_UARTDBG_RIS_CTSRMIS(v) (((v) << 1) & 0x2) | ||
373 | #define BP_UARTDBG_RIS_RIRMIS 0 | ||
374 | #define BM_UARTDBG_RIS_RIRMIS 0x1 | ||
375 | #define BF_UARTDBG_RIS_RIRMIS(v) (((v) << 0) & 0x1) | ||
376 | |||
377 | /** | ||
378 | * Register: HW_UARTDBG_MIS | ||
379 | * Address: 0x40 | ||
380 | * SCT: no | ||
381 | */ | ||
382 | #define HW_UARTDBG_MIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40)) | ||
383 | #define BP_UARTDBG_MIS_UNAVAILABLE 16 | ||
384 | #define BM_UARTDBG_MIS_UNAVAILABLE 0xffff0000 | ||
385 | #define BF_UARTDBG_MIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
386 | #define BP_UARTDBG_MIS_RESERVED 11 | ||
387 | #define BM_UARTDBG_MIS_RESERVED 0xf800 | ||
388 | #define BF_UARTDBG_MIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
389 | #define BP_UARTDBG_MIS_OEMIS 10 | ||
390 | #define BM_UARTDBG_MIS_OEMIS 0x400 | ||
391 | #define BF_UARTDBG_MIS_OEMIS(v) (((v) << 10) & 0x400) | ||
392 | #define BP_UARTDBG_MIS_BEMIS 9 | ||
393 | #define BM_UARTDBG_MIS_BEMIS 0x200 | ||
394 | #define BF_UARTDBG_MIS_BEMIS(v) (((v) << 9) & 0x200) | ||
395 | #define BP_UARTDBG_MIS_PEMIS 8 | ||
396 | #define BM_UARTDBG_MIS_PEMIS 0x100 | ||
397 | #define BF_UARTDBG_MIS_PEMIS(v) (((v) << 8) & 0x100) | ||
398 | #define BP_UARTDBG_MIS_FEMIS 7 | ||
399 | #define BM_UARTDBG_MIS_FEMIS 0x80 | ||
400 | #define BF_UARTDBG_MIS_FEMIS(v) (((v) << 7) & 0x80) | ||
401 | #define BP_UARTDBG_MIS_RTMIS 6 | ||
402 | #define BM_UARTDBG_MIS_RTMIS 0x40 | ||
403 | #define BF_UARTDBG_MIS_RTMIS(v) (((v) << 6) & 0x40) | ||
404 | #define BP_UARTDBG_MIS_TXMIS 5 | ||
405 | #define BM_UARTDBG_MIS_TXMIS 0x20 | ||
406 | #define BF_UARTDBG_MIS_TXMIS(v) (((v) << 5) & 0x20) | ||
407 | #define BP_UARTDBG_MIS_RXMIS 4 | ||
408 | #define BM_UARTDBG_MIS_RXMIS 0x10 | ||
409 | #define BF_UARTDBG_MIS_RXMIS(v) (((v) << 4) & 0x10) | ||
410 | #define BP_UARTDBG_MIS_DSRMMIS 3 | ||
411 | #define BM_UARTDBG_MIS_DSRMMIS 0x8 | ||
412 | #define BF_UARTDBG_MIS_DSRMMIS(v) (((v) << 3) & 0x8) | ||
413 | #define BP_UARTDBG_MIS_DCDMMIS 2 | ||
414 | #define BM_UARTDBG_MIS_DCDMMIS 0x4 | ||
415 | #define BF_UARTDBG_MIS_DCDMMIS(v) (((v) << 2) & 0x4) | ||
416 | #define BP_UARTDBG_MIS_CTSMMIS 1 | ||
417 | #define BM_UARTDBG_MIS_CTSMMIS 0x2 | ||
418 | #define BF_UARTDBG_MIS_CTSMMIS(v) (((v) << 1) & 0x2) | ||
419 | #define BP_UARTDBG_MIS_RIMMIS 0 | ||
420 | #define BM_UARTDBG_MIS_RIMMIS 0x1 | ||
421 | #define BF_UARTDBG_MIS_RIMMIS(v) (((v) << 0) & 0x1) | ||
422 | |||
423 | /** | ||
424 | * Register: HW_UARTDBG_ICR | ||
425 | * Address: 0x44 | ||
426 | * SCT: no | ||
427 | */ | ||
428 | #define HW_UARTDBG_ICR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44)) | ||
429 | #define BP_UARTDBG_ICR_UNAVAILABLE 16 | ||
430 | #define BM_UARTDBG_ICR_UNAVAILABLE 0xffff0000 | ||
431 | #define BF_UARTDBG_ICR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
432 | #define BP_UARTDBG_ICR_RESERVED 11 | ||
433 | #define BM_UARTDBG_ICR_RESERVED 0xf800 | ||
434 | #define BF_UARTDBG_ICR_RESERVED(v) (((v) << 11) & 0xf800) | ||
435 | #define BP_UARTDBG_ICR_OEIC 10 | ||
436 | #define BM_UARTDBG_ICR_OEIC 0x400 | ||
437 | #define BF_UARTDBG_ICR_OEIC(v) (((v) << 10) & 0x400) | ||
438 | #define BP_UARTDBG_ICR_BEIC 9 | ||
439 | #define BM_UARTDBG_ICR_BEIC 0x200 | ||
440 | #define BF_UARTDBG_ICR_BEIC(v) (((v) << 9) & 0x200) | ||
441 | #define BP_UARTDBG_ICR_PEIC 8 | ||
442 | #define BM_UARTDBG_ICR_PEIC 0x100 | ||
443 | #define BF_UARTDBG_ICR_PEIC(v) (((v) << 8) & 0x100) | ||
444 | #define BP_UARTDBG_ICR_FEIC 7 | ||
445 | #define BM_UARTDBG_ICR_FEIC 0x80 | ||
446 | #define BF_UARTDBG_ICR_FEIC(v) (((v) << 7) & 0x80) | ||
447 | #define BP_UARTDBG_ICR_RTIC 6 | ||
448 | #define BM_UARTDBG_ICR_RTIC 0x40 | ||
449 | #define BF_UARTDBG_ICR_RTIC(v) (((v) << 6) & 0x40) | ||
450 | #define BP_UARTDBG_ICR_TXIC 5 | ||
451 | #define BM_UARTDBG_ICR_TXIC 0x20 | ||
452 | #define BF_UARTDBG_ICR_TXIC(v) (((v) << 5) & 0x20) | ||
453 | #define BP_UARTDBG_ICR_RXIC 4 | ||
454 | #define BM_UARTDBG_ICR_RXIC 0x10 | ||
455 | #define BF_UARTDBG_ICR_RXIC(v) (((v) << 4) & 0x10) | ||
456 | #define BP_UARTDBG_ICR_DSRMIC 3 | ||
457 | #define BM_UARTDBG_ICR_DSRMIC 0x8 | ||
458 | #define BF_UARTDBG_ICR_DSRMIC(v) (((v) << 3) & 0x8) | ||
459 | #define BP_UARTDBG_ICR_DCDMIC 2 | ||
460 | #define BM_UARTDBG_ICR_DCDMIC 0x4 | ||
461 | #define BF_UARTDBG_ICR_DCDMIC(v) (((v) << 2) & 0x4) | ||
462 | #define BP_UARTDBG_ICR_CTSMIC 1 | ||
463 | #define BM_UARTDBG_ICR_CTSMIC 0x2 | ||
464 | #define BF_UARTDBG_ICR_CTSMIC(v) (((v) << 1) & 0x2) | ||
465 | #define BP_UARTDBG_ICR_RIMIC 0 | ||
466 | #define BM_UARTDBG_ICR_RIMIC 0x1 | ||
467 | #define BF_UARTDBG_ICR_RIMIC(v) (((v) << 0) & 0x1) | ||
468 | |||
469 | /** | ||
470 | * Register: HW_UARTDBG_DMACR | ||
471 | * Address: 0x48 | ||
472 | * SCT: no | ||
473 | */ | ||
474 | #define HW_UARTDBG_DMACR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48)) | ||
475 | #define BP_UARTDBG_DMACR_UNAVAILABLE 16 | ||
476 | #define BM_UARTDBG_DMACR_UNAVAILABLE 0xffff0000 | ||
477 | #define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
478 | #define BP_UARTDBG_DMACR_RESERVED 3 | ||
479 | #define BM_UARTDBG_DMACR_RESERVED 0xfff8 | ||
480 | #define BF_UARTDBG_DMACR_RESERVED(v) (((v) << 3) & 0xfff8) | ||
481 | #define BP_UARTDBG_DMACR_DMAONERR 2 | ||
482 | #define BM_UARTDBG_DMACR_DMAONERR 0x4 | ||
483 | #define BF_UARTDBG_DMACR_DMAONERR(v) (((v) << 2) & 0x4) | ||
484 | #define BP_UARTDBG_DMACR_TXDMAE 1 | ||
485 | #define BM_UARTDBG_DMACR_TXDMAE 0x2 | ||
486 | #define BF_UARTDBG_DMACR_TXDMAE(v) (((v) << 1) & 0x2) | ||
487 | #define BP_UARTDBG_DMACR_RXDMAE 0 | ||
488 | #define BM_UARTDBG_DMACR_RXDMAE 0x1 | ||
489 | #define BF_UARTDBG_DMACR_RXDMAE(v) (((v) << 0) & 0x1) | ||
490 | |||
491 | #endif /* __HEADERGEN__STMP3600__UARTDBG__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h new file mode 100644 index 0000000000..f255a3bc6c --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h | |||
@@ -0,0 +1,405 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__USBPHY__H__ | ||
24 | #define __HEADERGEN__STMP3600__USBPHY__H__ | ||
25 | |||
26 | #define REGS_USBPHY_BASE (0x8007c000) | ||
27 | |||
28 | #define REGS_USBPHY_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_USBPHY_PWD | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_USBPHY_PWD (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0)) | ||
36 | #define HW_USBPHY_PWD_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4)) | ||
37 | #define HW_USBPHY_PWD_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8)) | ||
38 | #define HW_USBPHY_PWD_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc)) | ||
39 | #define BP_USBPHY_PWD_RXPWDRX 20 | ||
40 | #define BM_USBPHY_PWD_RXPWDRX 0x100000 | ||
41 | #define BF_USBPHY_PWD_RXPWDRX(v) (((v) << 20) & 0x100000) | ||
42 | #define BP_USBPHY_PWD_RXPWDDIFF 19 | ||
43 | #define BM_USBPHY_PWD_RXPWDDIFF 0x80000 | ||
44 | #define BF_USBPHY_PWD_RXPWDDIFF(v) (((v) << 19) & 0x80000) | ||
45 | #define BP_USBPHY_PWD_RXPWD1PT1 18 | ||
46 | #define BM_USBPHY_PWD_RXPWD1PT1 0x40000 | ||
47 | #define BF_USBPHY_PWD_RXPWD1PT1(v) (((v) << 18) & 0x40000) | ||
48 | #define BP_USBPHY_PWD_RXPWDENV 17 | ||
49 | #define BM_USBPHY_PWD_RXPWDENV 0x20000 | ||
50 | #define BF_USBPHY_PWD_RXPWDENV(v) (((v) << 17) & 0x20000) | ||
51 | #define BP_USBPHY_PWD_TXPWDCOMP 14 | ||
52 | #define BM_USBPHY_PWD_TXPWDCOMP 0x4000 | ||
53 | #define BF_USBPHY_PWD_TXPWDCOMP(v) (((v) << 14) & 0x4000) | ||
54 | #define BP_USBPHY_PWD_TXPWDVBG 13 | ||
55 | #define BM_USBPHY_PWD_TXPWDVBG 0x2000 | ||
56 | #define BF_USBPHY_PWD_TXPWDVBG(v) (((v) << 13) & 0x2000) | ||
57 | #define BP_USBPHY_PWD_TXPWDV2I 12 | ||
58 | #define BM_USBPHY_PWD_TXPWDV2I 0x1000 | ||
59 | #define BF_USBPHY_PWD_TXPWDV2I(v) (((v) << 12) & 0x1000) | ||
60 | #define BP_USBPHY_PWD_TXPWDIBIAS 11 | ||
61 | #define BM_USBPHY_PWD_TXPWDIBIAS 0x800 | ||
62 | #define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800) | ||
63 | #define BP_USBPHY_PWD_TXPWDFS 10 | ||
64 | #define BM_USBPHY_PWD_TXPWDFS 0x400 | ||
65 | #define BF_USBPHY_PWD_TXPWDFS(v) (((v) << 10) & 0x400) | ||
66 | |||
67 | /** | ||
68 | * Register: HW_USBPHY_TX | ||
69 | * Address: 0x10 | ||
70 | * SCT: yes | ||
71 | */ | ||
72 | #define HW_USBPHY_TX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0)) | ||
73 | #define HW_USBPHY_TX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4)) | ||
74 | #define HW_USBPHY_TX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8)) | ||
75 | #define HW_USBPHY_TX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc)) | ||
76 | #define BP_USBPHY_TX_TXCMPOUT_STATUS 23 | ||
77 | #define BM_USBPHY_TX_TXCMPOUT_STATUS 0x800000 | ||
78 | #define BF_USBPHY_TX_TXCMPOUT_STATUS(v) (((v) << 23) & 0x800000) | ||
79 | #define BP_USBPHY_TX_TXENCAL45DP 21 | ||
80 | #define BM_USBPHY_TX_TXENCAL45DP 0x200000 | ||
81 | #define BF_USBPHY_TX_TXENCAL45DP(v) (((v) << 21) & 0x200000) | ||
82 | #define BP_USBPHY_TX_TXCAL45DP 16 | ||
83 | #define BM_USBPHY_TX_TXCAL45DP 0x1f0000 | ||
84 | #define BF_USBPHY_TX_TXCAL45DP(v) (((v) << 16) & 0x1f0000) | ||
85 | #define BP_USBPHY_TX_TXENCAL45DN 13 | ||
86 | #define BM_USBPHY_TX_TXENCAL45DN 0x2000 | ||
87 | #define BF_USBPHY_TX_TXENCAL45DN(v) (((v) << 13) & 0x2000) | ||
88 | #define BP_USBPHY_TX_TXCAL45DN 8 | ||
89 | #define BM_USBPHY_TX_TXCAL45DN 0x1f00 | ||
90 | #define BF_USBPHY_TX_TXCAL45DN(v) (((v) << 8) & 0x1f00) | ||
91 | #define BP_USBPHY_TX_TXCALIBRATE 7 | ||
92 | #define BM_USBPHY_TX_TXCALIBRATE 0x80 | ||
93 | #define BF_USBPHY_TX_TXCALIBRATE(v) (((v) << 7) & 0x80) | ||
94 | |||
95 | /** | ||
96 | * Register: HW_USBPHY_RX | ||
97 | * Address: 0x20 | ||
98 | * SCT: yes | ||
99 | */ | ||
100 | #define HW_USBPHY_RX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0)) | ||
101 | #define HW_USBPHY_RX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4)) | ||
102 | #define HW_USBPHY_RX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8)) | ||
103 | #define HW_USBPHY_RX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc)) | ||
104 | #define BP_USBPHY_RX_RXDBYPASS 22 | ||
105 | #define BM_USBPHY_RX_RXDBYPASS 0x400000 | ||
106 | #define BF_USBPHY_RX_RXDBYPASS(v) (((v) << 22) & 0x400000) | ||
107 | #define BP_USBPHY_RX_DISCONADJ 4 | ||
108 | #define BM_USBPHY_RX_DISCONADJ 0x30 | ||
109 | #define BF_USBPHY_RX_DISCONADJ(v) (((v) << 4) & 0x30) | ||
110 | #define BP_USBPHY_RX_ENVADJ 0 | ||
111 | #define BM_USBPHY_RX_ENVADJ 0x3 | ||
112 | #define BF_USBPHY_RX_ENVADJ(v) (((v) << 0) & 0x3) | ||
113 | |||
114 | /** | ||
115 | * Register: HW_USBPHY_CTRL | ||
116 | * Address: 0x30 | ||
117 | * SCT: yes | ||
118 | */ | ||
119 | #define HW_USBPHY_CTRL (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0)) | ||
120 | #define HW_USBPHY_CTRL_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4)) | ||
121 | #define HW_USBPHY_CTRL_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8)) | ||
122 | #define HW_USBPHY_CTRL_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc)) | ||
123 | #define BP_USBPHY_CTRL_SFTRST 31 | ||
124 | #define BM_USBPHY_CTRL_SFTRST 0x80000000 | ||
125 | #define BF_USBPHY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
126 | #define BP_USBPHY_CTRL_CLKGATE 30 | ||
127 | #define BM_USBPHY_CTRL_CLKGATE 0x40000000 | ||
128 | #define BF_USBPHY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
129 | #define BP_USBPHY_CTRL_UTMI_SUSPENDM 29 | ||
130 | #define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 | ||
131 | #define BF_USBPHY_CTRL_UTMI_SUSPENDM(v) (((v) << 29) & 0x20000000) | ||
132 | #define BP_USBPHY_CTRL_RESUME_IRQ 10 | ||
133 | #define BM_USBPHY_CTRL_RESUME_IRQ 0x400 | ||
134 | #define BF_USBPHY_CTRL_RESUME_IRQ(v) (((v) << 10) & 0x400) | ||
135 | #define BP_USBPHY_CTRL_ENIRQRESUMEDETECT 9 | ||
136 | #define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x200 | ||
137 | #define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v) (((v) << 9) & 0x200) | ||
138 | #define BP_USBPHY_CTRL_ENOTGIDDETECT 7 | ||
139 | #define BM_USBPHY_CTRL_ENOTGIDDETECT 0x80 | ||
140 | #define BF_USBPHY_CTRL_ENOTGIDDETECT(v) (((v) << 7) & 0x80) | ||
141 | #define BP_USBPHY_CTRL_ENDEVPLUGINDETECT 4 | ||
142 | #define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x10 | ||
143 | #define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v) (((v) << 4) & 0x10) | ||
144 | #define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 3 | ||
145 | #define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x8 | ||
146 | #define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v) (((v) << 3) & 0x8) | ||
147 | #define BP_USBPHY_CTRL_ENIRQHOSTDISCON 2 | ||
148 | #define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x4 | ||
149 | #define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v) (((v) << 2) & 0x4) | ||
150 | #define BP_USBPHY_CTRL_ENHOSTDISCONDETECT 1 | ||
151 | #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x2 | ||
152 | #define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v) (((v) << 1) & 0x2) | ||
153 | #define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0 | ||
154 | #define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x1 | ||
155 | #define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v) (((v) << 0) & 0x1) | ||
156 | |||
157 | /** | ||
158 | * Register: HW_USBPHY_STATUS | ||
159 | * Address: 0x40 | ||
160 | * SCT: no | ||
161 | */ | ||
162 | #define HW_USBPHY_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40)) | ||
163 | #define BP_USBPHY_STATUS_RESUME_STATUS 10 | ||
164 | #define BM_USBPHY_STATUS_RESUME_STATUS 0x400 | ||
165 | #define BF_USBPHY_STATUS_RESUME_STATUS(v) (((v) << 10) & 0x400) | ||
166 | #define BP_USBPHY_STATUS_OTGID_STATUS 8 | ||
167 | #define BM_USBPHY_STATUS_OTGID_STATUS 0x100 | ||
168 | #define BF_USBPHY_STATUS_OTGID_STATUS(v) (((v) << 8) & 0x100) | ||
169 | #define BP_USBPHY_STATUS_DEVPLUGIN_STATUS 6 | ||
170 | #define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x40 | ||
171 | #define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v) (((v) << 6) & 0x40) | ||
172 | #define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 3 | ||
173 | #define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x8 | ||
174 | #define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8) | ||
175 | |||
176 | /** | ||
177 | * Register: HW_USBPHY_DEBUG | ||
178 | * Address: 0x50 | ||
179 | * SCT: yes | ||
180 | */ | ||
181 | #define HW_USBPHY_DEBUG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0)) | ||
182 | #define HW_USBPHY_DEBUG_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4)) | ||
183 | #define HW_USBPHY_DEBUG_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8)) | ||
184 | #define HW_USBPHY_DEBUG_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc)) | ||
185 | #define BP_USBPHY_DEBUG_CLKGATE 30 | ||
186 | #define BM_USBPHY_DEBUG_CLKGATE 0x40000000 | ||
187 | #define BF_USBPHY_DEBUG_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
188 | #define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 | ||
189 | #define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1e000000 | ||
190 | #define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) (((v) << 25) & 0x1e000000) | ||
191 | #define BP_USBPHY_DEBUG_ENSQUELCHRESET 24 | ||
192 | #define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x1000000 | ||
193 | #define BF_USBPHY_DEBUG_ENSQUELCHRESET(v) (((v) << 24) & 0x1000000) | ||
194 | #define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 | ||
195 | #define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x1f0000 | ||
196 | #define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) (((v) << 16) & 0x1f0000) | ||
197 | #define BP_USBPHY_DEBUG_ENTX2RXCOUNT 12 | ||
198 | #define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x1000 | ||
199 | #define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v) (((v) << 12) & 0x1000) | ||
200 | #define BP_USBPHY_DEBUG_TX2RXCOUNT 8 | ||
201 | #define BM_USBPHY_DEBUG_TX2RXCOUNT 0xf00 | ||
202 | #define BF_USBPHY_DEBUG_TX2RXCOUNT(v) (((v) << 8) & 0xf00) | ||
203 | #define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 | ||
204 | #define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x30 | ||
205 | #define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) (((v) << 4) & 0x30) | ||
206 | #define BP_USBPHY_DEBUG_HSTPULLDOWN 2 | ||
207 | #define BM_USBPHY_DEBUG_HSTPULLDOWN 0xc | ||
208 | #define BF_USBPHY_DEBUG_HSTPULLDOWN(v) (((v) << 2) & 0xc) | ||
209 | #define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 1 | ||
210 | #define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x2 | ||
211 | #define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2) | ||
212 | #define BP_USBPHY_DEBUG_OTGIDPIOLOCK 0 | ||
213 | #define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x1 | ||
214 | #define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v) (((v) << 0) & 0x1) | ||
215 | |||
216 | /** | ||
217 | * Register: HW_USBPHY_DEBUG0_STATUS | ||
218 | * Address: 0x60 | ||
219 | * SCT: no | ||
220 | */ | ||
221 | #define HW_USBPHY_DEBUG0_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60)) | ||
222 | #define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 | ||
223 | #define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xfc000000 | ||
224 | #define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) (((v) << 26) & 0xfc000000) | ||
225 | #define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 | ||
226 | #define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x3ff0000 | ||
227 | #define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
228 | #define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 | ||
229 | #define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0xffff | ||
230 | #define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) (((v) << 0) & 0xffff) | ||
231 | |||
232 | /** | ||
233 | * Register: HW_USBPHY_DEBUG1_STATUS | ||
234 | * Address: 0x70 | ||
235 | * SCT: no | ||
236 | */ | ||
237 | #define HW_USBPHY_DEBUG1_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70)) | ||
238 | #define BP_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA 16 | ||
239 | #define BM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA 0xffff0000 | ||
240 | #define BF_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA(v) (((v) << 16) & 0xffff0000) | ||
241 | #define BP_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA 0 | ||
242 | #define BM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA 0xffff | ||
243 | #define BF_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA(v) (((v) << 0) & 0xffff) | ||
244 | |||
245 | /** | ||
246 | * Register: HW_USBPHY_DEBUG2_STATUS | ||
247 | * Address: 0x80 | ||
248 | * SCT: no | ||
249 | */ | ||
250 | #define HW_USBPHY_DEBUG2_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80)) | ||
251 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH 22 | ||
252 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH 0x400000 | ||
253 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH(v) (((v) << 22) & 0x400000) | ||
254 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALID 21 | ||
255 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID 0x200000 | ||
256 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALID(v) (((v) << 21) & 0x200000) | ||
257 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT 20 | ||
258 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT 0x100000 | ||
259 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT(v) (((v) << 20) & 0x100000) | ||
260 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT 18 | ||
261 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT 0xc0000 | ||
262 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT(v) (((v) << 18) & 0xc0000) | ||
263 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_OPMODE 16 | ||
264 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE 0x30000 | ||
265 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_OPMODE(v) (((v) << 16) & 0x30000) | ||
266 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE 6 | ||
267 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE 0xc0 | ||
268 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE(v) (((v) << 6) & 0xc0) | ||
269 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM 5 | ||
270 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM 0x20 | ||
271 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM(v) (((v) << 5) & 0x20) | ||
272 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH 4 | ||
273 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH 0x10 | ||
274 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH(v) (((v) << 4) & 0x10) | ||
275 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALID 3 | ||
276 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID 0x8 | ||
277 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALID(v) (((v) << 3) & 0x8) | ||
278 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE 2 | ||
279 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE 0x4 | ||
280 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE(v) (((v) << 2) & 0x4) | ||
281 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_RXERROR 1 | ||
282 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR 0x2 | ||
283 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_RXERROR(v) (((v) << 1) & 0x2) | ||
284 | #define BP_USBPHY_DEBUG2_STATUS_UTMI_TXREADY 0 | ||
285 | #define BM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY 0x1 | ||
286 | #define BF_USBPHY_DEBUG2_STATUS_UTMI_TXREADY(v) (((v) << 0) & 0x1) | ||
287 | |||
288 | /** | ||
289 | * Register: HW_USBPHY_DEBUG3_STATUS | ||
290 | * Address: 0x90 | ||
291 | * SCT: no | ||
292 | */ | ||
293 | #define HW_USBPHY_DEBUG3_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90)) | ||
294 | #define BP_USBPHY_DEBUG3_STATUS_B_CNT_FSM 28 | ||
295 | #define BM_USBPHY_DEBUG3_STATUS_B_CNT_FSM 0x70000000 | ||
296 | #define BF_USBPHY_DEBUG3_STATUS_B_CNT_FSM(v) (((v) << 28) & 0x70000000) | ||
297 | #define BP_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM 23 | ||
298 | #define BM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM 0x3800000 | ||
299 | #define BF_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM(v) (((v) << 23) & 0x3800000) | ||
300 | #define BP_USBPHY_DEBUG3_STATUS_BIT_CNT 12 | ||
301 | #define BM_USBPHY_DEBUG3_STATUS_BIT_CNT 0x3ff000 | ||
302 | #define BF_USBPHY_DEBUG3_STATUS_BIT_CNT(v) (((v) << 12) & 0x3ff000) | ||
303 | #define BP_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM 8 | ||
304 | #define BM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM 0xf00 | ||
305 | #define BF_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM(v) (((v) << 8) & 0xf00) | ||
306 | #define BP_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT 0 | ||
307 | #define BM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT 0xff | ||
308 | #define BF_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT(v) (((v) << 0) & 0xff) | ||
309 | |||
310 | /** | ||
311 | * Register: HW_USBPHY_DEBUG4_STATUS | ||
312 | * Address: 0xa0 | ||
313 | * SCT: no | ||
314 | */ | ||
315 | #define HW_USBPHY_DEBUG4_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xa0)) | ||
316 | #define BP_USBPHY_DEBUG4_STATUS_BYTE_FSM 16 | ||
317 | #define BM_USBPHY_DEBUG4_STATUS_BYTE_FSM 0x1fff0000 | ||
318 | #define BF_USBPHY_DEBUG4_STATUS_BYTE_FSM(v) (((v) << 16) & 0x1fff0000) | ||
319 | #define BP_USBPHY_DEBUG4_STATUS_SND_FSM 0 | ||
320 | #define BM_USBPHY_DEBUG4_STATUS_SND_FSM 0x3fff | ||
321 | #define BF_USBPHY_DEBUG4_STATUS_SND_FSM(v) (((v) << 0) & 0x3fff) | ||
322 | |||
323 | /** | ||
324 | * Register: HW_USBPHY_DEBUG5_STATUS | ||
325 | * Address: 0xb0 | ||
326 | * SCT: no | ||
327 | */ | ||
328 | #define HW_USBPHY_DEBUG5_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xb0)) | ||
329 | #define BP_USBPHY_DEBUG5_STATUS_MAIN_FSM 24 | ||
330 | #define BM_USBPHY_DEBUG5_STATUS_MAIN_FSM 0xf000000 | ||
331 | #define BF_USBPHY_DEBUG5_STATUS_MAIN_FSM(v) (((v) << 24) & 0xf000000) | ||
332 | #define BP_USBPHY_DEBUG5_STATUS_SYNC_FSM 16 | ||
333 | #define BM_USBPHY_DEBUG5_STATUS_SYNC_FSM 0x3f0000 | ||
334 | #define BF_USBPHY_DEBUG5_STATUS_SYNC_FSM(v) (((v) << 16) & 0x3f0000) | ||
335 | #define BP_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM 12 | ||
336 | #define BM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM 0x7000 | ||
337 | #define BF_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM(v) (((v) << 12) & 0x7000) | ||
338 | #define BP_USBPHY_DEBUG5_STATUS_SHIFT_FSM 8 | ||
339 | #define BM_USBPHY_DEBUG5_STATUS_SHIFT_FSM 0x700 | ||
340 | #define BF_USBPHY_DEBUG5_STATUS_SHIFT_FSM(v) (((v) << 8) & 0x700) | ||
341 | #define BP_USBPHY_DEBUG5_STATUS_SOF_FSM 0 | ||
342 | #define BM_USBPHY_DEBUG5_STATUS_SOF_FSM 0x1f | ||
343 | #define BF_USBPHY_DEBUG5_STATUS_SOF_FSM(v) (((v) << 0) & 0x1f) | ||
344 | |||
345 | /** | ||
346 | * Register: HW_USBPHY_DEBUG6_STATUS | ||
347 | * Address: 0xc0 | ||
348 | * SCT: no | ||
349 | */ | ||
350 | #define HW_USBPHY_DEBUG6_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xc0)) | ||
351 | #define BP_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM 8 | ||
352 | #define BM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM 0x700 | ||
353 | #define BF_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM(v) (((v) << 8) & 0x700) | ||
354 | #define BP_USBPHY_DEBUG6_STATUS_EOP_FSM 0 | ||
355 | #define BM_USBPHY_DEBUG6_STATUS_EOP_FSM 0xff | ||
356 | #define BF_USBPHY_DEBUG6_STATUS_EOP_FSM(v) (((v) << 0) & 0xff) | ||
357 | |||
358 | /** | ||
359 | * Register: HW_USBPHY_DEBUG7_STATUS | ||
360 | * Address: 0xd0 | ||
361 | * SCT: no | ||
362 | */ | ||
363 | #define HW_USBPHY_DEBUG7_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xd0)) | ||
364 | #define BP_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM 28 | ||
365 | #define BM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM 0x30000000 | ||
366 | #define BF_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM(v) (((v) << 28) & 0x30000000) | ||
367 | #define BP_USBPHY_DEBUG7_STATUS_BIT_CNT 24 | ||
368 | #define BM_USBPHY_DEBUG7_STATUS_BIT_CNT 0xf000000 | ||
369 | #define BF_USBPHY_DEBUG7_STATUS_BIT_CNT(v) (((v) << 24) & 0xf000000) | ||
370 | #define BP_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT 20 | ||
371 | #define BM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT 0x700000 | ||
372 | #define BF_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT(v) (((v) << 20) & 0x700000) | ||
373 | #define BP_USBPHY_DEBUG7_STATUS_LD_FSM 16 | ||
374 | #define BM_USBPHY_DEBUG7_STATUS_LD_FSM 0x30000 | ||
375 | #define BF_USBPHY_DEBUG7_STATUS_LD_FSM(v) (((v) << 16) & 0x30000) | ||
376 | #define BP_USBPHY_DEBUG7_STATUS_FIFO_FSM 8 | ||
377 | #define BM_USBPHY_DEBUG7_STATUS_FIFO_FSM 0x3f00 | ||
378 | #define BF_USBPHY_DEBUG7_STATUS_FIFO_FSM(v) (((v) << 8) & 0x3f00) | ||
379 | #define BP_USBPHY_DEBUG7_STATUS_MAIN_FSM 4 | ||
380 | #define BM_USBPHY_DEBUG7_STATUS_MAIN_FSM 0xf0 | ||
381 | #define BF_USBPHY_DEBUG7_STATUS_MAIN_FSM(v) (((v) << 4) & 0xf0) | ||
382 | #define BP_USBPHY_DEBUG7_STATUS_EOP_FSM 0 | ||
383 | #define BM_USBPHY_DEBUG7_STATUS_EOP_FSM 0xf | ||
384 | #define BF_USBPHY_DEBUG7_STATUS_EOP_FSM(v) (((v) << 0) & 0xf) | ||
385 | |||
386 | /** | ||
387 | * Register: HW_USBPHY_DEBUG8_STATUS | ||
388 | * Address: 0xe0 | ||
389 | * SCT: no | ||
390 | */ | ||
391 | #define HW_USBPHY_DEBUG8_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xe0)) | ||
392 | #define BP_USBPHY_DEBUG8_STATUS_RX_SIE_FSM 28 | ||
393 | #define BM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM 0xf0000000 | ||
394 | #define BF_USBPHY_DEBUG8_STATUS_RX_SIE_FSM(v) (((v) << 28) & 0xf0000000) | ||
395 | #define BP_USBPHY_DEBUG8_STATUS_TX_SIE_FSM 24 | ||
396 | #define BM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM 0xf000000 | ||
397 | #define BF_USBPHY_DEBUG8_STATUS_TX_SIE_FSM(v) (((v) << 24) & 0xf000000) | ||
398 | #define BP_USBPHY_DEBUG8_STATUS_SHIFT_FSM 8 | ||
399 | #define BM_USBPHY_DEBUG8_STATUS_SHIFT_FSM 0x300 | ||
400 | #define BF_USBPHY_DEBUG8_STATUS_SHIFT_FSM(v) (((v) << 8) & 0x300) | ||
401 | #define BP_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM 0 | ||
402 | #define BM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM 0x7f | ||
403 | #define BF_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM(v) (((v) << 0) & 0x7f) | ||
404 | |||
405 | #endif /* __HEADERGEN__STMP3600__USBPHY__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h new file mode 100644 index 0000000000..fe654841af --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h | |||
@@ -0,0 +1,301 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__APBH__H__ | ||
24 | #define __HEADERGEN__STMP3700__APBH__H__ | ||
25 | |||
26 | #define REGS_APBH_BASE (0x80004000) | ||
27 | |||
28 | #define REGS_APBH_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_APBH_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_APBH_CTRL0 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0)) | ||
36 | #define HW_APBH_CTRL0_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4)) | ||
37 | #define HW_APBH_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8)) | ||
38 | #define HW_APBH_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc)) | ||
39 | #define BP_APBH_CTRL0_SFTRST 31 | ||
40 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_APBH_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_APBH_CTRL0_CLKGATE 30 | ||
43 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_APBH_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
46 | #define BM_APBH_CTRL0_RESET_CHANNEL 0xff0000 | ||
47 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP1 0x1 | ||
48 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP2 0x2 | ||
49 | #define BV_APBH_CTRL0_RESET_CHANNEL__LCDIF 0x4 | ||
50 | #define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 | ||
51 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 | ||
52 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 | ||
53 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x40 | ||
54 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x80 | ||
55 | #define BF_APBH_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
56 | #define BF_APBH_CTRL0_RESET_CHANNEL_V(v) ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
57 | #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 | ||
58 | #define BM_APBH_CTRL0_CLKGATE_CHANNEL 0xff00 | ||
59 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x1 | ||
60 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x2 | ||
61 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x4 | ||
62 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 | ||
63 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 | ||
64 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 | ||
65 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x40 | ||
66 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x80 | ||
67 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) << 8) & 0xff00) | ||
68 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v) ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00) | ||
69 | #define BP_APBH_CTRL0_FREEZE_CHANNEL 0 | ||
70 | #define BM_APBH_CTRL0_FREEZE_CHANNEL 0xff | ||
71 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1 0x1 | ||
72 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2 0x2 | ||
73 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__LCDIF 0x4 | ||
74 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 | ||
75 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 | ||
76 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 | ||
77 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x30 | ||
78 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x40 | ||
79 | #define BF_APBH_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
80 | #define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
81 | |||
82 | /** | ||
83 | * Register: HW_APBH_CTRL1 | ||
84 | * Address: 0x10 | ||
85 | * SCT: yes | ||
86 | */ | ||
87 | #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0)) | ||
88 | #define HW_APBH_CTRL1_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4)) | ||
89 | #define HW_APBH_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8)) | ||
90 | #define HW_APBH_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc)) | ||
91 | #define BP_APBH_CTRL1_CH_AHB_ERROR_IRQ 16 | ||
92 | #define BM_APBH_CTRL1_CH_AHB_ERROR_IRQ 0xff0000 | ||
93 | #define BF_APBH_CTRL1_CH_AHB_ERROR_IRQ(v) (((v) << 16) & 0xff0000) | ||
94 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 8 | ||
95 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff00 | ||
96 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00) | ||
97 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
98 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
99 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
100 | |||
101 | /** | ||
102 | * Register: HW_APBH_DEVSEL | ||
103 | * Address: 0x20 | ||
104 | * SCT: no | ||
105 | */ | ||
106 | #define HW_APBH_DEVSEL (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20)) | ||
107 | #define BP_APBH_DEVSEL_CH7 28 | ||
108 | #define BM_APBH_DEVSEL_CH7 0xf0000000 | ||
109 | #define BF_APBH_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
110 | #define BP_APBH_DEVSEL_CH6 24 | ||
111 | #define BM_APBH_DEVSEL_CH6 0xf000000 | ||
112 | #define BF_APBH_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
113 | #define BP_APBH_DEVSEL_CH5 20 | ||
114 | #define BM_APBH_DEVSEL_CH5 0xf00000 | ||
115 | #define BF_APBH_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
116 | #define BP_APBH_DEVSEL_CH4 16 | ||
117 | #define BM_APBH_DEVSEL_CH4 0xf0000 | ||
118 | #define BF_APBH_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
119 | #define BP_APBH_DEVSEL_CH3 12 | ||
120 | #define BM_APBH_DEVSEL_CH3 0xf000 | ||
121 | #define BF_APBH_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
122 | #define BP_APBH_DEVSEL_CH2 8 | ||
123 | #define BM_APBH_DEVSEL_CH2 0xf00 | ||
124 | #define BF_APBH_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
125 | #define BP_APBH_DEVSEL_CH1 4 | ||
126 | #define BM_APBH_DEVSEL_CH1 0xf0 | ||
127 | #define BF_APBH_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
128 | #define BP_APBH_DEVSEL_CH0 0 | ||
129 | #define BM_APBH_DEVSEL_CH0 0xf | ||
130 | #define BF_APBH_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
131 | |||
132 | /** | ||
133 | * Register: HW_APBH_CHn_CURCMDAR | ||
134 | * Address: 0x40+n*0x70 | ||
135 | * SCT: no | ||
136 | */ | ||
137 | #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70)) | ||
138 | #define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 | ||
139 | #define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
140 | #define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
141 | |||
142 | /** | ||
143 | * Register: HW_APBH_CHn_NXTCMDAR | ||
144 | * Address: 0x50+n*0x70 | ||
145 | * SCT: no | ||
146 | */ | ||
147 | #define HW_APBH_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70)) | ||
148 | #define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 | ||
149 | #define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
150 | #define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_APBH_CHn_CMD | ||
154 | * Address: 0x60+n*0x70 | ||
155 | * SCT: no | ||
156 | */ | ||
157 | #define HW_APBH_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70)) | ||
158 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
159 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xffff0000 | ||
160 | #define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
161 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
162 | #define BM_APBH_CHn_CMD_CMDWORDS 0xf000 | ||
163 | #define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
164 | #define BP_APBH_CHn_CMD_HALTONTERMINATE 8 | ||
165 | #define BM_APBH_CHn_CMD_HALTONTERMINATE 0x100 | ||
166 | #define BF_APBH_CHn_CMD_HALTONTERMINATE(v) (((v) << 8) & 0x100) | ||
167 | #define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 | ||
168 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x80 | ||
169 | #define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
170 | #define BP_APBH_CHn_CMD_SEMAPHORE 6 | ||
171 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x40 | ||
172 | #define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
173 | #define BP_APBH_CHn_CMD_NANDWAIT4READY 5 | ||
174 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x20 | ||
175 | #define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & 0x20) | ||
176 | #define BP_APBH_CHn_CMD_NANDLOCK 4 | ||
177 | #define BM_APBH_CHn_CMD_NANDLOCK 0x10 | ||
178 | #define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & 0x10) | ||
179 | #define BP_APBH_CHn_CMD_IRQONCMPLT 3 | ||
180 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x8 | ||
181 | #define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
182 | #define BP_APBH_CHn_CMD_CHAIN 2 | ||
183 | #define BM_APBH_CHn_CMD_CHAIN 0x4 | ||
184 | #define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
185 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
186 | #define BM_APBH_CHn_CMD_COMMAND 0x3 | ||
187 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
188 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
189 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
190 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 | ||
191 | #define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
192 | #define BF_APBH_CHn_CMD_COMMAND_V(v) ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
193 | |||
194 | /** | ||
195 | * Register: HW_APBH_CHn_BAR | ||
196 | * Address: 0x70+n*0x70 | ||
197 | * SCT: no | ||
198 | */ | ||
199 | #define HW_APBH_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70)) | ||
200 | #define BP_APBH_CHn_BAR_ADDRESS 0 | ||
201 | #define BM_APBH_CHn_BAR_ADDRESS 0xffffffff | ||
202 | #define BF_APBH_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
203 | |||
204 | /** | ||
205 | * Register: HW_APBH_CHn_SEMA | ||
206 | * Address: 0x80+n*0x70 | ||
207 | * SCT: no | ||
208 | */ | ||
209 | #define HW_APBH_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70)) | ||
210 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
211 | #define BM_APBH_CHn_SEMA_PHORE 0xff0000 | ||
212 | #define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
213 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
214 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0xff | ||
215 | #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_APBH_CHn_DEBUG1 | ||
219 | * Address: 0x90+n*0x70 | ||
220 | * SCT: no | ||
221 | */ | ||
222 | #define HW_APBH_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70)) | ||
223 | #define BP_APBH_CHn_DEBUG1_REQ 31 | ||
224 | #define BM_APBH_CHn_DEBUG1_REQ 0x80000000 | ||
225 | #define BF_APBH_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
226 | #define BP_APBH_CHn_DEBUG1_BURST 30 | ||
227 | #define BM_APBH_CHn_DEBUG1_BURST 0x40000000 | ||
228 | #define BF_APBH_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
229 | #define BP_APBH_CHn_DEBUG1_KICK 29 | ||
230 | #define BM_APBH_CHn_DEBUG1_KICK 0x20000000 | ||
231 | #define BF_APBH_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
232 | #define BP_APBH_CHn_DEBUG1_END 28 | ||
233 | #define BM_APBH_CHn_DEBUG1_END 0x10000000 | ||
234 | #define BF_APBH_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
235 | #define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
236 | #define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
237 | #define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
238 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
239 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
240 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
241 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
242 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
243 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
244 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
245 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
246 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
247 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
248 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
249 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
250 | #define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 | ||
251 | #define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x1f | ||
252 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
253 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
254 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
255 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
256 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
257 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
258 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
259 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
260 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
261 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
262 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
263 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
264 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
265 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
266 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
267 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
268 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
269 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
270 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
271 | |||
272 | /** | ||
273 | * Register: HW_APBH_CHn_DEBUG2 | ||
274 | * Address: 0xa0+n*0x70 | ||
275 | * SCT: no | ||
276 | */ | ||
277 | #define HW_APBH_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0xa0+(n)*0x70)) | ||
278 | #define BP_APBH_CHn_DEBUG2_APB_BYTES 16 | ||
279 | #define BM_APBH_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
280 | #define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
281 | #define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 | ||
282 | #define BM_APBH_CHn_DEBUG2_AHB_BYTES 0xffff | ||
283 | #define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
284 | |||
285 | /** | ||
286 | * Register: HW_APBH_VERSION | ||
287 | * Address: 0x3f0 | ||
288 | * SCT: no | ||
289 | */ | ||
290 | #define HW_APBH_VERSION (*(volatile unsigned long *)(REGS_APBH_BASE + 0x3f0)) | ||
291 | #define BP_APBH_VERSION_MAJOR 24 | ||
292 | #define BM_APBH_VERSION_MAJOR 0xff000000 | ||
293 | #define BF_APBH_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
294 | #define BP_APBH_VERSION_MINOR 16 | ||
295 | #define BM_APBH_VERSION_MINOR 0xff0000 | ||
296 | #define BF_APBH_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
297 | #define BP_APBH_VERSION_STEP 0 | ||
298 | #define BM_APBH_VERSION_STEP 0xffff | ||
299 | #define BF_APBH_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
300 | |||
301 | #endif /* __HEADERGEN__STMP3700__APBH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h new file mode 100644 index 0000000000..5f93e5de3c --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h | |||
@@ -0,0 +1,294 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__APBX__H__ | ||
24 | #define __HEADERGEN__STMP3700__APBX__H__ | ||
25 | |||
26 | #define REGS_APBX_BASE (0x80024000) | ||
27 | |||
28 | #define REGS_APBX_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_APBX_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_APBX_CTRL0 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0)) | ||
36 | #define HW_APBX_CTRL0_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4)) | ||
37 | #define HW_APBX_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8)) | ||
38 | #define HW_APBX_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc)) | ||
39 | #define BP_APBX_CTRL0_SFTRST 31 | ||
40 | #define BM_APBX_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_APBX_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_APBX_CTRL0_CLKGATE 30 | ||
43 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_APBX_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_APBX_CTRL0_RESET_CHANNEL 16 | ||
46 | #define BM_APBX_CTRL0_RESET_CHANNEL 0xff0000 | ||
47 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN 0x1 | ||
48 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT 0x2 | ||
49 | #define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX 0x4 | ||
50 | #define BV_APBX_CTRL0_RESET_CHANNEL__SAIF2 0x4 | ||
51 | #define BV_APBX_CTRL0_RESET_CHANNEL__I2C 0x8 | ||
52 | #define BV_APBX_CTRL0_RESET_CHANNEL__SAIF1 0x10 | ||
53 | #define BV_APBX_CTRL0_RESET_CHANNEL__DRI 0x20 | ||
54 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX 0x40 | ||
55 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX 0x40 | ||
56 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX 0x80 | ||
57 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX 0x80 | ||
58 | #define BF_APBX_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
59 | #define BF_APBX_CTRL0_RESET_CHANNEL_V(v) ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
60 | #define BP_APBX_CTRL0_FREEZE_CHANNEL 0 | ||
61 | #define BM_APBX_CTRL0_FREEZE_CHANNEL 0xff | ||
62 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN 0x1 | ||
63 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT 0x2 | ||
64 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX 0x4 | ||
65 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF2 0x4 | ||
66 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C 0x8 | ||
67 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF1 0x10 | ||
68 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI 0x20 | ||
69 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX 0x40 | ||
70 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX 0x40 | ||
71 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX 0x80 | ||
72 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX 0x80 | ||
73 | #define BF_APBX_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
74 | #define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
75 | |||
76 | /** | ||
77 | * Register: HW_APBX_CTRL1 | ||
78 | * Address: 0x10 | ||
79 | * SCT: yes | ||
80 | */ | ||
81 | #define HW_APBX_CTRL1 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0)) | ||
82 | #define HW_APBX_CTRL1_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4)) | ||
83 | #define HW_APBX_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8)) | ||
84 | #define HW_APBX_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc)) | ||
85 | #define BP_APBX_CTRL1_CH_AHB_ERROR_IRQ 16 | ||
86 | #define BM_APBX_CTRL1_CH_AHB_ERROR_IRQ 0xff0000 | ||
87 | #define BF_APBX_CTRL1_CH_AHB_ERROR_IRQ(v) (((v) << 16) & 0xff0000) | ||
88 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 8 | ||
89 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff00 | ||
90 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00) | ||
91 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
92 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
93 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
94 | |||
95 | /** | ||
96 | * Register: HW_APBX_DEVSEL | ||
97 | * Address: 0x20 | ||
98 | * SCT: no | ||
99 | */ | ||
100 | #define HW_APBX_DEVSEL (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20)) | ||
101 | #define BP_APBX_DEVSEL_CH7 28 | ||
102 | #define BM_APBX_DEVSEL_CH7 0xf0000000 | ||
103 | #define BV_APBX_DEVSEL_CH7__USE_UART 0x0 | ||
104 | #define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 | ||
105 | #define BF_APBX_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
106 | #define BF_APBX_DEVSEL_CH7_V(v) ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000) | ||
107 | #define BP_APBX_DEVSEL_CH6 24 | ||
108 | #define BM_APBX_DEVSEL_CH6 0xf000000 | ||
109 | #define BV_APBX_DEVSEL_CH6__USE_UART 0x0 | ||
110 | #define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 | ||
111 | #define BF_APBX_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
112 | #define BF_APBX_DEVSEL_CH6_V(v) ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000) | ||
113 | #define BP_APBX_DEVSEL_CH5 20 | ||
114 | #define BM_APBX_DEVSEL_CH5 0xf00000 | ||
115 | #define BF_APBX_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
116 | #define BP_APBX_DEVSEL_CH4 16 | ||
117 | #define BM_APBX_DEVSEL_CH4 0xf0000 | ||
118 | #define BF_APBX_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
119 | #define BP_APBX_DEVSEL_CH3 12 | ||
120 | #define BM_APBX_DEVSEL_CH3 0xf000 | ||
121 | #define BF_APBX_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
122 | #define BP_APBX_DEVSEL_CH2 8 | ||
123 | #define BM_APBX_DEVSEL_CH2 0xf00 | ||
124 | #define BV_APBX_DEVSEL_CH2__USE_SPDIF 0x0 | ||
125 | #define BV_APBX_DEVSEL_CH2__USE_SAIF2 0x1 | ||
126 | #define BF_APBX_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
127 | #define BF_APBX_DEVSEL_CH2_V(v) ((BV_APBX_DEVSEL_CH2__##v << 8) & 0xf00) | ||
128 | #define BP_APBX_DEVSEL_CH1 4 | ||
129 | #define BM_APBX_DEVSEL_CH1 0xf0 | ||
130 | #define BF_APBX_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
131 | #define BP_APBX_DEVSEL_CH0 0 | ||
132 | #define BM_APBX_DEVSEL_CH0 0xf | ||
133 | #define BF_APBX_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
134 | |||
135 | /** | ||
136 | * Register: HW_APBX_CHn_CURCMDAR | ||
137 | * Address: 0x40+n*0x70 | ||
138 | * SCT: no | ||
139 | */ | ||
140 | #define HW_APBX_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70)) | ||
141 | #define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 | ||
142 | #define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
143 | #define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
144 | |||
145 | /** | ||
146 | * Register: HW_APBX_CHn_NXTCMDAR | ||
147 | * Address: 0x50+n*0x70 | ||
148 | * SCT: no | ||
149 | */ | ||
150 | #define HW_APBX_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70)) | ||
151 | #define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 | ||
152 | #define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
153 | #define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
154 | |||
155 | /** | ||
156 | * Register: HW_APBX_CHn_CMD | ||
157 | * Address: 0x60+n*0x70 | ||
158 | * SCT: no | ||
159 | */ | ||
160 | #define HW_APBX_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70)) | ||
161 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 | ||
162 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xffff0000 | ||
163 | #define BF_APBX_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
164 | #define BP_APBX_CHn_CMD_CMDWORDS 12 | ||
165 | #define BM_APBX_CHn_CMD_CMDWORDS 0xf000 | ||
166 | #define BF_APBX_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
167 | #define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 | ||
168 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x80 | ||
169 | #define BF_APBX_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
170 | #define BP_APBX_CHn_CMD_SEMAPHORE 6 | ||
171 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x40 | ||
172 | #define BF_APBX_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
173 | #define BP_APBX_CHn_CMD_IRQONCMPLT 3 | ||
174 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x8 | ||
175 | #define BF_APBX_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
176 | #define BP_APBX_CHn_CMD_CHAIN 2 | ||
177 | #define BM_APBX_CHn_CMD_CHAIN 0x4 | ||
178 | #define BF_APBX_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
179 | #define BP_APBX_CHn_CMD_COMMAND 0 | ||
180 | #define BM_APBX_CHn_CMD_COMMAND 0x3 | ||
181 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
182 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
183 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
184 | #define BF_APBX_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
185 | #define BF_APBX_CHn_CMD_COMMAND_V(v) ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
186 | |||
187 | /** | ||
188 | * Register: HW_APBX_CHn_BAR | ||
189 | * Address: 0x70+n*0x70 | ||
190 | * SCT: no | ||
191 | */ | ||
192 | #define HW_APBX_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70)) | ||
193 | #define BP_APBX_CHn_BAR_ADDRESS 0 | ||
194 | #define BM_APBX_CHn_BAR_ADDRESS 0xffffffff | ||
195 | #define BF_APBX_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
196 | |||
197 | /** | ||
198 | * Register: HW_APBX_CHn_SEMA | ||
199 | * Address: 0x80+n*0x70 | ||
200 | * SCT: no | ||
201 | */ | ||
202 | #define HW_APBX_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70)) | ||
203 | #define BP_APBX_CHn_SEMA_PHORE 16 | ||
204 | #define BM_APBX_CHn_SEMA_PHORE 0xff0000 | ||
205 | #define BF_APBX_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
206 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 | ||
207 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0xff | ||
208 | #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
209 | |||
210 | /** | ||
211 | * Register: HW_APBX_CHn_DEBUG1 | ||
212 | * Address: 0x90+n*0x70 | ||
213 | * SCT: no | ||
214 | */ | ||
215 | #define HW_APBX_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70)) | ||
216 | #define BP_APBX_CHn_DEBUG1_REQ 31 | ||
217 | #define BM_APBX_CHn_DEBUG1_REQ 0x80000000 | ||
218 | #define BF_APBX_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
219 | #define BP_APBX_CHn_DEBUG1_BURST 30 | ||
220 | #define BM_APBX_CHn_DEBUG1_BURST 0x40000000 | ||
221 | #define BF_APBX_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
222 | #define BP_APBX_CHn_DEBUG1_KICK 29 | ||
223 | #define BM_APBX_CHn_DEBUG1_KICK 0x20000000 | ||
224 | #define BF_APBX_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
225 | #define BP_APBX_CHn_DEBUG1_END 28 | ||
226 | #define BM_APBX_CHn_DEBUG1_END 0x10000000 | ||
227 | #define BF_APBX_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
228 | #define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
229 | #define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
230 | #define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
231 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
232 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
233 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
234 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
235 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
236 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
237 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
238 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
239 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
240 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
241 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
242 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
243 | #define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 | ||
244 | #define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x1f | ||
245 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
246 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
247 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
248 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
249 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
250 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
251 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
252 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
253 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
254 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
255 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
256 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
257 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
258 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
259 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
260 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
261 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
262 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
263 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
264 | |||
265 | /** | ||
266 | * Register: HW_APBX_CHn_DEBUG2 | ||
267 | * Address: 0xa0+n*0x70 | ||
268 | * SCT: no | ||
269 | */ | ||
270 | #define HW_APBX_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0xa0+(n)*0x70)) | ||
271 | #define BP_APBX_CHn_DEBUG2_APB_BYTES 16 | ||
272 | #define BM_APBX_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
273 | #define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
274 | #define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 | ||
275 | #define BM_APBX_CHn_DEBUG2_AHB_BYTES 0xffff | ||
276 | #define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
277 | |||
278 | /** | ||
279 | * Register: HW_APBX_VERSION | ||
280 | * Address: 0x3f0 | ||
281 | * SCT: no | ||
282 | */ | ||
283 | #define HW_APBX_VERSION (*(volatile unsigned long *)(REGS_APBX_BASE + 0x3f0)) | ||
284 | #define BP_APBX_VERSION_MAJOR 24 | ||
285 | #define BM_APBX_VERSION_MAJOR 0xff000000 | ||
286 | #define BF_APBX_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
287 | #define BP_APBX_VERSION_MINOR 16 | ||
288 | #define BM_APBX_VERSION_MINOR 0xff0000 | ||
289 | #define BF_APBX_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
290 | #define BP_APBX_VERSION_STEP 0 | ||
291 | #define BM_APBX_VERSION_STEP 0xffff | ||
292 | #define BF_APBX_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
293 | |||
294 | #endif /* __HEADERGEN__STMP3700__APBX__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h new file mode 100644 index 0000000000..8bb4cb3e71 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h | |||
@@ -0,0 +1,284 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__AUDIOIN__H__ | ||
24 | #define __HEADERGEN__STMP3700__AUDIOIN__H__ | ||
25 | |||
26 | #define REGS_AUDIOIN_BASE (0x8004c000) | ||
27 | |||
28 | #define REGS_AUDIOIN_VERSION "3.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_AUDIOIN_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_AUDIOIN_CTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0)) | ||
36 | #define HW_AUDIOIN_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4)) | ||
37 | #define HW_AUDIOIN_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8)) | ||
38 | #define HW_AUDIOIN_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc)) | ||
39 | #define BP_AUDIOIN_CTRL_SFTRST 31 | ||
40 | #define BM_AUDIOIN_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_AUDIOIN_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_AUDIOIN_CTRL_CLKGATE 30 | ||
43 | #define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_AUDIOIN_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 | ||
46 | #define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
47 | #define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
48 | #define BP_AUDIOIN_CTRL_LR_SWAP 10 | ||
49 | #define BM_AUDIOIN_CTRL_LR_SWAP 0x400 | ||
50 | #define BF_AUDIOIN_CTRL_LR_SWAP(v) (((v) << 10) & 0x400) | ||
51 | #define BP_AUDIOIN_CTRL_EDGE_SYNC 9 | ||
52 | #define BM_AUDIOIN_CTRL_EDGE_SYNC 0x200 | ||
53 | #define BF_AUDIOIN_CTRL_EDGE_SYNC(v) (((v) << 9) & 0x200) | ||
54 | #define BP_AUDIOIN_CTRL_INVERT_1BIT 8 | ||
55 | #define BM_AUDIOIN_CTRL_INVERT_1BIT 0x100 | ||
56 | #define BF_AUDIOIN_CTRL_INVERT_1BIT(v) (((v) << 8) & 0x100) | ||
57 | #define BP_AUDIOIN_CTRL_OFFSET_ENABLE 7 | ||
58 | #define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x80 | ||
59 | #define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v) (((v) << 7) & 0x80) | ||
60 | #define BP_AUDIOIN_CTRL_HPF_ENABLE 6 | ||
61 | #define BM_AUDIOIN_CTRL_HPF_ENABLE 0x40 | ||
62 | #define BF_AUDIOIN_CTRL_HPF_ENABLE(v) (((v) << 6) & 0x40) | ||
63 | #define BP_AUDIOIN_CTRL_WORD_LENGTH 5 | ||
64 | #define BM_AUDIOIN_CTRL_WORD_LENGTH 0x20 | ||
65 | #define BF_AUDIOIN_CTRL_WORD_LENGTH(v) (((v) << 5) & 0x20) | ||
66 | #define BP_AUDIOIN_CTRL_LOOPBACK 4 | ||
67 | #define BM_AUDIOIN_CTRL_LOOPBACK 0x10 | ||
68 | #define BF_AUDIOIN_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
69 | #define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
70 | #define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
71 | #define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
72 | #define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
73 | #define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
74 | #define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
75 | #define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
76 | #define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
77 | #define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
78 | #define BP_AUDIOIN_CTRL_RUN 0 | ||
79 | #define BM_AUDIOIN_CTRL_RUN 0x1 | ||
80 | #define BF_AUDIOIN_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
81 | |||
82 | /** | ||
83 | * Register: HW_AUDIOIN_STAT | ||
84 | * Address: 0x10 | ||
85 | * SCT: no | ||
86 | */ | ||
87 | #define HW_AUDIOIN_STAT (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10)) | ||
88 | #define BP_AUDIOIN_STAT_ADC_PRESENT 31 | ||
89 | #define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 | ||
90 | #define BF_AUDIOIN_STAT_ADC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_AUDIOIN_ADCSRR | ||
94 | * Address: 0x20 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_AUDIOIN_ADCSRR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0)) | ||
98 | #define HW_AUDIOIN_ADCSRR_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4)) | ||
99 | #define HW_AUDIOIN_ADCSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8)) | ||
100 | #define HW_AUDIOIN_ADCSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc)) | ||
101 | #define BP_AUDIOIN_ADCSRR_OSR 31 | ||
102 | #define BM_AUDIOIN_ADCSRR_OSR 0x80000000 | ||
103 | #define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 | ||
104 | #define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 | ||
105 | #define BF_AUDIOIN_ADCSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
106 | #define BF_AUDIOIN_ADCSRR_OSR_V(v) ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000) | ||
107 | #define BP_AUDIOIN_ADCSRR_BASEMULT 28 | ||
108 | #define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 | ||
109 | #define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 | ||
110 | #define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
111 | #define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 | ||
112 | #define BF_AUDIOIN_ADCSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
113 | #define BF_AUDIOIN_ADCSRR_BASEMULT_V(v) ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000) | ||
114 | #define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 | ||
115 | #define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x7000000 | ||
116 | #define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
117 | #define BP_AUDIOIN_ADCSRR_SRC_INT 16 | ||
118 | #define BM_AUDIOIN_ADCSRR_SRC_INT 0x1f0000 | ||
119 | #define BF_AUDIOIN_ADCSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
120 | #define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 | ||
121 | #define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x1fff | ||
122 | #define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
123 | |||
124 | /** | ||
125 | * Register: HW_AUDIOIN_ADCVOLUME | ||
126 | * Address: 0x30 | ||
127 | * SCT: yes | ||
128 | */ | ||
129 | #define HW_AUDIOIN_ADCVOLUME (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0)) | ||
130 | #define HW_AUDIOIN_ADCVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4)) | ||
131 | #define HW_AUDIOIN_ADCVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8)) | ||
132 | #define HW_AUDIOIN_ADCVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc)) | ||
133 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 28 | ||
134 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
135 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
136 | #define BP_AUDIOIN_ADCVOLUME_EN_ZCD 25 | ||
137 | #define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x2000000 | ||
138 | #define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
139 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 | ||
140 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0xff0000 | ||
141 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
142 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
143 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
144 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
145 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 | ||
146 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0xff | ||
147 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_AUDIOIN_ADCDEBUG | ||
151 | * Address: 0x40 | ||
152 | * SCT: yes | ||
153 | */ | ||
154 | #define HW_AUDIOIN_ADCDEBUG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0)) | ||
155 | #define HW_AUDIOIN_ADCDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4)) | ||
156 | #define HW_AUDIOIN_ADCDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8)) | ||
157 | #define HW_AUDIOIN_ADCDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc)) | ||
158 | #define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 31 | ||
159 | #define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 | ||
160 | #define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v) (((v) << 31) & 0x80000000) | ||
161 | #define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 3 | ||
162 | #define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x8 | ||
163 | #define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8) | ||
164 | #define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 2 | ||
165 | #define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x4 | ||
166 | #define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
167 | #define BP_AUDIOIN_ADCDEBUG_DMA_PREQ 1 | ||
168 | #define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x2 | ||
169 | #define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
170 | #define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS 0 | ||
171 | #define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x1 | ||
172 | #define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_AUDIOIN_ADCVOL | ||
176 | * Address: 0x50 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_AUDIOIN_ADCVOL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0)) | ||
180 | #define HW_AUDIOIN_ADCVOL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4)) | ||
181 | #define HW_AUDIOIN_ADCVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8)) | ||
182 | #define HW_AUDIOIN_ADCVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc)) | ||
183 | #define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 28 | ||
184 | #define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000 | ||
185 | #define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
186 | #define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD 25 | ||
187 | #define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x2000000 | ||
188 | #define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v) (((v) << 25) & 0x2000000) | ||
189 | #define BP_AUDIOIN_ADCVOL_MUTE 24 | ||
190 | #define BM_AUDIOIN_ADCVOL_MUTE 0x1000000 | ||
191 | #define BF_AUDIOIN_ADCVOL_MUTE(v) (((v) << 24) & 0x1000000) | ||
192 | #define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 | ||
193 | #define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x3000 | ||
194 | #define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) (((v) << 12) & 0x3000) | ||
195 | #define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 | ||
196 | #define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0xf00 | ||
197 | #define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) (((v) << 8) & 0xf00) | ||
198 | #define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 | ||
199 | #define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x30 | ||
200 | #define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) (((v) << 4) & 0x30) | ||
201 | #define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 | ||
202 | #define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0xf | ||
203 | #define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) (((v) << 0) & 0xf) | ||
204 | |||
205 | /** | ||
206 | * Register: HW_AUDIOIN_MICLINE | ||
207 | * Address: 0x60 | ||
208 | * SCT: yes | ||
209 | */ | ||
210 | #define HW_AUDIOIN_MICLINE (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0)) | ||
211 | #define HW_AUDIOIN_MICLINE_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4)) | ||
212 | #define HW_AUDIOIN_MICLINE_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8)) | ||
213 | #define HW_AUDIOIN_MICLINE_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc)) | ||
214 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE1 29 | ||
215 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 | ||
216 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v) (((v) << 29) & 0x20000000) | ||
217 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE2 28 | ||
218 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 | ||
219 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v) (((v) << 28) & 0x10000000) | ||
220 | #define BP_AUDIOIN_MICLINE_MIC_SELECT 24 | ||
221 | #define BM_AUDIOIN_MICLINE_MIC_SELECT 0x1000000 | ||
222 | #define BF_AUDIOIN_MICLINE_MIC_SELECT(v) (((v) << 24) & 0x1000000) | ||
223 | #define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 | ||
224 | #define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x300000 | ||
225 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off 0x0 | ||
226 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm 0x1 | ||
227 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm 0x2 | ||
228 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm 0x3 | ||
229 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) (((v) << 20) & 0x300000) | ||
230 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v) ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000) | ||
231 | #define BP_AUDIOIN_MICLINE_MIC_BIAS 16 | ||
232 | #define BM_AUDIOIN_MICLINE_MIC_BIAS 0x70000 | ||
233 | #define BF_AUDIOIN_MICLINE_MIC_BIAS(v) (((v) << 16) & 0x70000) | ||
234 | #define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4 | ||
235 | #define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x30 | ||
236 | #define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) (((v) << 4) & 0x30) | ||
237 | #define BP_AUDIOIN_MICLINE_MIC_GAIN 0 | ||
238 | #define BM_AUDIOIN_MICLINE_MIC_GAIN 0x3 | ||
239 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB 0x0 | ||
240 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB 0x1 | ||
241 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB 0x2 | ||
242 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB 0x3 | ||
243 | #define BF_AUDIOIN_MICLINE_MIC_GAIN(v) (((v) << 0) & 0x3) | ||
244 | #define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v) ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3) | ||
245 | |||
246 | /** | ||
247 | * Register: HW_AUDIOIN_ANACLKCTRL | ||
248 | * Address: 0x70 | ||
249 | * SCT: yes | ||
250 | */ | ||
251 | #define HW_AUDIOIN_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0)) | ||
252 | #define HW_AUDIOIN_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4)) | ||
253 | #define HW_AUDIOIN_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8)) | ||
254 | #define HW_AUDIOIN_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc)) | ||
255 | #define BP_AUDIOIN_ANACLKCTRL_CLKGATE 31 | ||
256 | #define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 | ||
257 | #define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
258 | #define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF 6 | ||
259 | #define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x40 | ||
260 | #define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v) (((v) << 6) & 0x40) | ||
261 | #define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER 5 | ||
262 | #define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x20 | ||
263 | #define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v) (((v) << 5) & 0x20) | ||
264 | #define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 4 | ||
265 | #define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x10 | ||
266 | #define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v) (((v) << 4) & 0x10) | ||
267 | #define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 | ||
268 | #define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x7 | ||
269 | #define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) (((v) << 0) & 0x7) | ||
270 | |||
271 | /** | ||
272 | * Register: HW_AUDIOIN_DATA | ||
273 | * Address: 0x80 | ||
274 | * SCT: no | ||
275 | */ | ||
276 | #define HW_AUDIOIN_DATA (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80)) | ||
277 | #define BP_AUDIOIN_DATA_HIGH 16 | ||
278 | #define BM_AUDIOIN_DATA_HIGH 0xffff0000 | ||
279 | #define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
280 | #define BP_AUDIOIN_DATA_LOW 0 | ||
281 | #define BM_AUDIOIN_DATA_LOW 0xffff | ||
282 | #define BF_AUDIOIN_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
283 | |||
284 | #endif /* __HEADERGEN__STMP3700__AUDIOIN__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h new file mode 100644 index 0000000000..c45ea1e0d0 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h | |||
@@ -0,0 +1,511 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__AUDIOOUT__H__ | ||
24 | #define __HEADERGEN__STMP3700__AUDIOOUT__H__ | ||
25 | |||
26 | #define REGS_AUDIOOUT_BASE (0x80048000) | ||
27 | |||
28 | #define REGS_AUDIOOUT_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_AUDIOOUT_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_AUDIOOUT_CTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0)) | ||
36 | #define HW_AUDIOOUT_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4)) | ||
37 | #define HW_AUDIOOUT_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8)) | ||
38 | #define HW_AUDIOOUT_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc)) | ||
39 | #define BP_AUDIOOUT_CTRL_SFTRST 31 | ||
40 | #define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_AUDIOOUT_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_AUDIOOUT_CTRL_CLKGATE 30 | ||
43 | #define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_AUDIOOUT_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 | ||
46 | #define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
47 | #define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
48 | #define BP_AUDIOOUT_CTRL_LR_SWAP 14 | ||
49 | #define BM_AUDIOOUT_CTRL_LR_SWAP 0x4000 | ||
50 | #define BF_AUDIOOUT_CTRL_LR_SWAP(v) (((v) << 14) & 0x4000) | ||
51 | #define BP_AUDIOOUT_CTRL_EDGE_SYNC 13 | ||
52 | #define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x2000 | ||
53 | #define BF_AUDIOOUT_CTRL_EDGE_SYNC(v) (((v) << 13) & 0x2000) | ||
54 | #define BP_AUDIOOUT_CTRL_INVERT_1BIT 12 | ||
55 | #define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x1000 | ||
56 | #define BF_AUDIOOUT_CTRL_INVERT_1BIT(v) (((v) << 12) & 0x1000) | ||
57 | #define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 | ||
58 | #define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x300 | ||
59 | #define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) (((v) << 8) & 0x300) | ||
60 | #define BP_AUDIOOUT_CTRL_WORD_LENGTH 6 | ||
61 | #define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x40 | ||
62 | #define BF_AUDIOOUT_CTRL_WORD_LENGTH(v) (((v) << 6) & 0x40) | ||
63 | #define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 5 | ||
64 | #define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x20 | ||
65 | #define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v) (((v) << 5) & 0x20) | ||
66 | #define BP_AUDIOOUT_CTRL_LOOPBACK 4 | ||
67 | #define BM_AUDIOOUT_CTRL_LOOPBACK 0x10 | ||
68 | #define BF_AUDIOOUT_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
69 | #define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
70 | #define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
71 | #define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
72 | #define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
73 | #define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
74 | #define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
75 | #define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
76 | #define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
77 | #define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
78 | #define BP_AUDIOOUT_CTRL_RUN 0 | ||
79 | #define BM_AUDIOOUT_CTRL_RUN 0x1 | ||
80 | #define BF_AUDIOOUT_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
81 | |||
82 | /** | ||
83 | * Register: HW_AUDIOOUT_STAT | ||
84 | * Address: 0x10 | ||
85 | * SCT: no | ||
86 | */ | ||
87 | #define HW_AUDIOOUT_STAT (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10)) | ||
88 | #define BP_AUDIOOUT_STAT_DAC_PRESENT 31 | ||
89 | #define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 | ||
90 | #define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_AUDIOOUT_DACSRR | ||
94 | * Address: 0x20 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_AUDIOOUT_DACSRR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0)) | ||
98 | #define HW_AUDIOOUT_DACSRR_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4)) | ||
99 | #define HW_AUDIOOUT_DACSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8)) | ||
100 | #define HW_AUDIOOUT_DACSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc)) | ||
101 | #define BP_AUDIOOUT_DACSRR_OSR 31 | ||
102 | #define BM_AUDIOOUT_DACSRR_OSR 0x80000000 | ||
103 | #define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 | ||
104 | #define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 | ||
105 | #define BF_AUDIOOUT_DACSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
106 | #define BF_AUDIOOUT_DACSRR_OSR_V(v) ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000) | ||
107 | #define BP_AUDIOOUT_DACSRR_BASEMULT 28 | ||
108 | #define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 | ||
109 | #define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 | ||
110 | #define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
111 | #define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 | ||
112 | #define BF_AUDIOOUT_DACSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
113 | #define BF_AUDIOOUT_DACSRR_BASEMULT_V(v) ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000) | ||
114 | #define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 | ||
115 | #define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x7000000 | ||
116 | #define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
117 | #define BP_AUDIOOUT_DACSRR_SRC_INT 16 | ||
118 | #define BM_AUDIOOUT_DACSRR_SRC_INT 0x1f0000 | ||
119 | #define BF_AUDIOOUT_DACSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
120 | #define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 | ||
121 | #define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x1fff | ||
122 | #define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
123 | |||
124 | /** | ||
125 | * Register: HW_AUDIOOUT_DACVOLUME | ||
126 | * Address: 0x30 | ||
127 | * SCT: yes | ||
128 | */ | ||
129 | #define HW_AUDIOOUT_DACVOLUME (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0)) | ||
130 | #define HW_AUDIOOUT_DACVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4)) | ||
131 | #define HW_AUDIOOUT_DACVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8)) | ||
132 | #define HW_AUDIOOUT_DACVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc)) | ||
133 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 28 | ||
134 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
135 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
136 | #define BP_AUDIOOUT_DACVOLUME_EN_ZCD 25 | ||
137 | #define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x2000000 | ||
138 | #define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
139 | #define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT 24 | ||
140 | #define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x1000000 | ||
141 | #define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v) (((v) << 24) & 0x1000000) | ||
142 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 | ||
143 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0xff0000 | ||
144 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
145 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
146 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
147 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
148 | #define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT 8 | ||
149 | #define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x100 | ||
150 | #define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v) (((v) << 8) & 0x100) | ||
151 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 | ||
152 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0xff | ||
153 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
154 | |||
155 | /** | ||
156 | * Register: HW_AUDIOOUT_DACDEBUG | ||
157 | * Address: 0x40 | ||
158 | * SCT: yes | ||
159 | */ | ||
160 | #define HW_AUDIOOUT_DACDEBUG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0)) | ||
161 | #define HW_AUDIOOUT_DACDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4)) | ||
162 | #define HW_AUDIOOUT_DACDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8)) | ||
163 | #define HW_AUDIOOUT_DACDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc)) | ||
164 | #define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 31 | ||
165 | #define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 | ||
166 | #define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v) (((v) << 31) & 0x80000000) | ||
167 | #define BP_AUDIOOUT_DACDEBUG_RAM_SS 8 | ||
168 | #define BM_AUDIOOUT_DACDEBUG_RAM_SS 0xf00 | ||
169 | #define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) (((v) << 8) & 0xf00) | ||
170 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 5 | ||
171 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x20 | ||
172 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v) (((v) << 5) & 0x20) | ||
173 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 4 | ||
174 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x10 | ||
175 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v) (((v) << 4) & 0x10) | ||
176 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 3 | ||
177 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x8 | ||
178 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v) (((v) << 3) & 0x8) | ||
179 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 2 | ||
180 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x4 | ||
181 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
182 | #define BP_AUDIOOUT_DACDEBUG_DMA_PREQ 1 | ||
183 | #define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x2 | ||
184 | #define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
185 | #define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS 0 | ||
186 | #define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x1 | ||
187 | #define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
188 | |||
189 | /** | ||
190 | * Register: HW_AUDIOOUT_HPVOL | ||
191 | * Address: 0x50 | ||
192 | * SCT: yes | ||
193 | */ | ||
194 | #define HW_AUDIOOUT_HPVOL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0)) | ||
195 | #define HW_AUDIOOUT_HPVOL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4)) | ||
196 | #define HW_AUDIOOUT_HPVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8)) | ||
197 | #define HW_AUDIOOUT_HPVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc)) | ||
198 | #define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 28 | ||
199 | #define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000 | ||
200 | #define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
201 | #define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD 25 | ||
202 | #define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x2000000 | ||
203 | #define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v) (((v) << 25) & 0x2000000) | ||
204 | #define BP_AUDIOOUT_HPVOL_MUTE 24 | ||
205 | #define BM_AUDIOOUT_HPVOL_MUTE 0x1000000 | ||
206 | #define BF_AUDIOOUT_HPVOL_MUTE(v) (((v) << 24) & 0x1000000) | ||
207 | #define BP_AUDIOOUT_HPVOL_SELECT 16 | ||
208 | #define BM_AUDIOOUT_HPVOL_SELECT 0x10000 | ||
209 | #define BF_AUDIOOUT_HPVOL_SELECT(v) (((v) << 16) & 0x10000) | ||
210 | #define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 | ||
211 | #define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x7f00 | ||
212 | #define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) (((v) << 8) & 0x7f00) | ||
213 | #define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 | ||
214 | #define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x7f | ||
215 | #define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) (((v) << 0) & 0x7f) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_AUDIOOUT_RESERVED | ||
219 | * Address: 0x60 | ||
220 | * SCT: no | ||
221 | */ | ||
222 | #define HW_AUDIOOUT_RESERVED (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60)) | ||
223 | |||
224 | /** | ||
225 | * Register: HW_AUDIOOUT_PWRDN | ||
226 | * Address: 0x70 | ||
227 | * SCT: yes | ||
228 | */ | ||
229 | #define HW_AUDIOOUT_PWRDN (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0)) | ||
230 | #define HW_AUDIOOUT_PWRDN_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4)) | ||
231 | #define HW_AUDIOOUT_PWRDN_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8)) | ||
232 | #define HW_AUDIOOUT_PWRDN_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc)) | ||
233 | #define BP_AUDIOOUT_PWRDN_LINEOUT 24 | ||
234 | #define BM_AUDIOOUT_PWRDN_LINEOUT 0x1000000 | ||
235 | #define BF_AUDIOOUT_PWRDN_LINEOUT(v) (((v) << 24) & 0x1000000) | ||
236 | #define BP_AUDIOOUT_PWRDN_SELFBIAS 20 | ||
237 | #define BM_AUDIOOUT_PWRDN_SELFBIAS 0x100000 | ||
238 | #define BF_AUDIOOUT_PWRDN_SELFBIAS(v) (((v) << 20) & 0x100000) | ||
239 | #define BP_AUDIOOUT_PWRDN_RIGHT_ADC 16 | ||
240 | #define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x10000 | ||
241 | #define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v) (((v) << 16) & 0x10000) | ||
242 | #define BP_AUDIOOUT_PWRDN_DAC 12 | ||
243 | #define BM_AUDIOOUT_PWRDN_DAC 0x1000 | ||
244 | #define BF_AUDIOOUT_PWRDN_DAC(v) (((v) << 12) & 0x1000) | ||
245 | #define BP_AUDIOOUT_PWRDN_ADC 8 | ||
246 | #define BM_AUDIOOUT_PWRDN_ADC 0x100 | ||
247 | #define BF_AUDIOOUT_PWRDN_ADC(v) (((v) << 8) & 0x100) | ||
248 | #define BP_AUDIOOUT_PWRDN_CAPLESS 4 | ||
249 | #define BM_AUDIOOUT_PWRDN_CAPLESS 0x10 | ||
250 | #define BF_AUDIOOUT_PWRDN_CAPLESS(v) (((v) << 4) & 0x10) | ||
251 | #define BP_AUDIOOUT_PWRDN_HEADPHONE 0 | ||
252 | #define BM_AUDIOOUT_PWRDN_HEADPHONE 0x1 | ||
253 | #define BF_AUDIOOUT_PWRDN_HEADPHONE(v) (((v) << 0) & 0x1) | ||
254 | |||
255 | /** | ||
256 | * Register: HW_AUDIOOUT_REFCTRL | ||
257 | * Address: 0x80 | ||
258 | * SCT: yes | ||
259 | */ | ||
260 | #define HW_AUDIOOUT_REFCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0)) | ||
261 | #define HW_AUDIOOUT_REFCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4)) | ||
262 | #define HW_AUDIOOUT_REFCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8)) | ||
263 | #define HW_AUDIOOUT_REFCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc)) | ||
264 | #define BP_AUDIOOUT_REFCTRL_FASTSETTLING 26 | ||
265 | #define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x4000000 | ||
266 | #define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v) (((v) << 26) & 0x4000000) | ||
267 | #define BP_AUDIOOUT_REFCTRL_RAISE_REF 25 | ||
268 | #define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x2000000 | ||
269 | #define BF_AUDIOOUT_REFCTRL_RAISE_REF(v) (((v) << 25) & 0x2000000) | ||
270 | #define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 24 | ||
271 | #define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x1000000 | ||
272 | #define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v) (((v) << 24) & 0x1000000) | ||
273 | #define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 | ||
274 | #define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x700000 | ||
275 | #define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) (((v) << 20) & 0x700000) | ||
276 | #define BP_AUDIOOUT_REFCTRL_LOW_PWR 19 | ||
277 | #define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x80000 | ||
278 | #define BF_AUDIOOUT_REFCTRL_LOW_PWR(v) (((v) << 19) & 0x80000) | ||
279 | #define BP_AUDIOOUT_REFCTRL_LW_REF 18 | ||
280 | #define BM_AUDIOOUT_REFCTRL_LW_REF 0x40000 | ||
281 | #define BF_AUDIOOUT_REFCTRL_LW_REF(v) (((v) << 18) & 0x40000) | ||
282 | #define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 | ||
283 | #define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x30000 | ||
284 | #define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) (((v) << 16) & 0x30000) | ||
285 | #define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 14 | ||
286 | #define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x4000 | ||
287 | #define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v) (((v) << 14) & 0x4000) | ||
288 | #define BP_AUDIOOUT_REFCTRL_ADJ_ADC 13 | ||
289 | #define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x2000 | ||
290 | #define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v) (((v) << 13) & 0x2000) | ||
291 | #define BP_AUDIOOUT_REFCTRL_ADJ_VAG 12 | ||
292 | #define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x1000 | ||
293 | #define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v) (((v) << 12) & 0x1000) | ||
294 | #define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 | ||
295 | #define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0xf00 | ||
296 | #define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) (((v) << 8) & 0xf00) | ||
297 | #define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 | ||
298 | #define BM_AUDIOOUT_REFCTRL_VAG_VAL 0xf0 | ||
299 | #define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) (((v) << 4) & 0xf0) | ||
300 | #define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 | ||
301 | #define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x7 | ||
302 | #define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) (((v) << 0) & 0x7) | ||
303 | |||
304 | /** | ||
305 | * Register: HW_AUDIOOUT_ANACTRL | ||
306 | * Address: 0x90 | ||
307 | * SCT: yes | ||
308 | */ | ||
309 | #define HW_AUDIOOUT_ANACTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0)) | ||
310 | #define HW_AUDIOOUT_ANACTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4)) | ||
311 | #define HW_AUDIOOUT_ANACTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8)) | ||
312 | #define HW_AUDIOOUT_ANACTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc)) | ||
313 | #define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS 28 | ||
314 | #define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 | ||
315 | #define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v) (((v) << 28) & 0x10000000) | ||
316 | #define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS 24 | ||
317 | #define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x1000000 | ||
318 | #define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v) (((v) << 24) & 0x1000000) | ||
319 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 | ||
320 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x300000 | ||
321 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) (((v) << 20) & 0x300000) | ||
322 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 | ||
323 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x60000 | ||
324 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) (((v) << 17) & 0x60000) | ||
325 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 | ||
326 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x7000 | ||
327 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) (((v) << 12) & 0x7000) | ||
328 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 | ||
329 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x700 | ||
330 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) (((v) << 8) & 0x700) | ||
331 | #define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND 5 | ||
332 | #define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x20 | ||
333 | #define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v) (((v) << 5) & 0x20) | ||
334 | #define BP_AUDIOOUT_ANACTRL_HP_CLASSAB 4 | ||
335 | #define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x10 | ||
336 | #define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v) (((v) << 4) & 0x10) | ||
337 | |||
338 | /** | ||
339 | * Register: HW_AUDIOOUT_TEST | ||
340 | * Address: 0xa0 | ||
341 | * SCT: yes | ||
342 | */ | ||
343 | #define HW_AUDIOOUT_TEST (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0)) | ||
344 | #define HW_AUDIOOUT_TEST_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4)) | ||
345 | #define HW_AUDIOOUT_TEST_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8)) | ||
346 | #define HW_AUDIOOUT_TEST_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc)) | ||
347 | #define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 | ||
348 | #define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 | ||
349 | #define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) (((v) << 28) & 0x70000000) | ||
350 | #define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP 26 | ||
351 | #define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x4000000 | ||
352 | #define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v) (((v) << 26) & 0x4000000) | ||
353 | #define BP_AUDIOOUT_TEST_TM_LINEOUT 25 | ||
354 | #define BM_AUDIOOUT_TEST_TM_LINEOUT 0x2000000 | ||
355 | #define BF_AUDIOOUT_TEST_TM_LINEOUT(v) (((v) << 25) & 0x2000000) | ||
356 | #define BP_AUDIOOUT_TEST_TM_HPCOMMON 24 | ||
357 | #define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x1000000 | ||
358 | #define BF_AUDIOOUT_TEST_TM_HPCOMMON(v) (((v) << 24) & 0x1000000) | ||
359 | #define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 | ||
360 | #define BM_AUDIOOUT_TEST_HP_I1_ADJ 0xc00000 | ||
361 | #define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) (((v) << 22) & 0xc00000) | ||
362 | #define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 | ||
363 | #define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x300000 | ||
364 | #define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) (((v) << 20) & 0x300000) | ||
365 | #define BP_AUDIOOUT_TEST_VAG_CLASSA 13 | ||
366 | #define BM_AUDIOOUT_TEST_VAG_CLASSA 0x2000 | ||
367 | #define BF_AUDIOOUT_TEST_VAG_CLASSA(v) (((v) << 13) & 0x2000) | ||
368 | #define BP_AUDIOOUT_TEST_VAG_DOUBLE_I 12 | ||
369 | #define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x1000 | ||
370 | #define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v) (((v) << 12) & 0x1000) | ||
371 | #define BP_AUDIOOUT_TEST_DAC_CLASSA 2 | ||
372 | #define BM_AUDIOOUT_TEST_DAC_CLASSA 0x4 | ||
373 | #define BF_AUDIOOUT_TEST_DAC_CLASSA(v) (((v) << 2) & 0x4) | ||
374 | #define BP_AUDIOOUT_TEST_DAC_DOUBLE_I 1 | ||
375 | #define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x2 | ||
376 | #define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v) (((v) << 1) & 0x2) | ||
377 | #define BP_AUDIOOUT_TEST_DAC_DIS_RTZ 0 | ||
378 | #define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x1 | ||
379 | #define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v) (((v) << 0) & 0x1) | ||
380 | |||
381 | /** | ||
382 | * Register: HW_AUDIOOUT_BISTCTRL | ||
383 | * Address: 0xb0 | ||
384 | * SCT: yes | ||
385 | */ | ||
386 | #define HW_AUDIOOUT_BISTCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0)) | ||
387 | #define HW_AUDIOOUT_BISTCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4)) | ||
388 | #define HW_AUDIOOUT_BISTCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8)) | ||
389 | #define HW_AUDIOOUT_BISTCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc)) | ||
390 | #define BP_AUDIOOUT_BISTCTRL_FAIL 3 | ||
391 | #define BM_AUDIOOUT_BISTCTRL_FAIL 0x8 | ||
392 | #define BF_AUDIOOUT_BISTCTRL_FAIL(v) (((v) << 3) & 0x8) | ||
393 | #define BP_AUDIOOUT_BISTCTRL_PASS 2 | ||
394 | #define BM_AUDIOOUT_BISTCTRL_PASS 0x4 | ||
395 | #define BF_AUDIOOUT_BISTCTRL_PASS(v) (((v) << 2) & 0x4) | ||
396 | #define BP_AUDIOOUT_BISTCTRL_DONE 1 | ||
397 | #define BM_AUDIOOUT_BISTCTRL_DONE 0x2 | ||
398 | #define BF_AUDIOOUT_BISTCTRL_DONE(v) (((v) << 1) & 0x2) | ||
399 | #define BP_AUDIOOUT_BISTCTRL_START 0 | ||
400 | #define BM_AUDIOOUT_BISTCTRL_START 0x1 | ||
401 | #define BF_AUDIOOUT_BISTCTRL_START(v) (((v) << 0) & 0x1) | ||
402 | |||
403 | /** | ||
404 | * Register: HW_AUDIOOUT_BISTSTAT0 | ||
405 | * Address: 0xc0 | ||
406 | * SCT: no | ||
407 | */ | ||
408 | #define HW_AUDIOOUT_BISTSTAT0 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0)) | ||
409 | #define BP_AUDIOOUT_BISTSTAT0_DATA 0 | ||
410 | #define BM_AUDIOOUT_BISTSTAT0_DATA 0xffffff | ||
411 | #define BF_AUDIOOUT_BISTSTAT0_DATA(v) (((v) << 0) & 0xffffff) | ||
412 | |||
413 | /** | ||
414 | * Register: HW_AUDIOOUT_BISTSTAT1 | ||
415 | * Address: 0xd0 | ||
416 | * SCT: no | ||
417 | */ | ||
418 | #define HW_AUDIOOUT_BISTSTAT1 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0)) | ||
419 | #define BP_AUDIOOUT_BISTSTAT1_STATE 24 | ||
420 | #define BM_AUDIOOUT_BISTSTAT1_STATE 0x1f000000 | ||
421 | #define BF_AUDIOOUT_BISTSTAT1_STATE(v) (((v) << 24) & 0x1f000000) | ||
422 | #define BP_AUDIOOUT_BISTSTAT1_ADDR 0 | ||
423 | #define BM_AUDIOOUT_BISTSTAT1_ADDR 0xff | ||
424 | #define BF_AUDIOOUT_BISTSTAT1_ADDR(v) (((v) << 0) & 0xff) | ||
425 | |||
426 | /** | ||
427 | * Register: HW_AUDIOOUT_ANACLKCTRL | ||
428 | * Address: 0xe0 | ||
429 | * SCT: yes | ||
430 | */ | ||
431 | #define HW_AUDIOOUT_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0)) | ||
432 | #define HW_AUDIOOUT_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4)) | ||
433 | #define HW_AUDIOOUT_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8)) | ||
434 | #define HW_AUDIOOUT_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc)) | ||
435 | #define BP_AUDIOOUT_ANACLKCTRL_CLKGATE 31 | ||
436 | #define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 | ||
437 | #define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
438 | #define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 4 | ||
439 | #define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x10 | ||
440 | #define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10) | ||
441 | #define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 | ||
442 | #define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x7 | ||
443 | #define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) (((v) << 0) & 0x7) | ||
444 | |||
445 | /** | ||
446 | * Register: HW_AUDIOOUT_DATA | ||
447 | * Address: 0xf0 | ||
448 | * SCT: yes | ||
449 | */ | ||
450 | #define HW_AUDIOOUT_DATA (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0)) | ||
451 | #define HW_AUDIOOUT_DATA_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4)) | ||
452 | #define HW_AUDIOOUT_DATA_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8)) | ||
453 | #define HW_AUDIOOUT_DATA_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc)) | ||
454 | #define BP_AUDIOOUT_DATA_HIGH 16 | ||
455 | #define BM_AUDIOOUT_DATA_HIGH 0xffff0000 | ||
456 | #define BF_AUDIOOUT_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
457 | #define BP_AUDIOOUT_DATA_LOW 0 | ||
458 | #define BM_AUDIOOUT_DATA_LOW 0xffff | ||
459 | #define BF_AUDIOOUT_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
460 | |||
461 | /** | ||
462 | * Register: HW_AUDIOOUT_LINEOUTCTRL | ||
463 | * Address: 0x100 | ||
464 | * SCT: yes | ||
465 | */ | ||
466 | #define HW_AUDIOOUT_LINEOUTCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x0)) | ||
467 | #define HW_AUDIOOUT_LINEOUTCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x4)) | ||
468 | #define HW_AUDIOOUT_LINEOUTCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x8)) | ||
469 | #define HW_AUDIOOUT_LINEOUTCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0xc)) | ||
470 | #define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING 28 | ||
471 | #define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING 0x10000000 | ||
472 | #define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
473 | #define BP_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD 25 | ||
474 | #define BM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD 0x2000000 | ||
475 | #define BF_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD(v) (((v) << 25) & 0x2000000) | ||
476 | #define BP_AUDIOOUT_LINEOUTCTRL_MUTE 24 | ||
477 | #define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x1000000 | ||
478 | #define BF_AUDIOOUT_LINEOUTCTRL_MUTE(v) (((v) << 24) & 0x1000000) | ||
479 | #define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20 | ||
480 | #define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0xf00000 | ||
481 | #define BF_AUDIOOUT_LINEOUTCTRL_VAG_CTRL(v) (((v) << 20) & 0xf00000) | ||
482 | #define BP_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT 16 | ||
483 | #define BM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT 0xf0000 | ||
484 | #define BF_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT(v) (((v) << 16) & 0xf0000) | ||
485 | #define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 13 | ||
486 | #define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0xe000 | ||
487 | #define BF_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP(v) (((v) << 13) & 0xe000) | ||
488 | #define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT 8 | ||
489 | #define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT 0x1f00 | ||
490 | #define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT(v) (((v) << 8) & 0x1f00) | ||
491 | #define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT 0 | ||
492 | #define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT 0x1f | ||
493 | #define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT(v) (((v) << 0) & 0x1f) | ||
494 | |||
495 | /** | ||
496 | * Register: HW_AUDIOOUT_VERSION | ||
497 | * Address: 0x200 | ||
498 | * SCT: no | ||
499 | */ | ||
500 | #define HW_AUDIOOUT_VERSION (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x200)) | ||
501 | #define BP_AUDIOOUT_VERSION_MAJOR 24 | ||
502 | #define BM_AUDIOOUT_VERSION_MAJOR 0xff000000 | ||
503 | #define BF_AUDIOOUT_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
504 | #define BP_AUDIOOUT_VERSION_MINOR 16 | ||
505 | #define BM_AUDIOOUT_VERSION_MINOR 0xff0000 | ||
506 | #define BF_AUDIOOUT_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
507 | #define BP_AUDIOOUT_VERSION_STEP 0 | ||
508 | #define BM_AUDIOOUT_VERSION_STEP 0xffff | ||
509 | #define BF_AUDIOOUT_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
510 | |||
511 | #endif /* __HEADERGEN__STMP3700__AUDIOOUT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h new file mode 100644 index 0000000000..0449161d11 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h | |||
@@ -0,0 +1,459 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__CLKCTRL__H__ | ||
24 | #define __HEADERGEN__STMP3700__CLKCTRL__H__ | ||
25 | |||
26 | #define REGS_CLKCTRL_BASE (0x80040000) | ||
27 | |||
28 | #define REGS_CLKCTRL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_CLKCTRL_PLLCTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_CLKCTRL_PLLCTRL0_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_CLKCTRL_PLLCTRL0_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_CLKCTRL_PLLCTRL0_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 | ||
40 | #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 | ||
41 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 | ||
42 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 | ||
43 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 | ||
44 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 | ||
45 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) (((v) << 28) & 0x30000000) | ||
46 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000) | ||
47 | #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 | ||
48 | #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x3000000 | ||
49 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 | ||
50 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 | ||
51 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 | ||
52 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 | ||
53 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) (((v) << 24) & 0x3000000) | ||
54 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000) | ||
55 | #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 | ||
56 | #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x300000 | ||
57 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 | ||
58 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 | ||
59 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 | ||
60 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 | ||
61 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) (((v) << 20) & 0x300000) | ||
62 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000) | ||
63 | #define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 | ||
64 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 | ||
65 | #define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) << 18) & 0x40000) | ||
66 | #define BP_CLKCTRL_PLLCTRL0_POWER 16 | ||
67 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 | ||
68 | #define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) << 16) & 0x10000) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_CLKCTRL_PLLCTRL1 | ||
72 | * Address: 0x10 | ||
73 | * SCT: no | ||
74 | */ | ||
75 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10)) | ||
76 | #define BP_CLKCTRL_PLLCTRL1_LOCK 31 | ||
77 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
78 | #define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) << 31) & 0x80000000) | ||
79 | #define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 | ||
80 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
81 | #define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) << 30) & 0x40000000) | ||
82 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
83 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff | ||
84 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) << 0) & 0xffff) | ||
85 | |||
86 | /** | ||
87 | * Register: HW_CLKCTRL_CPU | ||
88 | * Address: 0x20 | ||
89 | * SCT: yes | ||
90 | */ | ||
91 | #define HW_CLKCTRL_CPU (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0)) | ||
92 | #define HW_CLKCTRL_CPU_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4)) | ||
93 | #define HW_CLKCTRL_CPU_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8)) | ||
94 | #define HW_CLKCTRL_CPU_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc)) | ||
95 | #define BP_CLKCTRL_CPU_BUSY_REF_XTAL 29 | ||
96 | #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 | ||
97 | #define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
98 | #define BP_CLKCTRL_CPU_BUSY_REF_CPU 28 | ||
99 | #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 | ||
100 | #define BF_CLKCTRL_CPU_BUSY_REF_CPU(v) (((v) << 28) & 0x10000000) | ||
101 | #define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 26 | ||
102 | #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x4000000 | ||
103 | #define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) (((v) << 26) & 0x4000000) | ||
104 | #define BP_CLKCTRL_CPU_DIV_XTAL 16 | ||
105 | #define BM_CLKCTRL_CPU_DIV_XTAL 0x3ff0000 | ||
106 | #define BF_CLKCTRL_CPU_DIV_XTAL(v) (((v) << 16) & 0x3ff0000) | ||
107 | #define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 | ||
108 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 | ||
109 | #define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) << 12) & 0x1000) | ||
110 | #define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN 10 | ||
111 | #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x400 | ||
112 | #define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) (((v) << 10) & 0x400) | ||
113 | #define BP_CLKCTRL_CPU_DIV_CPU 0 | ||
114 | #define BM_CLKCTRL_CPU_DIV_CPU 0x3ff | ||
115 | #define BF_CLKCTRL_CPU_DIV_CPU(v) (((v) << 0) & 0x3ff) | ||
116 | |||
117 | /** | ||
118 | * Register: HW_CLKCTRL_HBUS | ||
119 | * Address: 0x30 | ||
120 | * SCT: yes | ||
121 | */ | ||
122 | #define HW_CLKCTRL_HBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0)) | ||
123 | #define HW_CLKCTRL_HBUS_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4)) | ||
124 | #define HW_CLKCTRL_HBUS_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8)) | ||
125 | #define HW_CLKCTRL_HBUS_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc)) | ||
126 | #define BP_CLKCTRL_HBUS_BUSY 29 | ||
127 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
128 | #define BF_CLKCTRL_HBUS_BUSY(v) (((v) << 29) & 0x20000000) | ||
129 | #define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 26 | ||
130 | #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x4000000 | ||
131 | #define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) (((v) << 26) & 0x4000000) | ||
132 | #define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 25 | ||
133 | #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x2000000 | ||
134 | #define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) (((v) << 25) & 0x2000000) | ||
135 | #define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 24 | ||
136 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x1000000 | ||
137 | #define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) (((v) << 24) & 0x1000000) | ||
138 | #define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 23 | ||
139 | #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x800000 | ||
140 | #define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) (((v) << 23) & 0x800000) | ||
141 | #define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 22 | ||
142 | #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x400000 | ||
143 | #define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) (((v) << 22) & 0x400000) | ||
144 | #define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 21 | ||
145 | #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x200000 | ||
146 | #define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) (((v) << 21) & 0x200000) | ||
147 | #define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 | ||
148 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 | ||
149 | #define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) << 20) & 0x100000) | ||
150 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
151 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x70000 | ||
152 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
153 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
154 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
155 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
156 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 | ||
157 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 | ||
158 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) << 16) & 0x70000) | ||
159 | #define BF_CLKCTRL_HBUS_SLOW_DIV_V(v) ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000) | ||
160 | #define BP_CLKCTRL_HBUS_DIV_FRAC_EN 5 | ||
161 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x20 | ||
162 | #define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v) (((v) << 5) & 0x20) | ||
163 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
164 | #define BM_CLKCTRL_HBUS_DIV 0x1f | ||
165 | #define BF_CLKCTRL_HBUS_DIV(v) (((v) << 0) & 0x1f) | ||
166 | |||
167 | /** | ||
168 | * Register: HW_CLKCTRL_XBUS | ||
169 | * Address: 0x40 | ||
170 | * SCT: no | ||
171 | */ | ||
172 | #define HW_CLKCTRL_XBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40)) | ||
173 | #define BP_CLKCTRL_XBUS_BUSY 31 | ||
174 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
175 | #define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000) | ||
176 | #define BP_CLKCTRL_XBUS_DIV_FRAC_EN 10 | ||
177 | #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x400 | ||
178 | #define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
179 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
180 | #define BM_CLKCTRL_XBUS_DIV 0x3ff | ||
181 | #define BF_CLKCTRL_XBUS_DIV(v) (((v) << 0) & 0x3ff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_CLKCTRL_XTAL | ||
185 | * Address: 0x50 | ||
186 | * SCT: yes | ||
187 | */ | ||
188 | #define HW_CLKCTRL_XTAL (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0)) | ||
189 | #define HW_CLKCTRL_XTAL_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4)) | ||
190 | #define HW_CLKCTRL_XTAL_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8)) | ||
191 | #define HW_CLKCTRL_XTAL_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc)) | ||
192 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
193 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
194 | #define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) << 31) & 0x80000000) | ||
195 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
196 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
197 | #define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) << 30) & 0x40000000) | ||
198 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
199 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
200 | #define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) << 29) & 0x20000000) | ||
201 | #define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 | ||
202 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
203 | #define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) << 28) & 0x10000000) | ||
204 | #define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 | ||
205 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 | ||
206 | #define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) << 27) & 0x8000000) | ||
207 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
208 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 | ||
209 | #define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) << 26) & 0x4000000) | ||
210 | #define BP_CLKCTRL_XTAL_DIV_UART 0 | ||
211 | #define BM_CLKCTRL_XTAL_DIV_UART 0x3 | ||
212 | #define BF_CLKCTRL_XTAL_DIV_UART(v) (((v) << 0) & 0x3) | ||
213 | |||
214 | /** | ||
215 | * Register: HW_CLKCTRL_PIX | ||
216 | * Address: 0x60 | ||
217 | * SCT: no | ||
218 | */ | ||
219 | #define HW_CLKCTRL_PIX (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60)) | ||
220 | #define BP_CLKCTRL_PIX_CLKGATE 31 | ||
221 | #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 | ||
222 | #define BF_CLKCTRL_PIX_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
223 | #define BP_CLKCTRL_PIX_BUSY 29 | ||
224 | #define BM_CLKCTRL_PIX_BUSY 0x20000000 | ||
225 | #define BF_CLKCTRL_PIX_BUSY(v) (((v) << 29) & 0x20000000) | ||
226 | #define BP_CLKCTRL_PIX_DIV_FRAC_EN 15 | ||
227 | #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x8000 | ||
228 | #define BF_CLKCTRL_PIX_DIV_FRAC_EN(v) (((v) << 15) & 0x8000) | ||
229 | #define BP_CLKCTRL_PIX_DIV 0 | ||
230 | #define BM_CLKCTRL_PIX_DIV 0x7fff | ||
231 | #define BF_CLKCTRL_PIX_DIV(v) (((v) << 0) & 0x7fff) | ||
232 | |||
233 | /** | ||
234 | * Register: HW_CLKCTRL_SSP | ||
235 | * Address: 0x70 | ||
236 | * SCT: no | ||
237 | */ | ||
238 | #define HW_CLKCTRL_SSP (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70)) | ||
239 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
240 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
241 | #define BF_CLKCTRL_SSP_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
242 | #define BP_CLKCTRL_SSP_BUSY 29 | ||
243 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
244 | #define BF_CLKCTRL_SSP_BUSY(v) (((v) << 29) & 0x20000000) | ||
245 | #define BP_CLKCTRL_SSP_DIV_FRAC_EN 9 | ||
246 | #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x200 | ||
247 | #define BF_CLKCTRL_SSP_DIV_FRAC_EN(v) (((v) << 9) & 0x200) | ||
248 | #define BP_CLKCTRL_SSP_DIV 0 | ||
249 | #define BM_CLKCTRL_SSP_DIV 0x1ff | ||
250 | #define BF_CLKCTRL_SSP_DIV(v) (((v) << 0) & 0x1ff) | ||
251 | |||
252 | /** | ||
253 | * Register: HW_CLKCTRL_GPMI | ||
254 | * Address: 0x80 | ||
255 | * SCT: no | ||
256 | */ | ||
257 | #define HW_CLKCTRL_GPMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80)) | ||
258 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
259 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
260 | #define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
261 | #define BP_CLKCTRL_GPMI_BUSY 29 | ||
262 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
263 | #define BF_CLKCTRL_GPMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
264 | #define BP_CLKCTRL_GPMI_DIV_FRAC_EN 10 | ||
265 | #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x400 | ||
266 | #define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
267 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
268 | #define BM_CLKCTRL_GPMI_DIV 0x3ff | ||
269 | #define BF_CLKCTRL_GPMI_DIV(v) (((v) << 0) & 0x3ff) | ||
270 | |||
271 | /** | ||
272 | * Register: HW_CLKCTRL_SPDIF | ||
273 | * Address: 0x90 | ||
274 | * SCT: no | ||
275 | */ | ||
276 | #define HW_CLKCTRL_SPDIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90)) | ||
277 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
278 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
279 | #define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
280 | |||
281 | /** | ||
282 | * Register: HW_CLKCTRL_EMI | ||
283 | * Address: 0xa0 | ||
284 | * SCT: no | ||
285 | */ | ||
286 | #define HW_CLKCTRL_EMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0)) | ||
287 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
288 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
289 | #define BF_CLKCTRL_EMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
290 | #define BP_CLKCTRL_EMI_BUSY_REF_XTAL 29 | ||
291 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 | ||
292 | #define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
293 | #define BP_CLKCTRL_EMI_BUSY_REF_EMI 28 | ||
294 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 | ||
295 | #define BF_CLKCTRL_EMI_BUSY_REF_EMI(v) (((v) << 28) & 0x10000000) | ||
296 | #define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC 17 | ||
297 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x20000 | ||
298 | #define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) (((v) << 17) & 0x20000) | ||
299 | #define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE 16 | ||
300 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x10000 | ||
301 | #define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000) | ||
302 | #define BP_CLKCTRL_EMI_DIV_XTAL 8 | ||
303 | #define BM_CLKCTRL_EMI_DIV_XTAL 0xf00 | ||
304 | #define BF_CLKCTRL_EMI_DIV_XTAL(v) (((v) << 8) & 0xf00) | ||
305 | #define BP_CLKCTRL_EMI_DIV_EMI 0 | ||
306 | #define BM_CLKCTRL_EMI_DIV_EMI 0x3f | ||
307 | #define BF_CLKCTRL_EMI_DIV_EMI(v) (((v) << 0) & 0x3f) | ||
308 | |||
309 | /** | ||
310 | * Register: HW_CLKCTRL_IR | ||
311 | * Address: 0xb0 | ||
312 | * SCT: no | ||
313 | */ | ||
314 | #define HW_CLKCTRL_IR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0)) | ||
315 | #define BP_CLKCTRL_IR_CLKGATE 31 | ||
316 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
317 | #define BF_CLKCTRL_IR_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
318 | #define BP_CLKCTRL_IR_AUTO_DIV 29 | ||
319 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
320 | #define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) << 29) & 0x20000000) | ||
321 | #define BP_CLKCTRL_IR_IR_BUSY 28 | ||
322 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
323 | #define BF_CLKCTRL_IR_IR_BUSY(v) (((v) << 28) & 0x10000000) | ||
324 | #define BP_CLKCTRL_IR_IROV_BUSY 27 | ||
325 | #define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 | ||
326 | #define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) << 27) & 0x8000000) | ||
327 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
328 | #define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 | ||
329 | #define BF_CLKCTRL_IR_IROV_DIV(v) (((v) << 16) & 0x1ff0000) | ||
330 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
331 | #define BM_CLKCTRL_IR_IR_DIV 0x3ff | ||
332 | #define BF_CLKCTRL_IR_IR_DIV(v) (((v) << 0) & 0x3ff) | ||
333 | |||
334 | /** | ||
335 | * Register: HW_CLKCTRL_SAIF | ||
336 | * Address: 0xc0 | ||
337 | * SCT: no | ||
338 | */ | ||
339 | #define HW_CLKCTRL_SAIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0)) | ||
340 | #define BP_CLKCTRL_SAIF_CLKGATE 31 | ||
341 | #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 | ||
342 | #define BF_CLKCTRL_SAIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
343 | #define BP_CLKCTRL_SAIF_BUSY 29 | ||
344 | #define BM_CLKCTRL_SAIF_BUSY 0x20000000 | ||
345 | #define BF_CLKCTRL_SAIF_BUSY(v) (((v) << 29) & 0x20000000) | ||
346 | #define BP_CLKCTRL_SAIF_DIV_FRAC_EN 16 | ||
347 | #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x10000 | ||
348 | #define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v) (((v) << 16) & 0x10000) | ||
349 | #define BP_CLKCTRL_SAIF_DIV 0 | ||
350 | #define BM_CLKCTRL_SAIF_DIV 0xffff | ||
351 | #define BF_CLKCTRL_SAIF_DIV(v) (((v) << 0) & 0xffff) | ||
352 | |||
353 | /** | ||
354 | * Register: HW_CLKCTRL_FRAC | ||
355 | * Address: 0xd0 | ||
356 | * SCT: yes | ||
357 | */ | ||
358 | #define HW_CLKCTRL_FRAC (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x0)) | ||
359 | #define HW_CLKCTRL_FRAC_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x4)) | ||
360 | #define HW_CLKCTRL_FRAC_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x8)) | ||
361 | #define HW_CLKCTRL_FRAC_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0xc)) | ||
362 | #define BP_CLKCTRL_FRAC_CLKGATEIO 31 | ||
363 | #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 | ||
364 | #define BF_CLKCTRL_FRAC_CLKGATEIO(v) (((v) << 31) & 0x80000000) | ||
365 | #define BP_CLKCTRL_FRAC_IO_STABLE 30 | ||
366 | #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 | ||
367 | #define BF_CLKCTRL_FRAC_IO_STABLE(v) (((v) << 30) & 0x40000000) | ||
368 | #define BP_CLKCTRL_FRAC_IOFRAC 24 | ||
369 | #define BM_CLKCTRL_FRAC_IOFRAC 0x3f000000 | ||
370 | #define BF_CLKCTRL_FRAC_IOFRAC(v) (((v) << 24) & 0x3f000000) | ||
371 | #define BP_CLKCTRL_FRAC_CLKGATEPIX 23 | ||
372 | #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x800000 | ||
373 | #define BF_CLKCTRL_FRAC_CLKGATEPIX(v) (((v) << 23) & 0x800000) | ||
374 | #define BP_CLKCTRL_FRAC_PIX_STABLE 22 | ||
375 | #define BM_CLKCTRL_FRAC_PIX_STABLE 0x400000 | ||
376 | #define BF_CLKCTRL_FRAC_PIX_STABLE(v) (((v) << 22) & 0x400000) | ||
377 | #define BP_CLKCTRL_FRAC_PIXFRAC 16 | ||
378 | #define BM_CLKCTRL_FRAC_PIXFRAC 0x3f0000 | ||
379 | #define BF_CLKCTRL_FRAC_PIXFRAC(v) (((v) << 16) & 0x3f0000) | ||
380 | #define BP_CLKCTRL_FRAC_CLKGATEEMI 15 | ||
381 | #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x8000 | ||
382 | #define BF_CLKCTRL_FRAC_CLKGATEEMI(v) (((v) << 15) & 0x8000) | ||
383 | #define BP_CLKCTRL_FRAC_EMI_STABLE 14 | ||
384 | #define BM_CLKCTRL_FRAC_EMI_STABLE 0x4000 | ||
385 | #define BF_CLKCTRL_FRAC_EMI_STABLE(v) (((v) << 14) & 0x4000) | ||
386 | #define BP_CLKCTRL_FRAC_EMIFRAC 8 | ||
387 | #define BM_CLKCTRL_FRAC_EMIFRAC 0x3f00 | ||
388 | #define BF_CLKCTRL_FRAC_EMIFRAC(v) (((v) << 8) & 0x3f00) | ||
389 | #define BP_CLKCTRL_FRAC_CLKGATECPU 7 | ||
390 | #define BM_CLKCTRL_FRAC_CLKGATECPU 0x80 | ||
391 | #define BF_CLKCTRL_FRAC_CLKGATECPU(v) (((v) << 7) & 0x80) | ||
392 | #define BP_CLKCTRL_FRAC_CPU_STABLE 6 | ||
393 | #define BM_CLKCTRL_FRAC_CPU_STABLE 0x40 | ||
394 | #define BF_CLKCTRL_FRAC_CPU_STABLE(v) (((v) << 6) & 0x40) | ||
395 | #define BP_CLKCTRL_FRAC_CPUFRAC 0 | ||
396 | #define BM_CLKCTRL_FRAC_CPUFRAC 0x3f | ||
397 | #define BF_CLKCTRL_FRAC_CPUFRAC(v) (((v) << 0) & 0x3f) | ||
398 | |||
399 | /** | ||
400 | * Register: HW_CLKCTRL_CLKSEQ | ||
401 | * Address: 0xe0 | ||
402 | * SCT: yes | ||
403 | */ | ||
404 | #define HW_CLKCTRL_CLKSEQ (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x0)) | ||
405 | #define HW_CLKCTRL_CLKSEQ_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x4)) | ||
406 | #define HW_CLKCTRL_CLKSEQ_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x8)) | ||
407 | #define HW_CLKCTRL_CLKSEQ_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0xc)) | ||
408 | #define BP_CLKCTRL_CLKSEQ_BYPASS_CPU 7 | ||
409 | #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x80 | ||
410 | #define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v) (((v) << 7) & 0x80) | ||
411 | #define BP_CLKCTRL_CLKSEQ_BYPASS_EMI 6 | ||
412 | #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x40 | ||
413 | #define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v) (((v) << 6) & 0x40) | ||
414 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SSP 5 | ||
415 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x20 | ||
416 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v) (((v) << 5) & 0x20) | ||
417 | #define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI 4 | ||
418 | #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x10 | ||
419 | #define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) (((v) << 4) & 0x10) | ||
420 | #define BP_CLKCTRL_CLKSEQ_BYPASS_IR 3 | ||
421 | #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x8 | ||
422 | #define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v) (((v) << 3) & 0x8) | ||
423 | #define BP_CLKCTRL_CLKSEQ_BYPASS_PIX 1 | ||
424 | #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x2 | ||
425 | #define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v) (((v) << 1) & 0x2) | ||
426 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF 0 | ||
427 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x1 | ||
428 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) (((v) << 0) & 0x1) | ||
429 | |||
430 | /** | ||
431 | * Register: HW_CLKCTRL_RESET | ||
432 | * Address: 0xf0 | ||
433 | * SCT: no | ||
434 | */ | ||
435 | #define HW_CLKCTRL_RESET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0)) | ||
436 | #define BP_CLKCTRL_RESET_CHIP 1 | ||
437 | #define BM_CLKCTRL_RESET_CHIP 0x2 | ||
438 | #define BF_CLKCTRL_RESET_CHIP(v) (((v) << 1) & 0x2) | ||
439 | #define BP_CLKCTRL_RESET_DIG 0 | ||
440 | #define BM_CLKCTRL_RESET_DIG 0x1 | ||
441 | #define BF_CLKCTRL_RESET_DIG(v) (((v) << 0) & 0x1) | ||
442 | |||
443 | /** | ||
444 | * Register: HW_CLKCTRL_VERSION | ||
445 | * Address: 0x100 | ||
446 | * SCT: no | ||
447 | */ | ||
448 | #define HW_CLKCTRL_VERSION (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100)) | ||
449 | #define BP_CLKCTRL_VERSION_MAJOR 24 | ||
450 | #define BM_CLKCTRL_VERSION_MAJOR 0xff000000 | ||
451 | #define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
452 | #define BP_CLKCTRL_VERSION_MINOR 16 | ||
453 | #define BM_CLKCTRL_VERSION_MINOR 0xff0000 | ||
454 | #define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
455 | #define BP_CLKCTRL_VERSION_STEP 0 | ||
456 | #define BM_CLKCTRL_VERSION_STEP 0xffff | ||
457 | #define BF_CLKCTRL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
458 | |||
459 | #endif /* __HEADERGEN__STMP3700__CLKCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h new file mode 100644 index 0000000000..f0b6273439 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h | |||
@@ -0,0 +1,707 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__DCP__H__ | ||
24 | #define __HEADERGEN__STMP3700__DCP__H__ | ||
25 | |||
26 | #define REGS_DCP_BASE (0x80028000) | ||
27 | |||
28 | #define REGS_DCP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DCP_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DCP_CTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DCP_CTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DCP_CTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DCP_CTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DCP_CTRL_SFTRST 31 | ||
40 | #define BM_DCP_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_DCP_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_DCP_CTRL_CLKGATE 30 | ||
43 | #define BM_DCP_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_DCP_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_DCP_CTRL_PRESENT_CRYPTO 29 | ||
46 | #define BM_DCP_CTRL_PRESENT_CRYPTO 0x20000000 | ||
47 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1 | ||
48 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Absent 0x0 | ||
49 | #define BF_DCP_CTRL_PRESENT_CRYPTO(v) (((v) << 29) & 0x20000000) | ||
50 | #define BF_DCP_CTRL_PRESENT_CRYPTO_V(v) ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000) | ||
51 | #define BP_DCP_CTRL_PRESENT_CSC 28 | ||
52 | #define BM_DCP_CTRL_PRESENT_CSC 0x10000000 | ||
53 | #define BV_DCP_CTRL_PRESENT_CSC__Present 0x1 | ||
54 | #define BV_DCP_CTRL_PRESENT_CSC__Absent 0x0 | ||
55 | #define BF_DCP_CTRL_PRESENT_CSC(v) (((v) << 28) & 0x10000000) | ||
56 | #define BF_DCP_CTRL_PRESENT_CSC_V(v) ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000) | ||
57 | #define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES 23 | ||
58 | #define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x800000 | ||
59 | #define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v) (((v) << 23) & 0x800000) | ||
60 | #define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING 22 | ||
61 | #define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x400000 | ||
62 | #define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v) (((v) << 22) & 0x400000) | ||
63 | #define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 21 | ||
64 | #define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 0x200000 | ||
65 | #define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v) (((v) << 21) & 0x200000) | ||
66 | #define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE 8 | ||
67 | #define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE 0x100 | ||
68 | #define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v) (((v) << 8) & 0x100) | ||
69 | #define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 | ||
70 | #define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0xff | ||
71 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x1 | ||
72 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x2 | ||
73 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x4 | ||
74 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x8 | ||
75 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) (((v) << 0) & 0xff) | ||
76 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v) ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff) | ||
77 | |||
78 | /** | ||
79 | * Register: HW_DCP_STAT | ||
80 | * Address: 0x10 | ||
81 | * SCT: yes | ||
82 | */ | ||
83 | #define HW_DCP_STAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0)) | ||
84 | #define HW_DCP_STAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4)) | ||
85 | #define HW_DCP_STAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8)) | ||
86 | #define HW_DCP_STAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc)) | ||
87 | #define BP_DCP_STAT_OTP_KEY_READY 28 | ||
88 | #define BM_DCP_STAT_OTP_KEY_READY 0x10000000 | ||
89 | #define BF_DCP_STAT_OTP_KEY_READY(v) (((v) << 28) & 0x10000000) | ||
90 | #define BP_DCP_STAT_CUR_CHANNEL 24 | ||
91 | #define BM_DCP_STAT_CUR_CHANNEL 0xf000000 | ||
92 | #define BV_DCP_STAT_CUR_CHANNEL__None 0x0 | ||
93 | #define BV_DCP_STAT_CUR_CHANNEL__CH0 0x1 | ||
94 | #define BV_DCP_STAT_CUR_CHANNEL__CH1 0x2 | ||
95 | #define BV_DCP_STAT_CUR_CHANNEL__CH2 0x3 | ||
96 | #define BV_DCP_STAT_CUR_CHANNEL__CH3 0x4 | ||
97 | #define BV_DCP_STAT_CUR_CHANNEL__CSC 0x8 | ||
98 | #define BF_DCP_STAT_CUR_CHANNEL(v) (((v) << 24) & 0xf000000) | ||
99 | #define BF_DCP_STAT_CUR_CHANNEL_V(v) ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000) | ||
100 | #define BP_DCP_STAT_READY_CHANNELS 16 | ||
101 | #define BM_DCP_STAT_READY_CHANNELS 0xff0000 | ||
102 | #define BV_DCP_STAT_READY_CHANNELS__CH0 0x1 | ||
103 | #define BV_DCP_STAT_READY_CHANNELS__CH1 0x2 | ||
104 | #define BV_DCP_STAT_READY_CHANNELS__CH2 0x4 | ||
105 | #define BV_DCP_STAT_READY_CHANNELS__CH3 0x8 | ||
106 | #define BF_DCP_STAT_READY_CHANNELS(v) (((v) << 16) & 0xff0000) | ||
107 | #define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000) | ||
108 | #define BP_DCP_STAT_CSCIRQ 8 | ||
109 | #define BM_DCP_STAT_CSCIRQ 0x100 | ||
110 | #define BF_DCP_STAT_CSCIRQ(v) (((v) << 8) & 0x100) | ||
111 | #define BP_DCP_STAT_IRQ 0 | ||
112 | #define BM_DCP_STAT_IRQ 0xf | ||
113 | #define BF_DCP_STAT_IRQ(v) (((v) << 0) & 0xf) | ||
114 | |||
115 | /** | ||
116 | * Register: HW_DCP_CHANNELCTRL | ||
117 | * Address: 0x20 | ||
118 | * SCT: yes | ||
119 | */ | ||
120 | #define HW_DCP_CHANNELCTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0)) | ||
121 | #define HW_DCP_CHANNELCTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4)) | ||
122 | #define HW_DCP_CHANNELCTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8)) | ||
123 | #define HW_DCP_CHANNELCTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc)) | ||
124 | #define BP_DCP_CHANNELCTRL_CSC_PRIORITY 17 | ||
125 | #define BM_DCP_CHANNELCTRL_CSC_PRIORITY 0x60000 | ||
126 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH 0x3 | ||
127 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED 0x2 | ||
128 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW 0x1 | ||
129 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0 | ||
130 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v) (((v) << 17) & 0x60000) | ||
131 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v) ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000) | ||
132 | #define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED 16 | ||
133 | #define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED 0x10000 | ||
134 | #define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v) (((v) << 16) & 0x10000) | ||
135 | #define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 8 | ||
136 | #define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 0xff00 | ||
137 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x1 | ||
138 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x2 | ||
139 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x4 | ||
140 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x8 | ||
141 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) (((v) << 8) & 0xff00) | ||
142 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00) | ||
143 | #define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 | ||
144 | #define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0xff | ||
145 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x1 | ||
146 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x2 | ||
147 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x4 | ||
148 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x8 | ||
149 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) (((v) << 0) & 0xff) | ||
150 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_DCP_CAPABILITY0 | ||
154 | * Address: 0x30 | ||
155 | * SCT: no | ||
156 | */ | ||
157 | #define HW_DCP_CAPABILITY0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30)) | ||
158 | #define BP_DCP_CAPABILITY0_NUM_CHANNELS 8 | ||
159 | #define BM_DCP_CAPABILITY0_NUM_CHANNELS 0xf00 | ||
160 | #define BF_DCP_CAPABILITY0_NUM_CHANNELS(v) (((v) << 8) & 0xf00) | ||
161 | #define BP_DCP_CAPABILITY0_NUM_KEYS 0 | ||
162 | #define BM_DCP_CAPABILITY0_NUM_KEYS 0xff | ||
163 | #define BF_DCP_CAPABILITY0_NUM_KEYS(v) (((v) << 0) & 0xff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_DCP_CAPABILITY1 | ||
167 | * Address: 0x40 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_DCP_CAPABILITY1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40)) | ||
171 | #define BP_DCP_CAPABILITY1_HASH_ALGORITHMS 16 | ||
172 | #define BM_DCP_CAPABILITY1_HASH_ALGORITHMS 0xffff0000 | ||
173 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1 0x1 | ||
174 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x2 | ||
175 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) (((v) << 16) & 0xffff0000) | ||
176 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000) | ||
177 | #define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0 | ||
178 | #define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0xffff | ||
179 | #define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x1 | ||
180 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) (((v) << 0) & 0xffff) | ||
181 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_DCP_CONTEXT | ||
185 | * Address: 0x50 | ||
186 | * SCT: no | ||
187 | */ | ||
188 | #define HW_DCP_CONTEXT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50)) | ||
189 | #define BP_DCP_CONTEXT_ADDR 0 | ||
190 | #define BM_DCP_CONTEXT_ADDR 0xffffffff | ||
191 | #define BF_DCP_CONTEXT_ADDR(v) (((v) << 0) & 0xffffffff) | ||
192 | |||
193 | /** | ||
194 | * Register: HW_DCP_KEY | ||
195 | * Address: 0x60 | ||
196 | * SCT: no | ||
197 | */ | ||
198 | #define HW_DCP_KEY (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60)) | ||
199 | #define BP_DCP_KEY_INDEX 4 | ||
200 | #define BM_DCP_KEY_INDEX 0x30 | ||
201 | #define BF_DCP_KEY_INDEX(v) (((v) << 4) & 0x30) | ||
202 | #define BP_DCP_KEY_SUBWORD 0 | ||
203 | #define BM_DCP_KEY_SUBWORD 0x3 | ||
204 | #define BF_DCP_KEY_SUBWORD(v) (((v) << 0) & 0x3) | ||
205 | |||
206 | /** | ||
207 | * Register: HW_DCP_KEYDATA | ||
208 | * Address: 0x70 | ||
209 | * SCT: no | ||
210 | */ | ||
211 | #define HW_DCP_KEYDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70)) | ||
212 | #define BP_DCP_KEYDATA_DATA 0 | ||
213 | #define BM_DCP_KEYDATA_DATA 0xffffffff | ||
214 | #define BF_DCP_KEYDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
215 | |||
216 | /** | ||
217 | * Register: HW_DCP_PACKET0 | ||
218 | * Address: 0x80 | ||
219 | * SCT: no | ||
220 | */ | ||
221 | #define HW_DCP_PACKET0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80)) | ||
222 | #define BP_DCP_PACKET0_ADDR 0 | ||
223 | #define BM_DCP_PACKET0_ADDR 0xffffffff | ||
224 | #define BF_DCP_PACKET0_ADDR(v) (((v) << 0) & 0xffffffff) | ||
225 | |||
226 | /** | ||
227 | * Register: HW_DCP_PACKET1 | ||
228 | * Address: 0x90 | ||
229 | * SCT: no | ||
230 | */ | ||
231 | #define HW_DCP_PACKET1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90)) | ||
232 | #define BP_DCP_PACKET1_TAG 24 | ||
233 | #define BM_DCP_PACKET1_TAG 0xff000000 | ||
234 | #define BF_DCP_PACKET1_TAG(v) (((v) << 24) & 0xff000000) | ||
235 | #define BP_DCP_PACKET1_OUTPUT_WORDSWAP 23 | ||
236 | #define BM_DCP_PACKET1_OUTPUT_WORDSWAP 0x800000 | ||
237 | #define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v) (((v) << 23) & 0x800000) | ||
238 | #define BP_DCP_PACKET1_OUTPUT_BYTESWAP 22 | ||
239 | #define BM_DCP_PACKET1_OUTPUT_BYTESWAP 0x400000 | ||
240 | #define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v) (((v) << 22) & 0x400000) | ||
241 | #define BP_DCP_PACKET1_INPUT_WORDSWAP 21 | ||
242 | #define BM_DCP_PACKET1_INPUT_WORDSWAP 0x200000 | ||
243 | #define BF_DCP_PACKET1_INPUT_WORDSWAP(v) (((v) << 21) & 0x200000) | ||
244 | #define BP_DCP_PACKET1_INPUT_BYTESWAP 20 | ||
245 | #define BM_DCP_PACKET1_INPUT_BYTESWAP 0x100000 | ||
246 | #define BF_DCP_PACKET1_INPUT_BYTESWAP(v) (((v) << 20) & 0x100000) | ||
247 | #define BP_DCP_PACKET1_KEY_WORDSWAP 19 | ||
248 | #define BM_DCP_PACKET1_KEY_WORDSWAP 0x80000 | ||
249 | #define BF_DCP_PACKET1_KEY_WORDSWAP(v) (((v) << 19) & 0x80000) | ||
250 | #define BP_DCP_PACKET1_KEY_BYTESWAP 18 | ||
251 | #define BM_DCP_PACKET1_KEY_BYTESWAP 0x40000 | ||
252 | #define BF_DCP_PACKET1_KEY_BYTESWAP(v) (((v) << 18) & 0x40000) | ||
253 | #define BP_DCP_PACKET1_TEST_SEMA_IRQ 17 | ||
254 | #define BM_DCP_PACKET1_TEST_SEMA_IRQ 0x20000 | ||
255 | #define BF_DCP_PACKET1_TEST_SEMA_IRQ(v) (((v) << 17) & 0x20000) | ||
256 | #define BP_DCP_PACKET1_CONSTANT_FILL 16 | ||
257 | #define BM_DCP_PACKET1_CONSTANT_FILL 0x10000 | ||
258 | #define BF_DCP_PACKET1_CONSTANT_FILL(v) (((v) << 16) & 0x10000) | ||
259 | #define BP_DCP_PACKET1_HASH_OUTPUT 15 | ||
260 | #define BM_DCP_PACKET1_HASH_OUTPUT 0x8000 | ||
261 | #define BV_DCP_PACKET1_HASH_OUTPUT__INPUT 0x0 | ||
262 | #define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x1 | ||
263 | #define BF_DCP_PACKET1_HASH_OUTPUT(v) (((v) << 15) & 0x8000) | ||
264 | #define BF_DCP_PACKET1_HASH_OUTPUT_V(v) ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000) | ||
265 | #define BP_DCP_PACKET1_CHECK_HASH 14 | ||
266 | #define BM_DCP_PACKET1_CHECK_HASH 0x4000 | ||
267 | #define BF_DCP_PACKET1_CHECK_HASH(v) (((v) << 14) & 0x4000) | ||
268 | #define BP_DCP_PACKET1_HASH_TERM 13 | ||
269 | #define BM_DCP_PACKET1_HASH_TERM 0x2000 | ||
270 | #define BF_DCP_PACKET1_HASH_TERM(v) (((v) << 13) & 0x2000) | ||
271 | #define BP_DCP_PACKET1_HASH_INIT 12 | ||
272 | #define BM_DCP_PACKET1_HASH_INIT 0x1000 | ||
273 | #define BF_DCP_PACKET1_HASH_INIT(v) (((v) << 12) & 0x1000) | ||
274 | #define BP_DCP_PACKET1_PAYLOAD_KEY 11 | ||
275 | #define BM_DCP_PACKET1_PAYLOAD_KEY 0x800 | ||
276 | #define BF_DCP_PACKET1_PAYLOAD_KEY(v) (((v) << 11) & 0x800) | ||
277 | #define BP_DCP_PACKET1_OTP_KEY 10 | ||
278 | #define BM_DCP_PACKET1_OTP_KEY 0x400 | ||
279 | #define BF_DCP_PACKET1_OTP_KEY(v) (((v) << 10) & 0x400) | ||
280 | #define BP_DCP_PACKET1_CIPHER_INIT 9 | ||
281 | #define BM_DCP_PACKET1_CIPHER_INIT 0x200 | ||
282 | #define BF_DCP_PACKET1_CIPHER_INIT(v) (((v) << 9) & 0x200) | ||
283 | #define BP_DCP_PACKET1_CIPHER_ENCRYPT 8 | ||
284 | #define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x100 | ||
285 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x1 | ||
286 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x0 | ||
287 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT(v) (((v) << 8) & 0x100) | ||
288 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v) ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100) | ||
289 | #define BP_DCP_PACKET1_ENABLE_BLIT 7 | ||
290 | #define BM_DCP_PACKET1_ENABLE_BLIT 0x80 | ||
291 | #define BF_DCP_PACKET1_ENABLE_BLIT(v) (((v) << 7) & 0x80) | ||
292 | #define BP_DCP_PACKET1_ENABLE_HASH 6 | ||
293 | #define BM_DCP_PACKET1_ENABLE_HASH 0x40 | ||
294 | #define BF_DCP_PACKET1_ENABLE_HASH(v) (((v) << 6) & 0x40) | ||
295 | #define BP_DCP_PACKET1_ENABLE_CIPHER 5 | ||
296 | #define BM_DCP_PACKET1_ENABLE_CIPHER 0x20 | ||
297 | #define BF_DCP_PACKET1_ENABLE_CIPHER(v) (((v) << 5) & 0x20) | ||
298 | #define BP_DCP_PACKET1_ENABLE_MEMCOPY 4 | ||
299 | #define BM_DCP_PACKET1_ENABLE_MEMCOPY 0x10 | ||
300 | #define BF_DCP_PACKET1_ENABLE_MEMCOPY(v) (((v) << 4) & 0x10) | ||
301 | #define BP_DCP_PACKET1_CHAIN_CONTIGUOUS 3 | ||
302 | #define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x8 | ||
303 | #define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v) (((v) << 3) & 0x8) | ||
304 | #define BP_DCP_PACKET1_CHAIN 2 | ||
305 | #define BM_DCP_PACKET1_CHAIN 0x4 | ||
306 | #define BF_DCP_PACKET1_CHAIN(v) (((v) << 2) & 0x4) | ||
307 | #define BP_DCP_PACKET1_DECR_SEMAPHORE 1 | ||
308 | #define BM_DCP_PACKET1_DECR_SEMAPHORE 0x2 | ||
309 | #define BF_DCP_PACKET1_DECR_SEMAPHORE(v) (((v) << 1) & 0x2) | ||
310 | #define BP_DCP_PACKET1_INTERRUPT 0 | ||
311 | #define BM_DCP_PACKET1_INTERRUPT 0x1 | ||
312 | #define BF_DCP_PACKET1_INTERRUPT(v) (((v) << 0) & 0x1) | ||
313 | |||
314 | /** | ||
315 | * Register: HW_DCP_PACKET2 | ||
316 | * Address: 0xa0 | ||
317 | * SCT: no | ||
318 | */ | ||
319 | #define HW_DCP_PACKET2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0)) | ||
320 | #define BP_DCP_PACKET2_CIPHER_CFG 24 | ||
321 | #define BM_DCP_PACKET2_CIPHER_CFG 0xff000000 | ||
322 | #define BF_DCP_PACKET2_CIPHER_CFG(v) (((v) << 24) & 0xff000000) | ||
323 | #define BP_DCP_PACKET2_HASH_SELECT 16 | ||
324 | #define BM_DCP_PACKET2_HASH_SELECT 0xf0000 | ||
325 | #define BV_DCP_PACKET2_HASH_SELECT__SHA1 0x0 | ||
326 | #define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x1 | ||
327 | #define BF_DCP_PACKET2_HASH_SELECT(v) (((v) << 16) & 0xf0000) | ||
328 | #define BF_DCP_PACKET2_HASH_SELECT_V(v) ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000) | ||
329 | #define BP_DCP_PACKET2_KEY_SELECT 8 | ||
330 | #define BM_DCP_PACKET2_KEY_SELECT 0xff00 | ||
331 | #define BF_DCP_PACKET2_KEY_SELECT(v) (((v) << 8) & 0xff00) | ||
332 | #define BP_DCP_PACKET2_CIPHER_MODE 4 | ||
333 | #define BM_DCP_PACKET2_CIPHER_MODE 0xf0 | ||
334 | #define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x0 | ||
335 | #define BV_DCP_PACKET2_CIPHER_MODE__CCB 0x1 | ||
336 | #define BF_DCP_PACKET2_CIPHER_MODE(v) (((v) << 4) & 0xf0) | ||
337 | #define BF_DCP_PACKET2_CIPHER_MODE_V(v) ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0) | ||
338 | #define BP_DCP_PACKET2_CIPHER_SELECT 0 | ||
339 | #define BM_DCP_PACKET2_CIPHER_SELECT 0xf | ||
340 | #define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x0 | ||
341 | #define BF_DCP_PACKET2_CIPHER_SELECT(v) (((v) << 0) & 0xf) | ||
342 | #define BF_DCP_PACKET2_CIPHER_SELECT_V(v) ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf) | ||
343 | |||
344 | /** | ||
345 | * Register: HW_DCP_PACKET3 | ||
346 | * Address: 0xb0 | ||
347 | * SCT: no | ||
348 | */ | ||
349 | #define HW_DCP_PACKET3 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0)) | ||
350 | #define BP_DCP_PACKET3_ADDR 0 | ||
351 | #define BM_DCP_PACKET3_ADDR 0xffffffff | ||
352 | #define BF_DCP_PACKET3_ADDR(v) (((v) << 0) & 0xffffffff) | ||
353 | |||
354 | /** | ||
355 | * Register: HW_DCP_PACKET4 | ||
356 | * Address: 0xc0 | ||
357 | * SCT: no | ||
358 | */ | ||
359 | #define HW_DCP_PACKET4 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0)) | ||
360 | #define BP_DCP_PACKET4_ADDR 0 | ||
361 | #define BM_DCP_PACKET4_ADDR 0xffffffff | ||
362 | #define BF_DCP_PACKET4_ADDR(v) (((v) << 0) & 0xffffffff) | ||
363 | |||
364 | /** | ||
365 | * Register: HW_DCP_PACKET5 | ||
366 | * Address: 0xd0 | ||
367 | * SCT: no | ||
368 | */ | ||
369 | #define HW_DCP_PACKET5 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0)) | ||
370 | #define BP_DCP_PACKET5_COUNT 0 | ||
371 | #define BM_DCP_PACKET5_COUNT 0xffffffff | ||
372 | #define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff) | ||
373 | |||
374 | /** | ||
375 | * Register: HW_DCP_PACKET6 | ||
376 | * Address: 0xe0 | ||
377 | * SCT: no | ||
378 | */ | ||
379 | #define HW_DCP_PACKET6 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0)) | ||
380 | #define BP_DCP_PACKET6_ADDR 0 | ||
381 | #define BM_DCP_PACKET6_ADDR 0xffffffff | ||
382 | #define BF_DCP_PACKET6_ADDR(v) (((v) << 0) & 0xffffffff) | ||
383 | |||
384 | /** | ||
385 | * Register: HW_DCP_CHnCMDPTR | ||
386 | * Address: 0x100+n*0x40 | ||
387 | * SCT: no | ||
388 | */ | ||
389 | #define HW_DCP_CHnCMDPTR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40)) | ||
390 | #define BP_DCP_CHnCMDPTR_ADDR 0 | ||
391 | #define BM_DCP_CHnCMDPTR_ADDR 0xffffffff | ||
392 | #define BF_DCP_CHnCMDPTR_ADDR(v) (((v) << 0) & 0xffffffff) | ||
393 | |||
394 | /** | ||
395 | * Register: HW_DCP_CHnSEMA | ||
396 | * Address: 0x110+n*0x40 | ||
397 | * SCT: no | ||
398 | */ | ||
399 | #define HW_DCP_CHnSEMA(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40)) | ||
400 | #define BP_DCP_CHnSEMA_VALUE 16 | ||
401 | #define BM_DCP_CHnSEMA_VALUE 0xff0000 | ||
402 | #define BF_DCP_CHnSEMA_VALUE(v) (((v) << 16) & 0xff0000) | ||
403 | #define BP_DCP_CHnSEMA_INCREMENT 0 | ||
404 | #define BM_DCP_CHnSEMA_INCREMENT 0xff | ||
405 | #define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff) | ||
406 | |||
407 | /** | ||
408 | * Register: HW_DCP_CHnSTAT | ||
409 | * Address: 0x120+n*0x40 | ||
410 | * SCT: yes | ||
411 | */ | ||
412 | #define HW_DCP_CHnSTAT(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0)) | ||
413 | #define HW_DCP_CHnSTAT_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4)) | ||
414 | #define HW_DCP_CHnSTAT_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8)) | ||
415 | #define HW_DCP_CHnSTAT_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc)) | ||
416 | #define BP_DCP_CHnSTAT_TAG 24 | ||
417 | #define BM_DCP_CHnSTAT_TAG 0xff000000 | ||
418 | #define BF_DCP_CHnSTAT_TAG(v) (((v) << 24) & 0xff000000) | ||
419 | #define BP_DCP_CHnSTAT_ERROR_CODE 16 | ||
420 | #define BM_DCP_CHnSTAT_ERROR_CODE 0xff0000 | ||
421 | #define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x1 | ||
422 | #define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN 0x2 | ||
423 | #define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR 0x3 | ||
424 | #define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR 0x4 | ||
425 | #define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE 0x5 | ||
426 | #define BF_DCP_CHnSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
427 | #define BF_DCP_CHnSTAT_ERROR_CODE_V(v) ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
428 | #define BP_DCP_CHnSTAT_ERROR_DST 5 | ||
429 | #define BM_DCP_CHnSTAT_ERROR_DST 0x20 | ||
430 | #define BF_DCP_CHnSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
431 | #define BP_DCP_CHnSTAT_ERROR_SRC 4 | ||
432 | #define BM_DCP_CHnSTAT_ERROR_SRC 0x10 | ||
433 | #define BF_DCP_CHnSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
434 | #define BP_DCP_CHnSTAT_ERROR_PACKET 3 | ||
435 | #define BM_DCP_CHnSTAT_ERROR_PACKET 0x8 | ||
436 | #define BF_DCP_CHnSTAT_ERROR_PACKET(v) (((v) << 3) & 0x8) | ||
437 | #define BP_DCP_CHnSTAT_ERROR_SETUP 2 | ||
438 | #define BM_DCP_CHnSTAT_ERROR_SETUP 0x4 | ||
439 | #define BF_DCP_CHnSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
440 | #define BP_DCP_CHnSTAT_HASH_MISMATCH 1 | ||
441 | #define BM_DCP_CHnSTAT_HASH_MISMATCH 0x2 | ||
442 | #define BF_DCP_CHnSTAT_HASH_MISMATCH(v) (((v) << 1) & 0x2) | ||
443 | |||
444 | /** | ||
445 | * Register: HW_DCP_CHnOPTS | ||
446 | * Address: 0x130+n*0x40 | ||
447 | * SCT: yes | ||
448 | */ | ||
449 | #define HW_DCP_CHnOPTS(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0)) | ||
450 | #define HW_DCP_CHnOPTS_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4)) | ||
451 | #define HW_DCP_CHnOPTS_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8)) | ||
452 | #define HW_DCP_CHnOPTS_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc)) | ||
453 | #define BP_DCP_CHnOPTS_RECOVERY_TIMER 0 | ||
454 | #define BM_DCP_CHnOPTS_RECOVERY_TIMER 0xffff | ||
455 | #define BF_DCP_CHnOPTS_RECOVERY_TIMER(v) (((v) << 0) & 0xffff) | ||
456 | |||
457 | /** | ||
458 | * Register: HW_DCP_CSCCTRL0 | ||
459 | * Address: 0x300 | ||
460 | * SCT: yes | ||
461 | */ | ||
462 | #define HW_DCP_CSCCTRL0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0)) | ||
463 | #define HW_DCP_CSCCTRL0_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4)) | ||
464 | #define HW_DCP_CSCCTRL0_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8)) | ||
465 | #define HW_DCP_CSCCTRL0_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc)) | ||
466 | #define BP_DCP_CSCCTRL0_UPSAMPLE 14 | ||
467 | #define BM_DCP_CSCCTRL0_UPSAMPLE 0x4000 | ||
468 | #define BF_DCP_CSCCTRL0_UPSAMPLE(v) (((v) << 14) & 0x4000) | ||
469 | #define BP_DCP_CSCCTRL0_SCALE 13 | ||
470 | #define BM_DCP_CSCCTRL0_SCALE 0x2000 | ||
471 | #define BF_DCP_CSCCTRL0_SCALE(v) (((v) << 13) & 0x2000) | ||
472 | #define BP_DCP_CSCCTRL0_ROTATE 12 | ||
473 | #define BM_DCP_CSCCTRL0_ROTATE 0x1000 | ||
474 | #define BF_DCP_CSCCTRL0_ROTATE(v) (((v) << 12) & 0x1000) | ||
475 | #define BP_DCP_CSCCTRL0_SUBSAMPLE 11 | ||
476 | #define BM_DCP_CSCCTRL0_SUBSAMPLE 0x800 | ||
477 | #define BF_DCP_CSCCTRL0_SUBSAMPLE(v) (((v) << 11) & 0x800) | ||
478 | #define BP_DCP_CSCCTRL0_DELTA 10 | ||
479 | #define BM_DCP_CSCCTRL0_DELTA 0x400 | ||
480 | #define BF_DCP_CSCCTRL0_DELTA(v) (((v) << 10) & 0x400) | ||
481 | #define BP_DCP_CSCCTRL0_RGB_FORMAT 8 | ||
482 | #define BM_DCP_CSCCTRL0_RGB_FORMAT 0x300 | ||
483 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0 | ||
484 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24 0x2 | ||
485 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I 0x3 | ||
486 | #define BF_DCP_CSCCTRL0_RGB_FORMAT(v) (((v) << 8) & 0x300) | ||
487 | #define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v) ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300) | ||
488 | #define BP_DCP_CSCCTRL0_YUV_FORMAT 4 | ||
489 | #define BM_DCP_CSCCTRL0_YUV_FORMAT 0xf0 | ||
490 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0 | ||
491 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2 | ||
492 | #define BF_DCP_CSCCTRL0_YUV_FORMAT(v) (((v) << 4) & 0xf0) | ||
493 | #define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v) ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0) | ||
494 | #define BP_DCP_CSCCTRL0_ENABLE 0 | ||
495 | #define BM_DCP_CSCCTRL0_ENABLE 0x1 | ||
496 | #define BF_DCP_CSCCTRL0_ENABLE(v) (((v) << 0) & 0x1) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_DCP_CSCSTAT | ||
500 | * Address: 0x310 | ||
501 | * SCT: yes | ||
502 | */ | ||
503 | #define HW_DCP_CSCSTAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0)) | ||
504 | #define HW_DCP_CSCSTAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4)) | ||
505 | #define HW_DCP_CSCSTAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8)) | ||
506 | #define HW_DCP_CSCSTAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc)) | ||
507 | #define BP_DCP_CSCSTAT_ERROR_CODE 16 | ||
508 | #define BM_DCP_CSCSTAT_ERROR_CODE 0xff0000 | ||
509 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1 | ||
510 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2 | ||
511 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3 | ||
512 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4 | ||
513 | #define BF_DCP_CSCSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
514 | #define BF_DCP_CSCSTAT_ERROR_CODE_V(v) ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
515 | #define BP_DCP_CSCSTAT_ERROR_DST 5 | ||
516 | #define BM_DCP_CSCSTAT_ERROR_DST 0x20 | ||
517 | #define BF_DCP_CSCSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
518 | #define BP_DCP_CSCSTAT_ERROR_SRC 4 | ||
519 | #define BM_DCP_CSCSTAT_ERROR_SRC 0x10 | ||
520 | #define BF_DCP_CSCSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
521 | #define BP_DCP_CSCSTAT_ERROR_SETUP 2 | ||
522 | #define BM_DCP_CSCSTAT_ERROR_SETUP 0x4 | ||
523 | #define BF_DCP_CSCSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
524 | #define BP_DCP_CSCSTAT_COMPLETE 0 | ||
525 | #define BM_DCP_CSCSTAT_COMPLETE 0x1 | ||
526 | #define BF_DCP_CSCSTAT_COMPLETE(v) (((v) << 0) & 0x1) | ||
527 | |||
528 | /** | ||
529 | * Register: HW_DCP_CSCOUTBUFPARAM | ||
530 | * Address: 0x320 | ||
531 | * SCT: no | ||
532 | */ | ||
533 | #define HW_DCP_CSCOUTBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320)) | ||
534 | #define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE 12 | ||
535 | #define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE 0xfff000 | ||
536 | #define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000) | ||
537 | #define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE 0 | ||
538 | #define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE 0xfff | ||
539 | #define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
540 | |||
541 | /** | ||
542 | * Register: HW_DCP_CSCINBUFPARAM | ||
543 | * Address: 0x330 | ||
544 | * SCT: no | ||
545 | */ | ||
546 | #define HW_DCP_CSCINBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330)) | ||
547 | #define BP_DCP_CSCINBUFPARAM_LINE_SIZE 0 | ||
548 | #define BM_DCP_CSCINBUFPARAM_LINE_SIZE 0xfff | ||
549 | #define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
550 | |||
551 | /** | ||
552 | * Register: HW_DCP_CSCRGB | ||
553 | * Address: 0x340 | ||
554 | * SCT: no | ||
555 | */ | ||
556 | #define HW_DCP_CSCRGB (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340)) | ||
557 | #define BP_DCP_CSCRGB_ADDR 0 | ||
558 | #define BM_DCP_CSCRGB_ADDR 0xffffffff | ||
559 | #define BF_DCP_CSCRGB_ADDR(v) (((v) << 0) & 0xffffffff) | ||
560 | |||
561 | /** | ||
562 | * Register: HW_DCP_CSCLUMA | ||
563 | * Address: 0x350 | ||
564 | * SCT: no | ||
565 | */ | ||
566 | #define HW_DCP_CSCLUMA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350)) | ||
567 | #define BP_DCP_CSCLUMA_ADDR 0 | ||
568 | #define BM_DCP_CSCLUMA_ADDR 0xffffffff | ||
569 | #define BF_DCP_CSCLUMA_ADDR(v) (((v) << 0) & 0xffffffff) | ||
570 | |||
571 | /** | ||
572 | * Register: HW_DCP_CSCCHROMAU | ||
573 | * Address: 0x360 | ||
574 | * SCT: no | ||
575 | */ | ||
576 | #define HW_DCP_CSCCHROMAU (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360)) | ||
577 | #define BP_DCP_CSCCHROMAU_ADDR 0 | ||
578 | #define BM_DCP_CSCCHROMAU_ADDR 0xffffffff | ||
579 | #define BF_DCP_CSCCHROMAU_ADDR(v) (((v) << 0) & 0xffffffff) | ||
580 | |||
581 | /** | ||
582 | * Register: HW_DCP_CSCCHROMAV | ||
583 | * Address: 0x370 | ||
584 | * SCT: no | ||
585 | */ | ||
586 | #define HW_DCP_CSCCHROMAV (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370)) | ||
587 | #define BP_DCP_CSCCHROMAV_ADDR 0 | ||
588 | #define BM_DCP_CSCCHROMAV_ADDR 0xffffffff | ||
589 | #define BF_DCP_CSCCHROMAV_ADDR(v) (((v) << 0) & 0xffffffff) | ||
590 | |||
591 | /** | ||
592 | * Register: HW_DCP_CSCCOEFF0 | ||
593 | * Address: 0x380 | ||
594 | * SCT: no | ||
595 | */ | ||
596 | #define HW_DCP_CSCCOEFF0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380)) | ||
597 | #define BP_DCP_CSCCOEFF0_C0 16 | ||
598 | #define BM_DCP_CSCCOEFF0_C0 0x3ff0000 | ||
599 | #define BF_DCP_CSCCOEFF0_C0(v) (((v) << 16) & 0x3ff0000) | ||
600 | #define BP_DCP_CSCCOEFF0_UV_OFFSET 8 | ||
601 | #define BM_DCP_CSCCOEFF0_UV_OFFSET 0xff00 | ||
602 | #define BF_DCP_CSCCOEFF0_UV_OFFSET(v) (((v) << 8) & 0xff00) | ||
603 | #define BP_DCP_CSCCOEFF0_Y_OFFSET 0 | ||
604 | #define BM_DCP_CSCCOEFF0_Y_OFFSET 0xff | ||
605 | #define BF_DCP_CSCCOEFF0_Y_OFFSET(v) (((v) << 0) & 0xff) | ||
606 | |||
607 | /** | ||
608 | * Register: HW_DCP_CSCCOEFF1 | ||
609 | * Address: 0x390 | ||
610 | * SCT: no | ||
611 | */ | ||
612 | #define HW_DCP_CSCCOEFF1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390)) | ||
613 | #define BP_DCP_CSCCOEFF1_C1 16 | ||
614 | #define BM_DCP_CSCCOEFF1_C1 0x3ff0000 | ||
615 | #define BF_DCP_CSCCOEFF1_C1(v) (((v) << 16) & 0x3ff0000) | ||
616 | #define BP_DCP_CSCCOEFF1_C4 0 | ||
617 | #define BM_DCP_CSCCOEFF1_C4 0x3ff | ||
618 | #define BF_DCP_CSCCOEFF1_C4(v) (((v) << 0) & 0x3ff) | ||
619 | |||
620 | /** | ||
621 | * Register: HW_DCP_CSCCOEFF2 | ||
622 | * Address: 0x3a0 | ||
623 | * SCT: no | ||
624 | */ | ||
625 | #define HW_DCP_CSCCOEFF2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0)) | ||
626 | #define BP_DCP_CSCCOEFF2_C2 16 | ||
627 | #define BM_DCP_CSCCOEFF2_C2 0x3ff0000 | ||
628 | #define BF_DCP_CSCCOEFF2_C2(v) (((v) << 16) & 0x3ff0000) | ||
629 | #define BP_DCP_CSCCOEFF2_C3 0 | ||
630 | #define BM_DCP_CSCCOEFF2_C3 0x3ff | ||
631 | #define BF_DCP_CSCCOEFF2_C3(v) (((v) << 0) & 0x3ff) | ||
632 | |||
633 | /** | ||
634 | * Register: HW_DCP_CSCXSCALE | ||
635 | * Address: 0x3e0 | ||
636 | * SCT: no | ||
637 | */ | ||
638 | #define HW_DCP_CSCXSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0)) | ||
639 | #define BP_DCP_CSCXSCALE_INT 24 | ||
640 | #define BM_DCP_CSCXSCALE_INT 0x3000000 | ||
641 | #define BF_DCP_CSCXSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
642 | #define BP_DCP_CSCXSCALE_FRAC 12 | ||
643 | #define BM_DCP_CSCXSCALE_FRAC 0xfff000 | ||
644 | #define BF_DCP_CSCXSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
645 | #define BP_DCP_CSCXSCALE_WIDTH 0 | ||
646 | #define BM_DCP_CSCXSCALE_WIDTH 0xfff | ||
647 | #define BF_DCP_CSCXSCALE_WIDTH(v) (((v) << 0) & 0xfff) | ||
648 | |||
649 | /** | ||
650 | * Register: HW_DCP_CSCYSCALE | ||
651 | * Address: 0x3f0 | ||
652 | * SCT: no | ||
653 | */ | ||
654 | #define HW_DCP_CSCYSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0)) | ||
655 | #define BP_DCP_CSCYSCALE_INT 24 | ||
656 | #define BM_DCP_CSCYSCALE_INT 0x3000000 | ||
657 | #define BF_DCP_CSCYSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
658 | #define BP_DCP_CSCYSCALE_FRAC 12 | ||
659 | #define BM_DCP_CSCYSCALE_FRAC 0xfff000 | ||
660 | #define BF_DCP_CSCYSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
661 | #define BP_DCP_CSCYSCALE_HEIGHT 0 | ||
662 | #define BM_DCP_CSCYSCALE_HEIGHT 0xfff | ||
663 | #define BF_DCP_CSCYSCALE_HEIGHT(v) (((v) << 0) & 0xfff) | ||
664 | |||
665 | /** | ||
666 | * Register: HW_DCP_DBGSELECT | ||
667 | * Address: 0x400 | ||
668 | * SCT: no | ||
669 | */ | ||
670 | #define HW_DCP_DBGSELECT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400)) | ||
671 | #define BP_DCP_DBGSELECT_INDEX 0 | ||
672 | #define BM_DCP_DBGSELECT_INDEX 0xff | ||
673 | #define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1 | ||
674 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10 | ||
675 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11 | ||
676 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12 | ||
677 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13 | ||
678 | #define BF_DCP_DBGSELECT_INDEX(v) (((v) << 0) & 0xff) | ||
679 | #define BF_DCP_DBGSELECT_INDEX_V(v) ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff) | ||
680 | |||
681 | /** | ||
682 | * Register: HW_DCP_DBGDATA | ||
683 | * Address: 0x410 | ||
684 | * SCT: no | ||
685 | */ | ||
686 | #define HW_DCP_DBGDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410)) | ||
687 | #define BP_DCP_DBGDATA_DATA 0 | ||
688 | #define BM_DCP_DBGDATA_DATA 0xffffffff | ||
689 | #define BF_DCP_DBGDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
690 | |||
691 | /** | ||
692 | * Register: HW_DCP_VERSION | ||
693 | * Address: 0x420 | ||
694 | * SCT: no | ||
695 | */ | ||
696 | #define HW_DCP_VERSION (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420)) | ||
697 | #define BP_DCP_VERSION_MAJOR 24 | ||
698 | #define BM_DCP_VERSION_MAJOR 0xff000000 | ||
699 | #define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
700 | #define BP_DCP_VERSION_MINOR 16 | ||
701 | #define BM_DCP_VERSION_MINOR 0xff0000 | ||
702 | #define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
703 | #define BP_DCP_VERSION_STEP 0 | ||
704 | #define BM_DCP_VERSION_STEP 0xffff | ||
705 | #define BF_DCP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
706 | |||
707 | #endif /* __HEADERGEN__STMP3700__DCP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h new file mode 100644 index 0000000000..69d4e7128f --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h | |||
@@ -0,0 +1,759 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__DIGCTL__H__ | ||
24 | #define __HEADERGEN__STMP3700__DIGCTL__H__ | ||
25 | |||
26 | #define REGS_DIGCTL_BASE (0x8001c000) | ||
27 | |||
28 | #define REGS_DIGCTL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DIGCTL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DIGCTL_CTRL_TRAP_IRQ 29 | ||
40 | #define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 | ||
41 | #define BF_DIGCTL_CTRL_TRAP_IRQ(v) (((v) << 29) & 0x20000000) | ||
42 | #define BP_DIGCTL_CTRL_DCP_BIST_CLKEN 23 | ||
43 | #define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x800000 | ||
44 | #define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v) (((v) << 23) & 0x800000) | ||
45 | #define BP_DIGCTL_CTRL_DCP_BIST_START 22 | ||
46 | #define BM_DIGCTL_CTRL_DCP_BIST_START 0x400000 | ||
47 | #define BF_DIGCTL_CTRL_DCP_BIST_START(v) (((v) << 22) & 0x400000) | ||
48 | #define BP_DIGCTL_CTRL_ARM_BIST_CLKEN 21 | ||
49 | #define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x200000 | ||
50 | #define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v) (((v) << 21) & 0x200000) | ||
51 | #define BP_DIGCTL_CTRL_USB_TESTMODE 20 | ||
52 | #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 | ||
53 | #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) | ||
54 | #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 | ||
55 | #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 | ||
56 | #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) | ||
57 | #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 | ||
58 | #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 | ||
59 | #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) | ||
60 | #define BP_DIGCTL_CTRL_ARM_BIST_START 17 | ||
61 | #define BM_DIGCTL_CTRL_ARM_BIST_START 0x20000 | ||
62 | #define BF_DIGCTL_CTRL_ARM_BIST_START(v) (((v) << 17) & 0x20000) | ||
63 | #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 | ||
64 | #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 | ||
65 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 | ||
66 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 | ||
67 | #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) | ||
68 | #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) | ||
69 | #define BP_DIGCTL_CTRL_SAIF_LOOPBACK 15 | ||
70 | #define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x8000 | ||
71 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 | ||
72 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 | ||
73 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v) (((v) << 15) & 0x8000) | ||
74 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000) | ||
75 | #define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 | ||
76 | #define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x6000 | ||
77 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 | ||
78 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 | ||
79 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 | ||
80 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 | ||
81 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) (((v) << 13) & 0x6000) | ||
82 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000) | ||
83 | #define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL 12 | ||
84 | #define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x1000 | ||
85 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 | ||
86 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 | ||
87 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) (((v) << 12) & 0x1000) | ||
88 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000) | ||
89 | #define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 11 | ||
90 | #define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x800 | ||
91 | #define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) (((v) << 11) & 0x800) | ||
92 | #define BP_DIGCTL_CTRL_USE_SERIAL_JTAG 6 | ||
93 | #define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x40 | ||
94 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 | ||
95 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 | ||
96 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v) (((v) << 6) & 0x40) | ||
97 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v) ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40) | ||
98 | #define BP_DIGCTL_CTRL_TRAP_IN_RANGE 5 | ||
99 | #define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x20 | ||
100 | #define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v) (((v) << 5) & 0x20) | ||
101 | #define BP_DIGCTL_CTRL_TRAP_ENABLE 4 | ||
102 | #define BM_DIGCTL_CTRL_TRAP_ENABLE 0x10 | ||
103 | #define BF_DIGCTL_CTRL_TRAP_ENABLE(v) (((v) << 4) & 0x10) | ||
104 | #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 | ||
105 | #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 | ||
106 | #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) | ||
107 | #define BP_DIGCTL_CTRL_USB_CLKGATE 2 | ||
108 | #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 | ||
109 | #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 | ||
110 | #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 | ||
111 | #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) | ||
112 | #define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) | ||
113 | #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 | ||
114 | #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 | ||
115 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 | ||
116 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 | ||
117 | #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) | ||
118 | #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) | ||
119 | #define BP_DIGCTL_CTRL_LATCH_ENTROPY 0 | ||
120 | #define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x1 | ||
121 | #define BF_DIGCTL_CTRL_LATCH_ENTROPY(v) (((v) << 0) & 0x1) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_DIGCTL_STATUS | ||
125 | * Address: 0x10 | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10)) | ||
129 | #define BP_DIGCTL_STATUS_USB_HS_PRESENT 31 | ||
130 | #define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 | ||
131 | #define BF_DIGCTL_STATUS_USB_HS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
132 | #define BP_DIGCTL_STATUS_USB_OTG_PRESENT 30 | ||
133 | #define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 | ||
134 | #define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v) (((v) << 30) & 0x40000000) | ||
135 | #define BP_DIGCTL_STATUS_USB_HOST_PRESENT 29 | ||
136 | #define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 | ||
137 | #define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v) (((v) << 29) & 0x20000000) | ||
138 | #define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT 28 | ||
139 | #define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 | ||
140 | #define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
141 | #define BP_DIGCTL_STATUS_DCP_BIST_FAIL 10 | ||
142 | #define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x400 | ||
143 | #define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v) (((v) << 10) & 0x400) | ||
144 | #define BP_DIGCTL_STATUS_DCP_BIST_PASS 9 | ||
145 | #define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x200 | ||
146 | #define BF_DIGCTL_STATUS_DCP_BIST_PASS(v) (((v) << 9) & 0x200) | ||
147 | #define BP_DIGCTL_STATUS_DCP_BIST_DONE 8 | ||
148 | #define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x100 | ||
149 | #define BF_DIGCTL_STATUS_DCP_BIST_DONE(v) (((v) << 8) & 0x100) | ||
150 | #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 | ||
151 | #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 | ||
152 | #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) | ||
153 | #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 | ||
154 | #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0xe | ||
155 | #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0xe) | ||
156 | #define BP_DIGCTL_STATUS_WRITTEN 0 | ||
157 | #define BM_DIGCTL_STATUS_WRITTEN 0x1 | ||
158 | #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) | ||
159 | |||
160 | /** | ||
161 | * Register: HW_DIGCTL_HCLKCOUNT | ||
162 | * Address: 0x20 | ||
163 | * SCT: no | ||
164 | */ | ||
165 | #define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20)) | ||
166 | #define BP_DIGCTL_HCLKCOUNT_COUNT 0 | ||
167 | #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff | ||
168 | #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_DIGCTL_RAMCTRL | ||
172 | * Address: 0x30 | ||
173 | * SCT: yes | ||
174 | */ | ||
175 | #define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) | ||
176 | #define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) | ||
177 | #define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) | ||
178 | #define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) | ||
179 | #define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 | ||
180 | #define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0xf00 | ||
181 | #define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) (((v) << 8) & 0xf00) | ||
182 | #define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0 | ||
183 | #define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x1 | ||
184 | #define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) (((v) << 0) & 0x1) | ||
185 | |||
186 | /** | ||
187 | * Register: HW_DIGCTL_RAMREPAIR | ||
188 | * Address: 0x40 | ||
189 | * SCT: yes | ||
190 | */ | ||
191 | #define HW_DIGCTL_RAMREPAIR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) | ||
192 | #define HW_DIGCTL_RAMREPAIR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) | ||
193 | #define HW_DIGCTL_RAMREPAIR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) | ||
194 | #define HW_DIGCTL_RAMREPAIR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) | ||
195 | #define BP_DIGCTL_RAMREPAIR_ADDR 0 | ||
196 | #define BM_DIGCTL_RAMREPAIR_ADDR 0xffff | ||
197 | #define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) << 0) & 0xffff) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_DIGCTL_ROMCTRL | ||
201 | * Address: 0x50 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_DIGCTL_ROMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) | ||
205 | #define HW_DIGCTL_ROMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) | ||
206 | #define HW_DIGCTL_ROMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) | ||
207 | #define HW_DIGCTL_ROMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) | ||
208 | #define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 | ||
209 | #define BM_DIGCTL_ROMCTRL_RD_MARGIN 0xf | ||
210 | #define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) (((v) << 0) & 0xf) | ||
211 | |||
212 | /** | ||
213 | * Register: HW_DIGCTL_WRITEONCE | ||
214 | * Address: 0x60 | ||
215 | * SCT: no | ||
216 | */ | ||
217 | #define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) | ||
218 | #define BP_DIGCTL_WRITEONCE_BITS 0 | ||
219 | #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff | ||
220 | #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) | ||
221 | |||
222 | /** | ||
223 | * Register: HW_DIGCTL_ENTROPY | ||
224 | * Address: 0x90 | ||
225 | * SCT: no | ||
226 | */ | ||
227 | #define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) | ||
228 | #define BP_DIGCTL_ENTROPY_VALUE 0 | ||
229 | #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff | ||
230 | #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) | ||
231 | |||
232 | /** | ||
233 | * Register: HW_DIGCTL_ENTROPY_LATCHED | ||
234 | * Address: 0xa0 | ||
235 | * SCT: no | ||
236 | */ | ||
237 | #define HW_DIGCTL_ENTROPY_LATCHED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) | ||
238 | #define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 | ||
239 | #define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xffffffff | ||
240 | #define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (((v) << 0) & 0xffffffff) | ||
241 | |||
242 | /** | ||
243 | * Register: HW_DIGCTL_SJTAGDBG | ||
244 | * Address: 0xb0 | ||
245 | * SCT: yes | ||
246 | */ | ||
247 | #define HW_DIGCTL_SJTAGDBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) | ||
248 | #define HW_DIGCTL_SJTAGDBG_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) | ||
249 | #define HW_DIGCTL_SJTAGDBG_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) | ||
250 | #define HW_DIGCTL_SJTAGDBG_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) | ||
251 | #define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 | ||
252 | #define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x7ff0000 | ||
253 | #define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) (((v) << 16) & 0x7ff0000) | ||
254 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDO 10 | ||
255 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x400 | ||
256 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v) (((v) << 10) & 0x400) | ||
257 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDI 9 | ||
258 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x200 | ||
259 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v) (((v) << 9) & 0x200) | ||
260 | #define BP_DIGCTL_SJTAGDBG_SJTAG_MODE 8 | ||
261 | #define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x100 | ||
262 | #define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v) (((v) << 8) & 0x100) | ||
263 | #define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 | ||
264 | #define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0xf0 | ||
265 | #define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) (((v) << 4) & 0xf0) | ||
266 | #define BP_DIGCTL_SJTAGDBG_ACTIVE 3 | ||
267 | #define BM_DIGCTL_SJTAGDBG_ACTIVE 0x8 | ||
268 | #define BF_DIGCTL_SJTAGDBG_ACTIVE(v) (((v) << 3) & 0x8) | ||
269 | #define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 2 | ||
270 | #define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x4 | ||
271 | #define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) (((v) << 2) & 0x4) | ||
272 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 1 | ||
273 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x2 | ||
274 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) (((v) << 1) & 0x2) | ||
275 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0 | ||
276 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x1 | ||
277 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) (((v) << 0) & 0x1) | ||
278 | |||
279 | /** | ||
280 | * Register: HW_DIGCTL_MICROSECONDS | ||
281 | * Address: 0xc0 | ||
282 | * SCT: yes | ||
283 | */ | ||
284 | #define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0)) | ||
285 | #define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4)) | ||
286 | #define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8)) | ||
287 | #define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc)) | ||
288 | #define BP_DIGCTL_MICROSECONDS_VALUE 0 | ||
289 | #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff | ||
290 | #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) | ||
291 | |||
292 | /** | ||
293 | * Register: HW_DIGCTL_DBGRD | ||
294 | * Address: 0xd0 | ||
295 | * SCT: no | ||
296 | */ | ||
297 | #define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) | ||
298 | #define BP_DIGCTL_DBGRD_COMPLEMENT 0 | ||
299 | #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff | ||
300 | #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) | ||
301 | |||
302 | /** | ||
303 | * Register: HW_DIGCTL_DBG | ||
304 | * Address: 0xe0 | ||
305 | * SCT: no | ||
306 | */ | ||
307 | #define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0)) | ||
308 | #define BP_DIGCTL_DBG_VALUE 0 | ||
309 | #define BM_DIGCTL_DBG_VALUE 0xffffffff | ||
310 | #define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) | ||
311 | |||
312 | /** | ||
313 | * Register: HW_DIGCTL_OCRAM_BIST_CSR | ||
314 | * Address: 0xf0 | ||
315 | * SCT: yes | ||
316 | */ | ||
317 | #define HW_DIGCTL_OCRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0)) | ||
318 | #define HW_DIGCTL_OCRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4)) | ||
319 | #define HW_DIGCTL_OCRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8)) | ||
320 | #define HW_DIGCTL_OCRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc)) | ||
321 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 9 | ||
322 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x200 | ||
323 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) (((v) << 9) & 0x200) | ||
324 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 8 | ||
325 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x100 | ||
326 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) (((v) << 8) & 0x100) | ||
327 | #define BP_DIGCTL_OCRAM_BIST_CSR_FAIL 3 | ||
328 | #define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x8 | ||
329 | #define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) | ||
330 | #define BP_DIGCTL_OCRAM_BIST_CSR_PASS 2 | ||
331 | #define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x4 | ||
332 | #define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) | ||
333 | #define BP_DIGCTL_OCRAM_BIST_CSR_DONE 1 | ||
334 | #define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x2 | ||
335 | #define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) | ||
336 | #define BP_DIGCTL_OCRAM_BIST_CSR_START 0 | ||
337 | #define BM_DIGCTL_OCRAM_BIST_CSR_START 0x1 | ||
338 | #define BF_DIGCTL_OCRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) | ||
339 | |||
340 | /** | ||
341 | * Register: HW_DIGCTL_OCRAM_STATUS0 | ||
342 | * Address: 0x110 | ||
343 | * SCT: no | ||
344 | */ | ||
345 | #define HW_DIGCTL_OCRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110)) | ||
346 | #define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 | ||
347 | #define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xffffffff | ||
348 | #define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) | ||
349 | |||
350 | /** | ||
351 | * Register: HW_DIGCTL_OCRAM_STATUS1 | ||
352 | * Address: 0x120 | ||
353 | * SCT: no | ||
354 | */ | ||
355 | #define HW_DIGCTL_OCRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120)) | ||
356 | #define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 | ||
357 | #define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xffffffff | ||
358 | #define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) | ||
359 | |||
360 | /** | ||
361 | * Register: HW_DIGCTL_OCRAM_STATUS2 | ||
362 | * Address: 0x130 | ||
363 | * SCT: no | ||
364 | */ | ||
365 | #define HW_DIGCTL_OCRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130)) | ||
366 | #define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 | ||
367 | #define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xffffffff | ||
368 | #define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) | ||
369 | |||
370 | /** | ||
371 | * Register: HW_DIGCTL_OCRAM_STATUS3 | ||
372 | * Address: 0x140 | ||
373 | * SCT: no | ||
374 | */ | ||
375 | #define HW_DIGCTL_OCRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140)) | ||
376 | #define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 | ||
377 | #define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xffffffff | ||
378 | #define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) | ||
379 | |||
380 | /** | ||
381 | * Register: HW_DIGCTL_OCRAM_STATUS4 | ||
382 | * Address: 0x150 | ||
383 | * SCT: no | ||
384 | */ | ||
385 | #define HW_DIGCTL_OCRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150)) | ||
386 | #define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 | ||
387 | #define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xffffffff | ||
388 | #define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) | ||
389 | |||
390 | /** | ||
391 | * Register: HW_DIGCTL_OCRAM_STATUS5 | ||
392 | * Address: 0x160 | ||
393 | * SCT: no | ||
394 | */ | ||
395 | #define HW_DIGCTL_OCRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160)) | ||
396 | #define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 | ||
397 | #define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xffffffff | ||
398 | #define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) | ||
399 | |||
400 | /** | ||
401 | * Register: HW_DIGCTL_OCRAM_STATUS6 | ||
402 | * Address: 0x170 | ||
403 | * SCT: no | ||
404 | */ | ||
405 | #define HW_DIGCTL_OCRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170)) | ||
406 | #define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 | ||
407 | #define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xffffffff | ||
408 | #define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) | ||
409 | |||
410 | /** | ||
411 | * Register: HW_DIGCTL_OCRAM_STATUS7 | ||
412 | * Address: 0x180 | ||
413 | * SCT: no | ||
414 | */ | ||
415 | #define HW_DIGCTL_OCRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180)) | ||
416 | #define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 | ||
417 | #define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xffffffff | ||
418 | #define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) | ||
419 | |||
420 | /** | ||
421 | * Register: HW_DIGCTL_OCRAM_STATUS8 | ||
422 | * Address: 0x190 | ||
423 | * SCT: no | ||
424 | */ | ||
425 | #define HW_DIGCTL_OCRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190)) | ||
426 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 | ||
427 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0xffff0000 | ||
428 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0xffff0000) | ||
429 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 | ||
430 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0xffff | ||
431 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0xffff) | ||
432 | |||
433 | /** | ||
434 | * Register: HW_DIGCTL_OCRAM_STATUS9 | ||
435 | * Address: 0x1a0 | ||
436 | * SCT: no | ||
437 | */ | ||
438 | #define HW_DIGCTL_OCRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0)) | ||
439 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 | ||
440 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0xffff0000 | ||
441 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0xffff0000) | ||
442 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 | ||
443 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0xffff | ||
444 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0xffff) | ||
445 | |||
446 | /** | ||
447 | * Register: HW_DIGCTL_OCRAM_STATUS10 | ||
448 | * Address: 0x1b0 | ||
449 | * SCT: no | ||
450 | */ | ||
451 | #define HW_DIGCTL_OCRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0)) | ||
452 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 | ||
453 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0xffff0000 | ||
454 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0xffff0000) | ||
455 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 | ||
456 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0xffff | ||
457 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0xffff) | ||
458 | |||
459 | /** | ||
460 | * Register: HW_DIGCTL_OCRAM_STATUS11 | ||
461 | * Address: 0x1c0 | ||
462 | * SCT: no | ||
463 | */ | ||
464 | #define HW_DIGCTL_OCRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0)) | ||
465 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 | ||
466 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0xffff0000 | ||
467 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0xffff0000) | ||
468 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 | ||
469 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0xffff | ||
470 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0xffff) | ||
471 | |||
472 | /** | ||
473 | * Register: HW_DIGCTL_OCRAM_STATUS12 | ||
474 | * Address: 0x1d0 | ||
475 | * SCT: no | ||
476 | */ | ||
477 | #define HW_DIGCTL_OCRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0)) | ||
478 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 | ||
479 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x1f000000 | ||
480 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000) | ||
481 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 | ||
482 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x1f0000 | ||
483 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000) | ||
484 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 | ||
485 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x1f00 | ||
486 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00) | ||
487 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 | ||
488 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x1f | ||
489 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f) | ||
490 | |||
491 | /** | ||
492 | * Register: HW_DIGCTL_OCRAM_STATUS13 | ||
493 | * Address: 0x1e0 | ||
494 | * SCT: no | ||
495 | */ | ||
496 | #define HW_DIGCTL_OCRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0)) | ||
497 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 | ||
498 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x1f000000 | ||
499 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000) | ||
500 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 | ||
501 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x1f0000 | ||
502 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000) | ||
503 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 | ||
504 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x1f00 | ||
505 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00) | ||
506 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 | ||
507 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x1f | ||
508 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f) | ||
509 | |||
510 | /** | ||
511 | * Register: HW_DIGCTL_SCRATCH0 | ||
512 | * Address: 0x290 | ||
513 | * SCT: no | ||
514 | */ | ||
515 | #define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) | ||
516 | #define BP_DIGCTL_SCRATCH0_PTR 0 | ||
517 | #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff | ||
518 | #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) | ||
519 | |||
520 | /** | ||
521 | * Register: HW_DIGCTL_SCRATCH1 | ||
522 | * Address: 0x2a0 | ||
523 | * SCT: no | ||
524 | */ | ||
525 | #define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) | ||
526 | #define BP_DIGCTL_SCRATCH1_PTR 0 | ||
527 | #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff | ||
528 | #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) | ||
529 | |||
530 | /** | ||
531 | * Register: HW_DIGCTL_ARMCACHE | ||
532 | * Address: 0x2b0 | ||
533 | * SCT: no | ||
534 | */ | ||
535 | #define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) | ||
536 | #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 | ||
537 | #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 | ||
538 | #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) | ||
539 | #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 | ||
540 | #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 | ||
541 | #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) | ||
542 | #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 | ||
543 | #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 | ||
544 | #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) | ||
545 | |||
546 | /** | ||
547 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW | ||
548 | * Address: 0x2c0 | ||
549 | * SCT: no | ||
550 | */ | ||
551 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0)) | ||
552 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 | ||
553 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xffffffff | ||
554 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (((v) << 0) & 0xffffffff) | ||
555 | |||
556 | /** | ||
557 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH | ||
558 | * Address: 0x2d0 | ||
559 | * SCT: no | ||
560 | */ | ||
561 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0)) | ||
562 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 | ||
563 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xffffffff | ||
564 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (((v) << 0) & 0xffffffff) | ||
565 | |||
566 | /** | ||
567 | * Register: HW_DIGCTL_SGTL | ||
568 | * Address: 0x300 | ||
569 | * SCT: no | ||
570 | */ | ||
571 | #define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) | ||
572 | #define BP_DIGCTL_SGTL_COPYRIGHT 0 | ||
573 | #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff | ||
574 | #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) | ||
575 | |||
576 | /** | ||
577 | * Register: HW_DIGCTL_CHIPID | ||
578 | * Address: 0x310 | ||
579 | * SCT: no | ||
580 | */ | ||
581 | #define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) | ||
582 | #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 | ||
583 | #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 | ||
584 | #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) | ||
585 | #define BP_DIGCTL_CHIPID_REVISION 0 | ||
586 | #define BM_DIGCTL_CHIPID_REVISION 0xff | ||
587 | #define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) | ||
588 | |||
589 | /** | ||
590 | * Register: HW_DIGCTL_AHB_STATS_SELECT | ||
591 | * Address: 0x330 | ||
592 | * SCT: no | ||
593 | */ | ||
594 | #define HW_DIGCTL_AHB_STATS_SELECT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330)) | ||
595 | #define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 | ||
596 | #define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0xf000000 | ||
597 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 | ||
598 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 | ||
599 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 | ||
600 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) (((v) << 24) & 0xf000000) | ||
601 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000) | ||
602 | #define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 | ||
603 | #define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0xf0000 | ||
604 | #define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 | ||
605 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) (((v) << 16) & 0xf0000) | ||
606 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000) | ||
607 | #define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 | ||
608 | #define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0xf00 | ||
609 | #define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 | ||
610 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) (((v) << 8) & 0xf00) | ||
611 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00) | ||
612 | #define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 | ||
613 | #define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0xf | ||
614 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 | ||
615 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 | ||
616 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) (((v) << 0) & 0xf) | ||
617 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf) | ||
618 | |||
619 | /** | ||
620 | * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES | ||
621 | * Address: 0x340 | ||
622 | * SCT: no | ||
623 | */ | ||
624 | #define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340)) | ||
625 | #define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 | ||
626 | #define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
627 | #define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
628 | |||
629 | /** | ||
630 | * Register: HW_DIGCTL_L0_AHB_DATA_STALLED | ||
631 | * Address: 0x350 | ||
632 | * SCT: no | ||
633 | */ | ||
634 | #define HW_DIGCTL_L0_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350)) | ||
635 | #define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 | ||
636 | #define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xffffffff | ||
637 | #define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
638 | |||
639 | /** | ||
640 | * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES | ||
641 | * Address: 0x360 | ||
642 | * SCT: no | ||
643 | */ | ||
644 | #define HW_DIGCTL_L0_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360)) | ||
645 | #define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 | ||
646 | #define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
647 | #define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
648 | |||
649 | /** | ||
650 | * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES | ||
651 | * Address: 0x370 | ||
652 | * SCT: no | ||
653 | */ | ||
654 | #define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370)) | ||
655 | #define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 | ||
656 | #define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
657 | #define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
658 | |||
659 | /** | ||
660 | * Register: HW_DIGCTL_L1_AHB_DATA_STALLED | ||
661 | * Address: 0x380 | ||
662 | * SCT: no | ||
663 | */ | ||
664 | #define HW_DIGCTL_L1_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380)) | ||
665 | #define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 | ||
666 | #define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xffffffff | ||
667 | #define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
668 | |||
669 | /** | ||
670 | * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES | ||
671 | * Address: 0x390 | ||
672 | * SCT: no | ||
673 | */ | ||
674 | #define HW_DIGCTL_L1_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390)) | ||
675 | #define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 | ||
676 | #define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
677 | #define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
678 | |||
679 | /** | ||
680 | * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES | ||
681 | * Address: 0x3a0 | ||
682 | * SCT: no | ||
683 | */ | ||
684 | #define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0)) | ||
685 | #define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 | ||
686 | #define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
687 | #define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
688 | |||
689 | /** | ||
690 | * Register: HW_DIGCTL_L2_AHB_DATA_STALLED | ||
691 | * Address: 0x3b0 | ||
692 | * SCT: no | ||
693 | */ | ||
694 | #define HW_DIGCTL_L2_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0)) | ||
695 | #define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 | ||
696 | #define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xffffffff | ||
697 | #define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
698 | |||
699 | /** | ||
700 | * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES | ||
701 | * Address: 0x3c0 | ||
702 | * SCT: no | ||
703 | */ | ||
704 | #define HW_DIGCTL_L2_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0)) | ||
705 | #define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 | ||
706 | #define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
707 | #define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
708 | |||
709 | /** | ||
710 | * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES | ||
711 | * Address: 0x3d0 | ||
712 | * SCT: no | ||
713 | */ | ||
714 | #define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0)) | ||
715 | #define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 | ||
716 | #define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
717 | #define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
718 | |||
719 | /** | ||
720 | * Register: HW_DIGCTL_L3_AHB_DATA_STALLED | ||
721 | * Address: 0x3e0 | ||
722 | * SCT: no | ||
723 | */ | ||
724 | #define HW_DIGCTL_L3_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0)) | ||
725 | #define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 | ||
726 | #define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xffffffff | ||
727 | #define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
728 | |||
729 | /** | ||
730 | * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES | ||
731 | * Address: 0x3f0 | ||
732 | * SCT: no | ||
733 | */ | ||
734 | #define HW_DIGCTL_L3_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0)) | ||
735 | #define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 | ||
736 | #define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
737 | #define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
738 | |||
739 | /** | ||
740 | * Register: HW_DIGCTL_MPTEn_LOC | ||
741 | * Address: 0x400+n*0x10 | ||
742 | * SCT: no | ||
743 | */ | ||
744 | #define HW_DIGCTL_MPTEn_LOC(n) (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10)) | ||
745 | #define BP_DIGCTL_MPTEn_LOC_LOC 0 | ||
746 | #define BM_DIGCTL_MPTEn_LOC_LOC 0xfff | ||
747 | #define BF_DIGCTL_MPTEn_LOC_LOC(v) (((v) << 0) & 0xfff) | ||
748 | |||
749 | /** | ||
750 | * Register: HW_DIGCTL_EMICLK_DELAY | ||
751 | * Address: 0x480 | ||
752 | * SCT: no | ||
753 | */ | ||
754 | #define HW_DIGCTL_EMICLK_DELAY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x480)) | ||
755 | #define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 | ||
756 | #define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x1f | ||
757 | #define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) (((v) << 0) & 0x1f) | ||
758 | |||
759 | #endif /* __HEADERGEN__STMP3700__DIGCTL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h new file mode 100644 index 0000000000..7ec44c41ee --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h | |||
@@ -0,0 +1,671 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__DRAM__H__ | ||
24 | #define __HEADERGEN__STMP3700__DRAM__H__ | ||
25 | |||
26 | #define REGS_DRAM_BASE (0x800e0000) | ||
27 | |||
28 | #define REGS_DRAM_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DRAM_CTL00 | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_DRAM_CTL00 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0)) | ||
36 | #define BP_DRAM_CTL00_AHB0_W_PRIORITY 24 | ||
37 | #define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x1000000 | ||
38 | #define BF_DRAM_CTL00_AHB0_W_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
39 | #define BP_DRAM_CTL00_AHB0_R_PRIORITY 16 | ||
40 | #define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x10000 | ||
41 | #define BF_DRAM_CTL00_AHB0_R_PRIORITY(v) (((v) << 16) & 0x10000) | ||
42 | #define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG 8 | ||
43 | #define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x100 | ||
44 | #define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100) | ||
45 | #define BP_DRAM_CTL00_ADDR_CMP_EN 0 | ||
46 | #define BM_DRAM_CTL00_ADDR_CMP_EN 0x1 | ||
47 | #define BF_DRAM_CTL00_ADDR_CMP_EN(v) (((v) << 0) & 0x1) | ||
48 | |||
49 | /** | ||
50 | * Register: HW_DRAM_CTL01 | ||
51 | * Address: 0x4 | ||
52 | * SCT: no | ||
53 | */ | ||
54 | #define HW_DRAM_CTL01 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4)) | ||
55 | #define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG 24 | ||
56 | #define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x1000000 | ||
57 | #define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000) | ||
58 | #define BP_DRAM_CTL01_AHB1_W_PRIORITY 16 | ||
59 | #define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x10000 | ||
60 | #define BF_DRAM_CTL01_AHB1_W_PRIORITY(v) (((v) << 16) & 0x10000) | ||
61 | #define BP_DRAM_CTL01_AHB1_R_PRIORITY 8 | ||
62 | #define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x100 | ||
63 | #define BF_DRAM_CTL01_AHB1_R_PRIORITY(v) (((v) << 8) & 0x100) | ||
64 | #define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0 | ||
65 | #define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x1 | ||
66 | #define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1) | ||
67 | |||
68 | /** | ||
69 | * Register: HW_DRAM_CTL02 | ||
70 | * Address: 0x8 | ||
71 | * SCT: no | ||
72 | */ | ||
73 | #define HW_DRAM_CTL02 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8)) | ||
74 | #define BP_DRAM_CTL02_AHB3_R_PRIORITY 24 | ||
75 | #define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x1000000 | ||
76 | #define BF_DRAM_CTL02_AHB3_R_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
77 | #define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG 16 | ||
78 | #define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x10000 | ||
79 | #define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000) | ||
80 | #define BP_DRAM_CTL02_AHB2_W_PRIORITY 8 | ||
81 | #define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x100 | ||
82 | #define BF_DRAM_CTL02_AHB2_W_PRIORITY(v) (((v) << 8) & 0x100) | ||
83 | #define BP_DRAM_CTL02_AHB2_R_PRIORITY 0 | ||
84 | #define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x1 | ||
85 | #define BF_DRAM_CTL02_AHB2_R_PRIORITY(v) (((v) << 0) & 0x1) | ||
86 | |||
87 | /** | ||
88 | * Register: HW_DRAM_CTL03 | ||
89 | * Address: 0xc | ||
90 | * SCT: no | ||
91 | */ | ||
92 | #define HW_DRAM_CTL03 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc)) | ||
93 | #define BP_DRAM_CTL03_AUTO_REFRESH_MODE 24 | ||
94 | #define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x1000000 | ||
95 | #define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v) (((v) << 24) & 0x1000000) | ||
96 | #define BP_DRAM_CTL03_AREFRESH 16 | ||
97 | #define BM_DRAM_CTL03_AREFRESH 0x10000 | ||
98 | #define BF_DRAM_CTL03_AREFRESH(v) (((v) << 16) & 0x10000) | ||
99 | #define BP_DRAM_CTL03_AP 8 | ||
100 | #define BM_DRAM_CTL03_AP 0x100 | ||
101 | #define BF_DRAM_CTL03_AP(v) (((v) << 8) & 0x100) | ||
102 | #define BP_DRAM_CTL03_AHB3_W_PRIORITY 0 | ||
103 | #define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x1 | ||
104 | #define BF_DRAM_CTL03_AHB3_W_PRIORITY(v) (((v) << 0) & 0x1) | ||
105 | |||
106 | /** | ||
107 | * Register: HW_DRAM_CTL04 | ||
108 | * Address: 0x10 | ||
109 | * SCT: no | ||
110 | */ | ||
111 | #define HW_DRAM_CTL04 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10)) | ||
112 | #define BP_DRAM_CTL04_DLL_BYPASS_MODE 24 | ||
113 | #define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x1000000 | ||
114 | #define BF_DRAM_CTL04_DLL_BYPASS_MODE(v) (((v) << 24) & 0x1000000) | ||
115 | #define BP_DRAM_CTL04_DLLLOCKREG 16 | ||
116 | #define BM_DRAM_CTL04_DLLLOCKREG 0x10000 | ||
117 | #define BF_DRAM_CTL04_DLLLOCKREG(v) (((v) << 16) & 0x10000) | ||
118 | #define BP_DRAM_CTL04_CONCURRENTAP 8 | ||
119 | #define BM_DRAM_CTL04_CONCURRENTAP 0x100 | ||
120 | #define BF_DRAM_CTL04_CONCURRENTAP(v) (((v) << 8) & 0x100) | ||
121 | #define BP_DRAM_CTL04_BANK_SPLIT_EN 0 | ||
122 | #define BM_DRAM_CTL04_BANK_SPLIT_EN 0x1 | ||
123 | #define BF_DRAM_CTL04_BANK_SPLIT_EN(v) (((v) << 0) & 0x1) | ||
124 | |||
125 | /** | ||
126 | * Register: HW_DRAM_CTL05 | ||
127 | * Address: 0x14 | ||
128 | * SCT: no | ||
129 | */ | ||
130 | #define HW_DRAM_CTL05 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14)) | ||
131 | #define BP_DRAM_CTL05_INTRPTREADA 24 | ||
132 | #define BM_DRAM_CTL05_INTRPTREADA 0x1000000 | ||
133 | #define BF_DRAM_CTL05_INTRPTREADA(v) (((v) << 24) & 0x1000000) | ||
134 | #define BP_DRAM_CTL05_INTRPTAPBURST 16 | ||
135 | #define BM_DRAM_CTL05_INTRPTAPBURST 0x10000 | ||
136 | #define BF_DRAM_CTL05_INTRPTAPBURST(v) (((v) << 16) & 0x10000) | ||
137 | #define BP_DRAM_CTL05_FAST_WRITE 8 | ||
138 | #define BM_DRAM_CTL05_FAST_WRITE 0x100 | ||
139 | #define BF_DRAM_CTL05_FAST_WRITE(v) (((v) << 8) & 0x100) | ||
140 | #define BP_DRAM_CTL05_EN_LOWPOWER_MODE 0 | ||
141 | #define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x1 | ||
142 | #define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v) (((v) << 0) & 0x1) | ||
143 | |||
144 | /** | ||
145 | * Register: HW_DRAM_CTL06 | ||
146 | * Address: 0x18 | ||
147 | * SCT: no | ||
148 | */ | ||
149 | #define HW_DRAM_CTL06 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18)) | ||
150 | #define BP_DRAM_CTL06_POWER_DOWN 24 | ||
151 | #define BM_DRAM_CTL06_POWER_DOWN 0x1000000 | ||
152 | #define BF_DRAM_CTL06_POWER_DOWN(v) (((v) << 24) & 0x1000000) | ||
153 | #define BP_DRAM_CTL06_PLACEMENT_EN 16 | ||
154 | #define BM_DRAM_CTL06_PLACEMENT_EN 0x10000 | ||
155 | #define BF_DRAM_CTL06_PLACEMENT_EN(v) (((v) << 16) & 0x10000) | ||
156 | #define BP_DRAM_CTL06_NO_CMD_INIT 8 | ||
157 | #define BM_DRAM_CTL06_NO_CMD_INIT 0x100 | ||
158 | #define BF_DRAM_CTL06_NO_CMD_INIT(v) (((v) << 8) & 0x100) | ||
159 | #define BP_DRAM_CTL06_INTRPTWRITEA 0 | ||
160 | #define BM_DRAM_CTL06_INTRPTWRITEA 0x1 | ||
161 | #define BF_DRAM_CTL06_INTRPTWRITEA(v) (((v) << 0) & 0x1) | ||
162 | |||
163 | /** | ||
164 | * Register: HW_DRAM_CTL07 | ||
165 | * Address: 0x1c | ||
166 | * SCT: no | ||
167 | */ | ||
168 | #define HW_DRAM_CTL07 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c)) | ||
169 | #define BP_DRAM_CTL07_RW_SAME_EN 24 | ||
170 | #define BM_DRAM_CTL07_RW_SAME_EN 0x1000000 | ||
171 | #define BF_DRAM_CTL07_RW_SAME_EN(v) (((v) << 24) & 0x1000000) | ||
172 | #define BP_DRAM_CTL07_REG_DIMM_ENABLE 16 | ||
173 | #define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x10000 | ||
174 | #define BF_DRAM_CTL07_REG_DIMM_ENABLE(v) (((v) << 16) & 0x10000) | ||
175 | #define BP_DRAM_CTL07_RD2RD_TURN 8 | ||
176 | #define BM_DRAM_CTL07_RD2RD_TURN 0x100 | ||
177 | #define BF_DRAM_CTL07_RD2RD_TURN(v) (((v) << 8) & 0x100) | ||
178 | #define BP_DRAM_CTL07_PRIORITY_EN 0 | ||
179 | #define BM_DRAM_CTL07_PRIORITY_EN 0x1 | ||
180 | #define BF_DRAM_CTL07_PRIORITY_EN(v) (((v) << 0) & 0x1) | ||
181 | |||
182 | /** | ||
183 | * Register: HW_DRAM_CTL08 | ||
184 | * Address: 0x20 | ||
185 | * SCT: no | ||
186 | */ | ||
187 | #define HW_DRAM_CTL08 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20)) | ||
188 | #define BP_DRAM_CTL08_TRAS_LOCKOUT 24 | ||
189 | #define BM_DRAM_CTL08_TRAS_LOCKOUT 0x1000000 | ||
190 | #define BF_DRAM_CTL08_TRAS_LOCKOUT(v) (((v) << 24) & 0x1000000) | ||
191 | #define BP_DRAM_CTL08_START 16 | ||
192 | #define BM_DRAM_CTL08_START 0x10000 | ||
193 | #define BF_DRAM_CTL08_START(v) (((v) << 16) & 0x10000) | ||
194 | #define BP_DRAM_CTL08_SREFRESH 8 | ||
195 | #define BM_DRAM_CTL08_SREFRESH 0x100 | ||
196 | #define BF_DRAM_CTL08_SREFRESH(v) (((v) << 8) & 0x100) | ||
197 | #define BP_DRAM_CTL08_SDR_MODE 0 | ||
198 | #define BM_DRAM_CTL08_SDR_MODE 0x1 | ||
199 | #define BF_DRAM_CTL08_SDR_MODE(v) (((v) << 0) & 0x1) | ||
200 | |||
201 | /** | ||
202 | * Register: HW_DRAM_CTL09 | ||
203 | * Address: 0x24 | ||
204 | * SCT: no | ||
205 | */ | ||
206 | #define HW_DRAM_CTL09 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24)) | ||
207 | #define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24 | ||
208 | #define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x3000000 | ||
209 | #define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) (((v) << 24) & 0x3000000) | ||
210 | #define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16 | ||
211 | #define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x30000 | ||
212 | #define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000) | ||
213 | #define BP_DRAM_CTL09_WRITE_MODEREG 8 | ||
214 | #define BM_DRAM_CTL09_WRITE_MODEREG 0x100 | ||
215 | #define BF_DRAM_CTL09_WRITE_MODEREG(v) (((v) << 8) & 0x100) | ||
216 | #define BP_DRAM_CTL09_WRITEINTERP 0 | ||
217 | #define BM_DRAM_CTL09_WRITEINTERP 0x1 | ||
218 | #define BF_DRAM_CTL09_WRITEINTERP(v) (((v) << 0) & 0x1) | ||
219 | |||
220 | /** | ||
221 | * Register: HW_DRAM_CTL10 | ||
222 | * Address: 0x28 | ||
223 | * SCT: no | ||
224 | */ | ||
225 | #define HW_DRAM_CTL10 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28)) | ||
226 | #define BP_DRAM_CTL10_AGE_COUNT 24 | ||
227 | #define BM_DRAM_CTL10_AGE_COUNT 0x7000000 | ||
228 | #define BF_DRAM_CTL10_AGE_COUNT(v) (((v) << 24) & 0x7000000) | ||
229 | #define BP_DRAM_CTL10_ADDR_PINS 16 | ||
230 | #define BM_DRAM_CTL10_ADDR_PINS 0x70000 | ||
231 | #define BF_DRAM_CTL10_ADDR_PINS(v) (((v) << 16) & 0x70000) | ||
232 | #define BP_DRAM_CTL10_TEMRS 8 | ||
233 | #define BM_DRAM_CTL10_TEMRS 0x300 | ||
234 | #define BF_DRAM_CTL10_TEMRS(v) (((v) << 8) & 0x300) | ||
235 | #define BP_DRAM_CTL10_Q_FULLNESS 0 | ||
236 | #define BM_DRAM_CTL10_Q_FULLNESS 0x3 | ||
237 | #define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3) | ||
238 | |||
239 | /** | ||
240 | * Register: HW_DRAM_CTL11 | ||
241 | * Address: 0x2c | ||
242 | * SCT: no | ||
243 | */ | ||
244 | #define HW_DRAM_CTL11 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c)) | ||
245 | #define BP_DRAM_CTL11_MAX_CS_REG 24 | ||
246 | #define BM_DRAM_CTL11_MAX_CS_REG 0x7000000 | ||
247 | #define BF_DRAM_CTL11_MAX_CS_REG(v) (((v) << 24) & 0x7000000) | ||
248 | #define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16 | ||
249 | #define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x70000 | ||
250 | #define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) (((v) << 16) & 0x70000) | ||
251 | #define BP_DRAM_CTL11_COLUMN_SIZE 8 | ||
252 | #define BM_DRAM_CTL11_COLUMN_SIZE 0x700 | ||
253 | #define BF_DRAM_CTL11_COLUMN_SIZE(v) (((v) << 8) & 0x700) | ||
254 | #define BP_DRAM_CTL11_CASLAT 0 | ||
255 | #define BM_DRAM_CTL11_CASLAT 0x7 | ||
256 | #define BF_DRAM_CTL11_CASLAT(v) (((v) << 0) & 0x7) | ||
257 | |||
258 | /** | ||
259 | * Register: HW_DRAM_CTL12 | ||
260 | * Address: 0x30 | ||
261 | * SCT: no | ||
262 | */ | ||
263 | #define HW_DRAM_CTL12 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30)) | ||
264 | #define BP_DRAM_CTL12_TWR_INT 24 | ||
265 | #define BM_DRAM_CTL12_TWR_INT 0x7000000 | ||
266 | #define BF_DRAM_CTL12_TWR_INT(v) (((v) << 24) & 0x7000000) | ||
267 | #define BP_DRAM_CTL12_TRRD 16 | ||
268 | #define BM_DRAM_CTL12_TRRD 0x70000 | ||
269 | #define BF_DRAM_CTL12_TRRD(v) (((v) << 16) & 0x70000) | ||
270 | #define BP_DRAM_CTL12_TCKE 0 | ||
271 | #define BM_DRAM_CTL12_TCKE 0x7 | ||
272 | #define BF_DRAM_CTL12_TCKE(v) (((v) << 0) & 0x7) | ||
273 | |||
274 | /** | ||
275 | * Register: HW_DRAM_CTL13 | ||
276 | * Address: 0x34 | ||
277 | * SCT: no | ||
278 | */ | ||
279 | #define HW_DRAM_CTL13 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34)) | ||
280 | #define BP_DRAM_CTL13_CASLAT_LIN_GATE 24 | ||
281 | #define BM_DRAM_CTL13_CASLAT_LIN_GATE 0xf000000 | ||
282 | #define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) (((v) << 24) & 0xf000000) | ||
283 | #define BP_DRAM_CTL13_CASLAT_LIN 16 | ||
284 | #define BM_DRAM_CTL13_CASLAT_LIN 0xf0000 | ||
285 | #define BF_DRAM_CTL13_CASLAT_LIN(v) (((v) << 16) & 0xf0000) | ||
286 | #define BP_DRAM_CTL13_APREBIT 8 | ||
287 | #define BM_DRAM_CTL13_APREBIT 0xf00 | ||
288 | #define BF_DRAM_CTL13_APREBIT(v) (((v) << 8) & 0xf00) | ||
289 | #define BP_DRAM_CTL13_TWTR 0 | ||
290 | #define BM_DRAM_CTL13_TWTR 0x7 | ||
291 | #define BF_DRAM_CTL13_TWTR(v) (((v) << 0) & 0x7) | ||
292 | |||
293 | /** | ||
294 | * Register: HW_DRAM_CTL14 | ||
295 | * Address: 0x38 | ||
296 | * SCT: no | ||
297 | */ | ||
298 | #define HW_DRAM_CTL14 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38)) | ||
299 | #define BP_DRAM_CTL14_MAX_COL_REG 24 | ||
300 | #define BM_DRAM_CTL14_MAX_COL_REG 0xf000000 | ||
301 | #define BF_DRAM_CTL14_MAX_COL_REG(v) (((v) << 24) & 0xf000000) | ||
302 | #define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16 | ||
303 | #define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0xf0000 | ||
304 | #define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) (((v) << 16) & 0xf0000) | ||
305 | #define BP_DRAM_CTL14_INITAREF 8 | ||
306 | #define BM_DRAM_CTL14_INITAREF 0xf00 | ||
307 | #define BF_DRAM_CTL14_INITAREF(v) (((v) << 8) & 0xf00) | ||
308 | #define BP_DRAM_CTL14_CS_MAP 0 | ||
309 | #define BM_DRAM_CTL14_CS_MAP 0xf | ||
310 | #define BF_DRAM_CTL14_CS_MAP(v) (((v) << 0) & 0xf) | ||
311 | |||
312 | /** | ||
313 | * Register: HW_DRAM_CTL15 | ||
314 | * Address: 0x3c | ||
315 | * SCT: no | ||
316 | */ | ||
317 | #define HW_DRAM_CTL15 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c)) | ||
318 | #define BP_DRAM_CTL15_TRP 24 | ||
319 | #define BM_DRAM_CTL15_TRP 0xf000000 | ||
320 | #define BF_DRAM_CTL15_TRP(v) (((v) << 24) & 0xf000000) | ||
321 | #define BP_DRAM_CTL15_TDAL 16 | ||
322 | #define BM_DRAM_CTL15_TDAL 0xf0000 | ||
323 | #define BF_DRAM_CTL15_TDAL(v) (((v) << 16) & 0xf0000) | ||
324 | #define BP_DRAM_CTL15_PORT_BUSY 8 | ||
325 | #define BM_DRAM_CTL15_PORT_BUSY 0xf00 | ||
326 | #define BF_DRAM_CTL15_PORT_BUSY(v) (((v) << 8) & 0xf00) | ||
327 | #define BP_DRAM_CTL15_MAX_ROW_REG 0 | ||
328 | #define BM_DRAM_CTL15_MAX_ROW_REG 0xf | ||
329 | #define BF_DRAM_CTL15_MAX_ROW_REG(v) (((v) << 0) & 0xf) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_DRAM_CTL16 | ||
333 | * Address: 0x40 | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_DRAM_CTL16 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40)) | ||
337 | #define BP_DRAM_CTL16_TMRD 24 | ||
338 | #define BM_DRAM_CTL16_TMRD 0x1f000000 | ||
339 | #define BF_DRAM_CTL16_TMRD(v) (((v) << 24) & 0x1f000000) | ||
340 | #define BP_DRAM_CTL16_LOWPOWER_CONTROL 16 | ||
341 | #define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x1f0000 | ||
342 | #define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) (((v) << 16) & 0x1f0000) | ||
343 | #define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8 | ||
344 | #define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x1f00 | ||
345 | #define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) (((v) << 8) & 0x1f00) | ||
346 | #define BP_DRAM_CTL16_INT_ACK 0 | ||
347 | #define BM_DRAM_CTL16_INT_ACK 0xf | ||
348 | #define BF_DRAM_CTL16_INT_ACK(v) (((v) << 0) & 0xf) | ||
349 | |||
350 | /** | ||
351 | * Register: HW_DRAM_CTL17 | ||
352 | * Address: 0x44 | ||
353 | * SCT: no | ||
354 | */ | ||
355 | #define HW_DRAM_CTL17 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44)) | ||
356 | #define BP_DRAM_CTL17_DLL_START_POINT 24 | ||
357 | #define BM_DRAM_CTL17_DLL_START_POINT 0xff000000 | ||
358 | #define BF_DRAM_CTL17_DLL_START_POINT(v) (((v) << 24) & 0xff000000) | ||
359 | #define BP_DRAM_CTL17_DLL_LOCK 16 | ||
360 | #define BM_DRAM_CTL17_DLL_LOCK 0xff0000 | ||
361 | #define BF_DRAM_CTL17_DLL_LOCK(v) (((v) << 16) & 0xff0000) | ||
362 | #define BP_DRAM_CTL17_DLL_INCREMENT 8 | ||
363 | #define BM_DRAM_CTL17_DLL_INCREMENT 0xff00 | ||
364 | #define BF_DRAM_CTL17_DLL_INCREMENT(v) (((v) << 8) & 0xff00) | ||
365 | #define BP_DRAM_CTL17_TRC 0 | ||
366 | #define BM_DRAM_CTL17_TRC 0x1f | ||
367 | #define BF_DRAM_CTL17_TRC(v) (((v) << 0) & 0x1f) | ||
368 | |||
369 | /** | ||
370 | * Register: HW_DRAM_CTL18 | ||
371 | * Address: 0x48 | ||
372 | * SCT: no | ||
373 | */ | ||
374 | #define HW_DRAM_CTL18 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48)) | ||
375 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24 | ||
376 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7f000000 | ||
377 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) (((v) << 24) & 0x7f000000) | ||
378 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16 | ||
379 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x7f0000 | ||
380 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) (((v) << 16) & 0x7f0000) | ||
381 | #define BP_DRAM_CTL18_INT_STATUS 8 | ||
382 | #define BM_DRAM_CTL18_INT_STATUS 0x1f00 | ||
383 | #define BF_DRAM_CTL18_INT_STATUS(v) (((v) << 8) & 0x1f00) | ||
384 | #define BP_DRAM_CTL18_INT_MASK 0 | ||
385 | #define BM_DRAM_CTL18_INT_MASK 0x1f | ||
386 | #define BF_DRAM_CTL18_INT_MASK(v) (((v) << 0) & 0x1f) | ||
387 | |||
388 | /** | ||
389 | * Register: HW_DRAM_CTL19 | ||
390 | * Address: 0x4c | ||
391 | * SCT: no | ||
392 | */ | ||
393 | #define HW_DRAM_CTL19 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c)) | ||
394 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24 | ||
395 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xff000000 | ||
396 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) (((v) << 24) & 0xff000000) | ||
397 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT 16 | ||
398 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x7f0000 | ||
399 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) (((v) << 16) & 0x7f0000) | ||
400 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8 | ||
401 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0xff00 | ||
402 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00) | ||
403 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0 | ||
404 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0xff | ||
405 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff) | ||
406 | |||
407 | /** | ||
408 | * Register: HW_DRAM_CTL20 | ||
409 | * Address: 0x50 | ||
410 | * SCT: no | ||
411 | */ | ||
412 | #define HW_DRAM_CTL20 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50)) | ||
413 | #define BP_DRAM_CTL20_TRCD_INT 24 | ||
414 | #define BM_DRAM_CTL20_TRCD_INT 0xff000000 | ||
415 | #define BF_DRAM_CTL20_TRCD_INT(v) (((v) << 24) & 0xff000000) | ||
416 | #define BP_DRAM_CTL20_TRAS_MIN 16 | ||
417 | #define BM_DRAM_CTL20_TRAS_MIN 0xff0000 | ||
418 | #define BF_DRAM_CTL20_TRAS_MIN(v) (((v) << 16) & 0xff0000) | ||
419 | #define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8 | ||
420 | #define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0xff00 | ||
421 | #define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) (((v) << 8) & 0xff00) | ||
422 | #define BP_DRAM_CTL20_WR_DQS_SHIFT 0 | ||
423 | #define BM_DRAM_CTL20_WR_DQS_SHIFT 0x7f | ||
424 | #define BF_DRAM_CTL20_WR_DQS_SHIFT(v) (((v) << 0) & 0x7f) | ||
425 | |||
426 | /** | ||
427 | * Register: HW_DRAM_CTL21 | ||
428 | * Address: 0x54 | ||
429 | * SCT: no | ||
430 | */ | ||
431 | #define HW_DRAM_CTL21 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54)) | ||
432 | #define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8 | ||
433 | #define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x3ff00 | ||
434 | #define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) (((v) << 8) & 0x3ff00) | ||
435 | #define BP_DRAM_CTL21_TRFC 0 | ||
436 | #define BM_DRAM_CTL21_TRFC 0xff | ||
437 | #define BF_DRAM_CTL21_TRFC(v) (((v) << 0) & 0xff) | ||
438 | |||
439 | /** | ||
440 | * Register: HW_DRAM_CTL22 | ||
441 | * Address: 0x58 | ||
442 | * SCT: no | ||
443 | */ | ||
444 | #define HW_DRAM_CTL22 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58)) | ||
445 | #define BP_DRAM_CTL22_AHB0_WRCNT 16 | ||
446 | #define BM_DRAM_CTL22_AHB0_WRCNT 0x7ff0000 | ||
447 | #define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
448 | #define BP_DRAM_CTL22_AHB0_RDCNT 0 | ||
449 | #define BM_DRAM_CTL22_AHB0_RDCNT 0x7ff | ||
450 | #define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff) | ||
451 | |||
452 | /** | ||
453 | * Register: HW_DRAM_CTL23 | ||
454 | * Address: 0x5c | ||
455 | * SCT: no | ||
456 | */ | ||
457 | #define HW_DRAM_CTL23 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c)) | ||
458 | #define BP_DRAM_CTL23_AHB1_WRCNT 16 | ||
459 | #define BM_DRAM_CTL23_AHB1_WRCNT 0x7ff0000 | ||
460 | #define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
461 | #define BP_DRAM_CTL23_AHB1_RDCNT 0 | ||
462 | #define BM_DRAM_CTL23_AHB1_RDCNT 0x7ff | ||
463 | #define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff) | ||
464 | |||
465 | /** | ||
466 | * Register: HW_DRAM_CTL24 | ||
467 | * Address: 0x60 | ||
468 | * SCT: no | ||
469 | */ | ||
470 | #define HW_DRAM_CTL24 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60)) | ||
471 | #define BP_DRAM_CTL24_AHB2_WRCNT 16 | ||
472 | #define BM_DRAM_CTL24_AHB2_WRCNT 0x7ff0000 | ||
473 | #define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
474 | #define BP_DRAM_CTL24_AHB2_RDCNT 0 | ||
475 | #define BM_DRAM_CTL24_AHB2_RDCNT 0x7ff | ||
476 | #define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff) | ||
477 | |||
478 | /** | ||
479 | * Register: HW_DRAM_CTL25 | ||
480 | * Address: 0x64 | ||
481 | * SCT: no | ||
482 | */ | ||
483 | #define HW_DRAM_CTL25 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64)) | ||
484 | #define BP_DRAM_CTL25_AHB3_WRCNT 16 | ||
485 | #define BM_DRAM_CTL25_AHB3_WRCNT 0x7ff0000 | ||
486 | #define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
487 | #define BP_DRAM_CTL25_AHB3_RDCNT 0 | ||
488 | #define BM_DRAM_CTL25_AHB3_RDCNT 0x7ff | ||
489 | #define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff) | ||
490 | |||
491 | /** | ||
492 | * Register: HW_DRAM_CTL26 | ||
493 | * Address: 0x68 | ||
494 | * SCT: no | ||
495 | */ | ||
496 | #define HW_DRAM_CTL26 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68)) | ||
497 | #define BP_DRAM_CTL26_TREF 0 | ||
498 | #define BM_DRAM_CTL26_TREF 0xfff | ||
499 | #define BF_DRAM_CTL26_TREF(v) (((v) << 0) & 0xfff) | ||
500 | |||
501 | /** | ||
502 | * Register: HW_DRAM_CTL27 | ||
503 | * Address: 0x6c | ||
504 | * SCT: no | ||
505 | */ | ||
506 | #define HW_DRAM_CTL27 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c)) | ||
507 | |||
508 | /** | ||
509 | * Register: HW_DRAM_CTL28 | ||
510 | * Address: 0x70 | ||
511 | * SCT: no | ||
512 | */ | ||
513 | #define HW_DRAM_CTL28 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70)) | ||
514 | |||
515 | /** | ||
516 | * Register: HW_DRAM_CTL29 | ||
517 | * Address: 0x74 | ||
518 | * SCT: no | ||
519 | */ | ||
520 | #define HW_DRAM_CTL29 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74)) | ||
521 | #define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 16 | ||
522 | #define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 0xffff0000 | ||
523 | #define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v) (((v) << 16) & 0xffff0000) | ||
524 | #define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0 | ||
525 | #define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0xffff | ||
526 | #define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v) (((v) << 0) & 0xffff) | ||
527 | |||
528 | /** | ||
529 | * Register: HW_DRAM_CTL30 | ||
530 | * Address: 0x78 | ||
531 | * SCT: no | ||
532 | */ | ||
533 | #define HW_DRAM_CTL30 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78)) | ||
534 | #define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 16 | ||
535 | #define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 0xffff0000 | ||
536 | #define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v) (((v) << 16) & 0xffff0000) | ||
537 | #define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0 | ||
538 | #define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0xffff | ||
539 | #define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v) (((v) << 0) & 0xffff) | ||
540 | |||
541 | /** | ||
542 | * Register: HW_DRAM_CTL31 | ||
543 | * Address: 0x7c | ||
544 | * SCT: no | ||
545 | */ | ||
546 | #define HW_DRAM_CTL31 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c)) | ||
547 | #define BP_DRAM_CTL31_TDLL 16 | ||
548 | #define BM_DRAM_CTL31_TDLL 0xffff0000 | ||
549 | #define BF_DRAM_CTL31_TDLL(v) (((v) << 16) & 0xffff0000) | ||
550 | #define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0 | ||
551 | #define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0xffff | ||
552 | #define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v) (((v) << 0) & 0xffff) | ||
553 | |||
554 | /** | ||
555 | * Register: HW_DRAM_CTL32 | ||
556 | * Address: 0x80 | ||
557 | * SCT: no | ||
558 | */ | ||
559 | #define HW_DRAM_CTL32 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80)) | ||
560 | #define BP_DRAM_CTL32_TXSNR 16 | ||
561 | #define BM_DRAM_CTL32_TXSNR 0xffff0000 | ||
562 | #define BF_DRAM_CTL32_TXSNR(v) (((v) << 16) & 0xffff0000) | ||
563 | #define BP_DRAM_CTL32_TRAS_MAX 0 | ||
564 | #define BM_DRAM_CTL32_TRAS_MAX 0xffff | ||
565 | #define BF_DRAM_CTL32_TRAS_MAX(v) (((v) << 0) & 0xffff) | ||
566 | |||
567 | /** | ||
568 | * Register: HW_DRAM_CTL33 | ||
569 | * Address: 0x84 | ||
570 | * SCT: no | ||
571 | */ | ||
572 | #define HW_DRAM_CTL33 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84)) | ||
573 | #define BP_DRAM_CTL33_VERSION 16 | ||
574 | #define BM_DRAM_CTL33_VERSION 0xffff0000 | ||
575 | #define BF_DRAM_CTL33_VERSION(v) (((v) << 16) & 0xffff0000) | ||
576 | #define BP_DRAM_CTL33_TXSR 0 | ||
577 | #define BM_DRAM_CTL33_TXSR 0xffff | ||
578 | #define BF_DRAM_CTL33_TXSR(v) (((v) << 0) & 0xffff) | ||
579 | |||
580 | /** | ||
581 | * Register: HW_DRAM_CTL34 | ||
582 | * Address: 0x88 | ||
583 | * SCT: no | ||
584 | */ | ||
585 | #define HW_DRAM_CTL34 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88)) | ||
586 | #define BP_DRAM_CTL34_TINIT 0 | ||
587 | #define BM_DRAM_CTL34_TINIT 0xffffff | ||
588 | #define BF_DRAM_CTL34_TINIT(v) (((v) << 0) & 0xffffff) | ||
589 | |||
590 | /** | ||
591 | * Register: HW_DRAM_CTL35 | ||
592 | * Address: 0x8c | ||
593 | * SCT: no | ||
594 | */ | ||
595 | #define HW_DRAM_CTL35 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c)) | ||
596 | #define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR 0 | ||
597 | #define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR 0x7fffffff | ||
598 | #define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v) (((v) << 0) & 0x7fffffff) | ||
599 | |||
600 | /** | ||
601 | * Register: HW_DRAM_CTL36 | ||
602 | * Address: 0x90 | ||
603 | * SCT: no | ||
604 | */ | ||
605 | #define HW_DRAM_CTL36 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90)) | ||
606 | #define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT 24 | ||
607 | #define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT 0x1000000 | ||
608 | #define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v) (((v) << 24) & 0x1000000) | ||
609 | #define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH 16 | ||
610 | #define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH 0x10000 | ||
611 | #define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v) (((v) << 16) & 0x10000) | ||
612 | #define BP_DRAM_CTL36_BUS_SHARE_ENABLE 8 | ||
613 | #define BM_DRAM_CTL36_BUS_SHARE_ENABLE 0x100 | ||
614 | #define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v) (((v) << 8) & 0x100) | ||
615 | #define BP_DRAM_CTL36_ACTIVE_AGING 0 | ||
616 | #define BM_DRAM_CTL36_ACTIVE_AGING 0x1 | ||
617 | #define BF_DRAM_CTL36_ACTIVE_AGING(v) (((v) << 0) & 0x1) | ||
618 | |||
619 | /** | ||
620 | * Register: HW_DRAM_CTL37 | ||
621 | * Address: 0x94 | ||
622 | * SCT: no | ||
623 | */ | ||
624 | #define HW_DRAM_CTL37 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94)) | ||
625 | #define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT 8 | ||
626 | #define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT 0x3ff00 | ||
627 | #define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v) (((v) << 8) & 0x3ff00) | ||
628 | #define BP_DRAM_CTL37_TREF_ENABLE 0 | ||
629 | #define BM_DRAM_CTL37_TREF_ENABLE 0x1 | ||
630 | #define BF_DRAM_CTL37_TREF_ENABLE(v) (((v) << 0) & 0x1) | ||
631 | |||
632 | /** | ||
633 | * Register: HW_DRAM_CTL38 | ||
634 | * Address: 0x98 | ||
635 | * SCT: no | ||
636 | */ | ||
637 | #define HW_DRAM_CTL38 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98)) | ||
638 | #define BP_DRAM_CTL38_EMRS2_DATA_0 16 | ||
639 | #define BM_DRAM_CTL38_EMRS2_DATA_0 0x1fff0000 | ||
640 | #define BF_DRAM_CTL38_EMRS2_DATA_0(v) (((v) << 16) & 0x1fff0000) | ||
641 | #define BP_DRAM_CTL38_EMRS1_DATA 0 | ||
642 | #define BM_DRAM_CTL38_EMRS1_DATA 0x1fff | ||
643 | #define BF_DRAM_CTL38_EMRS1_DATA(v) (((v) << 0) & 0x1fff) | ||
644 | |||
645 | /** | ||
646 | * Register: HW_DRAM_CTL39 | ||
647 | * Address: 0x9c | ||
648 | * SCT: no | ||
649 | */ | ||
650 | #define HW_DRAM_CTL39 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c)) | ||
651 | #define BP_DRAM_CTL39_EMRS2_DATA_2 16 | ||
652 | #define BM_DRAM_CTL39_EMRS2_DATA_2 0x1fff0000 | ||
653 | #define BF_DRAM_CTL39_EMRS2_DATA_2(v) (((v) << 16) & 0x1fff0000) | ||
654 | #define BP_DRAM_CTL39_EMRS2_DATA_1 0 | ||
655 | #define BM_DRAM_CTL39_EMRS2_DATA_1 0x1fff | ||
656 | #define BF_DRAM_CTL39_EMRS2_DATA_1(v) (((v) << 0) & 0x1fff) | ||
657 | |||
658 | /** | ||
659 | * Register: HW_DRAM_CTL40 | ||
660 | * Address: 0xa0 | ||
661 | * SCT: no | ||
662 | */ | ||
663 | #define HW_DRAM_CTL40 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0)) | ||
664 | #define BP_DRAM_CTL40_TPDEX 16 | ||
665 | #define BM_DRAM_CTL40_TPDEX 0xffff0000 | ||
666 | #define BF_DRAM_CTL40_TPDEX(v) (((v) << 16) & 0xffff0000) | ||
667 | #define BP_DRAM_CTL40_EMRS2_DATA_3 0 | ||
668 | #define BM_DRAM_CTL40_EMRS2_DATA_3 0x1fff | ||
669 | #define BF_DRAM_CTL40_EMRS2_DATA_3(v) (((v) << 0) & 0x1fff) | ||
670 | |||
671 | #endif /* __HEADERGEN__STMP3700__DRAM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h new file mode 100644 index 0000000000..a3ae0f52d1 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h | |||
@@ -0,0 +1,274 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__DRI__H__ | ||
24 | #define __HEADERGEN__STMP3700__DRI__H__ | ||
25 | |||
26 | #define REGS_DRI_BASE (0x80074000) | ||
27 | |||
28 | #define REGS_DRI_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DRI_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DRI_CTRL_SFTRST 31 | ||
40 | #define BM_DRI_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_DRI_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_DRI_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_DRI_CTRL_CLKGATE 30 | ||
46 | #define BM_DRI_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_DRI_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_DRI_CTRL_ENABLE_INPUTS 29 | ||
52 | #define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 | ||
53 | #define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0 | ||
54 | #define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1 | ||
55 | #define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000) | ||
57 | #define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26 | ||
58 | #define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000 | ||
59 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0 | ||
60 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1 | ||
61 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000) | ||
62 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000) | ||
63 | #define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25 | ||
64 | #define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000 | ||
65 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0 | ||
66 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1 | ||
67 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000) | ||
68 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000) | ||
69 | #define BP_DRI_CTRL_DMA_DELAY_COUNT 16 | ||
70 | #define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000 | ||
71 | #define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000) | ||
72 | #define BP_DRI_CTRL_REACQUIRE_PHASE 15 | ||
73 | #define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000 | ||
74 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0 | ||
75 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1 | ||
76 | #define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000) | ||
77 | #define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000) | ||
78 | #define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11 | ||
79 | #define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800 | ||
80 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0 | ||
81 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1 | ||
82 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800) | ||
83 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800) | ||
84 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10 | ||
85 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400 | ||
86 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0 | ||
87 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1 | ||
88 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
89 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
90 | #define BP_DRI_CTRL_ATTENTION_IRQ_EN 9 | ||
91 | #define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200 | ||
92 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0 | ||
93 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1 | ||
94 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200) | ||
95 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200) | ||
96 | #define BP_DRI_CTRL_OVERFLOW_IRQ 3 | ||
97 | #define BM_DRI_CTRL_OVERFLOW_IRQ 0x8 | ||
98 | #define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
99 | #define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1 | ||
100 | #define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
101 | #define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8) | ||
102 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2 | ||
103 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4 | ||
104 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0 | ||
105 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1 | ||
106 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
107 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4) | ||
108 | #define BP_DRI_CTRL_ATTENTION_IRQ 1 | ||
109 | #define BM_DRI_CTRL_ATTENTION_IRQ 0x2 | ||
110 | #define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0 | ||
111 | #define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1 | ||
112 | #define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2) | ||
113 | #define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2) | ||
114 | #define BP_DRI_CTRL_RUN 0 | ||
115 | #define BM_DRI_CTRL_RUN 0x1 | ||
116 | #define BV_DRI_CTRL_RUN__HALT 0x0 | ||
117 | #define BV_DRI_CTRL_RUN__RUN 0x1 | ||
118 | #define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
119 | #define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1) | ||
120 | |||
121 | /** | ||
122 | * Register: HW_DRI_TIMING | ||
123 | * Address: 0x10 | ||
124 | * SCT: no | ||
125 | */ | ||
126 | #define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10)) | ||
127 | #define BP_DRI_TIMING_PILOT_REP_RATE 16 | ||
128 | #define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000 | ||
129 | #define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000) | ||
130 | #define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 | ||
131 | #define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff | ||
132 | #define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff) | ||
133 | |||
134 | /** | ||
135 | * Register: HW_DRI_STAT | ||
136 | * Address: 0x20 | ||
137 | * SCT: no | ||
138 | */ | ||
139 | #define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20)) | ||
140 | #define BP_DRI_STAT_DRI_PRESENT 31 | ||
141 | #define BM_DRI_STAT_DRI_PRESENT 0x80000000 | ||
142 | #define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0 | ||
143 | #define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1 | ||
144 | #define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000) | ||
145 | #define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000) | ||
146 | #define BP_DRI_STAT_PILOT_PHASE 16 | ||
147 | #define BM_DRI_STAT_PILOT_PHASE 0xf0000 | ||
148 | #define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000) | ||
149 | #define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3 | ||
150 | #define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8 | ||
151 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
152 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1 | ||
153 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
154 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8) | ||
155 | #define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2 | ||
156 | #define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4 | ||
157 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
158 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
159 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
160 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
161 | #define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1 | ||
162 | #define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2 | ||
163 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
164 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1 | ||
165 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
166 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2) | ||
167 | |||
168 | /** | ||
169 | * Register: HW_DRI_DATA | ||
170 | * Address: 0x30 | ||
171 | * SCT: no | ||
172 | */ | ||
173 | #define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30)) | ||
174 | #define BP_DRI_DATA_DATA 0 | ||
175 | #define BM_DRI_DATA_DATA 0xffffffff | ||
176 | #define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
177 | |||
178 | /** | ||
179 | * Register: HW_DRI_DEBUG0 | ||
180 | * Address: 0x40 | ||
181 | * SCT: yes | ||
182 | */ | ||
183 | #define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0)) | ||
184 | #define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4)) | ||
185 | #define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8)) | ||
186 | #define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc)) | ||
187 | #define BP_DRI_DEBUG0_DMAREQ 31 | ||
188 | #define BM_DRI_DEBUG0_DMAREQ 0x80000000 | ||
189 | #define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
190 | #define BP_DRI_DEBUG0_DMACMDKICK 30 | ||
191 | #define BM_DRI_DEBUG0_DMACMDKICK 0x40000000 | ||
192 | #define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000) | ||
193 | #define BP_DRI_DEBUG0_DRI_CLK_INPUT 29 | ||
194 | #define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000 | ||
195 | #define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000) | ||
196 | #define BP_DRI_DEBUG0_DRI_DATA_INPUT 28 | ||
197 | #define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000 | ||
198 | #define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000) | ||
199 | #define BP_DRI_DEBUG0_TEST_MODE 27 | ||
200 | #define BM_DRI_DEBUG0_TEST_MODE 0x8000000 | ||
201 | #define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000) | ||
202 | #define BP_DRI_DEBUG0_PILOT_REP_RATE 26 | ||
203 | #define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000 | ||
204 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0 | ||
205 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1 | ||
206 | #define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000) | ||
207 | #define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000) | ||
208 | #define BP_DRI_DEBUG0_SPARE 18 | ||
209 | #define BM_DRI_DEBUG0_SPARE 0x3fc0000 | ||
210 | #define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000) | ||
211 | #define BP_DRI_DEBUG0_FRAME 0 | ||
212 | #define BM_DRI_DEBUG0_FRAME 0x3ffff | ||
213 | #define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff) | ||
214 | |||
215 | /** | ||
216 | * Register: HW_DRI_DEBUG1 | ||
217 | * Address: 0x50 | ||
218 | * SCT: yes | ||
219 | */ | ||
220 | #define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0)) | ||
221 | #define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4)) | ||
222 | #define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8)) | ||
223 | #define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc)) | ||
224 | #define BP_DRI_DEBUG1_INVERT_PILOT 31 | ||
225 | #define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000 | ||
226 | #define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0 | ||
227 | #define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1 | ||
228 | #define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000) | ||
229 | #define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000) | ||
230 | #define BP_DRI_DEBUG1_INVERT_ATTENTION 30 | ||
231 | #define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000 | ||
232 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0 | ||
233 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1 | ||
234 | #define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000) | ||
235 | #define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000) | ||
236 | #define BP_DRI_DEBUG1_INVERT_DRI_DATA 29 | ||
237 | #define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000 | ||
238 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0 | ||
239 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1 | ||
240 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000) | ||
241 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000) | ||
242 | #define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28 | ||
243 | #define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000 | ||
244 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0 | ||
245 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1 | ||
246 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000) | ||
247 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000) | ||
248 | #define BP_DRI_DEBUG1_REVERSE_FRAME 27 | ||
249 | #define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000 | ||
250 | #define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0 | ||
251 | #define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1 | ||
252 | #define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000) | ||
253 | #define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000) | ||
254 | #define BP_DRI_DEBUG1_SWIZZLED_FRAME 0 | ||
255 | #define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff | ||
256 | #define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff) | ||
257 | |||
258 | /** | ||
259 | * Register: HW_DRI_VERSION | ||
260 | * Address: 0x60 | ||
261 | * SCT: no | ||
262 | */ | ||
263 | #define HW_DRI_VERSION (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60)) | ||
264 | #define BP_DRI_VERSION_MAJOR 24 | ||
265 | #define BM_DRI_VERSION_MAJOR 0xff000000 | ||
266 | #define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
267 | #define BP_DRI_VERSION_MINOR 16 | ||
268 | #define BM_DRI_VERSION_MINOR 0xff0000 | ||
269 | #define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
270 | #define BP_DRI_VERSION_STEP 0 | ||
271 | #define BM_DRI_VERSION_STEP 0xffff | ||
272 | #define BF_DRI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
273 | |||
274 | #endif /* __HEADERGEN__STMP3700__DRI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h new file mode 100644 index 0000000000..e84274169e --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h | |||
@@ -0,0 +1,387 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__ECC8__H__ | ||
24 | #define __HEADERGEN__STMP3700__ECC8__H__ | ||
25 | |||
26 | #define REGS_ECC8_BASE (0x80008000) | ||
27 | |||
28 | #define REGS_ECC8_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ECC8_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_ECC8_CTRL (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x0)) | ||
36 | #define HW_ECC8_CTRL_SET (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x4)) | ||
37 | #define HW_ECC8_CTRL_CLR (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x8)) | ||
38 | #define HW_ECC8_CTRL_TOG (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0xc)) | ||
39 | #define BP_ECC8_CTRL_SFTRST 31 | ||
40 | #define BM_ECC8_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_ECC8_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_ECC8_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_ECC8_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_ECC8_CTRL_SFTRST_V(v) ((BV_ECC8_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_ECC8_CTRL_CLKGATE 30 | ||
46 | #define BM_ECC8_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_ECC8_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_ECC8_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_ECC8_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_ECC8_CTRL_CLKGATE_V(v) ((BV_ECC8_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_ECC8_CTRL_AHBM_SFTRST 29 | ||
52 | #define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 | ||
53 | #define BV_ECC8_CTRL_AHBM_SFTRST__RUN 0x0 | ||
54 | #define BV_ECC8_CTRL_AHBM_SFTRST__RESET 0x1 | ||
55 | #define BF_ECC8_CTRL_AHBM_SFTRST(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_ECC8_CTRL_AHBM_SFTRST_V(v) ((BV_ECC8_CTRL_AHBM_SFTRST__##v << 29) & 0x20000000) | ||
57 | #define BP_ECC8_CTRL_THROTTLE 24 | ||
58 | #define BM_ECC8_CTRL_THROTTLE 0xf000000 | ||
59 | #define BF_ECC8_CTRL_THROTTLE(v) (((v) << 24) & 0xf000000) | ||
60 | #define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN 10 | ||
61 | #define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN 0x400 | ||
62 | #define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v) (((v) << 10) & 0x400) | ||
63 | #define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN 9 | ||
64 | #define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN 0x200 | ||
65 | #define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v) (((v) << 9) & 0x200) | ||
66 | #define BP_ECC8_CTRL_COMPLETE_IRQ_EN 8 | ||
67 | #define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x100 | ||
68 | #define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
69 | #define BP_ECC8_CTRL_BM_ERROR_IRQ 3 | ||
70 | #define BM_ECC8_CTRL_BM_ERROR_IRQ 0x8 | ||
71 | #define BF_ECC8_CTRL_BM_ERROR_IRQ(v) (((v) << 3) & 0x8) | ||
72 | #define BP_ECC8_CTRL_DEBUG_STALL_IRQ 2 | ||
73 | #define BM_ECC8_CTRL_DEBUG_STALL_IRQ 0x4 | ||
74 | #define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v) (((v) << 2) & 0x4) | ||
75 | #define BP_ECC8_CTRL_DEBUG_WRITE_IRQ 1 | ||
76 | #define BM_ECC8_CTRL_DEBUG_WRITE_IRQ 0x2 | ||
77 | #define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v) (((v) << 1) & 0x2) | ||
78 | #define BP_ECC8_CTRL_COMPLETE_IRQ 0 | ||
79 | #define BM_ECC8_CTRL_COMPLETE_IRQ 0x1 | ||
80 | #define BF_ECC8_CTRL_COMPLETE_IRQ(v) (((v) << 0) & 0x1) | ||
81 | |||
82 | /** | ||
83 | * Register: HW_ECC8_STATUS0 | ||
84 | * Address: 0x10 | ||
85 | * SCT: no | ||
86 | */ | ||
87 | #define HW_ECC8_STATUS0 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x10)) | ||
88 | #define BP_ECC8_STATUS0_HANDLE 16 | ||
89 | #define BM_ECC8_STATUS0_HANDLE 0xffff0000 | ||
90 | #define BF_ECC8_STATUS0_HANDLE(v) (((v) << 16) & 0xffff0000) | ||
91 | #define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT 15 | ||
92 | #define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT 0x8000 | ||
93 | #define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v) (((v) << 15) & 0x8000) | ||
94 | #define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT 14 | ||
95 | #define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT 0x4000 | ||
96 | #define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v) (((v) << 14) & 0x4000) | ||
97 | #define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT 13 | ||
98 | #define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT 0x2000 | ||
99 | #define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v) (((v) << 13) & 0x2000) | ||
100 | #define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT 12 | ||
101 | #define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT 0x1000 | ||
102 | #define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v) (((v) << 12) & 0x1000) | ||
103 | #define BP_ECC8_STATUS0_STATUS_AUX 8 | ||
104 | #define BM_ECC8_STATUS0_STATUS_AUX 0xf00 | ||
105 | #define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS 0x0 | ||
106 | #define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE 0x1 | ||
107 | #define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE 0x2 | ||
108 | #define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE 0x3 | ||
109 | #define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE 0x4 | ||
110 | #define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED 0xc | ||
111 | #define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE 0xe | ||
112 | #define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES 0xf | ||
113 | #define BF_ECC8_STATUS0_STATUS_AUX(v) (((v) << 8) & 0xf00) | ||
114 | #define BF_ECC8_STATUS0_STATUS_AUX_V(v) ((BV_ECC8_STATUS0_STATUS_AUX__##v << 8) & 0xf00) | ||
115 | #define BP_ECC8_STATUS0_ALLONES 4 | ||
116 | #define BM_ECC8_STATUS0_ALLONES 0x10 | ||
117 | #define BF_ECC8_STATUS0_ALLONES(v) (((v) << 4) & 0x10) | ||
118 | #define BP_ECC8_STATUS0_CORRECTED 3 | ||
119 | #define BM_ECC8_STATUS0_CORRECTED 0x8 | ||
120 | #define BF_ECC8_STATUS0_CORRECTED(v) (((v) << 3) & 0x8) | ||
121 | #define BP_ECC8_STATUS0_UNCORRECTABLE 2 | ||
122 | #define BM_ECC8_STATUS0_UNCORRECTABLE 0x4 | ||
123 | #define BF_ECC8_STATUS0_UNCORRECTABLE(v) (((v) << 2) & 0x4) | ||
124 | #define BP_ECC8_STATUS0_COMPLETED_CE 0 | ||
125 | #define BM_ECC8_STATUS0_COMPLETED_CE 0x3 | ||
126 | #define BF_ECC8_STATUS0_COMPLETED_CE(v) (((v) << 0) & 0x3) | ||
127 | |||
128 | /** | ||
129 | * Register: HW_ECC8_STATUS1 | ||
130 | * Address: 0x20 | ||
131 | * SCT: no | ||
132 | */ | ||
133 | #define HW_ECC8_STATUS1 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x20)) | ||
134 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD7 28 | ||
135 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD7 0xf0000000 | ||
136 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS 0x0 | ||
137 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE 0x1 | ||
138 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE 0x2 | ||
139 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE 0x3 | ||
140 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE 0x4 | ||
141 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE 0x5 | ||
142 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE 0x6 | ||
143 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE 0x7 | ||
144 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE 0x8 | ||
145 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED 0xc | ||
146 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE 0xe | ||
147 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES 0xf | ||
148 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v) (((v) << 28) & 0xf0000000) | ||
149 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD7__##v << 28) & 0xf0000000) | ||
150 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD6 24 | ||
151 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD6 0xf000000 | ||
152 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS 0x0 | ||
153 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE 0x1 | ||
154 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE 0x2 | ||
155 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE 0x3 | ||
156 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE 0x4 | ||
157 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE 0x5 | ||
158 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE 0x6 | ||
159 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE 0x7 | ||
160 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE 0x8 | ||
161 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED 0xc | ||
162 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE 0xe | ||
163 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES 0xf | ||
164 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v) (((v) << 24) & 0xf000000) | ||
165 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD6__##v << 24) & 0xf000000) | ||
166 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD5 20 | ||
167 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD5 0xf00000 | ||
168 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS 0x0 | ||
169 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE 0x1 | ||
170 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE 0x2 | ||
171 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE 0x3 | ||
172 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE 0x4 | ||
173 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE 0x5 | ||
174 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE 0x6 | ||
175 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE 0x7 | ||
176 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE 0x8 | ||
177 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED 0xc | ||
178 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE 0xe | ||
179 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES 0xf | ||
180 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v) (((v) << 20) & 0xf00000) | ||
181 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD5__##v << 20) & 0xf00000) | ||
182 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD4 16 | ||
183 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD4 0xf0000 | ||
184 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS 0x0 | ||
185 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE 0x1 | ||
186 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE 0x2 | ||
187 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE 0x3 | ||
188 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE 0x4 | ||
189 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE 0x5 | ||
190 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE 0x6 | ||
191 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE 0x7 | ||
192 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE 0x8 | ||
193 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED 0xc | ||
194 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE 0xe | ||
195 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES 0xf | ||
196 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v) (((v) << 16) & 0xf0000) | ||
197 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD4__##v << 16) & 0xf0000) | ||
198 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD3 12 | ||
199 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD3 0xf000 | ||
200 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS 0x0 | ||
201 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE 0x1 | ||
202 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE 0x2 | ||
203 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE 0x3 | ||
204 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE 0x4 | ||
205 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE 0x5 | ||
206 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE 0x6 | ||
207 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE 0x7 | ||
208 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE 0x8 | ||
209 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED 0xc | ||
210 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE 0xe | ||
211 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES 0xf | ||
212 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v) (((v) << 12) & 0xf000) | ||
213 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD3__##v << 12) & 0xf000) | ||
214 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD2 8 | ||
215 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD2 0xf00 | ||
216 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS 0x0 | ||
217 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE 0x1 | ||
218 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE 0x2 | ||
219 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE 0x3 | ||
220 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE 0x4 | ||
221 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE 0x5 | ||
222 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE 0x6 | ||
223 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE 0x7 | ||
224 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE 0x8 | ||
225 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED 0xc | ||
226 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE 0xe | ||
227 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES 0xf | ||
228 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v) (((v) << 8) & 0xf00) | ||
229 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD2__##v << 8) & 0xf00) | ||
230 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD1 4 | ||
231 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD1 0xf0 | ||
232 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS 0x0 | ||
233 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE 0x1 | ||
234 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE 0x2 | ||
235 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE 0x3 | ||
236 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE 0x4 | ||
237 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE 0x5 | ||
238 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE 0x6 | ||
239 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE 0x7 | ||
240 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE 0x8 | ||
241 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED 0xc | ||
242 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE 0xe | ||
243 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES 0xf | ||
244 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v) (((v) << 4) & 0xf0) | ||
245 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD1__##v << 4) & 0xf0) | ||
246 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD0 0 | ||
247 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD0 0xf | ||
248 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS 0x0 | ||
249 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE 0x1 | ||
250 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE 0x2 | ||
251 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE 0x3 | ||
252 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE 0x4 | ||
253 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE 0x5 | ||
254 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE 0x6 | ||
255 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE 0x7 | ||
256 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE 0x8 | ||
257 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED 0xc | ||
258 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE 0xe | ||
259 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES 0xf | ||
260 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v) (((v) << 0) & 0xf) | ||
261 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD0__##v << 0) & 0xf) | ||
262 | |||
263 | /** | ||
264 | * Register: HW_ECC8_DEBUG0 | ||
265 | * Address: 0x30 | ||
266 | * SCT: yes | ||
267 | */ | ||
268 | #define HW_ECC8_DEBUG0 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x0)) | ||
269 | #define HW_ECC8_DEBUG0_SET (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x4)) | ||
270 | #define HW_ECC8_DEBUG0_CLR (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x8)) | ||
271 | #define HW_ECC8_DEBUG0_TOG (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0xc)) | ||
272 | #define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 | ||
273 | #define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x1ff0000 | ||
274 | #define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 | ||
275 | #define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 | ||
276 | #define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << 16) & 0x1ff0000) | ||
277 | #define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000) | ||
278 | #define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND 15 | ||
279 | #define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND 0x8000 | ||
280 | #define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v) (((v) << 15) & 0x8000) | ||
281 | #define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 14 | ||
282 | #define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x4000 | ||
283 | #define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 | ||
284 | #define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 | ||
285 | #define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) (((v) << 14) & 0x4000) | ||
286 | #define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000) | ||
287 | #define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K 13 | ||
288 | #define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K 0x2000 | ||
289 | #define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 | ||
290 | #define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 | ||
291 | #define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v) (((v) << 13) & 0x2000) | ||
292 | #define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000) | ||
293 | #define BP_ECC8_DEBUG0_KES_DEBUG_KICK 12 | ||
294 | #define BM_ECC8_DEBUG0_KES_DEBUG_KICK 0x1000 | ||
295 | #define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v) (((v) << 12) & 0x1000) | ||
296 | #define BP_ECC8_DEBUG0_KES_STANDALONE 11 | ||
297 | #define BM_ECC8_DEBUG0_KES_STANDALONE 0x800 | ||
298 | #define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL 0x0 | ||
299 | #define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 | ||
300 | #define BF_ECC8_DEBUG0_KES_STANDALONE(v) (((v) << 11) & 0x800) | ||
301 | #define BF_ECC8_DEBUG0_KES_STANDALONE_V(v) ((BV_ECC8_DEBUG0_KES_STANDALONE__##v << 11) & 0x800) | ||
302 | #define BP_ECC8_DEBUG0_KES_DEBUG_STEP 10 | ||
303 | #define BM_ECC8_DEBUG0_KES_DEBUG_STEP 0x400 | ||
304 | #define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v) (((v) << 10) & 0x400) | ||
305 | #define BP_ECC8_DEBUG0_KES_DEBUG_STALL 9 | ||
306 | #define BM_ECC8_DEBUG0_KES_DEBUG_STALL 0x200 | ||
307 | #define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 | ||
308 | #define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 | ||
309 | #define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v) (((v) << 9) & 0x200) | ||
310 | #define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200) | ||
311 | #define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS 8 | ||
312 | #define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS 0x100 | ||
313 | #define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 | ||
314 | #define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 | ||
315 | #define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v) (((v) << 8) & 0x100) | ||
316 | #define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v) ((BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100) | ||
317 | #define BP_ECC8_DEBUG0_DEBUG_REG_SELECT 0 | ||
318 | #define BM_ECC8_DEBUG0_DEBUG_REG_SELECT 0x3f | ||
319 | #define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v) (((v) << 0) & 0x3f) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_ECC8_DBGKESREAD | ||
323 | * Address: 0x40 | ||
324 | * SCT: no | ||
325 | */ | ||
326 | #define HW_ECC8_DBGKESREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x40)) | ||
327 | #define BP_ECC8_DBGKESREAD_VALUES 0 | ||
328 | #define BM_ECC8_DBGKESREAD_VALUES 0xffffffff | ||
329 | #define BF_ECC8_DBGKESREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_ECC8_DBGCSFEREAD | ||
333 | * Address: 0x50 | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_ECC8_DBGCSFEREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x50)) | ||
337 | #define BP_ECC8_DBGCSFEREAD_VALUES 0 | ||
338 | #define BM_ECC8_DBGCSFEREAD_VALUES 0xffffffff | ||
339 | #define BF_ECC8_DBGCSFEREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
340 | |||
341 | /** | ||
342 | * Register: HW_ECC8_DBGSYNDGENREAD | ||
343 | * Address: 0x60 | ||
344 | * SCT: no | ||
345 | */ | ||
346 | #define HW_ECC8_DBGSYNDGENREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x60)) | ||
347 | #define BP_ECC8_DBGSYNDGENREAD_VALUES 0 | ||
348 | #define BM_ECC8_DBGSYNDGENREAD_VALUES 0xffffffff | ||
349 | #define BF_ECC8_DBGSYNDGENREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
350 | |||
351 | /** | ||
352 | * Register: HW_ECC8_DBGAHBMREAD | ||
353 | * Address: 0x70 | ||
354 | * SCT: no | ||
355 | */ | ||
356 | #define HW_ECC8_DBGAHBMREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x70)) | ||
357 | #define BP_ECC8_DBGAHBMREAD_VALUES 0 | ||
358 | #define BM_ECC8_DBGAHBMREAD_VALUES 0xffffffff | ||
359 | #define BF_ECC8_DBGAHBMREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
360 | |||
361 | /** | ||
362 | * Register: HW_ECC8_BLOCKNAME | ||
363 | * Address: 0x80 | ||
364 | * SCT: no | ||
365 | */ | ||
366 | #define HW_ECC8_BLOCKNAME (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x80)) | ||
367 | #define BP_ECC8_BLOCKNAME_NAME 0 | ||
368 | #define BM_ECC8_BLOCKNAME_NAME 0xffffffff | ||
369 | #define BF_ECC8_BLOCKNAME_NAME(v) (((v) << 0) & 0xffffffff) | ||
370 | |||
371 | /** | ||
372 | * Register: HW_ECC8_VERSION | ||
373 | * Address: 0xa0 | ||
374 | * SCT: no | ||
375 | */ | ||
376 | #define HW_ECC8_VERSION (*(volatile unsigned long *)(REGS_ECC8_BASE + 0xa0)) | ||
377 | #define BP_ECC8_VERSION_MAJOR 24 | ||
378 | #define BM_ECC8_VERSION_MAJOR 0xff000000 | ||
379 | #define BF_ECC8_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
380 | #define BP_ECC8_VERSION_MINOR 16 | ||
381 | #define BM_ECC8_VERSION_MINOR 0xff0000 | ||
382 | #define BF_ECC8_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
383 | #define BP_ECC8_VERSION_STEP 0 | ||
384 | #define BM_ECC8_VERSION_STEP 0xffff | ||
385 | #define BF_ECC8_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
386 | |||
387 | #endif /* __HEADERGEN__STMP3700__ECC8__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h new file mode 100644 index 0000000000..b81fb35313 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h | |||
@@ -0,0 +1,196 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__EMI__H__ | ||
24 | #define __HEADERGEN__STMP3700__EMI__H__ | ||
25 | |||
26 | #define REGS_EMI_BASE (0x80020000) | ||
27 | |||
28 | #define REGS_EMI_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_EMI_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_EMI_CTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_EMI_CTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_EMI_CTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_EMI_CTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_EMI_CTRL_SFTRST 31 | ||
40 | #define BM_EMI_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_EMI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_EMI_CTRL_CLKGATE 30 | ||
43 | #define BM_EMI_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_EMI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_EMI_CTRL_MEM_WIDTH 6 | ||
46 | #define BM_EMI_CTRL_MEM_WIDTH 0x40 | ||
47 | #define BF_EMI_CTRL_MEM_WIDTH(v) (((v) << 6) & 0x40) | ||
48 | #define BP_EMI_CTRL_WRITE_PROTECT 5 | ||
49 | #define BM_EMI_CTRL_WRITE_PROTECT 0x20 | ||
50 | #define BF_EMI_CTRL_WRITE_PROTECT(v) (((v) << 5) & 0x20) | ||
51 | #define BP_EMI_CTRL_RESET_OUT 4 | ||
52 | #define BM_EMI_CTRL_RESET_OUT 0x10 | ||
53 | #define BF_EMI_CTRL_RESET_OUT(v) (((v) << 4) & 0x10) | ||
54 | #define BP_EMI_CTRL_CE_SELECT 0 | ||
55 | #define BM_EMI_CTRL_CE_SELECT 0xf | ||
56 | #define BV_EMI_CTRL_CE_SELECT__NONE 0x0 | ||
57 | #define BV_EMI_CTRL_CE_SELECT__CE0 0x1 | ||
58 | #define BV_EMI_CTRL_CE_SELECT__CE1 0x2 | ||
59 | #define BV_EMI_CTRL_CE_SELECT__CE2 0x4 | ||
60 | #define BV_EMI_CTRL_CE_SELECT__CE3 0x8 | ||
61 | #define BF_EMI_CTRL_CE_SELECT(v) (((v) << 0) & 0xf) | ||
62 | #define BF_EMI_CTRL_CE_SELECT_V(v) ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf) | ||
63 | |||
64 | /** | ||
65 | * Register: HW_EMI_STAT | ||
66 | * Address: 0x10 | ||
67 | * SCT: no | ||
68 | */ | ||
69 | #define HW_EMI_STAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10)) | ||
70 | #define BP_EMI_STAT_DRAM_PRESENT 31 | ||
71 | #define BM_EMI_STAT_DRAM_PRESENT 0x80000000 | ||
72 | #define BF_EMI_STAT_DRAM_PRESENT(v) (((v) << 31) & 0x80000000) | ||
73 | #define BP_EMI_STAT_NOR_PRESENT 30 | ||
74 | #define BM_EMI_STAT_NOR_PRESENT 0x40000000 | ||
75 | #define BF_EMI_STAT_NOR_PRESENT(v) (((v) << 30) & 0x40000000) | ||
76 | #define BP_EMI_STAT_LARGE_DRAM_ENABLED 29 | ||
77 | #define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000 | ||
78 | #define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) << 29) & 0x20000000) | ||
79 | #define BP_EMI_STAT_DRAM_HALTED 1 | ||
80 | #define BM_EMI_STAT_DRAM_HALTED 0x2 | ||
81 | #define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0 | ||
82 | #define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1 | ||
83 | #define BF_EMI_STAT_DRAM_HALTED(v) (((v) << 1) & 0x2) | ||
84 | #define BF_EMI_STAT_DRAM_HALTED_V(v) ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2) | ||
85 | #define BP_EMI_STAT_NOR_BUSY 0 | ||
86 | #define BM_EMI_STAT_NOR_BUSY 0x1 | ||
87 | #define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0 | ||
88 | #define BV_EMI_STAT_NOR_BUSY__BUSY 0x1 | ||
89 | #define BF_EMI_STAT_NOR_BUSY(v) (((v) << 0) & 0x1) | ||
90 | #define BF_EMI_STAT_NOR_BUSY_V(v) ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_EMI_TIME | ||
94 | * Address: 0x20 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_EMI_TIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0)) | ||
98 | #define HW_EMI_TIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4)) | ||
99 | #define HW_EMI_TIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8)) | ||
100 | #define HW_EMI_TIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc)) | ||
101 | #define BP_EMI_TIME_THZ 24 | ||
102 | #define BM_EMI_TIME_THZ 0xf000000 | ||
103 | #define BF_EMI_TIME_THZ(v) (((v) << 24) & 0xf000000) | ||
104 | #define BP_EMI_TIME_TDH 16 | ||
105 | #define BM_EMI_TIME_TDH 0xf0000 | ||
106 | #define BF_EMI_TIME_TDH(v) (((v) << 16) & 0xf0000) | ||
107 | #define BP_EMI_TIME_TDS 8 | ||
108 | #define BM_EMI_TIME_TDS 0x1f00 | ||
109 | #define BF_EMI_TIME_TDS(v) (((v) << 8) & 0x1f00) | ||
110 | #define BP_EMI_TIME_TAS 0 | ||
111 | #define BM_EMI_TIME_TAS 0xf | ||
112 | #define BF_EMI_TIME_TAS(v) (((v) << 0) & 0xf) | ||
113 | |||
114 | /** | ||
115 | * Register: HW_EMI_DDR_TEST_MODE_CSR | ||
116 | * Address: 0x30 | ||
117 | * SCT: yes | ||
118 | */ | ||
119 | #define HW_EMI_DDR_TEST_MODE_CSR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0)) | ||
120 | #define HW_EMI_DDR_TEST_MODE_CSR_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4)) | ||
121 | #define HW_EMI_DDR_TEST_MODE_CSR_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8)) | ||
122 | #define HW_EMI_DDR_TEST_MODE_CSR_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc)) | ||
123 | #define BP_EMI_DDR_TEST_MODE_CSR_DONE 1 | ||
124 | #define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x2 | ||
125 | #define BF_EMI_DDR_TEST_MODE_CSR_DONE(v) (((v) << 1) & 0x2) | ||
126 | #define BP_EMI_DDR_TEST_MODE_CSR_START 0 | ||
127 | #define BM_EMI_DDR_TEST_MODE_CSR_START 0x1 | ||
128 | #define BF_EMI_DDR_TEST_MODE_CSR_START(v) (((v) << 0) & 0x1) | ||
129 | |||
130 | /** | ||
131 | * Register: HW_EMI_DEBUG | ||
132 | * Address: 0x80 | ||
133 | * SCT: no | ||
134 | */ | ||
135 | #define HW_EMI_DEBUG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80)) | ||
136 | #define BP_EMI_DEBUG_NOR_STATE 0 | ||
137 | #define BM_EMI_DEBUG_NOR_STATE 0xf | ||
138 | #define BF_EMI_DEBUG_NOR_STATE(v) (((v) << 0) & 0xf) | ||
139 | |||
140 | /** | ||
141 | * Register: HW_EMI_DDR_TEST_MODE_STATUS0 | ||
142 | * Address: 0x90 | ||
143 | * SCT: no | ||
144 | */ | ||
145 | #define HW_EMI_DDR_TEST_MODE_STATUS0 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90)) | ||
146 | #define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0 | ||
147 | #define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x1fff | ||
148 | #define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) (((v) << 0) & 0x1fff) | ||
149 | |||
150 | /** | ||
151 | * Register: HW_EMI_DDR_TEST_MODE_STATUS1 | ||
152 | * Address: 0xa0 | ||
153 | * SCT: no | ||
154 | */ | ||
155 | #define HW_EMI_DDR_TEST_MODE_STATUS1 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0)) | ||
156 | #define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0 | ||
157 | #define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x1fff | ||
158 | #define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) (((v) << 0) & 0x1fff) | ||
159 | |||
160 | /** | ||
161 | * Register: HW_EMI_DDR_TEST_MODE_STATUS2 | ||
162 | * Address: 0xb0 | ||
163 | * SCT: no | ||
164 | */ | ||
165 | #define HW_EMI_DDR_TEST_MODE_STATUS2 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0)) | ||
166 | #define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0 | ||
167 | #define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xffffffff | ||
168 | #define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (((v) << 0) & 0xffffffff) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_EMI_DDR_TEST_MODE_STATUS3 | ||
172 | * Address: 0xc0 | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_EMI_DDR_TEST_MODE_STATUS3 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0)) | ||
176 | #define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0 | ||
177 | #define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xffffffff | ||
178 | #define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (((v) << 0) & 0xffffffff) | ||
179 | |||
180 | /** | ||
181 | * Register: HW_EMI_VERSION | ||
182 | * Address: 0xf0 | ||
183 | * SCT: no | ||
184 | */ | ||
185 | #define HW_EMI_VERSION (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0)) | ||
186 | #define BP_EMI_VERSION_MAJOR 24 | ||
187 | #define BM_EMI_VERSION_MAJOR 0xff000000 | ||
188 | #define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
189 | #define BP_EMI_VERSION_MINOR 16 | ||
190 | #define BM_EMI_VERSION_MINOR 0xff0000 | ||
191 | #define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
192 | #define BP_EMI_VERSION_STEP 0 | ||
193 | #define BM_EMI_VERSION_STEP 0xffff | ||
194 | #define BF_EMI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
195 | |||
196 | #endif /* __HEADERGEN__STMP3700__EMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h new file mode 100644 index 0000000000..a872606da4 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h | |||
@@ -0,0 +1,355 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__GPIOMON__H__ | ||
24 | #define __HEADERGEN__STMP3700__GPIOMON__H__ | ||
25 | |||
26 | #define REGS_GPIOMON_BASE (0x8003c300) | ||
27 | |||
28 | #define REGS_GPIOMON_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_GPIOMON_BANK0_DATAIN | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_GPIOMON_BANK0_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x0)) | ||
36 | #define BP_GPIOMON_BANK0_DATAIN_DATA 0 | ||
37 | #define BM_GPIOMON_BANK0_DATAIN_DATA 0xffffffff | ||
38 | #define BF_GPIOMON_BANK0_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
39 | |||
40 | /** | ||
41 | * Register: HW_GPIOMON_BANK1_DATAIN | ||
42 | * Address: 0x10 | ||
43 | * SCT: no | ||
44 | */ | ||
45 | #define HW_GPIOMON_BANK1_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x10)) | ||
46 | #define BP_GPIOMON_BANK1_DATAIN_DATA 0 | ||
47 | #define BM_GPIOMON_BANK1_DATAIN_DATA 0xffffffff | ||
48 | #define BF_GPIOMON_BANK1_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
49 | |||
50 | /** | ||
51 | * Register: HW_GPIOMON_BANK2_DATAIN | ||
52 | * Address: 0x20 | ||
53 | * SCT: no | ||
54 | */ | ||
55 | #define HW_GPIOMON_BANK2_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x20)) | ||
56 | #define BP_GPIOMON_BANK2_DATAIN_DATA 0 | ||
57 | #define BM_GPIOMON_BANK2_DATAIN_DATA 0xffffffff | ||
58 | #define BF_GPIOMON_BANK2_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
59 | |||
60 | /** | ||
61 | * Register: HW_GPIOMON_BANK3_DATAIN | ||
62 | * Address: 0x30 | ||
63 | * SCT: no | ||
64 | */ | ||
65 | #define HW_GPIOMON_BANK3_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x30)) | ||
66 | #define BP_GPIOMON_BANK3_DATAIN_DATA 0 | ||
67 | #define BM_GPIOMON_BANK3_DATAIN_DATA 0xffffffff | ||
68 | #define BF_GPIOMON_BANK3_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_GPIOMON_BANK0_DATAOUT | ||
72 | * Address: 0x40 | ||
73 | * SCT: yes | ||
74 | */ | ||
75 | #define HW_GPIOMON_BANK0_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x0)) | ||
76 | #define HW_GPIOMON_BANK0_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x4)) | ||
77 | #define HW_GPIOMON_BANK0_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x8)) | ||
78 | #define HW_GPIOMON_BANK0_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0xc)) | ||
79 | #define BP_GPIOMON_BANK0_DATAOUT_DATA 0 | ||
80 | #define BM_GPIOMON_BANK0_DATAOUT_DATA 0xffffffff | ||
81 | #define BF_GPIOMON_BANK0_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_GPIOMON_BANK1_DATAOUT | ||
85 | * Address: 0x50 | ||
86 | * SCT: yes | ||
87 | */ | ||
88 | #define HW_GPIOMON_BANK1_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x0)) | ||
89 | #define HW_GPIOMON_BANK1_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x4)) | ||
90 | #define HW_GPIOMON_BANK1_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x8)) | ||
91 | #define HW_GPIOMON_BANK1_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0xc)) | ||
92 | #define BP_GPIOMON_BANK1_DATAOUT_DATA 0 | ||
93 | #define BM_GPIOMON_BANK1_DATAOUT_DATA 0xffffffff | ||
94 | #define BF_GPIOMON_BANK1_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
95 | |||
96 | /** | ||
97 | * Register: HW_GPIOMON_BANK2_DATAOUT | ||
98 | * Address: 0x60 | ||
99 | * SCT: yes | ||
100 | */ | ||
101 | #define HW_GPIOMON_BANK2_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x0)) | ||
102 | #define HW_GPIOMON_BANK2_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x4)) | ||
103 | #define HW_GPIOMON_BANK2_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x8)) | ||
104 | #define HW_GPIOMON_BANK2_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0xc)) | ||
105 | #define BP_GPIOMON_BANK2_DATAOUT_DATA 0 | ||
106 | #define BM_GPIOMON_BANK2_DATAOUT_DATA 0xffffffff | ||
107 | #define BF_GPIOMON_BANK2_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_GPIOMON_BANK3_DATAOUT | ||
111 | * Address: 0x70 | ||
112 | * SCT: yes | ||
113 | */ | ||
114 | #define HW_GPIOMON_BANK3_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x0)) | ||
115 | #define HW_GPIOMON_BANK3_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x4)) | ||
116 | #define HW_GPIOMON_BANK3_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x8)) | ||
117 | #define HW_GPIOMON_BANK3_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0xc)) | ||
118 | #define BP_GPIOMON_BANK3_DATAOUT_DATA 0 | ||
119 | #define BM_GPIOMON_BANK3_DATAOUT_DATA 0xffffffff | ||
120 | #define BF_GPIOMON_BANK3_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_GPIOMON_BANK0_DATAOEN | ||
124 | * Address: 0x80 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_GPIOMON_BANK0_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x0)) | ||
128 | #define HW_GPIOMON_BANK0_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x4)) | ||
129 | #define HW_GPIOMON_BANK0_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x8)) | ||
130 | #define HW_GPIOMON_BANK0_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0xc)) | ||
131 | #define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0 | ||
132 | #define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
133 | #define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
134 | |||
135 | /** | ||
136 | * Register: HW_GPIOMON_BANK1_DATAOEN | ||
137 | * Address: 0x90 | ||
138 | * SCT: yes | ||
139 | */ | ||
140 | #define HW_GPIOMON_BANK1_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x0)) | ||
141 | #define HW_GPIOMON_BANK1_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x4)) | ||
142 | #define HW_GPIOMON_BANK1_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x8)) | ||
143 | #define HW_GPIOMON_BANK1_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0xc)) | ||
144 | #define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0 | ||
145 | #define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
146 | #define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
147 | |||
148 | /** | ||
149 | * Register: HW_GPIOMON_BANK2_DATAOEN | ||
150 | * Address: 0xa0 | ||
151 | * SCT: yes | ||
152 | */ | ||
153 | #define HW_GPIOMON_BANK2_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x0)) | ||
154 | #define HW_GPIOMON_BANK2_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x4)) | ||
155 | #define HW_GPIOMON_BANK2_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x8)) | ||
156 | #define HW_GPIOMON_BANK2_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0xc)) | ||
157 | #define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0 | ||
158 | #define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
159 | #define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
160 | |||
161 | /** | ||
162 | * Register: HW_GPIOMON_BANK3_DATAOEN | ||
163 | * Address: 0xb0 | ||
164 | * SCT: yes | ||
165 | */ | ||
166 | #define HW_GPIOMON_BANK3_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x0)) | ||
167 | #define HW_GPIOMON_BANK3_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x4)) | ||
168 | #define HW_GPIOMON_BANK3_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x8)) | ||
169 | #define HW_GPIOMON_BANK3_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0xc)) | ||
170 | #define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0 | ||
171 | #define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
172 | #define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_GPIOMON_CTRL | ||
176 | * Address: 0xc0 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_GPIOMON_CTRL (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x0)) | ||
180 | #define HW_GPIOMON_CTRL_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x4)) | ||
181 | #define HW_GPIOMON_CTRL_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x8)) | ||
182 | #define HW_GPIOMON_CTRL_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0xc)) | ||
183 | #define BP_GPIOMON_CTRL_RSRVD 4 | ||
184 | #define BM_GPIOMON_CTRL_RSRVD 0xfffffff0 | ||
185 | #define BF_GPIOMON_CTRL_RSRVD(v) (((v) << 4) & 0xfffffff0) | ||
186 | #define BP_GPIOMON_CTRL_PINMUX_ALT_RESET 3 | ||
187 | #define BM_GPIOMON_CTRL_PINMUX_ALT_RESET 0x8 | ||
188 | #define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v) (((v) << 3) & 0x8) | ||
189 | #define BP_GPIOMON_CTRL_OEN_8MA 2 | ||
190 | #define BM_GPIOMON_CTRL_OEN_8MA 0x4 | ||
191 | #define BF_GPIOMON_CTRL_OEN_8MA(v) (((v) << 2) & 0x4) | ||
192 | #define BP_GPIOMON_CTRL_OEN_4MA 1 | ||
193 | #define BM_GPIOMON_CTRL_OEN_4MA 0x2 | ||
194 | #define BF_GPIOMON_CTRL_OEN_4MA(v) (((v) << 1) & 0x2) | ||
195 | #define BP_GPIOMON_CTRL_OEN_NAND 0 | ||
196 | #define BM_GPIOMON_CTRL_OEN_NAND 0x1 | ||
197 | #define BF_GPIOMON_CTRL_OEN_NAND(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK0 | ||
201 | * Address: 0xd0 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_GPIOMON_ALT1_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x0)) | ||
205 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x4)) | ||
206 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x8)) | ||
207 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0xc)) | ||
208 | #define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0 | ||
209 | #define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0xffffffff | ||
210 | #define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
211 | |||
212 | /** | ||
213 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK1 | ||
214 | * Address: 0xe0 | ||
215 | * SCT: yes | ||
216 | */ | ||
217 | #define HW_GPIOMON_ALT1_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x0)) | ||
218 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x4)) | ||
219 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x8)) | ||
220 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0xc)) | ||
221 | #define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0 | ||
222 | #define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0xffffffff | ||
223 | #define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
224 | |||
225 | /** | ||
226 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK2 | ||
227 | * Address: 0xf0 | ||
228 | * SCT: yes | ||
229 | */ | ||
230 | #define HW_GPIOMON_ALT1_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x0)) | ||
231 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x4)) | ||
232 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x8)) | ||
233 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0xc)) | ||
234 | #define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0 | ||
235 | #define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0xffffffff | ||
236 | #define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
237 | |||
238 | /** | ||
239 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK3 | ||
240 | * Address: 0x100 | ||
241 | * SCT: yes | ||
242 | */ | ||
243 | #define HW_GPIOMON_ALT1_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x0)) | ||
244 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x4)) | ||
245 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x8)) | ||
246 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0xc)) | ||
247 | #define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0 | ||
248 | #define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0xffffffff | ||
249 | #define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
250 | |||
251 | /** | ||
252 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK0 | ||
253 | * Address: 0x110 | ||
254 | * SCT: yes | ||
255 | */ | ||
256 | #define HW_GPIOMON_ALT2_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x0)) | ||
257 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x4)) | ||
258 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x8)) | ||
259 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0xc)) | ||
260 | #define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0 | ||
261 | #define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0xffffffff | ||
262 | #define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
263 | |||
264 | /** | ||
265 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK1 | ||
266 | * Address: 0x120 | ||
267 | * SCT: yes | ||
268 | */ | ||
269 | #define HW_GPIOMON_ALT2_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x0)) | ||
270 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x4)) | ||
271 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x8)) | ||
272 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0xc)) | ||
273 | #define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0 | ||
274 | #define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0xffffffff | ||
275 | #define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
276 | |||
277 | /** | ||
278 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK2 | ||
279 | * Address: 0x130 | ||
280 | * SCT: yes | ||
281 | */ | ||
282 | #define HW_GPIOMON_ALT2_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x0)) | ||
283 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x4)) | ||
284 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x8)) | ||
285 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0xc)) | ||
286 | #define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0 | ||
287 | #define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0xffffffff | ||
288 | #define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
289 | |||
290 | /** | ||
291 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK3 | ||
292 | * Address: 0x140 | ||
293 | * SCT: yes | ||
294 | */ | ||
295 | #define HW_GPIOMON_ALT2_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x0)) | ||
296 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x4)) | ||
297 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x8)) | ||
298 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0xc)) | ||
299 | #define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0 | ||
300 | #define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0xffffffff | ||
301 | #define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
302 | |||
303 | /** | ||
304 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK0 | ||
305 | * Address: 0x150 | ||
306 | * SCT: yes | ||
307 | */ | ||
308 | #define HW_GPIOMON_ALT3_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x0)) | ||
309 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x4)) | ||
310 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x8)) | ||
311 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0xc)) | ||
312 | #define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0 | ||
313 | #define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0xffffffff | ||
314 | #define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
315 | |||
316 | /** | ||
317 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK1 | ||
318 | * Address: 0x160 | ||
319 | * SCT: yes | ||
320 | */ | ||
321 | #define HW_GPIOMON_ALT3_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x0)) | ||
322 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x4)) | ||
323 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x8)) | ||
324 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0xc)) | ||
325 | #define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0 | ||
326 | #define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0xffffffff | ||
327 | #define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
328 | |||
329 | /** | ||
330 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK2 | ||
331 | * Address: 0x170 | ||
332 | * SCT: yes | ||
333 | */ | ||
334 | #define HW_GPIOMON_ALT3_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x0)) | ||
335 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x4)) | ||
336 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x8)) | ||
337 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0xc)) | ||
338 | #define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0 | ||
339 | #define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0xffffffff | ||
340 | #define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
341 | |||
342 | /** | ||
343 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK3 | ||
344 | * Address: 0x180 | ||
345 | * SCT: yes | ||
346 | */ | ||
347 | #define HW_GPIOMON_ALT3_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x0)) | ||
348 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x4)) | ||
349 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x8)) | ||
350 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0xc)) | ||
351 | #define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0 | ||
352 | #define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0xffffffff | ||
353 | #define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
354 | |||
355 | #endif /* __HEADERGEN__STMP3700__GPIOMON__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h new file mode 100644 index 0000000000..d8dcb3b5cf --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h | |||
@@ -0,0 +1,461 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__GPMI__H__ | ||
24 | #define __HEADERGEN__STMP3700__GPMI__H__ | ||
25 | |||
26 | #define REGS_GPMI_BASE (0x8000c000) | ||
27 | |||
28 | #define REGS_GPMI_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_GPMI_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_GPMI_CTRL0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_GPMI_CTRL0_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_GPMI_CTRL0_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_GPMI_CTRL0_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_GPMI_CTRL0_SFTRST 31 | ||
40 | #define BM_GPMI_CTRL0_SFTRST 0x80000000 | ||
41 | #define BV_GPMI_CTRL0_SFTRST__RUN 0x0 | ||
42 | #define BV_GPMI_CTRL0_SFTRST__RESET 0x1 | ||
43 | #define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_GPMI_CTRL0_SFTRST_V(v) ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_GPMI_CTRL0_CLKGATE 30 | ||
46 | #define BM_GPMI_CTRL0_CLKGATE 0x40000000 | ||
47 | #define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 | ||
48 | #define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_GPMI_CTRL0_CLKGATE_V(v) ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_GPMI_CTRL0_RUN 29 | ||
52 | #define BM_GPMI_CTRL0_RUN 0x20000000 | ||
53 | #define BV_GPMI_CTRL0_RUN__IDLE 0x0 | ||
54 | #define BV_GPMI_CTRL0_RUN__BUSY 0x1 | ||
55 | #define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_GPMI_CTRL0_RUN_V(v) ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000) | ||
57 | #define BP_GPMI_CTRL0_DEV_IRQ_EN 28 | ||
58 | #define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 | ||
59 | #define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
60 | #define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27 | ||
61 | #define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x8000000 | ||
62 | #define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & 0x8000000) | ||
63 | #define BP_GPMI_CTRL0_UDMA 26 | ||
64 | #define BM_GPMI_CTRL0_UDMA 0x4000000 | ||
65 | #define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 | ||
66 | #define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 | ||
67 | #define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & 0x4000000) | ||
68 | #define BF_GPMI_CTRL0_UDMA_V(v) ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000) | ||
69 | #define BP_GPMI_CTRL0_COMMAND_MODE 24 | ||
70 | #define BM_GPMI_CTRL0_COMMAND_MODE 0x3000000 | ||
71 | #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 | ||
72 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 | ||
73 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 | ||
74 | #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 | ||
75 | #define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & 0x3000000) | ||
76 | #define BF_GPMI_CTRL0_COMMAND_MODE_V(v) ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000) | ||
77 | #define BP_GPMI_CTRL0_WORD_LENGTH 23 | ||
78 | #define BM_GPMI_CTRL0_WORD_LENGTH 0x800000 | ||
79 | #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 | ||
80 | #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 | ||
81 | #define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & 0x800000) | ||
82 | #define BF_GPMI_CTRL0_WORD_LENGTH_V(v) ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000) | ||
83 | #define BP_GPMI_CTRL0_LOCK_CS 22 | ||
84 | #define BM_GPMI_CTRL0_LOCK_CS 0x400000 | ||
85 | #define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 | ||
86 | #define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 | ||
87 | #define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & 0x400000) | ||
88 | #define BF_GPMI_CTRL0_LOCK_CS_V(v) ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000) | ||
89 | #define BP_GPMI_CTRL0_CS 20 | ||
90 | #define BM_GPMI_CTRL0_CS 0x300000 | ||
91 | #define BF_GPMI_CTRL0_CS(v) (((v) << 20) & 0x300000) | ||
92 | #define BP_GPMI_CTRL0_ADDRESS 17 | ||
93 | #define BM_GPMI_CTRL0_ADDRESS 0xe0000 | ||
94 | #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 | ||
95 | #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 | ||
96 | #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 | ||
97 | #define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & 0xe0000) | ||
98 | #define BF_GPMI_CTRL0_ADDRESS_V(v) ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000) | ||
99 | #define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 | ||
100 | #define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x10000 | ||
101 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 | ||
102 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 | ||
103 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & 0x10000) | ||
104 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000) | ||
105 | #define BP_GPMI_CTRL0_XFER_COUNT 0 | ||
106 | #define BM_GPMI_CTRL0_XFER_COUNT 0xffff | ||
107 | #define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_GPMI_COMPARE | ||
111 | * Address: 0x10 | ||
112 | * SCT: no | ||
113 | */ | ||
114 | #define HW_GPMI_COMPARE (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10)) | ||
115 | #define BP_GPMI_COMPARE_MASK 16 | ||
116 | #define BM_GPMI_COMPARE_MASK 0xffff0000 | ||
117 | #define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & 0xffff0000) | ||
118 | #define BP_GPMI_COMPARE_REFERENCE 0 | ||
119 | #define BM_GPMI_COMPARE_REFERENCE 0xffff | ||
120 | #define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & 0xffff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_GPMI_ECCCTRL | ||
124 | * Address: 0x20 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_GPMI_ECCCTRL (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0)) | ||
128 | #define HW_GPMI_ECCCTRL_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4)) | ||
129 | #define HW_GPMI_ECCCTRL_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8)) | ||
130 | #define HW_GPMI_ECCCTRL_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc)) | ||
131 | #define BP_GPMI_ECCCTRL_HANDLE 16 | ||
132 | #define BM_GPMI_ECCCTRL_HANDLE 0xffff0000 | ||
133 | #define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & 0xffff0000) | ||
134 | #define BP_GPMI_ECCCTRL_ECC_CMD 13 | ||
135 | #define BM_GPMI_ECCCTRL_ECC_CMD 0x6000 | ||
136 | #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 | ||
137 | #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 | ||
138 | #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 | ||
139 | #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 | ||
140 | #define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & 0x6000) | ||
141 | #define BF_GPMI_ECCCTRL_ECC_CMD_V(v) ((BV_GPMI_ECCCTRL_ECC_CMD__##v << 13) & 0x6000) | ||
142 | #define BP_GPMI_ECCCTRL_ENABLE_ECC 12 | ||
143 | #define BM_GPMI_ECCCTRL_ENABLE_ECC 0x1000 | ||
144 | #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 | ||
145 | #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 | ||
146 | #define BF_GPMI_ECCCTRL_ENABLE_ECC(v) (((v) << 12) & 0x1000) | ||
147 | #define BF_GPMI_ECCCTRL_ENABLE_ECC_V(v) ((BV_GPMI_ECCCTRL_ENABLE_ECC__##v << 12) & 0x1000) | ||
148 | #define BP_GPMI_ECCCTRL_BUFFER_MASK 0 | ||
149 | #define BM_GPMI_ECCCTRL_BUFFER_MASK 0x1ff | ||
150 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 | ||
151 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x80 | ||
152 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x40 | ||
153 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x20 | ||
154 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x10 | ||
155 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x8 | ||
156 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x4 | ||
157 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x2 | ||
158 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x1 | ||
159 | #define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & 0x1ff) | ||
160 | #define BF_GPMI_ECCCTRL_BUFFER_MASK_V(v) ((BV_GPMI_ECCCTRL_BUFFER_MASK__##v << 0) & 0x1ff) | ||
161 | |||
162 | /** | ||
163 | * Register: HW_GPMI_ECCCOUNT | ||
164 | * Address: 0x30 | ||
165 | * SCT: no | ||
166 | */ | ||
167 | #define HW_GPMI_ECCCOUNT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30)) | ||
168 | #define BP_GPMI_ECCCOUNT_COUNT 0 | ||
169 | #define BM_GPMI_ECCCOUNT_COUNT 0xffff | ||
170 | #define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & 0xffff) | ||
171 | |||
172 | /** | ||
173 | * Register: HW_GPMI_PAYLOAD | ||
174 | * Address: 0x40 | ||
175 | * SCT: no | ||
176 | */ | ||
177 | #define HW_GPMI_PAYLOAD (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40)) | ||
178 | #define BP_GPMI_PAYLOAD_ADDRESS 2 | ||
179 | #define BM_GPMI_PAYLOAD_ADDRESS 0xfffffffc | ||
180 | #define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
181 | |||
182 | /** | ||
183 | * Register: HW_GPMI_AUXILIARY | ||
184 | * Address: 0x50 | ||
185 | * SCT: no | ||
186 | */ | ||
187 | #define HW_GPMI_AUXILIARY (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50)) | ||
188 | #define BP_GPMI_AUXILIARY_ADDRESS 2 | ||
189 | #define BM_GPMI_AUXILIARY_ADDRESS 0xfffffffc | ||
190 | #define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
191 | |||
192 | /** | ||
193 | * Register: HW_GPMI_CTRL1 | ||
194 | * Address: 0x60 | ||
195 | * SCT: yes | ||
196 | */ | ||
197 | #define HW_GPMI_CTRL1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x0)) | ||
198 | #define HW_GPMI_CTRL1_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x4)) | ||
199 | #define HW_GPMI_CTRL1_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x8)) | ||
200 | #define HW_GPMI_CTRL1_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0xc)) | ||
201 | #define BP_GPMI_CTRL1_DSAMPLE_TIME 12 | ||
202 | #define BM_GPMI_CTRL1_DSAMPLE_TIME 0x7000 | ||
203 | #define BF_GPMI_CTRL1_DSAMPLE_TIME(v) (((v) << 12) & 0x7000) | ||
204 | #define BP_GPMI_CTRL1_DMA2ECC_MODE 11 | ||
205 | #define BM_GPMI_CTRL1_DMA2ECC_MODE 0x800 | ||
206 | #define BF_GPMI_CTRL1_DMA2ECC_MODE(v) (((v) << 11) & 0x800) | ||
207 | #define BP_GPMI_CTRL1_DEV_IRQ 10 | ||
208 | #define BM_GPMI_CTRL1_DEV_IRQ 0x400 | ||
209 | #define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & 0x400) | ||
210 | #define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 | ||
211 | #define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x200 | ||
212 | #define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & 0x200) | ||
213 | #define BP_GPMI_CTRL1_BURST_EN 8 | ||
214 | #define BM_GPMI_CTRL1_BURST_EN 0x100 | ||
215 | #define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & 0x100) | ||
216 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7 | ||
217 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x80 | ||
218 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & 0x80) | ||
219 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6 | ||
220 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x40 | ||
221 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & 0x40) | ||
222 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5 | ||
223 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x20 | ||
224 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & 0x20) | ||
225 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4 | ||
226 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x10 | ||
227 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & 0x10) | ||
228 | #define BP_GPMI_CTRL1_DEV_RESET 3 | ||
229 | #define BM_GPMI_CTRL1_DEV_RESET 0x8 | ||
230 | #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 | ||
231 | #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 | ||
232 | #define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & 0x8) | ||
233 | #define BF_GPMI_CTRL1_DEV_RESET_V(v) ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8) | ||
234 | #define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 | ||
235 | #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x4 | ||
236 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 | ||
237 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 | ||
238 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & 0x4) | ||
239 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v) ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4) | ||
240 | #define BP_GPMI_CTRL1_CAMERA_MODE 1 | ||
241 | #define BM_GPMI_CTRL1_CAMERA_MODE 0x2 | ||
242 | #define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & 0x2) | ||
243 | #define BP_GPMI_CTRL1_GPMI_MODE 0 | ||
244 | #define BM_GPMI_CTRL1_GPMI_MODE 0x1 | ||
245 | #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 | ||
246 | #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 | ||
247 | #define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & 0x1) | ||
248 | #define BF_GPMI_CTRL1_GPMI_MODE_V(v) ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1) | ||
249 | |||
250 | /** | ||
251 | * Register: HW_GPMI_TIMING0 | ||
252 | * Address: 0x70 | ||
253 | * SCT: no | ||
254 | */ | ||
255 | #define HW_GPMI_TIMING0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70)) | ||
256 | #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 | ||
257 | #define BM_GPMI_TIMING0_ADDRESS_SETUP 0xff0000 | ||
258 | #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & 0xff0000) | ||
259 | #define BP_GPMI_TIMING0_DATA_HOLD 8 | ||
260 | #define BM_GPMI_TIMING0_DATA_HOLD 0xff00 | ||
261 | #define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
262 | #define BP_GPMI_TIMING0_DATA_SETUP 0 | ||
263 | #define BM_GPMI_TIMING0_DATA_SETUP 0xff | ||
264 | #define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
265 | |||
266 | /** | ||
267 | * Register: HW_GPMI_TIMING1 | ||
268 | * Address: 0x80 | ||
269 | * SCT: no | ||
270 | */ | ||
271 | #define HW_GPMI_TIMING1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80)) | ||
272 | #define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 | ||
273 | #define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xffff0000 | ||
274 | #define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
275 | |||
276 | /** | ||
277 | * Register: HW_GPMI_TIMING2 | ||
278 | * Address: 0x90 | ||
279 | * SCT: no | ||
280 | */ | ||
281 | #define HW_GPMI_TIMING2 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x90)) | ||
282 | #define BP_GPMI_TIMING2_UDMA_TRP 24 | ||
283 | #define BM_GPMI_TIMING2_UDMA_TRP 0xff000000 | ||
284 | #define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & 0xff000000) | ||
285 | #define BP_GPMI_TIMING2_UDMA_ENV 16 | ||
286 | #define BM_GPMI_TIMING2_UDMA_ENV 0xff0000 | ||
287 | #define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & 0xff0000) | ||
288 | #define BP_GPMI_TIMING2_UDMA_HOLD 8 | ||
289 | #define BM_GPMI_TIMING2_UDMA_HOLD 0xff00 | ||
290 | #define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & 0xff00) | ||
291 | #define BP_GPMI_TIMING2_UDMA_SETUP 0 | ||
292 | #define BM_GPMI_TIMING2_UDMA_SETUP 0xff | ||
293 | #define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & 0xff) | ||
294 | |||
295 | /** | ||
296 | * Register: HW_GPMI_DATA | ||
297 | * Address: 0xa0 | ||
298 | * SCT: no | ||
299 | */ | ||
300 | #define HW_GPMI_DATA (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xa0)) | ||
301 | #define BP_GPMI_DATA_DATA 0 | ||
302 | #define BM_GPMI_DATA_DATA 0xffffffff | ||
303 | #define BF_GPMI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
304 | |||
305 | /** | ||
306 | * Register: HW_GPMI_STAT | ||
307 | * Address: 0xb0 | ||
308 | * SCT: no | ||
309 | */ | ||
310 | #define HW_GPMI_STAT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xb0)) | ||
311 | #define BP_GPMI_STAT_PRESENT 31 | ||
312 | #define BM_GPMI_STAT_PRESENT 0x80000000 | ||
313 | #define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 | ||
314 | #define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 | ||
315 | #define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
316 | #define BF_GPMI_STAT_PRESENT_V(v) ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000) | ||
317 | #define BP_GPMI_STAT_RDY_TIMEOUT 8 | ||
318 | #define BM_GPMI_STAT_RDY_TIMEOUT 0xf00 | ||
319 | #define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & 0xf00) | ||
320 | #define BP_GPMI_STAT_ATA_IRQ 7 | ||
321 | #define BM_GPMI_STAT_ATA_IRQ 0x80 | ||
322 | #define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & 0x80) | ||
323 | #define BP_GPMI_STAT_INVALID_BUFFER_MASK 6 | ||
324 | #define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x40 | ||
325 | #define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & 0x40) | ||
326 | #define BP_GPMI_STAT_FIFO_EMPTY 5 | ||
327 | #define BM_GPMI_STAT_FIFO_EMPTY 0x20 | ||
328 | #define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 | ||
329 | #define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 | ||
330 | #define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
331 | #define BF_GPMI_STAT_FIFO_EMPTY_V(v) ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20) | ||
332 | #define BP_GPMI_STAT_FIFO_FULL 4 | ||
333 | #define BM_GPMI_STAT_FIFO_FULL 0x10 | ||
334 | #define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 | ||
335 | #define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 | ||
336 | #define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & 0x10) | ||
337 | #define BF_GPMI_STAT_FIFO_FULL_V(v) ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10) | ||
338 | #define BP_GPMI_STAT_DEV3_ERROR 3 | ||
339 | #define BM_GPMI_STAT_DEV3_ERROR 0x8 | ||
340 | #define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & 0x8) | ||
341 | #define BP_GPMI_STAT_DEV2_ERROR 2 | ||
342 | #define BM_GPMI_STAT_DEV2_ERROR 0x4 | ||
343 | #define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & 0x4) | ||
344 | #define BP_GPMI_STAT_DEV1_ERROR 1 | ||
345 | #define BM_GPMI_STAT_DEV1_ERROR 0x2 | ||
346 | #define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & 0x2) | ||
347 | #define BP_GPMI_STAT_DEV0_ERROR 0 | ||
348 | #define BM_GPMI_STAT_DEV0_ERROR 0x1 | ||
349 | #define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & 0x1) | ||
350 | |||
351 | /** | ||
352 | * Register: HW_GPMI_DEBUG | ||
353 | * Address: 0xc0 | ||
354 | * SCT: no | ||
355 | */ | ||
356 | #define HW_GPMI_DEBUG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xc0)) | ||
357 | #define BP_GPMI_DEBUG_READY3 31 | ||
358 | #define BM_GPMI_DEBUG_READY3 0x80000000 | ||
359 | #define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & 0x80000000) | ||
360 | #define BP_GPMI_DEBUG_READY2 30 | ||
361 | #define BM_GPMI_DEBUG_READY2 0x40000000 | ||
362 | #define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & 0x40000000) | ||
363 | #define BP_GPMI_DEBUG_READY1 29 | ||
364 | #define BM_GPMI_DEBUG_READY1 0x20000000 | ||
365 | #define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & 0x20000000) | ||
366 | #define BP_GPMI_DEBUG_READY0 28 | ||
367 | #define BM_GPMI_DEBUG_READY0 0x10000000 | ||
368 | #define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & 0x10000000) | ||
369 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27 | ||
370 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x8000000 | ||
371 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & 0x8000000) | ||
372 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26 | ||
373 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x4000000 | ||
374 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & 0x4000000) | ||
375 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25 | ||
376 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x2000000 | ||
377 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & 0x2000000) | ||
378 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24 | ||
379 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x1000000 | ||
380 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & 0x1000000) | ||
381 | #define BP_GPMI_DEBUG_SENSE3 23 | ||
382 | #define BM_GPMI_DEBUG_SENSE3 0x800000 | ||
383 | #define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & 0x800000) | ||
384 | #define BP_GPMI_DEBUG_SENSE2 22 | ||
385 | #define BM_GPMI_DEBUG_SENSE2 0x400000 | ||
386 | #define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & 0x400000) | ||
387 | #define BP_GPMI_DEBUG_SENSE1 21 | ||
388 | #define BM_GPMI_DEBUG_SENSE1 0x200000 | ||
389 | #define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & 0x200000) | ||
390 | #define BP_GPMI_DEBUG_SENSE0 20 | ||
391 | #define BM_GPMI_DEBUG_SENSE0 0x100000 | ||
392 | #define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & 0x100000) | ||
393 | #define BP_GPMI_DEBUG_DMAREQ3 19 | ||
394 | #define BM_GPMI_DEBUG_DMAREQ3 0x80000 | ||
395 | #define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & 0x80000) | ||
396 | #define BP_GPMI_DEBUG_DMAREQ2 18 | ||
397 | #define BM_GPMI_DEBUG_DMAREQ2 0x40000 | ||
398 | #define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & 0x40000) | ||
399 | #define BP_GPMI_DEBUG_DMAREQ1 17 | ||
400 | #define BM_GPMI_DEBUG_DMAREQ1 0x20000 | ||
401 | #define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & 0x20000) | ||
402 | #define BP_GPMI_DEBUG_DMAREQ0 16 | ||
403 | #define BM_GPMI_DEBUG_DMAREQ0 0x10000 | ||
404 | #define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & 0x10000) | ||
405 | #define BP_GPMI_DEBUG_CMD_END 12 | ||
406 | #define BM_GPMI_DEBUG_CMD_END 0xf000 | ||
407 | #define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & 0xf000) | ||
408 | #define BP_GPMI_DEBUG_UDMA_STATE 8 | ||
409 | #define BM_GPMI_DEBUG_UDMA_STATE 0xf00 | ||
410 | #define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & 0xf00) | ||
411 | #define BP_GPMI_DEBUG_BUSY 7 | ||
412 | #define BM_GPMI_DEBUG_BUSY 0x80 | ||
413 | #define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 | ||
414 | #define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 | ||
415 | #define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & 0x80) | ||
416 | #define BF_GPMI_DEBUG_BUSY_V(v) ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80) | ||
417 | #define BP_GPMI_DEBUG_PIN_STATE 4 | ||
418 | #define BM_GPMI_DEBUG_PIN_STATE 0x70 | ||
419 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 | ||
420 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 | ||
421 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 | ||
422 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 | ||
423 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 | ||
424 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 | ||
425 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 | ||
426 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 | ||
427 | #define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & 0x70) | ||
428 | #define BF_GPMI_DEBUG_PIN_STATE_V(v) ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70) | ||
429 | #define BP_GPMI_DEBUG_MAIN_STATE 0 | ||
430 | #define BM_GPMI_DEBUG_MAIN_STATE 0xf | ||
431 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 | ||
432 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 | ||
433 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 | ||
434 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 | ||
435 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 | ||
436 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 | ||
437 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 | ||
438 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 | ||
439 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 | ||
440 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 | ||
441 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xa | ||
442 | #define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & 0xf) | ||
443 | #define BF_GPMI_DEBUG_MAIN_STATE_V(v) ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf) | ||
444 | |||
445 | /** | ||
446 | * Register: HW_GPMI_VERSION | ||
447 | * Address: 0xd0 | ||
448 | * SCT: no | ||
449 | */ | ||
450 | #define HW_GPMI_VERSION (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xd0)) | ||
451 | #define BP_GPMI_VERSION_MAJOR 24 | ||
452 | #define BM_GPMI_VERSION_MAJOR 0xff000000 | ||
453 | #define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
454 | #define BP_GPMI_VERSION_MINOR 16 | ||
455 | #define BM_GPMI_VERSION_MINOR 0xff0000 | ||
456 | #define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
457 | #define BP_GPMI_VERSION_STEP 0 | ||
458 | #define BM_GPMI_VERSION_STEP 0xffff | ||
459 | #define BF_GPMI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
460 | |||
461 | #endif /* __HEADERGEN__STMP3700__GPMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h new file mode 100644 index 0000000000..ea34d27db2 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h | |||
@@ -0,0 +1,537 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__I2C__H__ | ||
24 | #define __HEADERGEN__STMP3700__I2C__H__ | ||
25 | |||
26 | #define REGS_I2C_BASE (0x80058000) | ||
27 | |||
28 | #define REGS_I2C_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_I2C_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_I2C_CTRL0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0)) | ||
36 | #define HW_I2C_CTRL0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4)) | ||
37 | #define HW_I2C_CTRL0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8)) | ||
38 | #define HW_I2C_CTRL0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc)) | ||
39 | #define BP_I2C_CTRL0_SFTRST 31 | ||
40 | #define BM_I2C_CTRL0_SFTRST 0x80000000 | ||
41 | #define BV_I2C_CTRL0_SFTRST__RUN 0x0 | ||
42 | #define BV_I2C_CTRL0_SFTRST__RESET 0x1 | ||
43 | #define BF_I2C_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_I2C_CTRL0_SFTRST_V(v) ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_I2C_CTRL0_CLKGATE 30 | ||
46 | #define BM_I2C_CTRL0_CLKGATE 0x40000000 | ||
47 | #define BV_I2C_CTRL0_CLKGATE__RUN 0x0 | ||
48 | #define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_I2C_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_I2C_CTRL0_CLKGATE_V(v) ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_I2C_CTRL0_RUN 29 | ||
52 | #define BM_I2C_CTRL0_RUN 0x20000000 | ||
53 | #define BV_I2C_CTRL0_RUN__HALT 0x0 | ||
54 | #define BV_I2C_CTRL0_RUN__RUN 0x1 | ||
55 | #define BF_I2C_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_I2C_CTRL0_RUN_V(v) ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000) | ||
57 | #define BP_I2C_CTRL0_PRE_ACK 27 | ||
58 | #define BM_I2C_CTRL0_PRE_ACK 0x8000000 | ||
59 | #define BF_I2C_CTRL0_PRE_ACK(v) (((v) << 27) & 0x8000000) | ||
60 | #define BP_I2C_CTRL0_ACKNOWLEDGE 26 | ||
61 | #define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000 | ||
62 | #define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 | ||
63 | #define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 | ||
64 | #define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) << 26) & 0x4000000) | ||
65 | #define BF_I2C_CTRL0_ACKNOWLEDGE_V(v) ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000) | ||
66 | #define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25 | ||
67 | #define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000 | ||
68 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 | ||
69 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 | ||
70 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) << 25) & 0x2000000) | ||
71 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000) | ||
72 | #define BP_I2C_CTRL0_PIO_MODE 24 | ||
73 | #define BM_I2C_CTRL0_PIO_MODE 0x1000000 | ||
74 | #define BF_I2C_CTRL0_PIO_MODE(v) (((v) << 24) & 0x1000000) | ||
75 | #define BP_I2C_CTRL0_MULTI_MASTER 23 | ||
76 | #define BM_I2C_CTRL0_MULTI_MASTER 0x800000 | ||
77 | #define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 | ||
78 | #define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 | ||
79 | #define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) << 23) & 0x800000) | ||
80 | #define BF_I2C_CTRL0_MULTI_MASTER_V(v) ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000) | ||
81 | #define BP_I2C_CTRL0_CLOCK_HELD 22 | ||
82 | #define BM_I2C_CTRL0_CLOCK_HELD 0x400000 | ||
83 | #define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 | ||
84 | #define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 | ||
85 | #define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) << 22) & 0x400000) | ||
86 | #define BF_I2C_CTRL0_CLOCK_HELD_V(v) ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000) | ||
87 | #define BP_I2C_CTRL0_RETAIN_CLOCK 21 | ||
88 | #define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000 | ||
89 | #define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 | ||
90 | #define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 | ||
91 | #define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) << 21) & 0x200000) | ||
92 | #define BF_I2C_CTRL0_RETAIN_CLOCK_V(v) ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000) | ||
93 | #define BP_I2C_CTRL0_POST_SEND_STOP 20 | ||
94 | #define BM_I2C_CTRL0_POST_SEND_STOP 0x100000 | ||
95 | #define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 | ||
96 | #define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 | ||
97 | #define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) << 20) & 0x100000) | ||
98 | #define BF_I2C_CTRL0_POST_SEND_STOP_V(v) ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000) | ||
99 | #define BP_I2C_CTRL0_PRE_SEND_START 19 | ||
100 | #define BM_I2C_CTRL0_PRE_SEND_START 0x80000 | ||
101 | #define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 | ||
102 | #define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 | ||
103 | #define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) << 19) & 0x80000) | ||
104 | #define BF_I2C_CTRL0_PRE_SEND_START_V(v) ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000) | ||
105 | #define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18 | ||
106 | #define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000 | ||
107 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 | ||
108 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 | ||
109 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) << 18) & 0x40000) | ||
110 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000) | ||
111 | #define BP_I2C_CTRL0_MASTER_MODE 17 | ||
112 | #define BM_I2C_CTRL0_MASTER_MODE 0x20000 | ||
113 | #define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 | ||
114 | #define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 | ||
115 | #define BF_I2C_CTRL0_MASTER_MODE(v) (((v) << 17) & 0x20000) | ||
116 | #define BF_I2C_CTRL0_MASTER_MODE_V(v) ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000) | ||
117 | #define BP_I2C_CTRL0_DIRECTION 16 | ||
118 | #define BM_I2C_CTRL0_DIRECTION 0x10000 | ||
119 | #define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 | ||
120 | #define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 | ||
121 | #define BF_I2C_CTRL0_DIRECTION(v) (((v) << 16) & 0x10000) | ||
122 | #define BF_I2C_CTRL0_DIRECTION_V(v) ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000) | ||
123 | #define BP_I2C_CTRL0_XFER_COUNT 0 | ||
124 | #define BM_I2C_CTRL0_XFER_COUNT 0xffff | ||
125 | #define BF_I2C_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
126 | |||
127 | /** | ||
128 | * Register: HW_I2C_TIMING0 | ||
129 | * Address: 0x10 | ||
130 | * SCT: yes | ||
131 | */ | ||
132 | #define HW_I2C_TIMING0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0)) | ||
133 | #define HW_I2C_TIMING0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4)) | ||
134 | #define HW_I2C_TIMING0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8)) | ||
135 | #define HW_I2C_TIMING0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc)) | ||
136 | #define BP_I2C_TIMING0_HIGH_COUNT 16 | ||
137 | #define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000 | ||
138 | #define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
139 | #define BP_I2C_TIMING0_RCV_COUNT 0 | ||
140 | #define BM_I2C_TIMING0_RCV_COUNT 0x3ff | ||
141 | #define BF_I2C_TIMING0_RCV_COUNT(v) (((v) << 0) & 0x3ff) | ||
142 | |||
143 | /** | ||
144 | * Register: HW_I2C_TIMING1 | ||
145 | * Address: 0x20 | ||
146 | * SCT: yes | ||
147 | */ | ||
148 | #define HW_I2C_TIMING1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0)) | ||
149 | #define HW_I2C_TIMING1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4)) | ||
150 | #define HW_I2C_TIMING1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8)) | ||
151 | #define HW_I2C_TIMING1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc)) | ||
152 | #define BP_I2C_TIMING1_LOW_COUNT 16 | ||
153 | #define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000 | ||
154 | #define BF_I2C_TIMING1_LOW_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
155 | #define BP_I2C_TIMING1_XMIT_COUNT 0 | ||
156 | #define BM_I2C_TIMING1_XMIT_COUNT 0x3ff | ||
157 | #define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) << 0) & 0x3ff) | ||
158 | |||
159 | /** | ||
160 | * Register: HW_I2C_TIMING2 | ||
161 | * Address: 0x30 | ||
162 | * SCT: yes | ||
163 | */ | ||
164 | #define HW_I2C_TIMING2 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0)) | ||
165 | #define HW_I2C_TIMING2_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4)) | ||
166 | #define HW_I2C_TIMING2_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8)) | ||
167 | #define HW_I2C_TIMING2_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc)) | ||
168 | #define BP_I2C_TIMING2_BUS_FREE 16 | ||
169 | #define BM_I2C_TIMING2_BUS_FREE 0x3ff0000 | ||
170 | #define BF_I2C_TIMING2_BUS_FREE(v) (((v) << 16) & 0x3ff0000) | ||
171 | #define BP_I2C_TIMING2_LEADIN_COUNT 0 | ||
172 | #define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff | ||
173 | #define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) << 0) & 0x3ff) | ||
174 | |||
175 | /** | ||
176 | * Register: HW_I2C_CTRL1 | ||
177 | * Address: 0x40 | ||
178 | * SCT: yes | ||
179 | */ | ||
180 | #define HW_I2C_CTRL1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0)) | ||
181 | #define HW_I2C_CTRL1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4)) | ||
182 | #define HW_I2C_CTRL1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8)) | ||
183 | #define HW_I2C_CTRL1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc)) | ||
184 | #define BP_I2C_CTRL1_BCAST_SLAVE_EN 24 | ||
185 | #define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000 | ||
186 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 | ||
187 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 | ||
188 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) << 24) & 0x1000000) | ||
189 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v) ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000) | ||
190 | #define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 | ||
191 | #define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000 | ||
192 | #define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) << 16) & 0xff0000) | ||
193 | #define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15 | ||
194 | #define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000 | ||
195 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 | ||
196 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 | ||
197 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
198 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000) | ||
199 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14 | ||
200 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000 | ||
201 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 | ||
202 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 | ||
203 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
204 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000) | ||
205 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13 | ||
206 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000 | ||
207 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 | ||
208 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 | ||
209 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
210 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000) | ||
211 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12 | ||
212 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000 | ||
213 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 | ||
214 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 | ||
215 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
216 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000) | ||
217 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11 | ||
218 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800 | ||
219 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 | ||
220 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 | ||
221 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) << 11) & 0x800) | ||
222 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800) | ||
223 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10 | ||
224 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400 | ||
225 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 | ||
226 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 | ||
227 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
228 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
229 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9 | ||
230 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200 | ||
231 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 | ||
232 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 | ||
233 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) << 9) & 0x200) | ||
234 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200) | ||
235 | #define BP_I2C_CTRL1_SLAVE_IRQ_EN 8 | ||
236 | #define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100 | ||
237 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 | ||
238 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 | ||
239 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
240 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100) | ||
241 | #define BP_I2C_CTRL1_BUS_FREE_IRQ 7 | ||
242 | #define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80 | ||
243 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 | ||
244 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 | ||
245 | #define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) << 7) & 0x80) | ||
246 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80) | ||
247 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6 | ||
248 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | ||
249 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 | ||
250 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 | ||
251 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) << 6) & 0x40) | ||
252 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40) | ||
253 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5 | ||
254 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | ||
255 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 | ||
256 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 | ||
257 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) << 5) & 0x20) | ||
258 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20) | ||
259 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4 | ||
260 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | ||
261 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 | ||
262 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 | ||
263 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) << 4) & 0x10) | ||
264 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10) | ||
265 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ 3 | ||
266 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8 | ||
267 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 | ||
268 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 | ||
269 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) << 3) & 0x8) | ||
270 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8) | ||
271 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2 | ||
272 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4 | ||
273 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 | ||
274 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 | ||
275 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
276 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4) | ||
277 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1 | ||
278 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2 | ||
279 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 | ||
280 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 | ||
281 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) << 1) & 0x2) | ||
282 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2) | ||
283 | #define BP_I2C_CTRL1_SLAVE_IRQ 0 | ||
284 | #define BM_I2C_CTRL1_SLAVE_IRQ 0x1 | ||
285 | #define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 | ||
286 | #define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 | ||
287 | #define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) << 0) & 0x1) | ||
288 | #define BF_I2C_CTRL1_SLAVE_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1) | ||
289 | |||
290 | /** | ||
291 | * Register: HW_I2C_STAT | ||
292 | * Address: 0x50 | ||
293 | * SCT: no | ||
294 | */ | ||
295 | #define HW_I2C_STAT (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50)) | ||
296 | #define BP_I2C_STAT_MASTER_PRESENT 31 | ||
297 | #define BM_I2C_STAT_MASTER_PRESENT 0x80000000 | ||
298 | #define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 | ||
299 | #define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 | ||
300 | #define BF_I2C_STAT_MASTER_PRESENT(v) (((v) << 31) & 0x80000000) | ||
301 | #define BF_I2C_STAT_MASTER_PRESENT_V(v) ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000) | ||
302 | #define BP_I2C_STAT_SLAVE_PRESENT 30 | ||
303 | #define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 | ||
304 | #define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 | ||
305 | #define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 | ||
306 | #define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) << 30) & 0x40000000) | ||
307 | #define BF_I2C_STAT_SLAVE_PRESENT_V(v) ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000) | ||
308 | #define BP_I2C_STAT_ANY_ENABLED_IRQ 29 | ||
309 | #define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 | ||
310 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 | ||
311 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 | ||
312 | #define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) << 29) & 0x20000000) | ||
313 | #define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v) ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000) | ||
314 | #define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 | ||
315 | #define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000 | ||
316 | #define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) << 16) & 0xff0000) | ||
317 | #define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15 | ||
318 | #define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000 | ||
319 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 | ||
320 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 | ||
321 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) << 15) & 0x8000) | ||
322 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000) | ||
323 | #define BP_I2C_STAT_SLAVE_FOUND 14 | ||
324 | #define BM_I2C_STAT_SLAVE_FOUND 0x4000 | ||
325 | #define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 | ||
326 | #define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 | ||
327 | #define BF_I2C_STAT_SLAVE_FOUND(v) (((v) << 14) & 0x4000) | ||
328 | #define BF_I2C_STAT_SLAVE_FOUND_V(v) ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000) | ||
329 | #define BP_I2C_STAT_SLAVE_SEARCHING 13 | ||
330 | #define BM_I2C_STAT_SLAVE_SEARCHING 0x2000 | ||
331 | #define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 | ||
332 | #define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 | ||
333 | #define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) << 13) & 0x2000) | ||
334 | #define BF_I2C_STAT_SLAVE_SEARCHING_V(v) ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000) | ||
335 | #define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12 | ||
336 | #define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000 | ||
337 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 | ||
338 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 | ||
339 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) << 12) & 0x1000) | ||
340 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000) | ||
341 | #define BP_I2C_STAT_BUS_BUSY 11 | ||
342 | #define BM_I2C_STAT_BUS_BUSY 0x800 | ||
343 | #define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 | ||
344 | #define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 | ||
345 | #define BF_I2C_STAT_BUS_BUSY(v) (((v) << 11) & 0x800) | ||
346 | #define BF_I2C_STAT_BUS_BUSY_V(v) ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800) | ||
347 | #define BP_I2C_STAT_CLK_GEN_BUSY 10 | ||
348 | #define BM_I2C_STAT_CLK_GEN_BUSY 0x400 | ||
349 | #define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 | ||
350 | #define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 | ||
351 | #define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) << 10) & 0x400) | ||
352 | #define BF_I2C_STAT_CLK_GEN_BUSY_V(v) ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400) | ||
353 | #define BP_I2C_STAT_DATA_ENGINE_BUSY 9 | ||
354 | #define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200 | ||
355 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 | ||
356 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 | ||
357 | #define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) << 9) & 0x200) | ||
358 | #define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v) ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200) | ||
359 | #define BP_I2C_STAT_SLAVE_BUSY 8 | ||
360 | #define BM_I2C_STAT_SLAVE_BUSY 0x100 | ||
361 | #define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 | ||
362 | #define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 | ||
363 | #define BF_I2C_STAT_SLAVE_BUSY(v) (((v) << 8) & 0x100) | ||
364 | #define BF_I2C_STAT_SLAVE_BUSY_V(v) ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100) | ||
365 | #define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7 | ||
366 | #define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80 | ||
367 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
368 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 | ||
369 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) << 7) & 0x80) | ||
370 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80) | ||
371 | #define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6 | ||
372 | #define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40 | ||
373 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
374 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 | ||
375 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) << 6) & 0x40) | ||
376 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40) | ||
377 | #define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5 | ||
378 | #define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20 | ||
379 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
380 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 | ||
381 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) << 5) & 0x20) | ||
382 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20) | ||
383 | #define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4 | ||
384 | #define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10 | ||
385 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
386 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
387 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) << 4) & 0x10) | ||
388 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10) | ||
389 | #define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3 | ||
390 | #define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8 | ||
391 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
392 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
393 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
394 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8) | ||
395 | #define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2 | ||
396 | #define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4 | ||
397 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
398 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
399 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
400 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
401 | #define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1 | ||
402 | #define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2 | ||
403 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
404 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 | ||
405 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
406 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2) | ||
407 | #define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0 | ||
408 | #define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1 | ||
409 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
410 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 | ||
411 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) << 0) & 0x1) | ||
412 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1) | ||
413 | |||
414 | /** | ||
415 | * Register: HW_I2C_DATA | ||
416 | * Address: 0x60 | ||
417 | * SCT: no | ||
418 | */ | ||
419 | #define HW_I2C_DATA (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60)) | ||
420 | #define BP_I2C_DATA_DATA 0 | ||
421 | #define BM_I2C_DATA_DATA 0xffffffff | ||
422 | #define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
423 | |||
424 | /** | ||
425 | * Register: HW_I2C_DEBUG0 | ||
426 | * Address: 0x70 | ||
427 | * SCT: yes | ||
428 | */ | ||
429 | #define HW_I2C_DEBUG0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0)) | ||
430 | #define HW_I2C_DEBUG0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4)) | ||
431 | #define HW_I2C_DEBUG0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8)) | ||
432 | #define HW_I2C_DEBUG0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc)) | ||
433 | #define BP_I2C_DEBUG0_DMAREQ 31 | ||
434 | #define BM_I2C_DEBUG0_DMAREQ 0x80000000 | ||
435 | #define BF_I2C_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
436 | #define BP_I2C_DEBUG0_DMAENDCMD 30 | ||
437 | #define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 | ||
438 | #define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) << 30) & 0x40000000) | ||
439 | #define BP_I2C_DEBUG0_DMAKICK 29 | ||
440 | #define BM_I2C_DEBUG0_DMAKICK 0x20000000 | ||
441 | #define BF_I2C_DEBUG0_DMAKICK(v) (((v) << 29) & 0x20000000) | ||
442 | #define BP_I2C_DEBUG0_TBD 26 | ||
443 | #define BM_I2C_DEBUG0_TBD 0x1c000000 | ||
444 | #define BF_I2C_DEBUG0_TBD(v) (((v) << 26) & 0x1c000000) | ||
445 | #define BP_I2C_DEBUG0_DMA_STATE 16 | ||
446 | #define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000 | ||
447 | #define BF_I2C_DEBUG0_DMA_STATE(v) (((v) << 16) & 0x3ff0000) | ||
448 | #define BP_I2C_DEBUG0_START_TOGGLE 15 | ||
449 | #define BM_I2C_DEBUG0_START_TOGGLE 0x8000 | ||
450 | #define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) << 15) & 0x8000) | ||
451 | #define BP_I2C_DEBUG0_STOP_TOGGLE 14 | ||
452 | #define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000 | ||
453 | #define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) << 14) & 0x4000) | ||
454 | #define BP_I2C_DEBUG0_GRAB_TOGGLE 13 | ||
455 | #define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000 | ||
456 | #define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) << 13) & 0x2000) | ||
457 | #define BP_I2C_DEBUG0_CHANGE_TOGGLE 12 | ||
458 | #define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000 | ||
459 | #define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) << 12) & 0x1000) | ||
460 | #define BP_I2C_DEBUG0_TESTMODE 11 | ||
461 | #define BM_I2C_DEBUG0_TESTMODE 0x800 | ||
462 | #define BF_I2C_DEBUG0_TESTMODE(v) (((v) << 11) & 0x800) | ||
463 | #define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10 | ||
464 | #define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400 | ||
465 | #define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400) | ||
466 | #define BP_I2C_DEBUG0_SLAVE_STATE 0 | ||
467 | #define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff | ||
468 | #define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) << 0) & 0x3ff) | ||
469 | |||
470 | /** | ||
471 | * Register: HW_I2C_DEBUG1 | ||
472 | * Address: 0x80 | ||
473 | * SCT: yes | ||
474 | */ | ||
475 | #define HW_I2C_DEBUG1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0)) | ||
476 | #define HW_I2C_DEBUG1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4)) | ||
477 | #define HW_I2C_DEBUG1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8)) | ||
478 | #define HW_I2C_DEBUG1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc)) | ||
479 | #define BP_I2C_DEBUG1_I2C_CLK_IN 31 | ||
480 | #define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 | ||
481 | #define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) << 31) & 0x80000000) | ||
482 | #define BP_I2C_DEBUG1_I2C_DATA_IN 30 | ||
483 | #define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 | ||
484 | #define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) << 30) & 0x40000000) | ||
485 | #define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 | ||
486 | #define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000 | ||
487 | #define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) << 24) & 0xf000000) | ||
488 | #define BP_I2C_DEBUG1_CLK_GEN_STATE 16 | ||
489 | #define BM_I2C_DEBUG1_CLK_GEN_STATE 0x7f0000 | ||
490 | #define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) << 16) & 0x7f0000) | ||
491 | #define BP_I2C_DEBUG1_LST_MODE 9 | ||
492 | #define BM_I2C_DEBUG1_LST_MODE 0x600 | ||
493 | #define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 | ||
494 | #define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 | ||
495 | #define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 | ||
496 | #define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 | ||
497 | #define BF_I2C_DEBUG1_LST_MODE(v) (((v) << 9) & 0x600) | ||
498 | #define BF_I2C_DEBUG1_LST_MODE_V(v) ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600) | ||
499 | #define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8 | ||
500 | #define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100 | ||
501 | #define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) << 8) & 0x100) | ||
502 | #define BP_I2C_DEBUG1_FORCE_CLK_ON 5 | ||
503 | #define BM_I2C_DEBUG1_FORCE_CLK_ON 0x20 | ||
504 | #define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) << 5) & 0x20) | ||
505 | #define BP_I2C_DEBUG1_FORCE_CLK_IDLE 4 | ||
506 | #define BM_I2C_DEBUG1_FORCE_CLK_IDLE 0x10 | ||
507 | #define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v) (((v) << 4) & 0x10) | ||
508 | #define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3 | ||
509 | #define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8 | ||
510 | #define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) << 3) & 0x8) | ||
511 | #define BP_I2C_DEBUG1_FORCE_RCV_ACK 2 | ||
512 | #define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4 | ||
513 | #define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) << 2) & 0x4) | ||
514 | #define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1 | ||
515 | #define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2 | ||
516 | #define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) << 1) & 0x2) | ||
517 | #define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0 | ||
518 | #define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1 | ||
519 | #define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) << 0) & 0x1) | ||
520 | |||
521 | /** | ||
522 | * Register: HW_I2C_VERSION | ||
523 | * Address: 0x90 | ||
524 | * SCT: no | ||
525 | */ | ||
526 | #define HW_I2C_VERSION (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90)) | ||
527 | #define BP_I2C_VERSION_MAJOR 24 | ||
528 | #define BM_I2C_VERSION_MAJOR 0xff000000 | ||
529 | #define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
530 | #define BP_I2C_VERSION_MINOR 16 | ||
531 | #define BM_I2C_VERSION_MINOR 0xff0000 | ||
532 | #define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
533 | #define BP_I2C_VERSION_STEP 0 | ||
534 | #define BM_I2C_VERSION_STEP 0xffff | ||
535 | #define BF_I2C_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
536 | |||
537 | #endif /* __HEADERGEN__STMP3700__I2C__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h new file mode 100644 index 0000000000..a4b7d51519 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h | |||
@@ -0,0 +1,410 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__ICOLL__H__ | ||
24 | #define __HEADERGEN__STMP3700__ICOLL__H__ | ||
25 | |||
26 | #define REGS_ICOLL_BASE (0x80000000) | ||
27 | |||
28 | #define REGS_ICOLL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_ICOLL_VECTOR | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_ICOLL_VECTOR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_ICOLL_VECTOR_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_ICOLL_VECTOR_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_ICOLL_VECTOR_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_ICOLL_VECTOR_IRQVECTOR 2 | ||
40 | #define BM_ICOLL_VECTOR_IRQVECTOR 0xfffffffc | ||
41 | #define BF_ICOLL_VECTOR_IRQVECTOR(v) (((v) << 2) & 0xfffffffc) | ||
42 | |||
43 | /** | ||
44 | * Register: HW_ICOLL_LEVELACK | ||
45 | * Address: 0x10 | ||
46 | * SCT: no | ||
47 | */ | ||
48 | #define HW_ICOLL_LEVELACK (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10)) | ||
49 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 | ||
50 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0xf | ||
51 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | ||
52 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 | ||
53 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 | ||
54 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 | ||
55 | #define BF_ICOLL_LEVELACK_IRQLEVELACK(v) (((v) << 0) & 0xf) | ||
56 | #define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v) ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_ICOLL_CTRL | ||
60 | * Address: 0x20 | ||
61 | * SCT: yes | ||
62 | */ | ||
63 | #define HW_ICOLL_CTRL (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0)) | ||
64 | #define HW_ICOLL_CTRL_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4)) | ||
65 | #define HW_ICOLL_CTRL_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8)) | ||
66 | #define HW_ICOLL_CTRL_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc)) | ||
67 | #define BP_ICOLL_CTRL_SFTRST 31 | ||
68 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 | ||
69 | #define BV_ICOLL_CTRL_SFTRST__RUN 0x0 | ||
70 | #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 | ||
71 | #define BF_ICOLL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
72 | #define BF_ICOLL_CTRL_SFTRST_V(v) ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
73 | #define BP_ICOLL_CTRL_CLKGATE 30 | ||
74 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 | ||
75 | #define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 | ||
76 | #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 | ||
77 | #define BF_ICOLL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
78 | #define BF_ICOLL_CTRL_CLKGATE_V(v) ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
79 | #define BP_ICOLL_CTRL_VECTOR_PITCH 21 | ||
80 | #define BM_ICOLL_CTRL_VECTOR_PITCH 0xe00000 | ||
81 | #define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 | ||
82 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 | ||
83 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 | ||
84 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 | ||
85 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 | ||
86 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 | ||
87 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 | ||
88 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 | ||
89 | #define BF_ICOLL_CTRL_VECTOR_PITCH(v) (((v) << 21) & 0xe00000) | ||
90 | #define BF_ICOLL_CTRL_VECTOR_PITCH_V(v) ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000) | ||
91 | #define BP_ICOLL_CTRL_BYPASS_FSM 20 | ||
92 | #define BM_ICOLL_CTRL_BYPASS_FSM 0x100000 | ||
93 | #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 | ||
94 | #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 | ||
95 | #define BF_ICOLL_CTRL_BYPASS_FSM(v) (((v) << 20) & 0x100000) | ||
96 | #define BF_ICOLL_CTRL_BYPASS_FSM_V(v) ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000) | ||
97 | #define BP_ICOLL_CTRL_NO_NESTING 19 | ||
98 | #define BM_ICOLL_CTRL_NO_NESTING 0x80000 | ||
99 | #define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 | ||
100 | #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 | ||
101 | #define BF_ICOLL_CTRL_NO_NESTING(v) (((v) << 19) & 0x80000) | ||
102 | #define BF_ICOLL_CTRL_NO_NESTING_V(v) ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000) | ||
103 | #define BP_ICOLL_CTRL_ARM_RSE_MODE 18 | ||
104 | #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x40000 | ||
105 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE 0x0 | ||
106 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT 0x1 | ||
107 | #define BF_ICOLL_CTRL_ARM_RSE_MODE(v) (((v) << 18) & 0x40000) | ||
108 | #define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v) ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000) | ||
109 | #define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE 17 | ||
110 | #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x20000 | ||
111 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 | ||
112 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 | ||
113 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v) (((v) << 17) & 0x20000) | ||
114 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000) | ||
115 | #define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE 16 | ||
116 | #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x10000 | ||
117 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 | ||
118 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 | ||
119 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v) (((v) << 16) & 0x10000) | ||
120 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000) | ||
121 | #define BP_ICOLL_CTRL_ENABLE2FIQ35 7 | ||
122 | #define BM_ICOLL_CTRL_ENABLE2FIQ35 0x80 | ||
123 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE 0x0 | ||
124 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE 0x1 | ||
125 | #define BF_ICOLL_CTRL_ENABLE2FIQ35(v) (((v) << 7) & 0x80) | ||
126 | #define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 7) & 0x80) | ||
127 | #define BP_ICOLL_CTRL_ENABLE2FIQ34 6 | ||
128 | #define BM_ICOLL_CTRL_ENABLE2FIQ34 0x40 | ||
129 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE 0x0 | ||
130 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE 0x1 | ||
131 | #define BF_ICOLL_CTRL_ENABLE2FIQ34(v) (((v) << 6) & 0x40) | ||
132 | #define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 6) & 0x40) | ||
133 | #define BP_ICOLL_CTRL_ENABLE2FIQ33 5 | ||
134 | #define BM_ICOLL_CTRL_ENABLE2FIQ33 0x20 | ||
135 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE 0x0 | ||
136 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE 0x1 | ||
137 | #define BF_ICOLL_CTRL_ENABLE2FIQ33(v) (((v) << 5) & 0x20) | ||
138 | #define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 5) & 0x20) | ||
139 | #define BP_ICOLL_CTRL_ENABLE2FIQ32 4 | ||
140 | #define BM_ICOLL_CTRL_ENABLE2FIQ32 0x10 | ||
141 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE 0x0 | ||
142 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE 0x1 | ||
143 | #define BF_ICOLL_CTRL_ENABLE2FIQ32(v) (((v) << 4) & 0x10) | ||
144 | #define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 4) & 0x10) | ||
145 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T3 3 | ||
146 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T3 0x8 | ||
147 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T3__DISABLE 0x0 | ||
148 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T3__ENABLE 0x1 | ||
149 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T3(v) (((v) << 3) & 0x8) | ||
150 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T3_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T3__##v << 3) & 0x8) | ||
151 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T2 2 | ||
152 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T2 0x4 | ||
153 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T2__DISABLE 0x0 | ||
154 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T2__ENABLE 0x1 | ||
155 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T2(v) (((v) << 2) & 0x4) | ||
156 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T2_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T2__##v << 2) & 0x4) | ||
157 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T1 1 | ||
158 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T1 0x2 | ||
159 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T1__DISABLE 0x0 | ||
160 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T1__ENABLE 0x1 | ||
161 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T1(v) (((v) << 1) & 0x2) | ||
162 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T1_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T1__##v << 1) & 0x2) | ||
163 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T0 0 | ||
164 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T0 0x1 | ||
165 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T0__DISABLE 0x0 | ||
166 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T0__ENABLE 0x1 | ||
167 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T0(v) (((v) << 0) & 0x1) | ||
168 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T0_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T0__##v << 0) & 0x1) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_ICOLL_STAT | ||
172 | * Address: 0x30 | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_ICOLL_STAT (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30)) | ||
176 | #define BP_ICOLL_STAT_VECTOR_NUMBER 0 | ||
177 | #define BM_ICOLL_STAT_VECTOR_NUMBER 0x3f | ||
178 | #define BF_ICOLL_STAT_VECTOR_NUMBER(v) (((v) << 0) & 0x3f) | ||
179 | |||
180 | /** | ||
181 | * Register: HW_ICOLL_RAWn | ||
182 | * Address: 0x40+n*0x10 | ||
183 | * SCT: no | ||
184 | */ | ||
185 | #define HW_ICOLL_RAWn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10)) | ||
186 | #define BP_ICOLL_RAWn_RAW_IRQS 0 | ||
187 | #define BM_ICOLL_RAWn_RAW_IRQS 0xffffffff | ||
188 | #define BF_ICOLL_RAWn_RAW_IRQS(v) (((v) << 0) & 0xffffffff) | ||
189 | |||
190 | /** | ||
191 | * Register: HW_ICOLL_PRIORITYn | ||
192 | * Address: 0x60+n*0x10 | ||
193 | * SCT: yes | ||
194 | */ | ||
195 | #define HW_ICOLL_PRIORITYn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0)) | ||
196 | #define HW_ICOLL_PRIORITYn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4)) | ||
197 | #define HW_ICOLL_PRIORITYn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8)) | ||
198 | #define HW_ICOLL_PRIORITYn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc)) | ||
199 | #define BP_ICOLL_PRIORITYn_SOFTIRQ3 27 | ||
200 | #define BM_ICOLL_PRIORITYn_SOFTIRQ3 0x8000000 | ||
201 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT 0x0 | ||
202 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT 0x1 | ||
203 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3(v) (((v) << 27) & 0x8000000) | ||
204 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000) | ||
205 | #define BP_ICOLL_PRIORITYn_ENABLE3 26 | ||
206 | #define BM_ICOLL_PRIORITYn_ENABLE3 0x4000000 | ||
207 | #define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE 0x0 | ||
208 | #define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE 0x1 | ||
209 | #define BF_ICOLL_PRIORITYn_ENABLE3(v) (((v) << 26) & 0x4000000) | ||
210 | #define BF_ICOLL_PRIORITYn_ENABLE3_V(v) ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000) | ||
211 | #define BP_ICOLL_PRIORITYn_PRIORITY3 24 | ||
212 | #define BM_ICOLL_PRIORITYn_PRIORITY3 0x3000000 | ||
213 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0 0x0 | ||
214 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1 0x1 | ||
215 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2 0x2 | ||
216 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3 0x3 | ||
217 | #define BF_ICOLL_PRIORITYn_PRIORITY3(v) (((v) << 24) & 0x3000000) | ||
218 | #define BF_ICOLL_PRIORITYn_PRIORITY3_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000) | ||
219 | #define BP_ICOLL_PRIORITYn_SOFTIRQ2 19 | ||
220 | #define BM_ICOLL_PRIORITYn_SOFTIRQ2 0x80000 | ||
221 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT 0x0 | ||
222 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT 0x1 | ||
223 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2(v) (((v) << 19) & 0x80000) | ||
224 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000) | ||
225 | #define BP_ICOLL_PRIORITYn_ENABLE2 18 | ||
226 | #define BM_ICOLL_PRIORITYn_ENABLE2 0x40000 | ||
227 | #define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE 0x0 | ||
228 | #define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE 0x1 | ||
229 | #define BF_ICOLL_PRIORITYn_ENABLE2(v) (((v) << 18) & 0x40000) | ||
230 | #define BF_ICOLL_PRIORITYn_ENABLE2_V(v) ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000) | ||
231 | #define BP_ICOLL_PRIORITYn_PRIORITY2 16 | ||
232 | #define BM_ICOLL_PRIORITYn_PRIORITY2 0x30000 | ||
233 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0 0x0 | ||
234 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1 0x1 | ||
235 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2 0x2 | ||
236 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3 0x3 | ||
237 | #define BF_ICOLL_PRIORITYn_PRIORITY2(v) (((v) << 16) & 0x30000) | ||
238 | #define BF_ICOLL_PRIORITYn_PRIORITY2_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000) | ||
239 | #define BP_ICOLL_PRIORITYn_SOFTIRQ1 11 | ||
240 | #define BM_ICOLL_PRIORITYn_SOFTIRQ1 0x800 | ||
241 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT 0x0 | ||
242 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT 0x1 | ||
243 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1(v) (((v) << 11) & 0x800) | ||
244 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800) | ||
245 | #define BP_ICOLL_PRIORITYn_ENABLE1 10 | ||
246 | #define BM_ICOLL_PRIORITYn_ENABLE1 0x400 | ||
247 | #define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE 0x0 | ||
248 | #define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE 0x1 | ||
249 | #define BF_ICOLL_PRIORITYn_ENABLE1(v) (((v) << 10) & 0x400) | ||
250 | #define BF_ICOLL_PRIORITYn_ENABLE1_V(v) ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400) | ||
251 | #define BP_ICOLL_PRIORITYn_PRIORITY1 8 | ||
252 | #define BM_ICOLL_PRIORITYn_PRIORITY1 0x300 | ||
253 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0 0x0 | ||
254 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1 0x1 | ||
255 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2 0x2 | ||
256 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3 0x3 | ||
257 | #define BF_ICOLL_PRIORITYn_PRIORITY1(v) (((v) << 8) & 0x300) | ||
258 | #define BF_ICOLL_PRIORITYn_PRIORITY1_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300) | ||
259 | #define BP_ICOLL_PRIORITYn_SOFTIRQ0 3 | ||
260 | #define BM_ICOLL_PRIORITYn_SOFTIRQ0 0x8 | ||
261 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT 0x0 | ||
262 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT 0x1 | ||
263 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0(v) (((v) << 3) & 0x8) | ||
264 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8) | ||
265 | #define BP_ICOLL_PRIORITYn_ENABLE0 2 | ||
266 | #define BM_ICOLL_PRIORITYn_ENABLE0 0x4 | ||
267 | #define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE 0x0 | ||
268 | #define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE 0x1 | ||
269 | #define BF_ICOLL_PRIORITYn_ENABLE0(v) (((v) << 2) & 0x4) | ||
270 | #define BF_ICOLL_PRIORITYn_ENABLE0_V(v) ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4) | ||
271 | #define BP_ICOLL_PRIORITYn_PRIORITY0 0 | ||
272 | #define BM_ICOLL_PRIORITYn_PRIORITY0 0x3 | ||
273 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0 0x0 | ||
274 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1 0x1 | ||
275 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2 0x2 | ||
276 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3 0x3 | ||
277 | #define BF_ICOLL_PRIORITYn_PRIORITY0(v) (((v) << 0) & 0x3) | ||
278 | #define BF_ICOLL_PRIORITYn_PRIORITY0_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3) | ||
279 | |||
280 | /** | ||
281 | * Register: HW_ICOLL_VBASE | ||
282 | * Address: 0x160 | ||
283 | * SCT: yes | ||
284 | */ | ||
285 | #define HW_ICOLL_VBASE (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0)) | ||
286 | #define HW_ICOLL_VBASE_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4)) | ||
287 | #define HW_ICOLL_VBASE_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8)) | ||
288 | #define HW_ICOLL_VBASE_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc)) | ||
289 | #define BP_ICOLL_VBASE_TABLE_ADDRESS 2 | ||
290 | #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xfffffffc | ||
291 | #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
292 | |||
293 | /** | ||
294 | * Register: HW_ICOLL_DEBUG | ||
295 | * Address: 0x170 | ||
296 | * SCT: no | ||
297 | */ | ||
298 | #define HW_ICOLL_DEBUG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170)) | ||
299 | #define BP_ICOLL_DEBUG_INSERVICE 28 | ||
300 | #define BM_ICOLL_DEBUG_INSERVICE 0xf0000000 | ||
301 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 | ||
302 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 | ||
303 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 | ||
304 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 | ||
305 | #define BF_ICOLL_DEBUG_INSERVICE(v) (((v) << 28) & 0xf0000000) | ||
306 | #define BF_ICOLL_DEBUG_INSERVICE_V(v) ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000) | ||
307 | #define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 | ||
308 | #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0xf000000 | ||
309 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 | ||
310 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 | ||
311 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 | ||
312 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 | ||
313 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) (((v) << 24) & 0xf000000) | ||
314 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v) ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000) | ||
315 | #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 | ||
316 | #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0xf00000 | ||
317 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 | ||
318 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 | ||
319 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 | ||
320 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 | ||
321 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) (((v) << 20) & 0xf00000) | ||
322 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v) ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000) | ||
323 | #define BP_ICOLL_DEBUG_FIQ 17 | ||
324 | #define BM_ICOLL_DEBUG_FIQ 0x20000 | ||
325 | #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 | ||
326 | #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 | ||
327 | #define BF_ICOLL_DEBUG_FIQ(v) (((v) << 17) & 0x20000) | ||
328 | #define BF_ICOLL_DEBUG_FIQ_V(v) ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000) | ||
329 | #define BP_ICOLL_DEBUG_IRQ 16 | ||
330 | #define BM_ICOLL_DEBUG_IRQ 0x10000 | ||
331 | #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 | ||
332 | #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 | ||
333 | #define BF_ICOLL_DEBUG_IRQ(v) (((v) << 16) & 0x10000) | ||
334 | #define BF_ICOLL_DEBUG_IRQ_V(v) ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000) | ||
335 | #define BP_ICOLL_DEBUG_VECTOR_FSM 0 | ||
336 | #define BM_ICOLL_DEBUG_VECTOR_FSM 0x3ff | ||
337 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x0 | ||
338 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x1 | ||
339 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x2 | ||
340 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x4 | ||
341 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x8 | ||
342 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x10 | ||
343 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20 | ||
344 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40 | ||
345 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80 | ||
346 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 | ||
347 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 | ||
348 | #define BF_ICOLL_DEBUG_VECTOR_FSM(v) (((v) << 0) & 0x3ff) | ||
349 | #define BF_ICOLL_DEBUG_VECTOR_FSM_V(v) ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff) | ||
350 | |||
351 | /** | ||
352 | * Register: HW_ICOLL_DBGREAD0 | ||
353 | * Address: 0x180 | ||
354 | * SCT: no | ||
355 | */ | ||
356 | #define HW_ICOLL_DBGREAD0 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180)) | ||
357 | #define BP_ICOLL_DBGREAD0_VALUE 0 | ||
358 | #define BM_ICOLL_DBGREAD0_VALUE 0xffffffff | ||
359 | #define BF_ICOLL_DBGREAD0_VALUE(v) (((v) << 0) & 0xffffffff) | ||
360 | |||
361 | /** | ||
362 | * Register: HW_ICOLL_DBGREAD1 | ||
363 | * Address: 0x190 | ||
364 | * SCT: no | ||
365 | */ | ||
366 | #define HW_ICOLL_DBGREAD1 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x190)) | ||
367 | #define BP_ICOLL_DBGREAD1_VALUE 0 | ||
368 | #define BM_ICOLL_DBGREAD1_VALUE 0xffffffff | ||
369 | #define BF_ICOLL_DBGREAD1_VALUE(v) (((v) << 0) & 0xffffffff) | ||
370 | |||
371 | /** | ||
372 | * Register: HW_ICOLL_DBGFLAG | ||
373 | * Address: 0x1a0 | ||
374 | * SCT: yes | ||
375 | */ | ||
376 | #define HW_ICOLL_DBGFLAG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0)) | ||
377 | #define HW_ICOLL_DBGFLAG_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4)) | ||
378 | #define HW_ICOLL_DBGFLAG_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8)) | ||
379 | #define HW_ICOLL_DBGFLAG_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc)) | ||
380 | #define BP_ICOLL_DBGFLAG_FLAG 0 | ||
381 | #define BM_ICOLL_DBGFLAG_FLAG 0xffff | ||
382 | #define BF_ICOLL_DBGFLAG_FLAG(v) (((v) << 0) & 0xffff) | ||
383 | |||
384 | /** | ||
385 | * Register: HW_ICOLL_DBGREQUESTn | ||
386 | * Address: 0x1b0+n*0x10 | ||
387 | * SCT: no | ||
388 | */ | ||
389 | #define HW_ICOLL_DBGREQUESTn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10)) | ||
390 | #define BP_ICOLL_DBGREQUESTn_BITS 0 | ||
391 | #define BM_ICOLL_DBGREQUESTn_BITS 0xffffffff | ||
392 | #define BF_ICOLL_DBGREQUESTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
393 | |||
394 | /** | ||
395 | * Register: HW_ICOLL_VERSION | ||
396 | * Address: 0x1d0 | ||
397 | * SCT: no | ||
398 | */ | ||
399 | #define HW_ICOLL_VERSION (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1d0)) | ||
400 | #define BP_ICOLL_VERSION_MAJOR 24 | ||
401 | #define BM_ICOLL_VERSION_MAJOR 0xff000000 | ||
402 | #define BF_ICOLL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
403 | #define BP_ICOLL_VERSION_MINOR 16 | ||
404 | #define BM_ICOLL_VERSION_MINOR 0xff0000 | ||
405 | #define BF_ICOLL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
406 | #define BP_ICOLL_VERSION_STEP 0 | ||
407 | #define BM_ICOLL_VERSION_STEP 0xffff | ||
408 | #define BF_ICOLL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
409 | |||
410 | #endif /* __HEADERGEN__STMP3700__ICOLL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h new file mode 100644 index 0000000000..d7c14dcecf --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h | |||
@@ -0,0 +1,493 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__IR__H__ | ||
24 | #define __HEADERGEN__STMP3700__IR__H__ | ||
25 | |||
26 | #define REGS_IR_BASE (0x80078000) | ||
27 | |||
28 | #define REGS_IR_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_IR_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_IR_CTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0)) | ||
36 | #define HW_IR_CTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4)) | ||
37 | #define HW_IR_CTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8)) | ||
38 | #define HW_IR_CTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc)) | ||
39 | #define BP_IR_CTRL_SFTRST 31 | ||
40 | #define BM_IR_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_IR_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_IR_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_IR_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_IR_CTRL_SFTRST_V(v) ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_IR_CTRL_CLKGATE 30 | ||
46 | #define BM_IR_CTRL_CLKGATE 0x40000000 | ||
47 | #define BF_IR_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
48 | #define BP_IR_CTRL_MTA 24 | ||
49 | #define BM_IR_CTRL_MTA 0x7000000 | ||
50 | #define BV_IR_CTRL_MTA__MTA_10MS 0x0 | ||
51 | #define BV_IR_CTRL_MTA__MTA_5MS 0x1 | ||
52 | #define BV_IR_CTRL_MTA__MTA_1MS 0x2 | ||
53 | #define BV_IR_CTRL_MTA__MTA_500US 0x3 | ||
54 | #define BV_IR_CTRL_MTA__MTA_100US 0x4 | ||
55 | #define BV_IR_CTRL_MTA__MTA_50US 0x5 | ||
56 | #define BV_IR_CTRL_MTA__MTA_10US 0x6 | ||
57 | #define BV_IR_CTRL_MTA__MTA_0 0x7 | ||
58 | #define BF_IR_CTRL_MTA(v) (((v) << 24) & 0x7000000) | ||
59 | #define BF_IR_CTRL_MTA_V(v) ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000) | ||
60 | #define BP_IR_CTRL_MODE 22 | ||
61 | #define BM_IR_CTRL_MODE 0xc00000 | ||
62 | #define BV_IR_CTRL_MODE__SIR 0x0 | ||
63 | #define BV_IR_CTRL_MODE__MIR 0x1 | ||
64 | #define BV_IR_CTRL_MODE__FIR 0x2 | ||
65 | #define BV_IR_CTRL_MODE__VFIR 0x3 | ||
66 | #define BF_IR_CTRL_MODE(v) (((v) << 22) & 0xc00000) | ||
67 | #define BF_IR_CTRL_MODE_V(v) ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000) | ||
68 | #define BP_IR_CTRL_SPEED 19 | ||
69 | #define BM_IR_CTRL_SPEED 0x380000 | ||
70 | #define BV_IR_CTRL_SPEED__SPD000 0x0 | ||
71 | #define BV_IR_CTRL_SPEED__SPD001 0x1 | ||
72 | #define BV_IR_CTRL_SPEED__SPD010 0x2 | ||
73 | #define BV_IR_CTRL_SPEED__SPD011 0x3 | ||
74 | #define BV_IR_CTRL_SPEED__SPD100 0x4 | ||
75 | #define BV_IR_CTRL_SPEED__SPD101 0x5 | ||
76 | #define BF_IR_CTRL_SPEED(v) (((v) << 19) & 0x380000) | ||
77 | #define BF_IR_CTRL_SPEED_V(v) ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000) | ||
78 | #define BP_IR_CTRL_TC_TIME_DIV 8 | ||
79 | #define BM_IR_CTRL_TC_TIME_DIV 0x3f00 | ||
80 | #define BF_IR_CTRL_TC_TIME_DIV(v) (((v) << 8) & 0x3f00) | ||
81 | #define BP_IR_CTRL_TC_TYPE 7 | ||
82 | #define BM_IR_CTRL_TC_TYPE 0x80 | ||
83 | #define BF_IR_CTRL_TC_TYPE(v) (((v) << 7) & 0x80) | ||
84 | #define BP_IR_CTRL_SIR_GAP 4 | ||
85 | #define BM_IR_CTRL_SIR_GAP 0x70 | ||
86 | #define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0 | ||
87 | #define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1 | ||
88 | #define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2 | ||
89 | #define BV_IR_CTRL_SIR_GAP__GAP_500 0x3 | ||
90 | #define BV_IR_CTRL_SIR_GAP__GAP_100 0x4 | ||
91 | #define BV_IR_CTRL_SIR_GAP__GAP_50 0x5 | ||
92 | #define BV_IR_CTRL_SIR_GAP__GAP_10 0x6 | ||
93 | #define BV_IR_CTRL_SIR_GAP__GAP_0 0x7 | ||
94 | #define BF_IR_CTRL_SIR_GAP(v) (((v) << 4) & 0x70) | ||
95 | #define BF_IR_CTRL_SIR_GAP_V(v) ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70) | ||
96 | #define BP_IR_CTRL_SIPEN 3 | ||
97 | #define BM_IR_CTRL_SIPEN 0x8 | ||
98 | #define BF_IR_CTRL_SIPEN(v) (((v) << 3) & 0x8) | ||
99 | #define BP_IR_CTRL_TCEN 2 | ||
100 | #define BM_IR_CTRL_TCEN 0x4 | ||
101 | #define BF_IR_CTRL_TCEN(v) (((v) << 2) & 0x4) | ||
102 | #define BP_IR_CTRL_TXEN 1 | ||
103 | #define BM_IR_CTRL_TXEN 0x2 | ||
104 | #define BF_IR_CTRL_TXEN(v) (((v) << 1) & 0x2) | ||
105 | #define BP_IR_CTRL_RXEN 0 | ||
106 | #define BM_IR_CTRL_RXEN 0x1 | ||
107 | #define BF_IR_CTRL_RXEN(v) (((v) << 0) & 0x1) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_IR_TXDMA | ||
111 | * Address: 0x10 | ||
112 | * SCT: yes | ||
113 | */ | ||
114 | #define HW_IR_TXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0)) | ||
115 | #define HW_IR_TXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4)) | ||
116 | #define HW_IR_TXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8)) | ||
117 | #define HW_IR_TXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc)) | ||
118 | #define BP_IR_TXDMA_RUN 31 | ||
119 | #define BM_IR_TXDMA_RUN 0x80000000 | ||
120 | #define BF_IR_TXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
121 | #define BP_IR_TXDMA_EMPTY 29 | ||
122 | #define BM_IR_TXDMA_EMPTY 0x20000000 | ||
123 | #define BF_IR_TXDMA_EMPTY(v) (((v) << 29) & 0x20000000) | ||
124 | #define BP_IR_TXDMA_INT 28 | ||
125 | #define BM_IR_TXDMA_INT 0x10000000 | ||
126 | #define BF_IR_TXDMA_INT(v) (((v) << 28) & 0x10000000) | ||
127 | #define BP_IR_TXDMA_CHANGE 27 | ||
128 | #define BM_IR_TXDMA_CHANGE 0x8000000 | ||
129 | #define BF_IR_TXDMA_CHANGE(v) (((v) << 27) & 0x8000000) | ||
130 | #define BP_IR_TXDMA_NEW_MTA 24 | ||
131 | #define BM_IR_TXDMA_NEW_MTA 0x7000000 | ||
132 | #define BF_IR_TXDMA_NEW_MTA(v) (((v) << 24) & 0x7000000) | ||
133 | #define BP_IR_TXDMA_NEW_MODE 22 | ||
134 | #define BM_IR_TXDMA_NEW_MODE 0xc00000 | ||
135 | #define BF_IR_TXDMA_NEW_MODE(v) (((v) << 22) & 0xc00000) | ||
136 | #define BP_IR_TXDMA_NEW_SPEED 19 | ||
137 | #define BM_IR_TXDMA_NEW_SPEED 0x380000 | ||
138 | #define BF_IR_TXDMA_NEW_SPEED(v) (((v) << 19) & 0x380000) | ||
139 | #define BP_IR_TXDMA_BOF_TYPE 18 | ||
140 | #define BM_IR_TXDMA_BOF_TYPE 0x40000 | ||
141 | #define BF_IR_TXDMA_BOF_TYPE(v) (((v) << 18) & 0x40000) | ||
142 | #define BP_IR_TXDMA_XBOFS 12 | ||
143 | #define BM_IR_TXDMA_XBOFS 0x3f000 | ||
144 | #define BF_IR_TXDMA_XBOFS(v) (((v) << 12) & 0x3f000) | ||
145 | #define BP_IR_TXDMA_XFER_COUNT 0 | ||
146 | #define BM_IR_TXDMA_XFER_COUNT 0xfff | ||
147 | #define BF_IR_TXDMA_XFER_COUNT(v) (((v) << 0) & 0xfff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_IR_RXDMA | ||
151 | * Address: 0x20 | ||
152 | * SCT: yes | ||
153 | */ | ||
154 | #define HW_IR_RXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0)) | ||
155 | #define HW_IR_RXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4)) | ||
156 | #define HW_IR_RXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8)) | ||
157 | #define HW_IR_RXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc)) | ||
158 | #define BP_IR_RXDMA_RUN 31 | ||
159 | #define BM_IR_RXDMA_RUN 0x80000000 | ||
160 | #define BF_IR_RXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
161 | #define BP_IR_RXDMA_XFER_COUNT 0 | ||
162 | #define BM_IR_RXDMA_XFER_COUNT 0x3ff | ||
163 | #define BF_IR_RXDMA_XFER_COUNT(v) (((v) << 0) & 0x3ff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_IR_DBGCTRL | ||
167 | * Address: 0x30 | ||
168 | * SCT: yes | ||
169 | */ | ||
170 | #define HW_IR_DBGCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0)) | ||
171 | #define HW_IR_DBGCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4)) | ||
172 | #define HW_IR_DBGCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8)) | ||
173 | #define HW_IR_DBGCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc)) | ||
174 | #define BP_IR_DBGCTRL_VFIRSWZ 12 | ||
175 | #define BM_IR_DBGCTRL_VFIRSWZ 0x1000 | ||
176 | #define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0 | ||
177 | #define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1 | ||
178 | #define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) << 12) & 0x1000) | ||
179 | #define BF_IR_DBGCTRL_VFIRSWZ_V(v) ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000) | ||
180 | #define BP_IR_DBGCTRL_RXFRMOFF 11 | ||
181 | #define BM_IR_DBGCTRL_RXFRMOFF 0x800 | ||
182 | #define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) << 11) & 0x800) | ||
183 | #define BP_IR_DBGCTRL_RXCRCOFF 10 | ||
184 | #define BM_IR_DBGCTRL_RXCRCOFF 0x400 | ||
185 | #define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) << 10) & 0x400) | ||
186 | #define BP_IR_DBGCTRL_RXINVERT 9 | ||
187 | #define BM_IR_DBGCTRL_RXINVERT 0x200 | ||
188 | #define BF_IR_DBGCTRL_RXINVERT(v) (((v) << 9) & 0x200) | ||
189 | #define BP_IR_DBGCTRL_TXFRMOFF 8 | ||
190 | #define BM_IR_DBGCTRL_TXFRMOFF 0x100 | ||
191 | #define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) << 8) & 0x100) | ||
192 | #define BP_IR_DBGCTRL_TXCRCOFF 7 | ||
193 | #define BM_IR_DBGCTRL_TXCRCOFF 0x80 | ||
194 | #define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) << 7) & 0x80) | ||
195 | #define BP_IR_DBGCTRL_TXINVERT 6 | ||
196 | #define BM_IR_DBGCTRL_TXINVERT 0x40 | ||
197 | #define BF_IR_DBGCTRL_TXINVERT(v) (((v) << 6) & 0x40) | ||
198 | #define BP_IR_DBGCTRL_INTLOOPBACK 5 | ||
199 | #define BM_IR_DBGCTRL_INTLOOPBACK 0x20 | ||
200 | #define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) << 5) & 0x20) | ||
201 | #define BP_IR_DBGCTRL_DUPLEX 4 | ||
202 | #define BM_IR_DBGCTRL_DUPLEX 0x10 | ||
203 | #define BF_IR_DBGCTRL_DUPLEX(v) (((v) << 4) & 0x10) | ||
204 | #define BP_IR_DBGCTRL_MIO_RX 3 | ||
205 | #define BM_IR_DBGCTRL_MIO_RX 0x8 | ||
206 | #define BF_IR_DBGCTRL_MIO_RX(v) (((v) << 3) & 0x8) | ||
207 | #define BP_IR_DBGCTRL_MIO_TX 2 | ||
208 | #define BM_IR_DBGCTRL_MIO_TX 0x4 | ||
209 | #define BF_IR_DBGCTRL_MIO_TX(v) (((v) << 2) & 0x4) | ||
210 | #define BP_IR_DBGCTRL_MIO_SCLK 1 | ||
211 | #define BM_IR_DBGCTRL_MIO_SCLK 0x2 | ||
212 | #define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) << 1) & 0x2) | ||
213 | #define BP_IR_DBGCTRL_MIO_EN 0 | ||
214 | #define BM_IR_DBGCTRL_MIO_EN 0x1 | ||
215 | #define BF_IR_DBGCTRL_MIO_EN(v) (((v) << 0) & 0x1) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_IR_INTR | ||
219 | * Address: 0x40 | ||
220 | * SCT: yes | ||
221 | */ | ||
222 | #define HW_IR_INTR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0)) | ||
223 | #define HW_IR_INTR_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4)) | ||
224 | #define HW_IR_INTR_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8)) | ||
225 | #define HW_IR_INTR_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc)) | ||
226 | #define BP_IR_INTR_RXABORT_IRQ_EN 22 | ||
227 | #define BM_IR_INTR_RXABORT_IRQ_EN 0x400000 | ||
228 | #define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0 | ||
229 | #define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1 | ||
230 | #define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
231 | #define BF_IR_INTR_RXABORT_IRQ_EN_V(v) ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000) | ||
232 | #define BP_IR_INTR_SPEED_IRQ_EN 21 | ||
233 | #define BM_IR_INTR_SPEED_IRQ_EN 0x200000 | ||
234 | #define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0 | ||
235 | #define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1 | ||
236 | #define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
237 | #define BF_IR_INTR_SPEED_IRQ_EN_V(v) ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000) | ||
238 | #define BP_IR_INTR_RXOF_IRQ_EN 20 | ||
239 | #define BM_IR_INTR_RXOF_IRQ_EN 0x100000 | ||
240 | #define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0 | ||
241 | #define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1 | ||
242 | #define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
243 | #define BF_IR_INTR_RXOF_IRQ_EN_V(v) ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000) | ||
244 | #define BP_IR_INTR_TXUF_IRQ_EN 19 | ||
245 | #define BM_IR_INTR_TXUF_IRQ_EN 0x80000 | ||
246 | #define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0 | ||
247 | #define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1 | ||
248 | #define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
249 | #define BF_IR_INTR_TXUF_IRQ_EN_V(v) ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000) | ||
250 | #define BP_IR_INTR_TC_IRQ_EN 18 | ||
251 | #define BM_IR_INTR_TC_IRQ_EN 0x40000 | ||
252 | #define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0 | ||
253 | #define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1 | ||
254 | #define BF_IR_INTR_TC_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
255 | #define BF_IR_INTR_TC_IRQ_EN_V(v) ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000) | ||
256 | #define BP_IR_INTR_RX_IRQ_EN 17 | ||
257 | #define BM_IR_INTR_RX_IRQ_EN 0x20000 | ||
258 | #define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0 | ||
259 | #define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1 | ||
260 | #define BF_IR_INTR_RX_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
261 | #define BF_IR_INTR_RX_IRQ_EN_V(v) ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000) | ||
262 | #define BP_IR_INTR_TX_IRQ_EN 16 | ||
263 | #define BM_IR_INTR_TX_IRQ_EN 0x10000 | ||
264 | #define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0 | ||
265 | #define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1 | ||
266 | #define BF_IR_INTR_TX_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
267 | #define BF_IR_INTR_TX_IRQ_EN_V(v) ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000) | ||
268 | #define BP_IR_INTR_RXABORT_IRQ 6 | ||
269 | #define BM_IR_INTR_RXABORT_IRQ 0x40 | ||
270 | #define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0 | ||
271 | #define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1 | ||
272 | #define BF_IR_INTR_RXABORT_IRQ(v) (((v) << 6) & 0x40) | ||
273 | #define BF_IR_INTR_RXABORT_IRQ_V(v) ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40) | ||
274 | #define BP_IR_INTR_SPEED_IRQ 5 | ||
275 | #define BM_IR_INTR_SPEED_IRQ 0x20 | ||
276 | #define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0 | ||
277 | #define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1 | ||
278 | #define BF_IR_INTR_SPEED_IRQ(v) (((v) << 5) & 0x20) | ||
279 | #define BF_IR_INTR_SPEED_IRQ_V(v) ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20) | ||
280 | #define BP_IR_INTR_RXOF_IRQ 4 | ||
281 | #define BM_IR_INTR_RXOF_IRQ 0x10 | ||
282 | #define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0 | ||
283 | #define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1 | ||
284 | #define BF_IR_INTR_RXOF_IRQ(v) (((v) << 4) & 0x10) | ||
285 | #define BF_IR_INTR_RXOF_IRQ_V(v) ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10) | ||
286 | #define BP_IR_INTR_TXUF_IRQ 3 | ||
287 | #define BM_IR_INTR_TXUF_IRQ 0x8 | ||
288 | #define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0 | ||
289 | #define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1 | ||
290 | #define BF_IR_INTR_TXUF_IRQ(v) (((v) << 3) & 0x8) | ||
291 | #define BF_IR_INTR_TXUF_IRQ_V(v) ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8) | ||
292 | #define BP_IR_INTR_TC_IRQ 2 | ||
293 | #define BM_IR_INTR_TC_IRQ 0x4 | ||
294 | #define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0 | ||
295 | #define BV_IR_INTR_TC_IRQ__REQUEST 0x1 | ||
296 | #define BF_IR_INTR_TC_IRQ(v) (((v) << 2) & 0x4) | ||
297 | #define BF_IR_INTR_TC_IRQ_V(v) ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4) | ||
298 | #define BP_IR_INTR_RX_IRQ 1 | ||
299 | #define BM_IR_INTR_RX_IRQ 0x2 | ||
300 | #define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0 | ||
301 | #define BV_IR_INTR_RX_IRQ__REQUEST 0x1 | ||
302 | #define BF_IR_INTR_RX_IRQ(v) (((v) << 1) & 0x2) | ||
303 | #define BF_IR_INTR_RX_IRQ_V(v) ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2) | ||
304 | #define BP_IR_INTR_TX_IRQ 0 | ||
305 | #define BM_IR_INTR_TX_IRQ 0x1 | ||
306 | #define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0 | ||
307 | #define BV_IR_INTR_TX_IRQ__REQUEST 0x1 | ||
308 | #define BF_IR_INTR_TX_IRQ(v) (((v) << 0) & 0x1) | ||
309 | #define BF_IR_INTR_TX_IRQ_V(v) ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1) | ||
310 | |||
311 | /** | ||
312 | * Register: HW_IR_DATA | ||
313 | * Address: 0x50 | ||
314 | * SCT: no | ||
315 | */ | ||
316 | #define HW_IR_DATA (*(volatile unsigned long *)(REGS_IR_BASE + 0x50)) | ||
317 | #define BP_IR_DATA_DATA 0 | ||
318 | #define BM_IR_DATA_DATA 0xffffffff | ||
319 | #define BF_IR_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_IR_STAT | ||
323 | * Address: 0x60 | ||
324 | * SCT: no | ||
325 | */ | ||
326 | #define HW_IR_STAT (*(volatile unsigned long *)(REGS_IR_BASE + 0x60)) | ||
327 | #define BP_IR_STAT_PRESENT 31 | ||
328 | #define BM_IR_STAT_PRESENT 0x80000000 | ||
329 | #define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0 | ||
330 | #define BV_IR_STAT_PRESENT__AVAILABLE 0x1 | ||
331 | #define BF_IR_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
332 | #define BF_IR_STAT_PRESENT_V(v) ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000) | ||
333 | #define BP_IR_STAT_MODE_ALLOWED 29 | ||
334 | #define BM_IR_STAT_MODE_ALLOWED 0x60000000 | ||
335 | #define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0 | ||
336 | #define BV_IR_STAT_MODE_ALLOWED__FIR 0x1 | ||
337 | #define BV_IR_STAT_MODE_ALLOWED__MIR 0x2 | ||
338 | #define BV_IR_STAT_MODE_ALLOWED__SIR 0x3 | ||
339 | #define BF_IR_STAT_MODE_ALLOWED(v) (((v) << 29) & 0x60000000) | ||
340 | #define BF_IR_STAT_MODE_ALLOWED_V(v) ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000) | ||
341 | #define BP_IR_STAT_ANY_IRQ 28 | ||
342 | #define BM_IR_STAT_ANY_IRQ 0x10000000 | ||
343 | #define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0 | ||
344 | #define BV_IR_STAT_ANY_IRQ__REQUEST 0x1 | ||
345 | #define BF_IR_STAT_ANY_IRQ(v) (((v) << 28) & 0x10000000) | ||
346 | #define BF_IR_STAT_ANY_IRQ_V(v) ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000) | ||
347 | #define BP_IR_STAT_RXABORT_SUMMARY 22 | ||
348 | #define BM_IR_STAT_RXABORT_SUMMARY 0x400000 | ||
349 | #define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0 | ||
350 | #define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1 | ||
351 | #define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) << 22) & 0x400000) | ||
352 | #define BF_IR_STAT_RXABORT_SUMMARY_V(v) ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000) | ||
353 | #define BP_IR_STAT_SPEED_SUMMARY 21 | ||
354 | #define BM_IR_STAT_SPEED_SUMMARY 0x200000 | ||
355 | #define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0 | ||
356 | #define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1 | ||
357 | #define BF_IR_STAT_SPEED_SUMMARY(v) (((v) << 21) & 0x200000) | ||
358 | #define BF_IR_STAT_SPEED_SUMMARY_V(v) ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000) | ||
359 | #define BP_IR_STAT_RXOF_SUMMARY 20 | ||
360 | #define BM_IR_STAT_RXOF_SUMMARY 0x100000 | ||
361 | #define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0 | ||
362 | #define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1 | ||
363 | #define BF_IR_STAT_RXOF_SUMMARY(v) (((v) << 20) & 0x100000) | ||
364 | #define BF_IR_STAT_RXOF_SUMMARY_V(v) ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000) | ||
365 | #define BP_IR_STAT_TXUF_SUMMARY 19 | ||
366 | #define BM_IR_STAT_TXUF_SUMMARY 0x80000 | ||
367 | #define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0 | ||
368 | #define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1 | ||
369 | #define BF_IR_STAT_TXUF_SUMMARY(v) (((v) << 19) & 0x80000) | ||
370 | #define BF_IR_STAT_TXUF_SUMMARY_V(v) ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000) | ||
371 | #define BP_IR_STAT_TC_SUMMARY 18 | ||
372 | #define BM_IR_STAT_TC_SUMMARY 0x40000 | ||
373 | #define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0 | ||
374 | #define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1 | ||
375 | #define BF_IR_STAT_TC_SUMMARY(v) (((v) << 18) & 0x40000) | ||
376 | #define BF_IR_STAT_TC_SUMMARY_V(v) ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000) | ||
377 | #define BP_IR_STAT_RX_SUMMARY 17 | ||
378 | #define BM_IR_STAT_RX_SUMMARY 0x20000 | ||
379 | #define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0 | ||
380 | #define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1 | ||
381 | #define BF_IR_STAT_RX_SUMMARY(v) (((v) << 17) & 0x20000) | ||
382 | #define BF_IR_STAT_RX_SUMMARY_V(v) ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000) | ||
383 | #define BP_IR_STAT_TX_SUMMARY 16 | ||
384 | #define BM_IR_STAT_TX_SUMMARY 0x10000 | ||
385 | #define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0 | ||
386 | #define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1 | ||
387 | #define BF_IR_STAT_TX_SUMMARY(v) (((v) << 16) & 0x10000) | ||
388 | #define BF_IR_STAT_TX_SUMMARY_V(v) ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000) | ||
389 | #define BP_IR_STAT_MEDIA_BUSY 2 | ||
390 | #define BM_IR_STAT_MEDIA_BUSY 0x4 | ||
391 | #define BF_IR_STAT_MEDIA_BUSY(v) (((v) << 2) & 0x4) | ||
392 | #define BP_IR_STAT_RX_ACTIVE 1 | ||
393 | #define BM_IR_STAT_RX_ACTIVE 0x2 | ||
394 | #define BF_IR_STAT_RX_ACTIVE(v) (((v) << 1) & 0x2) | ||
395 | #define BP_IR_STAT_TX_ACTIVE 0 | ||
396 | #define BM_IR_STAT_TX_ACTIVE 0x1 | ||
397 | #define BF_IR_STAT_TX_ACTIVE(v) (((v) << 0) & 0x1) | ||
398 | |||
399 | /** | ||
400 | * Register: HW_IR_TCCTRL | ||
401 | * Address: 0x70 | ||
402 | * SCT: yes | ||
403 | */ | ||
404 | #define HW_IR_TCCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0)) | ||
405 | #define HW_IR_TCCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4)) | ||
406 | #define HW_IR_TCCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8)) | ||
407 | #define HW_IR_TCCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc)) | ||
408 | #define BP_IR_TCCTRL_INIT 31 | ||
409 | #define BM_IR_TCCTRL_INIT 0x80000000 | ||
410 | #define BF_IR_TCCTRL_INIT(v) (((v) << 31) & 0x80000000) | ||
411 | #define BP_IR_TCCTRL_GO 30 | ||
412 | #define BM_IR_TCCTRL_GO 0x40000000 | ||
413 | #define BF_IR_TCCTRL_GO(v) (((v) << 30) & 0x40000000) | ||
414 | #define BP_IR_TCCTRL_BUSY 29 | ||
415 | #define BM_IR_TCCTRL_BUSY 0x20000000 | ||
416 | #define BF_IR_TCCTRL_BUSY(v) (((v) << 29) & 0x20000000) | ||
417 | #define BP_IR_TCCTRL_TEMIC 24 | ||
418 | #define BM_IR_TCCTRL_TEMIC 0x1000000 | ||
419 | #define BV_IR_TCCTRL_TEMIC__LOW 0x0 | ||
420 | #define BV_IR_TCCTRL_TEMIC__HIGH 0x1 | ||
421 | #define BF_IR_TCCTRL_TEMIC(v) (((v) << 24) & 0x1000000) | ||
422 | #define BF_IR_TCCTRL_TEMIC_V(v) ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000) | ||
423 | #define BP_IR_TCCTRL_EXT_DATA 16 | ||
424 | #define BM_IR_TCCTRL_EXT_DATA 0xff0000 | ||
425 | #define BF_IR_TCCTRL_EXT_DATA(v) (((v) << 16) & 0xff0000) | ||
426 | #define BP_IR_TCCTRL_DATA 8 | ||
427 | #define BM_IR_TCCTRL_DATA 0xff00 | ||
428 | #define BF_IR_TCCTRL_DATA(v) (((v) << 8) & 0xff00) | ||
429 | #define BP_IR_TCCTRL_ADDR 5 | ||
430 | #define BM_IR_TCCTRL_ADDR 0xe0 | ||
431 | #define BF_IR_TCCTRL_ADDR(v) (((v) << 5) & 0xe0) | ||
432 | #define BP_IR_TCCTRL_INDX 1 | ||
433 | #define BM_IR_TCCTRL_INDX 0x1e | ||
434 | #define BF_IR_TCCTRL_INDX(v) (((v) << 1) & 0x1e) | ||
435 | #define BP_IR_TCCTRL_C 0 | ||
436 | #define BM_IR_TCCTRL_C 0x1 | ||
437 | #define BF_IR_TCCTRL_C(v) (((v) << 0) & 0x1) | ||
438 | |||
439 | /** | ||
440 | * Register: HW_IR_SI_READ | ||
441 | * Address: 0x80 | ||
442 | * SCT: no | ||
443 | */ | ||
444 | #define HW_IR_SI_READ (*(volatile unsigned long *)(REGS_IR_BASE + 0x80)) | ||
445 | #define BP_IR_SI_READ_ABORT 8 | ||
446 | #define BM_IR_SI_READ_ABORT 0x100 | ||
447 | #define BF_IR_SI_READ_ABORT(v) (((v) << 8) & 0x100) | ||
448 | #define BP_IR_SI_READ_DATA 0 | ||
449 | #define BM_IR_SI_READ_DATA 0xff | ||
450 | #define BF_IR_SI_READ_DATA(v) (((v) << 0) & 0xff) | ||
451 | |||
452 | /** | ||
453 | * Register: HW_IR_DEBUG | ||
454 | * Address: 0x90 | ||
455 | * SCT: no | ||
456 | */ | ||
457 | #define HW_IR_DEBUG (*(volatile unsigned long *)(REGS_IR_BASE + 0x90)) | ||
458 | #define BP_IR_DEBUG_TXDMAKICK 5 | ||
459 | #define BM_IR_DEBUG_TXDMAKICK 0x20 | ||
460 | #define BF_IR_DEBUG_TXDMAKICK(v) (((v) << 5) & 0x20) | ||
461 | #define BP_IR_DEBUG_RXDMAKICK 4 | ||
462 | #define BM_IR_DEBUG_RXDMAKICK 0x10 | ||
463 | #define BF_IR_DEBUG_RXDMAKICK(v) (((v) << 4) & 0x10) | ||
464 | #define BP_IR_DEBUG_TXDMAEND 3 | ||
465 | #define BM_IR_DEBUG_TXDMAEND 0x8 | ||
466 | #define BF_IR_DEBUG_TXDMAEND(v) (((v) << 3) & 0x8) | ||
467 | #define BP_IR_DEBUG_RXDMAEND 2 | ||
468 | #define BM_IR_DEBUG_RXDMAEND 0x4 | ||
469 | #define BF_IR_DEBUG_RXDMAEND(v) (((v) << 2) & 0x4) | ||
470 | #define BP_IR_DEBUG_TXDMAREQ 1 | ||
471 | #define BM_IR_DEBUG_TXDMAREQ 0x2 | ||
472 | #define BF_IR_DEBUG_TXDMAREQ(v) (((v) << 1) & 0x2) | ||
473 | #define BP_IR_DEBUG_RXDMAREQ 0 | ||
474 | #define BM_IR_DEBUG_RXDMAREQ 0x1 | ||
475 | #define BF_IR_DEBUG_RXDMAREQ(v) (((v) << 0) & 0x1) | ||
476 | |||
477 | /** | ||
478 | * Register: HW_IR_VERSION | ||
479 | * Address: 0xa0 | ||
480 | * SCT: no | ||
481 | */ | ||
482 | #define HW_IR_VERSION (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0)) | ||
483 | #define BP_IR_VERSION_MAJOR 24 | ||
484 | #define BM_IR_VERSION_MAJOR 0xff000000 | ||
485 | #define BF_IR_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
486 | #define BP_IR_VERSION_MINOR 16 | ||
487 | #define BM_IR_VERSION_MINOR 0xff0000 | ||
488 | #define BF_IR_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
489 | #define BP_IR_VERSION_STEP 0 | ||
490 | #define BM_IR_VERSION_STEP 0xffff | ||
491 | #define BF_IR_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
492 | |||
493 | #endif /* __HEADERGEN__STMP3700__IR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h new file mode 100644 index 0000000000..c528c81fee --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h | |||
@@ -0,0 +1,451 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__LCDIF__H__ | ||
24 | #define __HEADERGEN__STMP3700__LCDIF__H__ | ||
25 | |||
26 | #define REGS_LCDIF_BASE (0x80030000) | ||
27 | |||
28 | #define REGS_LCDIF_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_LCDIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_LCDIF_CTRL (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0)) | ||
36 | #define HW_LCDIF_CTRL_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4)) | ||
37 | #define HW_LCDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8)) | ||
38 | #define HW_LCDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc)) | ||
39 | #define BP_LCDIF_CTRL_SFTRST 31 | ||
40 | #define BM_LCDIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_LCDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_LCDIF_CTRL_CLKGATE 30 | ||
43 | #define BM_LCDIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_LCDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_LCDIF_CTRL_READ_WRITEB 29 | ||
46 | #define BM_LCDIF_CTRL_READ_WRITEB 0x20000000 | ||
47 | #define BF_LCDIF_CTRL_READ_WRITEB(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 28 | ||
49 | #define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000 | ||
50 | #define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_LCDIF_CTRL_DATA_SHIFT_DIR 27 | ||
52 | #define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x8000000 | ||
53 | #define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 | ||
54 | #define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 | ||
55 | #define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v) (((v) << 27) & 0x8000000) | ||
56 | #define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v) ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 27) & 0x8000000) | ||
57 | #define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25 | ||
58 | #define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x6000000 | ||
59 | #define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) (((v) << 25) & 0x6000000) | ||
60 | #define BP_LCDIF_CTRL_DVI_MODE 24 | ||
61 | #define BM_LCDIF_CTRL_DVI_MODE 0x1000000 | ||
62 | #define BF_LCDIF_CTRL_DVI_MODE(v) (((v) << 24) & 0x1000000) | ||
63 | #define BP_LCDIF_CTRL_BYPASS_COUNT 23 | ||
64 | #define BM_LCDIF_CTRL_BYPASS_COUNT 0x800000 | ||
65 | #define BF_LCDIF_CTRL_BYPASS_COUNT(v) (((v) << 23) & 0x800000) | ||
66 | #define BP_LCDIF_CTRL_DATA_SWIZZLE 21 | ||
67 | #define BM_LCDIF_CTRL_DATA_SWIZZLE 0x600000 | ||
68 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP 0x0 | ||
69 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 | ||
70 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 | ||
71 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 | ||
72 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP 0x2 | ||
73 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 | ||
74 | #define BF_LCDIF_CTRL_DATA_SWIZZLE(v) (((v) << 21) & 0x600000) | ||
75 | #define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v) ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000) | ||
76 | #define BP_LCDIF_CTRL_VSYNC_MODE 20 | ||
77 | #define BM_LCDIF_CTRL_VSYNC_MODE 0x100000 | ||
78 | #define BF_LCDIF_CTRL_VSYNC_MODE(v) (((v) << 20) & 0x100000) | ||
79 | #define BP_LCDIF_CTRL_DOTCLK_MODE 19 | ||
80 | #define BM_LCDIF_CTRL_DOTCLK_MODE 0x80000 | ||
81 | #define BF_LCDIF_CTRL_DOTCLK_MODE(v) (((v) << 19) & 0x80000) | ||
82 | #define BP_LCDIF_CTRL_DATA_SELECT 18 | ||
83 | #define BM_LCDIF_CTRL_DATA_SELECT 0x40000 | ||
84 | #define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 | ||
85 | #define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 | ||
86 | #define BF_LCDIF_CTRL_DATA_SELECT(v) (((v) << 18) & 0x40000) | ||
87 | #define BF_LCDIF_CTRL_DATA_SELECT_V(v) ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000) | ||
88 | #define BP_LCDIF_CTRL_WORD_LENGTH 17 | ||
89 | #define BM_LCDIF_CTRL_WORD_LENGTH 0x20000 | ||
90 | #define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 | ||
91 | #define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 | ||
92 | #define BF_LCDIF_CTRL_WORD_LENGTH(v) (((v) << 17) & 0x20000) | ||
93 | #define BF_LCDIF_CTRL_WORD_LENGTH_V(v) ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000) | ||
94 | #define BP_LCDIF_CTRL_RUN 16 | ||
95 | #define BM_LCDIF_CTRL_RUN 0x10000 | ||
96 | #define BF_LCDIF_CTRL_RUN(v) (((v) << 16) & 0x10000) | ||
97 | #define BP_LCDIF_CTRL_COUNT 0 | ||
98 | #define BM_LCDIF_CTRL_COUNT 0xffff | ||
99 | #define BF_LCDIF_CTRL_COUNT(v) (((v) << 0) & 0xffff) | ||
100 | |||
101 | /** | ||
102 | * Register: HW_LCDIF_CTRL1 | ||
103 | * Address: 0x10 | ||
104 | * SCT: yes | ||
105 | */ | ||
106 | #define HW_LCDIF_CTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0)) | ||
107 | #define HW_LCDIF_CTRL1_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4)) | ||
108 | #define HW_LCDIF_CTRL1_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8)) | ||
109 | #define HW_LCDIF_CTRL1_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc)) | ||
110 | #define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 | ||
111 | #define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0xf0000 | ||
112 | #define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) (((v) << 16) & 0xf0000) | ||
113 | #define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN 15 | ||
114 | #define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x8000 | ||
115 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
116 | #define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 14 | ||
117 | #define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x4000 | ||
118 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
119 | #define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 13 | ||
120 | #define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x2000 | ||
121 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
122 | #define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 12 | ||
123 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x1000 | ||
124 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
125 | #define BP_LCDIF_CTRL1_OVERFLOW_IRQ 11 | ||
126 | #define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x800 | ||
127 | #define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
128 | #define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 | ||
129 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v) (((v) << 11) & 0x800) | ||
130 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v) ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800) | ||
131 | #define BP_LCDIF_CTRL1_UNDERFLOW_IRQ 10 | ||
132 | #define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x400 | ||
133 | #define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 | ||
134 | #define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 | ||
135 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v) (((v) << 10) & 0x400) | ||
136 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v) ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400) | ||
137 | #define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 9 | ||
138 | #define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x200 | ||
139 | #define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 | ||
140 | #define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 | ||
141 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v) (((v) << 9) & 0x200) | ||
142 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v) ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200) | ||
143 | #define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ 8 | ||
144 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x100 | ||
145 | #define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 | ||
146 | #define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 | ||
147 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v) (((v) << 8) & 0x100) | ||
148 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v) ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100) | ||
149 | #define BP_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS 5 | ||
150 | #define BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS 0xe0 | ||
151 | #define BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(v) (((v) << 5) & 0xe0) | ||
152 | #define BP_LCDIF_CTRL1_FIRST_READ_DUMMY 4 | ||
153 | #define BM_LCDIF_CTRL1_FIRST_READ_DUMMY 0x10 | ||
154 | #define BF_LCDIF_CTRL1_FIRST_READ_DUMMY(v) (((v) << 4) & 0x10) | ||
155 | #define BP_LCDIF_CTRL1_LCD_CS_CTRL 3 | ||
156 | #define BM_LCDIF_CTRL1_LCD_CS_CTRL 0x8 | ||
157 | #define BF_LCDIF_CTRL1_LCD_CS_CTRL(v) (((v) << 3) & 0x8) | ||
158 | #define BP_LCDIF_CTRL1_BUSY_ENABLE 2 | ||
159 | #define BM_LCDIF_CTRL1_BUSY_ENABLE 0x4 | ||
160 | #define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 | ||
161 | #define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 | ||
162 | #define BF_LCDIF_CTRL1_BUSY_ENABLE(v) (((v) << 2) & 0x4) | ||
163 | #define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v) ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4) | ||
164 | #define BP_LCDIF_CTRL1_MODE86 1 | ||
165 | #define BM_LCDIF_CTRL1_MODE86 0x2 | ||
166 | #define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 | ||
167 | #define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 | ||
168 | #define BF_LCDIF_CTRL1_MODE86(v) (((v) << 1) & 0x2) | ||
169 | #define BF_LCDIF_CTRL1_MODE86_V(v) ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2) | ||
170 | #define BP_LCDIF_CTRL1_RESET 0 | ||
171 | #define BM_LCDIF_CTRL1_RESET 0x1 | ||
172 | #define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 | ||
173 | #define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 | ||
174 | #define BF_LCDIF_CTRL1_RESET(v) (((v) << 0) & 0x1) | ||
175 | #define BF_LCDIF_CTRL1_RESET_V(v) ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1) | ||
176 | |||
177 | /** | ||
178 | * Register: HW_LCDIF_TIMING | ||
179 | * Address: 0x20 | ||
180 | * SCT: no | ||
181 | */ | ||
182 | #define HW_LCDIF_TIMING (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20)) | ||
183 | #define BP_LCDIF_TIMING_CMD_HOLD 24 | ||
184 | #define BM_LCDIF_TIMING_CMD_HOLD 0xff000000 | ||
185 | #define BF_LCDIF_TIMING_CMD_HOLD(v) (((v) << 24) & 0xff000000) | ||
186 | #define BP_LCDIF_TIMING_CMD_SETUP 16 | ||
187 | #define BM_LCDIF_TIMING_CMD_SETUP 0xff0000 | ||
188 | #define BF_LCDIF_TIMING_CMD_SETUP(v) (((v) << 16) & 0xff0000) | ||
189 | #define BP_LCDIF_TIMING_DATA_HOLD 8 | ||
190 | #define BM_LCDIF_TIMING_DATA_HOLD 0xff00 | ||
191 | #define BF_LCDIF_TIMING_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
192 | #define BP_LCDIF_TIMING_DATA_SETUP 0 | ||
193 | #define BM_LCDIF_TIMING_DATA_SETUP 0xff | ||
194 | #define BF_LCDIF_TIMING_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
195 | |||
196 | /** | ||
197 | * Register: HW_LCDIF_VDCTRL0 | ||
198 | * Address: 0x30 | ||
199 | * SCT: yes | ||
200 | */ | ||
201 | #define HW_LCDIF_VDCTRL0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x0)) | ||
202 | #define HW_LCDIF_VDCTRL0_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x4)) | ||
203 | #define HW_LCDIF_VDCTRL0_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x8)) | ||
204 | #define HW_LCDIF_VDCTRL0_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0xc)) | ||
205 | #define BP_LCDIF_VDCTRL0_VSYNC_OEB 29 | ||
206 | #define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 | ||
207 | #define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 | ||
208 | #define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 | ||
209 | #define BF_LCDIF_VDCTRL0_VSYNC_OEB(v) (((v) << 29) & 0x20000000) | ||
210 | #define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v) ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000) | ||
211 | #define BP_LCDIF_VDCTRL0_ENABLE_PRESENT 28 | ||
212 | #define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 | ||
213 | #define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
214 | #define BP_LCDIF_VDCTRL0_VSYNC_POL 27 | ||
215 | #define BM_LCDIF_VDCTRL0_VSYNC_POL 0x8000000 | ||
216 | #define BF_LCDIF_VDCTRL0_VSYNC_POL(v) (((v) << 27) & 0x8000000) | ||
217 | #define BP_LCDIF_VDCTRL0_HSYNC_POL 26 | ||
218 | #define BM_LCDIF_VDCTRL0_HSYNC_POL 0x4000000 | ||
219 | #define BF_LCDIF_VDCTRL0_HSYNC_POL(v) (((v) << 26) & 0x4000000) | ||
220 | #define BP_LCDIF_VDCTRL0_DOTCLK_POL 25 | ||
221 | #define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x2000000 | ||
222 | #define BF_LCDIF_VDCTRL0_DOTCLK_POL(v) (((v) << 25) & 0x2000000) | ||
223 | #define BP_LCDIF_VDCTRL0_ENABLE_POL 24 | ||
224 | #define BM_LCDIF_VDCTRL0_ENABLE_POL 0x1000000 | ||
225 | #define BF_LCDIF_VDCTRL0_ENABLE_POL(v) (((v) << 24) & 0x1000000) | ||
226 | #define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 21 | ||
227 | #define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x200000 | ||
228 | #define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v) (((v) << 21) & 0x200000) | ||
229 | #define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 20 | ||
230 | #define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x100000 | ||
231 | #define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v) (((v) << 20) & 0x100000) | ||
232 | #define BP_LCDIF_VDCTRL0_INTERLACE 19 | ||
233 | #define BM_LCDIF_VDCTRL0_INTERLACE 0x80000 | ||
234 | #define BF_LCDIF_VDCTRL0_INTERLACE(v) (((v) << 19) & 0x80000) | ||
235 | #define BP_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT 0 | ||
236 | #define BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT 0x3ff | ||
237 | #define BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(v) (((v) << 0) & 0x3ff) | ||
238 | |||
239 | /** | ||
240 | * Register: HW_LCDIF_VDCTRL1 | ||
241 | * Address: 0x40 | ||
242 | * SCT: no | ||
243 | */ | ||
244 | #define HW_LCDIF_VDCTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40)) | ||
245 | #define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20 | ||
246 | #define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xfff00000 | ||
247 | #define BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(v) (((v) << 20) & 0xfff00000) | ||
248 | #define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 | ||
249 | #define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xfffff | ||
250 | #define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (((v) << 0) & 0xfffff) | ||
251 | |||
252 | /** | ||
253 | * Register: HW_LCDIF_VDCTRL2 | ||
254 | * Address: 0x50 | ||
255 | * SCT: no | ||
256 | */ | ||
257 | #define HW_LCDIF_VDCTRL2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50)) | ||
258 | #define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23 | ||
259 | #define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xff800000 | ||
260 | #define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) (((v) << 23) & 0xff800000) | ||
261 | #define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11 | ||
262 | #define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x7ff800 | ||
263 | #define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) (((v) << 11) & 0x7ff800) | ||
264 | #define BP_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT 0 | ||
265 | #define BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT 0x7ff | ||
266 | #define BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x7ff) | ||
267 | |||
268 | /** | ||
269 | * Register: HW_LCDIF_VDCTRL3 | ||
270 | * Address: 0x60 | ||
271 | * SCT: no | ||
272 | */ | ||
273 | #define HW_LCDIF_VDCTRL3 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60)) | ||
274 | #define BP_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 24 | ||
275 | #define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x1000000 | ||
276 | #define BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(v) (((v) << 24) & 0x1000000) | ||
277 | #define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12 | ||
278 | #define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0xfff000 | ||
279 | #define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 12) & 0xfff000) | ||
280 | #define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 | ||
281 | #define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x1ff | ||
282 | #define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) (((v) << 0) & 0x1ff) | ||
283 | |||
284 | /** | ||
285 | * Register: HW_LCDIF_DVICTRL0 | ||
286 | * Address: 0x70 | ||
287 | * SCT: no | ||
288 | */ | ||
289 | #define HW_LCDIF_DVICTRL0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70)) | ||
290 | #define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 | ||
291 | #define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7ff00000 | ||
292 | #define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) (((v) << 20) & 0x7ff00000) | ||
293 | #define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 | ||
294 | #define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0xffc00 | ||
295 | #define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00) | ||
296 | #define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 | ||
297 | #define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x3ff | ||
298 | #define BF_LCDIF_DVICTRL0_V_LINES_CNT(v) (((v) << 0) & 0x3ff) | ||
299 | |||
300 | /** | ||
301 | * Register: HW_LCDIF_DVICTRL1 | ||
302 | * Address: 0x80 | ||
303 | * SCT: no | ||
304 | */ | ||
305 | #define HW_LCDIF_DVICTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80)) | ||
306 | #define BP_LCDIF_DVICTRL1_F1_START_LINE 20 | ||
307 | #define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3ff00000 | ||
308 | #define BF_LCDIF_DVICTRL1_F1_START_LINE(v) (((v) << 20) & 0x3ff00000) | ||
309 | #define BP_LCDIF_DVICTRL1_F1_END_LINE 10 | ||
310 | #define BM_LCDIF_DVICTRL1_F1_END_LINE 0xffc00 | ||
311 | #define BF_LCDIF_DVICTRL1_F1_END_LINE(v) (((v) << 10) & 0xffc00) | ||
312 | #define BP_LCDIF_DVICTRL1_F2_START_LINE 0 | ||
313 | #define BM_LCDIF_DVICTRL1_F2_START_LINE 0x3ff | ||
314 | #define BF_LCDIF_DVICTRL1_F2_START_LINE(v) (((v) << 0) & 0x3ff) | ||
315 | |||
316 | /** | ||
317 | * Register: HW_LCDIF_DVICTRL2 | ||
318 | * Address: 0x90 | ||
319 | * SCT: no | ||
320 | */ | ||
321 | #define HW_LCDIF_DVICTRL2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90)) | ||
322 | #define BP_LCDIF_DVICTRL2_F2_END_LINE 20 | ||
323 | #define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3ff00000 | ||
324 | #define BF_LCDIF_DVICTRL2_F2_END_LINE(v) (((v) << 20) & 0x3ff00000) | ||
325 | #define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 | ||
326 | #define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0xffc00 | ||
327 | #define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) (((v) << 10) & 0xffc00) | ||
328 | #define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 | ||
329 | #define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x3ff | ||
330 | #define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) (((v) << 0) & 0x3ff) | ||
331 | |||
332 | /** | ||
333 | * Register: HW_LCDIF_DVICTRL3 | ||
334 | * Address: 0xa0 | ||
335 | * SCT: no | ||
336 | */ | ||
337 | #define HW_LCDIF_DVICTRL3 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0)) | ||
338 | #define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 | ||
339 | #define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3ff0000 | ||
340 | #define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) (((v) << 16) & 0x3ff0000) | ||
341 | #define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 | ||
342 | #define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x3ff | ||
343 | #define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) (((v) << 0) & 0x3ff) | ||
344 | |||
345 | /** | ||
346 | * Register: HW_LCDIF_DATA | ||
347 | * Address: 0xb0 | ||
348 | * SCT: no | ||
349 | */ | ||
350 | #define HW_LCDIF_DATA (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0)) | ||
351 | #define BP_LCDIF_DATA_DATA_THREE 24 | ||
352 | #define BM_LCDIF_DATA_DATA_THREE 0xff000000 | ||
353 | #define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000) | ||
354 | #define BP_LCDIF_DATA_DATA_TWO 16 | ||
355 | #define BM_LCDIF_DATA_DATA_TWO 0xff0000 | ||
356 | #define BF_LCDIF_DATA_DATA_TWO(v) (((v) << 16) & 0xff0000) | ||
357 | #define BP_LCDIF_DATA_DATA_ONE 8 | ||
358 | #define BM_LCDIF_DATA_DATA_ONE 0xff00 | ||
359 | #define BF_LCDIF_DATA_DATA_ONE(v) (((v) << 8) & 0xff00) | ||
360 | #define BP_LCDIF_DATA_DATA_ZERO 0 | ||
361 | #define BM_LCDIF_DATA_DATA_ZERO 0xff | ||
362 | #define BF_LCDIF_DATA_DATA_ZERO(v) (((v) << 0) & 0xff) | ||
363 | |||
364 | /** | ||
365 | * Register: HW_LCDIF_STAT | ||
366 | * Address: 0xc0 | ||
367 | * SCT: no | ||
368 | */ | ||
369 | #define HW_LCDIF_STAT (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0)) | ||
370 | #define BP_LCDIF_STAT_PRESENT 31 | ||
371 | #define BM_LCDIF_STAT_PRESENT 0x80000000 | ||
372 | #define BF_LCDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
373 | #define BP_LCDIF_STAT_DMA_REQ 30 | ||
374 | #define BM_LCDIF_STAT_DMA_REQ 0x40000000 | ||
375 | #define BF_LCDIF_STAT_DMA_REQ(v) (((v) << 30) & 0x40000000) | ||
376 | #define BP_LCDIF_STAT_RXFIFO_FULL 29 | ||
377 | #define BM_LCDIF_STAT_RXFIFO_FULL 0x20000000 | ||
378 | #define BF_LCDIF_STAT_RXFIFO_FULL(v) (((v) << 29) & 0x20000000) | ||
379 | #define BP_LCDIF_STAT_RXFIFO_EMPTY 28 | ||
380 | #define BM_LCDIF_STAT_RXFIFO_EMPTY 0x10000000 | ||
381 | #define BF_LCDIF_STAT_RXFIFO_EMPTY(v) (((v) << 28) & 0x10000000) | ||
382 | #define BP_LCDIF_STAT_TXFIFO_FULL 27 | ||
383 | #define BM_LCDIF_STAT_TXFIFO_FULL 0x8000000 | ||
384 | #define BF_LCDIF_STAT_TXFIFO_FULL(v) (((v) << 27) & 0x8000000) | ||
385 | #define BP_LCDIF_STAT_TXFIFO_EMPTY 26 | ||
386 | #define BM_LCDIF_STAT_TXFIFO_EMPTY 0x4000000 | ||
387 | #define BF_LCDIF_STAT_TXFIFO_EMPTY(v) (((v) << 26) & 0x4000000) | ||
388 | #define BP_LCDIF_STAT_BUSY 25 | ||
389 | #define BM_LCDIF_STAT_BUSY 0x2000000 | ||
390 | #define BF_LCDIF_STAT_BUSY(v) (((v) << 25) & 0x2000000) | ||
391 | #define BP_LCDIF_STAT_DVI_CURRENT_FIELD 24 | ||
392 | #define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x1000000 | ||
393 | #define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v) (((v) << 24) & 0x1000000) | ||
394 | |||
395 | /** | ||
396 | * Register: HW_LCDIF_VERSION | ||
397 | * Address: 0xd0 | ||
398 | * SCT: no | ||
399 | */ | ||
400 | #define HW_LCDIF_VERSION (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0)) | ||
401 | #define BP_LCDIF_VERSION_MAJOR 24 | ||
402 | #define BM_LCDIF_VERSION_MAJOR 0xff000000 | ||
403 | #define BF_LCDIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
404 | #define BP_LCDIF_VERSION_MINOR 16 | ||
405 | #define BM_LCDIF_VERSION_MINOR 0xff0000 | ||
406 | #define BF_LCDIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
407 | #define BP_LCDIF_VERSION_STEP 0 | ||
408 | #define BM_LCDIF_VERSION_STEP 0xffff | ||
409 | #define BF_LCDIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
410 | |||
411 | /** | ||
412 | * Register: HW_LCDIF_DEBUG0 | ||
413 | * Address: 0xe0 | ||
414 | * SCT: no | ||
415 | */ | ||
416 | #define HW_LCDIF_DEBUG0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0)) | ||
417 | #define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED 31 | ||
418 | #define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 | ||
419 | #define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v) (((v) << 31) & 0x80000000) | ||
420 | #define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 30 | ||
421 | #define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 | ||
422 | #define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v) (((v) << 30) & 0x40000000) | ||
423 | #define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 29 | ||
424 | #define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 | ||
425 | #define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v) (((v) << 29) & 0x20000000) | ||
426 | #define BP_LCDIF_DEBUG0_DMACMDKICK 28 | ||
427 | #define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 | ||
428 | #define BF_LCDIF_DEBUG0_DMACMDKICK(v) (((v) << 28) & 0x10000000) | ||
429 | #define BP_LCDIF_DEBUG0_ENABLE 27 | ||
430 | #define BM_LCDIF_DEBUG0_ENABLE 0x8000000 | ||
431 | #define BF_LCDIF_DEBUG0_ENABLE(v) (((v) << 27) & 0x8000000) | ||
432 | #define BP_LCDIF_DEBUG0_HSYNC 26 | ||
433 | #define BM_LCDIF_DEBUG0_HSYNC 0x4000000 | ||
434 | #define BF_LCDIF_DEBUG0_HSYNC(v) (((v) << 26) & 0x4000000) | ||
435 | #define BP_LCDIF_DEBUG0_VSYNC 25 | ||
436 | #define BM_LCDIF_DEBUG0_VSYNC 0x2000000 | ||
437 | #define BF_LCDIF_DEBUG0_VSYNC(v) (((v) << 25) & 0x2000000) | ||
438 | #define BP_LCDIF_DEBUG0_CUR_FRAME_TX 24 | ||
439 | #define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x1000000 | ||
440 | #define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v) (((v) << 24) & 0x1000000) | ||
441 | #define BP_LCDIF_DEBUG0_EMPTY_WORD 23 | ||
442 | #define BM_LCDIF_DEBUG0_EMPTY_WORD 0x800000 | ||
443 | #define BF_LCDIF_DEBUG0_EMPTY_WORD(v) (((v) << 23) & 0x800000) | ||
444 | #define BP_LCDIF_DEBUG0_CUR_STATE 16 | ||
445 | #define BM_LCDIF_DEBUG0_CUR_STATE 0x7f0000 | ||
446 | #define BF_LCDIF_DEBUG0_CUR_STATE(v) (((v) << 16) & 0x7f0000) | ||
447 | #define BP_LCDIF_DEBUG0_DATA_COUNT 0 | ||
448 | #define BM_LCDIF_DEBUG0_DATA_COUNT 0xffff | ||
449 | #define BF_LCDIF_DEBUG0_DATA_COUNT(v) (((v) << 0) & 0xffff) | ||
450 | |||
451 | #endif /* __HEADERGEN__STMP3700__LCDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h new file mode 100644 index 0000000000..ad0beecbae --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h | |||
@@ -0,0 +1,708 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__LRADC__H__ | ||
24 | #define __HEADERGEN__STMP3700__LRADC__H__ | ||
25 | |||
26 | #define REGS_LRADC_BASE (0x80050000) | ||
27 | |||
28 | #define REGS_LRADC_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_LRADC_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_LRADC_CTRL0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_LRADC_CTRL0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_LRADC_CTRL0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_LRADC_CTRL0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_LRADC_CTRL0_SFTRST 31 | ||
40 | #define BM_LRADC_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_LRADC_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_LRADC_CTRL0_CLKGATE 30 | ||
43 | #define BM_LRADC_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_LRADC_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21 | ||
46 | #define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000 | ||
47 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 | ||
48 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 | ||
49 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) << 21) & 0x200000) | ||
50 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000) | ||
51 | #define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20 | ||
52 | #define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000 | ||
53 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 | ||
54 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 | ||
55 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) << 20) & 0x100000) | ||
56 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000) | ||
57 | #define BP_LRADC_CTRL0_YMINUS_ENABLE 19 | ||
58 | #define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000 | ||
59 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 | ||
60 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 | ||
61 | #define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) << 19) & 0x80000) | ||
62 | #define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000) | ||
63 | #define BP_LRADC_CTRL0_XMINUS_ENABLE 18 | ||
64 | #define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000 | ||
65 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 | ||
66 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 | ||
67 | #define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) << 18) & 0x40000) | ||
68 | #define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000) | ||
69 | #define BP_LRADC_CTRL0_YPLUS_ENABLE 17 | ||
70 | #define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000 | ||
71 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 | ||
72 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 | ||
73 | #define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) << 17) & 0x20000) | ||
74 | #define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000) | ||
75 | #define BP_LRADC_CTRL0_XPLUS_ENABLE 16 | ||
76 | #define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000 | ||
77 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 | ||
78 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 | ||
79 | #define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) << 16) & 0x10000) | ||
80 | #define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000) | ||
81 | #define BP_LRADC_CTRL0_SCHEDULE 0 | ||
82 | #define BM_LRADC_CTRL0_SCHEDULE 0xff | ||
83 | #define BF_LRADC_CTRL0_SCHEDULE(v) (((v) << 0) & 0xff) | ||
84 | |||
85 | /** | ||
86 | * Register: HW_LRADC_CTRL1 | ||
87 | * Address: 0x10 | ||
88 | * SCT: yes | ||
89 | */ | ||
90 | #define HW_LRADC_CTRL1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0)) | ||
91 | #define HW_LRADC_CTRL1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4)) | ||
92 | #define HW_LRADC_CTRL1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8)) | ||
93 | #define HW_LRADC_CTRL1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc)) | ||
94 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24 | ||
95 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000 | ||
96 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 | ||
97 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 | ||
98 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
99 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000) | ||
100 | #define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23 | ||
101 | #define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000 | ||
102 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 | ||
103 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 | ||
104 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) << 23) & 0x800000) | ||
105 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000) | ||
106 | #define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22 | ||
107 | #define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000 | ||
108 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 | ||
109 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 | ||
110 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
111 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000) | ||
112 | #define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21 | ||
113 | #define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000 | ||
114 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 | ||
115 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 | ||
116 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
117 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000) | ||
118 | #define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20 | ||
119 | #define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000 | ||
120 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 | ||
121 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 | ||
122 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
123 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000) | ||
124 | #define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19 | ||
125 | #define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000 | ||
126 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 | ||
127 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 | ||
128 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
129 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000) | ||
130 | #define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18 | ||
131 | #define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000 | ||
132 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 | ||
133 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 | ||
134 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
135 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000) | ||
136 | #define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17 | ||
137 | #define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000 | ||
138 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 | ||
139 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 | ||
140 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
141 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000) | ||
142 | #define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16 | ||
143 | #define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000 | ||
144 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 | ||
145 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 | ||
146 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
147 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000) | ||
148 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8 | ||
149 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100 | ||
150 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 | ||
151 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 | ||
152 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) << 8) & 0x100) | ||
153 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100) | ||
154 | #define BP_LRADC_CTRL1_LRADC7_IRQ 7 | ||
155 | #define BM_LRADC_CTRL1_LRADC7_IRQ 0x80 | ||
156 | #define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 | ||
157 | #define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 | ||
158 | #define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) << 7) & 0x80) | ||
159 | #define BF_LRADC_CTRL1_LRADC7_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80) | ||
160 | #define BP_LRADC_CTRL1_LRADC6_IRQ 6 | ||
161 | #define BM_LRADC_CTRL1_LRADC6_IRQ 0x40 | ||
162 | #define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 | ||
163 | #define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 | ||
164 | #define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) << 6) & 0x40) | ||
165 | #define BF_LRADC_CTRL1_LRADC6_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40) | ||
166 | #define BP_LRADC_CTRL1_LRADC5_IRQ 5 | ||
167 | #define BM_LRADC_CTRL1_LRADC5_IRQ 0x20 | ||
168 | #define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 | ||
169 | #define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 | ||
170 | #define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) << 5) & 0x20) | ||
171 | #define BF_LRADC_CTRL1_LRADC5_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20) | ||
172 | #define BP_LRADC_CTRL1_LRADC4_IRQ 4 | ||
173 | #define BM_LRADC_CTRL1_LRADC4_IRQ 0x10 | ||
174 | #define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 | ||
175 | #define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 | ||
176 | #define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) << 4) & 0x10) | ||
177 | #define BF_LRADC_CTRL1_LRADC4_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10) | ||
178 | #define BP_LRADC_CTRL1_LRADC3_IRQ 3 | ||
179 | #define BM_LRADC_CTRL1_LRADC3_IRQ 0x8 | ||
180 | #define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 | ||
181 | #define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 | ||
182 | #define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) << 3) & 0x8) | ||
183 | #define BF_LRADC_CTRL1_LRADC3_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8) | ||
184 | #define BP_LRADC_CTRL1_LRADC2_IRQ 2 | ||
185 | #define BM_LRADC_CTRL1_LRADC2_IRQ 0x4 | ||
186 | #define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 | ||
187 | #define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 | ||
188 | #define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) << 2) & 0x4) | ||
189 | #define BF_LRADC_CTRL1_LRADC2_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4) | ||
190 | #define BP_LRADC_CTRL1_LRADC1_IRQ 1 | ||
191 | #define BM_LRADC_CTRL1_LRADC1_IRQ 0x2 | ||
192 | #define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 | ||
193 | #define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 | ||
194 | #define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) << 1) & 0x2) | ||
195 | #define BF_LRADC_CTRL1_LRADC1_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2) | ||
196 | #define BP_LRADC_CTRL1_LRADC0_IRQ 0 | ||
197 | #define BM_LRADC_CTRL1_LRADC0_IRQ 0x1 | ||
198 | #define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 | ||
199 | #define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 | ||
200 | #define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) << 0) & 0x1) | ||
201 | #define BF_LRADC_CTRL1_LRADC0_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_LRADC_CTRL2 | ||
205 | * Address: 0x20 | ||
206 | * SCT: yes | ||
207 | */ | ||
208 | #define HW_LRADC_CTRL2 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0)) | ||
209 | #define HW_LRADC_CTRL2_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4)) | ||
210 | #define HW_LRADC_CTRL2_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8)) | ||
211 | #define HW_LRADC_CTRL2_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc)) | ||
212 | #define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 | ||
213 | #define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000 | ||
214 | #define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) << 24) & 0xff000000) | ||
215 | #define BP_LRADC_CTRL2_BL_AMP_BYPASS 23 | ||
216 | #define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x800000 | ||
217 | #define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0 | ||
218 | #define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1 | ||
219 | #define BF_LRADC_CTRL2_BL_AMP_BYPASS(v) (((v) << 23) & 0x800000) | ||
220 | #define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v) ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000) | ||
221 | #define BP_LRADC_CTRL2_BL_ENABLE 22 | ||
222 | #define BM_LRADC_CTRL2_BL_ENABLE 0x400000 | ||
223 | #define BF_LRADC_CTRL2_BL_ENABLE(v) (((v) << 22) & 0x400000) | ||
224 | #define BP_LRADC_CTRL2_BL_MUX_SELECT 21 | ||
225 | #define BM_LRADC_CTRL2_BL_MUX_SELECT 0x200000 | ||
226 | #define BF_LRADC_CTRL2_BL_MUX_SELECT(v) (((v) << 21) & 0x200000) | ||
227 | #define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 | ||
228 | #define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x1f0000 | ||
229 | #define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) (((v) << 16) & 0x1f0000) | ||
230 | #define BP_LRADC_CTRL2_TEMPSENSE_PWD 15 | ||
231 | #define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x8000 | ||
232 | #define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x0 | ||
233 | #define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x1 | ||
234 | #define BF_LRADC_CTRL2_TEMPSENSE_PWD(v) (((v) << 15) & 0x8000) | ||
235 | #define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v) ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000) | ||
236 | #define BP_LRADC_CTRL2_EXT_EN1 13 | ||
237 | #define BM_LRADC_CTRL2_EXT_EN1 0x2000 | ||
238 | #define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0 | ||
239 | #define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1 | ||
240 | #define BF_LRADC_CTRL2_EXT_EN1(v) (((v) << 13) & 0x2000) | ||
241 | #define BF_LRADC_CTRL2_EXT_EN1_V(v) ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000) | ||
242 | #define BP_LRADC_CTRL2_EXT_EN0 12 | ||
243 | #define BM_LRADC_CTRL2_EXT_EN0 0x1000 | ||
244 | #define BF_LRADC_CTRL2_EXT_EN0(v) (((v) << 12) & 0x1000) | ||
245 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9 | ||
246 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200 | ||
247 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 | ||
248 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 | ||
249 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) << 9) & 0x200) | ||
250 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200) | ||
251 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8 | ||
252 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100 | ||
253 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 | ||
254 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 | ||
255 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) << 8) & 0x100) | ||
256 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100) | ||
257 | #define BP_LRADC_CTRL2_TEMP_ISRC1 4 | ||
258 | #define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0 | ||
259 | #define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf | ||
260 | #define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe | ||
261 | #define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd | ||
262 | #define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc | ||
263 | #define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb | ||
264 | #define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa | ||
265 | #define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 | ||
266 | #define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 | ||
267 | #define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 | ||
268 | #define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 | ||
269 | #define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 | ||
270 | #define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 | ||
271 | #define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 | ||
272 | #define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 | ||
273 | #define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 | ||
274 | #define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 | ||
275 | #define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) << 4) & 0xf0) | ||
276 | #define BF_LRADC_CTRL2_TEMP_ISRC1_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0) | ||
277 | #define BP_LRADC_CTRL2_TEMP_ISRC0 0 | ||
278 | #define BM_LRADC_CTRL2_TEMP_ISRC0 0xf | ||
279 | #define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf | ||
280 | #define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe | ||
281 | #define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd | ||
282 | #define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc | ||
283 | #define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb | ||
284 | #define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa | ||
285 | #define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 | ||
286 | #define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 | ||
287 | #define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 | ||
288 | #define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 | ||
289 | #define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 | ||
290 | #define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 | ||
291 | #define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 | ||
292 | #define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 | ||
293 | #define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 | ||
294 | #define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 | ||
295 | #define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) << 0) & 0xf) | ||
296 | #define BF_LRADC_CTRL2_TEMP_ISRC0_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf) | ||
297 | |||
298 | /** | ||
299 | * Register: HW_LRADC_CTRL3 | ||
300 | * Address: 0x30 | ||
301 | * SCT: yes | ||
302 | */ | ||
303 | #define HW_LRADC_CTRL3 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0)) | ||
304 | #define HW_LRADC_CTRL3_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4)) | ||
305 | #define HW_LRADC_CTRL3_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8)) | ||
306 | #define HW_LRADC_CTRL3_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc)) | ||
307 | #define BP_LRADC_CTRL3_DISCARD 24 | ||
308 | #define BM_LRADC_CTRL3_DISCARD 0x3000000 | ||
309 | #define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 | ||
310 | #define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 | ||
311 | #define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 | ||
312 | #define BF_LRADC_CTRL3_DISCARD(v) (((v) << 24) & 0x3000000) | ||
313 | #define BF_LRADC_CTRL3_DISCARD_V(v) ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000) | ||
314 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23 | ||
315 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000 | ||
316 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 | ||
317 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 | ||
318 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) << 23) & 0x800000) | ||
319 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000) | ||
320 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22 | ||
321 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000 | ||
322 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 | ||
323 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 | ||
324 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) << 22) & 0x400000) | ||
325 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000) | ||
326 | #define BP_LRADC_CTRL3_CYCLE_TIME 8 | ||
327 | #define BM_LRADC_CTRL3_CYCLE_TIME 0x300 | ||
328 | #define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 | ||
329 | #define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 | ||
330 | #define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 | ||
331 | #define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 | ||
332 | #define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) << 8) & 0x300) | ||
333 | #define BF_LRADC_CTRL3_CYCLE_TIME_V(v) ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300) | ||
334 | #define BP_LRADC_CTRL3_HIGH_TIME 4 | ||
335 | #define BM_LRADC_CTRL3_HIGH_TIME 0x30 | ||
336 | #define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 | ||
337 | #define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 | ||
338 | #define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 | ||
339 | #define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 | ||
340 | #define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) << 4) & 0x30) | ||
341 | #define BF_LRADC_CTRL3_HIGH_TIME_V(v) ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30) | ||
342 | #define BP_LRADC_CTRL3_DELAY_CLOCK 1 | ||
343 | #define BM_LRADC_CTRL3_DELAY_CLOCK 0x2 | ||
344 | #define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 | ||
345 | #define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 | ||
346 | #define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) << 1) & 0x2) | ||
347 | #define BF_LRADC_CTRL3_DELAY_CLOCK_V(v) ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2) | ||
348 | #define BP_LRADC_CTRL3_INVERT_CLOCK 0 | ||
349 | #define BM_LRADC_CTRL3_INVERT_CLOCK 0x1 | ||
350 | #define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 | ||
351 | #define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 | ||
352 | #define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) << 0) & 0x1) | ||
353 | #define BF_LRADC_CTRL3_INVERT_CLOCK_V(v) ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1) | ||
354 | |||
355 | /** | ||
356 | * Register: HW_LRADC_STATUS | ||
357 | * Address: 0x40 | ||
358 | * SCT: no | ||
359 | */ | ||
360 | #define HW_LRADC_STATUS (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40)) | ||
361 | #define BP_LRADC_STATUS_TEMP1_PRESENT 26 | ||
362 | #define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000 | ||
363 | #define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
364 | #define BP_LRADC_STATUS_TEMP0_PRESENT 25 | ||
365 | #define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000 | ||
366 | #define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
367 | #define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24 | ||
368 | #define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000 | ||
369 | #define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) << 24) & 0x1000000) | ||
370 | #define BP_LRADC_STATUS_CHANNEL7_PRESENT 23 | ||
371 | #define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000 | ||
372 | #define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) << 23) & 0x800000) | ||
373 | #define BP_LRADC_STATUS_CHANNEL6_PRESENT 22 | ||
374 | #define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000 | ||
375 | #define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) << 22) & 0x400000) | ||
376 | #define BP_LRADC_STATUS_CHANNEL5_PRESENT 21 | ||
377 | #define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000 | ||
378 | #define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) << 21) & 0x200000) | ||
379 | #define BP_LRADC_STATUS_CHANNEL4_PRESENT 20 | ||
380 | #define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000 | ||
381 | #define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) << 20) & 0x100000) | ||
382 | #define BP_LRADC_STATUS_CHANNEL3_PRESENT 19 | ||
383 | #define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000 | ||
384 | #define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) << 19) & 0x80000) | ||
385 | #define BP_LRADC_STATUS_CHANNEL2_PRESENT 18 | ||
386 | #define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000 | ||
387 | #define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) << 18) & 0x40000) | ||
388 | #define BP_LRADC_STATUS_CHANNEL1_PRESENT 17 | ||
389 | #define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000 | ||
390 | #define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) << 17) & 0x20000) | ||
391 | #define BP_LRADC_STATUS_CHANNEL0_PRESENT 16 | ||
392 | #define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000 | ||
393 | #define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) << 16) & 0x10000) | ||
394 | #define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 | ||
395 | #define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1 | ||
396 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 | ||
397 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 | ||
398 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) << 0) & 0x1) | ||
399 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1) | ||
400 | |||
401 | /** | ||
402 | * Register: HW_LRADC_CHn | ||
403 | * Address: 0x50+n*0x10 | ||
404 | * SCT: yes | ||
405 | */ | ||
406 | #define HW_LRADC_CHn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0)) | ||
407 | #define HW_LRADC_CHn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4)) | ||
408 | #define HW_LRADC_CHn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8)) | ||
409 | #define HW_LRADC_CHn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc)) | ||
410 | #define BP_LRADC_CHn_TOGGLE 31 | ||
411 | #define BM_LRADC_CHn_TOGGLE 0x80000000 | ||
412 | #define BF_LRADC_CHn_TOGGLE(v) (((v) << 31) & 0x80000000) | ||
413 | #define BP_LRADC_CHn_ACCUMULATE 29 | ||
414 | #define BM_LRADC_CHn_ACCUMULATE 0x20000000 | ||
415 | #define BF_LRADC_CHn_ACCUMULATE(v) (((v) << 29) & 0x20000000) | ||
416 | #define BP_LRADC_CHn_NUM_SAMPLES 24 | ||
417 | #define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000 | ||
418 | #define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000) | ||
419 | #define BP_LRADC_CHn_VALUE 0 | ||
420 | #define BM_LRADC_CHn_VALUE 0x3ffff | ||
421 | #define BF_LRADC_CHn_VALUE(v) (((v) << 0) & 0x3ffff) | ||
422 | |||
423 | /** | ||
424 | * Register: HW_LRADC_DELAYn | ||
425 | * Address: 0xd0+n*0x10 | ||
426 | * SCT: yes | ||
427 | */ | ||
428 | #define HW_LRADC_DELAYn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0)) | ||
429 | #define HW_LRADC_DELAYn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4)) | ||
430 | #define HW_LRADC_DELAYn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8)) | ||
431 | #define HW_LRADC_DELAYn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc)) | ||
432 | #define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 | ||
433 | #define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000 | ||
434 | #define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) << 24) & 0xff000000) | ||
435 | #define BP_LRADC_DELAYn_KICK 20 | ||
436 | #define BM_LRADC_DELAYn_KICK 0x100000 | ||
437 | #define BF_LRADC_DELAYn_KICK(v) (((v) << 20) & 0x100000) | ||
438 | #define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 | ||
439 | #define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000 | ||
440 | #define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) << 16) & 0xf0000) | ||
441 | #define BP_LRADC_DELAYn_LOOP_COUNT 11 | ||
442 | #define BM_LRADC_DELAYn_LOOP_COUNT 0xf800 | ||
443 | #define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) << 11) & 0xf800) | ||
444 | #define BP_LRADC_DELAYn_DELAY 0 | ||
445 | #define BM_LRADC_DELAYn_DELAY 0x7ff | ||
446 | #define BF_LRADC_DELAYn_DELAY(v) (((v) << 0) & 0x7ff) | ||
447 | |||
448 | /** | ||
449 | * Register: HW_LRADC_DEBUG0 | ||
450 | * Address: 0x110 | ||
451 | * SCT: no | ||
452 | */ | ||
453 | #define HW_LRADC_DEBUG0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110)) | ||
454 | #define BP_LRADC_DEBUG0_READONLY 16 | ||
455 | #define BM_LRADC_DEBUG0_READONLY 0xffff0000 | ||
456 | #define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000) | ||
457 | #define BP_LRADC_DEBUG0_STATE 0 | ||
458 | #define BM_LRADC_DEBUG0_STATE 0xfff | ||
459 | #define BF_LRADC_DEBUG0_STATE(v) (((v) << 0) & 0xfff) | ||
460 | |||
461 | /** | ||
462 | * Register: HW_LRADC_DEBUG1 | ||
463 | * Address: 0x120 | ||
464 | * SCT: yes | ||
465 | */ | ||
466 | #define HW_LRADC_DEBUG1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0)) | ||
467 | #define HW_LRADC_DEBUG1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4)) | ||
468 | #define HW_LRADC_DEBUG1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8)) | ||
469 | #define HW_LRADC_DEBUG1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc)) | ||
470 | #define BP_LRADC_DEBUG1_REQUEST 16 | ||
471 | #define BM_LRADC_DEBUG1_REQUEST 0xff0000 | ||
472 | #define BF_LRADC_DEBUG1_REQUEST(v) (((v) << 16) & 0xff0000) | ||
473 | #define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 | ||
474 | #define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00 | ||
475 | #define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) << 8) & 0x1f00) | ||
476 | #define BP_LRADC_DEBUG1_TESTMODE6 2 | ||
477 | #define BM_LRADC_DEBUG1_TESTMODE6 0x4 | ||
478 | #define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 | ||
479 | #define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 | ||
480 | #define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) << 2) & 0x4) | ||
481 | #define BF_LRADC_DEBUG1_TESTMODE6_V(v) ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4) | ||
482 | #define BP_LRADC_DEBUG1_TESTMODE5 1 | ||
483 | #define BM_LRADC_DEBUG1_TESTMODE5 0x2 | ||
484 | #define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 | ||
485 | #define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 | ||
486 | #define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) << 1) & 0x2) | ||
487 | #define BF_LRADC_DEBUG1_TESTMODE5_V(v) ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2) | ||
488 | #define BP_LRADC_DEBUG1_TESTMODE 0 | ||
489 | #define BM_LRADC_DEBUG1_TESTMODE 0x1 | ||
490 | #define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 | ||
491 | #define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 | ||
492 | #define BF_LRADC_DEBUG1_TESTMODE(v) (((v) << 0) & 0x1) | ||
493 | #define BF_LRADC_DEBUG1_TESTMODE_V(v) ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1) | ||
494 | |||
495 | /** | ||
496 | * Register: HW_LRADC_CONVERSION | ||
497 | * Address: 0x130 | ||
498 | * SCT: yes | ||
499 | */ | ||
500 | #define HW_LRADC_CONVERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0)) | ||
501 | #define HW_LRADC_CONVERSION_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4)) | ||
502 | #define HW_LRADC_CONVERSION_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8)) | ||
503 | #define HW_LRADC_CONVERSION_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc)) | ||
504 | #define BP_LRADC_CONVERSION_AUTOMATIC 20 | ||
505 | #define BM_LRADC_CONVERSION_AUTOMATIC 0x100000 | ||
506 | #define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 | ||
507 | #define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 | ||
508 | #define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) << 20) & 0x100000) | ||
509 | #define BF_LRADC_CONVERSION_AUTOMATIC_V(v) ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000) | ||
510 | #define BP_LRADC_CONVERSION_SCALE_FACTOR 16 | ||
511 | #define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000 | ||
512 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 | ||
513 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 | ||
514 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 | ||
515 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 | ||
516 | #define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) << 16) & 0x30000) | ||
517 | #define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v) ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000) | ||
518 | #define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 | ||
519 | #define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff | ||
520 | #define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) << 0) & 0x3ff) | ||
521 | |||
522 | /** | ||
523 | * Register: HW_LRADC_CTRL4 | ||
524 | * Address: 0x140 | ||
525 | * SCT: yes | ||
526 | */ | ||
527 | #define HW_LRADC_CTRL4 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0)) | ||
528 | #define HW_LRADC_CTRL4_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4)) | ||
529 | #define HW_LRADC_CTRL4_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8)) | ||
530 | #define HW_LRADC_CTRL4_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc)) | ||
531 | #define BP_LRADC_CTRL4_LRADC7SELECT 28 | ||
532 | #define BM_LRADC_CTRL4_LRADC7SELECT 0xf0000000 | ||
533 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 | ||
534 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 | ||
535 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 | ||
536 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 | ||
537 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 | ||
538 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 | ||
539 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 | ||
540 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 | ||
541 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 | ||
542 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 | ||
543 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xa | ||
544 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xb | ||
545 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xc | ||
546 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xd | ||
547 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xe | ||
548 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xf | ||
549 | #define BF_LRADC_CTRL4_LRADC7SELECT(v) (((v) << 28) & 0xf0000000) | ||
550 | #define BF_LRADC_CTRL4_LRADC7SELECT_V(v) ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000) | ||
551 | #define BP_LRADC_CTRL4_LRADC6SELECT 24 | ||
552 | #define BM_LRADC_CTRL4_LRADC6SELECT 0xf000000 | ||
553 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 | ||
554 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 | ||
555 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 | ||
556 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 | ||
557 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 | ||
558 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 | ||
559 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 | ||
560 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 | ||
561 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 | ||
562 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 | ||
563 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xa | ||
564 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xb | ||
565 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xc | ||
566 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xd | ||
567 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xe | ||
568 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xf | ||
569 | #define BF_LRADC_CTRL4_LRADC6SELECT(v) (((v) << 24) & 0xf000000) | ||
570 | #define BF_LRADC_CTRL4_LRADC6SELECT_V(v) ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000) | ||
571 | #define BP_LRADC_CTRL4_LRADC5SELECT 20 | ||
572 | #define BM_LRADC_CTRL4_LRADC5SELECT 0xf00000 | ||
573 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 | ||
574 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 | ||
575 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 | ||
576 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 | ||
577 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 | ||
578 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 | ||
579 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 | ||
580 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 | ||
581 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 | ||
582 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 | ||
583 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xa | ||
584 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xb | ||
585 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xc | ||
586 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xd | ||
587 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xe | ||
588 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xf | ||
589 | #define BF_LRADC_CTRL4_LRADC5SELECT(v) (((v) << 20) & 0xf00000) | ||
590 | #define BF_LRADC_CTRL4_LRADC5SELECT_V(v) ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000) | ||
591 | #define BP_LRADC_CTRL4_LRADC4SELECT 16 | ||
592 | #define BM_LRADC_CTRL4_LRADC4SELECT 0xf0000 | ||
593 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 | ||
594 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 | ||
595 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 | ||
596 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 | ||
597 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 | ||
598 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 | ||
599 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 | ||
600 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 | ||
601 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 | ||
602 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 | ||
603 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xa | ||
604 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xb | ||
605 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xc | ||
606 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xd | ||
607 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xe | ||
608 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xf | ||
609 | #define BF_LRADC_CTRL4_LRADC4SELECT(v) (((v) << 16) & 0xf0000) | ||
610 | #define BF_LRADC_CTRL4_LRADC4SELECT_V(v) ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000) | ||
611 | #define BP_LRADC_CTRL4_LRADC3SELECT 12 | ||
612 | #define BM_LRADC_CTRL4_LRADC3SELECT 0xf000 | ||
613 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 | ||
614 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 | ||
615 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 | ||
616 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 | ||
617 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 | ||
618 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 | ||
619 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 | ||
620 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 | ||
621 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 | ||
622 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 | ||
623 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xa | ||
624 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xb | ||
625 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xc | ||
626 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xd | ||
627 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xe | ||
628 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xf | ||
629 | #define BF_LRADC_CTRL4_LRADC3SELECT(v) (((v) << 12) & 0xf000) | ||
630 | #define BF_LRADC_CTRL4_LRADC3SELECT_V(v) ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000) | ||
631 | #define BP_LRADC_CTRL4_LRADC2SELECT 8 | ||
632 | #define BM_LRADC_CTRL4_LRADC2SELECT 0xf00 | ||
633 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 | ||
634 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 | ||
635 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 | ||
636 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 | ||
637 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 | ||
638 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 | ||
639 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 | ||
640 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 | ||
641 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 | ||
642 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 | ||
643 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xa | ||
644 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xb | ||
645 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xc | ||
646 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xd | ||
647 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xe | ||
648 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xf | ||
649 | #define BF_LRADC_CTRL4_LRADC2SELECT(v) (((v) << 8) & 0xf00) | ||
650 | #define BF_LRADC_CTRL4_LRADC2SELECT_V(v) ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00) | ||
651 | #define BP_LRADC_CTRL4_LRADC1SELECT 4 | ||
652 | #define BM_LRADC_CTRL4_LRADC1SELECT 0xf0 | ||
653 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 | ||
654 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 | ||
655 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 | ||
656 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 | ||
657 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 | ||
658 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 | ||
659 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 | ||
660 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 | ||
661 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 | ||
662 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 | ||
663 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xa | ||
664 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xb | ||
665 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xc | ||
666 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xd | ||
667 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xe | ||
668 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xf | ||
669 | #define BF_LRADC_CTRL4_LRADC1SELECT(v) (((v) << 4) & 0xf0) | ||
670 | #define BF_LRADC_CTRL4_LRADC1SELECT_V(v) ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0) | ||
671 | #define BP_LRADC_CTRL4_LRADC0SELECT 0 | ||
672 | #define BM_LRADC_CTRL4_LRADC0SELECT 0xf | ||
673 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 | ||
674 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 | ||
675 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 | ||
676 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 | ||
677 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 | ||
678 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 | ||
679 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 | ||
680 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 | ||
681 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 | ||
682 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 | ||
683 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xa | ||
684 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xb | ||
685 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xc | ||
686 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xd | ||
687 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xe | ||
688 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xf | ||
689 | #define BF_LRADC_CTRL4_LRADC0SELECT(v) (((v) << 0) & 0xf) | ||
690 | #define BF_LRADC_CTRL4_LRADC0SELECT_V(v) ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf) | ||
691 | |||
692 | /** | ||
693 | * Register: HW_LRADC_VERSION | ||
694 | * Address: 0x150 | ||
695 | * SCT: no | ||
696 | */ | ||
697 | #define HW_LRADC_VERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150)) | ||
698 | #define BP_LRADC_VERSION_MAJOR 24 | ||
699 | #define BM_LRADC_VERSION_MAJOR 0xff000000 | ||
700 | #define BF_LRADC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
701 | #define BP_LRADC_VERSION_MINOR 16 | ||
702 | #define BM_LRADC_VERSION_MINOR 0xff0000 | ||
703 | #define BF_LRADC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
704 | #define BP_LRADC_VERSION_STEP 0 | ||
705 | #define BM_LRADC_VERSION_STEP 0xffff | ||
706 | #define BF_LRADC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
707 | |||
708 | #endif /* __HEADERGEN__STMP3700__LRADC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h new file mode 100644 index 0000000000..082952fc95 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h | |||
@@ -0,0 +1,254 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__OCOTP__H__ | ||
24 | #define __HEADERGEN__STMP3700__OCOTP__H__ | ||
25 | |||
26 | #define REGS_OCOTP_BASE (0x8002c000) | ||
27 | |||
28 | #define REGS_OCOTP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_OCOTP_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_OCOTP_CTRL (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_OCOTP_CTRL_SET (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_OCOTP_CTRL_CLR (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_OCOTP_CTRL_TOG (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_OCOTP_CTRL_WR_UNLOCK 16 | ||
40 | #define BM_OCOTP_CTRL_WR_UNLOCK 0xffff0000 | ||
41 | #define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3e77 | ||
42 | #define BF_OCOTP_CTRL_WR_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
43 | #define BF_OCOTP_CTRL_WR_UNLOCK_V(v) ((BV_OCOTP_CTRL_WR_UNLOCK__##v << 16) & 0xffff0000) | ||
44 | #define BP_OCOTP_CTRL_RELOAD_SHADOWS 13 | ||
45 | #define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x2000 | ||
46 | #define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) (((v) << 13) & 0x2000) | ||
47 | #define BP_OCOTP_CTRL_RD_BANK_OPEN 12 | ||
48 | #define BM_OCOTP_CTRL_RD_BANK_OPEN 0x1000 | ||
49 | #define BF_OCOTP_CTRL_RD_BANK_OPEN(v) (((v) << 12) & 0x1000) | ||
50 | #define BP_OCOTP_CTRL_ERROR 9 | ||
51 | #define BM_OCOTP_CTRL_ERROR 0x200 | ||
52 | #define BF_OCOTP_CTRL_ERROR(v) (((v) << 9) & 0x200) | ||
53 | #define BP_OCOTP_CTRL_BUSY 8 | ||
54 | #define BM_OCOTP_CTRL_BUSY 0x100 | ||
55 | #define BF_OCOTP_CTRL_BUSY(v) (((v) << 8) & 0x100) | ||
56 | #define BP_OCOTP_CTRL_ADDR 0 | ||
57 | #define BM_OCOTP_CTRL_ADDR 0x1f | ||
58 | #define BF_OCOTP_CTRL_ADDR(v) (((v) << 0) & 0x1f) | ||
59 | |||
60 | /** | ||
61 | * Register: HW_OCOTP_DATA | ||
62 | * Address: 0x10 | ||
63 | * SCT: no | ||
64 | */ | ||
65 | #define HW_OCOTP_DATA (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x10)) | ||
66 | #define BP_OCOTP_DATA_DATA 0 | ||
67 | #define BM_OCOTP_DATA_DATA 0xffffffff | ||
68 | #define BF_OCOTP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_OCOTP_CUSTn | ||
72 | * Address: 0x20+n*0x10 | ||
73 | * SCT: no | ||
74 | */ | ||
75 | #define HW_OCOTP_CUSTn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x20+(n)*0x10)) | ||
76 | #define BP_OCOTP_CUSTn_BITS 0 | ||
77 | #define BM_OCOTP_CUSTn_BITS 0xffffffff | ||
78 | #define BF_OCOTP_CUSTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
79 | |||
80 | /** | ||
81 | * Register: HW_OCOTP_CRYPTOn | ||
82 | * Address: 0x60+n*0x10 | ||
83 | * SCT: no | ||
84 | */ | ||
85 | #define HW_OCOTP_CRYPTOn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x60+(n)*0x10)) | ||
86 | #define BP_OCOTP_CRYPTOn_BITS 0 | ||
87 | #define BM_OCOTP_CRYPTOn_BITS 0xffffffff | ||
88 | #define BF_OCOTP_CRYPTOn_BITS(v) (((v) << 0) & 0xffffffff) | ||
89 | |||
90 | /** | ||
91 | * Register: HW_OCOTP_HWCAPn | ||
92 | * Address: 0xa0+n*0x10 | ||
93 | * SCT: no | ||
94 | */ | ||
95 | #define HW_OCOTP_HWCAPn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0xa0+(n)*0x10)) | ||
96 | #define BP_OCOTP_HWCAPn_BITS 0 | ||
97 | #define BM_OCOTP_HWCAPn_BITS 0xffffffff | ||
98 | #define BF_OCOTP_HWCAPn_BITS(v) (((v) << 0) & 0xffffffff) | ||
99 | |||
100 | /** | ||
101 | * Register: HW_OCOTP_SWCAP | ||
102 | * Address: 0x100 | ||
103 | * SCT: no | ||
104 | */ | ||
105 | #define HW_OCOTP_SWCAP (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x100)) | ||
106 | #define BP_OCOTP_SWCAP_BITS 0 | ||
107 | #define BM_OCOTP_SWCAP_BITS 0xffffffff | ||
108 | #define BF_OCOTP_SWCAP_BITS(v) (((v) << 0) & 0xffffffff) | ||
109 | |||
110 | /** | ||
111 | * Register: HW_OCOTP_CUSTCAP | ||
112 | * Address: 0x110 | ||
113 | * SCT: no | ||
114 | */ | ||
115 | #define HW_OCOTP_CUSTCAP (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x110)) | ||
116 | #define BP_OCOTP_CUSTCAP_BITS 0 | ||
117 | #define BM_OCOTP_CUSTCAP_BITS 0xffffffff | ||
118 | #define BF_OCOTP_CUSTCAP_BITS(v) (((v) << 0) & 0xffffffff) | ||
119 | |||
120 | /** | ||
121 | * Register: HW_OCOTP_LOCK | ||
122 | * Address: 0x120 | ||
123 | * SCT: no | ||
124 | */ | ||
125 | #define HW_OCOTP_LOCK (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x120)) | ||
126 | #define BP_OCOTP_LOCK_ROM7 31 | ||
127 | #define BM_OCOTP_LOCK_ROM7 0x80000000 | ||
128 | #define BF_OCOTP_LOCK_ROM7(v) (((v) << 31) & 0x80000000) | ||
129 | #define BP_OCOTP_LOCK_ROM6 30 | ||
130 | #define BM_OCOTP_LOCK_ROM6 0x40000000 | ||
131 | #define BF_OCOTP_LOCK_ROM6(v) (((v) << 30) & 0x40000000) | ||
132 | #define BP_OCOTP_LOCK_ROM5 29 | ||
133 | #define BM_OCOTP_LOCK_ROM5 0x20000000 | ||
134 | #define BF_OCOTP_LOCK_ROM5(v) (((v) << 29) & 0x20000000) | ||
135 | #define BP_OCOTP_LOCK_ROM4 28 | ||
136 | #define BM_OCOTP_LOCK_ROM4 0x10000000 | ||
137 | #define BF_OCOTP_LOCK_ROM4(v) (((v) << 28) & 0x10000000) | ||
138 | #define BP_OCOTP_LOCK_ROM3 27 | ||
139 | #define BM_OCOTP_LOCK_ROM3 0x8000000 | ||
140 | #define BF_OCOTP_LOCK_ROM3(v) (((v) << 27) & 0x8000000) | ||
141 | #define BP_OCOTP_LOCK_ROM2 26 | ||
142 | #define BM_OCOTP_LOCK_ROM2 0x4000000 | ||
143 | #define BF_OCOTP_LOCK_ROM2(v) (((v) << 26) & 0x4000000) | ||
144 | #define BP_OCOTP_LOCK_ROM1 25 | ||
145 | #define BM_OCOTP_LOCK_ROM1 0x2000000 | ||
146 | #define BF_OCOTP_LOCK_ROM1(v) (((v) << 25) & 0x2000000) | ||
147 | #define BP_OCOTP_LOCK_ROM0 24 | ||
148 | #define BM_OCOTP_LOCK_ROM0 0x1000000 | ||
149 | #define BF_OCOTP_LOCK_ROM0(v) (((v) << 24) & 0x1000000) | ||
150 | #define BP_OCOTP_LOCK_HWSW_SHADOW_ALT 23 | ||
151 | #define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x800000 | ||
152 | #define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v) (((v) << 23) & 0x800000) | ||
153 | #define BP_OCOTP_LOCK_CRYPTODCP_ALT 22 | ||
154 | #define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x400000 | ||
155 | #define BF_OCOTP_LOCK_CRYPTODCP_ALT(v) (((v) << 22) & 0x400000) | ||
156 | #define BP_OCOTP_LOCK_CRYPTOKEY_ALT 21 | ||
157 | #define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x200000 | ||
158 | #define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v) (((v) << 21) & 0x200000) | ||
159 | #define BP_OCOTP_LOCK_PIN 20 | ||
160 | #define BM_OCOTP_LOCK_PIN 0x100000 | ||
161 | #define BF_OCOTP_LOCK_PIN(v) (((v) << 20) & 0x100000) | ||
162 | #define BP_OCOTP_LOCK_OPS 19 | ||
163 | #define BM_OCOTP_LOCK_OPS 0x80000 | ||
164 | #define BF_OCOTP_LOCK_OPS(v) (((v) << 19) & 0x80000) | ||
165 | #define BP_OCOTP_LOCK_UN2 18 | ||
166 | #define BM_OCOTP_LOCK_UN2 0x40000 | ||
167 | #define BF_OCOTP_LOCK_UN2(v) (((v) << 18) & 0x40000) | ||
168 | #define BP_OCOTP_LOCK_UN1 17 | ||
169 | #define BM_OCOTP_LOCK_UN1 0x20000 | ||
170 | #define BF_OCOTP_LOCK_UN1(v) (((v) << 17) & 0x20000) | ||
171 | #define BP_OCOTP_LOCK_UN0 16 | ||
172 | #define BM_OCOTP_LOCK_UN0 0x10000 | ||
173 | #define BF_OCOTP_LOCK_UN0(v) (((v) << 16) & 0x10000) | ||
174 | #define BP_OCOTP_LOCK_UNALLOCATED 10 | ||
175 | #define BM_OCOTP_LOCK_UNALLOCATED 0xfc00 | ||
176 | #define BF_OCOTP_LOCK_UNALLOCATED(v) (((v) << 10) & 0xfc00) | ||
177 | #define BP_OCOTP_LOCK_CUSTCAP 9 | ||
178 | #define BM_OCOTP_LOCK_CUSTCAP 0x200 | ||
179 | #define BF_OCOTP_LOCK_CUSTCAP(v) (((v) << 9) & 0x200) | ||
180 | #define BP_OCOTP_LOCK_HWSW 8 | ||
181 | #define BM_OCOTP_LOCK_HWSW 0x100 | ||
182 | #define BF_OCOTP_LOCK_HWSW(v) (((v) << 8) & 0x100) | ||
183 | #define BP_OCOTP_LOCK_CUSTCAP_SHADOW 7 | ||
184 | #define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x80 | ||
185 | #define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v) (((v) << 7) & 0x80) | ||
186 | #define BP_OCOTP_LOCK_HWSW_SHADOW 6 | ||
187 | #define BM_OCOTP_LOCK_HWSW_SHADOW 0x40 | ||
188 | #define BF_OCOTP_LOCK_HWSW_SHADOW(v) (((v) << 6) & 0x40) | ||
189 | #define BP_OCOTP_LOCK_CRYPTODCP 5 | ||
190 | #define BM_OCOTP_LOCK_CRYPTODCP 0x20 | ||
191 | #define BF_OCOTP_LOCK_CRYPTODCP(v) (((v) << 5) & 0x20) | ||
192 | #define BP_OCOTP_LOCK_CRYPTOKEY 4 | ||
193 | #define BM_OCOTP_LOCK_CRYPTOKEY 0x10 | ||
194 | #define BF_OCOTP_LOCK_CRYPTOKEY(v) (((v) << 4) & 0x10) | ||
195 | #define BP_OCOTP_LOCK_CUST3 3 | ||
196 | #define BM_OCOTP_LOCK_CUST3 0x8 | ||
197 | #define BF_OCOTP_LOCK_CUST3(v) (((v) << 3) & 0x8) | ||
198 | #define BP_OCOTP_LOCK_CUST2 2 | ||
199 | #define BM_OCOTP_LOCK_CUST2 0x4 | ||
200 | #define BF_OCOTP_LOCK_CUST2(v) (((v) << 2) & 0x4) | ||
201 | #define BP_OCOTP_LOCK_CUST1 1 | ||
202 | #define BM_OCOTP_LOCK_CUST1 0x2 | ||
203 | #define BF_OCOTP_LOCK_CUST1(v) (((v) << 1) & 0x2) | ||
204 | #define BP_OCOTP_LOCK_CUST0 0 | ||
205 | #define BM_OCOTP_LOCK_CUST0 0x1 | ||
206 | #define BF_OCOTP_LOCK_CUST0(v) (((v) << 0) & 0x1) | ||
207 | |||
208 | /** | ||
209 | * Register: HW_OCOTP_OPSn | ||
210 | * Address: 0x130+n*0x10 | ||
211 | * SCT: no | ||
212 | */ | ||
213 | #define HW_OCOTP_OPSn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x130+(n)*0x10)) | ||
214 | #define BP_OCOTP_OPSn_BITS 0 | ||
215 | #define BM_OCOTP_OPSn_BITS 0xffffffff | ||
216 | #define BF_OCOTP_OPSn_BITS(v) (((v) << 0) & 0xffffffff) | ||
217 | |||
218 | /** | ||
219 | * Register: HW_OCOTP_UNn | ||
220 | * Address: 0x170+n*0x10 | ||
221 | * SCT: no | ||
222 | */ | ||
223 | #define HW_OCOTP_UNn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x170+(n)*0x10)) | ||
224 | #define BP_OCOTP_UNn_BITS 0 | ||
225 | #define BM_OCOTP_UNn_BITS 0xffffffff | ||
226 | #define BF_OCOTP_UNn_BITS(v) (((v) << 0) & 0xffffffff) | ||
227 | |||
228 | /** | ||
229 | * Register: HW_OCOTP_ROMn | ||
230 | * Address: 0x1a0+n*0x10 | ||
231 | * SCT: no | ||
232 | */ | ||
233 | #define HW_OCOTP_ROMn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x1a0+(n)*0x10)) | ||
234 | #define BP_OCOTP_ROMn_BITS 0 | ||
235 | #define BM_OCOTP_ROMn_BITS 0xffffffff | ||
236 | #define BF_OCOTP_ROMn_BITS(v) (((v) << 0) & 0xffffffff) | ||
237 | |||
238 | /** | ||
239 | * Register: HW_OCOTP_VERSION | ||
240 | * Address: 0x220 | ||
241 | * SCT: no | ||
242 | */ | ||
243 | #define HW_OCOTP_VERSION (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x220)) | ||
244 | #define BP_OCOTP_VERSION_MAJOR 24 | ||
245 | #define BM_OCOTP_VERSION_MAJOR 0xff000000 | ||
246 | #define BF_OCOTP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
247 | #define BP_OCOTP_VERSION_MINOR 16 | ||
248 | #define BM_OCOTP_VERSION_MINOR 0xff0000 | ||
249 | #define BF_OCOTP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
250 | #define BP_OCOTP_VERSION_STEP 0 | ||
251 | #define BM_OCOTP_VERSION_STEP 0xffff | ||
252 | #define BF_OCOTP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
253 | |||
254 | #endif /* __HEADERGEN__STMP3700__OCOTP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h new file mode 100644 index 0000000000..bddc2dcfa9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h | |||
@@ -0,0 +1,213 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__PINCTRL__H__ | ||
24 | #define __HEADERGEN__STMP3700__PINCTRL__H__ | ||
25 | |||
26 | #define REGS_PINCTRL_BASE (0x80018000) | ||
27 | |||
28 | #define REGS_PINCTRL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_PINCTRL_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_PINCTRL_CTRL_SFTRST 31 | ||
40 | #define BM_PINCTRL_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_PINCTRL_CTRL_CLKGATE 30 | ||
43 | #define BM_PINCTRL_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_PINCTRL_CTRL_PRESENT3 29 | ||
46 | #define BM_PINCTRL_CTRL_PRESENT3 0x20000000 | ||
47 | #define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_PINCTRL_CTRL_PRESENT2 28 | ||
49 | #define BM_PINCTRL_CTRL_PRESENT2 0x10000000 | ||
50 | #define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_PINCTRL_CTRL_PRESENT1 27 | ||
52 | #define BM_PINCTRL_CTRL_PRESENT1 0x8000000 | ||
53 | #define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_PINCTRL_CTRL_PRESENT0 26 | ||
55 | #define BM_PINCTRL_CTRL_PRESENT0 0x4000000 | ||
56 | #define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_PINCTRL_CTRL_IRQOUT3 3 | ||
58 | #define BM_PINCTRL_CTRL_IRQOUT3 0x8 | ||
59 | #define BF_PINCTRL_CTRL_IRQOUT3(v) (((v) << 3) & 0x8) | ||
60 | #define BP_PINCTRL_CTRL_IRQOUT2 2 | ||
61 | #define BM_PINCTRL_CTRL_IRQOUT2 0x4 | ||
62 | #define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4) | ||
63 | #define BP_PINCTRL_CTRL_IRQOUT1 1 | ||
64 | #define BM_PINCTRL_CTRL_IRQOUT1 0x2 | ||
65 | #define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2) | ||
66 | #define BP_PINCTRL_CTRL_IRQOUT0 0 | ||
67 | #define BM_PINCTRL_CTRL_IRQOUT0 0x1 | ||
68 | #define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_PINCTRL_MUXSELn | ||
72 | * Address: 0x100+n*0x10 | ||
73 | * SCT: yes | ||
74 | */ | ||
75 | #define HW_PINCTRL_MUXSELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0)) | ||
76 | #define HW_PINCTRL_MUXSELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4)) | ||
77 | #define HW_PINCTRL_MUXSELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8)) | ||
78 | #define HW_PINCTRL_MUXSELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc)) | ||
79 | #define BP_PINCTRL_MUXSELn_BITS 0 | ||
80 | #define BM_PINCTRL_MUXSELn_BITS 0xffffffff | ||
81 | #define BF_PINCTRL_MUXSELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_PINCTRL_DRIVEn | ||
85 | * Address: 0x200+n*0x10 | ||
86 | * SCT: yes | ||
87 | */ | ||
88 | #define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0)) | ||
89 | #define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4)) | ||
90 | #define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8)) | ||
91 | #define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc)) | ||
92 | #define BP_PINCTRL_DRIVEn_BITS 0 | ||
93 | #define BM_PINCTRL_DRIVEn_BITS 0xffffffff | ||
94 | #define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
95 | |||
96 | /** | ||
97 | * Register: HW_PINCTRL_PULLn | ||
98 | * Address: 0x300+n*0x10 | ||
99 | * SCT: yes | ||
100 | */ | ||
101 | #define HW_PINCTRL_PULLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x0)) | ||
102 | #define HW_PINCTRL_PULLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x4)) | ||
103 | #define HW_PINCTRL_PULLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x8)) | ||
104 | #define HW_PINCTRL_PULLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0xc)) | ||
105 | #define BP_PINCTRL_PULLn_BITS 0 | ||
106 | #define BM_PINCTRL_PULLn_BITS 0xffffffff | ||
107 | #define BF_PINCTRL_PULLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_PINCTRL_DOUTn | ||
111 | * Address: 0x400+n*0x10 | ||
112 | * SCT: yes | ||
113 | */ | ||
114 | #define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0)) | ||
115 | #define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4)) | ||
116 | #define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8)) | ||
117 | #define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc)) | ||
118 | #define BP_PINCTRL_DOUTn_BITS 0 | ||
119 | #define BM_PINCTRL_DOUTn_BITS 0xffffffff | ||
120 | #define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_PINCTRL_DINn | ||
124 | * Address: 0x500+n*0x10 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0)) | ||
128 | #define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4)) | ||
129 | #define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8)) | ||
130 | #define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc)) | ||
131 | #define BP_PINCTRL_DINn_BITS 0 | ||
132 | #define BM_PINCTRL_DINn_BITS 0xffffffff | ||
133 | #define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff) | ||
134 | |||
135 | /** | ||
136 | * Register: HW_PINCTRL_DOEn | ||
137 | * Address: 0x600+n*0x10 | ||
138 | * SCT: yes | ||
139 | */ | ||
140 | #define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0)) | ||
141 | #define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4)) | ||
142 | #define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8)) | ||
143 | #define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc)) | ||
144 | #define BP_PINCTRL_DOEn_BITS 0 | ||
145 | #define BM_PINCTRL_DOEn_BITS 0xffffffff | ||
146 | #define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
147 | |||
148 | /** | ||
149 | * Register: HW_PINCTRL_PIN2IRQn | ||
150 | * Address: 0x700+n*0x10 | ||
151 | * SCT: yes | ||
152 | */ | ||
153 | #define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0)) | ||
154 | #define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4)) | ||
155 | #define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8)) | ||
156 | #define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc)) | ||
157 | #define BP_PINCTRL_PIN2IRQn_BITS 0 | ||
158 | #define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff | ||
159 | #define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff) | ||
160 | |||
161 | /** | ||
162 | * Register: HW_PINCTRL_IRQENn | ||
163 | * Address: 0x800+n*0x10 | ||
164 | * SCT: yes | ||
165 | */ | ||
166 | #define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0)) | ||
167 | #define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4)) | ||
168 | #define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8)) | ||
169 | #define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc)) | ||
170 | #define BP_PINCTRL_IRQENn_BITS 0 | ||
171 | #define BM_PINCTRL_IRQENn_BITS 0xffffffff | ||
172 | #define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_PINCTRL_IRQLEVELn | ||
176 | * Address: 0x900+n*0x10 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0)) | ||
180 | #define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4)) | ||
181 | #define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8)) | ||
182 | #define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc)) | ||
183 | #define BP_PINCTRL_IRQLEVELn_BITS 0 | ||
184 | #define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff | ||
185 | #define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
186 | |||
187 | /** | ||
188 | * Register: HW_PINCTRL_IRQPOLn | ||
189 | * Address: 0xa00+n*0x10 | ||
190 | * SCT: yes | ||
191 | */ | ||
192 | #define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0)) | ||
193 | #define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4)) | ||
194 | #define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8)) | ||
195 | #define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc)) | ||
196 | #define BP_PINCTRL_IRQPOLn_BITS 0 | ||
197 | #define BM_PINCTRL_IRQPOLn_BITS 0xffffffff | ||
198 | #define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
199 | |||
200 | /** | ||
201 | * Register: HW_PINCTRL_IRQSTATn | ||
202 | * Address: 0xb00+n*0x10 | ||
203 | * SCT: yes | ||
204 | */ | ||
205 | #define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0)) | ||
206 | #define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4)) | ||
207 | #define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8)) | ||
208 | #define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc)) | ||
209 | #define BP_PINCTRL_IRQSTATn_BITS 0 | ||
210 | #define BM_PINCTRL_IRQSTATn_BITS 0xffffffff | ||
211 | #define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff) | ||
212 | |||
213 | #endif /* __HEADERGEN__STMP3700__PINCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-power.h b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h new file mode 100644 index 0000000000..85116c79cb --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h | |||
@@ -0,0 +1,581 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__POWER__H__ | ||
24 | #define __HEADERGEN__STMP3700__POWER__H__ | ||
25 | |||
26 | #define REGS_POWER_BASE (0x80044000) | ||
27 | |||
28 | #define REGS_POWER_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_POWER_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_POWER_CTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0)) | ||
36 | #define HW_POWER_CTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4)) | ||
37 | #define HW_POWER_CTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8)) | ||
38 | #define HW_POWER_CTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc)) | ||
39 | #define BP_POWER_CTRL_CLKGATE 30 | ||
40 | #define BM_POWER_CTRL_CLKGATE 0x40000000 | ||
41 | #define BF_POWER_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
42 | #define BP_POWER_CTRL_PSWITCH_IRQ 22 | ||
43 | #define BM_POWER_CTRL_PSWITCH_IRQ 0x400000 | ||
44 | #define BF_POWER_CTRL_PSWITCH_IRQ(v) (((v) << 22) & 0x400000) | ||
45 | #define BP_POWER_CTRL_PSWITCH_IRQ_SRC 21 | ||
46 | #define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x200000 | ||
47 | #define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v) (((v) << 21) & 0x200000) | ||
48 | #define BP_POWER_CTRL_POLARITY_PSWITCH 20 | ||
49 | #define BM_POWER_CTRL_POLARITY_PSWITCH 0x100000 | ||
50 | #define BF_POWER_CTRL_POLARITY_PSWITCH(v) (((v) << 20) & 0x100000) | ||
51 | #define BP_POWER_CTRL_ENIRQ_PSWITCH 19 | ||
52 | #define BM_POWER_CTRL_ENIRQ_PSWITCH 0x80000 | ||
53 | #define BF_POWER_CTRL_ENIRQ_PSWITCH(v) (((v) << 19) & 0x80000) | ||
54 | #define BP_POWER_CTRL_POLARITY_LINREG_OK 18 | ||
55 | #define BM_POWER_CTRL_POLARITY_LINREG_OK 0x40000 | ||
56 | #define BF_POWER_CTRL_POLARITY_LINREG_OK(v) (((v) << 18) & 0x40000) | ||
57 | #define BP_POWER_CTRL_LINREG_OK_IRQ 17 | ||
58 | #define BM_POWER_CTRL_LINREG_OK_IRQ 0x20000 | ||
59 | #define BF_POWER_CTRL_LINREG_OK_IRQ(v) (((v) << 17) & 0x20000) | ||
60 | #define BP_POWER_CTRL_ENIRQ_LINREG_OK 16 | ||
61 | #define BM_POWER_CTRL_ENIRQ_LINREG_OK 0x10000 | ||
62 | #define BF_POWER_CTRL_ENIRQ_LINREG_OK(v) (((v) << 16) & 0x10000) | ||
63 | #define BP_POWER_CTRL_DC_OK_IRQ 15 | ||
64 | #define BM_POWER_CTRL_DC_OK_IRQ 0x8000 | ||
65 | #define BF_POWER_CTRL_DC_OK_IRQ(v) (((v) << 15) & 0x8000) | ||
66 | #define BP_POWER_CTRL_ENIRQ_DC_OK 14 | ||
67 | #define BM_POWER_CTRL_ENIRQ_DC_OK 0x4000 | ||
68 | #define BF_POWER_CTRL_ENIRQ_DC_OK(v) (((v) << 14) & 0x4000) | ||
69 | #define BP_POWER_CTRL_BATT_BO_IRQ 13 | ||
70 | #define BM_POWER_CTRL_BATT_BO_IRQ 0x2000 | ||
71 | #define BF_POWER_CTRL_BATT_BO_IRQ(v) (((v) << 13) & 0x2000) | ||
72 | #define BP_POWER_CTRL_ENIRQBATT_BO 12 | ||
73 | #define BM_POWER_CTRL_ENIRQBATT_BO 0x1000 | ||
74 | #define BF_POWER_CTRL_ENIRQBATT_BO(v) (((v) << 12) & 0x1000) | ||
75 | #define BP_POWER_CTRL_VDDIO_BO_IRQ 11 | ||
76 | #define BM_POWER_CTRL_VDDIO_BO_IRQ 0x800 | ||
77 | #define BF_POWER_CTRL_VDDIO_BO_IRQ(v) (((v) << 11) & 0x800) | ||
78 | #define BP_POWER_CTRL_ENIRQ_VDDIO_BO 10 | ||
79 | #define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x400 | ||
80 | #define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v) (((v) << 10) & 0x400) | ||
81 | #define BP_POWER_CTRL_VDDA_BO_IRQ 9 | ||
82 | #define BM_POWER_CTRL_VDDA_BO_IRQ 0x200 | ||
83 | #define BF_POWER_CTRL_VDDA_BO_IRQ(v) (((v) << 9) & 0x200) | ||
84 | #define BP_POWER_CTRL_ENIRQ_VDDA_BO 8 | ||
85 | #define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x100 | ||
86 | #define BF_POWER_CTRL_ENIRQ_VDDA_BO(v) (((v) << 8) & 0x100) | ||
87 | #define BP_POWER_CTRL_VDDD_BO_IRQ 7 | ||
88 | #define BM_POWER_CTRL_VDDD_BO_IRQ 0x80 | ||
89 | #define BF_POWER_CTRL_VDDD_BO_IRQ(v) (((v) << 7) & 0x80) | ||
90 | #define BP_POWER_CTRL_ENIRQ_VDDD_BO 6 | ||
91 | #define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x40 | ||
92 | #define BF_POWER_CTRL_ENIRQ_VDDD_BO(v) (((v) << 6) & 0x40) | ||
93 | #define BP_POWER_CTRL_POLARITY_VBUSVALID 5 | ||
94 | #define BM_POWER_CTRL_POLARITY_VBUSVALID 0x20 | ||
95 | #define BF_POWER_CTRL_POLARITY_VBUSVALID(v) (((v) << 5) & 0x20) | ||
96 | #define BP_POWER_CTRL_VBUSVALID_IRQ 4 | ||
97 | #define BM_POWER_CTRL_VBUSVALID_IRQ 0x10 | ||
98 | #define BF_POWER_CTRL_VBUSVALID_IRQ(v) (((v) << 4) & 0x10) | ||
99 | #define BP_POWER_CTRL_ENIRQ_VBUS_VALID 3 | ||
100 | #define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x8 | ||
101 | #define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v) (((v) << 3) & 0x8) | ||
102 | #define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 2 | ||
103 | #define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x4 | ||
104 | #define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v) (((v) << 2) & 0x4) | ||
105 | #define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 1 | ||
106 | #define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x2 | ||
107 | #define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v) (((v) << 1) & 0x2) | ||
108 | #define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 | ||
109 | #define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x1 | ||
110 | #define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v) (((v) << 0) & 0x1) | ||
111 | |||
112 | /** | ||
113 | * Register: HW_POWER_5VCTRL | ||
114 | * Address: 0x10 | ||
115 | * SCT: yes | ||
116 | */ | ||
117 | #define HW_POWER_5VCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0)) | ||
118 | #define HW_POWER_5VCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4)) | ||
119 | #define HW_POWER_5VCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8)) | ||
120 | #define HW_POWER_5VCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc)) | ||
121 | #define BP_POWER_5VCTRL_VBUSVALID_TRSH 10 | ||
122 | #define BM_POWER_5VCTRL_VBUSVALID_TRSH 0xc00 | ||
123 | #define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) (((v) << 10) & 0xc00) | ||
124 | #define BP_POWER_5VCTRL_PWDN_5VBRNOUT 8 | ||
125 | #define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x100 | ||
126 | #define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v) (((v) << 8) & 0x100) | ||
127 | #define BP_POWER_5VCTRL_ENABLE_ILIMIT 7 | ||
128 | #define BM_POWER_5VCTRL_ENABLE_ILIMIT 0x80 | ||
129 | #define BF_POWER_5VCTRL_ENABLE_ILIMIT(v) (((v) << 7) & 0x80) | ||
130 | #define BP_POWER_5VCTRL_DCDC_XFER 6 | ||
131 | #define BM_POWER_5VCTRL_DCDC_XFER 0x40 | ||
132 | #define BF_POWER_5VCTRL_DCDC_XFER(v) (((v) << 6) & 0x40) | ||
133 | #define BP_POWER_5VCTRL_EN_BATT_PULLDN 5 | ||
134 | #define BM_POWER_5VCTRL_EN_BATT_PULLDN 0x20 | ||
135 | #define BF_POWER_5VCTRL_EN_BATT_PULLDN(v) (((v) << 5) & 0x20) | ||
136 | #define BP_POWER_5VCTRL_VBUSVALID_5VDETECT 4 | ||
137 | #define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x10 | ||
138 | #define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v) (((v) << 4) & 0x10) | ||
139 | #define BP_POWER_5VCTRL_VBUSVALID_TO_B 3 | ||
140 | #define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x8 | ||
141 | #define BF_POWER_5VCTRL_VBUSVALID_TO_B(v) (((v) << 3) & 0x8) | ||
142 | #define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO 2 | ||
143 | #define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x4 | ||
144 | #define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v) (((v) << 2) & 0x4) | ||
145 | #define BP_POWER_5VCTRL_OTG_PWRUP_CMPS 1 | ||
146 | #define BM_POWER_5VCTRL_OTG_PWRUP_CMPS 0x2 | ||
147 | #define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v) (((v) << 1) & 0x2) | ||
148 | #define BP_POWER_5VCTRL_ENABLE_DCDC 0 | ||
149 | #define BM_POWER_5VCTRL_ENABLE_DCDC 0x1 | ||
150 | #define BF_POWER_5VCTRL_ENABLE_DCDC(v) (((v) << 0) & 0x1) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_POWER_MINPWR | ||
154 | * Address: 0x20 | ||
155 | * SCT: yes | ||
156 | */ | ||
157 | #define HW_POWER_MINPWR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0)) | ||
158 | #define HW_POWER_MINPWR_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4)) | ||
159 | #define HW_POWER_MINPWR_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8)) | ||
160 | #define HW_POWER_MINPWR_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc)) | ||
161 | #define BP_POWER_MINPWR_PWD_BO 11 | ||
162 | #define BM_POWER_MINPWR_PWD_BO 0x800 | ||
163 | #define BF_POWER_MINPWR_PWD_BO(v) (((v) << 11) & 0x800) | ||
164 | #define BP_POWER_MINPWR_USB_I_SUSPEND 10 | ||
165 | #define BM_POWER_MINPWR_USB_I_SUSPEND 0x400 | ||
166 | #define BF_POWER_MINPWR_USB_I_SUSPEND(v) (((v) << 10) & 0x400) | ||
167 | #define BP_POWER_MINPWR_ENABLE_OSC 9 | ||
168 | #define BM_POWER_MINPWR_ENABLE_OSC 0x200 | ||
169 | #define BF_POWER_MINPWR_ENABLE_OSC(v) (((v) << 9) & 0x200) | ||
170 | #define BP_POWER_MINPWR_SELECT_OSC 8 | ||
171 | #define BM_POWER_MINPWR_SELECT_OSC 0x100 | ||
172 | #define BF_POWER_MINPWR_SELECT_OSC(v) (((v) << 8) & 0x100) | ||
173 | #define BP_POWER_MINPWR_VBG_OFF 7 | ||
174 | #define BM_POWER_MINPWR_VBG_OFF 0x80 | ||
175 | #define BF_POWER_MINPWR_VBG_OFF(v) (((v) << 7) & 0x80) | ||
176 | #define BP_POWER_MINPWR_DOUBLE_FETS 6 | ||
177 | #define BM_POWER_MINPWR_DOUBLE_FETS 0x40 | ||
178 | #define BF_POWER_MINPWR_DOUBLE_FETS(v) (((v) << 6) & 0x40) | ||
179 | #define BP_POWER_MINPWR_HALF_FETS 5 | ||
180 | #define BM_POWER_MINPWR_HALF_FETS 0x20 | ||
181 | #define BF_POWER_MINPWR_HALF_FETS(v) (((v) << 5) & 0x20) | ||
182 | #define BP_POWER_MINPWR_LESSANA_I 4 | ||
183 | #define BM_POWER_MINPWR_LESSANA_I 0x10 | ||
184 | #define BF_POWER_MINPWR_LESSANA_I(v) (((v) << 4) & 0x10) | ||
185 | #define BP_POWER_MINPWR_PWD_XTAL24 3 | ||
186 | #define BM_POWER_MINPWR_PWD_XTAL24 0x8 | ||
187 | #define BF_POWER_MINPWR_PWD_XTAL24(v) (((v) << 3) & 0x8) | ||
188 | #define BP_POWER_MINPWR_DC_STOPCLK 2 | ||
189 | #define BM_POWER_MINPWR_DC_STOPCLK 0x4 | ||
190 | #define BF_POWER_MINPWR_DC_STOPCLK(v) (((v) << 2) & 0x4) | ||
191 | #define BP_POWER_MINPWR_EN_DC_PFM 1 | ||
192 | #define BM_POWER_MINPWR_EN_DC_PFM 0x2 | ||
193 | #define BF_POWER_MINPWR_EN_DC_PFM(v) (((v) << 1) & 0x2) | ||
194 | #define BP_POWER_MINPWR_DC_HALFCLK 0 | ||
195 | #define BM_POWER_MINPWR_DC_HALFCLK 0x1 | ||
196 | #define BF_POWER_MINPWR_DC_HALFCLK(v) (((v) << 0) & 0x1) | ||
197 | |||
198 | /** | ||
199 | * Register: HW_POWER_CHARGE | ||
200 | * Address: 0x30 | ||
201 | * SCT: yes | ||
202 | */ | ||
203 | #define HW_POWER_CHARGE (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0)) | ||
204 | #define HW_POWER_CHARGE_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4)) | ||
205 | #define HW_POWER_CHARGE_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8)) | ||
206 | #define HW_POWER_CHARGE_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc)) | ||
207 | #define BP_POWER_CHARGE_ENABLE_FAULT_DETECT 20 | ||
208 | #define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x100000 | ||
209 | #define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v) (((v) << 20) & 0x100000) | ||
210 | #define BP_POWER_CHARGE_CHRG_STS_OFF 19 | ||
211 | #define BM_POWER_CHARGE_CHRG_STS_OFF 0x80000 | ||
212 | #define BF_POWER_CHARGE_CHRG_STS_OFF(v) (((v) << 19) & 0x80000) | ||
213 | #define BP_POWER_CHARGE_USE_EXTERN_R 17 | ||
214 | #define BM_POWER_CHARGE_USE_EXTERN_R 0x20000 | ||
215 | #define BF_POWER_CHARGE_USE_EXTERN_R(v) (((v) << 17) & 0x20000) | ||
216 | #define BP_POWER_CHARGE_PWD_BATTCHRG 16 | ||
217 | #define BM_POWER_CHARGE_PWD_BATTCHRG 0x10000 | ||
218 | #define BF_POWER_CHARGE_PWD_BATTCHRG(v) (((v) << 16) & 0x10000) | ||
219 | #define BP_POWER_CHARGE_STOP_ILIMIT 8 | ||
220 | #define BM_POWER_CHARGE_STOP_ILIMIT 0xf00 | ||
221 | #define BF_POWER_CHARGE_STOP_ILIMIT(v) (((v) << 8) & 0xf00) | ||
222 | #define BP_POWER_CHARGE_BATTCHRG_I 0 | ||
223 | #define BM_POWER_CHARGE_BATTCHRG_I 0x3f | ||
224 | #define BF_POWER_CHARGE_BATTCHRG_I(v) (((v) << 0) & 0x3f) | ||
225 | |||
226 | /** | ||
227 | * Register: HW_POWER_VDDDCTRL | ||
228 | * Address: 0x40 | ||
229 | * SCT: no | ||
230 | */ | ||
231 | #define HW_POWER_VDDDCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40)) | ||
232 | #define BP_POWER_VDDDCTRL_ADJTN 28 | ||
233 | #define BM_POWER_VDDDCTRL_ADJTN 0xf0000000 | ||
234 | #define BF_POWER_VDDDCTRL_ADJTN(v) (((v) << 28) & 0xf0000000) | ||
235 | #define BP_POWER_VDDDCTRL_ALKALINE_CHARGE 24 | ||
236 | #define BM_POWER_VDDDCTRL_ALKALINE_CHARGE 0x1000000 | ||
237 | #define BF_POWER_VDDDCTRL_ALKALINE_CHARGE(v) (((v) << 24) & 0x1000000) | ||
238 | #define BP_POWER_VDDDCTRL_DISABLE_STEPPING 23 | ||
239 | #define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x800000 | ||
240 | #define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v) (((v) << 23) & 0x800000) | ||
241 | #define BP_POWER_VDDDCTRL_LINREG_FROM_BATT 22 | ||
242 | #define BM_POWER_VDDDCTRL_LINREG_FROM_BATT 0x400000 | ||
243 | #define BF_POWER_VDDDCTRL_LINREG_FROM_BATT(v) (((v) << 22) & 0x400000) | ||
244 | #define BP_POWER_VDDDCTRL_ENABLE_LINREG 21 | ||
245 | #define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x200000 | ||
246 | #define BF_POWER_VDDDCTRL_ENABLE_LINREG(v) (((v) << 21) & 0x200000) | ||
247 | #define BP_POWER_VDDDCTRL_DISABLE_FET 20 | ||
248 | #define BM_POWER_VDDDCTRL_DISABLE_FET 0x100000 | ||
249 | #define BF_POWER_VDDDCTRL_DISABLE_FET(v) (((v) << 20) & 0x100000) | ||
250 | #define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 | ||
251 | #define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x30000 | ||
252 | #define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) (((v) << 16) & 0x30000) | ||
253 | #define BP_POWER_VDDDCTRL_BO_OFFSET 8 | ||
254 | #define BM_POWER_VDDDCTRL_BO_OFFSET 0x700 | ||
255 | #define BF_POWER_VDDDCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
256 | #define BP_POWER_VDDDCTRL_TRG 0 | ||
257 | #define BM_POWER_VDDDCTRL_TRG 0x1f | ||
258 | #define BF_POWER_VDDDCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
259 | |||
260 | /** | ||
261 | * Register: HW_POWER_VDDACTRL | ||
262 | * Address: 0x50 | ||
263 | * SCT: no | ||
264 | */ | ||
265 | #define HW_POWER_VDDACTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50)) | ||
266 | #define BP_POWER_VDDACTRL_DISABLE_STEPPING 18 | ||
267 | #define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x40000 | ||
268 | #define BF_POWER_VDDACTRL_DISABLE_STEPPING(v) (((v) << 18) & 0x40000) | ||
269 | #define BP_POWER_VDDACTRL_ENABLE_LINREG 17 | ||
270 | #define BM_POWER_VDDACTRL_ENABLE_LINREG 0x20000 | ||
271 | #define BF_POWER_VDDACTRL_ENABLE_LINREG(v) (((v) << 17) & 0x20000) | ||
272 | #define BP_POWER_VDDACTRL_DISABLE_FET 16 | ||
273 | #define BM_POWER_VDDACTRL_DISABLE_FET 0x10000 | ||
274 | #define BF_POWER_VDDACTRL_DISABLE_FET(v) (((v) << 16) & 0x10000) | ||
275 | #define BP_POWER_VDDACTRL_LINREG_OFFSET 12 | ||
276 | #define BM_POWER_VDDACTRL_LINREG_OFFSET 0x3000 | ||
277 | #define BF_POWER_VDDACTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
278 | #define BP_POWER_VDDACTRL_BO_OFFSET 8 | ||
279 | #define BM_POWER_VDDACTRL_BO_OFFSET 0x700 | ||
280 | #define BF_POWER_VDDACTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
281 | #define BP_POWER_VDDACTRL_TRG 0 | ||
282 | #define BM_POWER_VDDACTRL_TRG 0x1f | ||
283 | #define BF_POWER_VDDACTRL_TRG(v) (((v) << 0) & 0x1f) | ||
284 | |||
285 | /** | ||
286 | * Register: HW_POWER_VDDIOCTRL | ||
287 | * Address: 0x60 | ||
288 | * SCT: no | ||
289 | */ | ||
290 | #define HW_POWER_VDDIOCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60)) | ||
291 | #define BP_POWER_VDDIOCTRL_ADJTN 16 | ||
292 | #define BM_POWER_VDDIOCTRL_ADJTN 0xf0000 | ||
293 | #define BF_POWER_VDDIOCTRL_ADJTN(v) (((v) << 16) & 0xf0000) | ||
294 | #define BP_POWER_VDDIOCTRL_DISABLE_STEPPING 15 | ||
295 | #define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x8000 | ||
296 | #define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v) (((v) << 15) & 0x8000) | ||
297 | #define BP_POWER_VDDIOCTRL_DISABLE_FET 14 | ||
298 | #define BM_POWER_VDDIOCTRL_DISABLE_FET 0x4000 | ||
299 | #define BF_POWER_VDDIOCTRL_DISABLE_FET(v) (((v) << 14) & 0x4000) | ||
300 | #define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 | ||
301 | #define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x3000 | ||
302 | #define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
303 | #define BP_POWER_VDDIOCTRL_BO_OFFSET 8 | ||
304 | #define BM_POWER_VDDIOCTRL_BO_OFFSET 0x700 | ||
305 | #define BF_POWER_VDDIOCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
306 | #define BP_POWER_VDDIOCTRL_TRG 0 | ||
307 | #define BM_POWER_VDDIOCTRL_TRG 0x1f | ||
308 | #define BF_POWER_VDDIOCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
309 | |||
310 | /** | ||
311 | * Register: HW_POWER_DCFUNCV | ||
312 | * Address: 0x70 | ||
313 | * SCT: no | ||
314 | */ | ||
315 | #define HW_POWER_DCFUNCV (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70)) | ||
316 | #define BP_POWER_DCFUNCV_VDDD 16 | ||
317 | #define BM_POWER_DCFUNCV_VDDD 0x3ff0000 | ||
318 | #define BF_POWER_DCFUNCV_VDDD(v) (((v) << 16) & 0x3ff0000) | ||
319 | #define BP_POWER_DCFUNCV_VDDIO 0 | ||
320 | #define BM_POWER_DCFUNCV_VDDIO 0x3ff | ||
321 | #define BF_POWER_DCFUNCV_VDDIO(v) (((v) << 0) & 0x3ff) | ||
322 | |||
323 | /** | ||
324 | * Register: HW_POWER_MISC | ||
325 | * Address: 0x80 | ||
326 | * SCT: no | ||
327 | */ | ||
328 | #define HW_POWER_MISC (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80)) | ||
329 | #define BP_POWER_MISC_FREQSEL 4 | ||
330 | #define BM_POWER_MISC_FREQSEL 0x30 | ||
331 | #define BF_POWER_MISC_FREQSEL(v) (((v) << 4) & 0x30) | ||
332 | #define BP_POWER_MISC_DELAY_TIMING 3 | ||
333 | #define BM_POWER_MISC_DELAY_TIMING 0x8 | ||
334 | #define BF_POWER_MISC_DELAY_TIMING(v) (((v) << 3) & 0x8) | ||
335 | #define BP_POWER_MISC_TEST 2 | ||
336 | #define BM_POWER_MISC_TEST 0x4 | ||
337 | #define BF_POWER_MISC_TEST(v) (((v) << 2) & 0x4) | ||
338 | #define BP_POWER_MISC_SEL_PLLCLK 1 | ||
339 | #define BM_POWER_MISC_SEL_PLLCLK 0x2 | ||
340 | #define BF_POWER_MISC_SEL_PLLCLK(v) (((v) << 1) & 0x2) | ||
341 | #define BP_POWER_MISC_PERIPHERALSWOFF 0 | ||
342 | #define BM_POWER_MISC_PERIPHERALSWOFF 0x1 | ||
343 | #define BF_POWER_MISC_PERIPHERALSWOFF(v) (((v) << 0) & 0x1) | ||
344 | |||
345 | /** | ||
346 | * Register: HW_POWER_DCLIMITS | ||
347 | * Address: 0x90 | ||
348 | * SCT: no | ||
349 | */ | ||
350 | #define HW_POWER_DCLIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90)) | ||
351 | #define BP_POWER_DCLIMITS_POSLIMIT_BOOST 16 | ||
352 | #define BM_POWER_DCLIMITS_POSLIMIT_BOOST 0x7f0000 | ||
353 | #define BF_POWER_DCLIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) | ||
354 | #define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 | ||
355 | #define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x7f00 | ||
356 | #define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
357 | #define BP_POWER_DCLIMITS_NEGLIMIT 0 | ||
358 | #define BM_POWER_DCLIMITS_NEGLIMIT 0x7f | ||
359 | #define BF_POWER_DCLIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
360 | |||
361 | /** | ||
362 | * Register: HW_POWER_LOOPCTRL | ||
363 | * Address: 0xa0 | ||
364 | * SCT: yes | ||
365 | */ | ||
366 | #define HW_POWER_LOOPCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0)) | ||
367 | #define HW_POWER_LOOPCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4)) | ||
368 | #define HW_POWER_LOOPCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8)) | ||
369 | #define HW_POWER_LOOPCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc)) | ||
370 | #define BP_POWER_LOOPCTRL_TOGGLE_DIF 20 | ||
371 | #define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x100000 | ||
372 | #define BF_POWER_LOOPCTRL_TOGGLE_DIF(v) (((v) << 20) & 0x100000) | ||
373 | #define BP_POWER_LOOPCTRL_HYST_SIGN 19 | ||
374 | #define BM_POWER_LOOPCTRL_HYST_SIGN 0x80000 | ||
375 | #define BF_POWER_LOOPCTRL_HYST_SIGN(v) (((v) << 19) & 0x80000) | ||
376 | #define BP_POWER_LOOPCTRL_EN_CM_HYST 18 | ||
377 | #define BM_POWER_LOOPCTRL_EN_CM_HYST 0x40000 | ||
378 | #define BF_POWER_LOOPCTRL_EN_CM_HYST(v) (((v) << 18) & 0x40000) | ||
379 | #define BP_POWER_LOOPCTRL_EN_DF_HYST 17 | ||
380 | #define BM_POWER_LOOPCTRL_EN_DF_HYST 0x20000 | ||
381 | #define BF_POWER_LOOPCTRL_EN_DF_HYST(v) (((v) << 17) & 0x20000) | ||
382 | #define BP_POWER_LOOPCTRL_CM_HYST_THRESH 16 | ||
383 | #define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x10000 | ||
384 | #define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000) | ||
385 | #define BP_POWER_LOOPCTRL_DF_HYST_THRESH 15 | ||
386 | #define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x8000 | ||
387 | #define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000) | ||
388 | #define BP_POWER_LOOPCTRL_RCSCALE_THRESH 14 | ||
389 | #define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x4000 | ||
390 | #define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000) | ||
391 | #define BP_POWER_LOOPCTRL_EN_RCSCALE 12 | ||
392 | #define BM_POWER_LOOPCTRL_EN_RCSCALE 0x3000 | ||
393 | #define BF_POWER_LOOPCTRL_EN_RCSCALE(v) (((v) << 12) & 0x3000) | ||
394 | #define BP_POWER_LOOPCTRL_DC_FF 8 | ||
395 | #define BM_POWER_LOOPCTRL_DC_FF 0x700 | ||
396 | #define BF_POWER_LOOPCTRL_DC_FF(v) (((v) << 8) & 0x700) | ||
397 | #define BP_POWER_LOOPCTRL_DC_R 4 | ||
398 | #define BM_POWER_LOOPCTRL_DC_R 0xf0 | ||
399 | #define BF_POWER_LOOPCTRL_DC_R(v) (((v) << 4) & 0xf0) | ||
400 | #define BP_POWER_LOOPCTRL_DC_C 0 | ||
401 | #define BM_POWER_LOOPCTRL_DC_C 0x3 | ||
402 | #define BF_POWER_LOOPCTRL_DC_C(v) (((v) << 0) & 0x3) | ||
403 | |||
404 | /** | ||
405 | * Register: HW_POWER_STS | ||
406 | * Address: 0xb0 | ||
407 | * SCT: no | ||
408 | */ | ||
409 | #define HW_POWER_STS (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0)) | ||
410 | #define BP_POWER_STS_BATT_CHRG_PRESENT 31 | ||
411 | #define BM_POWER_STS_BATT_CHRG_PRESENT 0x80000000 | ||
412 | #define BF_POWER_STS_BATT_CHRG_PRESENT(v) (((v) << 31) & 0x80000000) | ||
413 | #define BP_POWER_STS_PSWITCH 18 | ||
414 | #define BM_POWER_STS_PSWITCH 0xc0000 | ||
415 | #define BF_POWER_STS_PSWITCH(v) (((v) << 18) & 0xc0000) | ||
416 | #define BP_POWER_STS_AVALID_STATUS 17 | ||
417 | #define BM_POWER_STS_AVALID_STATUS 0x20000 | ||
418 | #define BF_POWER_STS_AVALID_STATUS(v) (((v) << 17) & 0x20000) | ||
419 | #define BP_POWER_STS_BVALID_STATUS 16 | ||
420 | #define BM_POWER_STS_BVALID_STATUS 0x10000 | ||
421 | #define BF_POWER_STS_BVALID_STATUS(v) (((v) << 16) & 0x10000) | ||
422 | #define BP_POWER_STS_VBUSVALID_STATUS 15 | ||
423 | #define BM_POWER_STS_VBUSVALID_STATUS 0x8000 | ||
424 | #define BF_POWER_STS_VBUSVALID_STATUS(v) (((v) << 15) & 0x8000) | ||
425 | #define BP_POWER_STS_SESSEND_STATUS 14 | ||
426 | #define BM_POWER_STS_SESSEND_STATUS 0x4000 | ||
427 | #define BF_POWER_STS_SESSEND_STATUS(v) (((v) << 14) & 0x4000) | ||
428 | #define BP_POWER_STS_MODE 13 | ||
429 | #define BM_POWER_STS_MODE 0x2000 | ||
430 | #define BF_POWER_STS_MODE(v) (((v) << 13) & 0x2000) | ||
431 | #define BP_POWER_STS_BATT_BO 12 | ||
432 | #define BM_POWER_STS_BATT_BO 0x1000 | ||
433 | #define BF_POWER_STS_BATT_BO(v) (((v) << 12) & 0x1000) | ||
434 | #define BP_POWER_STS_VDD5V_FAULT 11 | ||
435 | #define BM_POWER_STS_VDD5V_FAULT 0x800 | ||
436 | #define BF_POWER_STS_VDD5V_FAULT(v) (((v) << 11) & 0x800) | ||
437 | #define BP_POWER_STS_CHRGSTS 10 | ||
438 | #define BM_POWER_STS_CHRGSTS 0x400 | ||
439 | #define BF_POWER_STS_CHRGSTS(v) (((v) << 10) & 0x400) | ||
440 | #define BP_POWER_STS_LINREG_OK 9 | ||
441 | #define BM_POWER_STS_LINREG_OK 0x200 | ||
442 | #define BF_POWER_STS_LINREG_OK(v) (((v) << 9) & 0x200) | ||
443 | #define BP_POWER_STS_DC_OK 8 | ||
444 | #define BM_POWER_STS_DC_OK 0x100 | ||
445 | #define BF_POWER_STS_DC_OK(v) (((v) << 8) & 0x100) | ||
446 | #define BP_POWER_STS_VDDIO_BO 7 | ||
447 | #define BM_POWER_STS_VDDIO_BO 0x80 | ||
448 | #define BF_POWER_STS_VDDIO_BO(v) (((v) << 7) & 0x80) | ||
449 | #define BP_POWER_STS_VDDA_BO 6 | ||
450 | #define BM_POWER_STS_VDDA_BO 0x40 | ||
451 | #define BF_POWER_STS_VDDA_BO(v) (((v) << 6) & 0x40) | ||
452 | #define BP_POWER_STS_VDDD_BO 5 | ||
453 | #define BM_POWER_STS_VDDD_BO 0x20 | ||
454 | #define BF_POWER_STS_VDDD_BO(v) (((v) << 5) & 0x20) | ||
455 | #define BP_POWER_STS_VDD5V_GT_VDDIO 4 | ||
456 | #define BM_POWER_STS_VDD5V_GT_VDDIO 0x10 | ||
457 | #define BF_POWER_STS_VDD5V_GT_VDDIO(v) (((v) << 4) & 0x10) | ||
458 | #define BP_POWER_STS_AVALID 3 | ||
459 | #define BM_POWER_STS_AVALID 0x8 | ||
460 | #define BF_POWER_STS_AVALID(v) (((v) << 3) & 0x8) | ||
461 | #define BP_POWER_STS_BVALID 2 | ||
462 | #define BM_POWER_STS_BVALID 0x4 | ||
463 | #define BF_POWER_STS_BVALID(v) (((v) << 2) & 0x4) | ||
464 | #define BP_POWER_STS_VBUSVALID 1 | ||
465 | #define BM_POWER_STS_VBUSVALID 0x2 | ||
466 | #define BF_POWER_STS_VBUSVALID(v) (((v) << 1) & 0x2) | ||
467 | #define BP_POWER_STS_SESSEND 0 | ||
468 | #define BM_POWER_STS_SESSEND 0x1 | ||
469 | #define BF_POWER_STS_SESSEND(v) (((v) << 0) & 0x1) | ||
470 | |||
471 | /** | ||
472 | * Register: HW_POWER_SPEED | ||
473 | * Address: 0xc0 | ||
474 | * SCT: yes | ||
475 | */ | ||
476 | #define HW_POWER_SPEED (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0)) | ||
477 | #define HW_POWER_SPEED_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4)) | ||
478 | #define HW_POWER_SPEED_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8)) | ||
479 | #define HW_POWER_SPEED_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc)) | ||
480 | #define BP_POWER_SPEED_STATUS 16 | ||
481 | #define BM_POWER_SPEED_STATUS 0xff0000 | ||
482 | #define BF_POWER_SPEED_STATUS(v) (((v) << 16) & 0xff0000) | ||
483 | #define BP_POWER_SPEED_CTRL 0 | ||
484 | #define BM_POWER_SPEED_CTRL 0x3 | ||
485 | #define BF_POWER_SPEED_CTRL(v) (((v) << 0) & 0x3) | ||
486 | |||
487 | /** | ||
488 | * Register: HW_POWER_BATTMONITOR | ||
489 | * Address: 0xd0 | ||
490 | * SCT: no | ||
491 | */ | ||
492 | #define HW_POWER_BATTMONITOR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0)) | ||
493 | #define BP_POWER_BATTMONITOR_BATT_VAL 16 | ||
494 | #define BM_POWER_BATTMONITOR_BATT_VAL 0x3ff0000 | ||
495 | #define BF_POWER_BATTMONITOR_BATT_VAL(v) (((v) << 16) & 0x3ff0000) | ||
496 | #define BP_POWER_BATTMONITOR_EN_BATADJ 6 | ||
497 | #define BM_POWER_BATTMONITOR_EN_BATADJ 0x40 | ||
498 | #define BF_POWER_BATTMONITOR_EN_BATADJ(v) (((v) << 6) & 0x40) | ||
499 | #define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT 5 | ||
500 | #define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x20 | ||
501 | #define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 5) & 0x20) | ||
502 | #define BP_POWER_BATTMONITOR_BRWNOUT_PWD 4 | ||
503 | #define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x10 | ||
504 | #define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v) (((v) << 4) & 0x10) | ||
505 | #define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 | ||
506 | #define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0xf | ||
507 | #define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) (((v) << 0) & 0xf) | ||
508 | |||
509 | /** | ||
510 | * Register: HW_POWER_RESET | ||
511 | * Address: 0xe0 | ||
512 | * SCT: yes | ||
513 | */ | ||
514 | #define HW_POWER_RESET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x0)) | ||
515 | #define HW_POWER_RESET_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x4)) | ||
516 | #define HW_POWER_RESET_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x8)) | ||
517 | #define HW_POWER_RESET_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0xc)) | ||
518 | #define BP_POWER_RESET_UNLOCK 16 | ||
519 | #define BM_POWER_RESET_UNLOCK 0xffff0000 | ||
520 | #define BV_POWER_RESET_UNLOCK__KEY 0x3e77 | ||
521 | #define BF_POWER_RESET_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
522 | #define BF_POWER_RESET_UNLOCK_V(v) ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000) | ||
523 | #define BP_POWER_RESET_PWD_OFF 1 | ||
524 | #define BM_POWER_RESET_PWD_OFF 0x2 | ||
525 | #define BF_POWER_RESET_PWD_OFF(v) (((v) << 1) & 0x2) | ||
526 | #define BP_POWER_RESET_PWD 0 | ||
527 | #define BM_POWER_RESET_PWD 0x1 | ||
528 | #define BF_POWER_RESET_PWD(v) (((v) << 0) & 0x1) | ||
529 | |||
530 | /** | ||
531 | * Register: HW_POWER_DEBUG | ||
532 | * Address: 0xf0 | ||
533 | * SCT: yes | ||
534 | */ | ||
535 | #define HW_POWER_DEBUG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x0)) | ||
536 | #define HW_POWER_DEBUG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x4)) | ||
537 | #define HW_POWER_DEBUG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x8)) | ||
538 | #define HW_POWER_DEBUG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0xc)) | ||
539 | #define BP_POWER_DEBUG_VBUSVALIDPIOLOCK 3 | ||
540 | #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x8 | ||
541 | #define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v) (((v) << 3) & 0x8) | ||
542 | #define BP_POWER_DEBUG_AVALIDPIOLOCK 2 | ||
543 | #define BM_POWER_DEBUG_AVALIDPIOLOCK 0x4 | ||
544 | #define BF_POWER_DEBUG_AVALIDPIOLOCK(v) (((v) << 2) & 0x4) | ||
545 | #define BP_POWER_DEBUG_BVALIDPIOLOCK 1 | ||
546 | #define BM_POWER_DEBUG_BVALIDPIOLOCK 0x2 | ||
547 | #define BF_POWER_DEBUG_BVALIDPIOLOCK(v) (((v) << 1) & 0x2) | ||
548 | #define BP_POWER_DEBUG_SESSENDPIOLOCK 0 | ||
549 | #define BM_POWER_DEBUG_SESSENDPIOLOCK 0x1 | ||
550 | #define BF_POWER_DEBUG_SESSENDPIOLOCK(v) (((v) << 0) & 0x1) | ||
551 | |||
552 | /** | ||
553 | * Register: HW_POWER_SPECIAL | ||
554 | * Address: 0x100 | ||
555 | * SCT: yes | ||
556 | */ | ||
557 | #define HW_POWER_SPECIAL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0)) | ||
558 | #define HW_POWER_SPECIAL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4)) | ||
559 | #define HW_POWER_SPECIAL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8)) | ||
560 | #define HW_POWER_SPECIAL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc)) | ||
561 | #define BP_POWER_SPECIAL_TEST 0 | ||
562 | #define BM_POWER_SPECIAL_TEST 0xffffffff | ||
563 | #define BF_POWER_SPECIAL_TEST(v) (((v) << 0) & 0xffffffff) | ||
564 | |||
565 | /** | ||
566 | * Register: HW_POWER_VERSION | ||
567 | * Address: 0x110 | ||
568 | * SCT: no | ||
569 | */ | ||
570 | #define HW_POWER_VERSION (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110)) | ||
571 | #define BP_POWER_VERSION_MAJOR 24 | ||
572 | #define BM_POWER_VERSION_MAJOR 0xff000000 | ||
573 | #define BF_POWER_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
574 | #define BP_POWER_VERSION_MINOR 16 | ||
575 | #define BM_POWER_VERSION_MINOR 0xff0000 | ||
576 | #define BF_POWER_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
577 | #define BP_POWER_VERSION_STEP 0 | ||
578 | #define BM_POWER_VERSION_STEP 0xffff | ||
579 | #define BF_POWER_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
580 | |||
581 | #endif /* __HEADERGEN__STMP3700__POWER__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h new file mode 100644 index 0000000000..4d7b385d10 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h | |||
@@ -0,0 +1,153 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__PWM__H__ | ||
24 | #define __HEADERGEN__STMP3700__PWM__H__ | ||
25 | |||
26 | #define REGS_PWM_BASE (0x80064000) | ||
27 | |||
28 | #define REGS_PWM_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_PWM_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_PWM_CTRL (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0)) | ||
36 | #define HW_PWM_CTRL_SET (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4)) | ||
37 | #define HW_PWM_CTRL_CLR (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8)) | ||
38 | #define HW_PWM_CTRL_TOG (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc)) | ||
39 | #define BP_PWM_CTRL_SFTRST 31 | ||
40 | #define BM_PWM_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_PWM_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_PWM_CTRL_CLKGATE 30 | ||
43 | #define BM_PWM_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_PWM_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_PWM_CTRL_PWM4_PRESENT 29 | ||
46 | #define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 | ||
47 | #define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_PWM_CTRL_PWM3_PRESENT 28 | ||
49 | #define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 | ||
50 | #define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_PWM_CTRL_PWM2_PRESENT 27 | ||
52 | #define BM_PWM_CTRL_PWM2_PRESENT 0x8000000 | ||
53 | #define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_PWM_CTRL_PWM1_PRESENT 26 | ||
55 | #define BM_PWM_CTRL_PWM1_PRESENT 0x4000000 | ||
56 | #define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_PWM_CTRL_PWM0_PRESENT 25 | ||
58 | #define BM_PWM_CTRL_PWM0_PRESENT 0x2000000 | ||
59 | #define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 5 | ||
61 | #define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x20 | ||
62 | #define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v) (((v) << 5) & 0x20) | ||
63 | #define BP_PWM_CTRL_PWM4_ENABLE 4 | ||
64 | #define BM_PWM_CTRL_PWM4_ENABLE 0x10 | ||
65 | #define BF_PWM_CTRL_PWM4_ENABLE(v) (((v) << 4) & 0x10) | ||
66 | #define BP_PWM_CTRL_PWM3_ENABLE 3 | ||
67 | #define BM_PWM_CTRL_PWM3_ENABLE 0x8 | ||
68 | #define BF_PWM_CTRL_PWM3_ENABLE(v) (((v) << 3) & 0x8) | ||
69 | #define BP_PWM_CTRL_PWM2_ENABLE 2 | ||
70 | #define BM_PWM_CTRL_PWM2_ENABLE 0x4 | ||
71 | #define BF_PWM_CTRL_PWM2_ENABLE(v) (((v) << 2) & 0x4) | ||
72 | #define BP_PWM_CTRL_PWM1_ENABLE 1 | ||
73 | #define BM_PWM_CTRL_PWM1_ENABLE 0x2 | ||
74 | #define BF_PWM_CTRL_PWM1_ENABLE(v) (((v) << 1) & 0x2) | ||
75 | #define BP_PWM_CTRL_PWM0_ENABLE 0 | ||
76 | #define BM_PWM_CTRL_PWM0_ENABLE 0x1 | ||
77 | #define BF_PWM_CTRL_PWM0_ENABLE(v) (((v) << 0) & 0x1) | ||
78 | |||
79 | /** | ||
80 | * Register: HW_PWM_ACTIVEn | ||
81 | * Address: 0x10+n*0x20 | ||
82 | * SCT: yes | ||
83 | */ | ||
84 | #define HW_PWM_ACTIVEn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0)) | ||
85 | #define HW_PWM_ACTIVEn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4)) | ||
86 | #define HW_PWM_ACTIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8)) | ||
87 | #define HW_PWM_ACTIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc)) | ||
88 | #define BP_PWM_ACTIVEn_INACTIVE 16 | ||
89 | #define BM_PWM_ACTIVEn_INACTIVE 0xffff0000 | ||
90 | #define BF_PWM_ACTIVEn_INACTIVE(v) (((v) << 16) & 0xffff0000) | ||
91 | #define BP_PWM_ACTIVEn_ACTIVE 0 | ||
92 | #define BM_PWM_ACTIVEn_ACTIVE 0xffff | ||
93 | #define BF_PWM_ACTIVEn_ACTIVE(v) (((v) << 0) & 0xffff) | ||
94 | |||
95 | /** | ||
96 | * Register: HW_PWM_PERIODn | ||
97 | * Address: 0x20+n*0x20 | ||
98 | * SCT: yes | ||
99 | */ | ||
100 | #define HW_PWM_PERIODn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0)) | ||
101 | #define HW_PWM_PERIODn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4)) | ||
102 | #define HW_PWM_PERIODn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8)) | ||
103 | #define HW_PWM_PERIODn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc)) | ||
104 | #define BP_PWM_PERIODn_MATT 23 | ||
105 | #define BM_PWM_PERIODn_MATT 0x800000 | ||
106 | #define BF_PWM_PERIODn_MATT(v) (((v) << 23) & 0x800000) | ||
107 | #define BP_PWM_PERIODn_CDIV 20 | ||
108 | #define BM_PWM_PERIODn_CDIV 0x700000 | ||
109 | #define BV_PWM_PERIODn_CDIV__DIV_1 0x0 | ||
110 | #define BV_PWM_PERIODn_CDIV__DIV_2 0x1 | ||
111 | #define BV_PWM_PERIODn_CDIV__DIV_4 0x2 | ||
112 | #define BV_PWM_PERIODn_CDIV__DIV_8 0x3 | ||
113 | #define BV_PWM_PERIODn_CDIV__DIV_16 0x4 | ||
114 | #define BV_PWM_PERIODn_CDIV__DIV_64 0x5 | ||
115 | #define BV_PWM_PERIODn_CDIV__DIV_256 0x6 | ||
116 | #define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 | ||
117 | #define BF_PWM_PERIODn_CDIV(v) (((v) << 20) & 0x700000) | ||
118 | #define BF_PWM_PERIODn_CDIV_V(v) ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000) | ||
119 | #define BP_PWM_PERIODn_INACTIVE_STATE 18 | ||
120 | #define BM_PWM_PERIODn_INACTIVE_STATE 0xc0000 | ||
121 | #define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 | ||
122 | #define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 | ||
123 | #define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 | ||
124 | #define BF_PWM_PERIODn_INACTIVE_STATE(v) (((v) << 18) & 0xc0000) | ||
125 | #define BF_PWM_PERIODn_INACTIVE_STATE_V(v) ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000) | ||
126 | #define BP_PWM_PERIODn_ACTIVE_STATE 16 | ||
127 | #define BM_PWM_PERIODn_ACTIVE_STATE 0x30000 | ||
128 | #define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 | ||
129 | #define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 | ||
130 | #define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 | ||
131 | #define BF_PWM_PERIODn_ACTIVE_STATE(v) (((v) << 16) & 0x30000) | ||
132 | #define BF_PWM_PERIODn_ACTIVE_STATE_V(v) ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000) | ||
133 | #define BP_PWM_PERIODn_PERIOD 0 | ||
134 | #define BM_PWM_PERIODn_PERIOD 0xffff | ||
135 | #define BF_PWM_PERIODn_PERIOD(v) (((v) << 0) & 0xffff) | ||
136 | |||
137 | /** | ||
138 | * Register: HW_PWM_VERSION | ||
139 | * Address: 0xb0 | ||
140 | * SCT: no | ||
141 | */ | ||
142 | #define HW_PWM_VERSION (*(volatile unsigned long *)(REGS_PWM_BASE + 0xb0)) | ||
143 | #define BP_PWM_VERSION_MAJOR 24 | ||
144 | #define BM_PWM_VERSION_MAJOR 0xff000000 | ||
145 | #define BF_PWM_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
146 | #define BP_PWM_VERSION_MINOR 16 | ||
147 | #define BM_PWM_VERSION_MINOR 0xff0000 | ||
148 | #define BF_PWM_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
149 | #define BP_PWM_VERSION_STEP 0 | ||
150 | #define BM_PWM_VERSION_STEP 0xffff | ||
151 | #define BF_PWM_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
152 | |||
153 | #endif /* __HEADERGEN__STMP3700__PWM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h new file mode 100644 index 0000000000..ed2bf3270e --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h | |||
@@ -0,0 +1,312 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__RTC__H__ | ||
24 | #define __HEADERGEN__STMP3700__RTC__H__ | ||
25 | |||
26 | #define REGS_RTC_BASE (0x8005c000) | ||
27 | |||
28 | #define REGS_RTC_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_RTC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_RTC_CTRL (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_RTC_CTRL_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_RTC_CTRL_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_RTC_CTRL_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_RTC_CTRL_SFTRST 31 | ||
40 | #define BM_RTC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_RTC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_RTC_CTRL_CLKGATE 30 | ||
43 | #define BM_RTC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_RTC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG 6 | ||
46 | #define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x40 | ||
47 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40) | ||
48 | #define BP_RTC_CTRL_FORCE_UPDATE 5 | ||
49 | #define BM_RTC_CTRL_FORCE_UPDATE 0x20 | ||
50 | #define BF_RTC_CTRL_FORCE_UPDATE(v) (((v) << 5) & 0x20) | ||
51 | #define BP_RTC_CTRL_WATCHDOGEN 4 | ||
52 | #define BM_RTC_CTRL_WATCHDOGEN 0x10 | ||
53 | #define BF_RTC_CTRL_WATCHDOGEN(v) (((v) << 4) & 0x10) | ||
54 | #define BP_RTC_CTRL_ONEMSEC_IRQ 3 | ||
55 | #define BM_RTC_CTRL_ONEMSEC_IRQ 0x8 | ||
56 | #define BF_RTC_CTRL_ONEMSEC_IRQ(v) (((v) << 3) & 0x8) | ||
57 | #define BP_RTC_CTRL_ALARM_IRQ 2 | ||
58 | #define BM_RTC_CTRL_ALARM_IRQ 0x4 | ||
59 | #define BF_RTC_CTRL_ALARM_IRQ(v) (((v) << 2) & 0x4) | ||
60 | #define BP_RTC_CTRL_ONEMSEC_IRQ_EN 1 | ||
61 | #define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x2 | ||
62 | #define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v) (((v) << 1) & 0x2) | ||
63 | #define BP_RTC_CTRL_ALARM_IRQ_EN 0 | ||
64 | #define BM_RTC_CTRL_ALARM_IRQ_EN 0x1 | ||
65 | #define BF_RTC_CTRL_ALARM_IRQ_EN(v) (((v) << 0) & 0x1) | ||
66 | |||
67 | /** | ||
68 | * Register: HW_RTC_STAT | ||
69 | * Address: 0x10 | ||
70 | * SCT: no | ||
71 | */ | ||
72 | #define HW_RTC_STAT (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10)) | ||
73 | #define BP_RTC_STAT_RTC_PRESENT 31 | ||
74 | #define BM_RTC_STAT_RTC_PRESENT 0x80000000 | ||
75 | #define BF_RTC_STAT_RTC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
76 | #define BP_RTC_STAT_ALARM_PRESENT 30 | ||
77 | #define BM_RTC_STAT_ALARM_PRESENT 0x40000000 | ||
78 | #define BF_RTC_STAT_ALARM_PRESENT(v) (((v) << 30) & 0x40000000) | ||
79 | #define BP_RTC_STAT_WATCHDOG_PRESENT 29 | ||
80 | #define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 | ||
81 | #define BF_RTC_STAT_WATCHDOG_PRESENT(v) (((v) << 29) & 0x20000000) | ||
82 | #define BP_RTC_STAT_XTAL32000_PRESENT 28 | ||
83 | #define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 | ||
84 | #define BF_RTC_STAT_XTAL32000_PRESENT(v) (((v) << 28) & 0x10000000) | ||
85 | #define BP_RTC_STAT_XTAL32768_PRESENT 27 | ||
86 | #define BM_RTC_STAT_XTAL32768_PRESENT 0x8000000 | ||
87 | #define BF_RTC_STAT_XTAL32768_PRESENT(v) (((v) << 27) & 0x8000000) | ||
88 | #define BP_RTC_STAT_STALE_REGS 16 | ||
89 | #define BM_RTC_STAT_STALE_REGS 0xff0000 | ||
90 | #define BF_RTC_STAT_STALE_REGS(v) (((v) << 16) & 0xff0000) | ||
91 | #define BP_RTC_STAT_NEW_REGS 8 | ||
92 | #define BM_RTC_STAT_NEW_REGS 0xff00 | ||
93 | #define BF_RTC_STAT_NEW_REGS(v) (((v) << 8) & 0xff00) | ||
94 | |||
95 | /** | ||
96 | * Register: HW_RTC_MILLISECONDS | ||
97 | * Address: 0x20 | ||
98 | * SCT: yes | ||
99 | */ | ||
100 | #define HW_RTC_MILLISECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0)) | ||
101 | #define HW_RTC_MILLISECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4)) | ||
102 | #define HW_RTC_MILLISECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8)) | ||
103 | #define HW_RTC_MILLISECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc)) | ||
104 | #define BP_RTC_MILLISECONDS_COUNT 0 | ||
105 | #define BM_RTC_MILLISECONDS_COUNT 0xffffffff | ||
106 | #define BF_RTC_MILLISECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
107 | |||
108 | /** | ||
109 | * Register: HW_RTC_SECONDS | ||
110 | * Address: 0x30 | ||
111 | * SCT: yes | ||
112 | */ | ||
113 | #define HW_RTC_SECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0)) | ||
114 | #define HW_RTC_SECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4)) | ||
115 | #define HW_RTC_SECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8)) | ||
116 | #define HW_RTC_SECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc)) | ||
117 | #define BP_RTC_SECONDS_COUNT 0 | ||
118 | #define BM_RTC_SECONDS_COUNT 0xffffffff | ||
119 | #define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
120 | |||
121 | /** | ||
122 | * Register: HW_RTC_ALARM | ||
123 | * Address: 0x40 | ||
124 | * SCT: yes | ||
125 | */ | ||
126 | #define HW_RTC_ALARM (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0)) | ||
127 | #define HW_RTC_ALARM_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4)) | ||
128 | #define HW_RTC_ALARM_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8)) | ||
129 | #define HW_RTC_ALARM_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc)) | ||
130 | #define BP_RTC_ALARM_VALUE 0 | ||
131 | #define BM_RTC_ALARM_VALUE 0xffffffff | ||
132 | #define BF_RTC_ALARM_VALUE(v) (((v) << 0) & 0xffffffff) | ||
133 | |||
134 | /** | ||
135 | * Register: HW_RTC_WATCHDOG | ||
136 | * Address: 0x50 | ||
137 | * SCT: yes | ||
138 | */ | ||
139 | #define HW_RTC_WATCHDOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0)) | ||
140 | #define HW_RTC_WATCHDOG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4)) | ||
141 | #define HW_RTC_WATCHDOG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8)) | ||
142 | #define HW_RTC_WATCHDOG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc)) | ||
143 | #define BP_RTC_WATCHDOG_COUNT 0 | ||
144 | #define BM_RTC_WATCHDOG_COUNT 0xffffffff | ||
145 | #define BF_RTC_WATCHDOG_COUNT(v) (((v) << 0) & 0xffffffff) | ||
146 | |||
147 | /** | ||
148 | * Register: HW_RTC_PERSISTENT0 | ||
149 | * Address: 0x60 | ||
150 | * SCT: yes | ||
151 | */ | ||
152 | #define HW_RTC_PERSISTENT0 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0)) | ||
153 | #define HW_RTC_PERSISTENT0_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4)) | ||
154 | #define HW_RTC_PERSISTENT0_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8)) | ||
155 | #define HW_RTC_PERSISTENT0_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc)) | ||
156 | #define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 | ||
157 | #define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xfffc0000 | ||
158 | #define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) (((v) << 18) & 0xfffc0000) | ||
159 | #define BP_RTC_PERSISTENT0_AUTO_RESTART 17 | ||
160 | #define BM_RTC_PERSISTENT0_AUTO_RESTART 0x20000 | ||
161 | #define BF_RTC_PERSISTENT0_AUTO_RESTART(v) (((v) << 17) & 0x20000) | ||
162 | #define BP_RTC_PERSISTENT0_DISABLE_PSWITCH 16 | ||
163 | #define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x10000 | ||
164 | #define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v) (((v) << 16) & 0x10000) | ||
165 | #define BP_RTC_PERSISTENT0_LOWERBIAS 14 | ||
166 | #define BM_RTC_PERSISTENT0_LOWERBIAS 0xc000 | ||
167 | #define BF_RTC_PERSISTENT0_LOWERBIAS(v) (((v) << 14) & 0xc000) | ||
168 | #define BP_RTC_PERSISTENT0_DISABLE_XTALOK 13 | ||
169 | #define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x2000 | ||
170 | #define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v) (((v) << 13) & 0x2000) | ||
171 | #define BP_RTC_PERSISTENT0_MSEC_RES 8 | ||
172 | #define BM_RTC_PERSISTENT0_MSEC_RES 0x1f00 | ||
173 | #define BF_RTC_PERSISTENT0_MSEC_RES(v) (((v) << 8) & 0x1f00) | ||
174 | #define BP_RTC_PERSISTENT0_ALARM_WAKE 7 | ||
175 | #define BM_RTC_PERSISTENT0_ALARM_WAKE 0x80 | ||
176 | #define BF_RTC_PERSISTENT0_ALARM_WAKE(v) (((v) << 7) & 0x80) | ||
177 | #define BP_RTC_PERSISTENT0_XTAL32_FREQ 6 | ||
178 | #define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x40 | ||
179 | #define BF_RTC_PERSISTENT0_XTAL32_FREQ(v) (((v) << 6) & 0x40) | ||
180 | #define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 5 | ||
181 | #define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x20 | ||
182 | #define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v) (((v) << 5) & 0x20) | ||
183 | #define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 4 | ||
184 | #define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x10 | ||
185 | #define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v) (((v) << 4) & 0x10) | ||
186 | #define BP_RTC_PERSISTENT0_LCK_SECS 3 | ||
187 | #define BM_RTC_PERSISTENT0_LCK_SECS 0x8 | ||
188 | #define BF_RTC_PERSISTENT0_LCK_SECS(v) (((v) << 3) & 0x8) | ||
189 | #define BP_RTC_PERSISTENT0_ALARM_EN 2 | ||
190 | #define BM_RTC_PERSISTENT0_ALARM_EN 0x4 | ||
191 | #define BF_RTC_PERSISTENT0_ALARM_EN(v) (((v) << 2) & 0x4) | ||
192 | #define BP_RTC_PERSISTENT0_ALARM_WAKE_EN 1 | ||
193 | #define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x2 | ||
194 | #define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v) (((v) << 1) & 0x2) | ||
195 | #define BP_RTC_PERSISTENT0_CLOCKSOURCE 0 | ||
196 | #define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x1 | ||
197 | #define BF_RTC_PERSISTENT0_CLOCKSOURCE(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_RTC_PERSISTENT1 | ||
201 | * Address: 0x70 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_RTC_PERSISTENT1 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0)) | ||
205 | #define HW_RTC_PERSISTENT1_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4)) | ||
206 | #define HW_RTC_PERSISTENT1_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8)) | ||
207 | #define HW_RTC_PERSISTENT1_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc)) | ||
208 | #define BP_RTC_PERSISTENT1_GENERAL 0 | ||
209 | #define BM_RTC_PERSISTENT1_GENERAL 0xffffffff | ||
210 | #define BV_RTC_PERSISTENT1_GENERAL__SPARE3 0x4000 | ||
211 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_BOOT 0x2000 | ||
212 | #define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 | ||
213 | #define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x800 | ||
214 | #define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x400 | ||
215 | #define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x200 | ||
216 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x100 | ||
217 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x80 | ||
218 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_HI 0x40 | ||
219 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_LO 0x20 | ||
220 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_3 0x10 | ||
221 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_2 0x8 | ||
222 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_1 0x4 | ||
223 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_0 0x2 | ||
224 | #define BV_RTC_PERSISTENT1_GENERAL__ETM_ENABLE 0x1 | ||
225 | #define BF_RTC_PERSISTENT1_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
226 | #define BF_RTC_PERSISTENT1_GENERAL_V(v) ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff) | ||
227 | |||
228 | /** | ||
229 | * Register: HW_RTC_PERSISTENT2 | ||
230 | * Address: 0x80 | ||
231 | * SCT: yes | ||
232 | */ | ||
233 | #define HW_RTC_PERSISTENT2 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0)) | ||
234 | #define HW_RTC_PERSISTENT2_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4)) | ||
235 | #define HW_RTC_PERSISTENT2_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8)) | ||
236 | #define HW_RTC_PERSISTENT2_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc)) | ||
237 | #define BP_RTC_PERSISTENT2_GENERAL 0 | ||
238 | #define BM_RTC_PERSISTENT2_GENERAL 0xffffffff | ||
239 | #define BF_RTC_PERSISTENT2_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
240 | |||
241 | /** | ||
242 | * Register: HW_RTC_PERSISTENT3 | ||
243 | * Address: 0x90 | ||
244 | * SCT: yes | ||
245 | */ | ||
246 | #define HW_RTC_PERSISTENT3 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0)) | ||
247 | #define HW_RTC_PERSISTENT3_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4)) | ||
248 | #define HW_RTC_PERSISTENT3_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8)) | ||
249 | #define HW_RTC_PERSISTENT3_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc)) | ||
250 | #define BP_RTC_PERSISTENT3_GENERAL 0 | ||
251 | #define BM_RTC_PERSISTENT3_GENERAL 0xffffffff | ||
252 | #define BF_RTC_PERSISTENT3_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
253 | |||
254 | /** | ||
255 | * Register: HW_RTC_PERSISTENT4 | ||
256 | * Address: 0xa0 | ||
257 | * SCT: yes | ||
258 | */ | ||
259 | #define HW_RTC_PERSISTENT4 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0)) | ||
260 | #define HW_RTC_PERSISTENT4_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4)) | ||
261 | #define HW_RTC_PERSISTENT4_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8)) | ||
262 | #define HW_RTC_PERSISTENT4_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc)) | ||
263 | #define BP_RTC_PERSISTENT4_GENERAL 0 | ||
264 | #define BM_RTC_PERSISTENT4_GENERAL 0xffffffff | ||
265 | #define BF_RTC_PERSISTENT4_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
266 | |||
267 | /** | ||
268 | * Register: HW_RTC_PERSISTENT5 | ||
269 | * Address: 0xb0 | ||
270 | * SCT: yes | ||
271 | */ | ||
272 | #define HW_RTC_PERSISTENT5 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0)) | ||
273 | #define HW_RTC_PERSISTENT5_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4)) | ||
274 | #define HW_RTC_PERSISTENT5_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8)) | ||
275 | #define HW_RTC_PERSISTENT5_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc)) | ||
276 | #define BP_RTC_PERSISTENT5_GENERAL 0 | ||
277 | #define BM_RTC_PERSISTENT5_GENERAL 0xffffffff | ||
278 | #define BF_RTC_PERSISTENT5_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
279 | |||
280 | /** | ||
281 | * Register: HW_RTC_DEBUG | ||
282 | * Address: 0xc0 | ||
283 | * SCT: yes | ||
284 | */ | ||
285 | #define HW_RTC_DEBUG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0)) | ||
286 | #define HW_RTC_DEBUG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4)) | ||
287 | #define HW_RTC_DEBUG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8)) | ||
288 | #define HW_RTC_DEBUG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc)) | ||
289 | #define BP_RTC_DEBUG_WATCHDOG_RESET_MASK 1 | ||
290 | #define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x2 | ||
291 | #define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2) | ||
292 | #define BP_RTC_DEBUG_WATCHDOG_RESET 0 | ||
293 | #define BM_RTC_DEBUG_WATCHDOG_RESET 0x1 | ||
294 | #define BF_RTC_DEBUG_WATCHDOG_RESET(v) (((v) << 0) & 0x1) | ||
295 | |||
296 | /** | ||
297 | * Register: HW_RTC_VERSION | ||
298 | * Address: 0xd0 | ||
299 | * SCT: no | ||
300 | */ | ||
301 | #define HW_RTC_VERSION (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0)) | ||
302 | #define BP_RTC_VERSION_MAJOR 24 | ||
303 | #define BM_RTC_VERSION_MAJOR 0xff000000 | ||
304 | #define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
305 | #define BP_RTC_VERSION_MINOR 16 | ||
306 | #define BM_RTC_VERSION_MINOR 0xff0000 | ||
307 | #define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
308 | #define BP_RTC_VERSION_STEP 0 | ||
309 | #define BM_RTC_VERSION_STEP 0xffff | ||
310 | #define BF_RTC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
311 | |||
312 | #endif /* __HEADERGEN__STMP3700__RTC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h new file mode 100644 index 0000000000..01faeabc62 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h | |||
@@ -0,0 +1,154 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__SAIF__H__ | ||
24 | #define __HEADERGEN__STMP3700__SAIF__H__ | ||
25 | |||
26 | #define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000) | ||
27 | |||
28 | #define REGS_SAIF_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SAIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SAIF_CTRL(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0)) | ||
36 | #define HW_SAIF_CTRL_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4)) | ||
37 | #define HW_SAIF_CTRL_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8)) | ||
38 | #define HW_SAIF_CTRL_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc)) | ||
39 | #define BP_SAIF_CTRL_SFTRST 31 | ||
40 | #define BM_SAIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_SAIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SAIF_CTRL_CLKGATE 30 | ||
43 | #define BM_SAIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_SAIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 | ||
46 | #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 | ||
47 | #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) (((v) << 27) & 0x38000000) | ||
48 | #define BP_SAIF_CTRL_BITCLK_BASE_RATE 26 | ||
49 | #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x4000000 | ||
50 | #define BF_SAIF_CTRL_BITCLK_BASE_RATE(v) (((v) << 26) & 0x4000000) | ||
51 | #define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN 25 | ||
52 | #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x2000000 | ||
53 | #define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 25) & 0x2000000) | ||
54 | #define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 24 | ||
55 | #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x1000000 | ||
56 | #define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
57 | #define BP_SAIF_CTRL_DMAWAIT_COUNT 16 | ||
58 | #define BM_SAIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
59 | #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
60 | #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 | ||
61 | #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0xc000 | ||
62 | #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) (((v) << 14) & 0xc000) | ||
63 | #define BP_SAIF_CTRL_BIT_ORDER 12 | ||
64 | #define BM_SAIF_CTRL_BIT_ORDER 0x1000 | ||
65 | #define BF_SAIF_CTRL_BIT_ORDER(v) (((v) << 12) & 0x1000) | ||
66 | #define BP_SAIF_CTRL_DELAY 11 | ||
67 | #define BM_SAIF_CTRL_DELAY 0x800 | ||
68 | #define BF_SAIF_CTRL_DELAY(v) (((v) << 11) & 0x800) | ||
69 | #define BP_SAIF_CTRL_JUSTIFY 10 | ||
70 | #define BM_SAIF_CTRL_JUSTIFY 0x400 | ||
71 | #define BF_SAIF_CTRL_JUSTIFY(v) (((v) << 10) & 0x400) | ||
72 | #define BP_SAIF_CTRL_LRCLK_POLARITY 9 | ||
73 | #define BM_SAIF_CTRL_LRCLK_POLARITY 0x200 | ||
74 | #define BF_SAIF_CTRL_LRCLK_POLARITY(v) (((v) << 9) & 0x200) | ||
75 | #define BP_SAIF_CTRL_BITCLK_EDGE 8 | ||
76 | #define BM_SAIF_CTRL_BITCLK_EDGE 0x100 | ||
77 | #define BF_SAIF_CTRL_BITCLK_EDGE(v) (((v) << 8) & 0x100) | ||
78 | #define BP_SAIF_CTRL_WORD_LENGTH 4 | ||
79 | #define BM_SAIF_CTRL_WORD_LENGTH 0xf0 | ||
80 | #define BF_SAIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
81 | #define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE 3 | ||
82 | #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x8 | ||
83 | #define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8) | ||
84 | #define BP_SAIF_CTRL_SLAVE_MODE 2 | ||
85 | #define BM_SAIF_CTRL_SLAVE_MODE 0x4 | ||
86 | #define BF_SAIF_CTRL_SLAVE_MODE(v) (((v) << 2) & 0x4) | ||
87 | #define BP_SAIF_CTRL_READ_MODE 1 | ||
88 | #define BM_SAIF_CTRL_READ_MODE 0x2 | ||
89 | #define BF_SAIF_CTRL_READ_MODE(v) (((v) << 1) & 0x2) | ||
90 | #define BP_SAIF_CTRL_RUN 0 | ||
91 | #define BM_SAIF_CTRL_RUN 0x1 | ||
92 | #define BF_SAIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
93 | |||
94 | /** | ||
95 | * Register: HW_SAIF_STAT | ||
96 | * Address: 0x10 | ||
97 | * SCT: yes | ||
98 | */ | ||
99 | #define HW_SAIF_STAT(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0)) | ||
100 | #define HW_SAIF_STAT_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4)) | ||
101 | #define HW_SAIF_STAT_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8)) | ||
102 | #define HW_SAIF_STAT_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc)) | ||
103 | #define BP_SAIF_STAT_PRESENT 31 | ||
104 | #define BM_SAIF_STAT_PRESENT 0x80000000 | ||
105 | #define BF_SAIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
106 | #define BP_SAIF_STAT_DMA_PREQ 16 | ||
107 | #define BM_SAIF_STAT_DMA_PREQ 0x10000 | ||
108 | #define BF_SAIF_STAT_DMA_PREQ(v) (((v) << 16) & 0x10000) | ||
109 | #define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ 6 | ||
110 | #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x40 | ||
111 | #define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v) (((v) << 6) & 0x40) | ||
112 | #define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ 5 | ||
113 | #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x20 | ||
114 | #define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v) (((v) << 5) & 0x20) | ||
115 | #define BP_SAIF_STAT_FIFO_SERVICE_IRQ 4 | ||
116 | #define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x10 | ||
117 | #define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v) (((v) << 4) & 0x10) | ||
118 | #define BP_SAIF_STAT_BUSY 0 | ||
119 | #define BM_SAIF_STAT_BUSY 0x1 | ||
120 | #define BF_SAIF_STAT_BUSY(v) (((v) << 0) & 0x1) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_SAIF_DATA | ||
124 | * Address: 0x20 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_SAIF_DATA(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0)) | ||
128 | #define HW_SAIF_DATA_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4)) | ||
129 | #define HW_SAIF_DATA_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8)) | ||
130 | #define HW_SAIF_DATA_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc)) | ||
131 | #define BP_SAIF_DATA_PCM_RIGHT 16 | ||
132 | #define BM_SAIF_DATA_PCM_RIGHT 0xffff0000 | ||
133 | #define BF_SAIF_DATA_PCM_RIGHT(v) (((v) << 16) & 0xffff0000) | ||
134 | #define BP_SAIF_DATA_PCM_LEFT 0 | ||
135 | #define BM_SAIF_DATA_PCM_LEFT 0xffff | ||
136 | #define BF_SAIF_DATA_PCM_LEFT(v) (((v) << 0) & 0xffff) | ||
137 | |||
138 | /** | ||
139 | * Register: HW_SAIF_VERSION | ||
140 | * Address: 0x30 | ||
141 | * SCT: no | ||
142 | */ | ||
143 | #define HW_SAIF_VERSION(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30)) | ||
144 | #define BP_SAIF_VERSION_MAJOR 24 | ||
145 | #define BM_SAIF_VERSION_MAJOR 0xff000000 | ||
146 | #define BF_SAIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
147 | #define BP_SAIF_VERSION_MINOR 16 | ||
148 | #define BM_SAIF_VERSION_MINOR 0xff0000 | ||
149 | #define BF_SAIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
150 | #define BP_SAIF_VERSION_STEP 0 | ||
151 | #define BM_SAIF_VERSION_STEP 0xffff | ||
152 | #define BF_SAIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
153 | |||
154 | #endif /* __HEADERGEN__STMP3700__SAIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h new file mode 100644 index 0000000000..4d58761ba9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h | |||
@@ -0,0 +1,181 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__SPDIF__H__ | ||
24 | #define __HEADERGEN__STMP3700__SPDIF__H__ | ||
25 | |||
26 | #define REGS_SPDIF_BASE (0x80054000) | ||
27 | |||
28 | #define REGS_SPDIF_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SPDIF_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SPDIF_CTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0)) | ||
36 | #define HW_SPDIF_CTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4)) | ||
37 | #define HW_SPDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8)) | ||
38 | #define HW_SPDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc)) | ||
39 | #define BP_SPDIF_CTRL_SFTRST 31 | ||
40 | #define BM_SPDIF_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_SPDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SPDIF_CTRL_CLKGATE 30 | ||
43 | #define BM_SPDIF_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_SPDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 | ||
46 | #define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
47 | #define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
48 | #define BP_SPDIF_CTRL_WAIT_END_XFER 5 | ||
49 | #define BM_SPDIF_CTRL_WAIT_END_XFER 0x20 | ||
50 | #define BF_SPDIF_CTRL_WAIT_END_XFER(v) (((v) << 5) & 0x20) | ||
51 | #define BP_SPDIF_CTRL_WORD_LENGTH 4 | ||
52 | #define BM_SPDIF_CTRL_WORD_LENGTH 0x10 | ||
53 | #define BF_SPDIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0x10) | ||
54 | #define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
55 | #define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
56 | #define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
57 | #define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
58 | #define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
59 | #define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
60 | #define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
61 | #define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
62 | #define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
63 | #define BP_SPDIF_CTRL_RUN 0 | ||
64 | #define BM_SPDIF_CTRL_RUN 0x1 | ||
65 | #define BF_SPDIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
66 | |||
67 | /** | ||
68 | * Register: HW_SPDIF_STAT | ||
69 | * Address: 0x10 | ||
70 | * SCT: no | ||
71 | */ | ||
72 | #define HW_SPDIF_STAT (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10)) | ||
73 | #define BP_SPDIF_STAT_PRESENT 31 | ||
74 | #define BM_SPDIF_STAT_PRESENT 0x80000000 | ||
75 | #define BF_SPDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
76 | #define BP_SPDIF_STAT_END_XFER 0 | ||
77 | #define BM_SPDIF_STAT_END_XFER 0x1 | ||
78 | #define BF_SPDIF_STAT_END_XFER(v) (((v) << 0) & 0x1) | ||
79 | |||
80 | /** | ||
81 | * Register: HW_SPDIF_FRAMECTRL | ||
82 | * Address: 0x20 | ||
83 | * SCT: yes | ||
84 | */ | ||
85 | #define HW_SPDIF_FRAMECTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0)) | ||
86 | #define HW_SPDIF_FRAMECTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4)) | ||
87 | #define HW_SPDIF_FRAMECTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8)) | ||
88 | #define HW_SPDIF_FRAMECTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc)) | ||
89 | #define BP_SPDIF_FRAMECTRL_V_CONFIG 17 | ||
90 | #define BM_SPDIF_FRAMECTRL_V_CONFIG 0x20000 | ||
91 | #define BF_SPDIF_FRAMECTRL_V_CONFIG(v) (((v) << 17) & 0x20000) | ||
92 | #define BP_SPDIF_FRAMECTRL_AUTO_MUTE 16 | ||
93 | #define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x10000 | ||
94 | #define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000) | ||
95 | #define BP_SPDIF_FRAMECTRL_USER_DATA 14 | ||
96 | #define BM_SPDIF_FRAMECTRL_USER_DATA 0x4000 | ||
97 | #define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000) | ||
98 | #define BP_SPDIF_FRAMECTRL_V 13 | ||
99 | #define BM_SPDIF_FRAMECTRL_V 0x2000 | ||
100 | #define BF_SPDIF_FRAMECTRL_V(v) (((v) << 13) & 0x2000) | ||
101 | #define BP_SPDIF_FRAMECTRL_L 12 | ||
102 | #define BM_SPDIF_FRAMECTRL_L 0x1000 | ||
103 | #define BF_SPDIF_FRAMECTRL_L(v) (((v) << 12) & 0x1000) | ||
104 | #define BP_SPDIF_FRAMECTRL_CC 4 | ||
105 | #define BM_SPDIF_FRAMECTRL_CC 0x7f0 | ||
106 | #define BF_SPDIF_FRAMECTRL_CC(v) (((v) << 4) & 0x7f0) | ||
107 | #define BP_SPDIF_FRAMECTRL_PRE 3 | ||
108 | #define BM_SPDIF_FRAMECTRL_PRE 0x8 | ||
109 | #define BF_SPDIF_FRAMECTRL_PRE(v) (((v) << 3) & 0x8) | ||
110 | #define BP_SPDIF_FRAMECTRL_COPY 2 | ||
111 | #define BM_SPDIF_FRAMECTRL_COPY 0x4 | ||
112 | #define BF_SPDIF_FRAMECTRL_COPY(v) (((v) << 2) & 0x4) | ||
113 | #define BP_SPDIF_FRAMECTRL_AUDIO 1 | ||
114 | #define BM_SPDIF_FRAMECTRL_AUDIO 0x2 | ||
115 | #define BF_SPDIF_FRAMECTRL_AUDIO(v) (((v) << 1) & 0x2) | ||
116 | #define BP_SPDIF_FRAMECTRL_PRO 0 | ||
117 | #define BM_SPDIF_FRAMECTRL_PRO 0x1 | ||
118 | #define BF_SPDIF_FRAMECTRL_PRO(v) (((v) << 0) & 0x1) | ||
119 | |||
120 | /** | ||
121 | * Register: HW_SPDIF_SRR | ||
122 | * Address: 0x30 | ||
123 | * SCT: yes | ||
124 | */ | ||
125 | #define HW_SPDIF_SRR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0)) | ||
126 | #define HW_SPDIF_SRR_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4)) | ||
127 | #define HW_SPDIF_SRR_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8)) | ||
128 | #define HW_SPDIF_SRR_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc)) | ||
129 | #define BP_SPDIF_SRR_BASEMULT 28 | ||
130 | #define BM_SPDIF_SRR_BASEMULT 0x70000000 | ||
131 | #define BF_SPDIF_SRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
132 | #define BP_SPDIF_SRR_RATE 0 | ||
133 | #define BM_SPDIF_SRR_RATE 0xfffff | ||
134 | #define BF_SPDIF_SRR_RATE(v) (((v) << 0) & 0xfffff) | ||
135 | |||
136 | /** | ||
137 | * Register: HW_SPDIF_DEBUG | ||
138 | * Address: 0x40 | ||
139 | * SCT: no | ||
140 | */ | ||
141 | #define HW_SPDIF_DEBUG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40)) | ||
142 | #define BP_SPDIF_DEBUG_DMA_PREQ 1 | ||
143 | #define BM_SPDIF_DEBUG_DMA_PREQ 0x2 | ||
144 | #define BF_SPDIF_DEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
145 | #define BP_SPDIF_DEBUG_FIFO_STATUS 0 | ||
146 | #define BM_SPDIF_DEBUG_FIFO_STATUS 0x1 | ||
147 | #define BF_SPDIF_DEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_SPDIF_DATA | ||
151 | * Address: 0x50 | ||
152 | * SCT: yes | ||
153 | */ | ||
154 | #define HW_SPDIF_DATA (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0)) | ||
155 | #define HW_SPDIF_DATA_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4)) | ||
156 | #define HW_SPDIF_DATA_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8)) | ||
157 | #define HW_SPDIF_DATA_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc)) | ||
158 | #define BP_SPDIF_DATA_HIGH 16 | ||
159 | #define BM_SPDIF_DATA_HIGH 0xffff0000 | ||
160 | #define BF_SPDIF_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
161 | #define BP_SPDIF_DATA_LOW 0 | ||
162 | #define BM_SPDIF_DATA_LOW 0xffff | ||
163 | #define BF_SPDIF_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_SPDIF_VERSION | ||
167 | * Address: 0x60 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_SPDIF_VERSION (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60)) | ||
171 | #define BP_SPDIF_VERSION_MAJOR 24 | ||
172 | #define BM_SPDIF_VERSION_MAJOR 0xff000000 | ||
173 | #define BF_SPDIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
174 | #define BP_SPDIF_VERSION_MINOR 16 | ||
175 | #define BM_SPDIF_VERSION_MINOR 0xff0000 | ||
176 | #define BF_SPDIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
177 | #define BP_SPDIF_VERSION_STEP 0 | ||
178 | #define BM_SPDIF_VERSION_STEP 0xffff | ||
179 | #define BF_SPDIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
180 | |||
181 | #endif /* __HEADERGEN__STMP3700__SPDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h new file mode 100644 index 0000000000..463cf26cf7 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h | |||
@@ -0,0 +1,558 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__SSP__H__ | ||
24 | #define __HEADERGEN__STMP3700__SSP__H__ | ||
25 | |||
26 | #define REGS_SSP_BASE(i) ((i) == 1 ? 0x80010000 : 0x80034000) | ||
27 | |||
28 | #define REGS_SSP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_SSP_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_SSP_CTRL0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x0)) | ||
36 | #define HW_SSP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x4)) | ||
37 | #define HW_SSP_CTRL0_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x8)) | ||
38 | #define HW_SSP_CTRL0_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0xc)) | ||
39 | #define BP_SSP_CTRL0_SFTRST 31 | ||
40 | #define BM_SSP_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_SSP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_SSP_CTRL0_CLKGATE 30 | ||
43 | #define BM_SSP_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_SSP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_SSP_CTRL0_RUN 29 | ||
46 | #define BM_SSP_CTRL0_RUN 0x20000000 | ||
47 | #define BF_SSP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_SSP_CTRL0_SDIO_IRQ_CHECK 28 | ||
49 | #define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 | ||
50 | #define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_SSP_CTRL0_LOCK_CS 27 | ||
52 | #define BM_SSP_CTRL0_LOCK_CS 0x8000000 | ||
53 | #define BF_SSP_CTRL0_LOCK_CS(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_SSP_CTRL0_IGNORE_CRC 26 | ||
55 | #define BM_SSP_CTRL0_IGNORE_CRC 0x4000000 | ||
56 | #define BF_SSP_CTRL0_IGNORE_CRC(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_SSP_CTRL0_READ 25 | ||
58 | #define BM_SSP_CTRL0_READ 0x2000000 | ||
59 | #define BF_SSP_CTRL0_READ(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_SSP_CTRL0_DATA_XFER 24 | ||
61 | #define BM_SSP_CTRL0_DATA_XFER 0x1000000 | ||
62 | #define BF_SSP_CTRL0_DATA_XFER(v) (((v) << 24) & 0x1000000) | ||
63 | #define BP_SSP_CTRL0_BUS_WIDTH 22 | ||
64 | #define BM_SSP_CTRL0_BUS_WIDTH 0xc00000 | ||
65 | #define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 | ||
66 | #define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 | ||
67 | #define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 | ||
68 | #define BF_SSP_CTRL0_BUS_WIDTH(v) (((v) << 22) & 0xc00000) | ||
69 | #define BF_SSP_CTRL0_BUS_WIDTH_V(v) ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0xc00000) | ||
70 | #define BP_SSP_CTRL0_WAIT_FOR_IRQ 21 | ||
71 | #define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x200000 | ||
72 | #define BF_SSP_CTRL0_WAIT_FOR_IRQ(v) (((v) << 21) & 0x200000) | ||
73 | #define BP_SSP_CTRL0_WAIT_FOR_CMD 20 | ||
74 | #define BM_SSP_CTRL0_WAIT_FOR_CMD 0x100000 | ||
75 | #define BF_SSP_CTRL0_WAIT_FOR_CMD(v) (((v) << 20) & 0x100000) | ||
76 | #define BP_SSP_CTRL0_LONG_RESP 19 | ||
77 | #define BM_SSP_CTRL0_LONG_RESP 0x80000 | ||
78 | #define BF_SSP_CTRL0_LONG_RESP(v) (((v) << 19) & 0x80000) | ||
79 | #define BP_SSP_CTRL0_CHECK_RESP 18 | ||
80 | #define BM_SSP_CTRL0_CHECK_RESP 0x40000 | ||
81 | #define BF_SSP_CTRL0_CHECK_RESP(v) (((v) << 18) & 0x40000) | ||
82 | #define BP_SSP_CTRL0_GET_RESP 17 | ||
83 | #define BM_SSP_CTRL0_GET_RESP 0x20000 | ||
84 | #define BF_SSP_CTRL0_GET_RESP(v) (((v) << 17) & 0x20000) | ||
85 | #define BP_SSP_CTRL0_ENABLE 16 | ||
86 | #define BM_SSP_CTRL0_ENABLE 0x10000 | ||
87 | #define BF_SSP_CTRL0_ENABLE(v) (((v) << 16) & 0x10000) | ||
88 | #define BP_SSP_CTRL0_XFER_COUNT 0 | ||
89 | #define BM_SSP_CTRL0_XFER_COUNT 0xffff | ||
90 | #define BF_SSP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
91 | |||
92 | /** | ||
93 | * Register: HW_SSP_CMD0 | ||
94 | * Address: 0x10 | ||
95 | * SCT: yes | ||
96 | */ | ||
97 | #define HW_SSP_CMD0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x0)) | ||
98 | #define HW_SSP_CMD0_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x4)) | ||
99 | #define HW_SSP_CMD0_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x8)) | ||
100 | #define HW_SSP_CMD0_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0xc)) | ||
101 | #define BP_SSP_CMD0_APPEND_8CYC 20 | ||
102 | #define BM_SSP_CMD0_APPEND_8CYC 0x100000 | ||
103 | #define BF_SSP_CMD0_APPEND_8CYC(v) (((v) << 20) & 0x100000) | ||
104 | #define BP_SSP_CMD0_BLOCK_SIZE 16 | ||
105 | #define BM_SSP_CMD0_BLOCK_SIZE 0xf0000 | ||
106 | #define BF_SSP_CMD0_BLOCK_SIZE(v) (((v) << 16) & 0xf0000) | ||
107 | #define BP_SSP_CMD0_BLOCK_COUNT 8 | ||
108 | #define BM_SSP_CMD0_BLOCK_COUNT 0xff00 | ||
109 | #define BF_SSP_CMD0_BLOCK_COUNT(v) (((v) << 8) & 0xff00) | ||
110 | #define BP_SSP_CMD0_CMD 0 | ||
111 | #define BM_SSP_CMD0_CMD 0xff | ||
112 | #define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x0 | ||
113 | #define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x1 | ||
114 | #define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x2 | ||
115 | #define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x3 | ||
116 | #define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x4 | ||
117 | #define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x5 | ||
118 | #define BV_SSP_CMD0_CMD__MMC_SWITCH 0x6 | ||
119 | #define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x7 | ||
120 | #define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x8 | ||
121 | #define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x9 | ||
122 | #define BV_SSP_CMD0_CMD__MMC_SEND_CID 0xa | ||
123 | #define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0xb | ||
124 | #define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0xc | ||
125 | #define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0xd | ||
126 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0xe | ||
127 | #define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0xf | ||
128 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 | ||
129 | #define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 | ||
130 | #define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 | ||
131 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 | ||
132 | #define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 | ||
133 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 | ||
134 | #define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 | ||
135 | #define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 | ||
136 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1a | ||
137 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1b | ||
138 | #define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1c | ||
139 | #define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1d | ||
140 | #define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1e | ||
141 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 | ||
142 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 | ||
143 | #define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 | ||
144 | #define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 | ||
145 | #define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 | ||
146 | #define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2a | ||
147 | #define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 | ||
148 | #define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 | ||
149 | #define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x0 | ||
150 | #define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x2 | ||
151 | #define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x3 | ||
152 | #define BV_SSP_CMD0_CMD__SD_SET_DSR 0x4 | ||
153 | #define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x5 | ||
154 | #define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x7 | ||
155 | #define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x9 | ||
156 | #define BV_SSP_CMD0_CMD__SD_SEND_CID 0xa | ||
157 | #define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0xc | ||
158 | #define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0xd | ||
159 | #define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0xf | ||
160 | #define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 | ||
161 | #define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 | ||
162 | #define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 | ||
163 | #define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 | ||
164 | #define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 | ||
165 | #define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1b | ||
166 | #define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1c | ||
167 | #define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1d | ||
168 | #define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1e | ||
169 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 | ||
170 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 | ||
171 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 | ||
172 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 | ||
173 | #define BV_SSP_CMD0_CMD__SD_ERASE 0x26 | ||
174 | #define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2a | ||
175 | #define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 | ||
176 | #define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 | ||
177 | #define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 | ||
178 | #define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 | ||
179 | #define BF_SSP_CMD0_CMD(v) (((v) << 0) & 0xff) | ||
180 | #define BF_SSP_CMD0_CMD_V(v) ((BV_SSP_CMD0_CMD__##v << 0) & 0xff) | ||
181 | |||
182 | /** | ||
183 | * Register: HW_SSP_CMD1 | ||
184 | * Address: 0x20 | ||
185 | * SCT: no | ||
186 | */ | ||
187 | #define HW_SSP_CMD1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x20)) | ||
188 | #define BP_SSP_CMD1_CMD_ARG 0 | ||
189 | #define BM_SSP_CMD1_CMD_ARG 0xffffffff | ||
190 | #define BF_SSP_CMD1_CMD_ARG(v) (((v) << 0) & 0xffffffff) | ||
191 | |||
192 | /** | ||
193 | * Register: HW_SSP_COMPREF | ||
194 | * Address: 0x30 | ||
195 | * SCT: no | ||
196 | */ | ||
197 | #define HW_SSP_COMPREF(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x30)) | ||
198 | #define BP_SSP_COMPREF_REFERENCE 0 | ||
199 | #define BM_SSP_COMPREF_REFERENCE 0xffffffff | ||
200 | #define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff) | ||
201 | |||
202 | /** | ||
203 | * Register: HW_SSP_COMPMASK | ||
204 | * Address: 0x40 | ||
205 | * SCT: no | ||
206 | */ | ||
207 | #define HW_SSP_COMPMASK(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x40)) | ||
208 | #define BP_SSP_COMPMASK_MASK 0 | ||
209 | #define BM_SSP_COMPMASK_MASK 0xffffffff | ||
210 | #define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff) | ||
211 | |||
212 | /** | ||
213 | * Register: HW_SSP_TIMING | ||
214 | * Address: 0x50 | ||
215 | * SCT: no | ||
216 | */ | ||
217 | #define HW_SSP_TIMING(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x50)) | ||
218 | #define BP_SSP_TIMING_TIMEOUT 16 | ||
219 | #define BM_SSP_TIMING_TIMEOUT 0xffff0000 | ||
220 | #define BF_SSP_TIMING_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
221 | #define BP_SSP_TIMING_CLOCK_DIVIDE 8 | ||
222 | #define BM_SSP_TIMING_CLOCK_DIVIDE 0xff00 | ||
223 | #define BF_SSP_TIMING_CLOCK_DIVIDE(v) (((v) << 8) & 0xff00) | ||
224 | #define BP_SSP_TIMING_CLOCK_RATE 0 | ||
225 | #define BM_SSP_TIMING_CLOCK_RATE 0xff | ||
226 | #define BF_SSP_TIMING_CLOCK_RATE(v) (((v) << 0) & 0xff) | ||
227 | |||
228 | /** | ||
229 | * Register: HW_SSP_CTRL1 | ||
230 | * Address: 0x60 | ||
231 | * SCT: yes | ||
232 | */ | ||
233 | #define HW_SSP_CTRL1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x0)) | ||
234 | #define HW_SSP_CTRL1_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x4)) | ||
235 | #define HW_SSP_CTRL1_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x8)) | ||
236 | #define HW_SSP_CTRL1_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0xc)) | ||
237 | #define BP_SSP_CTRL1_SDIO_IRQ 31 | ||
238 | #define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 | ||
239 | #define BF_SSP_CTRL1_SDIO_IRQ(v) (((v) << 31) & 0x80000000) | ||
240 | #define BP_SSP_CTRL1_SDIO_IRQ_EN 30 | ||
241 | #define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 | ||
242 | #define BF_SSP_CTRL1_SDIO_IRQ_EN(v) (((v) << 30) & 0x40000000) | ||
243 | #define BP_SSP_CTRL1_RESP_ERR_IRQ 29 | ||
244 | #define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 | ||
245 | #define BF_SSP_CTRL1_RESP_ERR_IRQ(v) (((v) << 29) & 0x20000000) | ||
246 | #define BP_SSP_CTRL1_RESP_ERR_IRQ_EN 28 | ||
247 | #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 | ||
248 | #define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
249 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ 27 | ||
250 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x8000000 | ||
251 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v) (((v) << 27) & 0x8000000) | ||
252 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 26 | ||
253 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x4000000 | ||
254 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v) (((v) << 26) & 0x4000000) | ||
255 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ 25 | ||
256 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x2000000 | ||
257 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v) (((v) << 25) & 0x2000000) | ||
258 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 24 | ||
259 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x1000000 | ||
260 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
261 | #define BP_SSP_CTRL1_DATA_CRC_IRQ 23 | ||
262 | #define BM_SSP_CTRL1_DATA_CRC_IRQ 0x800000 | ||
263 | #define BF_SSP_CTRL1_DATA_CRC_IRQ(v) (((v) << 23) & 0x800000) | ||
264 | #define BP_SSP_CTRL1_DATA_CRC_IRQ_EN 22 | ||
265 | #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x400000 | ||
266 | #define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
267 | #define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ 21 | ||
268 | #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x200000 | ||
269 | #define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v) (((v) << 21) & 0x200000) | ||
270 | #define BP_SSP_CTRL1_FIFO_UNDERRUN_EN 20 | ||
271 | #define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x100000 | ||
272 | #define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v) (((v) << 20) & 0x100000) | ||
273 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ 19 | ||
274 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x80000 | ||
275 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v) (((v) << 19) & 0x80000) | ||
276 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 18 | ||
277 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x40000 | ||
278 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
279 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ 17 | ||
280 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x20000 | ||
281 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v) (((v) << 17) & 0x20000) | ||
282 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 16 | ||
283 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x10000 | ||
284 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
285 | #define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ 15 | ||
286 | #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x8000 | ||
287 | #define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v) (((v) << 15) & 0x8000) | ||
288 | #define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 14 | ||
289 | #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x4000 | ||
290 | #define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
291 | #define BP_SSP_CTRL1_DMA_ENABLE 13 | ||
292 | #define BM_SSP_CTRL1_DMA_ENABLE 0x2000 | ||
293 | #define BF_SSP_CTRL1_DMA_ENABLE(v) (((v) << 13) & 0x2000) | ||
294 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_EN 12 | ||
295 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x1000 | ||
296 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v) (((v) << 12) & 0x1000) | ||
297 | #define BP_SSP_CTRL1_SLAVE_OUT_DISABLE 11 | ||
298 | #define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x800 | ||
299 | #define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v) (((v) << 11) & 0x800) | ||
300 | #define BP_SSP_CTRL1_PHASE 10 | ||
301 | #define BM_SSP_CTRL1_PHASE 0x400 | ||
302 | #define BF_SSP_CTRL1_PHASE(v) (((v) << 10) & 0x400) | ||
303 | #define BP_SSP_CTRL1_POLARITY 9 | ||
304 | #define BM_SSP_CTRL1_POLARITY 0x200 | ||
305 | #define BF_SSP_CTRL1_POLARITY(v) (((v) << 9) & 0x200) | ||
306 | #define BP_SSP_CTRL1_SLAVE_MODE 8 | ||
307 | #define BM_SSP_CTRL1_SLAVE_MODE 0x100 | ||
308 | #define BF_SSP_CTRL1_SLAVE_MODE(v) (((v) << 8) & 0x100) | ||
309 | #define BP_SSP_CTRL1_WORD_LENGTH 4 | ||
310 | #define BM_SSP_CTRL1_WORD_LENGTH 0xf0 | ||
311 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 | ||
312 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 | ||
313 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 | ||
314 | #define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 | ||
315 | #define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 | ||
316 | #define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xf | ||
317 | #define BF_SSP_CTRL1_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
318 | #define BF_SSP_CTRL1_WORD_LENGTH_V(v) ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0) | ||
319 | #define BP_SSP_CTRL1_SSP_MODE 0 | ||
320 | #define BM_SSP_CTRL1_SSP_MODE 0xf | ||
321 | #define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 | ||
322 | #define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 | ||
323 | #define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 | ||
324 | #define BV_SSP_CTRL1_SSP_MODE__MS 0x4 | ||
325 | #define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7 | ||
326 | #define BF_SSP_CTRL1_SSP_MODE(v) (((v) << 0) & 0xf) | ||
327 | #define BF_SSP_CTRL1_SSP_MODE_V(v) ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf) | ||
328 | |||
329 | /** | ||
330 | * Register: HW_SSP_DATA | ||
331 | * Address: 0x70 | ||
332 | * SCT: no | ||
333 | */ | ||
334 | #define HW_SSP_DATA(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x70)) | ||
335 | #define BP_SSP_DATA_DATA 0 | ||
336 | #define BM_SSP_DATA_DATA 0xffffffff | ||
337 | #define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
338 | |||
339 | /** | ||
340 | * Register: HW_SSP_SDRESP0 | ||
341 | * Address: 0x80 | ||
342 | * SCT: no | ||
343 | */ | ||
344 | #define HW_SSP_SDRESP0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x80)) | ||
345 | #define BP_SSP_SDRESP0_RESP0 0 | ||
346 | #define BM_SSP_SDRESP0_RESP0 0xffffffff | ||
347 | #define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff) | ||
348 | |||
349 | /** | ||
350 | * Register: HW_SSP_SDRESP1 | ||
351 | * Address: 0x90 | ||
352 | * SCT: no | ||
353 | */ | ||
354 | #define HW_SSP_SDRESP1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x90)) | ||
355 | #define BP_SSP_SDRESP1_RESP1 0 | ||
356 | #define BM_SSP_SDRESP1_RESP1 0xffffffff | ||
357 | #define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff) | ||
358 | |||
359 | /** | ||
360 | * Register: HW_SSP_SDRESP2 | ||
361 | * Address: 0xa0 | ||
362 | * SCT: no | ||
363 | */ | ||
364 | #define HW_SSP_SDRESP2(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xa0)) | ||
365 | #define BP_SSP_SDRESP2_RESP2 0 | ||
366 | #define BM_SSP_SDRESP2_RESP2 0xffffffff | ||
367 | #define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff) | ||
368 | |||
369 | /** | ||
370 | * Register: HW_SSP_SDRESP3 | ||
371 | * Address: 0xb0 | ||
372 | * SCT: no | ||
373 | */ | ||
374 | #define HW_SSP_SDRESP3(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xb0)) | ||
375 | #define BP_SSP_SDRESP3_RESP3 0 | ||
376 | #define BM_SSP_SDRESP3_RESP3 0xffffffff | ||
377 | #define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff) | ||
378 | |||
379 | /** | ||
380 | * Register: HW_SSP_STATUS | ||
381 | * Address: 0xc0 | ||
382 | * SCT: no | ||
383 | */ | ||
384 | #define HW_SSP_STATUS(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xc0)) | ||
385 | #define BP_SSP_STATUS_PRESENT 31 | ||
386 | #define BM_SSP_STATUS_PRESENT 0x80000000 | ||
387 | #define BF_SSP_STATUS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
388 | #define BP_SSP_STATUS_MS_PRESENT 30 | ||
389 | #define BM_SSP_STATUS_MS_PRESENT 0x40000000 | ||
390 | #define BF_SSP_STATUS_MS_PRESENT(v) (((v) << 30) & 0x40000000) | ||
391 | #define BP_SSP_STATUS_SD_PRESENT 29 | ||
392 | #define BM_SSP_STATUS_SD_PRESENT 0x20000000 | ||
393 | #define BF_SSP_STATUS_SD_PRESENT(v) (((v) << 29) & 0x20000000) | ||
394 | #define BP_SSP_STATUS_CARD_DETECT 28 | ||
395 | #define BM_SSP_STATUS_CARD_DETECT 0x10000000 | ||
396 | #define BF_SSP_STATUS_CARD_DETECT(v) (((v) << 28) & 0x10000000) | ||
397 | #define BP_SSP_STATUS_DMASENSE 21 | ||
398 | #define BM_SSP_STATUS_DMASENSE 0x200000 | ||
399 | #define BF_SSP_STATUS_DMASENSE(v) (((v) << 21) & 0x200000) | ||
400 | #define BP_SSP_STATUS_DMATERM 20 | ||
401 | #define BM_SSP_STATUS_DMATERM 0x100000 | ||
402 | #define BF_SSP_STATUS_DMATERM(v) (((v) << 20) & 0x100000) | ||
403 | #define BP_SSP_STATUS_DMAREQ 19 | ||
404 | #define BM_SSP_STATUS_DMAREQ 0x80000 | ||
405 | #define BF_SSP_STATUS_DMAREQ(v) (((v) << 19) & 0x80000) | ||
406 | #define BP_SSP_STATUS_DMAEND 18 | ||
407 | #define BM_SSP_STATUS_DMAEND 0x40000 | ||
408 | #define BF_SSP_STATUS_DMAEND(v) (((v) << 18) & 0x40000) | ||
409 | #define BP_SSP_STATUS_SDIO_IRQ 17 | ||
410 | #define BM_SSP_STATUS_SDIO_IRQ 0x20000 | ||
411 | #define BF_SSP_STATUS_SDIO_IRQ(v) (((v) << 17) & 0x20000) | ||
412 | #define BP_SSP_STATUS_RESP_CRC_ERR 16 | ||
413 | #define BM_SSP_STATUS_RESP_CRC_ERR 0x10000 | ||
414 | #define BF_SSP_STATUS_RESP_CRC_ERR(v) (((v) << 16) & 0x10000) | ||
415 | #define BP_SSP_STATUS_RESP_ERR 15 | ||
416 | #define BM_SSP_STATUS_RESP_ERR 0x8000 | ||
417 | #define BF_SSP_STATUS_RESP_ERR(v) (((v) << 15) & 0x8000) | ||
418 | #define BP_SSP_STATUS_RESP_TIMEOUT 14 | ||
419 | #define BM_SSP_STATUS_RESP_TIMEOUT 0x4000 | ||
420 | #define BF_SSP_STATUS_RESP_TIMEOUT(v) (((v) << 14) & 0x4000) | ||
421 | #define BP_SSP_STATUS_DATA_CRC_ERR 13 | ||
422 | #define BM_SSP_STATUS_DATA_CRC_ERR 0x2000 | ||
423 | #define BF_SSP_STATUS_DATA_CRC_ERR(v) (((v) << 13) & 0x2000) | ||
424 | #define BP_SSP_STATUS_TIMEOUT 12 | ||
425 | #define BM_SSP_STATUS_TIMEOUT 0x1000 | ||
426 | #define BF_SSP_STATUS_TIMEOUT(v) (((v) << 12) & 0x1000) | ||
427 | #define BP_SSP_STATUS_RECV_TIMEOUT_STAT 11 | ||
428 | #define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x800 | ||
429 | #define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v) (((v) << 11) & 0x800) | ||
430 | #define BP_SSP_STATUS_CEATA_CCS_ERR 10 | ||
431 | #define BM_SSP_STATUS_CEATA_CCS_ERR 0x400 | ||
432 | #define BF_SSP_STATUS_CEATA_CCS_ERR(v) (((v) << 10) & 0x400) | ||
433 | #define BP_SSP_STATUS_FIFO_OVRFLW 9 | ||
434 | #define BM_SSP_STATUS_FIFO_OVRFLW 0x200 | ||
435 | #define BF_SSP_STATUS_FIFO_OVRFLW(v) (((v) << 9) & 0x200) | ||
436 | #define BP_SSP_STATUS_FIFO_FULL 8 | ||
437 | #define BM_SSP_STATUS_FIFO_FULL 0x100 | ||
438 | #define BF_SSP_STATUS_FIFO_FULL(v) (((v) << 8) & 0x100) | ||
439 | #define BP_SSP_STATUS_FIFO_EMPTY 5 | ||
440 | #define BM_SSP_STATUS_FIFO_EMPTY 0x20 | ||
441 | #define BF_SSP_STATUS_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
442 | #define BP_SSP_STATUS_FIFO_UNDRFLW 4 | ||
443 | #define BM_SSP_STATUS_FIFO_UNDRFLW 0x10 | ||
444 | #define BF_SSP_STATUS_FIFO_UNDRFLW(v) (((v) << 4) & 0x10) | ||
445 | #define BP_SSP_STATUS_CMD_BUSY 3 | ||
446 | #define BM_SSP_STATUS_CMD_BUSY 0x8 | ||
447 | #define BF_SSP_STATUS_CMD_BUSY(v) (((v) << 3) & 0x8) | ||
448 | #define BP_SSP_STATUS_DATA_BUSY 2 | ||
449 | #define BM_SSP_STATUS_DATA_BUSY 0x4 | ||
450 | #define BF_SSP_STATUS_DATA_BUSY(v) (((v) << 2) & 0x4) | ||
451 | #define BP_SSP_STATUS_BUSY 0 | ||
452 | #define BM_SSP_STATUS_BUSY 0x1 | ||
453 | #define BF_SSP_STATUS_BUSY(v) (((v) << 0) & 0x1) | ||
454 | |||
455 | /** | ||
456 | * Register: HW_SSP_DEBUG | ||
457 | * Address: 0x100 | ||
458 | * SCT: no | ||
459 | */ | ||
460 | #define HW_SSP_DEBUG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x100)) | ||
461 | #define BP_SSP_DEBUG_DATACRC_ERR 28 | ||
462 | #define BM_SSP_DEBUG_DATACRC_ERR 0xf0000000 | ||
463 | #define BF_SSP_DEBUG_DATACRC_ERR(v) (((v) << 28) & 0xf0000000) | ||
464 | #define BP_SSP_DEBUG_DATA_STALL 27 | ||
465 | #define BM_SSP_DEBUG_DATA_STALL 0x8000000 | ||
466 | #define BF_SSP_DEBUG_DATA_STALL(v) (((v) << 27) & 0x8000000) | ||
467 | #define BP_SSP_DEBUG_DAT_SM 24 | ||
468 | #define BM_SSP_DEBUG_DAT_SM 0x7000000 | ||
469 | #define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 | ||
470 | #define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 | ||
471 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 | ||
472 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 | ||
473 | #define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 | ||
474 | #define BF_SSP_DEBUG_DAT_SM(v) (((v) << 24) & 0x7000000) | ||
475 | #define BF_SSP_DEBUG_DAT_SM_V(v) ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000) | ||
476 | #define BP_SSP_DEBUG_MSTK_SM 20 | ||
477 | #define BM_SSP_DEBUG_MSTK_SM 0xf00000 | ||
478 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 | ||
479 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 | ||
480 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 | ||
481 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 | ||
482 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 | ||
483 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 | ||
484 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 | ||
485 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 | ||
486 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 | ||
487 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 | ||
488 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xa | ||
489 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xb | ||
490 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xc | ||
491 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xd | ||
492 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xe | ||
493 | #define BF_SSP_DEBUG_MSTK_SM(v) (((v) << 20) & 0xf00000) | ||
494 | #define BF_SSP_DEBUG_MSTK_SM_V(v) ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000) | ||
495 | #define BP_SSP_DEBUG_CMD_OE 19 | ||
496 | #define BM_SSP_DEBUG_CMD_OE 0x80000 | ||
497 | #define BF_SSP_DEBUG_CMD_OE(v) (((v) << 19) & 0x80000) | ||
498 | #define BP_SSP_DEBUG_DMA_SM 16 | ||
499 | #define BM_SSP_DEBUG_DMA_SM 0x70000 | ||
500 | #define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 | ||
501 | #define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 | ||
502 | #define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 | ||
503 | #define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 | ||
504 | #define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 | ||
505 | #define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 | ||
506 | #define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 | ||
507 | #define BF_SSP_DEBUG_DMA_SM(v) (((v) << 16) & 0x70000) | ||
508 | #define BF_SSP_DEBUG_DMA_SM_V(v) ((BV_SSP_DEBUG_DMA_SM__##v << 16) & 0x70000) | ||
509 | #define BP_SSP_DEBUG_MMC_SM 12 | ||
510 | #define BM_SSP_DEBUG_MMC_SM 0xf000 | ||
511 | #define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 | ||
512 | #define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 | ||
513 | #define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 | ||
514 | #define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 | ||
515 | #define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 | ||
516 | #define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 | ||
517 | #define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 | ||
518 | #define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 | ||
519 | #define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 | ||
520 | #define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 | ||
521 | #define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xa | ||
522 | #define BF_SSP_DEBUG_MMC_SM(v) (((v) << 12) & 0xf000) | ||
523 | #define BF_SSP_DEBUG_MMC_SM_V(v) ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0xf000) | ||
524 | #define BP_SSP_DEBUG_CMD_SM 10 | ||
525 | #define BM_SSP_DEBUG_CMD_SM 0xc00 | ||
526 | #define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 | ||
527 | #define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 | ||
528 | #define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 | ||
529 | #define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 | ||
530 | #define BF_SSP_DEBUG_CMD_SM(v) (((v) << 10) & 0xc00) | ||
531 | #define BF_SSP_DEBUG_CMD_SM_V(v) ((BV_SSP_DEBUG_CMD_SM__##v << 10) & 0xc00) | ||
532 | #define BP_SSP_DEBUG_SSP_CMD 9 | ||
533 | #define BM_SSP_DEBUG_SSP_CMD 0x200 | ||
534 | #define BF_SSP_DEBUG_SSP_CMD(v) (((v) << 9) & 0x200) | ||
535 | #define BP_SSP_DEBUG_SSP_RESP 8 | ||
536 | #define BM_SSP_DEBUG_SSP_RESP 0x100 | ||
537 | #define BF_SSP_DEBUG_SSP_RESP(v) (((v) << 8) & 0x100) | ||
538 | #define BP_SSP_DEBUG_SSP_RXD 0 | ||
539 | #define BM_SSP_DEBUG_SSP_RXD 0xff | ||
540 | #define BF_SSP_DEBUG_SSP_RXD(v) (((v) << 0) & 0xff) | ||
541 | |||
542 | /** | ||
543 | * Register: HW_SSP_VERSION | ||
544 | * Address: 0x110 | ||
545 | * SCT: no | ||
546 | */ | ||
547 | #define HW_SSP_VERSION(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x110)) | ||
548 | #define BP_SSP_VERSION_MAJOR 24 | ||
549 | #define BM_SSP_VERSION_MAJOR 0xff000000 | ||
550 | #define BF_SSP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
551 | #define BP_SSP_VERSION_MINOR 16 | ||
552 | #define BM_SSP_VERSION_MINOR 0xff0000 | ||
553 | #define BF_SSP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
554 | #define BP_SSP_VERSION_STEP 0 | ||
555 | #define BM_SSP_VERSION_STEP 0xffff | ||
556 | #define BF_SSP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
557 | |||
558 | #endif /* __HEADERGEN__STMP3700__SSP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h new file mode 100644 index 0000000000..a741fc6856 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h | |||
@@ -0,0 +1,283 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__TIMROT__H__ | ||
24 | #define __HEADERGEN__STMP3700__TIMROT__H__ | ||
25 | |||
26 | #define REGS_TIMROT_BASE (0x80068000) | ||
27 | |||
28 | #define REGS_TIMROT_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_TIMROT_ROTCTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_TIMROT_ROTCTRL (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0)) | ||
36 | #define HW_TIMROT_ROTCTRL_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4)) | ||
37 | #define HW_TIMROT_ROTCTRL_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8)) | ||
38 | #define HW_TIMROT_ROTCTRL_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc)) | ||
39 | #define BP_TIMROT_ROTCTRL_SFTRST 31 | ||
40 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | ||
41 | #define BF_TIMROT_ROTCTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_TIMROT_ROTCTRL_CLKGATE 30 | ||
43 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | ||
44 | #define BF_TIMROT_ROTCTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_TIMROT_ROTCTRL_ROTARY_PRESENT 29 | ||
46 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | ||
47 | #define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_TIMROT_ROTCTRL_TIM3_PRESENT 28 | ||
49 | #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 | ||
50 | #define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_TIMROT_ROTCTRL_TIM2_PRESENT 27 | ||
52 | #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x8000000 | ||
53 | #define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_TIMROT_ROTCTRL_TIM1_PRESENT 26 | ||
55 | #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x4000000 | ||
56 | #define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_TIMROT_ROTCTRL_TIM0_PRESENT 25 | ||
58 | #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x2000000 | ||
59 | #define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_TIMROT_ROTCTRL_STATE 22 | ||
61 | #define BM_TIMROT_ROTCTRL_STATE 0x1c00000 | ||
62 | #define BF_TIMROT_ROTCTRL_STATE(v) (((v) << 22) & 0x1c00000) | ||
63 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | ||
64 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x3f0000 | ||
65 | #define BF_TIMROT_ROTCTRL_DIVIDER(v) (((v) << 16) & 0x3f0000) | ||
66 | #define BP_TIMROT_ROTCTRL_RELATIVE 12 | ||
67 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x1000 | ||
68 | #define BF_TIMROT_ROTCTRL_RELATIVE(v) (((v) << 12) & 0x1000) | ||
69 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | ||
70 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0xc00 | ||
71 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 | ||
72 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 | ||
73 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 | ||
74 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 | ||
75 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) (((v) << 10) & 0xc00) | ||
76 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v) ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00) | ||
77 | #define BP_TIMROT_ROTCTRL_POLARITY_B 9 | ||
78 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x200 | ||
79 | #define BF_TIMROT_ROTCTRL_POLARITY_B(v) (((v) << 9) & 0x200) | ||
80 | #define BP_TIMROT_ROTCTRL_POLARITY_A 8 | ||
81 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x100 | ||
82 | #define BF_TIMROT_ROTCTRL_POLARITY_A(v) (((v) << 8) & 0x100) | ||
83 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
84 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x70 | ||
85 | #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 | ||
86 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 | ||
87 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 | ||
88 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 | ||
89 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 | ||
90 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 | ||
91 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 | ||
92 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 | ||
93 | #define BF_TIMROT_ROTCTRL_SELECT_B(v) (((v) << 4) & 0x70) | ||
94 | #define BF_TIMROT_ROTCTRL_SELECT_B_V(v) ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70) | ||
95 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
96 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x7 | ||
97 | #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 | ||
98 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 | ||
99 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 | ||
100 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 | ||
101 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 | ||
102 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 | ||
103 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 | ||
104 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 | ||
105 | #define BF_TIMROT_ROTCTRL_SELECT_A(v) (((v) << 0) & 0x7) | ||
106 | #define BF_TIMROT_ROTCTRL_SELECT_A_V(v) ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7) | ||
107 | |||
108 | /** | ||
109 | * Register: HW_TIMROT_ROTCOUNT | ||
110 | * Address: 0x10 | ||
111 | * SCT: no | ||
112 | */ | ||
113 | #define HW_TIMROT_ROTCOUNT (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10)) | ||
114 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 | ||
115 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0xffff | ||
116 | #define BF_TIMROT_ROTCOUNT_UPDOWN(v) (((v) << 0) & 0xffff) | ||
117 | |||
118 | /** | ||
119 | * Register: HW_TIMROT_TIMCTRLn | ||
120 | * Address: 0x20+n*0x20 | ||
121 | * SCT: yes | ||
122 | */ | ||
123 | #define HW_TIMROT_TIMCTRLn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0)) | ||
124 | #define HW_TIMROT_TIMCTRLn_SET(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4)) | ||
125 | #define HW_TIMROT_TIMCTRLn_CLR(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8)) | ||
126 | #define HW_TIMROT_TIMCTRLn_TOG(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc)) | ||
127 | #define BP_TIMROT_TIMCTRLn_IRQ 15 | ||
128 | #define BM_TIMROT_TIMCTRLn_IRQ 0x8000 | ||
129 | #define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & 0x8000) | ||
130 | #define BP_TIMROT_TIMCTRLn_IRQ_EN 14 | ||
131 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x4000 | ||
132 | #define BF_TIMROT_TIMCTRLn_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
133 | #define BP_TIMROT_TIMCTRLn_POLARITY 8 | ||
134 | #define BM_TIMROT_TIMCTRLn_POLARITY 0x100 | ||
135 | #define BF_TIMROT_TIMCTRLn_POLARITY(v) (((v) << 8) & 0x100) | ||
136 | #define BP_TIMROT_TIMCTRLn_UPDATE 7 | ||
137 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x80 | ||
138 | #define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & 0x80) | ||
139 | #define BP_TIMROT_TIMCTRLn_RELOAD 6 | ||
140 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x40 | ||
141 | #define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & 0x40) | ||
142 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 | ||
143 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x30 | ||
144 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 | ||
145 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 | ||
146 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 | ||
147 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 | ||
148 | #define BF_TIMROT_TIMCTRLn_PRESCALE(v) (((v) << 4) & 0x30) | ||
149 | #define BF_TIMROT_TIMCTRLn_PRESCALE_V(v) ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30) | ||
150 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
151 | #define BM_TIMROT_TIMCTRLn_SELECT 0xf | ||
152 | #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 | ||
153 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 | ||
154 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 | ||
155 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 | ||
156 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 | ||
157 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 | ||
158 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 | ||
159 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 | ||
160 | #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
161 | #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 | ||
162 | #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xa | ||
163 | #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xb | ||
164 | #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xc | ||
165 | #define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & 0xf) | ||
166 | #define BF_TIMROT_TIMCTRLn_SELECT_V(v) ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf) | ||
167 | |||
168 | /** | ||
169 | * Register: HW_TIMROT_TIMCOUNTn | ||
170 | * Address: 0x30+n*0x20 | ||
171 | * SCT: no | ||
172 | */ | ||
173 | #define HW_TIMROT_TIMCOUNTn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20)) | ||
174 | #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 | ||
175 | #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xffff0000 | ||
176 | #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
177 | #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 | ||
178 | #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0xffff | ||
179 | #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
180 | |||
181 | /** | ||
182 | * Register: HW_TIMROT_TIMCTRL3 | ||
183 | * Address: 0x80 | ||
184 | * SCT: yes | ||
185 | */ | ||
186 | #define HW_TIMROT_TIMCTRL3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0)) | ||
187 | #define HW_TIMROT_TIMCTRL3_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4)) | ||
188 | #define HW_TIMROT_TIMCTRL3_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8)) | ||
189 | #define HW_TIMROT_TIMCTRL3_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc)) | ||
190 | #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 | ||
191 | #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0xf0000 | ||
192 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 | ||
193 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 | ||
194 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 | ||
195 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 | ||
196 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 | ||
197 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 | ||
198 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 | ||
199 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 | ||
200 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 | ||
201 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 | ||
202 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xa | ||
203 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xb | ||
204 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc | ||
205 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) (((v) << 16) & 0xf0000) | ||
206 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v) ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000) | ||
207 | #define BP_TIMROT_TIMCTRL3_IRQ 15 | ||
208 | #define BM_TIMROT_TIMCTRL3_IRQ 0x8000 | ||
209 | #define BF_TIMROT_TIMCTRL3_IRQ(v) (((v) << 15) & 0x8000) | ||
210 | #define BP_TIMROT_TIMCTRL3_IRQ_EN 14 | ||
211 | #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x4000 | ||
212 | #define BF_TIMROT_TIMCTRL3_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
213 | #define BP_TIMROT_TIMCTRL3_DUTY_VALID 10 | ||
214 | #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x400 | ||
215 | #define BF_TIMROT_TIMCTRL3_DUTY_VALID(v) (((v) << 10) & 0x400) | ||
216 | #define BP_TIMROT_TIMCTRL3_DUTY_CYCLE 9 | ||
217 | #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x200 | ||
218 | #define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v) (((v) << 9) & 0x200) | ||
219 | #define BP_TIMROT_TIMCTRL3_POLARITY 8 | ||
220 | #define BM_TIMROT_TIMCTRL3_POLARITY 0x100 | ||
221 | #define BF_TIMROT_TIMCTRL3_POLARITY(v) (((v) << 8) & 0x100) | ||
222 | #define BP_TIMROT_TIMCTRL3_UPDATE 7 | ||
223 | #define BM_TIMROT_TIMCTRL3_UPDATE 0x80 | ||
224 | #define BF_TIMROT_TIMCTRL3_UPDATE(v) (((v) << 7) & 0x80) | ||
225 | #define BP_TIMROT_TIMCTRL3_RELOAD 6 | ||
226 | #define BM_TIMROT_TIMCTRL3_RELOAD 0x40 | ||
227 | #define BF_TIMROT_TIMCTRL3_RELOAD(v) (((v) << 6) & 0x40) | ||
228 | #define BP_TIMROT_TIMCTRL3_PRESCALE 4 | ||
229 | #define BM_TIMROT_TIMCTRL3_PRESCALE 0x30 | ||
230 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 | ||
231 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 | ||
232 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 | ||
233 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 | ||
234 | #define BF_TIMROT_TIMCTRL3_PRESCALE(v) (((v) << 4) & 0x30) | ||
235 | #define BF_TIMROT_TIMCTRL3_PRESCALE_V(v) ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30) | ||
236 | #define BP_TIMROT_TIMCTRL3_SELECT 0 | ||
237 | #define BM_TIMROT_TIMCTRL3_SELECT 0xf | ||
238 | #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 | ||
239 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 | ||
240 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 | ||
241 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 | ||
242 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 | ||
243 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 | ||
244 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 | ||
245 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 | ||
246 | #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 | ||
247 | #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 | ||
248 | #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xa | ||
249 | #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xb | ||
250 | #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xc | ||
251 | #define BF_TIMROT_TIMCTRL3_SELECT(v) (((v) << 0) & 0xf) | ||
252 | #define BF_TIMROT_TIMCTRL3_SELECT_V(v) ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf) | ||
253 | |||
254 | /** | ||
255 | * Register: HW_TIMROT_TIMCOUNT3 | ||
256 | * Address: 0x90 | ||
257 | * SCT: no | ||
258 | */ | ||
259 | #define HW_TIMROT_TIMCOUNT3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90)) | ||
260 | #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 | ||
261 | #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xffff0000 | ||
262 | #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
263 | #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 | ||
264 | #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0xffff | ||
265 | #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
266 | |||
267 | /** | ||
268 | * Register: HW_TIMROT_VERSION | ||
269 | * Address: 0xa0 | ||
270 | * SCT: no | ||
271 | */ | ||
272 | #define HW_TIMROT_VERSION (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0xa0)) | ||
273 | #define BP_TIMROT_VERSION_MAJOR 24 | ||
274 | #define BM_TIMROT_VERSION_MAJOR 0xff000000 | ||
275 | #define BF_TIMROT_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
276 | #define BP_TIMROT_VERSION_MINOR 16 | ||
277 | #define BM_TIMROT_VERSION_MINOR 0xff0000 | ||
278 | #define BF_TIMROT_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
279 | #define BP_TIMROT_VERSION_STEP 0 | ||
280 | #define BM_TIMROT_VERSION_STEP 0xffff | ||
281 | #define BF_TIMROT_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
282 | |||
283 | #endif /* __HEADERGEN__STMP3700__TIMROT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h new file mode 100644 index 0000000000..a346fc1246 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h | |||
@@ -0,0 +1,427 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__UARTAPP__H__ | ||
24 | #define __HEADERGEN__STMP3700__UARTAPP__H__ | ||
25 | |||
26 | #define REGS_UARTAPP_BASE(i) ((i) == 1 ? 0x8006c000 : 0x8006e000) | ||
27 | |||
28 | #define REGS_UARTAPP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_UARTAPP_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_UARTAPP_CTRL0(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x0)) | ||
36 | #define HW_UARTAPP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x4)) | ||
37 | #define HW_UARTAPP_CTRL0_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x8)) | ||
38 | #define HW_UARTAPP_CTRL0_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0xc)) | ||
39 | #define BP_UARTAPP_CTRL0_SFTRST 31 | ||
40 | #define BM_UARTAPP_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_UARTAPP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_UARTAPP_CTRL0_CLKGATE 30 | ||
43 | #define BM_UARTAPP_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_UARTAPP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_UARTAPP_CTRL0_RUN 29 | ||
46 | #define BM_UARTAPP_CTRL0_RUN 0x20000000 | ||
47 | #define BF_UARTAPP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_UARTAPP_CTRL0_RX_SOURCE 28 | ||
49 | #define BM_UARTAPP_CTRL0_RX_SOURCE 0x10000000 | ||
50 | #define BF_UARTAPP_CTRL0_RX_SOURCE(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_UARTAPP_CTRL0_RXTO_ENABLE 27 | ||
52 | #define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x8000000 | ||
53 | #define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_UARTAPP_CTRL0_RXTIMEOUT 16 | ||
55 | #define BM_UARTAPP_CTRL0_RXTIMEOUT 0x7ff0000 | ||
56 | #define BF_UARTAPP_CTRL0_RXTIMEOUT(v) (((v) << 16) & 0x7ff0000) | ||
57 | #define BP_UARTAPP_CTRL0_XFER_COUNT 0 | ||
58 | #define BM_UARTAPP_CTRL0_XFER_COUNT 0xffff | ||
59 | #define BF_UARTAPP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
60 | |||
61 | /** | ||
62 | * Register: HW_UARTAPP_CTRL1 | ||
63 | * Address: 0x10 | ||
64 | * SCT: yes | ||
65 | */ | ||
66 | #define HW_UARTAPP_CTRL1(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x0)) | ||
67 | #define HW_UARTAPP_CTRL1_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x4)) | ||
68 | #define HW_UARTAPP_CTRL1_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x8)) | ||
69 | #define HW_UARTAPP_CTRL1_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0xc)) | ||
70 | #define BP_UARTAPP_CTRL1_RUN 28 | ||
71 | #define BM_UARTAPP_CTRL1_RUN 0x10000000 | ||
72 | #define BF_UARTAPP_CTRL1_RUN(v) (((v) << 28) & 0x10000000) | ||
73 | #define BP_UARTAPP_CTRL1_XFER_COUNT 0 | ||
74 | #define BM_UARTAPP_CTRL1_XFER_COUNT 0xffff | ||
75 | #define BF_UARTAPP_CTRL1_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
76 | |||
77 | /** | ||
78 | * Register: HW_UARTAPP_CTRL2 | ||
79 | * Address: 0x20 | ||
80 | * SCT: yes | ||
81 | */ | ||
82 | #define HW_UARTAPP_CTRL2(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x0)) | ||
83 | #define HW_UARTAPP_CTRL2_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x4)) | ||
84 | #define HW_UARTAPP_CTRL2_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x8)) | ||
85 | #define HW_UARTAPP_CTRL2_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0xc)) | ||
86 | #define BP_UARTAPP_CTRL2_INVERT_RTS 31 | ||
87 | #define BM_UARTAPP_CTRL2_INVERT_RTS 0x80000000 | ||
88 | #define BF_UARTAPP_CTRL2_INVERT_RTS(v) (((v) << 31) & 0x80000000) | ||
89 | #define BP_UARTAPP_CTRL2_INVERT_CTS 30 | ||
90 | #define BM_UARTAPP_CTRL2_INVERT_CTS 0x40000000 | ||
91 | #define BF_UARTAPP_CTRL2_INVERT_CTS(v) (((v) << 30) & 0x40000000) | ||
92 | #define BP_UARTAPP_CTRL2_INVERT_TX 29 | ||
93 | #define BM_UARTAPP_CTRL2_INVERT_TX 0x20000000 | ||
94 | #define BF_UARTAPP_CTRL2_INVERT_TX(v) (((v) << 29) & 0x20000000) | ||
95 | #define BP_UARTAPP_CTRL2_INVERT_RX 28 | ||
96 | #define BM_UARTAPP_CTRL2_INVERT_RX 0x10000000 | ||
97 | #define BF_UARTAPP_CTRL2_INVERT_RX(v) (((v) << 28) & 0x10000000) | ||
98 | #define BP_UARTAPP_CTRL2_RTS_SEMAPHORE 27 | ||
99 | #define BM_UARTAPP_CTRL2_RTS_SEMAPHORE 0x8000000 | ||
100 | #define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v) (((v) << 27) & 0x8000000) | ||
101 | #define BP_UARTAPP_CTRL2_DMAONERR 26 | ||
102 | #define BM_UARTAPP_CTRL2_DMAONERR 0x4000000 | ||
103 | #define BF_UARTAPP_CTRL2_DMAONERR(v) (((v) << 26) & 0x4000000) | ||
104 | #define BP_UARTAPP_CTRL2_TXDMAE 25 | ||
105 | #define BM_UARTAPP_CTRL2_TXDMAE 0x2000000 | ||
106 | #define BF_UARTAPP_CTRL2_TXDMAE(v) (((v) << 25) & 0x2000000) | ||
107 | #define BP_UARTAPP_CTRL2_RXDMAE 24 | ||
108 | #define BM_UARTAPP_CTRL2_RXDMAE 0x1000000 | ||
109 | #define BF_UARTAPP_CTRL2_RXDMAE(v) (((v) << 24) & 0x1000000) | ||
110 | #define BP_UARTAPP_CTRL2_RXIFLSEL 20 | ||
111 | #define BM_UARTAPP_CTRL2_RXIFLSEL 0x700000 | ||
112 | #define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 | ||
113 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 | ||
114 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 | ||
115 | #define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 | ||
116 | #define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
117 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 | ||
118 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 | ||
119 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 | ||
120 | #define BF_UARTAPP_CTRL2_RXIFLSEL(v) (((v) << 20) & 0x700000) | ||
121 | #define BF_UARTAPP_CTRL2_RXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000) | ||
122 | #define BP_UARTAPP_CTRL2_TXIFLSEL 16 | ||
123 | #define BM_UARTAPP_CTRL2_TXIFLSEL 0x70000 | ||
124 | #define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 | ||
125 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 | ||
126 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 | ||
127 | #define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 | ||
128 | #define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
129 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 | ||
130 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 | ||
131 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 | ||
132 | #define BF_UARTAPP_CTRL2_TXIFLSEL(v) (((v) << 16) & 0x70000) | ||
133 | #define BF_UARTAPP_CTRL2_TXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000) | ||
134 | #define BP_UARTAPP_CTRL2_CTSEN 15 | ||
135 | #define BM_UARTAPP_CTRL2_CTSEN 0x8000 | ||
136 | #define BF_UARTAPP_CTRL2_CTSEN(v) (((v) << 15) & 0x8000) | ||
137 | #define BP_UARTAPP_CTRL2_RTSEN 14 | ||
138 | #define BM_UARTAPP_CTRL2_RTSEN 0x4000 | ||
139 | #define BF_UARTAPP_CTRL2_RTSEN(v) (((v) << 14) & 0x4000) | ||
140 | #define BP_UARTAPP_CTRL2_OUT2 13 | ||
141 | #define BM_UARTAPP_CTRL2_OUT2 0x2000 | ||
142 | #define BF_UARTAPP_CTRL2_OUT2(v) (((v) << 13) & 0x2000) | ||
143 | #define BP_UARTAPP_CTRL2_OUT1 12 | ||
144 | #define BM_UARTAPP_CTRL2_OUT1 0x1000 | ||
145 | #define BF_UARTAPP_CTRL2_OUT1(v) (((v) << 12) & 0x1000) | ||
146 | #define BP_UARTAPP_CTRL2_RTS 11 | ||
147 | #define BM_UARTAPP_CTRL2_RTS 0x800 | ||
148 | #define BF_UARTAPP_CTRL2_RTS(v) (((v) << 11) & 0x800) | ||
149 | #define BP_UARTAPP_CTRL2_DTR 10 | ||
150 | #define BM_UARTAPP_CTRL2_DTR 0x400 | ||
151 | #define BF_UARTAPP_CTRL2_DTR(v) (((v) << 10) & 0x400) | ||
152 | #define BP_UARTAPP_CTRL2_RXE 9 | ||
153 | #define BM_UARTAPP_CTRL2_RXE 0x200 | ||
154 | #define BF_UARTAPP_CTRL2_RXE(v) (((v) << 9) & 0x200) | ||
155 | #define BP_UARTAPP_CTRL2_TXE 8 | ||
156 | #define BM_UARTAPP_CTRL2_TXE 0x100 | ||
157 | #define BF_UARTAPP_CTRL2_TXE(v) (((v) << 8) & 0x100) | ||
158 | #define BP_UARTAPP_CTRL2_LBE 7 | ||
159 | #define BM_UARTAPP_CTRL2_LBE 0x80 | ||
160 | #define BF_UARTAPP_CTRL2_LBE(v) (((v) << 7) & 0x80) | ||
161 | #define BP_UARTAPP_CTRL2_USE_LCR2 6 | ||
162 | #define BM_UARTAPP_CTRL2_USE_LCR2 0x40 | ||
163 | #define BF_UARTAPP_CTRL2_USE_LCR2(v) (((v) << 6) & 0x40) | ||
164 | #define BP_UARTAPP_CTRL2_SIRLP 2 | ||
165 | #define BM_UARTAPP_CTRL2_SIRLP 0x4 | ||
166 | #define BF_UARTAPP_CTRL2_SIRLP(v) (((v) << 2) & 0x4) | ||
167 | #define BP_UARTAPP_CTRL2_SIREN 1 | ||
168 | #define BM_UARTAPP_CTRL2_SIREN 0x2 | ||
169 | #define BF_UARTAPP_CTRL2_SIREN(v) (((v) << 1) & 0x2) | ||
170 | #define BP_UARTAPP_CTRL2_UARTEN 0 | ||
171 | #define BM_UARTAPP_CTRL2_UARTEN 0x1 | ||
172 | #define BF_UARTAPP_CTRL2_UARTEN(v) (((v) << 0) & 0x1) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_UARTAPP_LINECTRL | ||
176 | * Address: 0x30 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_UARTAPP_LINECTRL(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x0)) | ||
180 | #define HW_UARTAPP_LINECTRL_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x4)) | ||
181 | #define HW_UARTAPP_LINECTRL_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x8)) | ||
182 | #define HW_UARTAPP_LINECTRL_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0xc)) | ||
183 | #define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 | ||
184 | #define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xffff0000 | ||
185 | #define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
186 | #define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 | ||
187 | #define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x3f00 | ||
188 | #define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
189 | #define BP_UARTAPP_LINECTRL_SPS 7 | ||
190 | #define BM_UARTAPP_LINECTRL_SPS 0x80 | ||
191 | #define BF_UARTAPP_LINECTRL_SPS(v) (((v) << 7) & 0x80) | ||
192 | #define BP_UARTAPP_LINECTRL_WLEN 5 | ||
193 | #define BM_UARTAPP_LINECTRL_WLEN 0x60 | ||
194 | #define BF_UARTAPP_LINECTRL_WLEN(v) (((v) << 5) & 0x60) | ||
195 | #define BP_UARTAPP_LINECTRL_FEN 4 | ||
196 | #define BM_UARTAPP_LINECTRL_FEN 0x10 | ||
197 | #define BF_UARTAPP_LINECTRL_FEN(v) (((v) << 4) & 0x10) | ||
198 | #define BP_UARTAPP_LINECTRL_STP2 3 | ||
199 | #define BM_UARTAPP_LINECTRL_STP2 0x8 | ||
200 | #define BF_UARTAPP_LINECTRL_STP2(v) (((v) << 3) & 0x8) | ||
201 | #define BP_UARTAPP_LINECTRL_EPS 2 | ||
202 | #define BM_UARTAPP_LINECTRL_EPS 0x4 | ||
203 | #define BF_UARTAPP_LINECTRL_EPS(v) (((v) << 2) & 0x4) | ||
204 | #define BP_UARTAPP_LINECTRL_PEN 1 | ||
205 | #define BM_UARTAPP_LINECTRL_PEN 0x2 | ||
206 | #define BF_UARTAPP_LINECTRL_PEN(v) (((v) << 1) & 0x2) | ||
207 | #define BP_UARTAPP_LINECTRL_BRK 0 | ||
208 | #define BM_UARTAPP_LINECTRL_BRK 0x1 | ||
209 | #define BF_UARTAPP_LINECTRL_BRK(v) (((v) << 0) & 0x1) | ||
210 | |||
211 | /** | ||
212 | * Register: HW_UARTAPP_LINECTRL2 | ||
213 | * Address: 0x40 | ||
214 | * SCT: yes | ||
215 | */ | ||
216 | #define HW_UARTAPP_LINECTRL2(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x0)) | ||
217 | #define HW_UARTAPP_LINECTRL2_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x4)) | ||
218 | #define HW_UARTAPP_LINECTRL2_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x8)) | ||
219 | #define HW_UARTAPP_LINECTRL2_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0xc)) | ||
220 | #define BP_UARTAPP_LINECTRL2_BAUD_DIVINT 16 | ||
221 | #define BM_UARTAPP_LINECTRL2_BAUD_DIVINT 0xffff0000 | ||
222 | #define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
223 | #define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC 8 | ||
224 | #define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC 0x3f00 | ||
225 | #define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
226 | #define BP_UARTAPP_LINECTRL2_SPS 7 | ||
227 | #define BM_UARTAPP_LINECTRL2_SPS 0x80 | ||
228 | #define BF_UARTAPP_LINECTRL2_SPS(v) (((v) << 7) & 0x80) | ||
229 | #define BP_UARTAPP_LINECTRL2_WLEN 5 | ||
230 | #define BM_UARTAPP_LINECTRL2_WLEN 0x60 | ||
231 | #define BF_UARTAPP_LINECTRL2_WLEN(v) (((v) << 5) & 0x60) | ||
232 | #define BP_UARTAPP_LINECTRL2_FEN 4 | ||
233 | #define BM_UARTAPP_LINECTRL2_FEN 0x10 | ||
234 | #define BF_UARTAPP_LINECTRL2_FEN(v) (((v) << 4) & 0x10) | ||
235 | #define BP_UARTAPP_LINECTRL2_STP2 3 | ||
236 | #define BM_UARTAPP_LINECTRL2_STP2 0x8 | ||
237 | #define BF_UARTAPP_LINECTRL2_STP2(v) (((v) << 3) & 0x8) | ||
238 | #define BP_UARTAPP_LINECTRL2_EPS 2 | ||
239 | #define BM_UARTAPP_LINECTRL2_EPS 0x4 | ||
240 | #define BF_UARTAPP_LINECTRL2_EPS(v) (((v) << 2) & 0x4) | ||
241 | #define BP_UARTAPP_LINECTRL2_PEN 1 | ||
242 | #define BM_UARTAPP_LINECTRL2_PEN 0x2 | ||
243 | #define BF_UARTAPP_LINECTRL2_PEN(v) (((v) << 1) & 0x2) | ||
244 | |||
245 | /** | ||
246 | * Register: HW_UARTAPP_INTR | ||
247 | * Address: 0x50 | ||
248 | * SCT: yes | ||
249 | */ | ||
250 | #define HW_UARTAPP_INTR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x0)) | ||
251 | #define HW_UARTAPP_INTR_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x4)) | ||
252 | #define HW_UARTAPP_INTR_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x8)) | ||
253 | #define HW_UARTAPP_INTR_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0xc)) | ||
254 | #define BP_UARTAPP_INTR_OEIEN 26 | ||
255 | #define BM_UARTAPP_INTR_OEIEN 0x4000000 | ||
256 | #define BF_UARTAPP_INTR_OEIEN(v) (((v) << 26) & 0x4000000) | ||
257 | #define BP_UARTAPP_INTR_BEIEN 25 | ||
258 | #define BM_UARTAPP_INTR_BEIEN 0x2000000 | ||
259 | #define BF_UARTAPP_INTR_BEIEN(v) (((v) << 25) & 0x2000000) | ||
260 | #define BP_UARTAPP_INTR_PEIEN 24 | ||
261 | #define BM_UARTAPP_INTR_PEIEN 0x1000000 | ||
262 | #define BF_UARTAPP_INTR_PEIEN(v) (((v) << 24) & 0x1000000) | ||
263 | #define BP_UARTAPP_INTR_FEIEN 23 | ||
264 | #define BM_UARTAPP_INTR_FEIEN 0x800000 | ||
265 | #define BF_UARTAPP_INTR_FEIEN(v) (((v) << 23) & 0x800000) | ||
266 | #define BP_UARTAPP_INTR_RTIEN 22 | ||
267 | #define BM_UARTAPP_INTR_RTIEN 0x400000 | ||
268 | #define BF_UARTAPP_INTR_RTIEN(v) (((v) << 22) & 0x400000) | ||
269 | #define BP_UARTAPP_INTR_TXIEN 21 | ||
270 | #define BM_UARTAPP_INTR_TXIEN 0x200000 | ||
271 | #define BF_UARTAPP_INTR_TXIEN(v) (((v) << 21) & 0x200000) | ||
272 | #define BP_UARTAPP_INTR_RXIEN 20 | ||
273 | #define BM_UARTAPP_INTR_RXIEN 0x100000 | ||
274 | #define BF_UARTAPP_INTR_RXIEN(v) (((v) << 20) & 0x100000) | ||
275 | #define BP_UARTAPP_INTR_DSRMIEN 19 | ||
276 | #define BM_UARTAPP_INTR_DSRMIEN 0x80000 | ||
277 | #define BF_UARTAPP_INTR_DSRMIEN(v) (((v) << 19) & 0x80000) | ||
278 | #define BP_UARTAPP_INTR_DCDMIEN 18 | ||
279 | #define BM_UARTAPP_INTR_DCDMIEN 0x40000 | ||
280 | #define BF_UARTAPP_INTR_DCDMIEN(v) (((v) << 18) & 0x40000) | ||
281 | #define BP_UARTAPP_INTR_CTSMIEN 17 | ||
282 | #define BM_UARTAPP_INTR_CTSMIEN 0x20000 | ||
283 | #define BF_UARTAPP_INTR_CTSMIEN(v) (((v) << 17) & 0x20000) | ||
284 | #define BP_UARTAPP_INTR_RIMIEN 16 | ||
285 | #define BM_UARTAPP_INTR_RIMIEN 0x10000 | ||
286 | #define BF_UARTAPP_INTR_RIMIEN(v) (((v) << 16) & 0x10000) | ||
287 | #define BP_UARTAPP_INTR_OEIS 10 | ||
288 | #define BM_UARTAPP_INTR_OEIS 0x400 | ||
289 | #define BF_UARTAPP_INTR_OEIS(v) (((v) << 10) & 0x400) | ||
290 | #define BP_UARTAPP_INTR_BEIS 9 | ||
291 | #define BM_UARTAPP_INTR_BEIS 0x200 | ||
292 | #define BF_UARTAPP_INTR_BEIS(v) (((v) << 9) & 0x200) | ||
293 | #define BP_UARTAPP_INTR_PEIS 8 | ||
294 | #define BM_UARTAPP_INTR_PEIS 0x100 | ||
295 | #define BF_UARTAPP_INTR_PEIS(v) (((v) << 8) & 0x100) | ||
296 | #define BP_UARTAPP_INTR_FEIS 7 | ||
297 | #define BM_UARTAPP_INTR_FEIS 0x80 | ||
298 | #define BF_UARTAPP_INTR_FEIS(v) (((v) << 7) & 0x80) | ||
299 | #define BP_UARTAPP_INTR_RTIS 6 | ||
300 | #define BM_UARTAPP_INTR_RTIS 0x40 | ||
301 | #define BF_UARTAPP_INTR_RTIS(v) (((v) << 6) & 0x40) | ||
302 | #define BP_UARTAPP_INTR_TXIS 5 | ||
303 | #define BM_UARTAPP_INTR_TXIS 0x20 | ||
304 | #define BF_UARTAPP_INTR_TXIS(v) (((v) << 5) & 0x20) | ||
305 | #define BP_UARTAPP_INTR_RXIS 4 | ||
306 | #define BM_UARTAPP_INTR_RXIS 0x10 | ||
307 | #define BF_UARTAPP_INTR_RXIS(v) (((v) << 4) & 0x10) | ||
308 | #define BP_UARTAPP_INTR_DSRMIS 3 | ||
309 | #define BM_UARTAPP_INTR_DSRMIS 0x8 | ||
310 | #define BF_UARTAPP_INTR_DSRMIS(v) (((v) << 3) & 0x8) | ||
311 | #define BP_UARTAPP_INTR_DCDMIS 2 | ||
312 | #define BM_UARTAPP_INTR_DCDMIS 0x4 | ||
313 | #define BF_UARTAPP_INTR_DCDMIS(v) (((v) << 2) & 0x4) | ||
314 | #define BP_UARTAPP_INTR_CTSMIS 1 | ||
315 | #define BM_UARTAPP_INTR_CTSMIS 0x2 | ||
316 | #define BF_UARTAPP_INTR_CTSMIS(v) (((v) << 1) & 0x2) | ||
317 | #define BP_UARTAPP_INTR_RIMIS 0 | ||
318 | #define BM_UARTAPP_INTR_RIMIS 0x1 | ||
319 | #define BF_UARTAPP_INTR_RIMIS(v) (((v) << 0) & 0x1) | ||
320 | |||
321 | /** | ||
322 | * Register: HW_UARTAPP_DATA | ||
323 | * Address: 0x60 | ||
324 | * SCT: no | ||
325 | */ | ||
326 | #define HW_UARTAPP_DATA(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x60)) | ||
327 | #define BP_UARTAPP_DATA_DATA 0 | ||
328 | #define BM_UARTAPP_DATA_DATA 0xffffffff | ||
329 | #define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_UARTAPP_STAT | ||
333 | * Address: 0x70 | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_UARTAPP_STAT(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x70)) | ||
337 | #define BP_UARTAPP_STAT_PRESENT 31 | ||
338 | #define BM_UARTAPP_STAT_PRESENT 0x80000000 | ||
339 | #define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 | ||
340 | #define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 | ||
341 | #define BF_UARTAPP_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
342 | #define BF_UARTAPP_STAT_PRESENT_V(v) ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000) | ||
343 | #define BP_UARTAPP_STAT_HISPEED 30 | ||
344 | #define BM_UARTAPP_STAT_HISPEED 0x40000000 | ||
345 | #define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 | ||
346 | #define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 | ||
347 | #define BF_UARTAPP_STAT_HISPEED(v) (((v) << 30) & 0x40000000) | ||
348 | #define BF_UARTAPP_STAT_HISPEED_V(v) ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000) | ||
349 | #define BP_UARTAPP_STAT_BUSY 29 | ||
350 | #define BM_UARTAPP_STAT_BUSY 0x20000000 | ||
351 | #define BF_UARTAPP_STAT_BUSY(v) (((v) << 29) & 0x20000000) | ||
352 | #define BP_UARTAPP_STAT_CTS 28 | ||
353 | #define BM_UARTAPP_STAT_CTS 0x10000000 | ||
354 | #define BF_UARTAPP_STAT_CTS(v) (((v) << 28) & 0x10000000) | ||
355 | #define BP_UARTAPP_STAT_TXFE 27 | ||
356 | #define BM_UARTAPP_STAT_TXFE 0x8000000 | ||
357 | #define BF_UARTAPP_STAT_TXFE(v) (((v) << 27) & 0x8000000) | ||
358 | #define BP_UARTAPP_STAT_RXFF 26 | ||
359 | #define BM_UARTAPP_STAT_RXFF 0x4000000 | ||
360 | #define BF_UARTAPP_STAT_RXFF(v) (((v) << 26) & 0x4000000) | ||
361 | #define BP_UARTAPP_STAT_TXFF 25 | ||
362 | #define BM_UARTAPP_STAT_TXFF 0x2000000 | ||
363 | #define BF_UARTAPP_STAT_TXFF(v) (((v) << 25) & 0x2000000) | ||
364 | #define BP_UARTAPP_STAT_RXFE 24 | ||
365 | #define BM_UARTAPP_STAT_RXFE 0x1000000 | ||
366 | #define BF_UARTAPP_STAT_RXFE(v) (((v) << 24) & 0x1000000) | ||
367 | #define BP_UARTAPP_STAT_RXBYTE_INVALID 20 | ||
368 | #define BM_UARTAPP_STAT_RXBYTE_INVALID 0xf00000 | ||
369 | #define BF_UARTAPP_STAT_RXBYTE_INVALID(v) (((v) << 20) & 0xf00000) | ||
370 | #define BP_UARTAPP_STAT_OERR 19 | ||
371 | #define BM_UARTAPP_STAT_OERR 0x80000 | ||
372 | #define BF_UARTAPP_STAT_OERR(v) (((v) << 19) & 0x80000) | ||
373 | #define BP_UARTAPP_STAT_BERR 18 | ||
374 | #define BM_UARTAPP_STAT_BERR 0x40000 | ||
375 | #define BF_UARTAPP_STAT_BERR(v) (((v) << 18) & 0x40000) | ||
376 | #define BP_UARTAPP_STAT_PERR 17 | ||
377 | #define BM_UARTAPP_STAT_PERR 0x20000 | ||
378 | #define BF_UARTAPP_STAT_PERR(v) (((v) << 17) & 0x20000) | ||
379 | #define BP_UARTAPP_STAT_FERR 16 | ||
380 | #define BM_UARTAPP_STAT_FERR 0x10000 | ||
381 | #define BF_UARTAPP_STAT_FERR(v) (((v) << 16) & 0x10000) | ||
382 | #define BP_UARTAPP_STAT_RXCOUNT 0 | ||
383 | #define BM_UARTAPP_STAT_RXCOUNT 0xffff | ||
384 | #define BF_UARTAPP_STAT_RXCOUNT(v) (((v) << 0) & 0xffff) | ||
385 | |||
386 | /** | ||
387 | * Register: HW_UARTAPP_DEBUG | ||
388 | * Address: 0x80 | ||
389 | * SCT: no | ||
390 | */ | ||
391 | #define HW_UARTAPP_DEBUG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x80)) | ||
392 | #define BP_UARTAPP_DEBUG_TXDMARUN 5 | ||
393 | #define BM_UARTAPP_DEBUG_TXDMARUN 0x20 | ||
394 | #define BF_UARTAPP_DEBUG_TXDMARUN(v) (((v) << 5) & 0x20) | ||
395 | #define BP_UARTAPP_DEBUG_RXDMARUN 4 | ||
396 | #define BM_UARTAPP_DEBUG_RXDMARUN 0x10 | ||
397 | #define BF_UARTAPP_DEBUG_RXDMARUN(v) (((v) << 4) & 0x10) | ||
398 | #define BP_UARTAPP_DEBUG_TXCMDEND 3 | ||
399 | #define BM_UARTAPP_DEBUG_TXCMDEND 0x8 | ||
400 | #define BF_UARTAPP_DEBUG_TXCMDEND(v) (((v) << 3) & 0x8) | ||
401 | #define BP_UARTAPP_DEBUG_RXCMDEND 2 | ||
402 | #define BM_UARTAPP_DEBUG_RXCMDEND 0x4 | ||
403 | #define BF_UARTAPP_DEBUG_RXCMDEND(v) (((v) << 2) & 0x4) | ||
404 | #define BP_UARTAPP_DEBUG_TXDMARQ 1 | ||
405 | #define BM_UARTAPP_DEBUG_TXDMARQ 0x2 | ||
406 | #define BF_UARTAPP_DEBUG_TXDMARQ(v) (((v) << 1) & 0x2) | ||
407 | #define BP_UARTAPP_DEBUG_RXDMARQ 0 | ||
408 | #define BM_UARTAPP_DEBUG_RXDMARQ 0x1 | ||
409 | #define BF_UARTAPP_DEBUG_RXDMARQ(v) (((v) << 0) & 0x1) | ||
410 | |||
411 | /** | ||
412 | * Register: HW_UARTAPP_VERSION | ||
413 | * Address: 0x90 | ||
414 | * SCT: no | ||
415 | */ | ||
416 | #define HW_UARTAPP_VERSION(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x90)) | ||
417 | #define BP_UARTAPP_VERSION_MAJOR 24 | ||
418 | #define BM_UARTAPP_VERSION_MAJOR 0xff000000 | ||
419 | #define BF_UARTAPP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
420 | #define BP_UARTAPP_VERSION_MINOR 16 | ||
421 | #define BM_UARTAPP_VERSION_MINOR 0xff0000 | ||
422 | #define BF_UARTAPP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
423 | #define BP_UARTAPP_VERSION_STEP 0 | ||
424 | #define BM_UARTAPP_VERSION_STEP 0xffff | ||
425 | #define BF_UARTAPP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
426 | |||
427 | #endif /* __HEADERGEN__STMP3700__UARTAPP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h new file mode 100644 index 0000000000..d1ef6f2608 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h | |||
@@ -0,0 +1,491 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__UARTDBG__H__ | ||
24 | #define __HEADERGEN__STMP3700__UARTDBG__H__ | ||
25 | |||
26 | #define REGS_UARTDBG_BASE (0x80070000) | ||
27 | |||
28 | #define REGS_UARTDBG_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_UARTDBG_DR | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_UARTDBG_DR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0)) | ||
36 | #define BP_UARTDBG_DR_UNAVAILABLE 16 | ||
37 | #define BM_UARTDBG_DR_UNAVAILABLE 0xffff0000 | ||
38 | #define BF_UARTDBG_DR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
39 | #define BP_UARTDBG_DR_RESERVED 12 | ||
40 | #define BM_UARTDBG_DR_RESERVED 0xf000 | ||
41 | #define BF_UARTDBG_DR_RESERVED(v) (((v) << 12) & 0xf000) | ||
42 | #define BP_UARTDBG_DR_OE 11 | ||
43 | #define BM_UARTDBG_DR_OE 0x800 | ||
44 | #define BF_UARTDBG_DR_OE(v) (((v) << 11) & 0x800) | ||
45 | #define BP_UARTDBG_DR_BE 10 | ||
46 | #define BM_UARTDBG_DR_BE 0x400 | ||
47 | #define BF_UARTDBG_DR_BE(v) (((v) << 10) & 0x400) | ||
48 | #define BP_UARTDBG_DR_PE 9 | ||
49 | #define BM_UARTDBG_DR_PE 0x200 | ||
50 | #define BF_UARTDBG_DR_PE(v) (((v) << 9) & 0x200) | ||
51 | #define BP_UARTDBG_DR_FE 8 | ||
52 | #define BM_UARTDBG_DR_FE 0x100 | ||
53 | #define BF_UARTDBG_DR_FE(v) (((v) << 8) & 0x100) | ||
54 | #define BP_UARTDBG_DR_DATA 0 | ||
55 | #define BM_UARTDBG_DR_DATA 0xff | ||
56 | #define BF_UARTDBG_DR_DATA(v) (((v) << 0) & 0xff) | ||
57 | |||
58 | /** | ||
59 | * Register: HW_UARTDBG_RSR_ECR | ||
60 | * Address: 0x4 | ||
61 | * SCT: no | ||
62 | */ | ||
63 | #define HW_UARTDBG_RSR_ECR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4)) | ||
64 | #define BP_UARTDBG_RSR_ECR_UNAVAILABLE 8 | ||
65 | #define BM_UARTDBG_RSR_ECR_UNAVAILABLE 0xffffff00 | ||
66 | #define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
67 | #define BP_UARTDBG_RSR_ECR_EC 4 | ||
68 | #define BM_UARTDBG_RSR_ECR_EC 0xf0 | ||
69 | #define BF_UARTDBG_RSR_ECR_EC(v) (((v) << 4) & 0xf0) | ||
70 | #define BP_UARTDBG_RSR_ECR_OE 3 | ||
71 | #define BM_UARTDBG_RSR_ECR_OE 0x8 | ||
72 | #define BF_UARTDBG_RSR_ECR_OE(v) (((v) << 3) & 0x8) | ||
73 | #define BP_UARTDBG_RSR_ECR_BE 2 | ||
74 | #define BM_UARTDBG_RSR_ECR_BE 0x4 | ||
75 | #define BF_UARTDBG_RSR_ECR_BE(v) (((v) << 2) & 0x4) | ||
76 | #define BP_UARTDBG_RSR_ECR_PE 1 | ||
77 | #define BM_UARTDBG_RSR_ECR_PE 0x2 | ||
78 | #define BF_UARTDBG_RSR_ECR_PE(v) (((v) << 1) & 0x2) | ||
79 | #define BP_UARTDBG_RSR_ECR_FE 0 | ||
80 | #define BM_UARTDBG_RSR_ECR_FE 0x1 | ||
81 | #define BF_UARTDBG_RSR_ECR_FE(v) (((v) << 0) & 0x1) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_UARTDBG_FR | ||
85 | * Address: 0x18 | ||
86 | * SCT: no | ||
87 | */ | ||
88 | #define HW_UARTDBG_FR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18)) | ||
89 | #define BP_UARTDBG_FR_UNAVAILABLE 16 | ||
90 | #define BM_UARTDBG_FR_UNAVAILABLE 0xffff0000 | ||
91 | #define BF_UARTDBG_FR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
92 | #define BP_UARTDBG_FR_RESERVED 9 | ||
93 | #define BM_UARTDBG_FR_RESERVED 0xfe00 | ||
94 | #define BF_UARTDBG_FR_RESERVED(v) (((v) << 9) & 0xfe00) | ||
95 | #define BP_UARTDBG_FR_RI 8 | ||
96 | #define BM_UARTDBG_FR_RI 0x100 | ||
97 | #define BF_UARTDBG_FR_RI(v) (((v) << 8) & 0x100) | ||
98 | #define BP_UARTDBG_FR_TXFE 7 | ||
99 | #define BM_UARTDBG_FR_TXFE 0x80 | ||
100 | #define BF_UARTDBG_FR_TXFE(v) (((v) << 7) & 0x80) | ||
101 | #define BP_UARTDBG_FR_RXFF 6 | ||
102 | #define BM_UARTDBG_FR_RXFF 0x40 | ||
103 | #define BF_UARTDBG_FR_RXFF(v) (((v) << 6) & 0x40) | ||
104 | #define BP_UARTDBG_FR_TXFF 5 | ||
105 | #define BM_UARTDBG_FR_TXFF 0x20 | ||
106 | #define BF_UARTDBG_FR_TXFF(v) (((v) << 5) & 0x20) | ||
107 | #define BP_UARTDBG_FR_RXFE 4 | ||
108 | #define BM_UARTDBG_FR_RXFE 0x10 | ||
109 | #define BF_UARTDBG_FR_RXFE(v) (((v) << 4) & 0x10) | ||
110 | #define BP_UARTDBG_FR_BUSY 3 | ||
111 | #define BM_UARTDBG_FR_BUSY 0x8 | ||
112 | #define BF_UARTDBG_FR_BUSY(v) (((v) << 3) & 0x8) | ||
113 | #define BP_UARTDBG_FR_DCD 2 | ||
114 | #define BM_UARTDBG_FR_DCD 0x4 | ||
115 | #define BF_UARTDBG_FR_DCD(v) (((v) << 2) & 0x4) | ||
116 | #define BP_UARTDBG_FR_DSR 1 | ||
117 | #define BM_UARTDBG_FR_DSR 0x2 | ||
118 | #define BF_UARTDBG_FR_DSR(v) (((v) << 1) & 0x2) | ||
119 | #define BP_UARTDBG_FR_CTS 0 | ||
120 | #define BM_UARTDBG_FR_CTS 0x1 | ||
121 | #define BF_UARTDBG_FR_CTS(v) (((v) << 0) & 0x1) | ||
122 | |||
123 | /** | ||
124 | * Register: HW_UARTDBG_ILPR | ||
125 | * Address: 0x20 | ||
126 | * SCT: no | ||
127 | */ | ||
128 | #define HW_UARTDBG_ILPR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20)) | ||
129 | #define BP_UARTDBG_ILPR_UNAVAILABLE 8 | ||
130 | #define BM_UARTDBG_ILPR_UNAVAILABLE 0xffffff00 | ||
131 | #define BF_UARTDBG_ILPR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
132 | #define BP_UARTDBG_ILPR_ILPDVSR 0 | ||
133 | #define BM_UARTDBG_ILPR_ILPDVSR 0xff | ||
134 | #define BF_UARTDBG_ILPR_ILPDVSR(v) (((v) << 0) & 0xff) | ||
135 | |||
136 | /** | ||
137 | * Register: HW_UARTDBG_IBRD | ||
138 | * Address: 0x24 | ||
139 | * SCT: no | ||
140 | */ | ||
141 | #define HW_UARTDBG_IBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24)) | ||
142 | #define BP_UARTDBG_IBRD_UNAVAILABLE 16 | ||
143 | #define BM_UARTDBG_IBRD_UNAVAILABLE 0xffff0000 | ||
144 | #define BF_UARTDBG_IBRD_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
145 | #define BP_UARTDBG_IBRD_BAUD_DIVINT 0 | ||
146 | #define BM_UARTDBG_IBRD_BAUD_DIVINT 0xffff | ||
147 | #define BF_UARTDBG_IBRD_BAUD_DIVINT(v) (((v) << 0) & 0xffff) | ||
148 | |||
149 | /** | ||
150 | * Register: HW_UARTDBG_FBRD | ||
151 | * Address: 0x28 | ||
152 | * SCT: no | ||
153 | */ | ||
154 | #define HW_UARTDBG_FBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28)) | ||
155 | #define BP_UARTDBG_FBRD_UNAVAILABLE 8 | ||
156 | #define BM_UARTDBG_FBRD_UNAVAILABLE 0xffffff00 | ||
157 | #define BF_UARTDBG_FBRD_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
158 | #define BP_UARTDBG_FBRD_RESERVED 6 | ||
159 | #define BM_UARTDBG_FBRD_RESERVED 0xc0 | ||
160 | #define BF_UARTDBG_FBRD_RESERVED(v) (((v) << 6) & 0xc0) | ||
161 | #define BP_UARTDBG_FBRD_BAUD_DIVFRAC 0 | ||
162 | #define BM_UARTDBG_FBRD_BAUD_DIVFRAC 0x3f | ||
163 | #define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_UARTDBG_LCR_H | ||
167 | * Address: 0x2c | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_UARTDBG_LCR_H (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c)) | ||
171 | #define BP_UARTDBG_LCR_H_UNAVAILABLE 16 | ||
172 | #define BM_UARTDBG_LCR_H_UNAVAILABLE 0xffff0000 | ||
173 | #define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
174 | #define BP_UARTDBG_LCR_H_RESERVED 8 | ||
175 | #define BM_UARTDBG_LCR_H_RESERVED 0xff00 | ||
176 | #define BF_UARTDBG_LCR_H_RESERVED(v) (((v) << 8) & 0xff00) | ||
177 | #define BP_UARTDBG_LCR_H_SPS 7 | ||
178 | #define BM_UARTDBG_LCR_H_SPS 0x80 | ||
179 | #define BF_UARTDBG_LCR_H_SPS(v) (((v) << 7) & 0x80) | ||
180 | #define BP_UARTDBG_LCR_H_WLEN 5 | ||
181 | #define BM_UARTDBG_LCR_H_WLEN 0x60 | ||
182 | #define BF_UARTDBG_LCR_H_WLEN(v) (((v) << 5) & 0x60) | ||
183 | #define BP_UARTDBG_LCR_H_FEN 4 | ||
184 | #define BM_UARTDBG_LCR_H_FEN 0x10 | ||
185 | #define BF_UARTDBG_LCR_H_FEN(v) (((v) << 4) & 0x10) | ||
186 | #define BP_UARTDBG_LCR_H_STP2 3 | ||
187 | #define BM_UARTDBG_LCR_H_STP2 0x8 | ||
188 | #define BF_UARTDBG_LCR_H_STP2(v) (((v) << 3) & 0x8) | ||
189 | #define BP_UARTDBG_LCR_H_EPS 2 | ||
190 | #define BM_UARTDBG_LCR_H_EPS 0x4 | ||
191 | #define BF_UARTDBG_LCR_H_EPS(v) (((v) << 2) & 0x4) | ||
192 | #define BP_UARTDBG_LCR_H_PEN 1 | ||
193 | #define BM_UARTDBG_LCR_H_PEN 0x2 | ||
194 | #define BF_UARTDBG_LCR_H_PEN(v) (((v) << 1) & 0x2) | ||
195 | #define BP_UARTDBG_LCR_H_BRK 0 | ||
196 | #define BM_UARTDBG_LCR_H_BRK 0x1 | ||
197 | #define BF_UARTDBG_LCR_H_BRK(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_UARTDBG_CR | ||
201 | * Address: 0x30 | ||
202 | * SCT: no | ||
203 | */ | ||
204 | #define HW_UARTDBG_CR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30)) | ||
205 | #define BP_UARTDBG_CR_UNAVAILABLE 16 | ||
206 | #define BM_UARTDBG_CR_UNAVAILABLE 0xffff0000 | ||
207 | #define BF_UARTDBG_CR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
208 | #define BP_UARTDBG_CR_CTSEN 15 | ||
209 | #define BM_UARTDBG_CR_CTSEN 0x8000 | ||
210 | #define BF_UARTDBG_CR_CTSEN(v) (((v) << 15) & 0x8000) | ||
211 | #define BP_UARTDBG_CR_RTSEN 14 | ||
212 | #define BM_UARTDBG_CR_RTSEN 0x4000 | ||
213 | #define BF_UARTDBG_CR_RTSEN(v) (((v) << 14) & 0x4000) | ||
214 | #define BP_UARTDBG_CR_OUT2 13 | ||
215 | #define BM_UARTDBG_CR_OUT2 0x2000 | ||
216 | #define BF_UARTDBG_CR_OUT2(v) (((v) << 13) & 0x2000) | ||
217 | #define BP_UARTDBG_CR_OUT1 12 | ||
218 | #define BM_UARTDBG_CR_OUT1 0x1000 | ||
219 | #define BF_UARTDBG_CR_OUT1(v) (((v) << 12) & 0x1000) | ||
220 | #define BP_UARTDBG_CR_RTS 11 | ||
221 | #define BM_UARTDBG_CR_RTS 0x800 | ||
222 | #define BF_UARTDBG_CR_RTS(v) (((v) << 11) & 0x800) | ||
223 | #define BP_UARTDBG_CR_DTR 10 | ||
224 | #define BM_UARTDBG_CR_DTR 0x400 | ||
225 | #define BF_UARTDBG_CR_DTR(v) (((v) << 10) & 0x400) | ||
226 | #define BP_UARTDBG_CR_RXE 9 | ||
227 | #define BM_UARTDBG_CR_RXE 0x200 | ||
228 | #define BF_UARTDBG_CR_RXE(v) (((v) << 9) & 0x200) | ||
229 | #define BP_UARTDBG_CR_TXE 8 | ||
230 | #define BM_UARTDBG_CR_TXE 0x100 | ||
231 | #define BF_UARTDBG_CR_TXE(v) (((v) << 8) & 0x100) | ||
232 | #define BP_UARTDBG_CR_LBE 7 | ||
233 | #define BM_UARTDBG_CR_LBE 0x80 | ||
234 | #define BF_UARTDBG_CR_LBE(v) (((v) << 7) & 0x80) | ||
235 | #define BP_UARTDBG_CR_RESERVED 3 | ||
236 | #define BM_UARTDBG_CR_RESERVED 0x78 | ||
237 | #define BF_UARTDBG_CR_RESERVED(v) (((v) << 3) & 0x78) | ||
238 | #define BP_UARTDBG_CR_SIRLP 2 | ||
239 | #define BM_UARTDBG_CR_SIRLP 0x4 | ||
240 | #define BF_UARTDBG_CR_SIRLP(v) (((v) << 2) & 0x4) | ||
241 | #define BP_UARTDBG_CR_SIREN 1 | ||
242 | #define BM_UARTDBG_CR_SIREN 0x2 | ||
243 | #define BF_UARTDBG_CR_SIREN(v) (((v) << 1) & 0x2) | ||
244 | #define BP_UARTDBG_CR_UARTEN 0 | ||
245 | #define BM_UARTDBG_CR_UARTEN 0x1 | ||
246 | #define BF_UARTDBG_CR_UARTEN(v) (((v) << 0) & 0x1) | ||
247 | |||
248 | /** | ||
249 | * Register: HW_UARTDBG_IFLS | ||
250 | * Address: 0x34 | ||
251 | * SCT: no | ||
252 | */ | ||
253 | #define HW_UARTDBG_IFLS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34)) | ||
254 | #define BP_UARTDBG_IFLS_UNAVAILABLE 16 | ||
255 | #define BM_UARTDBG_IFLS_UNAVAILABLE 0xffff0000 | ||
256 | #define BF_UARTDBG_IFLS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
257 | #define BP_UARTDBG_IFLS_RESERVED 6 | ||
258 | #define BM_UARTDBG_IFLS_RESERVED 0xffc0 | ||
259 | #define BF_UARTDBG_IFLS_RESERVED(v) (((v) << 6) & 0xffc0) | ||
260 | #define BP_UARTDBG_IFLS_RXIFLSEL 3 | ||
261 | #define BM_UARTDBG_IFLS_RXIFLSEL 0x38 | ||
262 | #define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY 0x0 | ||
263 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER 0x1 | ||
264 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF 0x2 | ||
265 | #define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS 0x3 | ||
266 | #define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
267 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5 0x5 | ||
268 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6 0x6 | ||
269 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7 0x7 | ||
270 | #define BF_UARTDBG_IFLS_RXIFLSEL(v) (((v) << 3) & 0x38) | ||
271 | #define BF_UARTDBG_IFLS_RXIFLSEL_V(v) ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38) | ||
272 | #define BP_UARTDBG_IFLS_TXIFLSEL 0 | ||
273 | #define BM_UARTDBG_IFLS_TXIFLSEL 0x7 | ||
274 | #define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY 0x0 | ||
275 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER 0x1 | ||
276 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF 0x2 | ||
277 | #define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS 0x3 | ||
278 | #define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
279 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5 0x5 | ||
280 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6 0x6 | ||
281 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7 0x7 | ||
282 | #define BF_UARTDBG_IFLS_TXIFLSEL(v) (((v) << 0) & 0x7) | ||
283 | #define BF_UARTDBG_IFLS_TXIFLSEL_V(v) ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7) | ||
284 | |||
285 | /** | ||
286 | * Register: HW_UARTDBG_IMSC | ||
287 | * Address: 0x38 | ||
288 | * SCT: no | ||
289 | */ | ||
290 | #define HW_UARTDBG_IMSC (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38)) | ||
291 | #define BP_UARTDBG_IMSC_UNAVAILABLE 16 | ||
292 | #define BM_UARTDBG_IMSC_UNAVAILABLE 0xffff0000 | ||
293 | #define BF_UARTDBG_IMSC_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
294 | #define BP_UARTDBG_IMSC_RESERVED 11 | ||
295 | #define BM_UARTDBG_IMSC_RESERVED 0xf800 | ||
296 | #define BF_UARTDBG_IMSC_RESERVED(v) (((v) << 11) & 0xf800) | ||
297 | #define BP_UARTDBG_IMSC_OEIM 10 | ||
298 | #define BM_UARTDBG_IMSC_OEIM 0x400 | ||
299 | #define BF_UARTDBG_IMSC_OEIM(v) (((v) << 10) & 0x400) | ||
300 | #define BP_UARTDBG_IMSC_BEIM 9 | ||
301 | #define BM_UARTDBG_IMSC_BEIM 0x200 | ||
302 | #define BF_UARTDBG_IMSC_BEIM(v) (((v) << 9) & 0x200) | ||
303 | #define BP_UARTDBG_IMSC_PEIM 8 | ||
304 | #define BM_UARTDBG_IMSC_PEIM 0x100 | ||
305 | #define BF_UARTDBG_IMSC_PEIM(v) (((v) << 8) & 0x100) | ||
306 | #define BP_UARTDBG_IMSC_FEIM 7 | ||
307 | #define BM_UARTDBG_IMSC_FEIM 0x80 | ||
308 | #define BF_UARTDBG_IMSC_FEIM(v) (((v) << 7) & 0x80) | ||
309 | #define BP_UARTDBG_IMSC_RTIM 6 | ||
310 | #define BM_UARTDBG_IMSC_RTIM 0x40 | ||
311 | #define BF_UARTDBG_IMSC_RTIM(v) (((v) << 6) & 0x40) | ||
312 | #define BP_UARTDBG_IMSC_TXIM 5 | ||
313 | #define BM_UARTDBG_IMSC_TXIM 0x20 | ||
314 | #define BF_UARTDBG_IMSC_TXIM(v) (((v) << 5) & 0x20) | ||
315 | #define BP_UARTDBG_IMSC_RXIM 4 | ||
316 | #define BM_UARTDBG_IMSC_RXIM 0x10 | ||
317 | #define BF_UARTDBG_IMSC_RXIM(v) (((v) << 4) & 0x10) | ||
318 | #define BP_UARTDBG_IMSC_DSRMIM 3 | ||
319 | #define BM_UARTDBG_IMSC_DSRMIM 0x8 | ||
320 | #define BF_UARTDBG_IMSC_DSRMIM(v) (((v) << 3) & 0x8) | ||
321 | #define BP_UARTDBG_IMSC_DCDMIM 2 | ||
322 | #define BM_UARTDBG_IMSC_DCDMIM 0x4 | ||
323 | #define BF_UARTDBG_IMSC_DCDMIM(v) (((v) << 2) & 0x4) | ||
324 | #define BP_UARTDBG_IMSC_CTSMIM 1 | ||
325 | #define BM_UARTDBG_IMSC_CTSMIM 0x2 | ||
326 | #define BF_UARTDBG_IMSC_CTSMIM(v) (((v) << 1) & 0x2) | ||
327 | #define BP_UARTDBG_IMSC_RIMIM 0 | ||
328 | #define BM_UARTDBG_IMSC_RIMIM 0x1 | ||
329 | #define BF_UARTDBG_IMSC_RIMIM(v) (((v) << 0) & 0x1) | ||
330 | |||
331 | /** | ||
332 | * Register: HW_UARTDBG_RIS | ||
333 | * Address: 0x3c | ||
334 | * SCT: no | ||
335 | */ | ||
336 | #define HW_UARTDBG_RIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c)) | ||
337 | #define BP_UARTDBG_RIS_UNAVAILABLE 16 | ||
338 | #define BM_UARTDBG_RIS_UNAVAILABLE 0xffff0000 | ||
339 | #define BF_UARTDBG_RIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
340 | #define BP_UARTDBG_RIS_RESERVED 11 | ||
341 | #define BM_UARTDBG_RIS_RESERVED 0xf800 | ||
342 | #define BF_UARTDBG_RIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
343 | #define BP_UARTDBG_RIS_OERIS 10 | ||
344 | #define BM_UARTDBG_RIS_OERIS 0x400 | ||
345 | #define BF_UARTDBG_RIS_OERIS(v) (((v) << 10) & 0x400) | ||
346 | #define BP_UARTDBG_RIS_BERIS 9 | ||
347 | #define BM_UARTDBG_RIS_BERIS 0x200 | ||
348 | #define BF_UARTDBG_RIS_BERIS(v) (((v) << 9) & 0x200) | ||
349 | #define BP_UARTDBG_RIS_PERIS 8 | ||
350 | #define BM_UARTDBG_RIS_PERIS 0x100 | ||
351 | #define BF_UARTDBG_RIS_PERIS(v) (((v) << 8) & 0x100) | ||
352 | #define BP_UARTDBG_RIS_FERIS 7 | ||
353 | #define BM_UARTDBG_RIS_FERIS 0x80 | ||
354 | #define BF_UARTDBG_RIS_FERIS(v) (((v) << 7) & 0x80) | ||
355 | #define BP_UARTDBG_RIS_RTRIS 6 | ||
356 | #define BM_UARTDBG_RIS_RTRIS 0x40 | ||
357 | #define BF_UARTDBG_RIS_RTRIS(v) (((v) << 6) & 0x40) | ||
358 | #define BP_UARTDBG_RIS_TXRIS 5 | ||
359 | #define BM_UARTDBG_RIS_TXRIS 0x20 | ||
360 | #define BF_UARTDBG_RIS_TXRIS(v) (((v) << 5) & 0x20) | ||
361 | #define BP_UARTDBG_RIS_RXRIS 4 | ||
362 | #define BM_UARTDBG_RIS_RXRIS 0x10 | ||
363 | #define BF_UARTDBG_RIS_RXRIS(v) (((v) << 4) & 0x10) | ||
364 | #define BP_UARTDBG_RIS_DSRRMIS 3 | ||
365 | #define BM_UARTDBG_RIS_DSRRMIS 0x8 | ||
366 | #define BF_UARTDBG_RIS_DSRRMIS(v) (((v) << 3) & 0x8) | ||
367 | #define BP_UARTDBG_RIS_DCDRMIS 2 | ||
368 | #define BM_UARTDBG_RIS_DCDRMIS 0x4 | ||
369 | #define BF_UARTDBG_RIS_DCDRMIS(v) (((v) << 2) & 0x4) | ||
370 | #define BP_UARTDBG_RIS_CTSRMIS 1 | ||
371 | #define BM_UARTDBG_RIS_CTSRMIS 0x2 | ||
372 | #define BF_UARTDBG_RIS_CTSRMIS(v) (((v) << 1) & 0x2) | ||
373 | #define BP_UARTDBG_RIS_RIRMIS 0 | ||
374 | #define BM_UARTDBG_RIS_RIRMIS 0x1 | ||
375 | #define BF_UARTDBG_RIS_RIRMIS(v) (((v) << 0) & 0x1) | ||
376 | |||
377 | /** | ||
378 | * Register: HW_UARTDBG_MIS | ||
379 | * Address: 0x40 | ||
380 | * SCT: no | ||
381 | */ | ||
382 | #define HW_UARTDBG_MIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40)) | ||
383 | #define BP_UARTDBG_MIS_UNAVAILABLE 16 | ||
384 | #define BM_UARTDBG_MIS_UNAVAILABLE 0xffff0000 | ||
385 | #define BF_UARTDBG_MIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
386 | #define BP_UARTDBG_MIS_RESERVED 11 | ||
387 | #define BM_UARTDBG_MIS_RESERVED 0xf800 | ||
388 | #define BF_UARTDBG_MIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
389 | #define BP_UARTDBG_MIS_OEMIS 10 | ||
390 | #define BM_UARTDBG_MIS_OEMIS 0x400 | ||
391 | #define BF_UARTDBG_MIS_OEMIS(v) (((v) << 10) & 0x400) | ||
392 | #define BP_UARTDBG_MIS_BEMIS 9 | ||
393 | #define BM_UARTDBG_MIS_BEMIS 0x200 | ||
394 | #define BF_UARTDBG_MIS_BEMIS(v) (((v) << 9) & 0x200) | ||
395 | #define BP_UARTDBG_MIS_PEMIS 8 | ||
396 | #define BM_UARTDBG_MIS_PEMIS 0x100 | ||
397 | #define BF_UARTDBG_MIS_PEMIS(v) (((v) << 8) & 0x100) | ||
398 | #define BP_UARTDBG_MIS_FEMIS 7 | ||
399 | #define BM_UARTDBG_MIS_FEMIS 0x80 | ||
400 | #define BF_UARTDBG_MIS_FEMIS(v) (((v) << 7) & 0x80) | ||
401 | #define BP_UARTDBG_MIS_RTMIS 6 | ||
402 | #define BM_UARTDBG_MIS_RTMIS 0x40 | ||
403 | #define BF_UARTDBG_MIS_RTMIS(v) (((v) << 6) & 0x40) | ||
404 | #define BP_UARTDBG_MIS_TXMIS 5 | ||
405 | #define BM_UARTDBG_MIS_TXMIS 0x20 | ||
406 | #define BF_UARTDBG_MIS_TXMIS(v) (((v) << 5) & 0x20) | ||
407 | #define BP_UARTDBG_MIS_RXMIS 4 | ||
408 | #define BM_UARTDBG_MIS_RXMIS 0x10 | ||
409 | #define BF_UARTDBG_MIS_RXMIS(v) (((v) << 4) & 0x10) | ||
410 | #define BP_UARTDBG_MIS_DSRMMIS 3 | ||
411 | #define BM_UARTDBG_MIS_DSRMMIS 0x8 | ||
412 | #define BF_UARTDBG_MIS_DSRMMIS(v) (((v) << 3) & 0x8) | ||
413 | #define BP_UARTDBG_MIS_DCDMMIS 2 | ||
414 | #define BM_UARTDBG_MIS_DCDMMIS 0x4 | ||
415 | #define BF_UARTDBG_MIS_DCDMMIS(v) (((v) << 2) & 0x4) | ||
416 | #define BP_UARTDBG_MIS_CTSMMIS 1 | ||
417 | #define BM_UARTDBG_MIS_CTSMMIS 0x2 | ||
418 | #define BF_UARTDBG_MIS_CTSMMIS(v) (((v) << 1) & 0x2) | ||
419 | #define BP_UARTDBG_MIS_RIMMIS 0 | ||
420 | #define BM_UARTDBG_MIS_RIMMIS 0x1 | ||
421 | #define BF_UARTDBG_MIS_RIMMIS(v) (((v) << 0) & 0x1) | ||
422 | |||
423 | /** | ||
424 | * Register: HW_UARTDBG_ICR | ||
425 | * Address: 0x44 | ||
426 | * SCT: no | ||
427 | */ | ||
428 | #define HW_UARTDBG_ICR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44)) | ||
429 | #define BP_UARTDBG_ICR_UNAVAILABLE 16 | ||
430 | #define BM_UARTDBG_ICR_UNAVAILABLE 0xffff0000 | ||
431 | #define BF_UARTDBG_ICR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
432 | #define BP_UARTDBG_ICR_RESERVED 11 | ||
433 | #define BM_UARTDBG_ICR_RESERVED 0xf800 | ||
434 | #define BF_UARTDBG_ICR_RESERVED(v) (((v) << 11) & 0xf800) | ||
435 | #define BP_UARTDBG_ICR_OEIC 10 | ||
436 | #define BM_UARTDBG_ICR_OEIC 0x400 | ||
437 | #define BF_UARTDBG_ICR_OEIC(v) (((v) << 10) & 0x400) | ||
438 | #define BP_UARTDBG_ICR_BEIC 9 | ||
439 | #define BM_UARTDBG_ICR_BEIC 0x200 | ||
440 | #define BF_UARTDBG_ICR_BEIC(v) (((v) << 9) & 0x200) | ||
441 | #define BP_UARTDBG_ICR_PEIC 8 | ||
442 | #define BM_UARTDBG_ICR_PEIC 0x100 | ||
443 | #define BF_UARTDBG_ICR_PEIC(v) (((v) << 8) & 0x100) | ||
444 | #define BP_UARTDBG_ICR_FEIC 7 | ||
445 | #define BM_UARTDBG_ICR_FEIC 0x80 | ||
446 | #define BF_UARTDBG_ICR_FEIC(v) (((v) << 7) & 0x80) | ||
447 | #define BP_UARTDBG_ICR_RTIC 6 | ||
448 | #define BM_UARTDBG_ICR_RTIC 0x40 | ||
449 | #define BF_UARTDBG_ICR_RTIC(v) (((v) << 6) & 0x40) | ||
450 | #define BP_UARTDBG_ICR_TXIC 5 | ||
451 | #define BM_UARTDBG_ICR_TXIC 0x20 | ||
452 | #define BF_UARTDBG_ICR_TXIC(v) (((v) << 5) & 0x20) | ||
453 | #define BP_UARTDBG_ICR_RXIC 4 | ||
454 | #define BM_UARTDBG_ICR_RXIC 0x10 | ||
455 | #define BF_UARTDBG_ICR_RXIC(v) (((v) << 4) & 0x10) | ||
456 | #define BP_UARTDBG_ICR_DSRMIC 3 | ||
457 | #define BM_UARTDBG_ICR_DSRMIC 0x8 | ||
458 | #define BF_UARTDBG_ICR_DSRMIC(v) (((v) << 3) & 0x8) | ||
459 | #define BP_UARTDBG_ICR_DCDMIC 2 | ||
460 | #define BM_UARTDBG_ICR_DCDMIC 0x4 | ||
461 | #define BF_UARTDBG_ICR_DCDMIC(v) (((v) << 2) & 0x4) | ||
462 | #define BP_UARTDBG_ICR_CTSMIC 1 | ||
463 | #define BM_UARTDBG_ICR_CTSMIC 0x2 | ||
464 | #define BF_UARTDBG_ICR_CTSMIC(v) (((v) << 1) & 0x2) | ||
465 | #define BP_UARTDBG_ICR_RIMIC 0 | ||
466 | #define BM_UARTDBG_ICR_RIMIC 0x1 | ||
467 | #define BF_UARTDBG_ICR_RIMIC(v) (((v) << 0) & 0x1) | ||
468 | |||
469 | /** | ||
470 | * Register: HW_UARTDBG_DMACR | ||
471 | * Address: 0x48 | ||
472 | * SCT: no | ||
473 | */ | ||
474 | #define HW_UARTDBG_DMACR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48)) | ||
475 | #define BP_UARTDBG_DMACR_UNAVAILABLE 16 | ||
476 | #define BM_UARTDBG_DMACR_UNAVAILABLE 0xffff0000 | ||
477 | #define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
478 | #define BP_UARTDBG_DMACR_RESERVED 3 | ||
479 | #define BM_UARTDBG_DMACR_RESERVED 0xfff8 | ||
480 | #define BF_UARTDBG_DMACR_RESERVED(v) (((v) << 3) & 0xfff8) | ||
481 | #define BP_UARTDBG_DMACR_DMAONERR 2 | ||
482 | #define BM_UARTDBG_DMACR_DMAONERR 0x4 | ||
483 | #define BF_UARTDBG_DMACR_DMAONERR(v) (((v) << 2) & 0x4) | ||
484 | #define BP_UARTDBG_DMACR_TXDMAE 1 | ||
485 | #define BM_UARTDBG_DMACR_TXDMAE 0x2 | ||
486 | #define BF_UARTDBG_DMACR_TXDMAE(v) (((v) << 1) & 0x2) | ||
487 | #define BP_UARTDBG_DMACR_RXDMAE 0 | ||
488 | #define BM_UARTDBG_DMACR_RXDMAE 0x1 | ||
489 | #define BF_UARTDBG_DMACR_RXDMAE(v) (((v) << 0) & 0x1) | ||
490 | |||
491 | #endif /* __HEADERGEN__STMP3700__UARTDBG__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h new file mode 100644 index 0000000000..d621bac1e9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h | |||
@@ -0,0 +1,877 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__USBCTRL__H__ | ||
24 | #define __HEADERGEN__STMP3700__USBCTRL__H__ | ||
25 | |||
26 | #define REGS_USBCTRL_BASE (0x80080000) | ||
27 | |||
28 | #define REGS_USBCTRL_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_USBCTRL_ID | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_USBCTRL_ID (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x0)) | ||
36 | #define BP_USBCTRL_ID_REV 16 | ||
37 | #define BM_USBCTRL_ID_REV 0xff0000 | ||
38 | #define BF_USBCTRL_ID_REV(v) (((v) << 16) & 0xff0000) | ||
39 | #define BP_USBCTRL_ID_ID_N 8 | ||
40 | #define BM_USBCTRL_ID_ID_N 0xff00 | ||
41 | #define BF_USBCTRL_ID_ID_N(v) (((v) << 8) & 0xff00) | ||
42 | #define BP_USBCTRL_ID_ID 0 | ||
43 | #define BM_USBCTRL_ID_ID 0xff | ||
44 | #define BF_USBCTRL_ID_ID(v) (((v) << 0) & 0xff) | ||
45 | |||
46 | /** | ||
47 | * Register: HW_USBCTRL_GENERAL | ||
48 | * Address: 0x4 | ||
49 | * SCT: no | ||
50 | */ | ||
51 | #define HW_USBCTRL_GENERAL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x4)) | ||
52 | #define BP_USBCTRL_GENERAL_SM 9 | ||
53 | #define BM_USBCTRL_GENERAL_SM 0x200 | ||
54 | #define BF_USBCTRL_GENERAL_SM(v) (((v) << 9) & 0x200) | ||
55 | #define BP_USBCTRL_GENERAL_PHYM 6 | ||
56 | #define BM_USBCTRL_GENERAL_PHYM 0x1c0 | ||
57 | #define BF_USBCTRL_GENERAL_PHYM(v) (((v) << 6) & 0x1c0) | ||
58 | #define BP_USBCTRL_GENERAL_PHYW 4 | ||
59 | #define BM_USBCTRL_GENERAL_PHYW 0x30 | ||
60 | #define BF_USBCTRL_GENERAL_PHYW(v) (((v) << 4) & 0x30) | ||
61 | #define BP_USBCTRL_GENERAL_BWT 3 | ||
62 | #define BM_USBCTRL_GENERAL_BWT 0x8 | ||
63 | #define BF_USBCTRL_GENERAL_BWT(v) (((v) << 3) & 0x8) | ||
64 | #define BP_USBCTRL_GENERAL_CLKC 1 | ||
65 | #define BM_USBCTRL_GENERAL_CLKC 0x6 | ||
66 | #define BF_USBCTRL_GENERAL_CLKC(v) (((v) << 1) & 0x6) | ||
67 | #define BP_USBCTRL_GENERAL_RT 0 | ||
68 | #define BM_USBCTRL_GENERAL_RT 0x1 | ||
69 | #define BF_USBCTRL_GENERAL_RT(v) (((v) << 0) & 0x1) | ||
70 | |||
71 | /** | ||
72 | * Register: HW_USBCTRL_HOST | ||
73 | * Address: 0x8 | ||
74 | * SCT: no | ||
75 | */ | ||
76 | #define HW_USBCTRL_HOST (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8)) | ||
77 | #define BP_USBCTRL_HOST_TTPER 24 | ||
78 | #define BM_USBCTRL_HOST_TTPER 0xff000000 | ||
79 | #define BF_USBCTRL_HOST_TTPER(v) (((v) << 24) & 0xff000000) | ||
80 | #define BP_USBCTRL_HOST_TTASY 16 | ||
81 | #define BM_USBCTRL_HOST_TTASY 0xff0000 | ||
82 | #define BF_USBCTRL_HOST_TTASY(v) (((v) << 16) & 0xff0000) | ||
83 | #define BP_USBCTRL_HOST_NPORT 1 | ||
84 | #define BM_USBCTRL_HOST_NPORT 0xe | ||
85 | #define BF_USBCTRL_HOST_NPORT(v) (((v) << 1) & 0xe) | ||
86 | #define BP_USBCTRL_HOST_HC 0 | ||
87 | #define BM_USBCTRL_HOST_HC 0x1 | ||
88 | #define BF_USBCTRL_HOST_HC(v) (((v) << 0) & 0x1) | ||
89 | |||
90 | /** | ||
91 | * Register: HW_USBCTRL_DEVICE | ||
92 | * Address: 0xc | ||
93 | * SCT: no | ||
94 | */ | ||
95 | #define HW_USBCTRL_DEVICE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0xc)) | ||
96 | #define BP_USBCTRL_DEVICE_DEVEP 1 | ||
97 | #define BM_USBCTRL_DEVICE_DEVEP 0x3e | ||
98 | #define BF_USBCTRL_DEVICE_DEVEP(v) (((v) << 1) & 0x3e) | ||
99 | #define BP_USBCTRL_DEVICE_DC 0 | ||
100 | #define BM_USBCTRL_DEVICE_DC 0x1 | ||
101 | #define BF_USBCTRL_DEVICE_DC(v) (((v) << 0) & 0x1) | ||
102 | |||
103 | /** | ||
104 | * Register: HW_USBCTRL_TXBUF | ||
105 | * Address: 0x10 | ||
106 | * SCT: no | ||
107 | */ | ||
108 | #define HW_USBCTRL_TXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x10)) | ||
109 | #define BP_USBCTRL_TXBUF_TXLCR 31 | ||
110 | #define BM_USBCTRL_TXBUF_TXLCR 0x80000000 | ||
111 | #define BF_USBCTRL_TXBUF_TXLCR(v) (((v) << 31) & 0x80000000) | ||
112 | #define BP_USBCTRL_TXBUF_TXCHANADD 16 | ||
113 | #define BM_USBCTRL_TXBUF_TXCHANADD 0xff0000 | ||
114 | #define BF_USBCTRL_TXBUF_TXCHANADD(v) (((v) << 16) & 0xff0000) | ||
115 | #define BP_USBCTRL_TXBUF_TXADD 8 | ||
116 | #define BM_USBCTRL_TXBUF_TXADD 0xff00 | ||
117 | #define BF_USBCTRL_TXBUF_TXADD(v) (((v) << 8) & 0xff00) | ||
118 | #define BP_USBCTRL_TXBUF_TXBURST 0 | ||
119 | #define BM_USBCTRL_TXBUF_TXBURST 0xff | ||
120 | #define BF_USBCTRL_TXBUF_TXBURST(v) (((v) << 0) & 0xff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_USBCTRL_RXBUF | ||
124 | * Address: 0x14 | ||
125 | * SCT: no | ||
126 | */ | ||
127 | #define HW_USBCTRL_RXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14)) | ||
128 | #define BP_USBCTRL_RXBUF_RXADD 8 | ||
129 | #define BM_USBCTRL_RXBUF_RXADD 0xff00 | ||
130 | #define BF_USBCTRL_RXBUF_RXADD(v) (((v) << 8) & 0xff00) | ||
131 | #define BP_USBCTRL_RXBUF_RXBURST 0 | ||
132 | #define BM_USBCTRL_RXBUF_RXBURST 0xff | ||
133 | #define BF_USBCTRL_RXBUF_RXBURST(v) (((v) << 0) & 0xff) | ||
134 | |||
135 | /** | ||
136 | * Register: HW_USBCTRL_TTTXBUF | ||
137 | * Address: 0x18 | ||
138 | * SCT: no | ||
139 | */ | ||
140 | #define HW_USBCTRL_TTTXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x18)) | ||
141 | #define BP_USBCTRL_TTTXBUF_TTTXBUF 0 | ||
142 | #define BM_USBCTRL_TTTXBUF_TTTXBUF 0xffffffff | ||
143 | #define BF_USBCTRL_TTTXBUF_TTTXBUF(v) (((v) << 0) & 0xffffffff) | ||
144 | |||
145 | /** | ||
146 | * Register: HW_USBCTRL_TTRXBUF | ||
147 | * Address: 0x1c | ||
148 | * SCT: no | ||
149 | */ | ||
150 | #define HW_USBCTRL_TTRXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c)) | ||
151 | #define BP_USBCTRL_TTRXBUF_TTRXBUF 0 | ||
152 | #define BM_USBCTRL_TTRXBUF_TTRXBUF 0xffffffff | ||
153 | #define BF_USBCTRL_TTRXBUF_TTRXBUF(v) (((v) << 0) & 0xffffffff) | ||
154 | |||
155 | /** | ||
156 | * Register: HW_USBCTRL_CAPLENGTH | ||
157 | * Address: 0x100 | ||
158 | * SCT: no | ||
159 | */ | ||
160 | #define HW_USBCTRL_CAPLENGTH (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x100)) | ||
161 | #define BP_USBCTRL_CAPLENGTH_HCIVER 16 | ||
162 | #define BM_USBCTRL_CAPLENGTH_HCIVER 0xffff0000 | ||
163 | #define BF_USBCTRL_CAPLENGTH_HCIVER(v) (((v) << 16) & 0xffff0000) | ||
164 | #define BP_USBCTRL_CAPLENGTH_LENGTH 0 | ||
165 | #define BM_USBCTRL_CAPLENGTH_LENGTH 0xff | ||
166 | #define BF_USBCTRL_CAPLENGTH_LENGTH(v) (((v) << 0) & 0xff) | ||
167 | |||
168 | /** | ||
169 | * Register: HW_USBCTRL_HCSPARAMS | ||
170 | * Address: 0x104 | ||
171 | * SCT: no | ||
172 | */ | ||
173 | #define HW_USBCTRL_HCSPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x104)) | ||
174 | #define BP_USBCTRL_HCSPARAMS_NPORTS 0 | ||
175 | #define BM_USBCTRL_HCSPARAMS_NPORTS 0xf | ||
176 | #define BF_USBCTRL_HCSPARAMS_NPORTS(v) (((v) << 0) & 0xf) | ||
177 | #define BP_USBCTRL_HCSPARAMS_PPC 4 | ||
178 | #define BM_USBCTRL_HCSPARAMS_PPC 0x10 | ||
179 | #define BF_USBCTRL_HCSPARAMS_PPC(v) (((v) << 4) & 0x10) | ||
180 | #define BP_USBCTRL_HCSPARAMS_NPCC 8 | ||
181 | #define BM_USBCTRL_HCSPARAMS_NPCC 0xf00 | ||
182 | #define BF_USBCTRL_HCSPARAMS_NPCC(v) (((v) << 8) & 0xf00) | ||
183 | #define BP_USBCTRL_HCSPARAMS_NCC 12 | ||
184 | #define BM_USBCTRL_HCSPARAMS_NCC 0xf000 | ||
185 | #define BF_USBCTRL_HCSPARAMS_NCC(v) (((v) << 12) & 0xf000) | ||
186 | #define BP_USBCTRL_HCSPARAMS_PI 16 | ||
187 | #define BM_USBCTRL_HCSPARAMS_PI 0x10000 | ||
188 | #define BF_USBCTRL_HCSPARAMS_PI(v) (((v) << 16) & 0x10000) | ||
189 | #define BP_USBCTRL_HCSPARAMS_NPTT 20 | ||
190 | #define BM_USBCTRL_HCSPARAMS_NPTT 0xf00000 | ||
191 | #define BF_USBCTRL_HCSPARAMS_NPTT(v) (((v) << 20) & 0xf00000) | ||
192 | #define BP_USBCTRL_HCSPARAMS_NTT 24 | ||
193 | #define BM_USBCTRL_HCSPARAMS_NTT 0xf000000 | ||
194 | #define BF_USBCTRL_HCSPARAMS_NTT(v) (((v) << 24) & 0xf000000) | ||
195 | |||
196 | /** | ||
197 | * Register: HW_USBCTRL_HCCPARAMS | ||
198 | * Address: 0x108 | ||
199 | * SCT: no | ||
200 | */ | ||
201 | #define HW_USBCTRL_HCCPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x108)) | ||
202 | #define BP_USBCTRL_HCCPARAMS_ADDR64BITCAP 0 | ||
203 | #define BM_USBCTRL_HCCPARAMS_ADDR64BITCAP 0x1 | ||
204 | #define BF_USBCTRL_HCCPARAMS_ADDR64BITCAP(v) (((v) << 0) & 0x1) | ||
205 | #define BP_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG 1 | ||
206 | #define BM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG 0x2 | ||
207 | #define BF_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG(v) (((v) << 1) & 0x2) | ||
208 | #define BP_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP 2 | ||
209 | #define BM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP 0x4 | ||
210 | #define BF_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP(v) (((v) << 2) & 0x4) | ||
211 | #define BP_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD 8 | ||
212 | #define BM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD 0xff00 | ||
213 | #define BF_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD(v) (((v) << 8) & 0xff00) | ||
214 | |||
215 | /** | ||
216 | * Register: HW_USBCTRL_DCIVERSION | ||
217 | * Address: 0x120 | ||
218 | * SCT: no | ||
219 | */ | ||
220 | #define HW_USBCTRL_DCIVERSION (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x120)) | ||
221 | #define BP_USBCTRL_DCIVERSION_DCIVER 0 | ||
222 | #define BM_USBCTRL_DCIVERSION_DCIVER 0xffff | ||
223 | #define BF_USBCTRL_DCIVERSION_DCIVER(v) (((v) << 0) & 0xffff) | ||
224 | |||
225 | /** | ||
226 | * Register: HW_USBCTRL_DCCPARAMS | ||
227 | * Address: 0x124 | ||
228 | * SCT: no | ||
229 | */ | ||
230 | #define HW_USBCTRL_DCCPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x124)) | ||
231 | #define BP_USBCTRL_DCCPARAMS_HC 8 | ||
232 | #define BM_USBCTRL_DCCPARAMS_HC 0x100 | ||
233 | #define BF_USBCTRL_DCCPARAMS_HC(v) (((v) << 8) & 0x100) | ||
234 | #define BP_USBCTRL_DCCPARAMS_DC 7 | ||
235 | #define BM_USBCTRL_DCCPARAMS_DC 0x80 | ||
236 | #define BF_USBCTRL_DCCPARAMS_DC(v) (((v) << 7) & 0x80) | ||
237 | #define BP_USBCTRL_DCCPARAMS_DEN 0 | ||
238 | #define BM_USBCTRL_DCCPARAMS_DEN 0x1f | ||
239 | #define BF_USBCTRL_DCCPARAMS_DEN(v) (((v) << 0) & 0x1f) | ||
240 | |||
241 | /** | ||
242 | * Register: HW_USBCTRL_USBCMD | ||
243 | * Address: 0x140 | ||
244 | * SCT: no | ||
245 | */ | ||
246 | #define HW_USBCTRL_USBCMD (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x140)) | ||
247 | #define BP_USBCTRL_USBCMD_RS 0 | ||
248 | #define BM_USBCTRL_USBCMD_RS 0x1 | ||
249 | #define BF_USBCTRL_USBCMD_RS(v) (((v) << 0) & 0x1) | ||
250 | #define BP_USBCTRL_USBCMD_RST 1 | ||
251 | #define BM_USBCTRL_USBCMD_RST 0x2 | ||
252 | #define BF_USBCTRL_USBCMD_RST(v) (((v) << 1) & 0x2) | ||
253 | #define BP_USBCTRL_USBCMD_FS0 2 | ||
254 | #define BM_USBCTRL_USBCMD_FS0 0x4 | ||
255 | #define BF_USBCTRL_USBCMD_FS0(v) (((v) << 2) & 0x4) | ||
256 | #define BP_USBCTRL_USBCMD_FS1 3 | ||
257 | #define BM_USBCTRL_USBCMD_FS1 0x8 | ||
258 | #define BF_USBCTRL_USBCMD_FS1(v) (((v) << 3) & 0x8) | ||
259 | #define BP_USBCTRL_USBCMD_PSE 4 | ||
260 | #define BM_USBCTRL_USBCMD_PSE 0x10 | ||
261 | #define BF_USBCTRL_USBCMD_PSE(v) (((v) << 4) & 0x10) | ||
262 | #define BP_USBCTRL_USBCMD_ASE 5 | ||
263 | #define BM_USBCTRL_USBCMD_ASE 0x20 | ||
264 | #define BF_USBCTRL_USBCMD_ASE(v) (((v) << 5) & 0x20) | ||
265 | #define BP_USBCTRL_USBCMD_IAA 6 | ||
266 | #define BM_USBCTRL_USBCMD_IAA 0x40 | ||
267 | #define BF_USBCTRL_USBCMD_IAA(v) (((v) << 6) & 0x40) | ||
268 | #define BP_USBCTRL_USBCMD_LR 7 | ||
269 | #define BM_USBCTRL_USBCMD_LR 0x80 | ||
270 | #define BF_USBCTRL_USBCMD_LR(v) (((v) << 7) & 0x80) | ||
271 | #define BP_USBCTRL_USBCMD_ASP0 8 | ||
272 | #define BM_USBCTRL_USBCMD_ASP0 0x100 | ||
273 | #define BF_USBCTRL_USBCMD_ASP0(v) (((v) << 8) & 0x100) | ||
274 | #define BP_USBCTRL_USBCMD_ASP1 9 | ||
275 | #define BM_USBCTRL_USBCMD_ASP1 0x200 | ||
276 | #define BF_USBCTRL_USBCMD_ASP1(v) (((v) << 9) & 0x200) | ||
277 | #define BP_USBCTRL_USBCMD_ASPE 11 | ||
278 | #define BM_USBCTRL_USBCMD_ASPE 0x800 | ||
279 | #define BF_USBCTRL_USBCMD_ASPE(v) (((v) << 11) & 0x800) | ||
280 | #define BP_USBCTRL_USBCMD_FS2 15 | ||
281 | #define BM_USBCTRL_USBCMD_FS2 0x8000 | ||
282 | #define BF_USBCTRL_USBCMD_FS2(v) (((v) << 15) & 0x8000) | ||
283 | #define BP_USBCTRL_USBCMD_ITC 16 | ||
284 | #define BM_USBCTRL_USBCMD_ITC 0xff0000 | ||
285 | #define BF_USBCTRL_USBCMD_ITC(v) (((v) << 16) & 0xff0000) | ||
286 | |||
287 | /** | ||
288 | * Register: HW_USBCTRL_USBSTS | ||
289 | * Address: 0x144 | ||
290 | * SCT: no | ||
291 | */ | ||
292 | #define HW_USBCTRL_USBSTS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x144)) | ||
293 | #define BP_USBCTRL_USBSTS_UI 0 | ||
294 | #define BM_USBCTRL_USBSTS_UI 0x1 | ||
295 | #define BF_USBCTRL_USBSTS_UI(v) (((v) << 0) & 0x1) | ||
296 | #define BP_USBCTRL_USBSTS_UEI 1 | ||
297 | #define BM_USBCTRL_USBSTS_UEI 0x2 | ||
298 | #define BF_USBCTRL_USBSTS_UEI(v) (((v) << 1) & 0x2) | ||
299 | #define BP_USBCTRL_USBSTS_PCI 2 | ||
300 | #define BM_USBCTRL_USBSTS_PCI 0x4 | ||
301 | #define BF_USBCTRL_USBSTS_PCI(v) (((v) << 2) & 0x4) | ||
302 | #define BP_USBCTRL_USBSTS_FRI 3 | ||
303 | #define BM_USBCTRL_USBSTS_FRI 0x8 | ||
304 | #define BF_USBCTRL_USBSTS_FRI(v) (((v) << 3) & 0x8) | ||
305 | #define BP_USBCTRL_USBSTS_SEI 4 | ||
306 | #define BM_USBCTRL_USBSTS_SEI 0x10 | ||
307 | #define BF_USBCTRL_USBSTS_SEI(v) (((v) << 4) & 0x10) | ||
308 | #define BP_USBCTRL_USBSTS_AAI 5 | ||
309 | #define BM_USBCTRL_USBSTS_AAI 0x20 | ||
310 | #define BF_USBCTRL_USBSTS_AAI(v) (((v) << 5) & 0x20) | ||
311 | #define BP_USBCTRL_USBSTS_URI 6 | ||
312 | #define BM_USBCTRL_USBSTS_URI 0x40 | ||
313 | #define BF_USBCTRL_USBSTS_URI(v) (((v) << 6) & 0x40) | ||
314 | #define BP_USBCTRL_USBSTS_SRI 7 | ||
315 | #define BM_USBCTRL_USBSTS_SRI 0x80 | ||
316 | #define BF_USBCTRL_USBSTS_SRI(v) (((v) << 7) & 0x80) | ||
317 | #define BP_USBCTRL_USBSTS_SLI 8 | ||
318 | #define BM_USBCTRL_USBSTS_SLI 0x100 | ||
319 | #define BF_USBCTRL_USBSTS_SLI(v) (((v) << 8) & 0x100) | ||
320 | #define BP_USBCTRL_USBSTS_ULPII 10 | ||
321 | #define BM_USBCTRL_USBSTS_ULPII 0x400 | ||
322 | #define BF_USBCTRL_USBSTS_ULPII(v) (((v) << 10) & 0x400) | ||
323 | #define BP_USBCTRL_USBSTS_HCH 12 | ||
324 | #define BM_USBCTRL_USBSTS_HCH 0x1000 | ||
325 | #define BF_USBCTRL_USBSTS_HCH(v) (((v) << 12) & 0x1000) | ||
326 | #define BP_USBCTRL_USBSTS_RCL 13 | ||
327 | #define BM_USBCTRL_USBSTS_RCL 0x2000 | ||
328 | #define BF_USBCTRL_USBSTS_RCL(v) (((v) << 13) & 0x2000) | ||
329 | #define BP_USBCTRL_USBSTS_PS 14 | ||
330 | #define BM_USBCTRL_USBSTS_PS 0x4000 | ||
331 | #define BF_USBCTRL_USBSTS_PS(v) (((v) << 14) & 0x4000) | ||
332 | #define BP_USBCTRL_USBSTS_AS 15 | ||
333 | #define BM_USBCTRL_USBSTS_AS 0x8000 | ||
334 | #define BF_USBCTRL_USBSTS_AS(v) (((v) << 15) & 0x8000) | ||
335 | #define BP_USBCTRL_USBSTS_NAKI 16 | ||
336 | #define BM_USBCTRL_USBSTS_NAKI 0x10000 | ||
337 | #define BF_USBCTRL_USBSTS_NAKI(v) (((v) << 16) & 0x10000) | ||
338 | |||
339 | /** | ||
340 | * Register: HW_USBCTRL_USBINTR | ||
341 | * Address: 0x148 | ||
342 | * SCT: no | ||
343 | */ | ||
344 | #define HW_USBCTRL_USBINTR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x148)) | ||
345 | #define BP_USBCTRL_USBINTR_UE 0 | ||
346 | #define BM_USBCTRL_USBINTR_UE 0x1 | ||
347 | #define BF_USBCTRL_USBINTR_UE(v) (((v) << 0) & 0x1) | ||
348 | #define BP_USBCTRL_USBINTR_UEE 1 | ||
349 | #define BM_USBCTRL_USBINTR_UEE 0x2 | ||
350 | #define BF_USBCTRL_USBINTR_UEE(v) (((v) << 1) & 0x2) | ||
351 | #define BP_USBCTRL_USBINTR_PCE 2 | ||
352 | #define BM_USBCTRL_USBINTR_PCE 0x4 | ||
353 | #define BF_USBCTRL_USBINTR_PCE(v) (((v) << 2) & 0x4) | ||
354 | #define BP_USBCTRL_USBINTR_FRE 3 | ||
355 | #define BM_USBCTRL_USBINTR_FRE 0x8 | ||
356 | #define BF_USBCTRL_USBINTR_FRE(v) (((v) << 3) & 0x8) | ||
357 | #define BP_USBCTRL_USBINTR_SEE 4 | ||
358 | #define BM_USBCTRL_USBINTR_SEE 0x10 | ||
359 | #define BF_USBCTRL_USBINTR_SEE(v) (((v) << 4) & 0x10) | ||
360 | #define BP_USBCTRL_USBINTR_AAE 5 | ||
361 | #define BM_USBCTRL_USBINTR_AAE 0x20 | ||
362 | #define BF_USBCTRL_USBINTR_AAE(v) (((v) << 5) & 0x20) | ||
363 | #define BP_USBCTRL_USBINTR_URE 6 | ||
364 | #define BM_USBCTRL_USBINTR_URE 0x40 | ||
365 | #define BF_USBCTRL_USBINTR_URE(v) (((v) << 6) & 0x40) | ||
366 | #define BP_USBCTRL_USBINTR_SRE 7 | ||
367 | #define BM_USBCTRL_USBINTR_SRE 0x80 | ||
368 | #define BF_USBCTRL_USBINTR_SRE(v) (((v) << 7) & 0x80) | ||
369 | #define BP_USBCTRL_USBINTR_SLE 8 | ||
370 | #define BM_USBCTRL_USBINTR_SLE 0x100 | ||
371 | #define BF_USBCTRL_USBINTR_SLE(v) (((v) << 8) & 0x100) | ||
372 | #define BP_USBCTRL_USBINTR_ULPIE 10 | ||
373 | #define BM_USBCTRL_USBINTR_ULPIE 0x400 | ||
374 | #define BF_USBCTRL_USBINTR_ULPIE(v) (((v) << 10) & 0x400) | ||
375 | #define BP_USBCTRL_USBINTR_NAKE 16 | ||
376 | #define BM_USBCTRL_USBINTR_NAKE 0x10000 | ||
377 | #define BF_USBCTRL_USBINTR_NAKE(v) (((v) << 16) & 0x10000) | ||
378 | |||
379 | /** | ||
380 | * Register: HW_USBCTRL_FRINDEX | ||
381 | * Address: 0x14c | ||
382 | * SCT: no | ||
383 | */ | ||
384 | #define HW_USBCTRL_FRINDEX (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14c)) | ||
385 | #define BP_USBCTRL_FRINDEX_LISTINDEX 3 | ||
386 | #define BM_USBCTRL_FRINDEX_LISTINDEX 0x3ff8 | ||
387 | #define BF_USBCTRL_FRINDEX_LISTINDEX(v) (((v) << 3) & 0x3ff8) | ||
388 | #define BP_USBCTRL_FRINDEX_UINDEX 0 | ||
389 | #define BM_USBCTRL_FRINDEX_UINDEX 0x7 | ||
390 | #define BF_USBCTRL_FRINDEX_UINDEX(v) (((v) << 0) & 0x7) | ||
391 | |||
392 | /** | ||
393 | * Register: HW_USBCTRL_CTRLDSSEGMENT | ||
394 | * Address: 0x150 | ||
395 | * SCT: no | ||
396 | */ | ||
397 | #define HW_USBCTRL_CTRLDSSEGMENT (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x150)) | ||
398 | #define BP_USBCTRL_CTRLDSSEGMENT_EMPTY 0 | ||
399 | #define BM_USBCTRL_CTRLDSSEGMENT_EMPTY 0xffffffff | ||
400 | #define BF_USBCTRL_CTRLDSSEGMENT_EMPTY(v) (((v) << 0) & 0xffffffff) | ||
401 | |||
402 | /** | ||
403 | * Register: HW_USBCTRL_PERIODICLISTBASE | ||
404 | * Address: 0x154 | ||
405 | * SCT: no | ||
406 | */ | ||
407 | #define HW_USBCTRL_PERIODICLISTBASE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154)) | ||
408 | #define BP_USBCTRL_PERIODICLISTBASE_BASEADDR 12 | ||
409 | #define BM_USBCTRL_PERIODICLISTBASE_BASEADDR 0xfffff000 | ||
410 | #define BF_USBCTRL_PERIODICLISTBASE_BASEADDR(v) (((v) << 12) & 0xfffff000) | ||
411 | |||
412 | /** | ||
413 | * Register: HW_USBCTRL_ASYNCLISTADDR | ||
414 | * Address: 0x158 | ||
415 | * SCT: no | ||
416 | */ | ||
417 | #define HW_USBCTRL_ASYNCLISTADDR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158)) | ||
418 | #define BP_USBCTRL_ASYNCLISTADDR_ASYBASE 5 | ||
419 | #define BM_USBCTRL_ASYNCLISTADDR_ASYBASE 0xffffffe0 | ||
420 | #define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) (((v) << 5) & 0xffffffe0) | ||
421 | |||
422 | /** | ||
423 | * Register: HW_USBCTRL_TTCTRL | ||
424 | * Address: 0x15c | ||
425 | * SCT: no | ||
426 | */ | ||
427 | #define HW_USBCTRL_TTCTRL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x15c)) | ||
428 | #define BP_USBCTRL_TTCTRL_TTHA 24 | ||
429 | #define BM_USBCTRL_TTCTRL_TTHA 0x7f000000 | ||
430 | #define BF_USBCTRL_TTCTRL_TTHA(v) (((v) << 24) & 0x7f000000) | ||
431 | |||
432 | /** | ||
433 | * Register: HW_USBCTRL_BURSTSIZE | ||
434 | * Address: 0x160 | ||
435 | * SCT: no | ||
436 | */ | ||
437 | #define HW_USBCTRL_BURSTSIZE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x160)) | ||
438 | #define BP_USBCTRL_BURSTSIZE_TX 8 | ||
439 | #define BM_USBCTRL_BURSTSIZE_TX 0xff00 | ||
440 | #define BF_USBCTRL_BURSTSIZE_TX(v) (((v) << 8) & 0xff00) | ||
441 | #define BP_USBCTRL_BURSTSIZE_RX 0 | ||
442 | #define BM_USBCTRL_BURSTSIZE_RX 0xff | ||
443 | #define BF_USBCTRL_BURSTSIZE_RX(v) (((v) << 0) & 0xff) | ||
444 | |||
445 | /** | ||
446 | * Register: HW_USBCTRL_TXFILLTUNING | ||
447 | * Address: 0x164 | ||
448 | * SCT: no | ||
449 | */ | ||
450 | #define HW_USBCTRL_TXFILLTUNING (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x164)) | ||
451 | #define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES 16 | ||
452 | #define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES 0x3f0000 | ||
453 | #define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v) (((v) << 16) & 0x3f0000) | ||
454 | #define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH 8 | ||
455 | #define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH 0x1f00 | ||
456 | #define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v) (((v) << 8) & 0x1f00) | ||
457 | #define BP_USBCTRL_TXFILLTUNING_TXSCHOH 0 | ||
458 | #define BM_USBCTRL_TXFILLTUNING_TXSCHOH 0xff | ||
459 | #define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v) (((v) << 0) & 0xff) | ||
460 | |||
461 | /** | ||
462 | * Register: HW_USBCTRL_TXTTFILLTUNING | ||
463 | * Address: 0x168 | ||
464 | * SCT: no | ||
465 | */ | ||
466 | #define HW_USBCTRL_TXTTFILLTUNING (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x168)) | ||
467 | #define BP_USBCTRL_TXTTFILLTUNING_EMPTY 0 | ||
468 | #define BM_USBCTRL_TXTTFILLTUNING_EMPTY 0xffffffff | ||
469 | #define BF_USBCTRL_TXTTFILLTUNING_EMPTY(v) (((v) << 0) & 0xffffffff) | ||
470 | |||
471 | /** | ||
472 | * Register: HW_USBCTRL_ULPI | ||
473 | * Address: 0x170 | ||
474 | * SCT: no | ||
475 | */ | ||
476 | #define HW_USBCTRL_ULPI (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x170)) | ||
477 | #define BP_USBCTRL_ULPI_WAKEUP 31 | ||
478 | #define BM_USBCTRL_ULPI_WAKEUP 0x80000000 | ||
479 | #define BF_USBCTRL_ULPI_WAKEUP(v) (((v) << 31) & 0x80000000) | ||
480 | #define BP_USBCTRL_ULPI_RUN 30 | ||
481 | #define BM_USBCTRL_ULPI_RUN 0x40000000 | ||
482 | #define BF_USBCTRL_ULPI_RUN(v) (((v) << 30) & 0x40000000) | ||
483 | #define BP_USBCTRL_ULPI_RDWR 29 | ||
484 | #define BM_USBCTRL_ULPI_RDWR 0x20000000 | ||
485 | #define BF_USBCTRL_ULPI_RDWR(v) (((v) << 29) & 0x20000000) | ||
486 | #define BP_USBCTRL_ULPI_ERROR 28 | ||
487 | #define BM_USBCTRL_ULPI_ERROR 0x10000000 | ||
488 | #define BF_USBCTRL_ULPI_ERROR(v) (((v) << 28) & 0x10000000) | ||
489 | #define BP_USBCTRL_ULPI_SYNC 27 | ||
490 | #define BM_USBCTRL_ULPI_SYNC 0x8000000 | ||
491 | #define BF_USBCTRL_ULPI_SYNC(v) (((v) << 27) & 0x8000000) | ||
492 | #define BP_USBCTRL_ULPI_PORT 24 | ||
493 | #define BM_USBCTRL_ULPI_PORT 0x7000000 | ||
494 | #define BF_USBCTRL_ULPI_PORT(v) (((v) << 24) & 0x7000000) | ||
495 | #define BP_USBCTRL_ULPI_ADDR 16 | ||
496 | #define BM_USBCTRL_ULPI_ADDR 0xff0000 | ||
497 | #define BF_USBCTRL_ULPI_ADDR(v) (((v) << 16) & 0xff0000) | ||
498 | #define BP_USBCTRL_ULPI_DATARD 8 | ||
499 | #define BM_USBCTRL_ULPI_DATARD 0xff00 | ||
500 | #define BF_USBCTRL_ULPI_DATARD(v) (((v) << 8) & 0xff00) | ||
501 | #define BP_USBCTRL_ULPI_DATAWR 0 | ||
502 | #define BM_USBCTRL_ULPI_DATAWR 0xff | ||
503 | #define BF_USBCTRL_ULPI_DATAWR(v) (((v) << 0) & 0xff) | ||
504 | |||
505 | /** | ||
506 | * Register: HW_USBCTRL_VFRAME | ||
507 | * Address: 0x174 | ||
508 | * SCT: no | ||
509 | */ | ||
510 | #define HW_USBCTRL_VFRAME (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x174)) | ||
511 | #define BP_USBCTRL_VFRAME_EMPTY 0 | ||
512 | #define BM_USBCTRL_VFRAME_EMPTY 0xffffffff | ||
513 | #define BF_USBCTRL_VFRAME_EMPTY(v) (((v) << 0) & 0xffffffff) | ||
514 | |||
515 | /** | ||
516 | * Register: HW_USBCTRL_EPNAK | ||
517 | * Address: 0x178 | ||
518 | * SCT: no | ||
519 | */ | ||
520 | #define HW_USBCTRL_EPNAK (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x178)) | ||
521 | #define BP_USBCTRL_EPNAK_EPTN 16 | ||
522 | #define BM_USBCTRL_EPNAK_EPTN 0xffff0000 | ||
523 | #define BF_USBCTRL_EPNAK_EPTN(v) (((v) << 16) & 0xffff0000) | ||
524 | #define BP_USBCTRL_EPNAK_EPRN 0 | ||
525 | #define BM_USBCTRL_EPNAK_EPRN 0xffff | ||
526 | #define BF_USBCTRL_EPNAK_EPRN(v) (((v) << 0) & 0xffff) | ||
527 | |||
528 | /** | ||
529 | * Register: HW_USBCTRL_EPNAKEN | ||
530 | * Address: 0x17c | ||
531 | * SCT: no | ||
532 | */ | ||
533 | #define HW_USBCTRL_EPNAKEN (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x17c)) | ||
534 | #define BP_USBCTRL_EPNAKEN_EPTNE 16 | ||
535 | #define BM_USBCTRL_EPNAKEN_EPTNE 0xffff0000 | ||
536 | #define BF_USBCTRL_EPNAKEN_EPTNE(v) (((v) << 16) & 0xffff0000) | ||
537 | #define BP_USBCTRL_EPNAKEN_EPRNE 0 | ||
538 | #define BM_USBCTRL_EPNAKEN_EPRNE 0xffff | ||
539 | #define BF_USBCTRL_EPNAKEN_EPRNE(v) (((v) << 0) & 0xffff) | ||
540 | |||
541 | /** | ||
542 | * Register: HW_USBCTRL_CONFIGFLAG | ||
543 | * Address: 0x180 | ||
544 | * SCT: no | ||
545 | */ | ||
546 | #define HW_USBCTRL_CONFIGFLAG (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x180)) | ||
547 | #define BP_USBCTRL_CONFIGFLAG_FLAG 0 | ||
548 | #define BM_USBCTRL_CONFIGFLAG_FLAG 0x1 | ||
549 | #define BF_USBCTRL_CONFIGFLAG_FLAG(v) (((v) << 0) & 0x1) | ||
550 | |||
551 | /** | ||
552 | * Register: HW_USBCTRL_PORTSC1 | ||
553 | * Address: 0x184 | ||
554 | * SCT: no | ||
555 | */ | ||
556 | #define HW_USBCTRL_PORTSC1 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x184)) | ||
557 | #define BP_USBCTRL_PORTSC1_PTS 30 | ||
558 | #define BM_USBCTRL_PORTSC1_PTS 0xc0000000 | ||
559 | #define BV_USBCTRL_PORTSC1_PTS__UTMI 0x0 | ||
560 | #define BV_USBCTRL_PORTSC1_PTS__PHIL 0x1 | ||
561 | #define BV_USBCTRL_PORTSC1_PTS__ULPI 0x2 | ||
562 | #define BV_USBCTRL_PORTSC1_PTS__SERIAL 0x3 | ||
563 | #define BF_USBCTRL_PORTSC1_PTS(v) (((v) << 30) & 0xc0000000) | ||
564 | #define BF_USBCTRL_PORTSC1_PTS_V(v) ((BV_USBCTRL_PORTSC1_PTS__##v << 30) & 0xc0000000) | ||
565 | #define BP_USBCTRL_PORTSC1_STS 29 | ||
566 | #define BM_USBCTRL_PORTSC1_STS 0x20000000 | ||
567 | #define BF_USBCTRL_PORTSC1_STS(v) (((v) << 29) & 0x20000000) | ||
568 | #define BP_USBCTRL_PORTSC1_PTW 28 | ||
569 | #define BM_USBCTRL_PORTSC1_PTW 0x10000000 | ||
570 | #define BF_USBCTRL_PORTSC1_PTW(v) (((v) << 28) & 0x10000000) | ||
571 | #define BP_USBCTRL_PORTSC1_PSPD 26 | ||
572 | #define BM_USBCTRL_PORTSC1_PSPD 0xc000000 | ||
573 | #define BV_USBCTRL_PORTSC1_PSPD__FULL 0x0 | ||
574 | #define BV_USBCTRL_PORTSC1_PSPD__LO 0x1 | ||
575 | #define BV_USBCTRL_PORTSC1_PSPD__HI 0x2 | ||
576 | #define BF_USBCTRL_PORTSC1_PSPD(v) (((v) << 26) & 0xc000000) | ||
577 | #define BF_USBCTRL_PORTSC1_PSPD_V(v) ((BV_USBCTRL_PORTSC1_PSPD__##v << 26) & 0xc000000) | ||
578 | #define BP_USBCTRL_PORTSC1_PFSC 24 | ||
579 | #define BM_USBCTRL_PORTSC1_PFSC 0x1000000 | ||
580 | #define BF_USBCTRL_PORTSC1_PFSC(v) (((v) << 24) & 0x1000000) | ||
581 | #define BP_USBCTRL_PORTSC1_PHCD 23 | ||
582 | #define BM_USBCTRL_PORTSC1_PHCD 0x800000 | ||
583 | #define BF_USBCTRL_PORTSC1_PHCD(v) (((v) << 23) & 0x800000) | ||
584 | #define BP_USBCTRL_PORTSC1_WKOC 22 | ||
585 | #define BM_USBCTRL_PORTSC1_WKOC 0x400000 | ||
586 | #define BF_USBCTRL_PORTSC1_WKOC(v) (((v) << 22) & 0x400000) | ||
587 | #define BP_USBCTRL_PORTSC1_WKDS 21 | ||
588 | #define BM_USBCTRL_PORTSC1_WKDS 0x200000 | ||
589 | #define BF_USBCTRL_PORTSC1_WKDS(v) (((v) << 21) & 0x200000) | ||
590 | #define BP_USBCTRL_PORTSC1_WKCN 20 | ||
591 | #define BM_USBCTRL_PORTSC1_WKCN 0x100000 | ||
592 | #define BF_USBCTRL_PORTSC1_WKCN(v) (((v) << 20) & 0x100000) | ||
593 | #define BP_USBCTRL_PORTSC1_PTC 16 | ||
594 | #define BM_USBCTRL_PORTSC1_PTC 0xf0000 | ||
595 | #define BV_USBCTRL_PORTSC1_PTC__DISABLE 0x0 | ||
596 | #define BV_USBCTRL_PORTSC1_PTC__J 0x1 | ||
597 | #define BV_USBCTRL_PORTSC1_PTC__K 0x2 | ||
598 | #define BV_USBCTRL_PORTSC1_PTC__SE0orNAK 0x3 | ||
599 | #define BV_USBCTRL_PORTSC1_PTC__Packet 0x4 | ||
600 | #define BV_USBCTRL_PORTSC1_PTC__ForceEnableHS 0x5 | ||
601 | #define BV_USBCTRL_PORTSC1_PTC__ForceEnableFS 0x6 | ||
602 | #define BV_USBCTRL_PORTSC1_PTC__ForceEnableLS 0x7 | ||
603 | #define BF_USBCTRL_PORTSC1_PTC(v) (((v) << 16) & 0xf0000) | ||
604 | #define BF_USBCTRL_PORTSC1_PTC_V(v) ((BV_USBCTRL_PORTSC1_PTC__##v << 16) & 0xf0000) | ||
605 | #define BP_USBCTRL_PORTSC1_PIC 14 | ||
606 | #define BM_USBCTRL_PORTSC1_PIC 0xc000 | ||
607 | #define BV_USBCTRL_PORTSC1_PIC__OFF 0x0 | ||
608 | #define BV_USBCTRL_PORTSC1_PIC__AMBER 0x1 | ||
609 | #define BV_USBCTRL_PORTSC1_PIC__GREEN 0x2 | ||
610 | #define BV_USBCTRL_PORTSC1_PIC__UNDEF 0x3 | ||
611 | #define BF_USBCTRL_PORTSC1_PIC(v) (((v) << 14) & 0xc000) | ||
612 | #define BF_USBCTRL_PORTSC1_PIC_V(v) ((BV_USBCTRL_PORTSC1_PIC__##v << 14) & 0xc000) | ||
613 | #define BP_USBCTRL_PORTSC1_PO 13 | ||
614 | #define BM_USBCTRL_PORTSC1_PO 0x2000 | ||
615 | #define BF_USBCTRL_PORTSC1_PO(v) (((v) << 13) & 0x2000) | ||
616 | #define BP_USBCTRL_PORTSC1_PP 12 | ||
617 | #define BM_USBCTRL_PORTSC1_PP 0x1000 | ||
618 | #define BF_USBCTRL_PORTSC1_PP(v) (((v) << 12) & 0x1000) | ||
619 | #define BP_USBCTRL_PORTSC1_LS 10 | ||
620 | #define BM_USBCTRL_PORTSC1_LS 0xc00 | ||
621 | #define BV_USBCTRL_PORTSC1_LS__SE0 0x0 | ||
622 | #define BV_USBCTRL_PORTSC1_LS__K 0x1 | ||
623 | #define BV_USBCTRL_PORTSC1_LS__J 0x2 | ||
624 | #define BF_USBCTRL_PORTSC1_LS(v) (((v) << 10) & 0xc00) | ||
625 | #define BF_USBCTRL_PORTSC1_LS_V(v) ((BV_USBCTRL_PORTSC1_LS__##v << 10) & 0xc00) | ||
626 | #define BP_USBCTRL_PORTSC1_HSP 9 | ||
627 | #define BM_USBCTRL_PORTSC1_HSP 0x200 | ||
628 | #define BF_USBCTRL_PORTSC1_HSP(v) (((v) << 9) & 0x200) | ||
629 | #define BP_USBCTRL_PORTSC1_PR 8 | ||
630 | #define BM_USBCTRL_PORTSC1_PR 0x100 | ||
631 | #define BF_USBCTRL_PORTSC1_PR(v) (((v) << 8) & 0x100) | ||
632 | #define BP_USBCTRL_PORTSC1_SUSP 7 | ||
633 | #define BM_USBCTRL_PORTSC1_SUSP 0x80 | ||
634 | #define BF_USBCTRL_PORTSC1_SUSP(v) (((v) << 7) & 0x80) | ||
635 | #define BP_USBCTRL_PORTSC1_FPR 6 | ||
636 | #define BM_USBCTRL_PORTSC1_FPR 0x40 | ||
637 | #define BF_USBCTRL_PORTSC1_FPR(v) (((v) << 6) & 0x40) | ||
638 | #define BP_USBCTRL_PORTSC1_OCC 5 | ||
639 | #define BM_USBCTRL_PORTSC1_OCC 0x20 | ||
640 | #define BF_USBCTRL_PORTSC1_OCC(v) (((v) << 5) & 0x20) | ||
641 | #define BP_USBCTRL_PORTSC1_OCA 4 | ||
642 | #define BM_USBCTRL_PORTSC1_OCA 0x10 | ||
643 | #define BF_USBCTRL_PORTSC1_OCA(v) (((v) << 4) & 0x10) | ||
644 | #define BP_USBCTRL_PORTSC1_PEC 3 | ||
645 | #define BM_USBCTRL_PORTSC1_PEC 0x8 | ||
646 | #define BF_USBCTRL_PORTSC1_PEC(v) (((v) << 3) & 0x8) | ||
647 | #define BP_USBCTRL_PORTSC1_PE 2 | ||
648 | #define BM_USBCTRL_PORTSC1_PE 0x4 | ||
649 | #define BF_USBCTRL_PORTSC1_PE(v) (((v) << 2) & 0x4) | ||
650 | #define BP_USBCTRL_PORTSC1_CSC 1 | ||
651 | #define BM_USBCTRL_PORTSC1_CSC 0x2 | ||
652 | #define BF_USBCTRL_PORTSC1_CSC(v) (((v) << 1) & 0x2) | ||
653 | #define BP_USBCTRL_PORTSC1_CCS 0 | ||
654 | #define BM_USBCTRL_PORTSC1_CCS 0x1 | ||
655 | #define BF_USBCTRL_PORTSC1_CCS(v) (((v) << 0) & 0x1) | ||
656 | |||
657 | /** | ||
658 | * Register: HW_USBCTRL_OTGSC | ||
659 | * Address: 0x1a4 | ||
660 | * SCT: no | ||
661 | */ | ||
662 | #define HW_USBCTRL_OTGSC (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a4)) | ||
663 | #define BP_USBCTRL_OTGSC_DPIE 30 | ||
664 | #define BM_USBCTRL_OTGSC_DPIE 0x40000000 | ||
665 | #define BF_USBCTRL_OTGSC_DPIE(v) (((v) << 30) & 0x40000000) | ||
666 | #define BP_USBCTRL_OTGSC_ONEMSE 29 | ||
667 | #define BM_USBCTRL_OTGSC_ONEMSE 0x20000000 | ||
668 | #define BF_USBCTRL_OTGSC_ONEMSE(v) (((v) << 29) & 0x20000000) | ||
669 | #define BP_USBCTRL_OTGSC_BSEIE 28 | ||
670 | #define BM_USBCTRL_OTGSC_BSEIE 0x10000000 | ||
671 | #define BF_USBCTRL_OTGSC_BSEIE(v) (((v) << 28) & 0x10000000) | ||
672 | #define BP_USBCTRL_OTGSC_BSVIE 27 | ||
673 | #define BM_USBCTRL_OTGSC_BSVIE 0x8000000 | ||
674 | #define BF_USBCTRL_OTGSC_BSVIE(v) (((v) << 27) & 0x8000000) | ||
675 | #define BP_USBCTRL_OTGSC_ASVIE 26 | ||
676 | #define BM_USBCTRL_OTGSC_ASVIE 0x4000000 | ||
677 | #define BF_USBCTRL_OTGSC_ASVIE(v) (((v) << 26) & 0x4000000) | ||
678 | #define BP_USBCTRL_OTGSC_AVVIE 25 | ||
679 | #define BM_USBCTRL_OTGSC_AVVIE 0x2000000 | ||
680 | #define BF_USBCTRL_OTGSC_AVVIE(v) (((v) << 25) & 0x2000000) | ||
681 | #define BP_USBCTRL_OTGSC_IDIE 24 | ||
682 | #define BM_USBCTRL_OTGSC_IDIE 0x1000000 | ||
683 | #define BF_USBCTRL_OTGSC_IDIE(v) (((v) << 24) & 0x1000000) | ||
684 | #define BP_USBCTRL_OTGSC_DPIS 22 | ||
685 | #define BM_USBCTRL_OTGSC_DPIS 0x400000 | ||
686 | #define BF_USBCTRL_OTGSC_DPIS(v) (((v) << 22) & 0x400000) | ||
687 | #define BP_USBCTRL_OTGSC_ONEMSS 21 | ||
688 | #define BM_USBCTRL_OTGSC_ONEMSS 0x200000 | ||
689 | #define BF_USBCTRL_OTGSC_ONEMSS(v) (((v) << 21) & 0x200000) | ||
690 | #define BP_USBCTRL_OTGSC_BSEIS 20 | ||
691 | #define BM_USBCTRL_OTGSC_BSEIS 0x100000 | ||
692 | #define BF_USBCTRL_OTGSC_BSEIS(v) (((v) << 20) & 0x100000) | ||
693 | #define BP_USBCTRL_OTGSC_BSVIS 19 | ||
694 | #define BM_USBCTRL_OTGSC_BSVIS 0x80000 | ||
695 | #define BF_USBCTRL_OTGSC_BSVIS(v) (((v) << 19) & 0x80000) | ||
696 | #define BP_USBCTRL_OTGSC_ASVIS 18 | ||
697 | #define BM_USBCTRL_OTGSC_ASVIS 0x40000 | ||
698 | #define BF_USBCTRL_OTGSC_ASVIS(v) (((v) << 18) & 0x40000) | ||
699 | #define BP_USBCTRL_OTGSC_AVVIS 17 | ||
700 | #define BM_USBCTRL_OTGSC_AVVIS 0x20000 | ||
701 | #define BF_USBCTRL_OTGSC_AVVIS(v) (((v) << 17) & 0x20000) | ||
702 | #define BP_USBCTRL_OTGSC_IDIS 16 | ||
703 | #define BM_USBCTRL_OTGSC_IDIS 0x10000 | ||
704 | #define BF_USBCTRL_OTGSC_IDIS(v) (((v) << 16) & 0x10000) | ||
705 | #define BP_USBCTRL_OTGSC_DPS 14 | ||
706 | #define BM_USBCTRL_OTGSC_DPS 0x4000 | ||
707 | #define BF_USBCTRL_OTGSC_DPS(v) (((v) << 14) & 0x4000) | ||
708 | #define BP_USBCTRL_OTGSC_ONEMST 13 | ||
709 | #define BM_USBCTRL_OTGSC_ONEMST 0x2000 | ||
710 | #define BF_USBCTRL_OTGSC_ONEMST(v) (((v) << 13) & 0x2000) | ||
711 | #define BP_USBCTRL_OTGSC_BSE 12 | ||
712 | #define BM_USBCTRL_OTGSC_BSE 0x1000 | ||
713 | #define BF_USBCTRL_OTGSC_BSE(v) (((v) << 12) & 0x1000) | ||
714 | #define BP_USBCTRL_OTGSC_BSV 11 | ||
715 | #define BM_USBCTRL_OTGSC_BSV 0x800 | ||
716 | #define BF_USBCTRL_OTGSC_BSV(v) (((v) << 11) & 0x800) | ||
717 | #define BP_USBCTRL_OTGSC_ASV 10 | ||
718 | #define BM_USBCTRL_OTGSC_ASV 0x400 | ||
719 | #define BF_USBCTRL_OTGSC_ASV(v) (((v) << 10) & 0x400) | ||
720 | #define BP_USBCTRL_OTGSC_AVV 9 | ||
721 | #define BM_USBCTRL_OTGSC_AVV 0x200 | ||
722 | #define BF_USBCTRL_OTGSC_AVV(v) (((v) << 9) & 0x200) | ||
723 | #define BP_USBCTRL_OTGSC_ID 8 | ||
724 | #define BM_USBCTRL_OTGSC_ID 0x100 | ||
725 | #define BF_USBCTRL_OTGSC_ID(v) (((v) << 8) & 0x100) | ||
726 | #define BP_USBCTRL_OTGSC_HABA 7 | ||
727 | #define BM_USBCTRL_OTGSC_HABA 0x80 | ||
728 | #define BF_USBCTRL_OTGSC_HABA(v) (((v) << 7) & 0x80) | ||
729 | #define BP_USBCTRL_OTGSC_HADP 6 | ||
730 | #define BM_USBCTRL_OTGSC_HADP 0x40 | ||
731 | #define BF_USBCTRL_OTGSC_HADP(v) (((v) << 6) & 0x40) | ||
732 | #define BP_USBCTRL_OTGSC_IDPU 5 | ||
733 | #define BM_USBCTRL_OTGSC_IDPU 0x20 | ||
734 | #define BF_USBCTRL_OTGSC_IDPU(v) (((v) << 5) & 0x20) | ||
735 | #define BP_USBCTRL_OTGSC_DP 4 | ||
736 | #define BM_USBCTRL_OTGSC_DP 0x10 | ||
737 | #define BF_USBCTRL_OTGSC_DP(v) (((v) << 4) & 0x10) | ||
738 | #define BP_USBCTRL_OTGSC_OT 3 | ||
739 | #define BM_USBCTRL_OTGSC_OT 0x8 | ||
740 | #define BF_USBCTRL_OTGSC_OT(v) (((v) << 3) & 0x8) | ||
741 | #define BP_USBCTRL_OTGSC_HAAR 2 | ||
742 | #define BM_USBCTRL_OTGSC_HAAR 0x4 | ||
743 | #define BF_USBCTRL_OTGSC_HAAR(v) (((v) << 2) & 0x4) | ||
744 | #define BP_USBCTRL_OTGSC_VC 1 | ||
745 | #define BM_USBCTRL_OTGSC_VC 0x2 | ||
746 | #define BF_USBCTRL_OTGSC_VC(v) (((v) << 1) & 0x2) | ||
747 | #define BP_USBCTRL_OTGSC_VD 0 | ||
748 | #define BM_USBCTRL_OTGSC_VD 0x1 | ||
749 | #define BF_USBCTRL_OTGSC_VD(v) (((v) << 0) & 0x1) | ||
750 | |||
751 | /** | ||
752 | * Register: HW_USBCTRL_USBMODE | ||
753 | * Address: 0x1a8 | ||
754 | * SCT: no | ||
755 | */ | ||
756 | #define HW_USBCTRL_USBMODE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a8)) | ||
757 | #define BP_USBCTRL_USBMODE_SDIS 4 | ||
758 | #define BM_USBCTRL_USBMODE_SDIS 0x10 | ||
759 | #define BF_USBCTRL_USBMODE_SDIS(v) (((v) << 4) & 0x10) | ||
760 | #define BP_USBCTRL_USBMODE_SLOM 3 | ||
761 | #define BM_USBCTRL_USBMODE_SLOM 0x8 | ||
762 | #define BF_USBCTRL_USBMODE_SLOM(v) (((v) << 3) & 0x8) | ||
763 | #define BP_USBCTRL_USBMODE_ES 2 | ||
764 | #define BM_USBCTRL_USBMODE_ES 0x4 | ||
765 | #define BF_USBCTRL_USBMODE_ES(v) (((v) << 2) & 0x4) | ||
766 | #define BP_USBCTRL_USBMODE_CM 0 | ||
767 | #define BM_USBCTRL_USBMODE_CM 0x3 | ||
768 | #define BV_USBCTRL_USBMODE_CM__IDLE 0x0 | ||
769 | #define BV_USBCTRL_USBMODE_CM__DEVICE 0x2 | ||
770 | #define BV_USBCTRL_USBMODE_CM__HOST 0x3 | ||
771 | #define BF_USBCTRL_USBMODE_CM(v) (((v) << 0) & 0x3) | ||
772 | #define BF_USBCTRL_USBMODE_CM_V(v) ((BV_USBCTRL_USBMODE_CM__##v << 0) & 0x3) | ||
773 | |||
774 | /** | ||
775 | * Register: HW_USBCTRL_ENDPTSETUPSTAT | ||
776 | * Address: 0x1ac | ||
777 | * SCT: no | ||
778 | */ | ||
779 | #define HW_USBCTRL_ENDPTSETUPSTAT (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1ac)) | ||
780 | #define BP_USBCTRL_ENDPTSETUPSTAT_STS 0 | ||
781 | #define BM_USBCTRL_ENDPTSETUPSTAT_STS 0xffff | ||
782 | #define BF_USBCTRL_ENDPTSETUPSTAT_STS(v) (((v) << 0) & 0xffff) | ||
783 | |||
784 | /** | ||
785 | * Register: HW_USBCTRL_ENDPTPRIME | ||
786 | * Address: 0x1b0 | ||
787 | * SCT: no | ||
788 | */ | ||
789 | #define HW_USBCTRL_ENDPTPRIME (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b0)) | ||
790 | #define BP_USBCTRL_ENDPTPRIME_PETB 16 | ||
791 | #define BM_USBCTRL_ENDPTPRIME_PETB 0xffff0000 | ||
792 | #define BF_USBCTRL_ENDPTPRIME_PETB(v) (((v) << 16) & 0xffff0000) | ||
793 | #define BP_USBCTRL_ENDPTPRIME_PERB 0 | ||
794 | #define BM_USBCTRL_ENDPTPRIME_PERB 0xffff | ||
795 | #define BF_USBCTRL_ENDPTPRIME_PERB(v) (((v) << 0) & 0xffff) | ||
796 | |||
797 | /** | ||
798 | * Register: HW_USBCTRL_ENDPTFLUSH | ||
799 | * Address: 0x1b4 | ||
800 | * SCT: no | ||
801 | */ | ||
802 | #define HW_USBCTRL_ENDPTFLUSH (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b4)) | ||
803 | #define BP_USBCTRL_ENDPTFLUSH_FETB 16 | ||
804 | #define BM_USBCTRL_ENDPTFLUSH_FETB 0xffff0000 | ||
805 | #define BF_USBCTRL_ENDPTFLUSH_FETB(v) (((v) << 16) & 0xffff0000) | ||
806 | #define BP_USBCTRL_ENDPTFLUSH_FERB 0 | ||
807 | #define BM_USBCTRL_ENDPTFLUSH_FERB 0xffff | ||
808 | #define BF_USBCTRL_ENDPTFLUSH_FERB(v) (((v) << 0) & 0xffff) | ||
809 | |||
810 | /** | ||
811 | * Register: HW_USBCTRL_ENDPTSTATUS | ||
812 | * Address: 0x1b8 | ||
813 | * SCT: no | ||
814 | */ | ||
815 | #define HW_USBCTRL_ENDPTSTATUS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b8)) | ||
816 | #define BP_USBCTRL_ENDPTSTATUS_ETBR 16 | ||
817 | #define BM_USBCTRL_ENDPTSTATUS_ETBR 0xffff0000 | ||
818 | #define BF_USBCTRL_ENDPTSTATUS_ETBR(v) (((v) << 16) & 0xffff0000) | ||
819 | #define BP_USBCTRL_ENDPTSTATUS_ERBR 0 | ||
820 | #define BM_USBCTRL_ENDPTSTATUS_ERBR 0xffff | ||
821 | #define BF_USBCTRL_ENDPTSTATUS_ERBR(v) (((v) << 0) & 0xffff) | ||
822 | |||
823 | /** | ||
824 | * Register: HW_USBCTRL_ENDPTCOMPLETE | ||
825 | * Address: 0x1bc | ||
826 | * SCT: no | ||
827 | */ | ||
828 | #define HW_USBCTRL_ENDPTCOMPLETE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1bc)) | ||
829 | #define BP_USBCTRL_ENDPTCOMPLETE_ETCE 16 | ||
830 | #define BM_USBCTRL_ENDPTCOMPLETE_ETCE 0xffff0000 | ||
831 | #define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v) (((v) << 16) & 0xffff0000) | ||
832 | #define BP_USBCTRL_ENDPTCOMPLETE_ERCE 0 | ||
833 | #define BM_USBCTRL_ENDPTCOMPLETE_ERCE 0xffff | ||
834 | #define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v) (((v) << 0) & 0xffff) | ||
835 | |||
836 | /** | ||
837 | * Register: HW_USBCTRL_ENDPTCTRLn | ||
838 | * Address: 0x1c0+n*0x4 | ||
839 | * SCT: no | ||
840 | */ | ||
841 | #define HW_USBCTRL_ENDPTCTRLn(n) (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c0+(n)*0x4)) | ||
842 | #define BP_USBCTRL_ENDPTCTRLn_TXE 23 | ||
843 | #define BM_USBCTRL_ENDPTCTRLn_TXE 0x800000 | ||
844 | #define BF_USBCTRL_ENDPTCTRLn_TXE(v) (((v) << 23) & 0x800000) | ||
845 | #define BP_USBCTRL_ENDPTCTRLn_TXR 22 | ||
846 | #define BM_USBCTRL_ENDPTCTRLn_TXR 0x400000 | ||
847 | #define BF_USBCTRL_ENDPTCTRLn_TXR(v) (((v) << 22) & 0x400000) | ||
848 | #define BP_USBCTRL_ENDPTCTRLn_TXI 21 | ||
849 | #define BM_USBCTRL_ENDPTCTRLn_TXI 0x200000 | ||
850 | #define BF_USBCTRL_ENDPTCTRLn_TXI(v) (((v) << 21) & 0x200000) | ||
851 | #define BP_USBCTRL_ENDPTCTRLn_TXT 18 | ||
852 | #define BM_USBCTRL_ENDPTCTRLn_TXT 0xc0000 | ||
853 | #define BV_USBCTRL_ENDPTCTRLn_TXT__ISOCHRONOUS 0x1 | ||
854 | #define BV_USBCTRL_ENDPTCTRLn_TXT__BULK 0x2 | ||
855 | #define BV_USBCTRL_ENDPTCTRLn_TXT__INT 0x3 | ||
856 | #define BF_USBCTRL_ENDPTCTRLn_TXT(v) (((v) << 18) & 0xc0000) | ||
857 | #define BF_USBCTRL_ENDPTCTRLn_TXT_V(v) ((BV_USBCTRL_ENDPTCTRLn_TXT__##v << 18) & 0xc0000) | ||
858 | #define BP_USBCTRL_ENDPTCTRLn_TXS 16 | ||
859 | #define BM_USBCTRL_ENDPTCTRLn_TXS 0x10000 | ||
860 | #define BF_USBCTRL_ENDPTCTRLn_TXS(v) (((v) << 16) & 0x10000) | ||
861 | #define BP_USBCTRL_ENDPTCTRLn_RXE 7 | ||
862 | #define BM_USBCTRL_ENDPTCTRLn_RXE 0x80 | ||
863 | #define BF_USBCTRL_ENDPTCTRLn_RXE(v) (((v) << 7) & 0x80) | ||
864 | #define BP_USBCTRL_ENDPTCTRLn_RXR 6 | ||
865 | #define BM_USBCTRL_ENDPTCTRLn_RXR 0x40 | ||
866 | #define BF_USBCTRL_ENDPTCTRLn_RXR(v) (((v) << 6) & 0x40) | ||
867 | #define BP_USBCTRL_ENDPTCTRLn_RXI 5 | ||
868 | #define BM_USBCTRL_ENDPTCTRLn_RXI 0x20 | ||
869 | #define BF_USBCTRL_ENDPTCTRLn_RXI(v) (((v) << 5) & 0x20) | ||
870 | #define BP_USBCTRL_ENDPTCTRLn_RXT 2 | ||
871 | #define BM_USBCTRL_ENDPTCTRLn_RXT 0xc | ||
872 | #define BF_USBCTRL_ENDPTCTRLn_RXT(v) (((v) << 2) & 0xc) | ||
873 | #define BP_USBCTRL_ENDPTCTRLn_RXS 0 | ||
874 | #define BM_USBCTRL_ENDPTCTRLn_RXS 0x1 | ||
875 | #define BF_USBCTRL_ENDPTCTRLn_RXS(v) (((v) << 0) & 0x1) | ||
876 | |||
877 | #endif /* __HEADERGEN__STMP3700__USBCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h new file mode 100644 index 0000000000..ae9359e1dd --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h | |||
@@ -0,0 +1,300 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__USBPHY__H__ | ||
24 | #define __HEADERGEN__STMP3700__USBPHY__H__ | ||
25 | |||
26 | #define REGS_USBPHY_BASE (0x8007c000) | ||
27 | |||
28 | #define REGS_USBPHY_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_USBPHY_PWD | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_USBPHY_PWD (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0)) | ||
36 | #define HW_USBPHY_PWD_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4)) | ||
37 | #define HW_USBPHY_PWD_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8)) | ||
38 | #define HW_USBPHY_PWD_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc)) | ||
39 | #define BP_USBPHY_PWD_RXPWDRX 20 | ||
40 | #define BM_USBPHY_PWD_RXPWDRX 0x100000 | ||
41 | #define BF_USBPHY_PWD_RXPWDRX(v) (((v) << 20) & 0x100000) | ||
42 | #define BP_USBPHY_PWD_RXPWDDIFF 19 | ||
43 | #define BM_USBPHY_PWD_RXPWDDIFF 0x80000 | ||
44 | #define BF_USBPHY_PWD_RXPWDDIFF(v) (((v) << 19) & 0x80000) | ||
45 | #define BP_USBPHY_PWD_RXPWD1PT1 18 | ||
46 | #define BM_USBPHY_PWD_RXPWD1PT1 0x40000 | ||
47 | #define BF_USBPHY_PWD_RXPWD1PT1(v) (((v) << 18) & 0x40000) | ||
48 | #define BP_USBPHY_PWD_RXPWDENV 17 | ||
49 | #define BM_USBPHY_PWD_RXPWDENV 0x20000 | ||
50 | #define BF_USBPHY_PWD_RXPWDENV(v) (((v) << 17) & 0x20000) | ||
51 | #define BP_USBPHY_PWD_TXPWDCOMP 14 | ||
52 | #define BM_USBPHY_PWD_TXPWDCOMP 0x4000 | ||
53 | #define BF_USBPHY_PWD_TXPWDCOMP(v) (((v) << 14) & 0x4000) | ||
54 | #define BP_USBPHY_PWD_TXPWDVBG 13 | ||
55 | #define BM_USBPHY_PWD_TXPWDVBG 0x2000 | ||
56 | #define BF_USBPHY_PWD_TXPWDVBG(v) (((v) << 13) & 0x2000) | ||
57 | #define BP_USBPHY_PWD_TXPWDV2I 12 | ||
58 | #define BM_USBPHY_PWD_TXPWDV2I 0x1000 | ||
59 | #define BF_USBPHY_PWD_TXPWDV2I(v) (((v) << 12) & 0x1000) | ||
60 | #define BP_USBPHY_PWD_TXPWDIBIAS 11 | ||
61 | #define BM_USBPHY_PWD_TXPWDIBIAS 0x800 | ||
62 | #define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800) | ||
63 | #define BP_USBPHY_PWD_TXPWDFS 10 | ||
64 | #define BM_USBPHY_PWD_TXPWDFS 0x400 | ||
65 | #define BF_USBPHY_PWD_TXPWDFS(v) (((v) << 10) & 0x400) | ||
66 | |||
67 | /** | ||
68 | * Register: HW_USBPHY_TX | ||
69 | * Address: 0x10 | ||
70 | * SCT: yes | ||
71 | */ | ||
72 | #define HW_USBPHY_TX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0)) | ||
73 | #define HW_USBPHY_TX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4)) | ||
74 | #define HW_USBPHY_TX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8)) | ||
75 | #define HW_USBPHY_TX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc)) | ||
76 | #define BP_USBPHY_TX_USBPHY_TX_EDGECTRL 26 | ||
77 | #define BM_USBPHY_TX_USBPHY_TX_EDGECTRL 0x1c000000 | ||
78 | #define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v) (((v) << 26) & 0x1c000000) | ||
79 | #define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT 25 | ||
80 | #define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT 0x2000000 | ||
81 | #define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v) (((v) << 25) & 0x2000000) | ||
82 | #define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX 24 | ||
83 | #define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX 0x1000000 | ||
84 | #define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v) (((v) << 24) & 0x1000000) | ||
85 | #define BP_USBPHY_TX_TXCMPOUT_STATUS 23 | ||
86 | #define BM_USBPHY_TX_TXCMPOUT_STATUS 0x800000 | ||
87 | #define BF_USBPHY_TX_TXCMPOUT_STATUS(v) (((v) << 23) & 0x800000) | ||
88 | #define BP_USBPHY_TX_TXENCAL45DP 21 | ||
89 | #define BM_USBPHY_TX_TXENCAL45DP 0x200000 | ||
90 | #define BF_USBPHY_TX_TXENCAL45DP(v) (((v) << 21) & 0x200000) | ||
91 | #define BP_USBPHY_TX_TXCAL45DP 16 | ||
92 | #define BM_USBPHY_TX_TXCAL45DP 0xf0000 | ||
93 | #define BF_USBPHY_TX_TXCAL45DP(v) (((v) << 16) & 0xf0000) | ||
94 | #define BP_USBPHY_TX_TXENCAL45DN 13 | ||
95 | #define BM_USBPHY_TX_TXENCAL45DN 0x2000 | ||
96 | #define BF_USBPHY_TX_TXENCAL45DN(v) (((v) << 13) & 0x2000) | ||
97 | #define BP_USBPHY_TX_TXCAL45DN 8 | ||
98 | #define BM_USBPHY_TX_TXCAL45DN 0xf00 | ||
99 | #define BF_USBPHY_TX_TXCAL45DN(v) (((v) << 8) & 0xf00) | ||
100 | #define BP_USBPHY_TX_TXCALIBRATE 7 | ||
101 | #define BM_USBPHY_TX_TXCALIBRATE 0x80 | ||
102 | #define BF_USBPHY_TX_TXCALIBRATE(v) (((v) << 7) & 0x80) | ||
103 | #define BP_USBPHY_TX_D_CAL 0 | ||
104 | #define BM_USBPHY_TX_D_CAL 0xf | ||
105 | #define BF_USBPHY_TX_D_CAL(v) (((v) << 0) & 0xf) | ||
106 | |||
107 | /** | ||
108 | * Register: HW_USBPHY_RX | ||
109 | * Address: 0x20 | ||
110 | * SCT: yes | ||
111 | */ | ||
112 | #define HW_USBPHY_RX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0)) | ||
113 | #define HW_USBPHY_RX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4)) | ||
114 | #define HW_USBPHY_RX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8)) | ||
115 | #define HW_USBPHY_RX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc)) | ||
116 | #define BP_USBPHY_RX_RXDBYPASS 22 | ||
117 | #define BM_USBPHY_RX_RXDBYPASS 0x400000 | ||
118 | #define BF_USBPHY_RX_RXDBYPASS(v) (((v) << 22) & 0x400000) | ||
119 | #define BP_USBPHY_RX_DISCONADJ 4 | ||
120 | #define BM_USBPHY_RX_DISCONADJ 0x30 | ||
121 | #define BF_USBPHY_RX_DISCONADJ(v) (((v) << 4) & 0x30) | ||
122 | #define BP_USBPHY_RX_ENVADJ 0 | ||
123 | #define BM_USBPHY_RX_ENVADJ 0x3 | ||
124 | #define BF_USBPHY_RX_ENVADJ(v) (((v) << 0) & 0x3) | ||
125 | |||
126 | /** | ||
127 | * Register: HW_USBPHY_CTRL | ||
128 | * Address: 0x30 | ||
129 | * SCT: yes | ||
130 | */ | ||
131 | #define HW_USBPHY_CTRL (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0)) | ||
132 | #define HW_USBPHY_CTRL_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4)) | ||
133 | #define HW_USBPHY_CTRL_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8)) | ||
134 | #define HW_USBPHY_CTRL_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc)) | ||
135 | #define BP_USBPHY_CTRL_SFTRST 31 | ||
136 | #define BM_USBPHY_CTRL_SFTRST 0x80000000 | ||
137 | #define BF_USBPHY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
138 | #define BP_USBPHY_CTRL_CLKGATE 30 | ||
139 | #define BM_USBPHY_CTRL_CLKGATE 0x40000000 | ||
140 | #define BF_USBPHY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
141 | #define BP_USBPHY_CTRL_UTMI_SUSPENDM 29 | ||
142 | #define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 | ||
143 | #define BF_USBPHY_CTRL_UTMI_SUSPENDM(v) (((v) << 29) & 0x20000000) | ||
144 | #define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0 28 | ||
145 | #define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 0x10000000 | ||
146 | #define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v) (((v) << 28) & 0x10000000) | ||
147 | #define BP_USBPHY_CTRL_DATA_ON_LRADC 13 | ||
148 | #define BM_USBPHY_CTRL_DATA_ON_LRADC 0x2000 | ||
149 | #define BF_USBPHY_CTRL_DATA_ON_LRADC(v) (((v) << 13) & 0x2000) | ||
150 | #define BP_USBPHY_CTRL_DEVPLUGIN_IRQ 12 | ||
151 | #define BM_USBPHY_CTRL_DEVPLUGIN_IRQ 0x1000 | ||
152 | #define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v) (((v) << 12) & 0x1000) | ||
153 | #define BP_USBPHY_CTRL_ENIRQDEVPLUGIN 11 | ||
154 | #define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x800 | ||
155 | #define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v) (((v) << 11) & 0x800) | ||
156 | #define BP_USBPHY_CTRL_RESUME_IRQ 10 | ||
157 | #define BM_USBPHY_CTRL_RESUME_IRQ 0x400 | ||
158 | #define BF_USBPHY_CTRL_RESUME_IRQ(v) (((v) << 10) & 0x400) | ||
159 | #define BP_USBPHY_CTRL_ENIRQRESUMEDETECT 9 | ||
160 | #define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x200 | ||
161 | #define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v) (((v) << 9) & 0x200) | ||
162 | #define BP_USBPHY_CTRL_ENOTGIDDETECT 7 | ||
163 | #define BM_USBPHY_CTRL_ENOTGIDDETECT 0x80 | ||
164 | #define BF_USBPHY_CTRL_ENOTGIDDETECT(v) (((v) << 7) & 0x80) | ||
165 | #define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY 5 | ||
166 | #define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY 0x20 | ||
167 | #define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v) (((v) << 5) & 0x20) | ||
168 | #define BP_USBPHY_CTRL_ENDEVPLUGINDETECT 4 | ||
169 | #define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x10 | ||
170 | #define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v) (((v) << 4) & 0x10) | ||
171 | #define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 3 | ||
172 | #define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x8 | ||
173 | #define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v) (((v) << 3) & 0x8) | ||
174 | #define BP_USBPHY_CTRL_ENIRQHOSTDISCON 2 | ||
175 | #define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x4 | ||
176 | #define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v) (((v) << 2) & 0x4) | ||
177 | #define BP_USBPHY_CTRL_ENHOSTDISCONDETECT 1 | ||
178 | #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x2 | ||
179 | #define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v) (((v) << 1) & 0x2) | ||
180 | #define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0 | ||
181 | #define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x1 | ||
182 | #define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v) (((v) << 0) & 0x1) | ||
183 | |||
184 | /** | ||
185 | * Register: HW_USBPHY_STATUS | ||
186 | * Address: 0x40 | ||
187 | * SCT: no | ||
188 | */ | ||
189 | #define HW_USBPHY_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40)) | ||
190 | #define BP_USBPHY_STATUS_RESUME_STATUS 10 | ||
191 | #define BM_USBPHY_STATUS_RESUME_STATUS 0x400 | ||
192 | #define BF_USBPHY_STATUS_RESUME_STATUS(v) (((v) << 10) & 0x400) | ||
193 | #define BP_USBPHY_STATUS_OTGID_STATUS 8 | ||
194 | #define BM_USBPHY_STATUS_OTGID_STATUS 0x100 | ||
195 | #define BF_USBPHY_STATUS_OTGID_STATUS(v) (((v) << 8) & 0x100) | ||
196 | #define BP_USBPHY_STATUS_DEVPLUGIN_STATUS 6 | ||
197 | #define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x40 | ||
198 | #define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v) (((v) << 6) & 0x40) | ||
199 | #define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 3 | ||
200 | #define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x8 | ||
201 | #define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_USBPHY_DEBUG | ||
205 | * Address: 0x50 | ||
206 | * SCT: yes | ||
207 | */ | ||
208 | #define HW_USBPHY_DEBUG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0)) | ||
209 | #define HW_USBPHY_DEBUG_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4)) | ||
210 | #define HW_USBPHY_DEBUG_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8)) | ||
211 | #define HW_USBPHY_DEBUG_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc)) | ||
212 | #define BP_USBPHY_DEBUG_CLKGATE 30 | ||
213 | #define BM_USBPHY_DEBUG_CLKGATE 0x40000000 | ||
214 | #define BF_USBPHY_DEBUG_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
215 | #define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG 29 | ||
216 | #define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG 0x20000000 | ||
217 | #define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v) (((v) << 29) & 0x20000000) | ||
218 | #define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 | ||
219 | #define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1e000000 | ||
220 | #define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) (((v) << 25) & 0x1e000000) | ||
221 | #define BP_USBPHY_DEBUG_ENSQUELCHRESET 24 | ||
222 | #define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x1000000 | ||
223 | #define BF_USBPHY_DEBUG_ENSQUELCHRESET(v) (((v) << 24) & 0x1000000) | ||
224 | #define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 | ||
225 | #define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x1f0000 | ||
226 | #define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) (((v) << 16) & 0x1f0000) | ||
227 | #define BP_USBPHY_DEBUG_ENTX2RXCOUNT 12 | ||
228 | #define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x1000 | ||
229 | #define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v) (((v) << 12) & 0x1000) | ||
230 | #define BP_USBPHY_DEBUG_TX2RXCOUNT 8 | ||
231 | #define BM_USBPHY_DEBUG_TX2RXCOUNT 0xf00 | ||
232 | #define BF_USBPHY_DEBUG_TX2RXCOUNT(v) (((v) << 8) & 0xf00) | ||
233 | #define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 | ||
234 | #define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x30 | ||
235 | #define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) (((v) << 4) & 0x30) | ||
236 | #define BP_USBPHY_DEBUG_HSTPULLDOWN 2 | ||
237 | #define BM_USBPHY_DEBUG_HSTPULLDOWN 0xc | ||
238 | #define BF_USBPHY_DEBUG_HSTPULLDOWN(v) (((v) << 2) & 0xc) | ||
239 | #define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 1 | ||
240 | #define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x2 | ||
241 | #define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2) | ||
242 | #define BP_USBPHY_DEBUG_OTGIDPIOLOCK 0 | ||
243 | #define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x1 | ||
244 | #define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v) (((v) << 0) & 0x1) | ||
245 | |||
246 | /** | ||
247 | * Register: HW_USBPHY_DEBUG0_STATUS | ||
248 | * Address: 0x60 | ||
249 | * SCT: no | ||
250 | */ | ||
251 | #define HW_USBPHY_DEBUG0_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60)) | ||
252 | #define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 | ||
253 | #define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xfc000000 | ||
254 | #define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) (((v) << 26) & 0xfc000000) | ||
255 | #define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 | ||
256 | #define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x3ff0000 | ||
257 | #define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
258 | #define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 | ||
259 | #define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0xffff | ||
260 | #define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) (((v) << 0) & 0xffff) | ||
261 | |||
262 | /** | ||
263 | * Register: HW_USBPHY_DEBUG1 | ||
264 | * Address: 0x70 | ||
265 | * SCT: yes | ||
266 | */ | ||
267 | #define HW_USBPHY_DEBUG1 (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x0)) | ||
268 | #define HW_USBPHY_DEBUG1_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x4)) | ||
269 | #define HW_USBPHY_DEBUG1_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x8)) | ||
270 | #define HW_USBPHY_DEBUG1_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0xc)) | ||
271 | #define BP_USBPHY_DEBUG1_ENTAILADJVD 13 | ||
272 | #define BM_USBPHY_DEBUG1_ENTAILADJVD 0x6000 | ||
273 | #define BF_USBPHY_DEBUG1_ENTAILADJVD(v) (((v) << 13) & 0x6000) | ||
274 | #define BP_USBPHY_DEBUG1_ENTX2TX 12 | ||
275 | #define BM_USBPHY_DEBUG1_ENTX2TX 0x1000 | ||
276 | #define BF_USBPHY_DEBUG1_ENTX2TX(v) (((v) << 12) & 0x1000) | ||
277 | #define BP_USBPHY_DEBUG1_PLL_IS_240 8 | ||
278 | #define BM_USBPHY_DEBUG1_PLL_IS_240 0x100 | ||
279 | #define BF_USBPHY_DEBUG1_PLL_IS_240(v) (((v) << 8) & 0x100) | ||
280 | #define BP_USBPHY_DEBUG1_DBG_ADDRESS 0 | ||
281 | #define BM_USBPHY_DEBUG1_DBG_ADDRESS 0xf | ||
282 | #define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) (((v) << 0) & 0xf) | ||
283 | |||
284 | /** | ||
285 | * Register: HW_USBPHY_VERSION | ||
286 | * Address: 0x80 | ||
287 | * SCT: no | ||
288 | */ | ||
289 | #define HW_USBPHY_VERSION (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80)) | ||
290 | #define BP_USBPHY_VERSION_MAJOR 24 | ||
291 | #define BM_USBPHY_VERSION_MAJOR 0xff000000 | ||
292 | #define BF_USBPHY_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
293 | #define BP_USBPHY_VERSION_MINOR 16 | ||
294 | #define BM_USBPHY_VERSION_MINOR 0xff0000 | ||
295 | #define BF_USBPHY_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
296 | #define BP_USBPHY_VERSION_STEP 0 | ||
297 | #define BM_USBPHY_VERSION_STEP 0xffff | ||
298 | #define BF_USBPHY_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
299 | |||
300 | #endif /* __HEADERGEN__STMP3700__USBPHY__H__ */ | ||