diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h | 288 |
1 files changed, 288 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h new file mode 100644 index 0000000000..ab8d9e6deb --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h | |||
@@ -0,0 +1,288 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__APBH__H__ | ||
24 | #define __HEADERGEN__STMP3600__APBH__H__ | ||
25 | |||
26 | #define REGS_APBH_BASE (0x80004000) | ||
27 | |||
28 | #define REGS_APBH_VERSION "2.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_APBH_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_APBH_CTRL0 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0)) | ||
36 | #define HW_APBH_CTRL0_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4)) | ||
37 | #define HW_APBH_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8)) | ||
38 | #define HW_APBH_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc)) | ||
39 | #define BP_APBH_CTRL0_SFTRST 31 | ||
40 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_APBH_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_APBH_CTRL0_CLKGATE 30 | ||
43 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_APBH_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
46 | #define BM_APBH_CTRL0_RESET_CHANNEL 0xff0000 | ||
47 | #define BV_APBH_CTRL0_RESET_CHANNEL__HWECC 0x1 | ||
48 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP 0x2 | ||
49 | #define BV_APBH_CTRL0_RESET_CHANNEL__SRC 0x4 | ||
50 | #define BV_APBH_CTRL0_RESET_CHANNEL__DEST 0x8 | ||
51 | #define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 | ||
52 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 | ||
53 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 | ||
54 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x30 | ||
55 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x40 | ||
56 | #define BF_APBH_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
57 | #define BF_APBH_CTRL0_RESET_CHANNEL_V(v) ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
58 | #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 | ||
59 | #define BM_APBH_CTRL0_CLKGATE_CHANNEL 0xff00 | ||
60 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__HWECC 0x1 | ||
61 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP 0x2 | ||
62 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SRC 0x4 | ||
63 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__DEST 0x8 | ||
64 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 | ||
65 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 | ||
66 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 | ||
67 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x30 | ||
68 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x40 | ||
69 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) << 8) & 0xff00) | ||
70 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v) ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00) | ||
71 | #define BP_APBH_CTRL0_FREEZE_CHANNEL 0 | ||
72 | #define BM_APBH_CTRL0_FREEZE_CHANNEL 0xff | ||
73 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__HWECC 0x1 | ||
74 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP 0x2 | ||
75 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SRC 0x4 | ||
76 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__DEST 0x8 | ||
77 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 | ||
78 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 | ||
79 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 | ||
80 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x30 | ||
81 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x40 | ||
82 | #define BF_APBH_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
83 | #define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
84 | |||
85 | /** | ||
86 | * Register: HW_APBH_CTRL1 | ||
87 | * Address: 0x10 | ||
88 | * SCT: yes | ||
89 | */ | ||
90 | #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0)) | ||
91 | #define HW_APBH_CTRL1_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4)) | ||
92 | #define HW_APBH_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8)) | ||
93 | #define HW_APBH_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc)) | ||
94 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 16 | ||
95 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff0000 | ||
96 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000) | ||
97 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
98 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
99 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
100 | |||
101 | /** | ||
102 | * Register: HW_APBH_DEVSEL | ||
103 | * Address: 0x20 | ||
104 | * SCT: no | ||
105 | */ | ||
106 | #define HW_APBH_DEVSEL (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20)) | ||
107 | #define BP_APBH_DEVSEL_CH7 28 | ||
108 | #define BM_APBH_DEVSEL_CH7 0xf0000000 | ||
109 | #define BF_APBH_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
110 | #define BP_APBH_DEVSEL_CH6 24 | ||
111 | #define BM_APBH_DEVSEL_CH6 0xf000000 | ||
112 | #define BF_APBH_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
113 | #define BP_APBH_DEVSEL_CH5 20 | ||
114 | #define BM_APBH_DEVSEL_CH5 0xf00000 | ||
115 | #define BF_APBH_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
116 | #define BP_APBH_DEVSEL_CH4 16 | ||
117 | #define BM_APBH_DEVSEL_CH4 0xf0000 | ||
118 | #define BF_APBH_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
119 | #define BP_APBH_DEVSEL_CH3 12 | ||
120 | #define BM_APBH_DEVSEL_CH3 0xf000 | ||
121 | #define BF_APBH_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
122 | #define BP_APBH_DEVSEL_CH2 8 | ||
123 | #define BM_APBH_DEVSEL_CH2 0xf00 | ||
124 | #define BF_APBH_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
125 | #define BP_APBH_DEVSEL_CH1 4 | ||
126 | #define BM_APBH_DEVSEL_CH1 0xf0 | ||
127 | #define BF_APBH_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
128 | #define BP_APBH_DEVSEL_CH0 0 | ||
129 | #define BM_APBH_DEVSEL_CH0 0xf | ||
130 | #define BF_APBH_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
131 | |||
132 | /** | ||
133 | * Register: HW_APBH_CHn_DEBUG2 | ||
134 | * Address: 0x90+n*0x70 | ||
135 | * SCT: no | ||
136 | */ | ||
137 | #define HW_APBH_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70)) | ||
138 | #define BP_APBH_CHn_DEBUG2_APB_BYTES 16 | ||
139 | #define BM_APBH_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
140 | #define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
141 | #define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 | ||
142 | #define BM_APBH_CHn_DEBUG2_AHB_BYTES 0xffff | ||
143 | #define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
144 | |||
145 | /** | ||
146 | * Register: HW_APBH_CHn_CURCMDAR | ||
147 | * Address: 0x30+n*0x70 | ||
148 | * SCT: no | ||
149 | */ | ||
150 | #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30+(n)*0x70)) | ||
151 | #define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 | ||
152 | #define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
153 | #define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
154 | |||
155 | /** | ||
156 | * Register: HW_APBH_CHn_BAR | ||
157 | * Address: 0x60+n*0x70 | ||
158 | * SCT: no | ||
159 | */ | ||
160 | #define HW_APBH_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70)) | ||
161 | #define BP_APBH_CHn_BAR_ADDRESS 0 | ||
162 | #define BM_APBH_CHn_BAR_ADDRESS 0xffffffff | ||
163 | #define BF_APBH_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_APBH_CHn_CMD | ||
167 | * Address: 0x50+n*0x70 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_APBH_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70)) | ||
171 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
172 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xffff0000 | ||
173 | #define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
174 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
175 | #define BM_APBH_CHn_CMD_CMDWORDS 0xf000 | ||
176 | #define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
177 | #define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 | ||
178 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x80 | ||
179 | #define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
180 | #define BP_APBH_CHn_CMD_SEMAPHORE 6 | ||
181 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x40 | ||
182 | #define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
183 | #define BP_APBH_CHn_CMD_NANDWAIT4READY 5 | ||
184 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x20 | ||
185 | #define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & 0x20) | ||
186 | #define BP_APBH_CHn_CMD_NANDLOCK 4 | ||
187 | #define BM_APBH_CHn_CMD_NANDLOCK 0x10 | ||
188 | #define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & 0x10) | ||
189 | #define BP_APBH_CHn_CMD_IRQONCMPLT 3 | ||
190 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x8 | ||
191 | #define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
192 | #define BP_APBH_CHn_CMD_CHAIN 2 | ||
193 | #define BM_APBH_CHn_CMD_CHAIN 0x4 | ||
194 | #define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
195 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
196 | #define BM_APBH_CHn_CMD_COMMAND 0x3 | ||
197 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
198 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
199 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
200 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 | ||
201 | #define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
202 | #define BF_APBH_CHn_CMD_COMMAND_V(v) ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
203 | |||
204 | /** | ||
205 | * Register: HW_APBH_CHn_NXTCMDAR | ||
206 | * Address: 0x40+n*0x70 | ||
207 | * SCT: no | ||
208 | */ | ||
209 | #define HW_APBH_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70)) | ||
210 | #define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 | ||
211 | #define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
212 | #define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
213 | |||
214 | /** | ||
215 | * Register: HW_APBH_CHn_SEMA | ||
216 | * Address: 0x70+n*0x70 | ||
217 | * SCT: no | ||
218 | */ | ||
219 | #define HW_APBH_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70)) | ||
220 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
221 | #define BM_APBH_CHn_SEMA_PHORE 0xff0000 | ||
222 | #define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
223 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
224 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0xff | ||
225 | #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
226 | |||
227 | /** | ||
228 | * Register: HW_APBH_CHn_DEBUG1 | ||
229 | * Address: 0x80+n*0x70 | ||
230 | * SCT: no | ||
231 | */ | ||
232 | #define HW_APBH_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70)) | ||
233 | #define BP_APBH_CHn_DEBUG1_REQ 31 | ||
234 | #define BM_APBH_CHn_DEBUG1_REQ 0x80000000 | ||
235 | #define BF_APBH_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
236 | #define BP_APBH_CHn_DEBUG1_BURST 30 | ||
237 | #define BM_APBH_CHn_DEBUG1_BURST 0x40000000 | ||
238 | #define BF_APBH_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
239 | #define BP_APBH_CHn_DEBUG1_KICK 29 | ||
240 | #define BM_APBH_CHn_DEBUG1_KICK 0x20000000 | ||
241 | #define BF_APBH_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
242 | #define BP_APBH_CHn_DEBUG1_END 28 | ||
243 | #define BM_APBH_CHn_DEBUG1_END 0x10000000 | ||
244 | #define BF_APBH_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
245 | #define BP_APBH_CHn_DEBUG1_RSVD2 25 | ||
246 | #define BM_APBH_CHn_DEBUG1_RSVD2 0xe000000 | ||
247 | #define BF_APBH_CHn_DEBUG1_RSVD2(v) (((v) << 25) & 0xe000000) | ||
248 | #define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
249 | #define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
250 | #define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
251 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
252 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
253 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
254 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
255 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
256 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
257 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
258 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
259 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
260 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
261 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
262 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
263 | #define BP_APBH_CHn_DEBUG1_RSVD1 5 | ||
264 | #define BM_APBH_CHn_DEBUG1_RSVD1 0xfffe0 | ||
265 | #define BF_APBH_CHn_DEBUG1_RSVD1(v) (((v) << 5) & 0xfffe0) | ||
266 | #define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 | ||
267 | #define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x1f | ||
268 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
269 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
270 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
271 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
272 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
273 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
274 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
275 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
276 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
277 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
278 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
279 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
280 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
281 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
282 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
283 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
284 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
285 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
286 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
287 | |||
288 | #endif /* __HEADERGEN__STMP3600__APBH__H__ */ | ||