diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-power.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-power.h | 581 |
1 files changed, 581 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-power.h b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h new file mode 100644 index 0000000000..85116c79cb --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h | |||
@@ -0,0 +1,581 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__POWER__H__ | ||
24 | #define __HEADERGEN__STMP3700__POWER__H__ | ||
25 | |||
26 | #define REGS_POWER_BASE (0x80044000) | ||
27 | |||
28 | #define REGS_POWER_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_POWER_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_POWER_CTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0)) | ||
36 | #define HW_POWER_CTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4)) | ||
37 | #define HW_POWER_CTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8)) | ||
38 | #define HW_POWER_CTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc)) | ||
39 | #define BP_POWER_CTRL_CLKGATE 30 | ||
40 | #define BM_POWER_CTRL_CLKGATE 0x40000000 | ||
41 | #define BF_POWER_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
42 | #define BP_POWER_CTRL_PSWITCH_IRQ 22 | ||
43 | #define BM_POWER_CTRL_PSWITCH_IRQ 0x400000 | ||
44 | #define BF_POWER_CTRL_PSWITCH_IRQ(v) (((v) << 22) & 0x400000) | ||
45 | #define BP_POWER_CTRL_PSWITCH_IRQ_SRC 21 | ||
46 | #define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x200000 | ||
47 | #define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v) (((v) << 21) & 0x200000) | ||
48 | #define BP_POWER_CTRL_POLARITY_PSWITCH 20 | ||
49 | #define BM_POWER_CTRL_POLARITY_PSWITCH 0x100000 | ||
50 | #define BF_POWER_CTRL_POLARITY_PSWITCH(v) (((v) << 20) & 0x100000) | ||
51 | #define BP_POWER_CTRL_ENIRQ_PSWITCH 19 | ||
52 | #define BM_POWER_CTRL_ENIRQ_PSWITCH 0x80000 | ||
53 | #define BF_POWER_CTRL_ENIRQ_PSWITCH(v) (((v) << 19) & 0x80000) | ||
54 | #define BP_POWER_CTRL_POLARITY_LINREG_OK 18 | ||
55 | #define BM_POWER_CTRL_POLARITY_LINREG_OK 0x40000 | ||
56 | #define BF_POWER_CTRL_POLARITY_LINREG_OK(v) (((v) << 18) & 0x40000) | ||
57 | #define BP_POWER_CTRL_LINREG_OK_IRQ 17 | ||
58 | #define BM_POWER_CTRL_LINREG_OK_IRQ 0x20000 | ||
59 | #define BF_POWER_CTRL_LINREG_OK_IRQ(v) (((v) << 17) & 0x20000) | ||
60 | #define BP_POWER_CTRL_ENIRQ_LINREG_OK 16 | ||
61 | #define BM_POWER_CTRL_ENIRQ_LINREG_OK 0x10000 | ||
62 | #define BF_POWER_CTRL_ENIRQ_LINREG_OK(v) (((v) << 16) & 0x10000) | ||
63 | #define BP_POWER_CTRL_DC_OK_IRQ 15 | ||
64 | #define BM_POWER_CTRL_DC_OK_IRQ 0x8000 | ||
65 | #define BF_POWER_CTRL_DC_OK_IRQ(v) (((v) << 15) & 0x8000) | ||
66 | #define BP_POWER_CTRL_ENIRQ_DC_OK 14 | ||
67 | #define BM_POWER_CTRL_ENIRQ_DC_OK 0x4000 | ||
68 | #define BF_POWER_CTRL_ENIRQ_DC_OK(v) (((v) << 14) & 0x4000) | ||
69 | #define BP_POWER_CTRL_BATT_BO_IRQ 13 | ||
70 | #define BM_POWER_CTRL_BATT_BO_IRQ 0x2000 | ||
71 | #define BF_POWER_CTRL_BATT_BO_IRQ(v) (((v) << 13) & 0x2000) | ||
72 | #define BP_POWER_CTRL_ENIRQBATT_BO 12 | ||
73 | #define BM_POWER_CTRL_ENIRQBATT_BO 0x1000 | ||
74 | #define BF_POWER_CTRL_ENIRQBATT_BO(v) (((v) << 12) & 0x1000) | ||
75 | #define BP_POWER_CTRL_VDDIO_BO_IRQ 11 | ||
76 | #define BM_POWER_CTRL_VDDIO_BO_IRQ 0x800 | ||
77 | #define BF_POWER_CTRL_VDDIO_BO_IRQ(v) (((v) << 11) & 0x800) | ||
78 | #define BP_POWER_CTRL_ENIRQ_VDDIO_BO 10 | ||
79 | #define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x400 | ||
80 | #define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v) (((v) << 10) & 0x400) | ||
81 | #define BP_POWER_CTRL_VDDA_BO_IRQ 9 | ||
82 | #define BM_POWER_CTRL_VDDA_BO_IRQ 0x200 | ||
83 | #define BF_POWER_CTRL_VDDA_BO_IRQ(v) (((v) << 9) & 0x200) | ||
84 | #define BP_POWER_CTRL_ENIRQ_VDDA_BO 8 | ||
85 | #define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x100 | ||
86 | #define BF_POWER_CTRL_ENIRQ_VDDA_BO(v) (((v) << 8) & 0x100) | ||
87 | #define BP_POWER_CTRL_VDDD_BO_IRQ 7 | ||
88 | #define BM_POWER_CTRL_VDDD_BO_IRQ 0x80 | ||
89 | #define BF_POWER_CTRL_VDDD_BO_IRQ(v) (((v) << 7) & 0x80) | ||
90 | #define BP_POWER_CTRL_ENIRQ_VDDD_BO 6 | ||
91 | #define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x40 | ||
92 | #define BF_POWER_CTRL_ENIRQ_VDDD_BO(v) (((v) << 6) & 0x40) | ||
93 | #define BP_POWER_CTRL_POLARITY_VBUSVALID 5 | ||
94 | #define BM_POWER_CTRL_POLARITY_VBUSVALID 0x20 | ||
95 | #define BF_POWER_CTRL_POLARITY_VBUSVALID(v) (((v) << 5) & 0x20) | ||
96 | #define BP_POWER_CTRL_VBUSVALID_IRQ 4 | ||
97 | #define BM_POWER_CTRL_VBUSVALID_IRQ 0x10 | ||
98 | #define BF_POWER_CTRL_VBUSVALID_IRQ(v) (((v) << 4) & 0x10) | ||
99 | #define BP_POWER_CTRL_ENIRQ_VBUS_VALID 3 | ||
100 | #define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x8 | ||
101 | #define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v) (((v) << 3) & 0x8) | ||
102 | #define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 2 | ||
103 | #define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x4 | ||
104 | #define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v) (((v) << 2) & 0x4) | ||
105 | #define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 1 | ||
106 | #define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x2 | ||
107 | #define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v) (((v) << 1) & 0x2) | ||
108 | #define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 | ||
109 | #define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x1 | ||
110 | #define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v) (((v) << 0) & 0x1) | ||
111 | |||
112 | /** | ||
113 | * Register: HW_POWER_5VCTRL | ||
114 | * Address: 0x10 | ||
115 | * SCT: yes | ||
116 | */ | ||
117 | #define HW_POWER_5VCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0)) | ||
118 | #define HW_POWER_5VCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4)) | ||
119 | #define HW_POWER_5VCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8)) | ||
120 | #define HW_POWER_5VCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc)) | ||
121 | #define BP_POWER_5VCTRL_VBUSVALID_TRSH 10 | ||
122 | #define BM_POWER_5VCTRL_VBUSVALID_TRSH 0xc00 | ||
123 | #define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) (((v) << 10) & 0xc00) | ||
124 | #define BP_POWER_5VCTRL_PWDN_5VBRNOUT 8 | ||
125 | #define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x100 | ||
126 | #define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v) (((v) << 8) & 0x100) | ||
127 | #define BP_POWER_5VCTRL_ENABLE_ILIMIT 7 | ||
128 | #define BM_POWER_5VCTRL_ENABLE_ILIMIT 0x80 | ||
129 | #define BF_POWER_5VCTRL_ENABLE_ILIMIT(v) (((v) << 7) & 0x80) | ||
130 | #define BP_POWER_5VCTRL_DCDC_XFER 6 | ||
131 | #define BM_POWER_5VCTRL_DCDC_XFER 0x40 | ||
132 | #define BF_POWER_5VCTRL_DCDC_XFER(v) (((v) << 6) & 0x40) | ||
133 | #define BP_POWER_5VCTRL_EN_BATT_PULLDN 5 | ||
134 | #define BM_POWER_5VCTRL_EN_BATT_PULLDN 0x20 | ||
135 | #define BF_POWER_5VCTRL_EN_BATT_PULLDN(v) (((v) << 5) & 0x20) | ||
136 | #define BP_POWER_5VCTRL_VBUSVALID_5VDETECT 4 | ||
137 | #define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x10 | ||
138 | #define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v) (((v) << 4) & 0x10) | ||
139 | #define BP_POWER_5VCTRL_VBUSVALID_TO_B 3 | ||
140 | #define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x8 | ||
141 | #define BF_POWER_5VCTRL_VBUSVALID_TO_B(v) (((v) << 3) & 0x8) | ||
142 | #define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO 2 | ||
143 | #define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x4 | ||
144 | #define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v) (((v) << 2) & 0x4) | ||
145 | #define BP_POWER_5VCTRL_OTG_PWRUP_CMPS 1 | ||
146 | #define BM_POWER_5VCTRL_OTG_PWRUP_CMPS 0x2 | ||
147 | #define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v) (((v) << 1) & 0x2) | ||
148 | #define BP_POWER_5VCTRL_ENABLE_DCDC 0 | ||
149 | #define BM_POWER_5VCTRL_ENABLE_DCDC 0x1 | ||
150 | #define BF_POWER_5VCTRL_ENABLE_DCDC(v) (((v) << 0) & 0x1) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_POWER_MINPWR | ||
154 | * Address: 0x20 | ||
155 | * SCT: yes | ||
156 | */ | ||
157 | #define HW_POWER_MINPWR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0)) | ||
158 | #define HW_POWER_MINPWR_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4)) | ||
159 | #define HW_POWER_MINPWR_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8)) | ||
160 | #define HW_POWER_MINPWR_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc)) | ||
161 | #define BP_POWER_MINPWR_PWD_BO 11 | ||
162 | #define BM_POWER_MINPWR_PWD_BO 0x800 | ||
163 | #define BF_POWER_MINPWR_PWD_BO(v) (((v) << 11) & 0x800) | ||
164 | #define BP_POWER_MINPWR_USB_I_SUSPEND 10 | ||
165 | #define BM_POWER_MINPWR_USB_I_SUSPEND 0x400 | ||
166 | #define BF_POWER_MINPWR_USB_I_SUSPEND(v) (((v) << 10) & 0x400) | ||
167 | #define BP_POWER_MINPWR_ENABLE_OSC 9 | ||
168 | #define BM_POWER_MINPWR_ENABLE_OSC 0x200 | ||
169 | #define BF_POWER_MINPWR_ENABLE_OSC(v) (((v) << 9) & 0x200) | ||
170 | #define BP_POWER_MINPWR_SELECT_OSC 8 | ||
171 | #define BM_POWER_MINPWR_SELECT_OSC 0x100 | ||
172 | #define BF_POWER_MINPWR_SELECT_OSC(v) (((v) << 8) & 0x100) | ||
173 | #define BP_POWER_MINPWR_VBG_OFF 7 | ||
174 | #define BM_POWER_MINPWR_VBG_OFF 0x80 | ||
175 | #define BF_POWER_MINPWR_VBG_OFF(v) (((v) << 7) & 0x80) | ||
176 | #define BP_POWER_MINPWR_DOUBLE_FETS 6 | ||
177 | #define BM_POWER_MINPWR_DOUBLE_FETS 0x40 | ||
178 | #define BF_POWER_MINPWR_DOUBLE_FETS(v) (((v) << 6) & 0x40) | ||
179 | #define BP_POWER_MINPWR_HALF_FETS 5 | ||
180 | #define BM_POWER_MINPWR_HALF_FETS 0x20 | ||
181 | #define BF_POWER_MINPWR_HALF_FETS(v) (((v) << 5) & 0x20) | ||
182 | #define BP_POWER_MINPWR_LESSANA_I 4 | ||
183 | #define BM_POWER_MINPWR_LESSANA_I 0x10 | ||
184 | #define BF_POWER_MINPWR_LESSANA_I(v) (((v) << 4) & 0x10) | ||
185 | #define BP_POWER_MINPWR_PWD_XTAL24 3 | ||
186 | #define BM_POWER_MINPWR_PWD_XTAL24 0x8 | ||
187 | #define BF_POWER_MINPWR_PWD_XTAL24(v) (((v) << 3) & 0x8) | ||
188 | #define BP_POWER_MINPWR_DC_STOPCLK 2 | ||
189 | #define BM_POWER_MINPWR_DC_STOPCLK 0x4 | ||
190 | #define BF_POWER_MINPWR_DC_STOPCLK(v) (((v) << 2) & 0x4) | ||
191 | #define BP_POWER_MINPWR_EN_DC_PFM 1 | ||
192 | #define BM_POWER_MINPWR_EN_DC_PFM 0x2 | ||
193 | #define BF_POWER_MINPWR_EN_DC_PFM(v) (((v) << 1) & 0x2) | ||
194 | #define BP_POWER_MINPWR_DC_HALFCLK 0 | ||
195 | #define BM_POWER_MINPWR_DC_HALFCLK 0x1 | ||
196 | #define BF_POWER_MINPWR_DC_HALFCLK(v) (((v) << 0) & 0x1) | ||
197 | |||
198 | /** | ||
199 | * Register: HW_POWER_CHARGE | ||
200 | * Address: 0x30 | ||
201 | * SCT: yes | ||
202 | */ | ||
203 | #define HW_POWER_CHARGE (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0)) | ||
204 | #define HW_POWER_CHARGE_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4)) | ||
205 | #define HW_POWER_CHARGE_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8)) | ||
206 | #define HW_POWER_CHARGE_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc)) | ||
207 | #define BP_POWER_CHARGE_ENABLE_FAULT_DETECT 20 | ||
208 | #define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x100000 | ||
209 | #define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v) (((v) << 20) & 0x100000) | ||
210 | #define BP_POWER_CHARGE_CHRG_STS_OFF 19 | ||
211 | #define BM_POWER_CHARGE_CHRG_STS_OFF 0x80000 | ||
212 | #define BF_POWER_CHARGE_CHRG_STS_OFF(v) (((v) << 19) & 0x80000) | ||
213 | #define BP_POWER_CHARGE_USE_EXTERN_R 17 | ||
214 | #define BM_POWER_CHARGE_USE_EXTERN_R 0x20000 | ||
215 | #define BF_POWER_CHARGE_USE_EXTERN_R(v) (((v) << 17) & 0x20000) | ||
216 | #define BP_POWER_CHARGE_PWD_BATTCHRG 16 | ||
217 | #define BM_POWER_CHARGE_PWD_BATTCHRG 0x10000 | ||
218 | #define BF_POWER_CHARGE_PWD_BATTCHRG(v) (((v) << 16) & 0x10000) | ||
219 | #define BP_POWER_CHARGE_STOP_ILIMIT 8 | ||
220 | #define BM_POWER_CHARGE_STOP_ILIMIT 0xf00 | ||
221 | #define BF_POWER_CHARGE_STOP_ILIMIT(v) (((v) << 8) & 0xf00) | ||
222 | #define BP_POWER_CHARGE_BATTCHRG_I 0 | ||
223 | #define BM_POWER_CHARGE_BATTCHRG_I 0x3f | ||
224 | #define BF_POWER_CHARGE_BATTCHRG_I(v) (((v) << 0) & 0x3f) | ||
225 | |||
226 | /** | ||
227 | * Register: HW_POWER_VDDDCTRL | ||
228 | * Address: 0x40 | ||
229 | * SCT: no | ||
230 | */ | ||
231 | #define HW_POWER_VDDDCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40)) | ||
232 | #define BP_POWER_VDDDCTRL_ADJTN 28 | ||
233 | #define BM_POWER_VDDDCTRL_ADJTN 0xf0000000 | ||
234 | #define BF_POWER_VDDDCTRL_ADJTN(v) (((v) << 28) & 0xf0000000) | ||
235 | #define BP_POWER_VDDDCTRL_ALKALINE_CHARGE 24 | ||
236 | #define BM_POWER_VDDDCTRL_ALKALINE_CHARGE 0x1000000 | ||
237 | #define BF_POWER_VDDDCTRL_ALKALINE_CHARGE(v) (((v) << 24) & 0x1000000) | ||
238 | #define BP_POWER_VDDDCTRL_DISABLE_STEPPING 23 | ||
239 | #define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x800000 | ||
240 | #define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v) (((v) << 23) & 0x800000) | ||
241 | #define BP_POWER_VDDDCTRL_LINREG_FROM_BATT 22 | ||
242 | #define BM_POWER_VDDDCTRL_LINREG_FROM_BATT 0x400000 | ||
243 | #define BF_POWER_VDDDCTRL_LINREG_FROM_BATT(v) (((v) << 22) & 0x400000) | ||
244 | #define BP_POWER_VDDDCTRL_ENABLE_LINREG 21 | ||
245 | #define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x200000 | ||
246 | #define BF_POWER_VDDDCTRL_ENABLE_LINREG(v) (((v) << 21) & 0x200000) | ||
247 | #define BP_POWER_VDDDCTRL_DISABLE_FET 20 | ||
248 | #define BM_POWER_VDDDCTRL_DISABLE_FET 0x100000 | ||
249 | #define BF_POWER_VDDDCTRL_DISABLE_FET(v) (((v) << 20) & 0x100000) | ||
250 | #define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 | ||
251 | #define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x30000 | ||
252 | #define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) (((v) << 16) & 0x30000) | ||
253 | #define BP_POWER_VDDDCTRL_BO_OFFSET 8 | ||
254 | #define BM_POWER_VDDDCTRL_BO_OFFSET 0x700 | ||
255 | #define BF_POWER_VDDDCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
256 | #define BP_POWER_VDDDCTRL_TRG 0 | ||
257 | #define BM_POWER_VDDDCTRL_TRG 0x1f | ||
258 | #define BF_POWER_VDDDCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
259 | |||
260 | /** | ||
261 | * Register: HW_POWER_VDDACTRL | ||
262 | * Address: 0x50 | ||
263 | * SCT: no | ||
264 | */ | ||
265 | #define HW_POWER_VDDACTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50)) | ||
266 | #define BP_POWER_VDDACTRL_DISABLE_STEPPING 18 | ||
267 | #define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x40000 | ||
268 | #define BF_POWER_VDDACTRL_DISABLE_STEPPING(v) (((v) << 18) & 0x40000) | ||
269 | #define BP_POWER_VDDACTRL_ENABLE_LINREG 17 | ||
270 | #define BM_POWER_VDDACTRL_ENABLE_LINREG 0x20000 | ||
271 | #define BF_POWER_VDDACTRL_ENABLE_LINREG(v) (((v) << 17) & 0x20000) | ||
272 | #define BP_POWER_VDDACTRL_DISABLE_FET 16 | ||
273 | #define BM_POWER_VDDACTRL_DISABLE_FET 0x10000 | ||
274 | #define BF_POWER_VDDACTRL_DISABLE_FET(v) (((v) << 16) & 0x10000) | ||
275 | #define BP_POWER_VDDACTRL_LINREG_OFFSET 12 | ||
276 | #define BM_POWER_VDDACTRL_LINREG_OFFSET 0x3000 | ||
277 | #define BF_POWER_VDDACTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
278 | #define BP_POWER_VDDACTRL_BO_OFFSET 8 | ||
279 | #define BM_POWER_VDDACTRL_BO_OFFSET 0x700 | ||
280 | #define BF_POWER_VDDACTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
281 | #define BP_POWER_VDDACTRL_TRG 0 | ||
282 | #define BM_POWER_VDDACTRL_TRG 0x1f | ||
283 | #define BF_POWER_VDDACTRL_TRG(v) (((v) << 0) & 0x1f) | ||
284 | |||
285 | /** | ||
286 | * Register: HW_POWER_VDDIOCTRL | ||
287 | * Address: 0x60 | ||
288 | * SCT: no | ||
289 | */ | ||
290 | #define HW_POWER_VDDIOCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60)) | ||
291 | #define BP_POWER_VDDIOCTRL_ADJTN 16 | ||
292 | #define BM_POWER_VDDIOCTRL_ADJTN 0xf0000 | ||
293 | #define BF_POWER_VDDIOCTRL_ADJTN(v) (((v) << 16) & 0xf0000) | ||
294 | #define BP_POWER_VDDIOCTRL_DISABLE_STEPPING 15 | ||
295 | #define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x8000 | ||
296 | #define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v) (((v) << 15) & 0x8000) | ||
297 | #define BP_POWER_VDDIOCTRL_DISABLE_FET 14 | ||
298 | #define BM_POWER_VDDIOCTRL_DISABLE_FET 0x4000 | ||
299 | #define BF_POWER_VDDIOCTRL_DISABLE_FET(v) (((v) << 14) & 0x4000) | ||
300 | #define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 | ||
301 | #define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x3000 | ||
302 | #define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
303 | #define BP_POWER_VDDIOCTRL_BO_OFFSET 8 | ||
304 | #define BM_POWER_VDDIOCTRL_BO_OFFSET 0x700 | ||
305 | #define BF_POWER_VDDIOCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
306 | #define BP_POWER_VDDIOCTRL_TRG 0 | ||
307 | #define BM_POWER_VDDIOCTRL_TRG 0x1f | ||
308 | #define BF_POWER_VDDIOCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
309 | |||
310 | /** | ||
311 | * Register: HW_POWER_DCFUNCV | ||
312 | * Address: 0x70 | ||
313 | * SCT: no | ||
314 | */ | ||
315 | #define HW_POWER_DCFUNCV (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70)) | ||
316 | #define BP_POWER_DCFUNCV_VDDD 16 | ||
317 | #define BM_POWER_DCFUNCV_VDDD 0x3ff0000 | ||
318 | #define BF_POWER_DCFUNCV_VDDD(v) (((v) << 16) & 0x3ff0000) | ||
319 | #define BP_POWER_DCFUNCV_VDDIO 0 | ||
320 | #define BM_POWER_DCFUNCV_VDDIO 0x3ff | ||
321 | #define BF_POWER_DCFUNCV_VDDIO(v) (((v) << 0) & 0x3ff) | ||
322 | |||
323 | /** | ||
324 | * Register: HW_POWER_MISC | ||
325 | * Address: 0x80 | ||
326 | * SCT: no | ||
327 | */ | ||
328 | #define HW_POWER_MISC (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80)) | ||
329 | #define BP_POWER_MISC_FREQSEL 4 | ||
330 | #define BM_POWER_MISC_FREQSEL 0x30 | ||
331 | #define BF_POWER_MISC_FREQSEL(v) (((v) << 4) & 0x30) | ||
332 | #define BP_POWER_MISC_DELAY_TIMING 3 | ||
333 | #define BM_POWER_MISC_DELAY_TIMING 0x8 | ||
334 | #define BF_POWER_MISC_DELAY_TIMING(v) (((v) << 3) & 0x8) | ||
335 | #define BP_POWER_MISC_TEST 2 | ||
336 | #define BM_POWER_MISC_TEST 0x4 | ||
337 | #define BF_POWER_MISC_TEST(v) (((v) << 2) & 0x4) | ||
338 | #define BP_POWER_MISC_SEL_PLLCLK 1 | ||
339 | #define BM_POWER_MISC_SEL_PLLCLK 0x2 | ||
340 | #define BF_POWER_MISC_SEL_PLLCLK(v) (((v) << 1) & 0x2) | ||
341 | #define BP_POWER_MISC_PERIPHERALSWOFF 0 | ||
342 | #define BM_POWER_MISC_PERIPHERALSWOFF 0x1 | ||
343 | #define BF_POWER_MISC_PERIPHERALSWOFF(v) (((v) << 0) & 0x1) | ||
344 | |||
345 | /** | ||
346 | * Register: HW_POWER_DCLIMITS | ||
347 | * Address: 0x90 | ||
348 | * SCT: no | ||
349 | */ | ||
350 | #define HW_POWER_DCLIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90)) | ||
351 | #define BP_POWER_DCLIMITS_POSLIMIT_BOOST 16 | ||
352 | #define BM_POWER_DCLIMITS_POSLIMIT_BOOST 0x7f0000 | ||
353 | #define BF_POWER_DCLIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) | ||
354 | #define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 | ||
355 | #define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x7f00 | ||
356 | #define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
357 | #define BP_POWER_DCLIMITS_NEGLIMIT 0 | ||
358 | #define BM_POWER_DCLIMITS_NEGLIMIT 0x7f | ||
359 | #define BF_POWER_DCLIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
360 | |||
361 | /** | ||
362 | * Register: HW_POWER_LOOPCTRL | ||
363 | * Address: 0xa0 | ||
364 | * SCT: yes | ||
365 | */ | ||
366 | #define HW_POWER_LOOPCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0)) | ||
367 | #define HW_POWER_LOOPCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4)) | ||
368 | #define HW_POWER_LOOPCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8)) | ||
369 | #define HW_POWER_LOOPCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc)) | ||
370 | #define BP_POWER_LOOPCTRL_TOGGLE_DIF 20 | ||
371 | #define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x100000 | ||
372 | #define BF_POWER_LOOPCTRL_TOGGLE_DIF(v) (((v) << 20) & 0x100000) | ||
373 | #define BP_POWER_LOOPCTRL_HYST_SIGN 19 | ||
374 | #define BM_POWER_LOOPCTRL_HYST_SIGN 0x80000 | ||
375 | #define BF_POWER_LOOPCTRL_HYST_SIGN(v) (((v) << 19) & 0x80000) | ||
376 | #define BP_POWER_LOOPCTRL_EN_CM_HYST 18 | ||
377 | #define BM_POWER_LOOPCTRL_EN_CM_HYST 0x40000 | ||
378 | #define BF_POWER_LOOPCTRL_EN_CM_HYST(v) (((v) << 18) & 0x40000) | ||
379 | #define BP_POWER_LOOPCTRL_EN_DF_HYST 17 | ||
380 | #define BM_POWER_LOOPCTRL_EN_DF_HYST 0x20000 | ||
381 | #define BF_POWER_LOOPCTRL_EN_DF_HYST(v) (((v) << 17) & 0x20000) | ||
382 | #define BP_POWER_LOOPCTRL_CM_HYST_THRESH 16 | ||
383 | #define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x10000 | ||
384 | #define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000) | ||
385 | #define BP_POWER_LOOPCTRL_DF_HYST_THRESH 15 | ||
386 | #define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x8000 | ||
387 | #define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000) | ||
388 | #define BP_POWER_LOOPCTRL_RCSCALE_THRESH 14 | ||
389 | #define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x4000 | ||
390 | #define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000) | ||
391 | #define BP_POWER_LOOPCTRL_EN_RCSCALE 12 | ||
392 | #define BM_POWER_LOOPCTRL_EN_RCSCALE 0x3000 | ||
393 | #define BF_POWER_LOOPCTRL_EN_RCSCALE(v) (((v) << 12) & 0x3000) | ||
394 | #define BP_POWER_LOOPCTRL_DC_FF 8 | ||
395 | #define BM_POWER_LOOPCTRL_DC_FF 0x700 | ||
396 | #define BF_POWER_LOOPCTRL_DC_FF(v) (((v) << 8) & 0x700) | ||
397 | #define BP_POWER_LOOPCTRL_DC_R 4 | ||
398 | #define BM_POWER_LOOPCTRL_DC_R 0xf0 | ||
399 | #define BF_POWER_LOOPCTRL_DC_R(v) (((v) << 4) & 0xf0) | ||
400 | #define BP_POWER_LOOPCTRL_DC_C 0 | ||
401 | #define BM_POWER_LOOPCTRL_DC_C 0x3 | ||
402 | #define BF_POWER_LOOPCTRL_DC_C(v) (((v) << 0) & 0x3) | ||
403 | |||
404 | /** | ||
405 | * Register: HW_POWER_STS | ||
406 | * Address: 0xb0 | ||
407 | * SCT: no | ||
408 | */ | ||
409 | #define HW_POWER_STS (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0)) | ||
410 | #define BP_POWER_STS_BATT_CHRG_PRESENT 31 | ||
411 | #define BM_POWER_STS_BATT_CHRG_PRESENT 0x80000000 | ||
412 | #define BF_POWER_STS_BATT_CHRG_PRESENT(v) (((v) << 31) & 0x80000000) | ||
413 | #define BP_POWER_STS_PSWITCH 18 | ||
414 | #define BM_POWER_STS_PSWITCH 0xc0000 | ||
415 | #define BF_POWER_STS_PSWITCH(v) (((v) << 18) & 0xc0000) | ||
416 | #define BP_POWER_STS_AVALID_STATUS 17 | ||
417 | #define BM_POWER_STS_AVALID_STATUS 0x20000 | ||
418 | #define BF_POWER_STS_AVALID_STATUS(v) (((v) << 17) & 0x20000) | ||
419 | #define BP_POWER_STS_BVALID_STATUS 16 | ||
420 | #define BM_POWER_STS_BVALID_STATUS 0x10000 | ||
421 | #define BF_POWER_STS_BVALID_STATUS(v) (((v) << 16) & 0x10000) | ||
422 | #define BP_POWER_STS_VBUSVALID_STATUS 15 | ||
423 | #define BM_POWER_STS_VBUSVALID_STATUS 0x8000 | ||
424 | #define BF_POWER_STS_VBUSVALID_STATUS(v) (((v) << 15) & 0x8000) | ||
425 | #define BP_POWER_STS_SESSEND_STATUS 14 | ||
426 | #define BM_POWER_STS_SESSEND_STATUS 0x4000 | ||
427 | #define BF_POWER_STS_SESSEND_STATUS(v) (((v) << 14) & 0x4000) | ||
428 | #define BP_POWER_STS_MODE 13 | ||
429 | #define BM_POWER_STS_MODE 0x2000 | ||
430 | #define BF_POWER_STS_MODE(v) (((v) << 13) & 0x2000) | ||
431 | #define BP_POWER_STS_BATT_BO 12 | ||
432 | #define BM_POWER_STS_BATT_BO 0x1000 | ||
433 | #define BF_POWER_STS_BATT_BO(v) (((v) << 12) & 0x1000) | ||
434 | #define BP_POWER_STS_VDD5V_FAULT 11 | ||
435 | #define BM_POWER_STS_VDD5V_FAULT 0x800 | ||
436 | #define BF_POWER_STS_VDD5V_FAULT(v) (((v) << 11) & 0x800) | ||
437 | #define BP_POWER_STS_CHRGSTS 10 | ||
438 | #define BM_POWER_STS_CHRGSTS 0x400 | ||
439 | #define BF_POWER_STS_CHRGSTS(v) (((v) << 10) & 0x400) | ||
440 | #define BP_POWER_STS_LINREG_OK 9 | ||
441 | #define BM_POWER_STS_LINREG_OK 0x200 | ||
442 | #define BF_POWER_STS_LINREG_OK(v) (((v) << 9) & 0x200) | ||
443 | #define BP_POWER_STS_DC_OK 8 | ||
444 | #define BM_POWER_STS_DC_OK 0x100 | ||
445 | #define BF_POWER_STS_DC_OK(v) (((v) << 8) & 0x100) | ||
446 | #define BP_POWER_STS_VDDIO_BO 7 | ||
447 | #define BM_POWER_STS_VDDIO_BO 0x80 | ||
448 | #define BF_POWER_STS_VDDIO_BO(v) (((v) << 7) & 0x80) | ||
449 | #define BP_POWER_STS_VDDA_BO 6 | ||
450 | #define BM_POWER_STS_VDDA_BO 0x40 | ||
451 | #define BF_POWER_STS_VDDA_BO(v) (((v) << 6) & 0x40) | ||
452 | #define BP_POWER_STS_VDDD_BO 5 | ||
453 | #define BM_POWER_STS_VDDD_BO 0x20 | ||
454 | #define BF_POWER_STS_VDDD_BO(v) (((v) << 5) & 0x20) | ||
455 | #define BP_POWER_STS_VDD5V_GT_VDDIO 4 | ||
456 | #define BM_POWER_STS_VDD5V_GT_VDDIO 0x10 | ||
457 | #define BF_POWER_STS_VDD5V_GT_VDDIO(v) (((v) << 4) & 0x10) | ||
458 | #define BP_POWER_STS_AVALID 3 | ||
459 | #define BM_POWER_STS_AVALID 0x8 | ||
460 | #define BF_POWER_STS_AVALID(v) (((v) << 3) & 0x8) | ||
461 | #define BP_POWER_STS_BVALID 2 | ||
462 | #define BM_POWER_STS_BVALID 0x4 | ||
463 | #define BF_POWER_STS_BVALID(v) (((v) << 2) & 0x4) | ||
464 | #define BP_POWER_STS_VBUSVALID 1 | ||
465 | #define BM_POWER_STS_VBUSVALID 0x2 | ||
466 | #define BF_POWER_STS_VBUSVALID(v) (((v) << 1) & 0x2) | ||
467 | #define BP_POWER_STS_SESSEND 0 | ||
468 | #define BM_POWER_STS_SESSEND 0x1 | ||
469 | #define BF_POWER_STS_SESSEND(v) (((v) << 0) & 0x1) | ||
470 | |||
471 | /** | ||
472 | * Register: HW_POWER_SPEED | ||
473 | * Address: 0xc0 | ||
474 | * SCT: yes | ||
475 | */ | ||
476 | #define HW_POWER_SPEED (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0)) | ||
477 | #define HW_POWER_SPEED_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4)) | ||
478 | #define HW_POWER_SPEED_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8)) | ||
479 | #define HW_POWER_SPEED_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc)) | ||
480 | #define BP_POWER_SPEED_STATUS 16 | ||
481 | #define BM_POWER_SPEED_STATUS 0xff0000 | ||
482 | #define BF_POWER_SPEED_STATUS(v) (((v) << 16) & 0xff0000) | ||
483 | #define BP_POWER_SPEED_CTRL 0 | ||
484 | #define BM_POWER_SPEED_CTRL 0x3 | ||
485 | #define BF_POWER_SPEED_CTRL(v) (((v) << 0) & 0x3) | ||
486 | |||
487 | /** | ||
488 | * Register: HW_POWER_BATTMONITOR | ||
489 | * Address: 0xd0 | ||
490 | * SCT: no | ||
491 | */ | ||
492 | #define HW_POWER_BATTMONITOR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0)) | ||
493 | #define BP_POWER_BATTMONITOR_BATT_VAL 16 | ||
494 | #define BM_POWER_BATTMONITOR_BATT_VAL 0x3ff0000 | ||
495 | #define BF_POWER_BATTMONITOR_BATT_VAL(v) (((v) << 16) & 0x3ff0000) | ||
496 | #define BP_POWER_BATTMONITOR_EN_BATADJ 6 | ||
497 | #define BM_POWER_BATTMONITOR_EN_BATADJ 0x40 | ||
498 | #define BF_POWER_BATTMONITOR_EN_BATADJ(v) (((v) << 6) & 0x40) | ||
499 | #define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT 5 | ||
500 | #define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x20 | ||
501 | #define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 5) & 0x20) | ||
502 | #define BP_POWER_BATTMONITOR_BRWNOUT_PWD 4 | ||
503 | #define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x10 | ||
504 | #define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v) (((v) << 4) & 0x10) | ||
505 | #define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 | ||
506 | #define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0xf | ||
507 | #define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) (((v) << 0) & 0xf) | ||
508 | |||
509 | /** | ||
510 | * Register: HW_POWER_RESET | ||
511 | * Address: 0xe0 | ||
512 | * SCT: yes | ||
513 | */ | ||
514 | #define HW_POWER_RESET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x0)) | ||
515 | #define HW_POWER_RESET_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x4)) | ||
516 | #define HW_POWER_RESET_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x8)) | ||
517 | #define HW_POWER_RESET_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0xc)) | ||
518 | #define BP_POWER_RESET_UNLOCK 16 | ||
519 | #define BM_POWER_RESET_UNLOCK 0xffff0000 | ||
520 | #define BV_POWER_RESET_UNLOCK__KEY 0x3e77 | ||
521 | #define BF_POWER_RESET_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
522 | #define BF_POWER_RESET_UNLOCK_V(v) ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000) | ||
523 | #define BP_POWER_RESET_PWD_OFF 1 | ||
524 | #define BM_POWER_RESET_PWD_OFF 0x2 | ||
525 | #define BF_POWER_RESET_PWD_OFF(v) (((v) << 1) & 0x2) | ||
526 | #define BP_POWER_RESET_PWD 0 | ||
527 | #define BM_POWER_RESET_PWD 0x1 | ||
528 | #define BF_POWER_RESET_PWD(v) (((v) << 0) & 0x1) | ||
529 | |||
530 | /** | ||
531 | * Register: HW_POWER_DEBUG | ||
532 | * Address: 0xf0 | ||
533 | * SCT: yes | ||
534 | */ | ||
535 | #define HW_POWER_DEBUG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x0)) | ||
536 | #define HW_POWER_DEBUG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x4)) | ||
537 | #define HW_POWER_DEBUG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x8)) | ||
538 | #define HW_POWER_DEBUG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0xc)) | ||
539 | #define BP_POWER_DEBUG_VBUSVALIDPIOLOCK 3 | ||
540 | #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x8 | ||
541 | #define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v) (((v) << 3) & 0x8) | ||
542 | #define BP_POWER_DEBUG_AVALIDPIOLOCK 2 | ||
543 | #define BM_POWER_DEBUG_AVALIDPIOLOCK 0x4 | ||
544 | #define BF_POWER_DEBUG_AVALIDPIOLOCK(v) (((v) << 2) & 0x4) | ||
545 | #define BP_POWER_DEBUG_BVALIDPIOLOCK 1 | ||
546 | #define BM_POWER_DEBUG_BVALIDPIOLOCK 0x2 | ||
547 | #define BF_POWER_DEBUG_BVALIDPIOLOCK(v) (((v) << 1) & 0x2) | ||
548 | #define BP_POWER_DEBUG_SESSENDPIOLOCK 0 | ||
549 | #define BM_POWER_DEBUG_SESSENDPIOLOCK 0x1 | ||
550 | #define BF_POWER_DEBUG_SESSENDPIOLOCK(v) (((v) << 0) & 0x1) | ||
551 | |||
552 | /** | ||
553 | * Register: HW_POWER_SPECIAL | ||
554 | * Address: 0x100 | ||
555 | * SCT: yes | ||
556 | */ | ||
557 | #define HW_POWER_SPECIAL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0)) | ||
558 | #define HW_POWER_SPECIAL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4)) | ||
559 | #define HW_POWER_SPECIAL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8)) | ||
560 | #define HW_POWER_SPECIAL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc)) | ||
561 | #define BP_POWER_SPECIAL_TEST 0 | ||
562 | #define BM_POWER_SPECIAL_TEST 0xffffffff | ||
563 | #define BF_POWER_SPECIAL_TEST(v) (((v) << 0) & 0xffffffff) | ||
564 | |||
565 | /** | ||
566 | * Register: HW_POWER_VERSION | ||
567 | * Address: 0x110 | ||
568 | * SCT: no | ||
569 | */ | ||
570 | #define HW_POWER_VERSION (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110)) | ||
571 | #define BP_POWER_VERSION_MAJOR 24 | ||
572 | #define BM_POWER_VERSION_MAJOR 0xff000000 | ||
573 | #define BF_POWER_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
574 | #define BP_POWER_VERSION_MINOR 16 | ||
575 | #define BM_POWER_VERSION_MINOR 0xff0000 | ||
576 | #define BF_POWER_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
577 | #define BP_POWER_VERSION_STEP 0 | ||
578 | #define BM_POWER_VERSION_STEP 0xffff | ||
579 | #define BF_POWER_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
580 | |||
581 | #endif /* __HEADERGEN__STMP3700__POWER__H__ */ | ||