diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h | 572 |
1 files changed, 572 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h new file mode 100644 index 0000000000..c799635306 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h | |||
@@ -0,0 +1,572 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__LRADC__H__ | ||
24 | #define __HEADERGEN__STMP3600__LRADC__H__ | ||
25 | |||
26 | #define REGS_LRADC_BASE (0x80050000) | ||
27 | |||
28 | #define REGS_LRADC_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_LRADC_CTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_LRADC_CTRL0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_LRADC_CTRL0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_LRADC_CTRL0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_LRADC_CTRL0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_LRADC_CTRL0_SFTRST 31 | ||
40 | #define BM_LRADC_CTRL0_SFTRST 0x80000000 | ||
41 | #define BF_LRADC_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_LRADC_CTRL0_CLKGATE 30 | ||
43 | #define BM_LRADC_CTRL0_CLKGATE 0x40000000 | ||
44 | #define BF_LRADC_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21 | ||
46 | #define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000 | ||
47 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 | ||
48 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 | ||
49 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) << 21) & 0x200000) | ||
50 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000) | ||
51 | #define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20 | ||
52 | #define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000 | ||
53 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 | ||
54 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 | ||
55 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) << 20) & 0x100000) | ||
56 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000) | ||
57 | #define BP_LRADC_CTRL0_YMINUS_ENABLE 19 | ||
58 | #define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000 | ||
59 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 | ||
60 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 | ||
61 | #define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) << 19) & 0x80000) | ||
62 | #define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000) | ||
63 | #define BP_LRADC_CTRL0_XMINUS_ENABLE 18 | ||
64 | #define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000 | ||
65 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 | ||
66 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 | ||
67 | #define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) << 18) & 0x40000) | ||
68 | #define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000) | ||
69 | #define BP_LRADC_CTRL0_YPLUS_ENABLE 17 | ||
70 | #define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000 | ||
71 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 | ||
72 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 | ||
73 | #define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) << 17) & 0x20000) | ||
74 | #define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000) | ||
75 | #define BP_LRADC_CTRL0_XPLUS_ENABLE 16 | ||
76 | #define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000 | ||
77 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 | ||
78 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 | ||
79 | #define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) << 16) & 0x10000) | ||
80 | #define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000) | ||
81 | #define BP_LRADC_CTRL0_SCHEDULE 0 | ||
82 | #define BM_LRADC_CTRL0_SCHEDULE 0xff | ||
83 | #define BF_LRADC_CTRL0_SCHEDULE(v) (((v) << 0) & 0xff) | ||
84 | |||
85 | /** | ||
86 | * Register: HW_LRADC_CTRL1 | ||
87 | * Address: 0x10 | ||
88 | * SCT: yes | ||
89 | */ | ||
90 | #define HW_LRADC_CTRL1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0)) | ||
91 | #define HW_LRADC_CTRL1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4)) | ||
92 | #define HW_LRADC_CTRL1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8)) | ||
93 | #define HW_LRADC_CTRL1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc)) | ||
94 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24 | ||
95 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000 | ||
96 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 | ||
97 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 | ||
98 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
99 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000) | ||
100 | #define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23 | ||
101 | #define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000 | ||
102 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 | ||
103 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 | ||
104 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) << 23) & 0x800000) | ||
105 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000) | ||
106 | #define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22 | ||
107 | #define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000 | ||
108 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 | ||
109 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 | ||
110 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
111 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000) | ||
112 | #define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21 | ||
113 | #define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000 | ||
114 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 | ||
115 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 | ||
116 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
117 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000) | ||
118 | #define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20 | ||
119 | #define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000 | ||
120 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 | ||
121 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 | ||
122 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
123 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000) | ||
124 | #define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19 | ||
125 | #define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000 | ||
126 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 | ||
127 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 | ||
128 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
129 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000) | ||
130 | #define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18 | ||
131 | #define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000 | ||
132 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 | ||
133 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 | ||
134 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
135 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000) | ||
136 | #define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17 | ||
137 | #define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000 | ||
138 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 | ||
139 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 | ||
140 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
141 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000) | ||
142 | #define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16 | ||
143 | #define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000 | ||
144 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 | ||
145 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 | ||
146 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
147 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000) | ||
148 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8 | ||
149 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100 | ||
150 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 | ||
151 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 | ||
152 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) << 8) & 0x100) | ||
153 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100) | ||
154 | #define BP_LRADC_CTRL1_LRADC7_IRQ 7 | ||
155 | #define BM_LRADC_CTRL1_LRADC7_IRQ 0x80 | ||
156 | #define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 | ||
157 | #define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 | ||
158 | #define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) << 7) & 0x80) | ||
159 | #define BF_LRADC_CTRL1_LRADC7_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80) | ||
160 | #define BP_LRADC_CTRL1_LRADC6_IRQ 6 | ||
161 | #define BM_LRADC_CTRL1_LRADC6_IRQ 0x40 | ||
162 | #define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 | ||
163 | #define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 | ||
164 | #define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) << 6) & 0x40) | ||
165 | #define BF_LRADC_CTRL1_LRADC6_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40) | ||
166 | #define BP_LRADC_CTRL1_LRADC5_IRQ 5 | ||
167 | #define BM_LRADC_CTRL1_LRADC5_IRQ 0x20 | ||
168 | #define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 | ||
169 | #define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 | ||
170 | #define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) << 5) & 0x20) | ||
171 | #define BF_LRADC_CTRL1_LRADC5_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20) | ||
172 | #define BP_LRADC_CTRL1_LRADC4_IRQ 4 | ||
173 | #define BM_LRADC_CTRL1_LRADC4_IRQ 0x10 | ||
174 | #define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 | ||
175 | #define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 | ||
176 | #define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) << 4) & 0x10) | ||
177 | #define BF_LRADC_CTRL1_LRADC4_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10) | ||
178 | #define BP_LRADC_CTRL1_LRADC3_IRQ 3 | ||
179 | #define BM_LRADC_CTRL1_LRADC3_IRQ 0x8 | ||
180 | #define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 | ||
181 | #define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 | ||
182 | #define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) << 3) & 0x8) | ||
183 | #define BF_LRADC_CTRL1_LRADC3_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8) | ||
184 | #define BP_LRADC_CTRL1_LRADC2_IRQ 2 | ||
185 | #define BM_LRADC_CTRL1_LRADC2_IRQ 0x4 | ||
186 | #define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 | ||
187 | #define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 | ||
188 | #define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) << 2) & 0x4) | ||
189 | #define BF_LRADC_CTRL1_LRADC2_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4) | ||
190 | #define BP_LRADC_CTRL1_LRADC1_IRQ 1 | ||
191 | #define BM_LRADC_CTRL1_LRADC1_IRQ 0x2 | ||
192 | #define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 | ||
193 | #define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 | ||
194 | #define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) << 1) & 0x2) | ||
195 | #define BF_LRADC_CTRL1_LRADC1_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2) | ||
196 | #define BP_LRADC_CTRL1_LRADC0_IRQ 0 | ||
197 | #define BM_LRADC_CTRL1_LRADC0_IRQ 0x1 | ||
198 | #define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 | ||
199 | #define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 | ||
200 | #define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) << 0) & 0x1) | ||
201 | #define BF_LRADC_CTRL1_LRADC0_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1) | ||
202 | |||
203 | /** | ||
204 | * Register: HW_LRADC_CTRL2 | ||
205 | * Address: 0x20 | ||
206 | * SCT: yes | ||
207 | */ | ||
208 | #define HW_LRADC_CTRL2 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0)) | ||
209 | #define HW_LRADC_CTRL2_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4)) | ||
210 | #define HW_LRADC_CTRL2_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8)) | ||
211 | #define HW_LRADC_CTRL2_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc)) | ||
212 | #define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 | ||
213 | #define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000 | ||
214 | #define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) << 24) & 0xff000000) | ||
215 | #define BP_LRADC_CTRL2_LRADC6SELECT 20 | ||
216 | #define BM_LRADC_CTRL2_LRADC6SELECT 0xf00000 | ||
217 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL0 0x0 | ||
218 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL1 0x1 | ||
219 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL2 0x2 | ||
220 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL3 0x3 | ||
221 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL4 0x4 | ||
222 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL5 0x5 | ||
223 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL6 0x6 | ||
224 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL7 0x7 | ||
225 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL8 0x8 | ||
226 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL9 0x9 | ||
227 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL10 0xa | ||
228 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL11 0xb | ||
229 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL12 0xc | ||
230 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL13 0xd | ||
231 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL14 0xe | ||
232 | #define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL15 0xf | ||
233 | #define BF_LRADC_CTRL2_LRADC6SELECT(v) (((v) << 20) & 0xf00000) | ||
234 | #define BF_LRADC_CTRL2_LRADC6SELECT_V(v) ((BV_LRADC_CTRL2_LRADC6SELECT__##v << 20) & 0xf00000) | ||
235 | #define BP_LRADC_CTRL2_LRADC7SELECT 16 | ||
236 | #define BM_LRADC_CTRL2_LRADC7SELECT 0xf0000 | ||
237 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL0 0x0 | ||
238 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL1 0x1 | ||
239 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL2 0x2 | ||
240 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL3 0x3 | ||
241 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL4 0x4 | ||
242 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL5 0x5 | ||
243 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL6 0x6 | ||
244 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL7 0x7 | ||
245 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL8 0x8 | ||
246 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL9 0x9 | ||
247 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL10 0xa | ||
248 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL11 0xb | ||
249 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL12 0xc | ||
250 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL13 0xd | ||
251 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL14 0xe | ||
252 | #define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL15 0xf | ||
253 | #define BF_LRADC_CTRL2_LRADC7SELECT(v) (((v) << 16) & 0xf0000) | ||
254 | #define BF_LRADC_CTRL2_LRADC7SELECT_V(v) ((BV_LRADC_CTRL2_LRADC7SELECT__##v << 16) & 0xf0000) | ||
255 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9 | ||
256 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200 | ||
257 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 | ||
258 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 | ||
259 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) << 9) & 0x200) | ||
260 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200) | ||
261 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8 | ||
262 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100 | ||
263 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 | ||
264 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 | ||
265 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) << 8) & 0x100) | ||
266 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100) | ||
267 | #define BP_LRADC_CTRL2_TEMP_ISRC1 4 | ||
268 | #define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0 | ||
269 | #define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf | ||
270 | #define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe | ||
271 | #define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd | ||
272 | #define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc | ||
273 | #define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb | ||
274 | #define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa | ||
275 | #define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 | ||
276 | #define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 | ||
277 | #define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 | ||
278 | #define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 | ||
279 | #define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 | ||
280 | #define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 | ||
281 | #define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 | ||
282 | #define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 | ||
283 | #define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 | ||
284 | #define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 | ||
285 | #define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) << 4) & 0xf0) | ||
286 | #define BF_LRADC_CTRL2_TEMP_ISRC1_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0) | ||
287 | #define BP_LRADC_CTRL2_TEMP_ISRC0 0 | ||
288 | #define BM_LRADC_CTRL2_TEMP_ISRC0 0xf | ||
289 | #define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf | ||
290 | #define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe | ||
291 | #define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd | ||
292 | #define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc | ||
293 | #define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb | ||
294 | #define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa | ||
295 | #define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 | ||
296 | #define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 | ||
297 | #define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 | ||
298 | #define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 | ||
299 | #define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 | ||
300 | #define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 | ||
301 | #define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 | ||
302 | #define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 | ||
303 | #define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 | ||
304 | #define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 | ||
305 | #define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) << 0) & 0xf) | ||
306 | #define BF_LRADC_CTRL2_TEMP_ISRC0_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf) | ||
307 | |||
308 | /** | ||
309 | * Register: HW_LRADC_CTRL3 | ||
310 | * Address: 0x30 | ||
311 | * SCT: yes | ||
312 | */ | ||
313 | #define HW_LRADC_CTRL3 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0)) | ||
314 | #define HW_LRADC_CTRL3_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4)) | ||
315 | #define HW_LRADC_CTRL3_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8)) | ||
316 | #define HW_LRADC_CTRL3_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc)) | ||
317 | #define BP_LRADC_CTRL3_DISCARD 24 | ||
318 | #define BM_LRADC_CTRL3_DISCARD 0x3000000 | ||
319 | #define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 | ||
320 | #define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 | ||
321 | #define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 | ||
322 | #define BF_LRADC_CTRL3_DISCARD(v) (((v) << 24) & 0x3000000) | ||
323 | #define BF_LRADC_CTRL3_DISCARD_V(v) ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000) | ||
324 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23 | ||
325 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000 | ||
326 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 | ||
327 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 | ||
328 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) << 23) & 0x800000) | ||
329 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000) | ||
330 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22 | ||
331 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000 | ||
332 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 | ||
333 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 | ||
334 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) << 22) & 0x400000) | ||
335 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000) | ||
336 | #define BP_LRADC_CTRL3_FORCE_PWD40UA_PWUP 21 | ||
337 | #define BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP 0x200000 | ||
338 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__OFF 0x0 | ||
339 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__ON 0x1 | ||
340 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v) (((v) << 21) & 0x200000) | ||
341 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__##v << 21) & 0x200000) | ||
342 | #define BP_LRADC_CTRL3_FORCE_PWD40UA_PWDN 20 | ||
343 | #define BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN 0x100000 | ||
344 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__ON 0x0 | ||
345 | #define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__OFF 0x1 | ||
346 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v) (((v) << 20) & 0x100000) | ||
347 | #define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__##v << 20) & 0x100000) | ||
348 | #define BP_LRADC_CTRL3_VDD_FILTER 16 | ||
349 | #define BM_LRADC_CTRL3_VDD_FILTER 0x30000 | ||
350 | #define BV_LRADC_CTRL3_VDD_FILTER__0OHMS 0x0 | ||
351 | #define BV_LRADC_CTRL3_VDD_FILTER__100OHMS 0x1 | ||
352 | #define BV_LRADC_CTRL3_VDD_FILTER__250OHMS 0x2 | ||
353 | #define BV_LRADC_CTRL3_VDD_FILTER__5000OHMS 0x3 | ||
354 | #define BF_LRADC_CTRL3_VDD_FILTER(v) (((v) << 16) & 0x30000) | ||
355 | #define BF_LRADC_CTRL3_VDD_FILTER_V(v) ((BV_LRADC_CTRL3_VDD_FILTER__##v << 16) & 0x30000) | ||
356 | #define BP_LRADC_CTRL3_ADD_CAP2INPUTS 12 | ||
357 | #define BM_LRADC_CTRL3_ADD_CAP2INPUTS 0x3000 | ||
358 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0PF 0x0 | ||
359 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0_5PF 0x1 | ||
360 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__1_0PF 0x2 | ||
361 | #define BV_LRADC_CTRL3_ADD_CAP2INPUTS__2_5PF 0x3 | ||
362 | #define BF_LRADC_CTRL3_ADD_CAP2INPUTS(v) (((v) << 12) & 0x3000) | ||
363 | #define BF_LRADC_CTRL3_ADD_CAP2INPUTS_V(v) ((BV_LRADC_CTRL3_ADD_CAP2INPUTS__##v << 12) & 0x3000) | ||
364 | #define BP_LRADC_CTRL3_CYCLE_TIME 8 | ||
365 | #define BM_LRADC_CTRL3_CYCLE_TIME 0x300 | ||
366 | #define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 | ||
367 | #define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 | ||
368 | #define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 | ||
369 | #define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 | ||
370 | #define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) << 8) & 0x300) | ||
371 | #define BF_LRADC_CTRL3_CYCLE_TIME_V(v) ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300) | ||
372 | #define BP_LRADC_CTRL3_HIGH_TIME 4 | ||
373 | #define BM_LRADC_CTRL3_HIGH_TIME 0x30 | ||
374 | #define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 | ||
375 | #define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 | ||
376 | #define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 | ||
377 | #define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 | ||
378 | #define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) << 4) & 0x30) | ||
379 | #define BF_LRADC_CTRL3_HIGH_TIME_V(v) ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30) | ||
380 | #define BP_LRADC_CTRL3_REMOVE_CFILT 3 | ||
381 | #define BM_LRADC_CTRL3_REMOVE_CFILT 0x8 | ||
382 | #define BV_LRADC_CTRL3_REMOVE_CFILT__OFF 0x0 | ||
383 | #define BV_LRADC_CTRL3_REMOVE_CFILT__ON 0x1 | ||
384 | #define BF_LRADC_CTRL3_REMOVE_CFILT(v) (((v) << 3) & 0x8) | ||
385 | #define BF_LRADC_CTRL3_REMOVE_CFILT_V(v) ((BV_LRADC_CTRL3_REMOVE_CFILT__##v << 3) & 0x8) | ||
386 | #define BP_LRADC_CTRL3_SHORT_RFILT 2 | ||
387 | #define BM_LRADC_CTRL3_SHORT_RFILT 0x4 | ||
388 | #define BV_LRADC_CTRL3_SHORT_RFILT__OFF 0x0 | ||
389 | #define BV_LRADC_CTRL3_SHORT_RFILT__ON 0x1 | ||
390 | #define BF_LRADC_CTRL3_SHORT_RFILT(v) (((v) << 2) & 0x4) | ||
391 | #define BF_LRADC_CTRL3_SHORT_RFILT_V(v) ((BV_LRADC_CTRL3_SHORT_RFILT__##v << 2) & 0x4) | ||
392 | #define BP_LRADC_CTRL3_DELAY_CLOCK 1 | ||
393 | #define BM_LRADC_CTRL3_DELAY_CLOCK 0x2 | ||
394 | #define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 | ||
395 | #define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 | ||
396 | #define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) << 1) & 0x2) | ||
397 | #define BF_LRADC_CTRL3_DELAY_CLOCK_V(v) ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2) | ||
398 | #define BP_LRADC_CTRL3_INVERT_CLOCK 0 | ||
399 | #define BM_LRADC_CTRL3_INVERT_CLOCK 0x1 | ||
400 | #define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 | ||
401 | #define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 | ||
402 | #define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) << 0) & 0x1) | ||
403 | #define BF_LRADC_CTRL3_INVERT_CLOCK_V(v) ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1) | ||
404 | |||
405 | /** | ||
406 | * Register: HW_LRADC_STATUS | ||
407 | * Address: 0x40 | ||
408 | * SCT: no | ||
409 | */ | ||
410 | #define HW_LRADC_STATUS (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40)) | ||
411 | #define BP_LRADC_STATUS_TEMP1_PRESENT 26 | ||
412 | #define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000 | ||
413 | #define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
414 | #define BP_LRADC_STATUS_TEMP0_PRESENT 25 | ||
415 | #define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000 | ||
416 | #define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
417 | #define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24 | ||
418 | #define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000 | ||
419 | #define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) << 24) & 0x1000000) | ||
420 | #define BP_LRADC_STATUS_CHANNEL7_PRESENT 23 | ||
421 | #define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000 | ||
422 | #define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) << 23) & 0x800000) | ||
423 | #define BP_LRADC_STATUS_CHANNEL6_PRESENT 22 | ||
424 | #define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000 | ||
425 | #define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) << 22) & 0x400000) | ||
426 | #define BP_LRADC_STATUS_CHANNEL5_PRESENT 21 | ||
427 | #define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000 | ||
428 | #define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) << 21) & 0x200000) | ||
429 | #define BP_LRADC_STATUS_CHANNEL4_PRESENT 20 | ||
430 | #define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000 | ||
431 | #define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) << 20) & 0x100000) | ||
432 | #define BP_LRADC_STATUS_CHANNEL3_PRESENT 19 | ||
433 | #define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000 | ||
434 | #define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) << 19) & 0x80000) | ||
435 | #define BP_LRADC_STATUS_CHANNEL2_PRESENT 18 | ||
436 | #define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000 | ||
437 | #define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) << 18) & 0x40000) | ||
438 | #define BP_LRADC_STATUS_CHANNEL1_PRESENT 17 | ||
439 | #define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000 | ||
440 | #define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) << 17) & 0x20000) | ||
441 | #define BP_LRADC_STATUS_CHANNEL0_PRESENT 16 | ||
442 | #define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000 | ||
443 | #define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) << 16) & 0x10000) | ||
444 | #define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 | ||
445 | #define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1 | ||
446 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 | ||
447 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 | ||
448 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) << 0) & 0x1) | ||
449 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1) | ||
450 | |||
451 | /** | ||
452 | * Register: HW_LRADC_DEBUG0 | ||
453 | * Address: 0x110 | ||
454 | * SCT: no | ||
455 | */ | ||
456 | #define HW_LRADC_DEBUG0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110)) | ||
457 | #define BP_LRADC_DEBUG0_READONLY 16 | ||
458 | #define BM_LRADC_DEBUG0_READONLY 0xffff0000 | ||
459 | #define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000) | ||
460 | #define BP_LRADC_DEBUG0_STATE 0 | ||
461 | #define BM_LRADC_DEBUG0_STATE 0xfff | ||
462 | #define BF_LRADC_DEBUG0_STATE(v) (((v) << 0) & 0xfff) | ||
463 | |||
464 | /** | ||
465 | * Register: HW_LRADC_DEBUG1 | ||
466 | * Address: 0x120 | ||
467 | * SCT: yes | ||
468 | */ | ||
469 | #define HW_LRADC_DEBUG1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0)) | ||
470 | #define HW_LRADC_DEBUG1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4)) | ||
471 | #define HW_LRADC_DEBUG1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8)) | ||
472 | #define HW_LRADC_DEBUG1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc)) | ||
473 | #define BP_LRADC_DEBUG1_REQUEST 16 | ||
474 | #define BM_LRADC_DEBUG1_REQUEST 0xff0000 | ||
475 | #define BF_LRADC_DEBUG1_REQUEST(v) (((v) << 16) & 0xff0000) | ||
476 | #define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 | ||
477 | #define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00 | ||
478 | #define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) << 8) & 0x1f00) | ||
479 | #define BP_LRADC_DEBUG1_TESTMODE6 2 | ||
480 | #define BM_LRADC_DEBUG1_TESTMODE6 0x4 | ||
481 | #define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 | ||
482 | #define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 | ||
483 | #define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) << 2) & 0x4) | ||
484 | #define BF_LRADC_DEBUG1_TESTMODE6_V(v) ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4) | ||
485 | #define BP_LRADC_DEBUG1_TESTMODE5 1 | ||
486 | #define BM_LRADC_DEBUG1_TESTMODE5 0x2 | ||
487 | #define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 | ||
488 | #define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 | ||
489 | #define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) << 1) & 0x2) | ||
490 | #define BF_LRADC_DEBUG1_TESTMODE5_V(v) ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2) | ||
491 | #define BP_LRADC_DEBUG1_TESTMODE 0 | ||
492 | #define BM_LRADC_DEBUG1_TESTMODE 0x1 | ||
493 | #define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 | ||
494 | #define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 | ||
495 | #define BF_LRADC_DEBUG1_TESTMODE(v) (((v) << 0) & 0x1) | ||
496 | #define BF_LRADC_DEBUG1_TESTMODE_V(v) ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_LRADC_CONVERSION | ||
500 | * Address: 0x130 | ||
501 | * SCT: yes | ||
502 | */ | ||
503 | #define HW_LRADC_CONVERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0)) | ||
504 | #define HW_LRADC_CONVERSION_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4)) | ||
505 | #define HW_LRADC_CONVERSION_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8)) | ||
506 | #define HW_LRADC_CONVERSION_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc)) | ||
507 | #define BP_LRADC_CONVERSION_AUTOMATIC 20 | ||
508 | #define BM_LRADC_CONVERSION_AUTOMATIC 0x100000 | ||
509 | #define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 | ||
510 | #define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 | ||
511 | #define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) << 20) & 0x100000) | ||
512 | #define BF_LRADC_CONVERSION_AUTOMATIC_V(v) ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000) | ||
513 | #define BP_LRADC_CONVERSION_SCALE_FACTOR 16 | ||
514 | #define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000 | ||
515 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 | ||
516 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 | ||
517 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 | ||
518 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 | ||
519 | #define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) << 16) & 0x30000) | ||
520 | #define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v) ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000) | ||
521 | #define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 | ||
522 | #define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff | ||
523 | #define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) << 0) & 0x3ff) | ||
524 | |||
525 | /** | ||
526 | * Register: HW_LRADC_DELAYn | ||
527 | * Address: 0xd0+n*0x10 | ||
528 | * SCT: yes | ||
529 | */ | ||
530 | #define HW_LRADC_DELAYn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0)) | ||
531 | #define HW_LRADC_DELAYn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4)) | ||
532 | #define HW_LRADC_DELAYn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8)) | ||
533 | #define HW_LRADC_DELAYn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc)) | ||
534 | #define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 | ||
535 | #define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000 | ||
536 | #define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) << 24) & 0xff000000) | ||
537 | #define BP_LRADC_DELAYn_KICK 20 | ||
538 | #define BM_LRADC_DELAYn_KICK 0x100000 | ||
539 | #define BF_LRADC_DELAYn_KICK(v) (((v) << 20) & 0x100000) | ||
540 | #define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 | ||
541 | #define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000 | ||
542 | #define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) << 16) & 0xf0000) | ||
543 | #define BP_LRADC_DELAYn_LOOP_COUNT 11 | ||
544 | #define BM_LRADC_DELAYn_LOOP_COUNT 0xf800 | ||
545 | #define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) << 11) & 0xf800) | ||
546 | #define BP_LRADC_DELAYn_DELAY 0 | ||
547 | #define BM_LRADC_DELAYn_DELAY 0x7ff | ||
548 | #define BF_LRADC_DELAYn_DELAY(v) (((v) << 0) & 0x7ff) | ||
549 | |||
550 | /** | ||
551 | * Register: HW_LRADC_CHn | ||
552 | * Address: 0x50+n*0x10 | ||
553 | * SCT: yes | ||
554 | */ | ||
555 | #define HW_LRADC_CHn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0)) | ||
556 | #define HW_LRADC_CHn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4)) | ||
557 | #define HW_LRADC_CHn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8)) | ||
558 | #define HW_LRADC_CHn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc)) | ||
559 | #define BP_LRADC_CHn_TOGGLE 31 | ||
560 | #define BM_LRADC_CHn_TOGGLE 0x80000000 | ||
561 | #define BF_LRADC_CHn_TOGGLE(v) (((v) << 31) & 0x80000000) | ||
562 | #define BP_LRADC_CHn_ACCUMULATE 29 | ||
563 | #define BM_LRADC_CHn_ACCUMULATE 0x20000000 | ||
564 | #define BF_LRADC_CHn_ACCUMULATE(v) (((v) << 29) & 0x20000000) | ||
565 | #define BP_LRADC_CHn_NUM_SAMPLES 24 | ||
566 | #define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000 | ||
567 | #define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000) | ||
568 | #define BP_LRADC_CHn_VALUE 0 | ||
569 | #define BM_LRADC_CHn_VALUE 0x3ffff | ||
570 | #define BF_LRADC_CHn_VALUE(v) (((v) << 0) & 0x3ffff) | ||
571 | |||
572 | #endif /* __HEADERGEN__STMP3600__LRADC__H__ */ | ||