diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h | 304 |
1 files changed, 304 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h new file mode 100644 index 0000000000..8661e75706 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h | |||
@@ -0,0 +1,304 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__RTC__H__ | ||
24 | #define __HEADERGEN__STMP3600__RTC__H__ | ||
25 | |||
26 | #define REGS_RTC_BASE (0x8005c000) | ||
27 | |||
28 | #define REGS_RTC_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_RTC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_RTC_CTRL (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_RTC_CTRL_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_RTC_CTRL_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_RTC_CTRL_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_RTC_CTRL_SFTRST 31 | ||
40 | #define BM_RTC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_RTC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_RTC_CTRL_CLKGATE 30 | ||
43 | #define BM_RTC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_RTC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_RTC_CTRL_CLKDIV 24 | ||
46 | #define BM_RTC_CTRL_CLKDIV 0xf000000 | ||
47 | #define BF_RTC_CTRL_CLKDIV(v) (((v) << 24) & 0xf000000) | ||
48 | #define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG 6 | ||
49 | #define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x40 | ||
50 | #define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NORMAL 0x0 | ||
51 | #define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NO_COPY 0x1 | ||
52 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40) | ||
53 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v) ((BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##v << 6) & 0x40) | ||
54 | #define BP_RTC_CTRL_FORCE_UPDATE 5 | ||
55 | #define BM_RTC_CTRL_FORCE_UPDATE 0x20 | ||
56 | #define BV_RTC_CTRL_FORCE_UPDATE__NORMAL 0x0 | ||
57 | #define BV_RTC_CTRL_FORCE_UPDATE__FORCE_COPY 0x1 | ||
58 | #define BF_RTC_CTRL_FORCE_UPDATE(v) (((v) << 5) & 0x20) | ||
59 | #define BF_RTC_CTRL_FORCE_UPDATE_V(v) ((BV_RTC_CTRL_FORCE_UPDATE__##v << 5) & 0x20) | ||
60 | #define BP_RTC_CTRL_WATCHDOGEN 4 | ||
61 | #define BM_RTC_CTRL_WATCHDOGEN 0x10 | ||
62 | #define BF_RTC_CTRL_WATCHDOGEN(v) (((v) << 4) & 0x10) | ||
63 | #define BP_RTC_CTRL_ONEMSEC_IRQ 3 | ||
64 | #define BM_RTC_CTRL_ONEMSEC_IRQ 0x8 | ||
65 | #define BF_RTC_CTRL_ONEMSEC_IRQ(v) (((v) << 3) & 0x8) | ||
66 | #define BP_RTC_CTRL_ALARM_IRQ 2 | ||
67 | #define BM_RTC_CTRL_ALARM_IRQ 0x4 | ||
68 | #define BF_RTC_CTRL_ALARM_IRQ(v) (((v) << 2) & 0x4) | ||
69 | #define BP_RTC_CTRL_ONEMSEC_IRQ_EN 1 | ||
70 | #define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x2 | ||
71 | #define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v) (((v) << 1) & 0x2) | ||
72 | #define BP_RTC_CTRL_ALARM_IRQ_EN 0 | ||
73 | #define BM_RTC_CTRL_ALARM_IRQ_EN 0x1 | ||
74 | #define BF_RTC_CTRL_ALARM_IRQ_EN(v) (((v) << 0) & 0x1) | ||
75 | |||
76 | /** | ||
77 | * Register: HW_RTC_STAT | ||
78 | * Address: 0x10 | ||
79 | * SCT: no | ||
80 | */ | ||
81 | #define HW_RTC_STAT (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10)) | ||
82 | #define BP_RTC_STAT_RTC_PRESENT 31 | ||
83 | #define BM_RTC_STAT_RTC_PRESENT 0x80000000 | ||
84 | #define BF_RTC_STAT_RTC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
85 | #define BP_RTC_STAT_ALARM_PRESENT 30 | ||
86 | #define BM_RTC_STAT_ALARM_PRESENT 0x40000000 | ||
87 | #define BF_RTC_STAT_ALARM_PRESENT(v) (((v) << 30) & 0x40000000) | ||
88 | #define BP_RTC_STAT_WATCHDOG_PRESENT 29 | ||
89 | #define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 | ||
90 | #define BF_RTC_STAT_WATCHDOG_PRESENT(v) (((v) << 29) & 0x20000000) | ||
91 | #define BP_RTC_STAT_XTAL32768_PRESENT 28 | ||
92 | #define BM_RTC_STAT_XTAL32768_PRESENT 0x10000000 | ||
93 | #define BF_RTC_STAT_XTAL32768_PRESENT(v) (((v) << 28) & 0x10000000) | ||
94 | #define BP_RTC_STAT_STALE_REGS 16 | ||
95 | #define BM_RTC_STAT_STALE_REGS 0x3f0000 | ||
96 | #define BF_RTC_STAT_STALE_REGS(v) (((v) << 16) & 0x3f0000) | ||
97 | #define BP_RTC_STAT_NEW_REGS 8 | ||
98 | #define BM_RTC_STAT_NEW_REGS 0x3f00 | ||
99 | #define BF_RTC_STAT_NEW_REGS(v) (((v) << 8) & 0x3f00) | ||
100 | #define BP_RTC_STAT_FUSE_UNLOCK 1 | ||
101 | #define BM_RTC_STAT_FUSE_UNLOCK 0x2 | ||
102 | #define BF_RTC_STAT_FUSE_UNLOCK(v) (((v) << 1) & 0x2) | ||
103 | #define BP_RTC_STAT_FUSE_DONE 0 | ||
104 | #define BM_RTC_STAT_FUSE_DONE 0x1 | ||
105 | #define BF_RTC_STAT_FUSE_DONE(v) (((v) << 0) & 0x1) | ||
106 | |||
107 | /** | ||
108 | * Register: HW_RTC_MILLISECONDS | ||
109 | * Address: 0x20 | ||
110 | * SCT: yes | ||
111 | */ | ||
112 | #define HW_RTC_MILLISECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0)) | ||
113 | #define HW_RTC_MILLISECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4)) | ||
114 | #define HW_RTC_MILLISECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8)) | ||
115 | #define HW_RTC_MILLISECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc)) | ||
116 | #define BP_RTC_MILLISECONDS_COUNT 0 | ||
117 | #define BM_RTC_MILLISECONDS_COUNT 0xffffffff | ||
118 | #define BF_RTC_MILLISECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
119 | |||
120 | /** | ||
121 | * Register: HW_RTC_SECONDS | ||
122 | * Address: 0x30 | ||
123 | * SCT: yes | ||
124 | */ | ||
125 | #define HW_RTC_SECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0)) | ||
126 | #define HW_RTC_SECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4)) | ||
127 | #define HW_RTC_SECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8)) | ||
128 | #define HW_RTC_SECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc)) | ||
129 | #define BP_RTC_SECONDS_COUNT 0 | ||
130 | #define BM_RTC_SECONDS_COUNT 0xffffffff | ||
131 | #define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_RTC_ALARM | ||
135 | * Address: 0x40 | ||
136 | * SCT: yes | ||
137 | */ | ||
138 | #define HW_RTC_ALARM (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0)) | ||
139 | #define HW_RTC_ALARM_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4)) | ||
140 | #define HW_RTC_ALARM_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8)) | ||
141 | #define HW_RTC_ALARM_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc)) | ||
142 | #define BP_RTC_ALARM_VALUE 0 | ||
143 | #define BM_RTC_ALARM_VALUE 0xffffffff | ||
144 | #define BF_RTC_ALARM_VALUE(v) (((v) << 0) & 0xffffffff) | ||
145 | |||
146 | /** | ||
147 | * Register: HW_RTC_WATCHDOG | ||
148 | * Address: 0x50 | ||
149 | * SCT: yes | ||
150 | */ | ||
151 | #define HW_RTC_WATCHDOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0)) | ||
152 | #define HW_RTC_WATCHDOG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4)) | ||
153 | #define HW_RTC_WATCHDOG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8)) | ||
154 | #define HW_RTC_WATCHDOG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc)) | ||
155 | #define BP_RTC_WATCHDOG_COUNT 0 | ||
156 | #define BM_RTC_WATCHDOG_COUNT 0xffffffff | ||
157 | #define BF_RTC_WATCHDOG_COUNT(v) (((v) << 0) & 0xffffffff) | ||
158 | |||
159 | /** | ||
160 | * Register: HW_RTC_PERSISTENT0 | ||
161 | * Address: 0x60 | ||
162 | * SCT: yes | ||
163 | */ | ||
164 | #define HW_RTC_PERSISTENT0 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0)) | ||
165 | #define HW_RTC_PERSISTENT0_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4)) | ||
166 | #define HW_RTC_PERSISTENT0_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8)) | ||
167 | #define HW_RTC_PERSISTENT0_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc)) | ||
168 | #define BP_RTC_PERSISTENT0_GENERAL 16 | ||
169 | #define BM_RTC_PERSISTENT0_GENERAL 0xffff0000 | ||
170 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_BOOT 0x8000 | ||
171 | #define BV_RTC_PERSISTENT0_GENERAL__ENUMERATE_500MA_TWICE 0x4000 | ||
172 | #define BV_RTC_PERSISTENT0_GENERAL__USB_BOOT_PLAYER_MODE 0x2000 | ||
173 | #define BV_RTC_PERSISTENT0_GENERAL__SKIP_CHECKDISK 0x1000 | ||
174 | #define BV_RTC_PERSISTENT0_GENERAL__USB_LOW_POWER_MODE 0x800 | ||
175 | #define BV_RTC_PERSISTENT0_GENERAL__OTG_HNP_BIT 0x400 | ||
176 | #define BV_RTC_PERSISTENT0_GENERAL__OTG_ATL_ROLE_BIT 0x200 | ||
177 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_HI 0x100 | ||
178 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_LO 0x80 | ||
179 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_3 0x40 | ||
180 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_2 0x20 | ||
181 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_1 0x10 | ||
182 | #define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_0 0x8 | ||
183 | #define BV_RTC_PERSISTENT0_GENERAL__ETM_ENABLE 0x4 | ||
184 | #define BF_RTC_PERSISTENT0_GENERAL(v) (((v) << 16) & 0xffff0000) | ||
185 | #define BF_RTC_PERSISTENT0_GENERAL_V(v) ((BV_RTC_PERSISTENT0_GENERAL__##v << 16) & 0xffff0000) | ||
186 | #define BP_RTC_PERSISTENT0_DCDC_CTRL 6 | ||
187 | #define BM_RTC_PERSISTENT0_DCDC_CTRL 0xffc0 | ||
188 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SD_PRESENT 0x200 | ||
189 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__LOWBAT_3P0 0x100 | ||
190 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SELFBIAS_PWRUP 0x80 | ||
191 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__AUTO_RESTART 0x40 | ||
192 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DETECT_LOWBAT 0x20 | ||
193 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS1 0x10 | ||
194 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS2 0x8 | ||
195 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE 0x4 | ||
196 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__DISABLE_XTALSTOP 0x2 | ||
197 | #define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE2 0x1 | ||
198 | #define BF_RTC_PERSISTENT0_DCDC_CTRL(v) (((v) << 6) & 0xffc0) | ||
199 | #define BF_RTC_PERSISTENT0_DCDC_CTRL_V(v) ((BV_RTC_PERSISTENT0_DCDC_CTRL__##v << 6) & 0xffc0) | ||
200 | #define BP_RTC_PERSISTENT0_XTAL32_PDOWN 5 | ||
201 | #define BM_RTC_PERSISTENT0_XTAL32_PDOWN 0x20 | ||
202 | #define BF_RTC_PERSISTENT0_XTAL32_PDOWN(v) (((v) << 5) & 0x20) | ||
203 | #define BP_RTC_PERSISTENT0_XTAL24_PDOWN 4 | ||
204 | #define BM_RTC_PERSISTENT0_XTAL24_PDOWN 0x10 | ||
205 | #define BF_RTC_PERSISTENT0_XTAL24_PDOWN(v) (((v) << 4) & 0x10) | ||
206 | #define BP_RTC_PERSISTENT0_ALARM_WAKE_EN 3 | ||
207 | #define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x8 | ||
208 | #define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v) (((v) << 3) & 0x8) | ||
209 | #define BP_RTC_PERSISTENT0_ALARM_EN 2 | ||
210 | #define BM_RTC_PERSISTENT0_ALARM_EN 0x4 | ||
211 | #define BF_RTC_PERSISTENT0_ALARM_EN(v) (((v) << 2) & 0x4) | ||
212 | #define BP_RTC_PERSISTENT0_ALARM_WAKE 1 | ||
213 | #define BM_RTC_PERSISTENT0_ALARM_WAKE 0x2 | ||
214 | #define BF_RTC_PERSISTENT0_ALARM_WAKE(v) (((v) << 1) & 0x2) | ||
215 | #define BP_RTC_PERSISTENT0_CLOCKSOURCE 0 | ||
216 | #define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x1 | ||
217 | #define BF_RTC_PERSISTENT0_CLOCKSOURCE(v) (((v) << 0) & 0x1) | ||
218 | |||
219 | /** | ||
220 | * Register: HW_RTC_PERSISTENT1 | ||
221 | * Address: 0x70 | ||
222 | * SCT: yes | ||
223 | */ | ||
224 | #define HW_RTC_PERSISTENT1 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0)) | ||
225 | #define HW_RTC_PERSISTENT1_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4)) | ||
226 | #define HW_RTC_PERSISTENT1_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8)) | ||
227 | #define HW_RTC_PERSISTENT1_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc)) | ||
228 | #define BP_RTC_PERSISTENT1_GENERAL 0 | ||
229 | #define BM_RTC_PERSISTENT1_GENERAL 0xffffffff | ||
230 | #define BF_RTC_PERSISTENT1_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
231 | |||
232 | /** | ||
233 | * Register: HW_RTC_PERSISTENT2 | ||
234 | * Address: 0x80 | ||
235 | * SCT: yes | ||
236 | */ | ||
237 | #define HW_RTC_PERSISTENT2 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0)) | ||
238 | #define HW_RTC_PERSISTENT2_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4)) | ||
239 | #define HW_RTC_PERSISTENT2_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8)) | ||
240 | #define HW_RTC_PERSISTENT2_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc)) | ||
241 | #define BP_RTC_PERSISTENT2_SRAM_LO 0 | ||
242 | #define BM_RTC_PERSISTENT2_SRAM_LO 0xffffffff | ||
243 | #define BV_RTC_PERSISTENT2_SRAM_LO__WARM_BOOT 0x80000000 | ||
244 | #define BF_RTC_PERSISTENT2_SRAM_LO(v) (((v) << 0) & 0xffffffff) | ||
245 | #define BF_RTC_PERSISTENT2_SRAM_LO_V(v) ((BV_RTC_PERSISTENT2_SRAM_LO__##v << 0) & 0xffffffff) | ||
246 | |||
247 | /** | ||
248 | * Register: HW_RTC_PERSISTENT3 | ||
249 | * Address: 0x90 | ||
250 | * SCT: yes | ||
251 | */ | ||
252 | #define HW_RTC_PERSISTENT3 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0)) | ||
253 | #define HW_RTC_PERSISTENT3_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4)) | ||
254 | #define HW_RTC_PERSISTENT3_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8)) | ||
255 | #define HW_RTC_PERSISTENT3_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc)) | ||
256 | #define BP_RTC_PERSISTENT3_SRAM_HI 0 | ||
257 | #define BM_RTC_PERSISTENT3_SRAM_HI 0xffffffff | ||
258 | #define BF_RTC_PERSISTENT3_SRAM_HI(v) (((v) << 0) & 0xffffffff) | ||
259 | |||
260 | /** | ||
261 | * Register: HW_RTC_DEBUG | ||
262 | * Address: 0xa0 | ||
263 | * SCT: yes | ||
264 | */ | ||
265 | #define HW_RTC_DEBUG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0)) | ||
266 | #define HW_RTC_DEBUG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4)) | ||
267 | #define HW_RTC_DEBUG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8)) | ||
268 | #define HW_RTC_DEBUG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc)) | ||
269 | #define BP_RTC_DEBUG_WATCHDOG_RESET_MASK 1 | ||
270 | #define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x2 | ||
271 | #define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2) | ||
272 | #define BP_RTC_DEBUG_WATCHDOG_RESET 0 | ||
273 | #define BM_RTC_DEBUG_WATCHDOG_RESET 0x1 | ||
274 | #define BF_RTC_DEBUG_WATCHDOG_RESET(v) (((v) << 0) & 0x1) | ||
275 | |||
276 | /** | ||
277 | * Register: HW_RTC_UNLOCK | ||
278 | * Address: 0x200 | ||
279 | * SCT: yes | ||
280 | */ | ||
281 | #define HW_RTC_UNLOCK (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x0)) | ||
282 | #define HW_RTC_UNLOCK_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x4)) | ||
283 | #define HW_RTC_UNLOCK_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x8)) | ||
284 | #define HW_RTC_UNLOCK_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0xc)) | ||
285 | #define BP_RTC_UNLOCK_KEY 0 | ||
286 | #define BM_RTC_UNLOCK_KEY 0xffffffff | ||
287 | #define BV_RTC_UNLOCK_KEY__VAL 0xc6a83957 | ||
288 | #define BF_RTC_UNLOCK_KEY(v) (((v) << 0) & 0xffffffff) | ||
289 | #define BF_RTC_UNLOCK_KEY_V(v) ((BV_RTC_UNLOCK_KEY__##v << 0) & 0xffffffff) | ||
290 | |||
291 | /** | ||
292 | * Register: HW_RTC_LASERFUSEn | ||
293 | * Address: 0x300+n*0x10 | ||
294 | * SCT: yes | ||
295 | */ | ||
296 | #define HW_RTC_LASERFUSEn(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x0)) | ||
297 | #define HW_RTC_LASERFUSEn_SET(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x4)) | ||
298 | #define HW_RTC_LASERFUSEn_CLR(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x8)) | ||
299 | #define HW_RTC_LASERFUSEn_TOG(n) (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0xc)) | ||
300 | #define BP_RTC_LASERFUSEn_BITS 0 | ||
301 | #define BM_RTC_LASERFUSEn_BITS 0xffffffff | ||
302 | #define BF_RTC_LASERFUSEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
303 | |||
304 | #endif /* __HEADERGEN__STMP3600__RTC__H__ */ | ||