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Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h')
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diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
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index 0000000000..bddc2dcfa9
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+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * This file was automatically generated by headergen, DO NOT EDIT it.
9 * headergen version: 2.1.7
10 * XML versions: stmp3700:3.2.0
11 *
12 * Copyright (C) 2013 by Amaury Pouly
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version 2
17 * of the License, or (at your option) any later version.
18 *
19 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
20 * KIND, either express or implied.
21 *
22 ****************************************************************************/
23#ifndef __HEADERGEN__STMP3700__PINCTRL__H__
24#define __HEADERGEN__STMP3700__PINCTRL__H__
25
26#define REGS_PINCTRL_BASE (0x80018000)
27
28#define REGS_PINCTRL_VERSION "3.2.0"
29
30/**
31 * Register: HW_PINCTRL_CTRL
32 * Address: 0
33 * SCT: yes
34*/
35#define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
36#define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
37#define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
38#define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
39#define BP_PINCTRL_CTRL_SFTRST 31
40#define BM_PINCTRL_CTRL_SFTRST 0x80000000
41#define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
42#define BP_PINCTRL_CTRL_CLKGATE 30
43#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
44#define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
45#define BP_PINCTRL_CTRL_PRESENT3 29
46#define BM_PINCTRL_CTRL_PRESENT3 0x20000000
47#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000)
48#define BP_PINCTRL_CTRL_PRESENT2 28
49#define BM_PINCTRL_CTRL_PRESENT2 0x10000000
50#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000)
51#define BP_PINCTRL_CTRL_PRESENT1 27
52#define BM_PINCTRL_CTRL_PRESENT1 0x8000000
53#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000)
54#define BP_PINCTRL_CTRL_PRESENT0 26
55#define BM_PINCTRL_CTRL_PRESENT0 0x4000000
56#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000)
57#define BP_PINCTRL_CTRL_IRQOUT3 3
58#define BM_PINCTRL_CTRL_IRQOUT3 0x8
59#define BF_PINCTRL_CTRL_IRQOUT3(v) (((v) << 3) & 0x8)
60#define BP_PINCTRL_CTRL_IRQOUT2 2
61#define BM_PINCTRL_CTRL_IRQOUT2 0x4
62#define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4)
63#define BP_PINCTRL_CTRL_IRQOUT1 1
64#define BM_PINCTRL_CTRL_IRQOUT1 0x2
65#define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2)
66#define BP_PINCTRL_CTRL_IRQOUT0 0
67#define BM_PINCTRL_CTRL_IRQOUT0 0x1
68#define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1)
69
70/**
71 * Register: HW_PINCTRL_MUXSELn
72 * Address: 0x100+n*0x10
73 * SCT: yes
74*/
75#define HW_PINCTRL_MUXSELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0))
76#define HW_PINCTRL_MUXSELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4))
77#define HW_PINCTRL_MUXSELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8))
78#define HW_PINCTRL_MUXSELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc))
79#define BP_PINCTRL_MUXSELn_BITS 0
80#define BM_PINCTRL_MUXSELn_BITS 0xffffffff
81#define BF_PINCTRL_MUXSELn_BITS(v) (((v) << 0) & 0xffffffff)
82
83/**
84 * Register: HW_PINCTRL_DRIVEn
85 * Address: 0x200+n*0x10
86 * SCT: yes
87*/
88#define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0))
89#define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4))
90#define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8))
91#define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc))
92#define BP_PINCTRL_DRIVEn_BITS 0
93#define BM_PINCTRL_DRIVEn_BITS 0xffffffff
94#define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff)
95
96/**
97 * Register: HW_PINCTRL_PULLn
98 * Address: 0x300+n*0x10
99 * SCT: yes
100*/
101#define HW_PINCTRL_PULLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x0))
102#define HW_PINCTRL_PULLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x4))
103#define HW_PINCTRL_PULLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x8))
104#define HW_PINCTRL_PULLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0xc))
105#define BP_PINCTRL_PULLn_BITS 0
106#define BM_PINCTRL_PULLn_BITS 0xffffffff
107#define BF_PINCTRL_PULLn_BITS(v) (((v) << 0) & 0xffffffff)
108
109/**
110 * Register: HW_PINCTRL_DOUTn
111 * Address: 0x400+n*0x10
112 * SCT: yes
113*/
114#define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0))
115#define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4))
116#define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8))
117#define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc))
118#define BP_PINCTRL_DOUTn_BITS 0
119#define BM_PINCTRL_DOUTn_BITS 0xffffffff
120#define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff)
121
122/**
123 * Register: HW_PINCTRL_DINn
124 * Address: 0x500+n*0x10
125 * SCT: yes
126*/
127#define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0))
128#define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4))
129#define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8))
130#define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc))
131#define BP_PINCTRL_DINn_BITS 0
132#define BM_PINCTRL_DINn_BITS 0xffffffff
133#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
134
135/**
136 * Register: HW_PINCTRL_DOEn
137 * Address: 0x600+n*0x10
138 * SCT: yes
139*/
140#define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0))
141#define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4))
142#define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8))
143#define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc))
144#define BP_PINCTRL_DOEn_BITS 0
145#define BM_PINCTRL_DOEn_BITS 0xffffffff
146#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
147
148/**
149 * Register: HW_PINCTRL_PIN2IRQn
150 * Address: 0x700+n*0x10
151 * SCT: yes
152*/
153#define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0))
154#define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4))
155#define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8))
156#define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc))
157#define BP_PINCTRL_PIN2IRQn_BITS 0
158#define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff
159#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
160
161/**
162 * Register: HW_PINCTRL_IRQENn
163 * Address: 0x800+n*0x10
164 * SCT: yes
165*/
166#define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0))
167#define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4))
168#define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8))
169#define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc))
170#define BP_PINCTRL_IRQENn_BITS 0
171#define BM_PINCTRL_IRQENn_BITS 0xffffffff
172#define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff)
173
174/**
175 * Register: HW_PINCTRL_IRQLEVELn
176 * Address: 0x900+n*0x10
177 * SCT: yes
178*/
179#define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0))
180#define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4))
181#define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8))
182#define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc))
183#define BP_PINCTRL_IRQLEVELn_BITS 0
184#define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff
185#define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff)
186
187/**
188 * Register: HW_PINCTRL_IRQPOLn
189 * Address: 0xa00+n*0x10
190 * SCT: yes
191*/
192#define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0))
193#define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4))
194#define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8))
195#define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc))
196#define BP_PINCTRL_IRQPOLn_BITS 0
197#define BM_PINCTRL_IRQPOLn_BITS 0xffffffff
198#define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff)
199
200/**
201 * Register: HW_PINCTRL_IRQSTATn
202 * Address: 0xb00+n*0x10
203 * SCT: yes
204*/
205#define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0))
206#define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4))
207#define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8))
208#define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc))
209#define BP_PINCTRL_IRQSTATn_BITS 0
210#define BM_PINCTRL_IRQSTATn_BITS 0xffffffff
211#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
212
213#endif /* __HEADERGEN__STMP3700__PINCTRL__H__ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 11:38:49 +0000