1 files changed, 154 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h
new file mode 100644
index 0000000000..01faeabc62
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h
@@ -0,0 +1,154 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__SAIF__H__
+#define __HEADERGEN__STMP3700__SAIF__H__
+#define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000)
+#define REGS_SAIF_VERSION "3.2.0"
+/**
+ * Register: HW_SAIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SAIF_CTRL(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0))
+#define HW_SAIF_CTRL_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4))
+#define HW_SAIF_CTRL_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8))
+#define HW_SAIF_CTRL_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc))
+#define BP_SAIF_CTRL_SFTRST                 31
+#define BM_SAIF_CTRL_SFTRST                 0x80000000
+#define BF_SAIF_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_SAIF_CTRL_CLKGATE                30
+#define BM_SAIF_CTRL_CLKGATE                0x40000000
+#define BF_SAIF_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_SAIF_CTRL_BITCLK_MULT_RATE       27
+#define BM_SAIF_CTRL_BITCLK_MULT_RATE       0x38000000
+#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v)    (((v) << 27) & 0x38000000)
+#define BP_SAIF_CTRL_BITCLK_BASE_RATE       26
+#define BM_SAIF_CTRL_BITCLK_BASE_RATE       0x4000000
+#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v)    (((v) << 26) & 0x4000000)
+#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN      25
+#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN      0x2000000
+#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 25) & 0x2000000)
+#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    24
+#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    0x1000000
+#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000)
+#define BP_SAIF_CTRL_DMAWAIT_COUNT          16
+#define BM_SAIF_CTRL_DMAWAIT_COUNT          0x1f0000
+#define BF_SAIF_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
+#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT     14
+#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT     0xc000
+#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v)  (((v) << 14) & 0xc000)
+#define BP_SAIF_CTRL_BIT_ORDER              12
+#define BM_SAIF_CTRL_BIT_ORDER              0x1000
+#define BF_SAIF_CTRL_BIT_ORDER(v)           (((v) << 12) & 0x1000)
+#define BP_SAIF_CTRL_DELAY                  11
+#define BM_SAIF_CTRL_DELAY                  0x800
+#define BF_SAIF_CTRL_DELAY(v)               (((v) << 11) & 0x800)
+#define BP_SAIF_CTRL_JUSTIFY                10
+#define BM_SAIF_CTRL_JUSTIFY                0x400
+#define BF_SAIF_CTRL_JUSTIFY(v)             (((v) << 10) & 0x400)
+#define BP_SAIF_CTRL_LRCLK_POLARITY         9
+#define BM_SAIF_CTRL_LRCLK_POLARITY         0x200
+#define BF_SAIF_CTRL_LRCLK_POLARITY(v)      (((v) << 9) & 0x200)
+#define BP_SAIF_CTRL_BITCLK_EDGE            8
+#define BM_SAIF_CTRL_BITCLK_EDGE            0x100
+#define BF_SAIF_CTRL_BITCLK_EDGE(v)         (((v) << 8) & 0x100)
+#define BP_SAIF_CTRL_WORD_LENGTH            4
+#define BM_SAIF_CTRL_WORD_LENGTH            0xf0
+#define BF_SAIF_CTRL_WORD_LENGTH(v)         (((v) << 4) & 0xf0)
+#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE    3
+#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE    0x8
+#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8)
+#define BP_SAIF_CTRL_SLAVE_MODE             2
+#define BM_SAIF_CTRL_SLAVE_MODE             0x4
+#define BF_SAIF_CTRL_SLAVE_MODE(v)          (((v) << 2) & 0x4)
+#define BP_SAIF_CTRL_READ_MODE              1
+#define BM_SAIF_CTRL_READ_MODE              0x2
+#define BF_SAIF_CTRL_READ_MODE(v)           (((v) << 1) & 0x2)
+#define BP_SAIF_CTRL_RUN                    0
+#define BM_SAIF_CTRL_RUN                    0x1
+#define BF_SAIF_CTRL_RUN(v)                 (((v) << 0) & 0x1)
+/**
+ * Register: HW_SAIF_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SAIF_STAT(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0))
+#define HW_SAIF_STAT_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4))
+#define HW_SAIF_STAT_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8))
+#define HW_SAIF_STAT_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc))
+#define BP_SAIF_STAT_PRESENT                31
+#define BM_SAIF_STAT_PRESENT                0x80000000
+#define BF_SAIF_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
+#define BP_SAIF_STAT_DMA_PREQ               16
+#define BM_SAIF_STAT_DMA_PREQ               0x10000
+#define BF_SAIF_STAT_DMA_PREQ(v)            (((v) << 16) & 0x10000)
+#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ     6
+#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ     0x40
+#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)  (((v) << 6) & 0x40)
+#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ      5
+#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ      0x20
+#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)   (((v) << 5) & 0x20)
+#define BP_SAIF_STAT_FIFO_SERVICE_IRQ       4
+#define BM_SAIF_STAT_FIFO_SERVICE_IRQ       0x10
+#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v)    (((v) << 4) & 0x10)
+#define BP_SAIF_STAT_BUSY                   0
+#define BM_SAIF_STAT_BUSY                   0x1
+#define BF_SAIF_STAT_BUSY(v)                (((v) << 0) & 0x1)
+/**
+ * Register: HW_SAIF_DATA
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_SAIF_DATA(d)             (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0))
+#define HW_SAIF_DATA_SET(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4))
+#define HW_SAIF_DATA_CLR(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8))
+#define HW_SAIF_DATA_TOG(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc))
+#define BP_SAIF_DATA_PCM_RIGHT      16
+#define BM_SAIF_DATA_PCM_RIGHT      0xffff0000
+#define BF_SAIF_DATA_PCM_RIGHT(v)   (((v) << 16) & 0xffff0000)
+#define BP_SAIF_DATA_PCM_LEFT       0
+#define BM_SAIF_DATA_PCM_LEFT       0xffff
+#define BF_SAIF_DATA_PCM_LEFT(v)    (((v) << 0) & 0xffff)
+/**
+ * Register: HW_SAIF_VERSION
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_SAIF_VERSION(d)          (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30))
+#define BP_SAIF_VERSION_MAJOR       24
+#define BM_SAIF_VERSION_MAJOR       0xff000000
+#define BF_SAIF_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_SAIF_VERSION_MINOR       16
+#define BM_SAIF_VERSION_MINOR       0xff0000
+#define BF_SAIF_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_SAIF_VERSION_STEP        0
+#define BM_SAIF_VERSION_STEP        0xffff
+#define BF_SAIF_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+#endif /* __HEADERGEN__STMP3700__SAIF__H__ */

diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h new file mode 100644 index 0000000000..01faeabc62 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h
@@ -0,0 +1,154 @@
	1	/***************************************************************************
	2	* __________ __ ___.
	3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
	4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
	5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
	6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
	7	* \/ \/ \/ \/ \/
	8	* This file was automatically generated by headergen, DO NOT EDIT it.
	9	* headergen version: 2.1.7
	10	* XML versions: stmp3700:3.2.0
	11	*
	12	* Copyright (C) 2013 by Amaury Pouly
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License
	16	* as published by the Free Software Foundation; either version 2
	17	* of the License, or (at your option) any later version.
	18	*
	19	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
	20	* KIND, either express or implied.
	21	*
	22	****************************************************************************/
	23	#ifndef __HEADERGEN__STMP3700__SAIF__H__
	24	#define __HEADERGEN__STMP3700__SAIF__H__
	25
	26	#define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000)
	27
	28	#define REGS_SAIF_VERSION "3.2.0"
	29
	30	/**
	31	* Register: HW_SAIF_CTRL
	32	* Address: 0
	33	* SCT: yes
	34	*/
	35	#define HW_SAIF_CTRL(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x0 + 0x0))
	36	#define HW_SAIF_CTRL_SET(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x0 + 0x4))
	37	#define HW_SAIF_CTRL_CLR(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x0 + 0x8))
	38	#define HW_SAIF_CTRL_TOG(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x0 + 0xc))
	39	#define BP_SAIF_CTRL_SFTRST 31
	40	#define BM_SAIF_CTRL_SFTRST 0x80000000
	41	#define BF_SAIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
	42	#define BP_SAIF_CTRL_CLKGATE 30
	43	#define BM_SAIF_CTRL_CLKGATE 0x40000000
	44	#define BF_SAIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
	45	#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27
	46	#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
	47	#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) (((v) << 27) & 0x38000000)
	48	#define BP_SAIF_CTRL_BITCLK_BASE_RATE 26
	49	#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x4000000
	50	#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v) (((v) << 26) & 0x4000000)
	51	#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN 25
	52	#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x2000000
	53	#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 25) & 0x2000000)
	54	#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 24
	55	#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x1000000
	56	#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000)
	57	#define BP_SAIF_CTRL_DMAWAIT_COUNT 16
	58	#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x1f0000
	59	#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000)
	60	#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
	61	#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0xc000
	62	#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) (((v) << 14) & 0xc000)
	63	#define BP_SAIF_CTRL_BIT_ORDER 12
	64	#define BM_SAIF_CTRL_BIT_ORDER 0x1000
	65	#define BF_SAIF_CTRL_BIT_ORDER(v) (((v) << 12) & 0x1000)
	66	#define BP_SAIF_CTRL_DELAY 11
	67	#define BM_SAIF_CTRL_DELAY 0x800
	68	#define BF_SAIF_CTRL_DELAY(v) (((v) << 11) & 0x800)
	69	#define BP_SAIF_CTRL_JUSTIFY 10
	70	#define BM_SAIF_CTRL_JUSTIFY 0x400
	71	#define BF_SAIF_CTRL_JUSTIFY(v) (((v) << 10) & 0x400)
	72	#define BP_SAIF_CTRL_LRCLK_POLARITY 9
	73	#define BM_SAIF_CTRL_LRCLK_POLARITY 0x200
	74	#define BF_SAIF_CTRL_LRCLK_POLARITY(v) (((v) << 9) & 0x200)
	75	#define BP_SAIF_CTRL_BITCLK_EDGE 8
	76	#define BM_SAIF_CTRL_BITCLK_EDGE 0x100
	77	#define BF_SAIF_CTRL_BITCLK_EDGE(v) (((v) << 8) & 0x100)
	78	#define BP_SAIF_CTRL_WORD_LENGTH 4
	79	#define BM_SAIF_CTRL_WORD_LENGTH 0xf0
	80	#define BF_SAIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0xf0)
	81	#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE 3
	82	#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x8
	83	#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8)
	84	#define BP_SAIF_CTRL_SLAVE_MODE 2
	85	#define BM_SAIF_CTRL_SLAVE_MODE 0x4
	86	#define BF_SAIF_CTRL_SLAVE_MODE(v) (((v) << 2) & 0x4)
	87	#define BP_SAIF_CTRL_READ_MODE 1
	88	#define BM_SAIF_CTRL_READ_MODE 0x2
	89	#define BF_SAIF_CTRL_READ_MODE(v) (((v) << 1) & 0x2)
	90	#define BP_SAIF_CTRL_RUN 0
	91	#define BM_SAIF_CTRL_RUN 0x1
	92	#define BF_SAIF_CTRL_RUN(v) (((v) << 0) & 0x1)
	93
	94	/**
	95	* Register: HW_SAIF_STAT
	96	* Address: 0x10
	97	* SCT: yes
	98	*/
	99	#define HW_SAIF_STAT(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x10 + 0x0))
	100	#define HW_SAIF_STAT_SET(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x10 + 0x4))
	101	#define HW_SAIF_STAT_CLR(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x10 + 0x8))
	102	#define HW_SAIF_STAT_TOG(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x10 + 0xc))
	103	#define BP_SAIF_STAT_PRESENT 31
	104	#define BM_SAIF_STAT_PRESENT 0x80000000
	105	#define BF_SAIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000)
	106	#define BP_SAIF_STAT_DMA_PREQ 16
	107	#define BM_SAIF_STAT_DMA_PREQ 0x10000
	108	#define BF_SAIF_STAT_DMA_PREQ(v) (((v) << 16) & 0x10000)
	109	#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ 6
	110	#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x40
	111	#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v) (((v) << 6) & 0x40)
	112	#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ 5
	113	#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x20
	114	#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v) (((v) << 5) & 0x20)
	115	#define BP_SAIF_STAT_FIFO_SERVICE_IRQ 4
	116	#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x10
	117	#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v) (((v) << 4) & 0x10)
	118	#define BP_SAIF_STAT_BUSY 0
	119	#define BM_SAIF_STAT_BUSY 0x1
	120	#define BF_SAIF_STAT_BUSY(v) (((v) << 0) & 0x1)
	121
	122	/**
	123	* Register: HW_SAIF_DATA
	124	* Address: 0x20
	125	* SCT: yes
	126	*/
	127	#define HW_SAIF_DATA(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x20 + 0x0))
	128	#define HW_SAIF_DATA_SET(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x20 + 0x4))
	129	#define HW_SAIF_DATA_CLR(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x20 + 0x8))
	130	#define HW_SAIF_DATA_TOG(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x20 + 0xc))
	131	#define BP_SAIF_DATA_PCM_RIGHT 16
	132	#define BM_SAIF_DATA_PCM_RIGHT 0xffff0000
	133	#define BF_SAIF_DATA_PCM_RIGHT(v) (((v) << 16) & 0xffff0000)
	134	#define BP_SAIF_DATA_PCM_LEFT 0
	135	#define BM_SAIF_DATA_PCM_LEFT 0xffff
	136	#define BF_SAIF_DATA_PCM_LEFT(v) (((v) << 0) & 0xffff)
	137
	138	/**
	139	* Register: HW_SAIF_VERSION
	140	* Address: 0x30
	141	* SCT: no
	142	*/
	143	#define HW_SAIF_VERSION(d) ((volatile unsigned long )(REGS_SAIF_BASE(d) + 0x30))
	144	#define BP_SAIF_VERSION_MAJOR 24
	145	#define BM_SAIF_VERSION_MAJOR 0xff000000
	146	#define BF_SAIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
	147	#define BP_SAIF_VERSION_MINOR 16
	148	#define BM_SAIF_VERSION_MINOR 0xff0000
	149	#define BF_SAIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
	150	#define BP_SAIF_VERSION_STEP 0
	151	#define BM_SAIF_VERSION_STEP 0xffff
	152	#define BF_SAIF_VERSION_STEP(v) (((v) << 0) & 0xffff)
	153
	154	#endif /* __HEADERGEN__STMP3700__SAIF__H__ */