diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/imx233/regs-dri.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/imx233/regs-dri.h | 304 |
1 files changed, 304 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dri.h b/firmware/target/arm/imx233/regs/imx233/regs-dri.h new file mode 100644 index 0000000000..4802b28c12 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-dri.h | |||
@@ -0,0 +1,304 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: imx233:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__IMX233__DRI__H__ | ||
24 | #define __HEADERGEN__IMX233__DRI__H__ | ||
25 | |||
26 | #define REGS_DRI_BASE (0x80074000) | ||
27 | |||
28 | #define REGS_DRI_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DRI_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DRI_CTRL_SFTRST 31 | ||
40 | #define BM_DRI_CTRL_SFTRST 0x80000000 | ||
41 | #define BV_DRI_CTRL_SFTRST__RUN 0x0 | ||
42 | #define BV_DRI_CTRL_SFTRST__RESET 0x1 | ||
43 | #define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
44 | #define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
45 | #define BP_DRI_CTRL_CLKGATE 30 | ||
46 | #define BM_DRI_CTRL_CLKGATE 0x40000000 | ||
47 | #define BV_DRI_CTRL_CLKGATE__RUN 0x0 | ||
48 | #define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1 | ||
49 | #define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
50 | #define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
51 | #define BP_DRI_CTRL_ENABLE_INPUTS 29 | ||
52 | #define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 | ||
53 | #define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0 | ||
54 | #define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1 | ||
55 | #define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000) | ||
56 | #define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000) | ||
57 | #define BP_DRI_CTRL_RSVD4 27 | ||
58 | #define BM_DRI_CTRL_RSVD4 0x18000000 | ||
59 | #define BF_DRI_CTRL_RSVD4(v) (((v) << 27) & 0x18000000) | ||
60 | #define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26 | ||
61 | #define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000 | ||
62 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0 | ||
63 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1 | ||
64 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000) | ||
65 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000) | ||
66 | #define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25 | ||
67 | #define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000 | ||
68 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0 | ||
69 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1 | ||
70 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000) | ||
71 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000) | ||
72 | #define BP_DRI_CTRL_RSVD3 21 | ||
73 | #define BM_DRI_CTRL_RSVD3 0x1e00000 | ||
74 | #define BF_DRI_CTRL_RSVD3(v) (((v) << 21) & 0x1e00000) | ||
75 | #define BP_DRI_CTRL_DMA_DELAY_COUNT 16 | ||
76 | #define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000 | ||
77 | #define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000) | ||
78 | #define BP_DRI_CTRL_REACQUIRE_PHASE 15 | ||
79 | #define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000 | ||
80 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0 | ||
81 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1 | ||
82 | #define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000) | ||
83 | #define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000) | ||
84 | #define BP_DRI_CTRL_RSVD2 12 | ||
85 | #define BM_DRI_CTRL_RSVD2 0x7000 | ||
86 | #define BF_DRI_CTRL_RSVD2(v) (((v) << 12) & 0x7000) | ||
87 | #define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11 | ||
88 | #define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800 | ||
89 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0 | ||
90 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1 | ||
91 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800) | ||
92 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800) | ||
93 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10 | ||
94 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400 | ||
95 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0 | ||
96 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1 | ||
97 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
98 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
99 | #define BP_DRI_CTRL_ATTENTION_IRQ_EN 9 | ||
100 | #define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200 | ||
101 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0 | ||
102 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1 | ||
103 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200) | ||
104 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200) | ||
105 | #define BP_DRI_CTRL_RSVD1 4 | ||
106 | #define BM_DRI_CTRL_RSVD1 0x1f0 | ||
107 | #define BF_DRI_CTRL_RSVD1(v) (((v) << 4) & 0x1f0) | ||
108 | #define BP_DRI_CTRL_OVERFLOW_IRQ 3 | ||
109 | #define BM_DRI_CTRL_OVERFLOW_IRQ 0x8 | ||
110 | #define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
111 | #define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1 | ||
112 | #define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
113 | #define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8) | ||
114 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2 | ||
115 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4 | ||
116 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0 | ||
117 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1 | ||
118 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
119 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4) | ||
120 | #define BP_DRI_CTRL_ATTENTION_IRQ 1 | ||
121 | #define BM_DRI_CTRL_ATTENTION_IRQ 0x2 | ||
122 | #define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0 | ||
123 | #define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1 | ||
124 | #define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2) | ||
125 | #define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2) | ||
126 | #define BP_DRI_CTRL_RUN 0 | ||
127 | #define BM_DRI_CTRL_RUN 0x1 | ||
128 | #define BV_DRI_CTRL_RUN__HALT 0x0 | ||
129 | #define BV_DRI_CTRL_RUN__RUN 0x1 | ||
130 | #define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
131 | #define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1) | ||
132 | |||
133 | /** | ||
134 | * Register: HW_DRI_TIMING | ||
135 | * Address: 0x10 | ||
136 | * SCT: no | ||
137 | */ | ||
138 | #define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10)) | ||
139 | #define BP_DRI_TIMING_RSVD2 20 | ||
140 | #define BM_DRI_TIMING_RSVD2 0xfff00000 | ||
141 | #define BF_DRI_TIMING_RSVD2(v) (((v) << 20) & 0xfff00000) | ||
142 | #define BP_DRI_TIMING_PILOT_REP_RATE 16 | ||
143 | #define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000 | ||
144 | #define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000) | ||
145 | #define BP_DRI_TIMING_RSVD1 8 | ||
146 | #define BM_DRI_TIMING_RSVD1 0xff00 | ||
147 | #define BF_DRI_TIMING_RSVD1(v) (((v) << 8) & 0xff00) | ||
148 | #define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 | ||
149 | #define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff | ||
150 | #define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_DRI_STAT | ||
154 | * Address: 0x20 | ||
155 | * SCT: no | ||
156 | */ | ||
157 | #define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20)) | ||
158 | #define BP_DRI_STAT_DRI_PRESENT 31 | ||
159 | #define BM_DRI_STAT_DRI_PRESENT 0x80000000 | ||
160 | #define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0 | ||
161 | #define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1 | ||
162 | #define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000) | ||
163 | #define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000) | ||
164 | #define BP_DRI_STAT_RSVD3 20 | ||
165 | #define BM_DRI_STAT_RSVD3 0x7ff00000 | ||
166 | #define BF_DRI_STAT_RSVD3(v) (((v) << 20) & 0x7ff00000) | ||
167 | #define BP_DRI_STAT_PILOT_PHASE 16 | ||
168 | #define BM_DRI_STAT_PILOT_PHASE 0xf0000 | ||
169 | #define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000) | ||
170 | #define BP_DRI_STAT_RSVD2 4 | ||
171 | #define BM_DRI_STAT_RSVD2 0xfff0 | ||
172 | #define BF_DRI_STAT_RSVD2(v) (((v) << 4) & 0xfff0) | ||
173 | #define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3 | ||
174 | #define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8 | ||
175 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
176 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1 | ||
177 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
178 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8) | ||
179 | #define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2 | ||
180 | #define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4 | ||
181 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
182 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
183 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
184 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
185 | #define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1 | ||
186 | #define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2 | ||
187 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
188 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1 | ||
189 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
190 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2) | ||
191 | #define BP_DRI_STAT_RSVD1 0 | ||
192 | #define BM_DRI_STAT_RSVD1 0x1 | ||
193 | #define BF_DRI_STAT_RSVD1(v) (((v) << 0) & 0x1) | ||
194 | |||
195 | /** | ||
196 | * Register: HW_DRI_DATA | ||
197 | * Address: 0x30 | ||
198 | * SCT: no | ||
199 | */ | ||
200 | #define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30)) | ||
201 | #define BP_DRI_DATA_DATA 0 | ||
202 | #define BM_DRI_DATA_DATA 0xffffffff | ||
203 | #define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
204 | |||
205 | /** | ||
206 | * Register: HW_DRI_DEBUG0 | ||
207 | * Address: 0x40 | ||
208 | * SCT: yes | ||
209 | */ | ||
210 | #define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0)) | ||
211 | #define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4)) | ||
212 | #define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8)) | ||
213 | #define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc)) | ||
214 | #define BP_DRI_DEBUG0_DMAREQ 31 | ||
215 | #define BM_DRI_DEBUG0_DMAREQ 0x80000000 | ||
216 | #define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
217 | #define BP_DRI_DEBUG0_DMACMDKICK 30 | ||
218 | #define BM_DRI_DEBUG0_DMACMDKICK 0x40000000 | ||
219 | #define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000) | ||
220 | #define BP_DRI_DEBUG0_DRI_CLK_INPUT 29 | ||
221 | #define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000 | ||
222 | #define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000) | ||
223 | #define BP_DRI_DEBUG0_DRI_DATA_INPUT 28 | ||
224 | #define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000 | ||
225 | #define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000) | ||
226 | #define BP_DRI_DEBUG0_TEST_MODE 27 | ||
227 | #define BM_DRI_DEBUG0_TEST_MODE 0x8000000 | ||
228 | #define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000) | ||
229 | #define BP_DRI_DEBUG0_PILOT_REP_RATE 26 | ||
230 | #define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000 | ||
231 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0 | ||
232 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1 | ||
233 | #define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000) | ||
234 | #define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000) | ||
235 | #define BP_DRI_DEBUG0_SPARE 18 | ||
236 | #define BM_DRI_DEBUG0_SPARE 0x3fc0000 | ||
237 | #define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000) | ||
238 | #define BP_DRI_DEBUG0_FRAME 0 | ||
239 | #define BM_DRI_DEBUG0_FRAME 0x3ffff | ||
240 | #define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff) | ||
241 | |||
242 | /** | ||
243 | * Register: HW_DRI_DEBUG1 | ||
244 | * Address: 0x50 | ||
245 | * SCT: yes | ||
246 | */ | ||
247 | #define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0)) | ||
248 | #define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4)) | ||
249 | #define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8)) | ||
250 | #define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc)) | ||
251 | #define BP_DRI_DEBUG1_INVERT_PILOT 31 | ||
252 | #define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000 | ||
253 | #define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0 | ||
254 | #define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1 | ||
255 | #define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000) | ||
256 | #define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000) | ||
257 | #define BP_DRI_DEBUG1_INVERT_ATTENTION 30 | ||
258 | #define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000 | ||
259 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0 | ||
260 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1 | ||
261 | #define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000) | ||
262 | #define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000) | ||
263 | #define BP_DRI_DEBUG1_INVERT_DRI_DATA 29 | ||
264 | #define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000 | ||
265 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0 | ||
266 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1 | ||
267 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000) | ||
268 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000) | ||
269 | #define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28 | ||
270 | #define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000 | ||
271 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0 | ||
272 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1 | ||
273 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000) | ||
274 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000) | ||
275 | #define BP_DRI_DEBUG1_REVERSE_FRAME 27 | ||
276 | #define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000 | ||
277 | #define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0 | ||
278 | #define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1 | ||
279 | #define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000) | ||
280 | #define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000) | ||
281 | #define BP_DRI_DEBUG1_RSVD1 18 | ||
282 | #define BM_DRI_DEBUG1_RSVD1 0x7fc0000 | ||
283 | #define BF_DRI_DEBUG1_RSVD1(v) (((v) << 18) & 0x7fc0000) | ||
284 | #define BP_DRI_DEBUG1_SWIZZLED_FRAME 0 | ||
285 | #define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff | ||
286 | #define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff) | ||
287 | |||
288 | /** | ||
289 | * Register: HW_DRI_VERSION | ||
290 | * Address: 0x60 | ||
291 | * SCT: no | ||
292 | */ | ||
293 | #define HW_DRI_VERSION (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60)) | ||
294 | #define BP_DRI_VERSION_MAJOR 24 | ||
295 | #define BM_DRI_VERSION_MAJOR 0xff000000 | ||
296 | #define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
297 | #define BP_DRI_VERSION_MINOR 16 | ||
298 | #define BM_DRI_VERSION_MINOR 0xff0000 | ||
299 | #define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
300 | #define BP_DRI_VERSION_STEP 0 | ||
301 | #define BM_DRI_VERSION_STEP 0xffff | ||
302 | #define BF_DRI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
303 | |||
304 | #endif /* __HEADERGEN__IMX233__DRI__H__ */ | ||