1 files changed, 223 insertions, 0 deletions

diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h
new file mode 100644
index 0000000000..b6e5ead2ba
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h
@@ -0,0 +1,223 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__HWECC__H__
+#define __HEADERGEN__STMP3600__HWECC__H__
+
+#define REGS_HWECC_BASE (0x80008000)
+
+#define REGS_HWECC_VERSION "2.3.0"
+
+/**
+ * Register: HW_HWECC_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_HWECC_CTRL                   (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x0))
+#define HW_HWECC_CTRL_SET               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x4))
+#define HW_HWECC_CTRL_CLR               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x8))
+#define HW_HWECC_CTRL_TOG               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0xc))
+#define BP_HWECC_CTRL_SFTRST            31
+#define BM_HWECC_CTRL_SFTRST            0x80000000
+#define BF_HWECC_CTRL_SFTRST(v)         (((v) << 31) & 0x80000000)
+#define BP_HWECC_CTRL_CLKGATE           30
+#define BM_HWECC_CTRL_CLKGATE           0x40000000
+#define BF_HWECC_CTRL_CLKGATE(v)        (((v) << 30) & 0x40000000)
+#define BP_HWECC_CTRL_NUM_SYMBOLS       16
+#define BM_HWECC_CTRL_NUM_SYMBOLS       0x1ff0000
+#define BF_HWECC_CTRL_NUM_SYMBOLS(v)    (((v) << 16) & 0x1ff0000)
+#define BP_HWECC_CTRL_DMAWAIT_COUNT     8
+#define BM_HWECC_CTRL_DMAWAIT_COUNT     0x1f00
+#define BF_HWECC_CTRL_DMAWAIT_COUNT(v)  (((v) << 8) & 0x1f00)
+#define BP_HWECC_CTRL_BYTE_ENABLE       6
+#define BM_HWECC_CTRL_BYTE_ENABLE       0x40
+#define BF_HWECC_CTRL_BYTE_ENABLE(v)    (((v) << 6) & 0x40)
+#define BP_HWECC_CTRL_ECC_SEL           5
+#define BM_HWECC_CTRL_ECC_SEL           0x20
+#define BF_HWECC_CTRL_ECC_SEL(v)        (((v) << 5) & 0x20)
+#define BP_HWECC_CTRL_ENC_SEL           4
+#define BM_HWECC_CTRL_ENC_SEL           0x10
+#define BF_HWECC_CTRL_ENC_SEL(v)        (((v) << 4) & 0x10)
+#define BP_HWECC_CTRL_UNCORR_IRQ        2
+#define BM_HWECC_CTRL_UNCORR_IRQ        0x4
+#define BF_HWECC_CTRL_UNCORR_IRQ(v)     (((v) << 2) & 0x4)
+#define BP_HWECC_CTRL_UNCORR_IRQ_EN     1
+#define BM_HWECC_CTRL_UNCORR_IRQ_EN     0x2
+#define BF_HWECC_CTRL_UNCORR_IRQ_EN(v)  (((v) << 1) & 0x2)
+#define BP_HWECC_CTRL_RUN               0
+#define BM_HWECC_CTRL_RUN               0x1
+#define BF_HWECC_CTRL_RUN(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_HWECC_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_HWECC_STAT                   (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x10))
+#define BP_HWECC_STAT_RSDEC_PRESENT     31
+#define BM_HWECC_STAT_RSDEC_PRESENT     0x80000000
+#define BF_HWECC_STAT_RSDEC_PRESENT(v)  (((v) << 31) & 0x80000000)
+#define BP_HWECC_STAT_RSENC_PRESENT     30
+#define BM_HWECC_STAT_RSENC_PRESENT     0x40000000
+#define BF_HWECC_STAT_RSENC_PRESENT(v)  (((v) << 30) & 0x40000000)
+#define BP_HWECC_STAT_SSDEC_PRESENT     29
+#define BM_HWECC_STAT_SSDEC_PRESENT     0x20000000
+#define BF_HWECC_STAT_SSDEC_PRESENT(v)  (((v) << 29) & 0x20000000)
+#define BP_HWECC_STAT_SSENC_PRESENT     28
+#define BM_HWECC_STAT_SSENC_PRESENT     0x10000000
+#define BF_HWECC_STAT_SSENC_PRESENT(v)  (((v) << 28) & 0x10000000)
+
+/**
+ * Register: HW_HWECC_DEBUG0
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG0                         (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x20))
+#define BP_HWECC_DEBUG0_DMA_PENDCMD             29
+#define BM_HWECC_DEBUG0_DMA_PENDCMD             0x20000000
+#define BF_HWECC_DEBUG0_DMA_PENDCMD(v)          (((v) << 29) & 0x20000000)
+#define BP_HWECC_DEBUG0_DMA_PREQ                28
+#define BM_HWECC_DEBUG0_DMA_PREQ                0x10000000
+#define BF_HWECC_DEBUG0_DMA_PREQ(v)             (((v) << 28) & 0x10000000)
+#define BP_HWECC_DEBUG0_SYMBOL_STATE            24
+#define BM_HWECC_DEBUG0_SYMBOL_STATE            0xf000000
+#define BF_HWECC_DEBUG0_SYMBOL_STATE(v)         (((v) << 24) & 0xf000000)
+#define BP_HWECC_DEBUG0_CTRL_STATE              16
+#define BM_HWECC_DEBUG0_CTRL_STATE              0x3f0000
+#define BF_HWECC_DEBUG0_CTRL_STATE(v)           (((v) << 16) & 0x3f0000)
+#define BP_HWECC_DEBUG0_ECC_EXCEPTION           12
+#define BM_HWECC_DEBUG0_ECC_EXCEPTION           0xf000
+#define BF_HWECC_DEBUG0_ECC_EXCEPTION(v)        (((v) << 12) & 0xf000)
+#define BP_HWECC_DEBUG0_NUM_BIT_ERRORS          4
+#define BM_HWECC_DEBUG0_NUM_BIT_ERRORS          0x3f0
+#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v)       (((v) << 4) & 0x3f0)
+#define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0
+#define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0x7
+#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v)    (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_HWECC_DEBUG1
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG1                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x30))
+#define BP_HWECC_DEBUG1_SYNDROME2       18
+#define BM_HWECC_DEBUG1_SYNDROME2       0x7fc0000
+#define BF_HWECC_DEBUG1_SYNDROME2(v)    (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG1_SYNDROME1       9
+#define BM_HWECC_DEBUG1_SYNDROME1       0x3fe00
+#define BF_HWECC_DEBUG1_SYNDROME1(v)    (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG1_SYNDROME0       0
+#define BM_HWECC_DEBUG1_SYNDROME0       0x1ff
+#define BF_HWECC_DEBUG1_SYNDROME0(v)    (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG2
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG2                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x40))
+#define BP_HWECC_DEBUG2_SYNDROME5       18
+#define BM_HWECC_DEBUG2_SYNDROME5       0x7fc0000
+#define BF_HWECC_DEBUG2_SYNDROME5(v)    (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG2_SYNDROME4       9
+#define BM_HWECC_DEBUG2_SYNDROME4       0x3fe00
+#define BF_HWECC_DEBUG2_SYNDROME4(v)    (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG2_SYNDROME3       0
+#define BM_HWECC_DEBUG2_SYNDROME3       0x1ff
+#define BF_HWECC_DEBUG2_SYNDROME3(v)    (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG3
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG3                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x50))
+#define BP_HWECC_DEBUG3_OMEGA0          18
+#define BM_HWECC_DEBUG3_OMEGA0          0x7fc0000
+#define BF_HWECC_DEBUG3_OMEGA0(v)       (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG3_SYNDROME7       9
+#define BM_HWECC_DEBUG3_SYNDROME7       0x3fe00
+#define BF_HWECC_DEBUG3_SYNDROME7(v)    (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG3_SYNDROME6       0
+#define BM_HWECC_DEBUG3_SYNDROME6       0x1ff
+#define BF_HWECC_DEBUG3_SYNDROME6(v)    (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG4
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG4             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x60))
+#define BP_HWECC_DEBUG4_OMEGA3      18
+#define BM_HWECC_DEBUG4_OMEGA3      0x7fc0000
+#define BF_HWECC_DEBUG4_OMEGA3(v)   (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG4_OMEGA2      9
+#define BM_HWECC_DEBUG4_OMEGA2      0x3fe00
+#define BF_HWECC_DEBUG4_OMEGA2(v)   (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG4_OMEGA1      0
+#define BM_HWECC_DEBUG4_OMEGA1      0x1ff
+#define BF_HWECC_DEBUG4_OMEGA1(v)   (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG5
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG5             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x70))
+#define BP_HWECC_DEBUG5_LAMBDA2     18
+#define BM_HWECC_DEBUG5_LAMBDA2     0x7fc0000
+#define BF_HWECC_DEBUG5_LAMBDA2(v)  (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG5_LAMBDA1     9
+#define BM_HWECC_DEBUG5_LAMBDA1     0x3fe00
+#define BF_HWECC_DEBUG5_LAMBDA1(v)  (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG5_LAMBDA0     0
+#define BM_HWECC_DEBUG5_LAMBDA0     0x1ff
+#define BF_HWECC_DEBUG5_LAMBDA0(v)  (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG6
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG6             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x80))
+#define BP_HWECC_DEBUG6_LAMBDA4     9
+#define BM_HWECC_DEBUG6_LAMBDA4     0x3fe00
+#define BF_HWECC_DEBUG6_LAMBDA4(v)  (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG6_LAMBDA3     0
+#define BM_HWECC_DEBUG6_LAMBDA3     0x1ff
+#define BF_HWECC_DEBUG6_LAMBDA3(v)  (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DATA
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_HWECC_DATA           (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x0))
+#define HW_HWECC_DATA_SET       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x4))
+#define HW_HWECC_DATA_CLR       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x8))
+#define HW_HWECC_DATA_TOG       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0xc))
+#define BP_HWECC_DATA_DATA      0
+#define BM_HWECC_DATA_DATA      0xffffffff
+#define BF_HWECC_DATA_DATA(v)   (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3600__HWECC__H__ */