diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h | 707 |
1 files changed, 707 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h new file mode 100644 index 0000000000..f0b6273439 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h | |||
@@ -0,0 +1,707 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__DCP__H__ | ||
24 | #define __HEADERGEN__STMP3700__DCP__H__ | ||
25 | |||
26 | #define REGS_DCP_BASE (0x80028000) | ||
27 | |||
28 | #define REGS_DCP_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_DCP_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_DCP_CTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0)) | ||
36 | #define HW_DCP_CTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4)) | ||
37 | #define HW_DCP_CTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8)) | ||
38 | #define HW_DCP_CTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc)) | ||
39 | #define BP_DCP_CTRL_SFTRST 31 | ||
40 | #define BM_DCP_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_DCP_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_DCP_CTRL_CLKGATE 30 | ||
43 | #define BM_DCP_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_DCP_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_DCP_CTRL_PRESENT_CRYPTO 29 | ||
46 | #define BM_DCP_CTRL_PRESENT_CRYPTO 0x20000000 | ||
47 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1 | ||
48 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Absent 0x0 | ||
49 | #define BF_DCP_CTRL_PRESENT_CRYPTO(v) (((v) << 29) & 0x20000000) | ||
50 | #define BF_DCP_CTRL_PRESENT_CRYPTO_V(v) ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000) | ||
51 | #define BP_DCP_CTRL_PRESENT_CSC 28 | ||
52 | #define BM_DCP_CTRL_PRESENT_CSC 0x10000000 | ||
53 | #define BV_DCP_CTRL_PRESENT_CSC__Present 0x1 | ||
54 | #define BV_DCP_CTRL_PRESENT_CSC__Absent 0x0 | ||
55 | #define BF_DCP_CTRL_PRESENT_CSC(v) (((v) << 28) & 0x10000000) | ||
56 | #define BF_DCP_CTRL_PRESENT_CSC_V(v) ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000) | ||
57 | #define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES 23 | ||
58 | #define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x800000 | ||
59 | #define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v) (((v) << 23) & 0x800000) | ||
60 | #define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING 22 | ||
61 | #define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x400000 | ||
62 | #define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v) (((v) << 22) & 0x400000) | ||
63 | #define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 21 | ||
64 | #define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 0x200000 | ||
65 | #define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v) (((v) << 21) & 0x200000) | ||
66 | #define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE 8 | ||
67 | #define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE 0x100 | ||
68 | #define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v) (((v) << 8) & 0x100) | ||
69 | #define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 | ||
70 | #define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0xff | ||
71 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x1 | ||
72 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x2 | ||
73 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x4 | ||
74 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x8 | ||
75 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) (((v) << 0) & 0xff) | ||
76 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v) ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff) | ||
77 | |||
78 | /** | ||
79 | * Register: HW_DCP_STAT | ||
80 | * Address: 0x10 | ||
81 | * SCT: yes | ||
82 | */ | ||
83 | #define HW_DCP_STAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0)) | ||
84 | #define HW_DCP_STAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4)) | ||
85 | #define HW_DCP_STAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8)) | ||
86 | #define HW_DCP_STAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc)) | ||
87 | #define BP_DCP_STAT_OTP_KEY_READY 28 | ||
88 | #define BM_DCP_STAT_OTP_KEY_READY 0x10000000 | ||
89 | #define BF_DCP_STAT_OTP_KEY_READY(v) (((v) << 28) & 0x10000000) | ||
90 | #define BP_DCP_STAT_CUR_CHANNEL 24 | ||
91 | #define BM_DCP_STAT_CUR_CHANNEL 0xf000000 | ||
92 | #define BV_DCP_STAT_CUR_CHANNEL__None 0x0 | ||
93 | #define BV_DCP_STAT_CUR_CHANNEL__CH0 0x1 | ||
94 | #define BV_DCP_STAT_CUR_CHANNEL__CH1 0x2 | ||
95 | #define BV_DCP_STAT_CUR_CHANNEL__CH2 0x3 | ||
96 | #define BV_DCP_STAT_CUR_CHANNEL__CH3 0x4 | ||
97 | #define BV_DCP_STAT_CUR_CHANNEL__CSC 0x8 | ||
98 | #define BF_DCP_STAT_CUR_CHANNEL(v) (((v) << 24) & 0xf000000) | ||
99 | #define BF_DCP_STAT_CUR_CHANNEL_V(v) ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000) | ||
100 | #define BP_DCP_STAT_READY_CHANNELS 16 | ||
101 | #define BM_DCP_STAT_READY_CHANNELS 0xff0000 | ||
102 | #define BV_DCP_STAT_READY_CHANNELS__CH0 0x1 | ||
103 | #define BV_DCP_STAT_READY_CHANNELS__CH1 0x2 | ||
104 | #define BV_DCP_STAT_READY_CHANNELS__CH2 0x4 | ||
105 | #define BV_DCP_STAT_READY_CHANNELS__CH3 0x8 | ||
106 | #define BF_DCP_STAT_READY_CHANNELS(v) (((v) << 16) & 0xff0000) | ||
107 | #define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000) | ||
108 | #define BP_DCP_STAT_CSCIRQ 8 | ||
109 | #define BM_DCP_STAT_CSCIRQ 0x100 | ||
110 | #define BF_DCP_STAT_CSCIRQ(v) (((v) << 8) & 0x100) | ||
111 | #define BP_DCP_STAT_IRQ 0 | ||
112 | #define BM_DCP_STAT_IRQ 0xf | ||
113 | #define BF_DCP_STAT_IRQ(v) (((v) << 0) & 0xf) | ||
114 | |||
115 | /** | ||
116 | * Register: HW_DCP_CHANNELCTRL | ||
117 | * Address: 0x20 | ||
118 | * SCT: yes | ||
119 | */ | ||
120 | #define HW_DCP_CHANNELCTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0)) | ||
121 | #define HW_DCP_CHANNELCTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4)) | ||
122 | #define HW_DCP_CHANNELCTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8)) | ||
123 | #define HW_DCP_CHANNELCTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc)) | ||
124 | #define BP_DCP_CHANNELCTRL_CSC_PRIORITY 17 | ||
125 | #define BM_DCP_CHANNELCTRL_CSC_PRIORITY 0x60000 | ||
126 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH 0x3 | ||
127 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED 0x2 | ||
128 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW 0x1 | ||
129 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0 | ||
130 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v) (((v) << 17) & 0x60000) | ||
131 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v) ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000) | ||
132 | #define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED 16 | ||
133 | #define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED 0x10000 | ||
134 | #define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v) (((v) << 16) & 0x10000) | ||
135 | #define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 8 | ||
136 | #define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 0xff00 | ||
137 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x1 | ||
138 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x2 | ||
139 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x4 | ||
140 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x8 | ||
141 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) (((v) << 8) & 0xff00) | ||
142 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00) | ||
143 | #define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 | ||
144 | #define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0xff | ||
145 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x1 | ||
146 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x2 | ||
147 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x4 | ||
148 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x8 | ||
149 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) (((v) << 0) & 0xff) | ||
150 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff) | ||
151 | |||
152 | /** | ||
153 | * Register: HW_DCP_CAPABILITY0 | ||
154 | * Address: 0x30 | ||
155 | * SCT: no | ||
156 | */ | ||
157 | #define HW_DCP_CAPABILITY0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30)) | ||
158 | #define BP_DCP_CAPABILITY0_NUM_CHANNELS 8 | ||
159 | #define BM_DCP_CAPABILITY0_NUM_CHANNELS 0xf00 | ||
160 | #define BF_DCP_CAPABILITY0_NUM_CHANNELS(v) (((v) << 8) & 0xf00) | ||
161 | #define BP_DCP_CAPABILITY0_NUM_KEYS 0 | ||
162 | #define BM_DCP_CAPABILITY0_NUM_KEYS 0xff | ||
163 | #define BF_DCP_CAPABILITY0_NUM_KEYS(v) (((v) << 0) & 0xff) | ||
164 | |||
165 | /** | ||
166 | * Register: HW_DCP_CAPABILITY1 | ||
167 | * Address: 0x40 | ||
168 | * SCT: no | ||
169 | */ | ||
170 | #define HW_DCP_CAPABILITY1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40)) | ||
171 | #define BP_DCP_CAPABILITY1_HASH_ALGORITHMS 16 | ||
172 | #define BM_DCP_CAPABILITY1_HASH_ALGORITHMS 0xffff0000 | ||
173 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1 0x1 | ||
174 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x2 | ||
175 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) (((v) << 16) & 0xffff0000) | ||
176 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000) | ||
177 | #define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0 | ||
178 | #define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0xffff | ||
179 | #define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x1 | ||
180 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) (((v) << 0) & 0xffff) | ||
181 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_DCP_CONTEXT | ||
185 | * Address: 0x50 | ||
186 | * SCT: no | ||
187 | */ | ||
188 | #define HW_DCP_CONTEXT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50)) | ||
189 | #define BP_DCP_CONTEXT_ADDR 0 | ||
190 | #define BM_DCP_CONTEXT_ADDR 0xffffffff | ||
191 | #define BF_DCP_CONTEXT_ADDR(v) (((v) << 0) & 0xffffffff) | ||
192 | |||
193 | /** | ||
194 | * Register: HW_DCP_KEY | ||
195 | * Address: 0x60 | ||
196 | * SCT: no | ||
197 | */ | ||
198 | #define HW_DCP_KEY (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60)) | ||
199 | #define BP_DCP_KEY_INDEX 4 | ||
200 | #define BM_DCP_KEY_INDEX 0x30 | ||
201 | #define BF_DCP_KEY_INDEX(v) (((v) << 4) & 0x30) | ||
202 | #define BP_DCP_KEY_SUBWORD 0 | ||
203 | #define BM_DCP_KEY_SUBWORD 0x3 | ||
204 | #define BF_DCP_KEY_SUBWORD(v) (((v) << 0) & 0x3) | ||
205 | |||
206 | /** | ||
207 | * Register: HW_DCP_KEYDATA | ||
208 | * Address: 0x70 | ||
209 | * SCT: no | ||
210 | */ | ||
211 | #define HW_DCP_KEYDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70)) | ||
212 | #define BP_DCP_KEYDATA_DATA 0 | ||
213 | #define BM_DCP_KEYDATA_DATA 0xffffffff | ||
214 | #define BF_DCP_KEYDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
215 | |||
216 | /** | ||
217 | * Register: HW_DCP_PACKET0 | ||
218 | * Address: 0x80 | ||
219 | * SCT: no | ||
220 | */ | ||
221 | #define HW_DCP_PACKET0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80)) | ||
222 | #define BP_DCP_PACKET0_ADDR 0 | ||
223 | #define BM_DCP_PACKET0_ADDR 0xffffffff | ||
224 | #define BF_DCP_PACKET0_ADDR(v) (((v) << 0) & 0xffffffff) | ||
225 | |||
226 | /** | ||
227 | * Register: HW_DCP_PACKET1 | ||
228 | * Address: 0x90 | ||
229 | * SCT: no | ||
230 | */ | ||
231 | #define HW_DCP_PACKET1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90)) | ||
232 | #define BP_DCP_PACKET1_TAG 24 | ||
233 | #define BM_DCP_PACKET1_TAG 0xff000000 | ||
234 | #define BF_DCP_PACKET1_TAG(v) (((v) << 24) & 0xff000000) | ||
235 | #define BP_DCP_PACKET1_OUTPUT_WORDSWAP 23 | ||
236 | #define BM_DCP_PACKET1_OUTPUT_WORDSWAP 0x800000 | ||
237 | #define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v) (((v) << 23) & 0x800000) | ||
238 | #define BP_DCP_PACKET1_OUTPUT_BYTESWAP 22 | ||
239 | #define BM_DCP_PACKET1_OUTPUT_BYTESWAP 0x400000 | ||
240 | #define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v) (((v) << 22) & 0x400000) | ||
241 | #define BP_DCP_PACKET1_INPUT_WORDSWAP 21 | ||
242 | #define BM_DCP_PACKET1_INPUT_WORDSWAP 0x200000 | ||
243 | #define BF_DCP_PACKET1_INPUT_WORDSWAP(v) (((v) << 21) & 0x200000) | ||
244 | #define BP_DCP_PACKET1_INPUT_BYTESWAP 20 | ||
245 | #define BM_DCP_PACKET1_INPUT_BYTESWAP 0x100000 | ||
246 | #define BF_DCP_PACKET1_INPUT_BYTESWAP(v) (((v) << 20) & 0x100000) | ||
247 | #define BP_DCP_PACKET1_KEY_WORDSWAP 19 | ||
248 | #define BM_DCP_PACKET1_KEY_WORDSWAP 0x80000 | ||
249 | #define BF_DCP_PACKET1_KEY_WORDSWAP(v) (((v) << 19) & 0x80000) | ||
250 | #define BP_DCP_PACKET1_KEY_BYTESWAP 18 | ||
251 | #define BM_DCP_PACKET1_KEY_BYTESWAP 0x40000 | ||
252 | #define BF_DCP_PACKET1_KEY_BYTESWAP(v) (((v) << 18) & 0x40000) | ||
253 | #define BP_DCP_PACKET1_TEST_SEMA_IRQ 17 | ||
254 | #define BM_DCP_PACKET1_TEST_SEMA_IRQ 0x20000 | ||
255 | #define BF_DCP_PACKET1_TEST_SEMA_IRQ(v) (((v) << 17) & 0x20000) | ||
256 | #define BP_DCP_PACKET1_CONSTANT_FILL 16 | ||
257 | #define BM_DCP_PACKET1_CONSTANT_FILL 0x10000 | ||
258 | #define BF_DCP_PACKET1_CONSTANT_FILL(v) (((v) << 16) & 0x10000) | ||
259 | #define BP_DCP_PACKET1_HASH_OUTPUT 15 | ||
260 | #define BM_DCP_PACKET1_HASH_OUTPUT 0x8000 | ||
261 | #define BV_DCP_PACKET1_HASH_OUTPUT__INPUT 0x0 | ||
262 | #define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x1 | ||
263 | #define BF_DCP_PACKET1_HASH_OUTPUT(v) (((v) << 15) & 0x8000) | ||
264 | #define BF_DCP_PACKET1_HASH_OUTPUT_V(v) ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000) | ||
265 | #define BP_DCP_PACKET1_CHECK_HASH 14 | ||
266 | #define BM_DCP_PACKET1_CHECK_HASH 0x4000 | ||
267 | #define BF_DCP_PACKET1_CHECK_HASH(v) (((v) << 14) & 0x4000) | ||
268 | #define BP_DCP_PACKET1_HASH_TERM 13 | ||
269 | #define BM_DCP_PACKET1_HASH_TERM 0x2000 | ||
270 | #define BF_DCP_PACKET1_HASH_TERM(v) (((v) << 13) & 0x2000) | ||
271 | #define BP_DCP_PACKET1_HASH_INIT 12 | ||
272 | #define BM_DCP_PACKET1_HASH_INIT 0x1000 | ||
273 | #define BF_DCP_PACKET1_HASH_INIT(v) (((v) << 12) & 0x1000) | ||
274 | #define BP_DCP_PACKET1_PAYLOAD_KEY 11 | ||
275 | #define BM_DCP_PACKET1_PAYLOAD_KEY 0x800 | ||
276 | #define BF_DCP_PACKET1_PAYLOAD_KEY(v) (((v) << 11) & 0x800) | ||
277 | #define BP_DCP_PACKET1_OTP_KEY 10 | ||
278 | #define BM_DCP_PACKET1_OTP_KEY 0x400 | ||
279 | #define BF_DCP_PACKET1_OTP_KEY(v) (((v) << 10) & 0x400) | ||
280 | #define BP_DCP_PACKET1_CIPHER_INIT 9 | ||
281 | #define BM_DCP_PACKET1_CIPHER_INIT 0x200 | ||
282 | #define BF_DCP_PACKET1_CIPHER_INIT(v) (((v) << 9) & 0x200) | ||
283 | #define BP_DCP_PACKET1_CIPHER_ENCRYPT 8 | ||
284 | #define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x100 | ||
285 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x1 | ||
286 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x0 | ||
287 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT(v) (((v) << 8) & 0x100) | ||
288 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v) ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100) | ||
289 | #define BP_DCP_PACKET1_ENABLE_BLIT 7 | ||
290 | #define BM_DCP_PACKET1_ENABLE_BLIT 0x80 | ||
291 | #define BF_DCP_PACKET1_ENABLE_BLIT(v) (((v) << 7) & 0x80) | ||
292 | #define BP_DCP_PACKET1_ENABLE_HASH 6 | ||
293 | #define BM_DCP_PACKET1_ENABLE_HASH 0x40 | ||
294 | #define BF_DCP_PACKET1_ENABLE_HASH(v) (((v) << 6) & 0x40) | ||
295 | #define BP_DCP_PACKET1_ENABLE_CIPHER 5 | ||
296 | #define BM_DCP_PACKET1_ENABLE_CIPHER 0x20 | ||
297 | #define BF_DCP_PACKET1_ENABLE_CIPHER(v) (((v) << 5) & 0x20) | ||
298 | #define BP_DCP_PACKET1_ENABLE_MEMCOPY 4 | ||
299 | #define BM_DCP_PACKET1_ENABLE_MEMCOPY 0x10 | ||
300 | #define BF_DCP_PACKET1_ENABLE_MEMCOPY(v) (((v) << 4) & 0x10) | ||
301 | #define BP_DCP_PACKET1_CHAIN_CONTIGUOUS 3 | ||
302 | #define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x8 | ||
303 | #define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v) (((v) << 3) & 0x8) | ||
304 | #define BP_DCP_PACKET1_CHAIN 2 | ||
305 | #define BM_DCP_PACKET1_CHAIN 0x4 | ||
306 | #define BF_DCP_PACKET1_CHAIN(v) (((v) << 2) & 0x4) | ||
307 | #define BP_DCP_PACKET1_DECR_SEMAPHORE 1 | ||
308 | #define BM_DCP_PACKET1_DECR_SEMAPHORE 0x2 | ||
309 | #define BF_DCP_PACKET1_DECR_SEMAPHORE(v) (((v) << 1) & 0x2) | ||
310 | #define BP_DCP_PACKET1_INTERRUPT 0 | ||
311 | #define BM_DCP_PACKET1_INTERRUPT 0x1 | ||
312 | #define BF_DCP_PACKET1_INTERRUPT(v) (((v) << 0) & 0x1) | ||
313 | |||
314 | /** | ||
315 | * Register: HW_DCP_PACKET2 | ||
316 | * Address: 0xa0 | ||
317 | * SCT: no | ||
318 | */ | ||
319 | #define HW_DCP_PACKET2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0)) | ||
320 | #define BP_DCP_PACKET2_CIPHER_CFG 24 | ||
321 | #define BM_DCP_PACKET2_CIPHER_CFG 0xff000000 | ||
322 | #define BF_DCP_PACKET2_CIPHER_CFG(v) (((v) << 24) & 0xff000000) | ||
323 | #define BP_DCP_PACKET2_HASH_SELECT 16 | ||
324 | #define BM_DCP_PACKET2_HASH_SELECT 0xf0000 | ||
325 | #define BV_DCP_PACKET2_HASH_SELECT__SHA1 0x0 | ||
326 | #define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x1 | ||
327 | #define BF_DCP_PACKET2_HASH_SELECT(v) (((v) << 16) & 0xf0000) | ||
328 | #define BF_DCP_PACKET2_HASH_SELECT_V(v) ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000) | ||
329 | #define BP_DCP_PACKET2_KEY_SELECT 8 | ||
330 | #define BM_DCP_PACKET2_KEY_SELECT 0xff00 | ||
331 | #define BF_DCP_PACKET2_KEY_SELECT(v) (((v) << 8) & 0xff00) | ||
332 | #define BP_DCP_PACKET2_CIPHER_MODE 4 | ||
333 | #define BM_DCP_PACKET2_CIPHER_MODE 0xf0 | ||
334 | #define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x0 | ||
335 | #define BV_DCP_PACKET2_CIPHER_MODE__CCB 0x1 | ||
336 | #define BF_DCP_PACKET2_CIPHER_MODE(v) (((v) << 4) & 0xf0) | ||
337 | #define BF_DCP_PACKET2_CIPHER_MODE_V(v) ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0) | ||
338 | #define BP_DCP_PACKET2_CIPHER_SELECT 0 | ||
339 | #define BM_DCP_PACKET2_CIPHER_SELECT 0xf | ||
340 | #define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x0 | ||
341 | #define BF_DCP_PACKET2_CIPHER_SELECT(v) (((v) << 0) & 0xf) | ||
342 | #define BF_DCP_PACKET2_CIPHER_SELECT_V(v) ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf) | ||
343 | |||
344 | /** | ||
345 | * Register: HW_DCP_PACKET3 | ||
346 | * Address: 0xb0 | ||
347 | * SCT: no | ||
348 | */ | ||
349 | #define HW_DCP_PACKET3 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0)) | ||
350 | #define BP_DCP_PACKET3_ADDR 0 | ||
351 | #define BM_DCP_PACKET3_ADDR 0xffffffff | ||
352 | #define BF_DCP_PACKET3_ADDR(v) (((v) << 0) & 0xffffffff) | ||
353 | |||
354 | /** | ||
355 | * Register: HW_DCP_PACKET4 | ||
356 | * Address: 0xc0 | ||
357 | * SCT: no | ||
358 | */ | ||
359 | #define HW_DCP_PACKET4 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0)) | ||
360 | #define BP_DCP_PACKET4_ADDR 0 | ||
361 | #define BM_DCP_PACKET4_ADDR 0xffffffff | ||
362 | #define BF_DCP_PACKET4_ADDR(v) (((v) << 0) & 0xffffffff) | ||
363 | |||
364 | /** | ||
365 | * Register: HW_DCP_PACKET5 | ||
366 | * Address: 0xd0 | ||
367 | * SCT: no | ||
368 | */ | ||
369 | #define HW_DCP_PACKET5 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0)) | ||
370 | #define BP_DCP_PACKET5_COUNT 0 | ||
371 | #define BM_DCP_PACKET5_COUNT 0xffffffff | ||
372 | #define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff) | ||
373 | |||
374 | /** | ||
375 | * Register: HW_DCP_PACKET6 | ||
376 | * Address: 0xe0 | ||
377 | * SCT: no | ||
378 | */ | ||
379 | #define HW_DCP_PACKET6 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0)) | ||
380 | #define BP_DCP_PACKET6_ADDR 0 | ||
381 | #define BM_DCP_PACKET6_ADDR 0xffffffff | ||
382 | #define BF_DCP_PACKET6_ADDR(v) (((v) << 0) & 0xffffffff) | ||
383 | |||
384 | /** | ||
385 | * Register: HW_DCP_CHnCMDPTR | ||
386 | * Address: 0x100+n*0x40 | ||
387 | * SCT: no | ||
388 | */ | ||
389 | #define HW_DCP_CHnCMDPTR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40)) | ||
390 | #define BP_DCP_CHnCMDPTR_ADDR 0 | ||
391 | #define BM_DCP_CHnCMDPTR_ADDR 0xffffffff | ||
392 | #define BF_DCP_CHnCMDPTR_ADDR(v) (((v) << 0) & 0xffffffff) | ||
393 | |||
394 | /** | ||
395 | * Register: HW_DCP_CHnSEMA | ||
396 | * Address: 0x110+n*0x40 | ||
397 | * SCT: no | ||
398 | */ | ||
399 | #define HW_DCP_CHnSEMA(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40)) | ||
400 | #define BP_DCP_CHnSEMA_VALUE 16 | ||
401 | #define BM_DCP_CHnSEMA_VALUE 0xff0000 | ||
402 | #define BF_DCP_CHnSEMA_VALUE(v) (((v) << 16) & 0xff0000) | ||
403 | #define BP_DCP_CHnSEMA_INCREMENT 0 | ||
404 | #define BM_DCP_CHnSEMA_INCREMENT 0xff | ||
405 | #define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff) | ||
406 | |||
407 | /** | ||
408 | * Register: HW_DCP_CHnSTAT | ||
409 | * Address: 0x120+n*0x40 | ||
410 | * SCT: yes | ||
411 | */ | ||
412 | #define HW_DCP_CHnSTAT(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0)) | ||
413 | #define HW_DCP_CHnSTAT_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4)) | ||
414 | #define HW_DCP_CHnSTAT_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8)) | ||
415 | #define HW_DCP_CHnSTAT_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc)) | ||
416 | #define BP_DCP_CHnSTAT_TAG 24 | ||
417 | #define BM_DCP_CHnSTAT_TAG 0xff000000 | ||
418 | #define BF_DCP_CHnSTAT_TAG(v) (((v) << 24) & 0xff000000) | ||
419 | #define BP_DCP_CHnSTAT_ERROR_CODE 16 | ||
420 | #define BM_DCP_CHnSTAT_ERROR_CODE 0xff0000 | ||
421 | #define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x1 | ||
422 | #define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN 0x2 | ||
423 | #define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR 0x3 | ||
424 | #define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR 0x4 | ||
425 | #define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE 0x5 | ||
426 | #define BF_DCP_CHnSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
427 | #define BF_DCP_CHnSTAT_ERROR_CODE_V(v) ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
428 | #define BP_DCP_CHnSTAT_ERROR_DST 5 | ||
429 | #define BM_DCP_CHnSTAT_ERROR_DST 0x20 | ||
430 | #define BF_DCP_CHnSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
431 | #define BP_DCP_CHnSTAT_ERROR_SRC 4 | ||
432 | #define BM_DCP_CHnSTAT_ERROR_SRC 0x10 | ||
433 | #define BF_DCP_CHnSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
434 | #define BP_DCP_CHnSTAT_ERROR_PACKET 3 | ||
435 | #define BM_DCP_CHnSTAT_ERROR_PACKET 0x8 | ||
436 | #define BF_DCP_CHnSTAT_ERROR_PACKET(v) (((v) << 3) & 0x8) | ||
437 | #define BP_DCP_CHnSTAT_ERROR_SETUP 2 | ||
438 | #define BM_DCP_CHnSTAT_ERROR_SETUP 0x4 | ||
439 | #define BF_DCP_CHnSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
440 | #define BP_DCP_CHnSTAT_HASH_MISMATCH 1 | ||
441 | #define BM_DCP_CHnSTAT_HASH_MISMATCH 0x2 | ||
442 | #define BF_DCP_CHnSTAT_HASH_MISMATCH(v) (((v) << 1) & 0x2) | ||
443 | |||
444 | /** | ||
445 | * Register: HW_DCP_CHnOPTS | ||
446 | * Address: 0x130+n*0x40 | ||
447 | * SCT: yes | ||
448 | */ | ||
449 | #define HW_DCP_CHnOPTS(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0)) | ||
450 | #define HW_DCP_CHnOPTS_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4)) | ||
451 | #define HW_DCP_CHnOPTS_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8)) | ||
452 | #define HW_DCP_CHnOPTS_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc)) | ||
453 | #define BP_DCP_CHnOPTS_RECOVERY_TIMER 0 | ||
454 | #define BM_DCP_CHnOPTS_RECOVERY_TIMER 0xffff | ||
455 | #define BF_DCP_CHnOPTS_RECOVERY_TIMER(v) (((v) << 0) & 0xffff) | ||
456 | |||
457 | /** | ||
458 | * Register: HW_DCP_CSCCTRL0 | ||
459 | * Address: 0x300 | ||
460 | * SCT: yes | ||
461 | */ | ||
462 | #define HW_DCP_CSCCTRL0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0)) | ||
463 | #define HW_DCP_CSCCTRL0_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4)) | ||
464 | #define HW_DCP_CSCCTRL0_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8)) | ||
465 | #define HW_DCP_CSCCTRL0_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc)) | ||
466 | #define BP_DCP_CSCCTRL0_UPSAMPLE 14 | ||
467 | #define BM_DCP_CSCCTRL0_UPSAMPLE 0x4000 | ||
468 | #define BF_DCP_CSCCTRL0_UPSAMPLE(v) (((v) << 14) & 0x4000) | ||
469 | #define BP_DCP_CSCCTRL0_SCALE 13 | ||
470 | #define BM_DCP_CSCCTRL0_SCALE 0x2000 | ||
471 | #define BF_DCP_CSCCTRL0_SCALE(v) (((v) << 13) & 0x2000) | ||
472 | #define BP_DCP_CSCCTRL0_ROTATE 12 | ||
473 | #define BM_DCP_CSCCTRL0_ROTATE 0x1000 | ||
474 | #define BF_DCP_CSCCTRL0_ROTATE(v) (((v) << 12) & 0x1000) | ||
475 | #define BP_DCP_CSCCTRL0_SUBSAMPLE 11 | ||
476 | #define BM_DCP_CSCCTRL0_SUBSAMPLE 0x800 | ||
477 | #define BF_DCP_CSCCTRL0_SUBSAMPLE(v) (((v) << 11) & 0x800) | ||
478 | #define BP_DCP_CSCCTRL0_DELTA 10 | ||
479 | #define BM_DCP_CSCCTRL0_DELTA 0x400 | ||
480 | #define BF_DCP_CSCCTRL0_DELTA(v) (((v) << 10) & 0x400) | ||
481 | #define BP_DCP_CSCCTRL0_RGB_FORMAT 8 | ||
482 | #define BM_DCP_CSCCTRL0_RGB_FORMAT 0x300 | ||
483 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0 | ||
484 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24 0x2 | ||
485 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I 0x3 | ||
486 | #define BF_DCP_CSCCTRL0_RGB_FORMAT(v) (((v) << 8) & 0x300) | ||
487 | #define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v) ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300) | ||
488 | #define BP_DCP_CSCCTRL0_YUV_FORMAT 4 | ||
489 | #define BM_DCP_CSCCTRL0_YUV_FORMAT 0xf0 | ||
490 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0 | ||
491 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2 | ||
492 | #define BF_DCP_CSCCTRL0_YUV_FORMAT(v) (((v) << 4) & 0xf0) | ||
493 | #define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v) ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0) | ||
494 | #define BP_DCP_CSCCTRL0_ENABLE 0 | ||
495 | #define BM_DCP_CSCCTRL0_ENABLE 0x1 | ||
496 | #define BF_DCP_CSCCTRL0_ENABLE(v) (((v) << 0) & 0x1) | ||
497 | |||
498 | /** | ||
499 | * Register: HW_DCP_CSCSTAT | ||
500 | * Address: 0x310 | ||
501 | * SCT: yes | ||
502 | */ | ||
503 | #define HW_DCP_CSCSTAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0)) | ||
504 | #define HW_DCP_CSCSTAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4)) | ||
505 | #define HW_DCP_CSCSTAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8)) | ||
506 | #define HW_DCP_CSCSTAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc)) | ||
507 | #define BP_DCP_CSCSTAT_ERROR_CODE 16 | ||
508 | #define BM_DCP_CSCSTAT_ERROR_CODE 0xff0000 | ||
509 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1 | ||
510 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2 | ||
511 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3 | ||
512 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4 | ||
513 | #define BF_DCP_CSCSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
514 | #define BF_DCP_CSCSTAT_ERROR_CODE_V(v) ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
515 | #define BP_DCP_CSCSTAT_ERROR_DST 5 | ||
516 | #define BM_DCP_CSCSTAT_ERROR_DST 0x20 | ||
517 | #define BF_DCP_CSCSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
518 | #define BP_DCP_CSCSTAT_ERROR_SRC 4 | ||
519 | #define BM_DCP_CSCSTAT_ERROR_SRC 0x10 | ||
520 | #define BF_DCP_CSCSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
521 | #define BP_DCP_CSCSTAT_ERROR_SETUP 2 | ||
522 | #define BM_DCP_CSCSTAT_ERROR_SETUP 0x4 | ||
523 | #define BF_DCP_CSCSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
524 | #define BP_DCP_CSCSTAT_COMPLETE 0 | ||
525 | #define BM_DCP_CSCSTAT_COMPLETE 0x1 | ||
526 | #define BF_DCP_CSCSTAT_COMPLETE(v) (((v) << 0) & 0x1) | ||
527 | |||
528 | /** | ||
529 | * Register: HW_DCP_CSCOUTBUFPARAM | ||
530 | * Address: 0x320 | ||
531 | * SCT: no | ||
532 | */ | ||
533 | #define HW_DCP_CSCOUTBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320)) | ||
534 | #define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE 12 | ||
535 | #define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE 0xfff000 | ||
536 | #define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000) | ||
537 | #define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE 0 | ||
538 | #define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE 0xfff | ||
539 | #define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
540 | |||
541 | /** | ||
542 | * Register: HW_DCP_CSCINBUFPARAM | ||
543 | * Address: 0x330 | ||
544 | * SCT: no | ||
545 | */ | ||
546 | #define HW_DCP_CSCINBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330)) | ||
547 | #define BP_DCP_CSCINBUFPARAM_LINE_SIZE 0 | ||
548 | #define BM_DCP_CSCINBUFPARAM_LINE_SIZE 0xfff | ||
549 | #define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
550 | |||
551 | /** | ||
552 | * Register: HW_DCP_CSCRGB | ||
553 | * Address: 0x340 | ||
554 | * SCT: no | ||
555 | */ | ||
556 | #define HW_DCP_CSCRGB (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340)) | ||
557 | #define BP_DCP_CSCRGB_ADDR 0 | ||
558 | #define BM_DCP_CSCRGB_ADDR 0xffffffff | ||
559 | #define BF_DCP_CSCRGB_ADDR(v) (((v) << 0) & 0xffffffff) | ||
560 | |||
561 | /** | ||
562 | * Register: HW_DCP_CSCLUMA | ||
563 | * Address: 0x350 | ||
564 | * SCT: no | ||
565 | */ | ||
566 | #define HW_DCP_CSCLUMA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350)) | ||
567 | #define BP_DCP_CSCLUMA_ADDR 0 | ||
568 | #define BM_DCP_CSCLUMA_ADDR 0xffffffff | ||
569 | #define BF_DCP_CSCLUMA_ADDR(v) (((v) << 0) & 0xffffffff) | ||
570 | |||
571 | /** | ||
572 | * Register: HW_DCP_CSCCHROMAU | ||
573 | * Address: 0x360 | ||
574 | * SCT: no | ||
575 | */ | ||
576 | #define HW_DCP_CSCCHROMAU (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360)) | ||
577 | #define BP_DCP_CSCCHROMAU_ADDR 0 | ||
578 | #define BM_DCP_CSCCHROMAU_ADDR 0xffffffff | ||
579 | #define BF_DCP_CSCCHROMAU_ADDR(v) (((v) << 0) & 0xffffffff) | ||
580 | |||
581 | /** | ||
582 | * Register: HW_DCP_CSCCHROMAV | ||
583 | * Address: 0x370 | ||
584 | * SCT: no | ||
585 | */ | ||
586 | #define HW_DCP_CSCCHROMAV (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370)) | ||
587 | #define BP_DCP_CSCCHROMAV_ADDR 0 | ||
588 | #define BM_DCP_CSCCHROMAV_ADDR 0xffffffff | ||
589 | #define BF_DCP_CSCCHROMAV_ADDR(v) (((v) << 0) & 0xffffffff) | ||
590 | |||
591 | /** | ||
592 | * Register: HW_DCP_CSCCOEFF0 | ||
593 | * Address: 0x380 | ||
594 | * SCT: no | ||
595 | */ | ||
596 | #define HW_DCP_CSCCOEFF0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380)) | ||
597 | #define BP_DCP_CSCCOEFF0_C0 16 | ||
598 | #define BM_DCP_CSCCOEFF0_C0 0x3ff0000 | ||
599 | #define BF_DCP_CSCCOEFF0_C0(v) (((v) << 16) & 0x3ff0000) | ||
600 | #define BP_DCP_CSCCOEFF0_UV_OFFSET 8 | ||
601 | #define BM_DCP_CSCCOEFF0_UV_OFFSET 0xff00 | ||
602 | #define BF_DCP_CSCCOEFF0_UV_OFFSET(v) (((v) << 8) & 0xff00) | ||
603 | #define BP_DCP_CSCCOEFF0_Y_OFFSET 0 | ||
604 | #define BM_DCP_CSCCOEFF0_Y_OFFSET 0xff | ||
605 | #define BF_DCP_CSCCOEFF0_Y_OFFSET(v) (((v) << 0) & 0xff) | ||
606 | |||
607 | /** | ||
608 | * Register: HW_DCP_CSCCOEFF1 | ||
609 | * Address: 0x390 | ||
610 | * SCT: no | ||
611 | */ | ||
612 | #define HW_DCP_CSCCOEFF1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390)) | ||
613 | #define BP_DCP_CSCCOEFF1_C1 16 | ||
614 | #define BM_DCP_CSCCOEFF1_C1 0x3ff0000 | ||
615 | #define BF_DCP_CSCCOEFF1_C1(v) (((v) << 16) & 0x3ff0000) | ||
616 | #define BP_DCP_CSCCOEFF1_C4 0 | ||
617 | #define BM_DCP_CSCCOEFF1_C4 0x3ff | ||
618 | #define BF_DCP_CSCCOEFF1_C4(v) (((v) << 0) & 0x3ff) | ||
619 | |||
620 | /** | ||
621 | * Register: HW_DCP_CSCCOEFF2 | ||
622 | * Address: 0x3a0 | ||
623 | * SCT: no | ||
624 | */ | ||
625 | #define HW_DCP_CSCCOEFF2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0)) | ||
626 | #define BP_DCP_CSCCOEFF2_C2 16 | ||
627 | #define BM_DCP_CSCCOEFF2_C2 0x3ff0000 | ||
628 | #define BF_DCP_CSCCOEFF2_C2(v) (((v) << 16) & 0x3ff0000) | ||
629 | #define BP_DCP_CSCCOEFF2_C3 0 | ||
630 | #define BM_DCP_CSCCOEFF2_C3 0x3ff | ||
631 | #define BF_DCP_CSCCOEFF2_C3(v) (((v) << 0) & 0x3ff) | ||
632 | |||
633 | /** | ||
634 | * Register: HW_DCP_CSCXSCALE | ||
635 | * Address: 0x3e0 | ||
636 | * SCT: no | ||
637 | */ | ||
638 | #define HW_DCP_CSCXSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0)) | ||
639 | #define BP_DCP_CSCXSCALE_INT 24 | ||
640 | #define BM_DCP_CSCXSCALE_INT 0x3000000 | ||
641 | #define BF_DCP_CSCXSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
642 | #define BP_DCP_CSCXSCALE_FRAC 12 | ||
643 | #define BM_DCP_CSCXSCALE_FRAC 0xfff000 | ||
644 | #define BF_DCP_CSCXSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
645 | #define BP_DCP_CSCXSCALE_WIDTH 0 | ||
646 | #define BM_DCP_CSCXSCALE_WIDTH 0xfff | ||
647 | #define BF_DCP_CSCXSCALE_WIDTH(v) (((v) << 0) & 0xfff) | ||
648 | |||
649 | /** | ||
650 | * Register: HW_DCP_CSCYSCALE | ||
651 | * Address: 0x3f0 | ||
652 | * SCT: no | ||
653 | */ | ||
654 | #define HW_DCP_CSCYSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0)) | ||
655 | #define BP_DCP_CSCYSCALE_INT 24 | ||
656 | #define BM_DCP_CSCYSCALE_INT 0x3000000 | ||
657 | #define BF_DCP_CSCYSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
658 | #define BP_DCP_CSCYSCALE_FRAC 12 | ||
659 | #define BM_DCP_CSCYSCALE_FRAC 0xfff000 | ||
660 | #define BF_DCP_CSCYSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
661 | #define BP_DCP_CSCYSCALE_HEIGHT 0 | ||
662 | #define BM_DCP_CSCYSCALE_HEIGHT 0xfff | ||
663 | #define BF_DCP_CSCYSCALE_HEIGHT(v) (((v) << 0) & 0xfff) | ||
664 | |||
665 | /** | ||
666 | * Register: HW_DCP_DBGSELECT | ||
667 | * Address: 0x400 | ||
668 | * SCT: no | ||
669 | */ | ||
670 | #define HW_DCP_DBGSELECT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400)) | ||
671 | #define BP_DCP_DBGSELECT_INDEX 0 | ||
672 | #define BM_DCP_DBGSELECT_INDEX 0xff | ||
673 | #define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1 | ||
674 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10 | ||
675 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11 | ||
676 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12 | ||
677 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13 | ||
678 | #define BF_DCP_DBGSELECT_INDEX(v) (((v) << 0) & 0xff) | ||
679 | #define BF_DCP_DBGSELECT_INDEX_V(v) ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff) | ||
680 | |||
681 | /** | ||
682 | * Register: HW_DCP_DBGDATA | ||
683 | * Address: 0x410 | ||
684 | * SCT: no | ||
685 | */ | ||
686 | #define HW_DCP_DBGDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410)) | ||
687 | #define BP_DCP_DBGDATA_DATA 0 | ||
688 | #define BM_DCP_DBGDATA_DATA 0xffffffff | ||
689 | #define BF_DCP_DBGDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
690 | |||
691 | /** | ||
692 | * Register: HW_DCP_VERSION | ||
693 | * Address: 0x420 | ||
694 | * SCT: no | ||
695 | */ | ||
696 | #define HW_DCP_VERSION (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420)) | ||
697 | #define BP_DCP_VERSION_MAJOR 24 | ||
698 | #define BM_DCP_VERSION_MAJOR 0xff000000 | ||
699 | #define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
700 | #define BP_DCP_VERSION_MINOR 16 | ||
701 | #define BM_DCP_VERSION_MINOR 0xff0000 | ||
702 | #define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
703 | #define BP_DCP_VERSION_STEP 0 | ||
704 | #define BM_DCP_VERSION_STEP 0xffff | ||
705 | #define BF_DCP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
706 | |||
707 | #endif /* __HEADERGEN__STMP3700__DCP__H__ */ | ||