diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h | 267 |
1 files changed, 267 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h new file mode 100644 index 0000000000..a726662ac8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h | |||
@@ -0,0 +1,267 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.3.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__TIMROT__H__ | ||
24 | #define __HEADERGEN__STMP3600__TIMROT__H__ | ||
25 | |||
26 | #define REGS_TIMROT_BASE (0x80068000) | ||
27 | |||
28 | #define REGS_TIMROT_VERSION "2.3.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_TIMROT_ROTCTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_TIMROT_ROTCTRL (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0)) | ||
36 | #define HW_TIMROT_ROTCTRL_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4)) | ||
37 | #define HW_TIMROT_ROTCTRL_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8)) | ||
38 | #define HW_TIMROT_ROTCTRL_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc)) | ||
39 | #define BP_TIMROT_ROTCTRL_SFTRST 31 | ||
40 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | ||
41 | #define BF_TIMROT_ROTCTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_TIMROT_ROTCTRL_CLKGATE 30 | ||
43 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | ||
44 | #define BF_TIMROT_ROTCTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_TIMROT_ROTCTRL_ROTARY_PRESENT 29 | ||
46 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | ||
47 | #define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v) (((v) << 29) & 0x20000000) | ||
48 | #define BP_TIMROT_ROTCTRL_TIM3_PRESENT 28 | ||
49 | #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 | ||
50 | #define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
51 | #define BP_TIMROT_ROTCTRL_TIM2_PRESENT 27 | ||
52 | #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x8000000 | ||
53 | #define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
54 | #define BP_TIMROT_ROTCTRL_TIM1_PRESENT 26 | ||
55 | #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x4000000 | ||
56 | #define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
57 | #define BP_TIMROT_ROTCTRL_TIM0_PRESENT 25 | ||
58 | #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x2000000 | ||
59 | #define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
60 | #define BP_TIMROT_ROTCTRL_STATE 22 | ||
61 | #define BM_TIMROT_ROTCTRL_STATE 0x1c00000 | ||
62 | #define BF_TIMROT_ROTCTRL_STATE(v) (((v) << 22) & 0x1c00000) | ||
63 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | ||
64 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x3f0000 | ||
65 | #define BF_TIMROT_ROTCTRL_DIVIDER(v) (((v) << 16) & 0x3f0000) | ||
66 | #define BP_TIMROT_ROTCTRL_RELATIVE 12 | ||
67 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x1000 | ||
68 | #define BF_TIMROT_ROTCTRL_RELATIVE(v) (((v) << 12) & 0x1000) | ||
69 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | ||
70 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0xc00 | ||
71 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 | ||
72 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 | ||
73 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 | ||
74 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 | ||
75 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) (((v) << 10) & 0xc00) | ||
76 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v) ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00) | ||
77 | #define BP_TIMROT_ROTCTRL_POLARITY_B 9 | ||
78 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x200 | ||
79 | #define BF_TIMROT_ROTCTRL_POLARITY_B(v) (((v) << 9) & 0x200) | ||
80 | #define BP_TIMROT_ROTCTRL_POLARITY_A 8 | ||
81 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x100 | ||
82 | #define BF_TIMROT_ROTCTRL_POLARITY_A(v) (((v) << 8) & 0x100) | ||
83 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
84 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x70 | ||
85 | #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 | ||
86 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 | ||
87 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 | ||
88 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 | ||
89 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 | ||
90 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 | ||
91 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 | ||
92 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 | ||
93 | #define BF_TIMROT_ROTCTRL_SELECT_B(v) (((v) << 4) & 0x70) | ||
94 | #define BF_TIMROT_ROTCTRL_SELECT_B_V(v) ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70) | ||
95 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
96 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x7 | ||
97 | #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 | ||
98 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 | ||
99 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 | ||
100 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 | ||
101 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 | ||
102 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 | ||
103 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 | ||
104 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 | ||
105 | #define BF_TIMROT_ROTCTRL_SELECT_A(v) (((v) << 0) & 0x7) | ||
106 | #define BF_TIMROT_ROTCTRL_SELECT_A_V(v) ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7) | ||
107 | |||
108 | /** | ||
109 | * Register: HW_TIMROT_ROTCOUNT | ||
110 | * Address: 0x10 | ||
111 | * SCT: no | ||
112 | */ | ||
113 | #define HW_TIMROT_ROTCOUNT (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10)) | ||
114 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 | ||
115 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0xffff | ||
116 | #define BF_TIMROT_ROTCOUNT_UPDOWN(v) (((v) << 0) & 0xffff) | ||
117 | |||
118 | /** | ||
119 | * Register: HW_TIMROT_TIMCTRL3 | ||
120 | * Address: 0x80 | ||
121 | * SCT: yes | ||
122 | */ | ||
123 | #define HW_TIMROT_TIMCTRL3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0)) | ||
124 | #define HW_TIMROT_TIMCTRL3_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4)) | ||
125 | #define HW_TIMROT_TIMCTRL3_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8)) | ||
126 | #define HW_TIMROT_TIMCTRL3_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc)) | ||
127 | #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 | ||
128 | #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0xf0000 | ||
129 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 | ||
130 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 | ||
131 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 | ||
132 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 | ||
133 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 | ||
134 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 | ||
135 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 | ||
136 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 | ||
137 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 | ||
138 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 | ||
139 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xa | ||
140 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xb | ||
141 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc | ||
142 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) (((v) << 16) & 0xf0000) | ||
143 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v) ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000) | ||
144 | #define BP_TIMROT_TIMCTRL3_IRQ 15 | ||
145 | #define BM_TIMROT_TIMCTRL3_IRQ 0x8000 | ||
146 | #define BF_TIMROT_TIMCTRL3_IRQ(v) (((v) << 15) & 0x8000) | ||
147 | #define BP_TIMROT_TIMCTRL3_IRQ_EN 14 | ||
148 | #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x4000 | ||
149 | #define BF_TIMROT_TIMCTRL3_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
150 | #define BP_TIMROT_TIMCTRL3_DUTY_VALID 10 | ||
151 | #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x400 | ||
152 | #define BF_TIMROT_TIMCTRL3_DUTY_VALID(v) (((v) << 10) & 0x400) | ||
153 | #define BP_TIMROT_TIMCTRL3_DUTY_CYCLE 9 | ||
154 | #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x200 | ||
155 | #define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v) (((v) << 9) & 0x200) | ||
156 | #define BP_TIMROT_TIMCTRL3_POLARITY 8 | ||
157 | #define BM_TIMROT_TIMCTRL3_POLARITY 0x100 | ||
158 | #define BF_TIMROT_TIMCTRL3_POLARITY(v) (((v) << 8) & 0x100) | ||
159 | #define BP_TIMROT_TIMCTRL3_UPDATE 7 | ||
160 | #define BM_TIMROT_TIMCTRL3_UPDATE 0x80 | ||
161 | #define BF_TIMROT_TIMCTRL3_UPDATE(v) (((v) << 7) & 0x80) | ||
162 | #define BP_TIMROT_TIMCTRL3_RELOAD 6 | ||
163 | #define BM_TIMROT_TIMCTRL3_RELOAD 0x40 | ||
164 | #define BF_TIMROT_TIMCTRL3_RELOAD(v) (((v) << 6) & 0x40) | ||
165 | #define BP_TIMROT_TIMCTRL3_PRESCALE 4 | ||
166 | #define BM_TIMROT_TIMCTRL3_PRESCALE 0x30 | ||
167 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 | ||
168 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 | ||
169 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 | ||
170 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 | ||
171 | #define BF_TIMROT_TIMCTRL3_PRESCALE(v) (((v) << 4) & 0x30) | ||
172 | #define BF_TIMROT_TIMCTRL3_PRESCALE_V(v) ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30) | ||
173 | #define BP_TIMROT_TIMCTRL3_SELECT 0 | ||
174 | #define BM_TIMROT_TIMCTRL3_SELECT 0xf | ||
175 | #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 | ||
176 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 | ||
177 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 | ||
178 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 | ||
179 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 | ||
180 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 | ||
181 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 | ||
182 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 | ||
183 | #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 | ||
184 | #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 | ||
185 | #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xa | ||
186 | #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xb | ||
187 | #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xc | ||
188 | #define BF_TIMROT_TIMCTRL3_SELECT(v) (((v) << 0) & 0xf) | ||
189 | #define BF_TIMROT_TIMCTRL3_SELECT_V(v) ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf) | ||
190 | |||
191 | /** | ||
192 | * Register: HW_TIMROT_TIMCOUNT3 | ||
193 | * Address: 0x90 | ||
194 | * SCT: no | ||
195 | */ | ||
196 | #define HW_TIMROT_TIMCOUNT3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90)) | ||
197 | #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 | ||
198 | #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xffff0000 | ||
199 | #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
200 | #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 | ||
201 | #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0xffff | ||
202 | #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
203 | |||
204 | /** | ||
205 | * Register: HW_TIMROT_TIMCOUNTn | ||
206 | * Address: 0x30+n*0x20 | ||
207 | * SCT: no | ||
208 | */ | ||
209 | #define HW_TIMROT_TIMCOUNTn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20)) | ||
210 | #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 | ||
211 | #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xffff0000 | ||
212 | #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
213 | #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 | ||
214 | #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0xffff | ||
215 | #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
216 | |||
217 | /** | ||
218 | * Register: HW_TIMROT_TIMCTRLn | ||
219 | * Address: 0x20+n*0x20 | ||
220 | * SCT: yes | ||
221 | */ | ||
222 | #define HW_TIMROT_TIMCTRLn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0)) | ||
223 | #define HW_TIMROT_TIMCTRLn_SET(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4)) | ||
224 | #define HW_TIMROT_TIMCTRLn_CLR(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8)) | ||
225 | #define HW_TIMROT_TIMCTRLn_TOG(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc)) | ||
226 | #define BP_TIMROT_TIMCTRLn_IRQ 15 | ||
227 | #define BM_TIMROT_TIMCTRLn_IRQ 0x8000 | ||
228 | #define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & 0x8000) | ||
229 | #define BP_TIMROT_TIMCTRLn_IRQ_EN 14 | ||
230 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x4000 | ||
231 | #define BF_TIMROT_TIMCTRLn_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
232 | #define BP_TIMROT_TIMCTRLn_POLARITY 8 | ||
233 | #define BM_TIMROT_TIMCTRLn_POLARITY 0x100 | ||
234 | #define BF_TIMROT_TIMCTRLn_POLARITY(v) (((v) << 8) & 0x100) | ||
235 | #define BP_TIMROT_TIMCTRLn_UPDATE 7 | ||
236 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x80 | ||
237 | #define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & 0x80) | ||
238 | #define BP_TIMROT_TIMCTRLn_RELOAD 6 | ||
239 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x40 | ||
240 | #define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & 0x40) | ||
241 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 | ||
242 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x30 | ||
243 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 | ||
244 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 | ||
245 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 | ||
246 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 | ||
247 | #define BF_TIMROT_TIMCTRLn_PRESCALE(v) (((v) << 4) & 0x30) | ||
248 | #define BF_TIMROT_TIMCTRLn_PRESCALE_V(v) ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30) | ||
249 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
250 | #define BM_TIMROT_TIMCTRLn_SELECT 0xf | ||
251 | #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 | ||
252 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 | ||
253 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 | ||
254 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 | ||
255 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 | ||
256 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 | ||
257 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 | ||
258 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 | ||
259 | #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
260 | #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 | ||
261 | #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xa | ||
262 | #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xb | ||
263 | #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xc | ||
264 | #define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & 0xf) | ||
265 | #define BF_TIMROT_TIMCTRLn_SELECT_V(v) ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf) | ||
266 | |||
267 | #endif /* __HEADERGEN__STMP3600__TIMROT__H__ */ | ||