1 files changed, 214 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-spdif.h b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h
new file mode 100644
index 0000000000..168e88bdb0
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h
@@ -0,0 +1,214 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__SPDIF__H__
+#define __HEADERGEN__IMX233__SPDIF__H__
+#define REGS_SPDIF_BASE (0x80054000)
+#define REGS_SPDIF_VERSION "3.2.0"
+/**
+ * Register: HW_SPDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SPDIF_CTRL                       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0))
+#define HW_SPDIF_CTRL_SET                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4))
+#define HW_SPDIF_CTRL_CLR                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8))
+#define HW_SPDIF_CTRL_TOG                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc))
+#define BP_SPDIF_CTRL_SFTRST                31
+#define BM_SPDIF_CTRL_SFTRST                0x80000000
+#define BF_SPDIF_CTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
+#define BP_SPDIF_CTRL_CLKGATE               30
+#define BM_SPDIF_CTRL_CLKGATE               0x40000000
+#define BF_SPDIF_CTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
+#define BP_SPDIF_CTRL_RSRVD1                21
+#define BM_SPDIF_CTRL_RSRVD1                0x3fe00000
+#define BF_SPDIF_CTRL_RSRVD1(v)             (((v) << 21) & 0x3fe00000)
+#define BP_SPDIF_CTRL_DMAWAIT_COUNT         16
+#define BM_SPDIF_CTRL_DMAWAIT_COUNT         0x1f0000
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)      (((v) << 16) & 0x1f0000)
+#define BP_SPDIF_CTRL_RSRVD0                6
+#define BM_SPDIF_CTRL_RSRVD0                0xffc0
+#define BF_SPDIF_CTRL_RSRVD0(v)             (((v) << 6) & 0xffc0)
+#define BP_SPDIF_CTRL_WAIT_END_XFER         5
+#define BM_SPDIF_CTRL_WAIT_END_XFER         0x20
+#define BF_SPDIF_CTRL_WAIT_END_XFER(v)      (((v) << 5) & 0x20)
+#define BP_SPDIF_CTRL_WORD_LENGTH           4
+#define BM_SPDIF_CTRL_WORD_LENGTH           0x10
+#define BF_SPDIF_CTRL_WORD_LENGTH(v)        (((v) << 4) & 0x10)
+#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    3
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    0x8
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
+#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     2
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     0x4
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)  (((v) << 2) & 0x4)
+#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     1
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     0x2
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)  (((v) << 1) & 0x2)
+#define BP_SPDIF_CTRL_RUN                   0
+#define BM_SPDIF_CTRL_RUN                   0x1
+#define BF_SPDIF_CTRL_RUN(v)                (((v) << 0) & 0x1)
+/**
+ * Register: HW_SPDIF_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SPDIF_STAT               (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x0))
+#define HW_SPDIF_STAT_SET           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x4))
+#define HW_SPDIF_STAT_CLR           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x8))
+#define HW_SPDIF_STAT_TOG           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0xc))
+#define BP_SPDIF_STAT_PRESENT       31
+#define BM_SPDIF_STAT_PRESENT       0x80000000
+#define BF_SPDIF_STAT_PRESENT(v)    (((v) << 31) & 0x80000000)
+#define BP_SPDIF_STAT_RSRVD1        1
+#define BM_SPDIF_STAT_RSRVD1        0x7ffffffe
+#define BF_SPDIF_STAT_RSRVD1(v)     (((v) << 1) & 0x7ffffffe)
+#define BP_SPDIF_STAT_END_XFER      0
+#define BM_SPDIF_STAT_END_XFER      0x1
+#define BF_SPDIF_STAT_END_XFER(v)   (((v) << 0) & 0x1)
+/**
+ * Register: HW_SPDIF_FRAMECTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_SPDIF_FRAMECTRL              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0))
+#define HW_SPDIF_FRAMECTRL_SET          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4))
+#define HW_SPDIF_FRAMECTRL_CLR          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8))
+#define HW_SPDIF_FRAMECTRL_TOG          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc))
+#define BP_SPDIF_FRAMECTRL_RSRVD2       18
+#define BM_SPDIF_FRAMECTRL_RSRVD2       0xfffc0000
+#define BF_SPDIF_FRAMECTRL_RSRVD2(v)    (((v) << 18) & 0xfffc0000)
+#define BP_SPDIF_FRAMECTRL_V_CONFIG     17
+#define BM_SPDIF_FRAMECTRL_V_CONFIG     0x20000
+#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)  (((v) << 17) & 0x20000)
+#define BP_SPDIF_FRAMECTRL_AUTO_MUTE    16
+#define BM_SPDIF_FRAMECTRL_AUTO_MUTE    0x10000
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
+#define BP_SPDIF_FRAMECTRL_RSRVD1       15
+#define BM_SPDIF_FRAMECTRL_RSRVD1       0x8000
+#define BF_SPDIF_FRAMECTRL_RSRVD1(v)    (((v) << 15) & 0x8000)
+#define BP_SPDIF_FRAMECTRL_USER_DATA    14
+#define BM_SPDIF_FRAMECTRL_USER_DATA    0x4000
+#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
+#define BP_SPDIF_FRAMECTRL_V            13
+#define BM_SPDIF_FRAMECTRL_V            0x2000
+#define BF_SPDIF_FRAMECTRL_V(v)         (((v) << 13) & 0x2000)
+#define BP_SPDIF_FRAMECTRL_L            12
+#define BM_SPDIF_FRAMECTRL_L            0x1000
+#define BF_SPDIF_FRAMECTRL_L(v)         (((v) << 12) & 0x1000)
+#define BP_SPDIF_FRAMECTRL_RSRVD0       11
+#define BM_SPDIF_FRAMECTRL_RSRVD0       0x800
+#define BF_SPDIF_FRAMECTRL_RSRVD0(v)    (((v) << 11) & 0x800)
+#define BP_SPDIF_FRAMECTRL_CC           4
+#define BM_SPDIF_FRAMECTRL_CC           0x7f0
+#define BF_SPDIF_FRAMECTRL_CC(v)        (((v) << 4) & 0x7f0)
+#define BP_SPDIF_FRAMECTRL_PRE          3
+#define BM_SPDIF_FRAMECTRL_PRE          0x8
+#define BF_SPDIF_FRAMECTRL_PRE(v)       (((v) << 3) & 0x8)
+#define BP_SPDIF_FRAMECTRL_COPY         2
+#define BM_SPDIF_FRAMECTRL_COPY         0x4
+#define BF_SPDIF_FRAMECTRL_COPY(v)      (((v) << 2) & 0x4)
+#define BP_SPDIF_FRAMECTRL_AUDIO        1
+#define BM_SPDIF_FRAMECTRL_AUDIO        0x2
+#define BF_SPDIF_FRAMECTRL_AUDIO(v)     (((v) << 1) & 0x2)
+#define BP_SPDIF_FRAMECTRL_PRO          0
+#define BM_SPDIF_FRAMECTRL_PRO          0x1
+#define BF_SPDIF_FRAMECTRL_PRO(v)       (((v) << 0) & 0x1)
+/**
+ * Register: HW_SPDIF_SRR
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_SPDIF_SRR                (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0))
+#define HW_SPDIF_SRR_SET            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4))
+#define HW_SPDIF_SRR_CLR            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8))
+#define HW_SPDIF_SRR_TOG            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc))
+#define BP_SPDIF_SRR_RSRVD1         31
+#define BM_SPDIF_SRR_RSRVD1         0x80000000
+#define BF_SPDIF_SRR_RSRVD1(v)      (((v) << 31) & 0x80000000)
+#define BP_SPDIF_SRR_BASEMULT       28
+#define BM_SPDIF_SRR_BASEMULT       0x70000000
+#define BF_SPDIF_SRR_BASEMULT(v)    (((v) << 28) & 0x70000000)
+#define BP_SPDIF_SRR_RSRVD0         20
+#define BM_SPDIF_SRR_RSRVD0         0xff00000
+#define BF_SPDIF_SRR_RSRVD0(v)      (((v) << 20) & 0xff00000)
+#define BP_SPDIF_SRR_RATE           0
+#define BM_SPDIF_SRR_RATE           0xfffff
+#define BF_SPDIF_SRR_RATE(v)        (((v) << 0) & 0xfffff)
+/**
+ * Register: HW_SPDIF_DEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_SPDIF_DEBUG                  (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x0))
+#define HW_SPDIF_DEBUG_SET              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x4))
+#define HW_SPDIF_DEBUG_CLR              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x8))
+#define HW_SPDIF_DEBUG_TOG              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0xc))
+#define BP_SPDIF_DEBUG_RSRVD1           2
+#define BM_SPDIF_DEBUG_RSRVD1           0xfffffffc
+#define BF_SPDIF_DEBUG_RSRVD1(v)        (((v) << 2) & 0xfffffffc)
+#define BP_SPDIF_DEBUG_DMA_PREQ         1
+#define BM_SPDIF_DEBUG_DMA_PREQ         0x2
+#define BF_SPDIF_DEBUG_DMA_PREQ(v)      (((v) << 1) & 0x2)
+#define BP_SPDIF_DEBUG_FIFO_STATUS      0
+#define BM_SPDIF_DEBUG_FIFO_STATUS      0x1
+#define BF_SPDIF_DEBUG_FIFO_STATUS(v)   (((v) << 0) & 0x1)
+/**
+ * Register: HW_SPDIF_DATA
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_SPDIF_DATA           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0))
+#define HW_SPDIF_DATA_SET       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4))
+#define HW_SPDIF_DATA_CLR       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8))
+#define HW_SPDIF_DATA_TOG       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc))
+#define BP_SPDIF_DATA_HIGH      16
+#define BM_SPDIF_DATA_HIGH      0xffff0000
+#define BF_SPDIF_DATA_HIGH(v)   (((v) << 16) & 0xffff0000)
+#define BP_SPDIF_DATA_LOW       0
+#define BM_SPDIF_DATA_LOW       0xffff
+#define BF_SPDIF_DATA_LOW(v)    (((v) << 0) & 0xffff)
+/**
+ * Register: HW_SPDIF_VERSION
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_SPDIF_VERSION            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60))
+#define BP_SPDIF_VERSION_MAJOR      24
+#define BM_SPDIF_VERSION_MAJOR      0xff000000
+#define BF_SPDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_SPDIF_VERSION_MINOR      16
+#define BM_SPDIF_VERSION_MINOR      0xff0000
+#define BF_SPDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_SPDIF_VERSION_STEP       0
+#define BM_SPDIF_VERSION_STEP       0xffff
+#define BF_SPDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+#endif /* __HEADERGEN__IMX233__SPDIF__H__ */

diff --git a/firmware/target/arm/imx233/regs/imx233/regs-spdif.h b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h new file mode 100644 index 0000000000..168e88bdb0 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h
@@ -0,0 +1,214 @@
	1	/***************************************************************************
	2	* __________ __ ___.
	3	* Open \______ \ ____ ____ \| \| _\_ \|__ _______ ___
	4	* Source \| _// _ \_/ ___\\| \|/ /\| __ \ / _ \ \/ /
	5	* Jukebox \| \| ( <_> ) \___\| < \| \_\ ( <_> > < <
	6	* Firmware \|____\|_ /\____/ \___ >__\|_ \\|___ /\____/__/\_ \
	7	* \/ \/ \/ \/ \/
	8	* This file was automatically generated by headergen, DO NOT EDIT it.
	9	* headergen version: 2.1.7
	10	* XML versions: imx233:3.2.0
	11	*
	12	* Copyright (C) 2013 by Amaury Pouly
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License
	16	* as published by the Free Software Foundation; either version 2
	17	* of the License, or (at your option) any later version.
	18	*
	19	* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
	20	* KIND, either express or implied.
	21	*
	22	****************************************************************************/
	23	#ifndef __HEADERGEN__IMX233__SPDIF__H__
	24	#define __HEADERGEN__IMX233__SPDIF__H__
	25
	26	#define REGS_SPDIF_BASE (0x80054000)
	27
	28	#define REGS_SPDIF_VERSION "3.2.0"
	29
	30	/**
	31	* Register: HW_SPDIF_CTRL
	32	* Address: 0
	33	* SCT: yes
	34	*/
	35	#define HW_SPDIF_CTRL ((volatile unsigned long )(REGS_SPDIF_BASE + 0x0 + 0x0))
	36	#define HW_SPDIF_CTRL_SET ((volatile unsigned long )(REGS_SPDIF_BASE + 0x0 + 0x4))
	37	#define HW_SPDIF_CTRL_CLR ((volatile unsigned long )(REGS_SPDIF_BASE + 0x0 + 0x8))
	38	#define HW_SPDIF_CTRL_TOG ((volatile unsigned long )(REGS_SPDIF_BASE + 0x0 + 0xc))
	39	#define BP_SPDIF_CTRL_SFTRST 31
	40	#define BM_SPDIF_CTRL_SFTRST 0x80000000
	41	#define BF_SPDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
	42	#define BP_SPDIF_CTRL_CLKGATE 30
	43	#define BM_SPDIF_CTRL_CLKGATE 0x40000000
	44	#define BF_SPDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
	45	#define BP_SPDIF_CTRL_RSRVD1 21
	46	#define BM_SPDIF_CTRL_RSRVD1 0x3fe00000
	47	#define BF_SPDIF_CTRL_RSRVD1(v) (((v) << 21) & 0x3fe00000)
	48	#define BP_SPDIF_CTRL_DMAWAIT_COUNT 16
	49	#define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x1f0000
	50	#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000)
	51	#define BP_SPDIF_CTRL_RSRVD0 6
	52	#define BM_SPDIF_CTRL_RSRVD0 0xffc0
	53	#define BF_SPDIF_CTRL_RSRVD0(v) (((v) << 6) & 0xffc0)
	54	#define BP_SPDIF_CTRL_WAIT_END_XFER 5
	55	#define BM_SPDIF_CTRL_WAIT_END_XFER 0x20
	56	#define BF_SPDIF_CTRL_WAIT_END_XFER(v) (((v) << 5) & 0x20)
	57	#define BP_SPDIF_CTRL_WORD_LENGTH 4
	58	#define BM_SPDIF_CTRL_WORD_LENGTH 0x10
	59	#define BF_SPDIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0x10)
	60	#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 3
	61	#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x8
	62	#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
	63	#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 2
	64	#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x4
	65	#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4)
	66	#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 1
	67	#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x2
	68	#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2)
	69	#define BP_SPDIF_CTRL_RUN 0
	70	#define BM_SPDIF_CTRL_RUN 0x1
	71	#define BF_SPDIF_CTRL_RUN(v) (((v) << 0) & 0x1)
	72
	73	/**
	74	* Register: HW_SPDIF_STAT
	75	* Address: 0x10
	76	* SCT: yes
	77	*/
	78	#define HW_SPDIF_STAT ((volatile unsigned long )(REGS_SPDIF_BASE + 0x10 + 0x0))
	79	#define HW_SPDIF_STAT_SET ((volatile unsigned long )(REGS_SPDIF_BASE + 0x10 + 0x4))
	80	#define HW_SPDIF_STAT_CLR ((volatile unsigned long )(REGS_SPDIF_BASE + 0x10 + 0x8))
	81	#define HW_SPDIF_STAT_TOG ((volatile unsigned long )(REGS_SPDIF_BASE + 0x10 + 0xc))
	82	#define BP_SPDIF_STAT_PRESENT 31
	83	#define BM_SPDIF_STAT_PRESENT 0x80000000
	84	#define BF_SPDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000)
	85	#define BP_SPDIF_STAT_RSRVD1 1
	86	#define BM_SPDIF_STAT_RSRVD1 0x7ffffffe
	87	#define BF_SPDIF_STAT_RSRVD1(v) (((v) << 1) & 0x7ffffffe)
	88	#define BP_SPDIF_STAT_END_XFER 0
	89	#define BM_SPDIF_STAT_END_XFER 0x1
	90	#define BF_SPDIF_STAT_END_XFER(v) (((v) << 0) & 0x1)
	91
	92	/**
	93	* Register: HW_SPDIF_FRAMECTRL
	94	* Address: 0x20
	95	* SCT: yes
	96	*/
	97	#define HW_SPDIF_FRAMECTRL ((volatile unsigned long )(REGS_SPDIF_BASE + 0x20 + 0x0))
	98	#define HW_SPDIF_FRAMECTRL_SET ((volatile unsigned long )(REGS_SPDIF_BASE + 0x20 + 0x4))
	99	#define HW_SPDIF_FRAMECTRL_CLR ((volatile unsigned long )(REGS_SPDIF_BASE + 0x20 + 0x8))
	100	#define HW_SPDIF_FRAMECTRL_TOG ((volatile unsigned long )(REGS_SPDIF_BASE + 0x20 + 0xc))
	101	#define BP_SPDIF_FRAMECTRL_RSRVD2 18
	102	#define BM_SPDIF_FRAMECTRL_RSRVD2 0xfffc0000
	103	#define BF_SPDIF_FRAMECTRL_RSRVD2(v) (((v) << 18) & 0xfffc0000)
	104	#define BP_SPDIF_FRAMECTRL_V_CONFIG 17
	105	#define BM_SPDIF_FRAMECTRL_V_CONFIG 0x20000
	106	#define BF_SPDIF_FRAMECTRL_V_CONFIG(v) (((v) << 17) & 0x20000)
	107	#define BP_SPDIF_FRAMECTRL_AUTO_MUTE 16
	108	#define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x10000
	109	#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
	110	#define BP_SPDIF_FRAMECTRL_RSRVD1 15
	111	#define BM_SPDIF_FRAMECTRL_RSRVD1 0x8000
	112	#define BF_SPDIF_FRAMECTRL_RSRVD1(v) (((v) << 15) & 0x8000)
	113	#define BP_SPDIF_FRAMECTRL_USER_DATA 14
	114	#define BM_SPDIF_FRAMECTRL_USER_DATA 0x4000
	115	#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
	116	#define BP_SPDIF_FRAMECTRL_V 13
	117	#define BM_SPDIF_FRAMECTRL_V 0x2000
	118	#define BF_SPDIF_FRAMECTRL_V(v) (((v) << 13) & 0x2000)
	119	#define BP_SPDIF_FRAMECTRL_L 12
	120	#define BM_SPDIF_FRAMECTRL_L 0x1000
	121	#define BF_SPDIF_FRAMECTRL_L(v) (((v) << 12) & 0x1000)
	122	#define BP_SPDIF_FRAMECTRL_RSRVD0 11
	123	#define BM_SPDIF_FRAMECTRL_RSRVD0 0x800
	124	#define BF_SPDIF_FRAMECTRL_RSRVD0(v) (((v) << 11) & 0x800)
	125	#define BP_SPDIF_FRAMECTRL_CC 4
	126	#define BM_SPDIF_FRAMECTRL_CC 0x7f0
	127	#define BF_SPDIF_FRAMECTRL_CC(v) (((v) << 4) & 0x7f0)
	128	#define BP_SPDIF_FRAMECTRL_PRE 3
	129	#define BM_SPDIF_FRAMECTRL_PRE 0x8
	130	#define BF_SPDIF_FRAMECTRL_PRE(v) (((v) << 3) & 0x8)
	131	#define BP_SPDIF_FRAMECTRL_COPY 2
	132	#define BM_SPDIF_FRAMECTRL_COPY 0x4
	133	#define BF_SPDIF_FRAMECTRL_COPY(v) (((v) << 2) & 0x4)
	134	#define BP_SPDIF_FRAMECTRL_AUDIO 1
	135	#define BM_SPDIF_FRAMECTRL_AUDIO 0x2
	136	#define BF_SPDIF_FRAMECTRL_AUDIO(v) (((v) << 1) & 0x2)
	137	#define BP_SPDIF_FRAMECTRL_PRO 0
	138	#define BM_SPDIF_FRAMECTRL_PRO 0x1
	139	#define BF_SPDIF_FRAMECTRL_PRO(v) (((v) << 0) & 0x1)
	140
	141	/**
	142	* Register: HW_SPDIF_SRR
	143	* Address: 0x30
	144	* SCT: yes
	145	*/
	146	#define HW_SPDIF_SRR ((volatile unsigned long )(REGS_SPDIF_BASE + 0x30 + 0x0))
	147	#define HW_SPDIF_SRR_SET ((volatile unsigned long )(REGS_SPDIF_BASE + 0x30 + 0x4))
	148	#define HW_SPDIF_SRR_CLR ((volatile unsigned long )(REGS_SPDIF_BASE + 0x30 + 0x8))
	149	#define HW_SPDIF_SRR_TOG ((volatile unsigned long )(REGS_SPDIF_BASE + 0x30 + 0xc))
	150	#define BP_SPDIF_SRR_RSRVD1 31
	151	#define BM_SPDIF_SRR_RSRVD1 0x80000000
	152	#define BF_SPDIF_SRR_RSRVD1(v) (((v) << 31) & 0x80000000)
	153	#define BP_SPDIF_SRR_BASEMULT 28
	154	#define BM_SPDIF_SRR_BASEMULT 0x70000000
	155	#define BF_SPDIF_SRR_BASEMULT(v) (((v) << 28) & 0x70000000)
	156	#define BP_SPDIF_SRR_RSRVD0 20
	157	#define BM_SPDIF_SRR_RSRVD0 0xff00000
	158	#define BF_SPDIF_SRR_RSRVD0(v) (((v) << 20) & 0xff00000)
	159	#define BP_SPDIF_SRR_RATE 0
	160	#define BM_SPDIF_SRR_RATE 0xfffff
	161	#define BF_SPDIF_SRR_RATE(v) (((v) << 0) & 0xfffff)
	162
	163	/**
	164	* Register: HW_SPDIF_DEBUG
	165	* Address: 0x40
	166	* SCT: yes
	167	*/
	168	#define HW_SPDIF_DEBUG ((volatile unsigned long )(REGS_SPDIF_BASE + 0x40 + 0x0))
	169	#define HW_SPDIF_DEBUG_SET ((volatile unsigned long )(REGS_SPDIF_BASE + 0x40 + 0x4))
	170	#define HW_SPDIF_DEBUG_CLR ((volatile unsigned long )(REGS_SPDIF_BASE + 0x40 + 0x8))
	171	#define HW_SPDIF_DEBUG_TOG ((volatile unsigned long )(REGS_SPDIF_BASE + 0x40 + 0xc))
	172	#define BP_SPDIF_DEBUG_RSRVD1 2
	173	#define BM_SPDIF_DEBUG_RSRVD1 0xfffffffc
	174	#define BF_SPDIF_DEBUG_RSRVD1(v) (((v) << 2) & 0xfffffffc)
	175	#define BP_SPDIF_DEBUG_DMA_PREQ 1
	176	#define BM_SPDIF_DEBUG_DMA_PREQ 0x2
	177	#define BF_SPDIF_DEBUG_DMA_PREQ(v) (((v) << 1) & 0x2)
	178	#define BP_SPDIF_DEBUG_FIFO_STATUS 0
	179	#define BM_SPDIF_DEBUG_FIFO_STATUS 0x1
	180	#define BF_SPDIF_DEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1)
	181
	182	/**
	183	* Register: HW_SPDIF_DATA
	184	* Address: 0x50
	185	* SCT: yes
	186	*/
	187	#define HW_SPDIF_DATA ((volatile unsigned long )(REGS_SPDIF_BASE + 0x50 + 0x0))
	188	#define HW_SPDIF_DATA_SET ((volatile unsigned long )(REGS_SPDIF_BASE + 0x50 + 0x4))
	189	#define HW_SPDIF_DATA_CLR ((volatile unsigned long )(REGS_SPDIF_BASE + 0x50 + 0x8))
	190	#define HW_SPDIF_DATA_TOG ((volatile unsigned long )(REGS_SPDIF_BASE + 0x50 + 0xc))
	191	#define BP_SPDIF_DATA_HIGH 16
	192	#define BM_SPDIF_DATA_HIGH 0xffff0000
	193	#define BF_SPDIF_DATA_HIGH(v) (((v) << 16) & 0xffff0000)
	194	#define BP_SPDIF_DATA_LOW 0
	195	#define BM_SPDIF_DATA_LOW 0xffff
	196	#define BF_SPDIF_DATA_LOW(v) (((v) << 0) & 0xffff)
	197
	198	/**
	199	* Register: HW_SPDIF_VERSION
	200	* Address: 0x60
	201	* SCT: no
	202	*/
	203	#define HW_SPDIF_VERSION ((volatile unsigned long )(REGS_SPDIF_BASE + 0x60))
	204	#define BP_SPDIF_VERSION_MAJOR 24
	205	#define BM_SPDIF_VERSION_MAJOR 0xff000000
	206	#define BF_SPDIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
	207	#define BP_SPDIF_VERSION_MINOR 16
	208	#define BM_SPDIF_VERSION_MINOR 0xff0000
	209	#define BF_SPDIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
	210	#define BP_SPDIF_VERSION_STEP 0
	211	#define BM_SPDIF_VERSION_STEP 0xffff
	212	#define BF_SPDIF_VERSION_STEP(v) (((v) << 0) & 0xffff)
	213
	214	#endif /* __HEADERGEN__IMX233__SPDIF__H__ */