imx233: generate register headers for stmp3600, stmp3700 and imx233

Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934

138 files changed, 41995 insertions, 0 deletions

diff --git a/firmware/target/arm/imx233/regs/imx233/regs-apbh.h b/firmware/target/arm/imx233/regs/imx233/regs-apbh.h
new file mode 100644
index 0000000000..bef0b82d78
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-apbh.h
@@ -0,0 +1,355 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__APBH__H__
+#define __HEADERGEN__IMX233__APBH__H__
+
+#define REGS_APBH_BASE (0x80004000)
+
+#define REGS_APBH_VERSION "3.2.0"
+
+/**
+ * Register: HW_APBH_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_APBH_CTRL0                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0))
+#define HW_APBH_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4))
+#define HW_APBH_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8))
+#define HW_APBH_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc))
+#define BP_APBH_CTRL0_SFTRST                    31
+#define BM_APBH_CTRL0_SFTRST                    0x80000000
+#define BF_APBH_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
+#define BP_APBH_CTRL0_CLKGATE                   30
+#define BM_APBH_CTRL0_CLKGATE                   0x40000000
+#define BF_APBH_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
+#define BP_APBH_CTRL0_AHB_BURST8_EN             29
+#define BM_APBH_CTRL0_AHB_BURST8_EN             0x20000000
+#define BF_APBH_CTRL0_AHB_BURST8_EN(v)          (((v) << 29) & 0x20000000)
+#define BP_APBH_CTRL0_APB_BURST4_EN             28
+#define BM_APBH_CTRL0_APB_BURST4_EN             0x10000000
+#define BF_APBH_CTRL0_APB_BURST4_EN(v)          (((v) << 28) & 0x10000000)
+#define BP_APBH_CTRL0_RSVD0                     24
+#define BM_APBH_CTRL0_RSVD0                     0xf000000
+#define BF_APBH_CTRL0_RSVD0(v)                  (((v) << 24) & 0xf000000)
+#define BP_APBH_CTRL0_RESET_CHANNEL             16
+#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1       0x2
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2       0x4
+#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x40
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x80
+#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
+#define BF_APBH_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1     0x2
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2     0x4
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x40
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x80
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) << 8) & 0xff00)
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v)      ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00)
+#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1      0x2
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2      0x4
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x40
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x80
+#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
+#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_APBH_CTRL1                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0))
+#define HW_APBH_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4))
+#define HW_APBH_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8))
+#define HW_APBH_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc))
+#define BP_APBH_CTRL1_RSVD1                 24
+#define BM_APBH_CTRL1_RSVD1                 0xff000000
+#define BF_APBH_CTRL1_RSVD1(v)              (((v) << 24) & 0xff000000)
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    16
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff0000
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000)
+#define BP_APBH_CTRL1_RSVD0                 8
+#define BM_APBH_CTRL1_RSVD0                 0xff00
+#define BF_APBH_CTRL1_RSVD0(v)              (((v) << 8) & 0xff00)
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ       0
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ       0xff
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_APBH_CTRL2                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x0))
+#define HW_APBH_CTRL2_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x4))
+#define HW_APBH_CTRL2_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0x8))
+#define HW_APBH_CTRL2_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20 + 0xc))
+#define BP_APBH_CTRL2_RSVD1                 24
+#define BM_APBH_CTRL2_RSVD1                 0xff000000
+#define BF_APBH_CTRL2_RSVD1(v)              (((v) << 24) & 0xff000000)
+#define BP_APBH_CTRL2_CH_ERROR_STATUS       16
+#define BM_APBH_CTRL2_CH_ERROR_STATUS       0xff0000
+#define BF_APBH_CTRL2_CH_ERROR_STATUS(v)    (((v) << 16) & 0xff0000)
+#define BP_APBH_CTRL2_RSVD0                 8
+#define BM_APBH_CTRL2_RSVD0                 0xff00
+#define BF_APBH_CTRL2_RSVD0(v)              (((v) << 8) & 0xff00)
+#define BP_APBH_CTRL2_CH_ERROR_IRQ          0
+#define BM_APBH_CTRL2_CH_ERROR_IRQ          0xff
+#define BF_APBH_CTRL2_CH_ERROR_IRQ(v)       (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_DEVSEL
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_APBH_DEVSEL          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30))
+#define BP_APBH_DEVSEL_CH7      28
+#define BM_APBH_DEVSEL_CH7      0xf0000000
+#define BF_APBH_DEVSEL_CH7(v)   (((v) << 28) & 0xf0000000)
+#define BP_APBH_DEVSEL_CH6      24
+#define BM_APBH_DEVSEL_CH6      0xf000000
+#define BF_APBH_DEVSEL_CH6(v)   (((v) << 24) & 0xf000000)
+#define BP_APBH_DEVSEL_CH5      20
+#define BM_APBH_DEVSEL_CH5      0xf00000
+#define BF_APBH_DEVSEL_CH5(v)   (((v) << 20) & 0xf00000)
+#define BP_APBH_DEVSEL_CH4      16
+#define BM_APBH_DEVSEL_CH4      0xf0000
+#define BF_APBH_DEVSEL_CH4(v)   (((v) << 16) & 0xf0000)
+#define BP_APBH_DEVSEL_CH3      12
+#define BM_APBH_DEVSEL_CH3      0xf000
+#define BF_APBH_DEVSEL_CH3(v)   (((v) << 12) & 0xf000)
+#define BP_APBH_DEVSEL_CH2      8
+#define BM_APBH_DEVSEL_CH2      0xf00
+#define BF_APBH_DEVSEL_CH2(v)   (((v) << 8) & 0xf00)
+#define BP_APBH_DEVSEL_CH1      4
+#define BM_APBH_DEVSEL_CH1      0xf0
+#define BF_APBH_DEVSEL_CH1(v)   (((v) << 4) & 0xf0)
+#define BP_APBH_DEVSEL_CH0      0
+#define BM_APBH_DEVSEL_CH0      0xf
+#define BF_APBH_DEVSEL_CH0(v)   (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_APBH_CHn_CURCMDAR
+ * Address: 0x40+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70))
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_NXTCMDAR
+ * Address: 0x50+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70))
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_CMD
+ * Address: 0x60+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70))
+#define BP_APBH_CHn_CMD_XFER_COUNT              16
+#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
+#define BP_APBH_CHn_CMD_CMDWORDS                12
+#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
+#define BP_APBH_CHn_CMD_RSVD1                   9
+#define BM_APBH_CHn_CMD_RSVD1                   0xe00
+#define BF_APBH_CHn_CMD_RSVD1(v)                (((v) << 9) & 0xe00)
+#define BP_APBH_CHn_CMD_HALTONTERMINATE         8
+#define BM_APBH_CHn_CMD_HALTONTERMINATE         0x100
+#define BF_APBH_CHn_CMD_HALTONTERMINATE(v)      (((v) << 8) & 0x100)
+#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
+#define BP_APBH_CHn_CMD_SEMAPHORE               6
+#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
+#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
+#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
+#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) << 5) & 0x20)
+#define BP_APBH_CHn_CMD_NANDLOCK                4
+#define BM_APBH_CHn_CMD_NANDLOCK                0x10
+#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) << 4) & 0x10)
+#define BP_APBH_CHn_CMD_IRQONCMPLT              3
+#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
+#define BP_APBH_CHn_CMD_CHAIN                   2
+#define BM_APBH_CHn_CMD_CHAIN                   0x4
+#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
+#define BP_APBH_CHn_CMD_COMMAND                 0
+#define BM_APBH_CHn_CMD_COMMAND                 0x3
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
+#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
+#define BF_APBH_CHn_CMD_COMMAND_V(v)            ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3)
+
+/**
+ * Register: HW_APBH_CHn_BAR
+ * Address: 0x70+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70))
+#define BP_APBH_CHn_BAR_ADDRESS     0
+#define BM_APBH_CHn_BAR_ADDRESS     0xffffffff
+#define BF_APBH_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_SEMA
+ * Address: 0x80+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70))
+#define BP_APBH_CHn_SEMA_RSVD2              24
+#define BM_APBH_CHn_SEMA_RSVD2              0xff000000
+#define BF_APBH_CHn_SEMA_RSVD2(v)           (((v) << 24) & 0xff000000)
+#define BP_APBH_CHn_SEMA_PHORE              16
+#define BM_APBH_CHn_SEMA_PHORE              0xff0000
+#define BF_APBH_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
+#define BP_APBH_CHn_SEMA_RSVD1              8
+#define BM_APBH_CHn_SEMA_RSVD1              0xff00
+#define BF_APBH_CHn_SEMA_RSVD1(v)           (((v) << 8) & 0xff00)
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA     0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA     0xff
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_CHn_DEBUG1
+ * Address: 0x90+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_DEBUG1(n)                               (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70))
+#define BP_APBH_CHn_DEBUG1_REQ                              31
+#define BM_APBH_CHn_DEBUG1_REQ                              0x80000000
+#define BF_APBH_CHn_DEBUG1_REQ(v)                           (((v) << 31) & 0x80000000)
+#define BP_APBH_CHn_DEBUG1_BURST                            30
+#define BM_APBH_CHn_DEBUG1_BURST                            0x40000000
+#define BF_APBH_CHn_DEBUG1_BURST(v)                         (((v) << 30) & 0x40000000)
+#define BP_APBH_CHn_DEBUG1_KICK                             29
+#define BM_APBH_CHn_DEBUG1_KICK                             0x20000000
+#define BF_APBH_CHn_DEBUG1_KICK(v)                          (((v) << 29) & 0x20000000)
+#define BP_APBH_CHn_DEBUG1_END                              28
+#define BM_APBH_CHn_DEBUG1_END                              0x10000000
+#define BF_APBH_CHn_DEBUG1_END(v)                           (((v) << 28) & 0x10000000)
+#define BP_APBH_CHn_DEBUG1_SENSE                            27
+#define BM_APBH_CHn_DEBUG1_SENSE                            0x8000000
+#define BF_APBH_CHn_DEBUG1_SENSE(v)                         (((v) << 27) & 0x8000000)
+#define BP_APBH_CHn_DEBUG1_READY                            26
+#define BM_APBH_CHn_DEBUG1_READY                            0x4000000
+#define BF_APBH_CHn_DEBUG1_READY(v)                         (((v) << 26) & 0x4000000)
+#define BP_APBH_CHn_DEBUG1_LOCK                             25
+#define BM_APBH_CHn_DEBUG1_LOCK                             0x2000000
+#define BF_APBH_CHn_DEBUG1_LOCK(v)                          (((v) << 25) & 0x2000000)
+#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID                 24
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID                 0x1000000
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)              (((v) << 24) & 0x1000000)
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                    23
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                    0x800000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)                 (((v) << 23) & 0x800000)
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                     22
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                     0x400000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)                  (((v) << 22) & 0x400000)
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                    21
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                    0x200000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)                 (((v) << 21) & 0x200000)
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                     20
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                     0x100000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)                  (((v) << 20) & 0x100000)
+#define BP_APBH_CHn_DEBUG1_RSVD1                            5
+#define BM_APBH_CHn_DEBUG1_RSVD1                            0xfffe0
+#define BF_APBH_CHn_DEBUG1_RSVD1(v)                         (((v) << 5) & 0xfffe0)
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE                     0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE                     0x1f
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE               0x0
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1           0x1
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3           0x2
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2           0x3
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE        0x4
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT           0x5
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4           0x6
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ            0x7
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH         0x8
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT          0x9
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE              0xc
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ           0xd
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN        0xe
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE      0xf
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE          0x14
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END           0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT         0x1c
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM    0x1d
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT         0x1e
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)                  (((v) << 0) & 0x1f)
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v)                ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
+
+/**
+ * Register: HW_APBH_CHn_DEBUG2
+ * Address: 0xa0+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBH_BASE + 0xa0+(n)*0x70))
+#define BP_APBH_CHn_DEBUG2_APB_BYTES    16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES    0xffff0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES    0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES    0xffff
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBH_VERSION
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_APBH_VERSION             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x3f0))
+#define BP_APBH_VERSION_MAJOR       24
+#define BM_APBH_VERSION_MAJOR       0xff000000
+#define BF_APBH_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_APBH_VERSION_MINOR       16
+#define BM_APBH_VERSION_MINOR       0xff0000
+#define BF_APBH_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_APBH_VERSION_STEP        0
+#define BM_APBH_VERSION_STEP        0xffff
+#define BF_APBH_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-apbx.h b/firmware/target/arm/imx233/regs/imx233/regs-apbx.h
new file mode 100644
index 0000000000..990ae26d24
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-apbx.h
@@ -0,0 +1,366 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.1
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__APBX__H__
+#define __HEADERGEN__IMX233__APBX__H__
+
+#define REGS_APBX_BASE (0x80024000)
+
+#define REGS_APBX_VERSION "3.2.1"
+
+/**
+ * Register: HW_APBX_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_APBX_CTRL0               (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0))
+#define HW_APBX_CTRL0_SET           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4))
+#define HW_APBX_CTRL0_CLR           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8))
+#define HW_APBX_CTRL0_TOG           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc))
+#define BP_APBX_CTRL0_SFTRST        31
+#define BM_APBX_CTRL0_SFTRST        0x80000000
+#define BF_APBX_CTRL0_SFTRST(v)     (((v) << 31) & 0x80000000)
+#define BP_APBX_CTRL0_CLKGATE       30
+#define BM_APBX_CTRL0_CLKGATE       0x40000000
+#define BF_APBX_CTRL0_CLKGATE(v)    (((v) << 30) & 0x40000000)
+#define BP_APBX_CTRL0_RSVD0         0
+#define BM_APBX_CTRL0_RSVD0         0x3fffffff
+#define BF_APBX_CTRL0_RSVD0(v)      (((v) << 0) & 0x3fffffff)
+
+/**
+ * Register: HW_APBX_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_APBX_CTRL1                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0))
+#define HW_APBX_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4))
+#define HW_APBX_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8))
+#define HW_APBX_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc))
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    16
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    0xffff0000
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xffff0000)
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ       0
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ       0xffff
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBX_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_APBX_CTRL2                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x0))
+#define HW_APBX_CTRL2_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x4))
+#define HW_APBX_CTRL2_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0x8))
+#define HW_APBX_CTRL2_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20 + 0xc))
+#define BP_APBX_CTRL2_CH_ERROR_STATUS       16
+#define BM_APBX_CTRL2_CH_ERROR_STATUS       0xffff0000
+#define BF_APBX_CTRL2_CH_ERROR_STATUS(v)    (((v) << 16) & 0xffff0000)
+#define BP_APBX_CTRL2_CH_ERROR_IRQ          0
+#define BM_APBX_CTRL2_CH_ERROR_IRQ          0xffff
+#define BF_APBX_CTRL2_CH_ERROR_IRQ(v)       (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBX_CHANNEL_CTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_APBX_CHANNEL_CTRL                            (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x0))
+#define HW_APBX_CHANNEL_CTRL_SET                        (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x4))
+#define HW_APBX_CHANNEL_CTRL_CLR                        (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0x8))
+#define HW_APBX_CHANNEL_CTRL_TOG                        (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30 + 0xc))
+#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL              16
+#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL              0xffff0000
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOIN     0x1
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOOUT    0x2
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX    0x4
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C         0x8
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1       0x10
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__DRI         0x20
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_RX     0x40
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX    0x40
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_TX     0x80
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX    0x80
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX    0x100
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX    0x200
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF2       0x400
+#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v)           (((v) << 16) & 0xffff0000)
+#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL_V(v)         ((BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__##v << 16) & 0xffff0000)
+#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL             0
+#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL             0xffff
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOIN    0x1
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOOUT   0x2
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX   0x4
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C        0x8
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1      0x10
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__DRI        0x20
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_RX    0x40
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX   0x40
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_TX    0x80
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX   0x80
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX   0x100
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX   0x200
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF2      0x400
+#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v)          (((v) << 0) & 0xffff)
+#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL_V(v)        ((BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__##v << 0) & 0xffff)
+
+/**
+ * Register: HW_APBX_DEVSEL
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_APBX_DEVSEL                  (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40))
+#define BP_APBX_DEVSEL_CH15             30
+#define BM_APBX_DEVSEL_CH15             0xc0000000
+#define BF_APBX_DEVSEL_CH15(v)          (((v) << 30) & 0xc0000000)
+#define BP_APBX_DEVSEL_CH14             28
+#define BM_APBX_DEVSEL_CH14             0x30000000
+#define BF_APBX_DEVSEL_CH14(v)          (((v) << 28) & 0x30000000)
+#define BP_APBX_DEVSEL_CH13             26
+#define BM_APBX_DEVSEL_CH13             0xc000000
+#define BF_APBX_DEVSEL_CH13(v)          (((v) << 26) & 0xc000000)
+#define BP_APBX_DEVSEL_CH12             24
+#define BM_APBX_DEVSEL_CH12             0x3000000
+#define BF_APBX_DEVSEL_CH12(v)          (((v) << 24) & 0x3000000)
+#define BP_APBX_DEVSEL_CH11             22
+#define BM_APBX_DEVSEL_CH11             0xc00000
+#define BF_APBX_DEVSEL_CH11(v)          (((v) << 22) & 0xc00000)
+#define BP_APBX_DEVSEL_CH10             20
+#define BM_APBX_DEVSEL_CH10             0x300000
+#define BF_APBX_DEVSEL_CH10(v)          (((v) << 20) & 0x300000)
+#define BP_APBX_DEVSEL_CH9              18
+#define BM_APBX_DEVSEL_CH9              0xc0000
+#define BF_APBX_DEVSEL_CH9(v)           (((v) << 18) & 0xc0000)
+#define BP_APBX_DEVSEL_CH8              16
+#define BM_APBX_DEVSEL_CH8              0x30000
+#define BF_APBX_DEVSEL_CH8(v)           (((v) << 16) & 0x30000)
+#define BP_APBX_DEVSEL_CH7              14
+#define BM_APBX_DEVSEL_CH7              0xc000
+#define BV_APBX_DEVSEL_CH7__USE_I2C1    0x0
+#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH7(v)           (((v) << 14) & 0xc000)
+#define BF_APBX_DEVSEL_CH7_V(v)         ((BV_APBX_DEVSEL_CH7__##v << 14) & 0xc000)
+#define BP_APBX_DEVSEL_CH6              12
+#define BM_APBX_DEVSEL_CH6              0x3000
+#define BV_APBX_DEVSEL_CH6__USE_SAIF1   0x0
+#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH6(v)           (((v) << 12) & 0x3000)
+#define BF_APBX_DEVSEL_CH6_V(v)         ((BV_APBX_DEVSEL_CH6__##v << 12) & 0x3000)
+#define BP_APBX_DEVSEL_CH5              10
+#define BM_APBX_DEVSEL_CH5              0xc00
+#define BF_APBX_DEVSEL_CH5(v)           (((v) << 10) & 0xc00)
+#define BP_APBX_DEVSEL_CH4              8
+#define BM_APBX_DEVSEL_CH4              0x300
+#define BF_APBX_DEVSEL_CH4(v)           (((v) << 8) & 0x300)
+#define BP_APBX_DEVSEL_CH3              6
+#define BM_APBX_DEVSEL_CH3              0xc0
+#define BF_APBX_DEVSEL_CH3(v)           (((v) << 6) & 0xc0)
+#define BP_APBX_DEVSEL_CH2              4
+#define BM_APBX_DEVSEL_CH2              0x30
+#define BF_APBX_DEVSEL_CH2(v)           (((v) << 4) & 0x30)
+#define BP_APBX_DEVSEL_CH1              2
+#define BM_APBX_DEVSEL_CH1              0xc
+#define BF_APBX_DEVSEL_CH1(v)           (((v) << 2) & 0xc)
+#define BP_APBX_DEVSEL_CH0              0
+#define BM_APBX_DEVSEL_CH0              0x3
+#define BF_APBX_DEVSEL_CH0(v)           (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_APBX_CHn_CURCMDAR
+ * Address: 0x100+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x100+(n)*0x70))
+#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_NXTCMDAR
+ * Address: 0x110+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x110+(n)*0x70))
+#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_CMD
+ * Address: 0x120+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBX_BASE + 0x120+(n)*0x70))
+#define BP_APBX_CHn_CMD_XFER_COUNT              16
+#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
+#define BP_APBX_CHn_CMD_CMDWORDS                12
+#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
+#define BP_APBX_CHn_CMD_RSVD1                   9
+#define BM_APBX_CHn_CMD_RSVD1                   0xe00
+#define BF_APBX_CHn_CMD_RSVD1(v)                (((v) << 9) & 0xe00)
+#define BP_APBX_CHn_CMD_HALTONTERMINATE         8
+#define BM_APBX_CHn_CMD_HALTONTERMINATE         0x100
+#define BF_APBX_CHn_CMD_HALTONTERMINATE(v)      (((v) << 8) & 0x100)
+#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
+#define BP_APBX_CHn_CMD_SEMAPHORE               6
+#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
+#define BP_APBX_CHn_CMD_RSVD0                   4
+#define BM_APBX_CHn_CMD_RSVD0                   0x30
+#define BF_APBX_CHn_CMD_RSVD0(v)                (((v) << 4) & 0x30)
+#define BP_APBX_CHn_CMD_IRQONCMPLT              3
+#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
+#define BP_APBX_CHn_CMD_CHAIN                   2
+#define BM_APBX_CHn_CMD_CHAIN                   0x4
+#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
+#define BP_APBX_CHn_CMD_COMMAND                 0
+#define BM_APBX_CHn_CMD_COMMAND                 0x3
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
+#define BF_APBX_CHn_CMD_COMMAND_V(v)            ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3)
+
+/**
+ * Register: HW_APBX_CHn_BAR
+ * Address: 0x130+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBX_BASE + 0x130+(n)*0x70))
+#define BP_APBX_CHn_BAR_ADDRESS     0
+#define BM_APBX_CHn_BAR_ADDRESS     0xffffffff
+#define BF_APBX_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_SEMA
+ * Address: 0x140+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x140+(n)*0x70))
+#define BP_APBX_CHn_SEMA_RSVD2              24
+#define BM_APBX_CHn_SEMA_RSVD2              0xff000000
+#define BF_APBX_CHn_SEMA_RSVD2(v)           (((v) << 24) & 0xff000000)
+#define BP_APBX_CHn_SEMA_PHORE              16
+#define BM_APBX_CHn_SEMA_PHORE              0xff0000
+#define BF_APBX_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
+#define BP_APBX_CHn_SEMA_RSVD1              8
+#define BM_APBX_CHn_SEMA_RSVD1              0xff00
+#define BF_APBX_CHn_SEMA_RSVD1(v)           (((v) << 8) & 0xff00)
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA     0
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA     0xff
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBX_CHn_DEBUG1
+ * Address: 0x150+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x150+(n)*0x70))
+#define BP_APBX_CHn_DEBUG1_REQ                          31
+#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
+#define BP_APBX_CHn_DEBUG1_BURST                        30
+#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
+#define BP_APBX_CHn_DEBUG1_KICK                         29
+#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
+#define BP_APBX_CHn_DEBUG1_END                          28
+#define BM_APBX_CHn_DEBUG1_END                          0x10000000
+#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
+#define BP_APBX_CHn_DEBUG1_RSVD2                        25
+#define BM_APBX_CHn_DEBUG1_RSVD2                        0xe000000
+#define BF_APBX_CHn_DEBUG1_RSVD2(v)                     (((v) << 25) & 0xe000000)
+#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
+#define BP_APBX_CHn_DEBUG1_RSVD1                        5
+#define BM_APBX_CHn_DEBUG1_RSVD1                        0xfffe0
+#define BF_APBX_CHn_DEBUG1_RSVD1(v)                     (((v) << 5) & 0xfffe0)
+#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
+
+/**
+ * Register: HW_APBX_CHn_DEBUG2
+ * Address: 0x160+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x160+(n)*0x70))
+#define BP_APBX_CHn_DEBUG2_APB_BYTES    16
+#define BM_APBX_CHn_DEBUG2_APB_BYTES    0xffff0000
+#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
+#define BP_APBX_CHn_DEBUG2_AHB_BYTES    0
+#define BM_APBX_CHn_DEBUG2_AHB_BYTES    0xffff
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBX_VERSION
+ * Address: 0x800
+ * SCT: no
+*/
+#define HW_APBX_VERSION             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x800))
+#define BP_APBX_VERSION_MAJOR       24
+#define BM_APBX_VERSION_MAJOR       0xff000000
+#define BF_APBX_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_APBX_VERSION_MINOR       16
+#define BM_APBX_VERSION_MINOR       0xff0000
+#define BF_APBX_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_APBX_VERSION_STEP        0
+#define BM_APBX_VERSION_STEP        0xffff
+#define BF_APBX_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-audioin.h b/firmware/target/arm/imx233/regs/imx233/regs-audioin.h
new file mode 100644
index 0000000000..f2dd252f3a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-audioin.h
@@ -0,0 +1,368 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.4.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__AUDIOIN__H__
+#define __HEADERGEN__IMX233__AUDIOIN__H__
+
+#define REGS_AUDIOIN_BASE (0x8004c000)
+
+#define REGS_AUDIOIN_VERSION "3.4.0"
+
+/**
+ * Register: HW_AUDIOIN_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_AUDIOIN_CTRL                         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0))
+#define HW_AUDIOIN_CTRL_SET                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4))
+#define HW_AUDIOIN_CTRL_CLR                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8))
+#define HW_AUDIOIN_CTRL_TOG                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc))
+#define BP_AUDIOIN_CTRL_SFTRST                  31
+#define BM_AUDIOIN_CTRL_SFTRST                  0x80000000
+#define BF_AUDIOIN_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_CTRL_CLKGATE                 30
+#define BM_AUDIOIN_CTRL_CLKGATE                 0x40000000
+#define BF_AUDIOIN_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_AUDIOIN_CTRL_RSRVD3                  21
+#define BM_AUDIOIN_CTRL_RSRVD3                  0x3fe00000
+#define BF_AUDIOIN_CTRL_RSRVD3(v)               (((v) << 21) & 0x3fe00000)
+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT           16
+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT           0x1f0000
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)        (((v) << 16) & 0x1f0000)
+#define BP_AUDIOIN_CTRL_RSRVD1                  11
+#define BM_AUDIOIN_CTRL_RSRVD1                  0xf800
+#define BF_AUDIOIN_CTRL_RSRVD1(v)               (((v) << 11) & 0xf800)
+#define BP_AUDIOIN_CTRL_LR_SWAP                 10
+#define BM_AUDIOIN_CTRL_LR_SWAP                 0x400
+#define BF_AUDIOIN_CTRL_LR_SWAP(v)              (((v) << 10) & 0x400)
+#define BP_AUDIOIN_CTRL_EDGE_SYNC               9
+#define BM_AUDIOIN_CTRL_EDGE_SYNC               0x200
+#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)            (((v) << 9) & 0x200)
+#define BP_AUDIOIN_CTRL_INVERT_1BIT             8
+#define BM_AUDIOIN_CTRL_INVERT_1BIT             0x100
+#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)          (((v) << 8) & 0x100)
+#define BP_AUDIOIN_CTRL_OFFSET_ENABLE           7
+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE           0x80
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)        (((v) << 7) & 0x80)
+#define BP_AUDIOIN_CTRL_HPF_ENABLE              6
+#define BM_AUDIOIN_CTRL_HPF_ENABLE              0x40
+#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)           (((v) << 6) & 0x40)
+#define BP_AUDIOIN_CTRL_WORD_LENGTH             5
+#define BM_AUDIOIN_CTRL_WORD_LENGTH             0x20
+#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)          (((v) << 5) & 0x20)
+#define BP_AUDIOIN_CTRL_LOOPBACK                4
+#define BM_AUDIOIN_CTRL_LOOPBACK                0x10
+#define BF_AUDIOIN_CTRL_LOOPBACK(v)             (((v) << 4) & 0x10)
+#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      3
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x8
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)   (((v) << 3) & 0x8)
+#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       2
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x4
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)    (((v) << 2) & 0x4)
+#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       1
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x2
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOIN_CTRL_RUN                     0
+#define BM_AUDIOIN_CTRL_RUN                     0x1
+#define BF_AUDIOIN_CTRL_RUN(v)                  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOIN_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_AUDIOIN_STAT                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x0))
+#define HW_AUDIOIN_STAT_SET             (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x4))
+#define HW_AUDIOIN_STAT_CLR             (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0x8))
+#define HW_AUDIOIN_STAT_TOG             (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10 + 0xc))
+#define BP_AUDIOIN_STAT_ADC_PRESENT     31
+#define BM_AUDIOIN_STAT_ADC_PRESENT     0x80000000
+#define BF_AUDIOIN_STAT_ADC_PRESENT(v)  (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_STAT_RSRVD3          0
+#define BM_AUDIOIN_STAT_RSRVD3          0x7fffffff
+#define BF_AUDIOIN_STAT_RSRVD3(v)       (((v) << 0) & 0x7fffffff)
+
+/**
+ * Register: HW_AUDIOIN_ADCSRR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCSRR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0))
+#define HW_AUDIOIN_ADCSRR_SET                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4))
+#define HW_AUDIOIN_ADCSRR_CLR                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8))
+#define HW_AUDIOIN_ADCSRR_TOG                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc))
+#define BP_AUDIOIN_ADCSRR_OSR                   31
+#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
+#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
+#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
+#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) << 31) & 0x80000000)
+#define BF_AUDIOIN_ADCSRR_OSR_V(v)              ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000)
+#define BP_AUDIOIN_ADCSRR_BASEMULT              28
+#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
+#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) << 28) & 0x70000000)
+#define BF_AUDIOIN_ADCSRR_BASEMULT_V(v)         ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000)
+#define BP_AUDIOIN_ADCSRR_RSRVD2                27
+#define BM_AUDIOIN_ADCSRR_RSRVD2                0x8000000
+#define BF_AUDIOIN_ADCSRR_RSRVD2(v)             (((v) << 27) & 0x8000000)
+#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
+#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) << 24) & 0x7000000)
+#define BP_AUDIOIN_ADCSRR_RSRVD1                21
+#define BM_AUDIOIN_ADCSRR_RSRVD1                0xe00000
+#define BF_AUDIOIN_ADCSRR_RSRVD1(v)             (((v) << 21) & 0xe00000)
+#define BP_AUDIOIN_ADCSRR_SRC_INT               16
+#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
+#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) << 16) & 0x1f0000)
+#define BP_AUDIOIN_ADCSRR_RSRVD0                13
+#define BM_AUDIOIN_ADCSRR_RSRVD0                0xe000
+#define BF_AUDIOIN_ADCSRR_RSRVD0(v)             (((v) << 13) & 0xe000)
+#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
+#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_AUDIOIN_ADCVOLUME
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCVOLUME                        (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0))
+#define HW_AUDIOIN_ADCVOLUME_SET                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4))
+#define HW_AUDIOIN_ADCVOLUME_CLR                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8))
+#define HW_AUDIOIN_ADCVOLUME_TOG                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc))
+#define BP_AUDIOIN_ADCVOLUME_RSRVD5                 29
+#define BM_AUDIOIN_ADCVOLUME_RSRVD5                 0xe0000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v)              (((v) << 29) & 0xe0000000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     28
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     0x10000000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)  (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_ADCVOLUME_RSRVD4                 26
+#define BM_AUDIOIN_ADCVOLUME_RSRVD4                 0xc000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v)              (((v) << 26) & 0xc000000)
+#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                 25
+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                 0x2000000
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)              (((v) << 25) & 0x2000000)
+#define BP_AUDIOIN_ADCVOLUME_RSRVD3                 24
+#define BM_AUDIOIN_ADCVOLUME_RSRVD3                 0x1000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD3(v)              (((v) << 24) & 0x1000000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT            16
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT            0xff0000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)         (((v) << 16) & 0xff0000)
+#define BP_AUDIOIN_ADCVOLUME_RSRVD2                 13
+#define BM_AUDIOIN_ADCVOLUME_RSRVD2                 0xe000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v)              (((v) << 13) & 0xe000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    12
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    0x1000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000)
+#define BP_AUDIOIN_ADCVOLUME_RSRVD1                 8
+#define BM_AUDIOIN_ADCVOLUME_RSRVD1                 0xf00
+#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v)              (((v) << 8) & 0xf00)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0xff
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)        (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOIN_ADCDEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCDEBUG                                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0))
+#define HW_AUDIOIN_ADCDEBUG_SET                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4))
+#define HW_AUDIOIN_ADCDEBUG_CLR                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8))
+#define HW_AUDIOIN_ADCDEBUG_TOG                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc))
+#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       31
+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       0x80000000
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                    (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_ADCDEBUG_RSRVD1                              4
+#define BM_AUDIOIN_ADCDEBUG_RSRVD1                              0x7ffffff0
+#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v)                           (((v) << 4) & 0x7ffffff0)
+#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    3
+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    0x8
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8)
+#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           2
+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           0x4
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)        (((v) << 2) & 0x4)
+#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                            1
+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                            0x2
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                         (((v) << 1) & 0x2)
+#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0
+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0x1
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOIN_ADCVOL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCVOL                           (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0))
+#define HW_AUDIOIN_ADCVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4))
+#define HW_AUDIOIN_ADCVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8))
+#define HW_AUDIOIN_ADCVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc))
+#define BP_AUDIOIN_ADCVOL_RSRVD4                    29
+#define BM_AUDIOIN_ADCVOL_RSRVD4                    0xe0000000
+#define BF_AUDIOIN_ADCVOL_RSRVD4(v)                 (((v) << 29) & 0xe0000000)
+#define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     28
+#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     0x10000000
+#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_ADCVOL_RSRVD3                    26
+#define BM_AUDIOIN_ADCVOL_RSRVD3                    0xc000000
+#define BF_AUDIOIN_ADCVOL_RSRVD3(v)                 (((v) << 26) & 0xc000000)
+#define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD                25
+#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD                0x2000000
+#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)             (((v) << 25) & 0x2000000)
+#define BP_AUDIOIN_ADCVOL_MUTE                      24
+#define BM_AUDIOIN_ADCVOL_MUTE                      0x1000000
+#define BF_AUDIOIN_ADCVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
+#define BP_AUDIOIN_ADCVOL_RSRVD2                    14
+#define BM_AUDIOIN_ADCVOL_RSRVD2                    0xffc000
+#define BF_AUDIOIN_ADCVOL_RSRVD2(v)                 (((v) << 14) & 0xffc000)
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT               12
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT               0x3000
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)            (((v) << 12) & 0x3000)
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT                 8
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT                 0xf00
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)              (((v) << 8) & 0xf00)
+#define BP_AUDIOIN_ADCVOL_RSRVD1                    6
+#define BM_AUDIOIN_ADCVOL_RSRVD1                    0xc0
+#define BF_AUDIOIN_ADCVOL_RSRVD1(v)                 (((v) << 6) & 0xc0)
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT              4
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT              0x30
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)           (((v) << 4) & 0x30)
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT                0
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT                0xf
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)             (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_AUDIOIN_MICLINE
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_AUDIOIN_MICLINE                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0))
+#define HW_AUDIOIN_MICLINE_SET                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4))
+#define HW_AUDIOIN_MICLINE_CLR                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8))
+#define HW_AUDIOIN_MICLINE_TOG                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc))
+#define BP_AUDIOIN_MICLINE_RSRVD6               30
+#define BM_AUDIOIN_MICLINE_RSRVD6               0xc0000000
+#define BF_AUDIOIN_MICLINE_RSRVD6(v)            (((v) << 30) & 0xc0000000)
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1         29
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1         0x20000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)      (((v) << 29) & 0x20000000)
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2         28
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2         0x10000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)      (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_MICLINE_RSRVD5               25
+#define BM_AUDIOIN_MICLINE_RSRVD5               0xe000000
+#define BF_AUDIOIN_MICLINE_RSRVD5(v)            (((v) << 25) & 0xe000000)
+#define BP_AUDIOIN_MICLINE_MIC_SELECT           24
+#define BM_AUDIOIN_MICLINE_MIC_SELECT           0x1000000
+#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)        (((v) << 24) & 0x1000000)
+#define BP_AUDIOIN_MICLINE_RSRVD4               22
+#define BM_AUDIOIN_MICLINE_RSRVD4               0xc00000
+#define BF_AUDIOIN_MICLINE_RSRVD4(v)            (((v) << 22) & 0xc00000)
+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR         20
+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR         0x300000
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off    0x0
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm  0x1
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm  0x2
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm  0x3
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)      (((v) << 20) & 0x300000)
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)    ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000)
+#define BP_AUDIOIN_MICLINE_RSRVD3               19
+#define BM_AUDIOIN_MICLINE_RSRVD3               0x80000
+#define BF_AUDIOIN_MICLINE_RSRVD3(v)            (((v) << 19) & 0x80000)
+#define BP_AUDIOIN_MICLINE_MIC_BIAS             16
+#define BM_AUDIOIN_MICLINE_MIC_BIAS             0x70000
+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)          (((v) << 16) & 0x70000)
+#define BP_AUDIOIN_MICLINE_RSRVD2               6
+#define BM_AUDIOIN_MICLINE_RSRVD2               0xffc0
+#define BF_AUDIOIN_MICLINE_RSRVD2(v)            (((v) << 6) & 0xffc0)
+#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK          4
+#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK          0x30
+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v)       (((v) << 4) & 0x30)
+#define BP_AUDIOIN_MICLINE_RSRVD1               2
+#define BM_AUDIOIN_MICLINE_RSRVD1               0xc
+#define BF_AUDIOIN_MICLINE_RSRVD1(v)            (((v) << 2) & 0xc)
+#define BP_AUDIOIN_MICLINE_MIC_GAIN             0
+#define BM_AUDIOIN_MICLINE_MIC_GAIN             0x3
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB        0x0
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB       0x1
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB       0x2
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB       0x3
+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)          (((v) << 0) & 0x3)
+#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v)        ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3)
+
+/**
+ * Register: HW_AUDIOIN_ANACLKCTRL
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ANACLKCTRL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0))
+#define HW_AUDIOIN_ANACLKCTRL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4))
+#define HW_AUDIOIN_ANACLKCTRL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8))
+#define HW_AUDIOIN_ANACLKCTRL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc))
+#define BP_AUDIOIN_ANACLKCTRL_CLKGATE           31
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE           0x80000000
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)        (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD4            11
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD4            0x7ffff800
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v)         (((v) << 11) & 0x7ffff800)
+#define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF        10
+#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF        0x400
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)     (((v) << 10) & 0x400)
+#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER       9
+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER       0x200
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)    (((v) << 9) & 0x200)
+#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     8
+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     0x100
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)  (((v) << 8) & 0x100)
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD3            6
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD3            0xc0
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v)         (((v) << 6) & 0xc0)
+#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT      4
+#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT      0x30
+#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v)   (((v) << 4) & 0x30)
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD2            3
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD2            0x8
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD2(v)         (((v) << 3) & 0x8)
+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV            0
+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV            0x7
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)         (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOIN_DATA
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_AUDIOIN_DATA         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x0))
+#define HW_AUDIOIN_DATA_SET     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x4))
+#define HW_AUDIOIN_DATA_CLR     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0x8))
+#define HW_AUDIOIN_DATA_TOG     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80 + 0xc))
+#define BP_AUDIOIN_DATA_HIGH    16
+#define BM_AUDIOIN_DATA_HIGH    0xffff0000
+#define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000)
+#define BP_AUDIOIN_DATA_LOW     0
+#define BM_AUDIOIN_DATA_LOW     0xffff
+#define BF_AUDIOIN_DATA_LOW(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-audioout.h b/firmware/target/arm/imx233/regs/imx233/regs-audioout.h
new file mode 100644
index 0000000000..2b9f62ae74
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-audioout.h
@@ -0,0 +1,673 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__AUDIOOUT__H__
+#define __HEADERGEN__IMX233__AUDIOOUT__H__
+
+#define REGS_AUDIOOUT_BASE (0x80048000)
+
+#define REGS_AUDIOOUT_VERSION "3.2.0"
+
+/**
+ * Register: HW_AUDIOOUT_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_CTRL                        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0))
+#define HW_AUDIOOUT_CTRL_SET                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4))
+#define HW_AUDIOOUT_CTRL_CLR                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8))
+#define HW_AUDIOOUT_CTRL_TOG                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc))
+#define BP_AUDIOOUT_CTRL_SFTRST                 31
+#define BM_AUDIOOUT_CTRL_SFTRST                 0x80000000
+#define BF_AUDIOOUT_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_CTRL_CLKGATE                30
+#define BM_AUDIOOUT_CTRL_CLKGATE                0x40000000
+#define BF_AUDIOOUT_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_AUDIOOUT_CTRL_RSRVD4                 21
+#define BM_AUDIOOUT_CTRL_RSRVD4                 0x3fe00000
+#define BF_AUDIOOUT_CTRL_RSRVD4(v)              (((v) << 21) & 0x3fe00000)
+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT          16
+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT          0x1f0000
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
+#define BP_AUDIOOUT_CTRL_RSRVD3                 15
+#define BM_AUDIOOUT_CTRL_RSRVD3                 0x8000
+#define BF_AUDIOOUT_CTRL_RSRVD3(v)              (((v) << 15) & 0x8000)
+#define BP_AUDIOOUT_CTRL_LR_SWAP                14
+#define BM_AUDIOOUT_CTRL_LR_SWAP                0x4000
+#define BF_AUDIOOUT_CTRL_LR_SWAP(v)             (((v) << 14) & 0x4000)
+#define BP_AUDIOOUT_CTRL_EDGE_SYNC              13
+#define BM_AUDIOOUT_CTRL_EDGE_SYNC              0x2000
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)           (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_CTRL_INVERT_1BIT            12
+#define BM_AUDIOOUT_CTRL_INVERT_1BIT            0x1000
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)         (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_CTRL_RSRVD2                 10
+#define BM_AUDIOOUT_CTRL_RSRVD2                 0xc00
+#define BF_AUDIOOUT_CTRL_RSRVD2(v)              (((v) << 10) & 0xc00)
+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT            8
+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT            0x300
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)         (((v) << 8) & 0x300)
+#define BP_AUDIOOUT_CTRL_RSRVD1                 7
+#define BM_AUDIOOUT_CTRL_RSRVD1                 0x80
+#define BF_AUDIOOUT_CTRL_RSRVD1(v)              (((v) << 7) & 0x80)
+#define BP_AUDIOOUT_CTRL_WORD_LENGTH            6
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH            0x40
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)         (((v) << 6) & 0x40)
+#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        5
+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        0x20
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)     (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_CTRL_LOOPBACK               4
+#define BM_AUDIOOUT_CTRL_LOOPBACK               0x10
+#define BF_AUDIOOUT_CTRL_LOOPBACK(v)            (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     3
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x8
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)  (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      2
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x4
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)   (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      1
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x2
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_CTRL_RUN                    0
+#define BM_AUDIOOUT_CTRL_RUN                    0x1
+#define BF_AUDIOOUT_CTRL_RUN(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_STAT                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x0))
+#define HW_AUDIOOUT_STAT_SET            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x4))
+#define HW_AUDIOOUT_STAT_CLR            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0x8))
+#define HW_AUDIOOUT_STAT_TOG            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10 + 0xc))
+#define BP_AUDIOOUT_STAT_DAC_PRESENT    31
+#define BM_AUDIOOUT_STAT_DAC_PRESENT    0x80000000
+#define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_STAT_RSRVD1         0
+#define BM_AUDIOOUT_STAT_RSRVD1         0x7fffffff
+#define BF_AUDIOOUT_STAT_RSRVD1(v)      (((v) << 0) & 0x7fffffff)
+
+/**
+ * Register: HW_AUDIOOUT_DACSRR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACSRR                          (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0))
+#define HW_AUDIOOUT_DACSRR_SET                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4))
+#define HW_AUDIOOUT_DACSRR_CLR                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8))
+#define HW_AUDIOOUT_DACSRR_TOG                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc))
+#define BP_AUDIOOUT_DACSRR_OSR                      31
+#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
+#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
+#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
+#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) << 31) & 0x80000000)
+#define BF_AUDIOOUT_DACSRR_OSR_V(v)                 ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000)
+#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
+#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
+#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) << 28) & 0x70000000)
+#define BF_AUDIOOUT_DACSRR_BASEMULT_V(v)            ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000)
+#define BP_AUDIOOUT_DACSRR_RSRVD2                   27
+#define BM_AUDIOOUT_DACSRR_RSRVD2                   0x8000000
+#define BF_AUDIOOUT_DACSRR_RSRVD2(v)                (((v) << 27) & 0x8000000)
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) << 24) & 0x7000000)
+#define BP_AUDIOOUT_DACSRR_RSRVD1                   21
+#define BM_AUDIOOUT_DACSRR_RSRVD1                   0xe00000
+#define BF_AUDIOOUT_DACSRR_RSRVD1(v)                (((v) << 21) & 0xe00000)
+#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
+#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
+#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) << 16) & 0x1f0000)
+#define BP_AUDIOOUT_DACSRR_RSRVD0                   13
+#define BM_AUDIOOUT_DACSRR_RSRVD0                   0xe000
+#define BF_AUDIOOUT_DACSRR_RSRVD0(v)                (((v) << 13) & 0xe000)
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_AUDIOOUT_DACVOLUME
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACVOLUME                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0))
+#define HW_AUDIOOUT_DACVOLUME_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4))
+#define HW_AUDIOOUT_DACVOLUME_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8))
+#define HW_AUDIOOUT_DACVOLUME_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc))
+#define BP_AUDIOOUT_DACVOLUME_RSRVD4                    29
+#define BM_AUDIOOUT_DACVOLUME_RSRVD4                    0xe0000000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v)                 (((v) << 29) & 0xe0000000)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_DACVOLUME_RSRVD3                    26
+#define BM_AUDIOOUT_DACVOLUME_RSRVD3                    0xc000000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v)                 (((v) << 26) & 0xc000000)
+#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) << 16) & 0xff0000)
+#define BP_AUDIOOUT_DACVOLUME_RSRVD2                    13
+#define BM_AUDIOOUT_DACVOLUME_RSRVD2                    0xe000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v)                 (((v) << 13) & 0xe000)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_DACVOLUME_RSRVD1                    9
+#define BM_AUDIOOUT_DACVOLUME_RSRVD1                    0xe00
+#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v)                 (((v) << 9) & 0xe00)
+#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) << 8) & 0x100)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOOUT_DACDEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACDEBUG                                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0))
+#define HW_AUDIOOUT_DACDEBUG_SET                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4))
+#define HW_AUDIOOUT_DACDEBUG_CLR                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8))
+#define HW_AUDIOOUT_DACDEBUG_TOG                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc))
+#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  31
+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  0x80000000
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)               (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_DACDEBUG_RSRVD2                         12
+#define BM_AUDIOOUT_DACDEBUG_RSRVD2                         0x7ffff000
+#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v)                      (((v) << 12) & 0x7ffff000)
+#define BP_AUDIOOUT_DACDEBUG_RAM_SS                         8
+#define BM_AUDIOOUT_DACDEBUG_RAM_SS                         0xf00
+#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v)                      (((v) << 8) & 0xf00)
+#define BP_AUDIOOUT_DACDEBUG_RSRVD1                         6
+#define BM_AUDIOOUT_DACDEBUG_RSRVD1                         0xc0
+#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v)                      (((v) << 6) & 0xc0)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       5
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       0x20
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)    (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       4
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       0x10
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)    (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      3
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      0x8
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)   (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      2
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      0x4
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)   (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                       1
+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                       0x2
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0
+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0x1
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_HPVOL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_HPVOL                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0))
+#define HW_AUDIOOUT_HPVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4))
+#define HW_AUDIOOUT_HPVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8))
+#define HW_AUDIOOUT_HPVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc))
+#define BP_AUDIOOUT_HPVOL_RSRVD5                    29
+#define BM_AUDIOOUT_HPVOL_RSRVD5                    0xe0000000
+#define BF_AUDIOOUT_HPVOL_RSRVD5(v)                 (((v) << 29) & 0xe0000000)
+#define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     28
+#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     0x10000000
+#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_HPVOL_RSRVD4                    26
+#define BM_AUDIOOUT_HPVOL_RSRVD4                    0xc000000
+#define BF_AUDIOOUT_HPVOL_RSRVD4(v)                 (((v) << 26) & 0xc000000)
+#define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD               25
+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD               0x2000000
+#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)            (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_HPVOL_MUTE                      24
+#define BM_AUDIOOUT_HPVOL_MUTE                      0x1000000
+#define BF_AUDIOOUT_HPVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_HPVOL_RSRVD3                    17
+#define BM_AUDIOOUT_HPVOL_RSRVD3                    0xfe0000
+#define BF_AUDIOOUT_HPVOL_RSRVD3(v)                 (((v) << 17) & 0xfe0000)
+#define BP_AUDIOOUT_HPVOL_SELECT                    16
+#define BM_AUDIOOUT_HPVOL_SELECT                    0x10000
+#define BF_AUDIOOUT_HPVOL_SELECT(v)                 (((v) << 16) & 0x10000)
+#define BP_AUDIOOUT_HPVOL_RSRVD2                    15
+#define BM_AUDIOOUT_HPVOL_RSRVD2                    0x8000
+#define BF_AUDIOOUT_HPVOL_RSRVD2(v)                 (((v) << 15) & 0x8000)
+#define BP_AUDIOOUT_HPVOL_VOL_LEFT                  8
+#define BM_AUDIOOUT_HPVOL_VOL_LEFT                  0x7f00
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)               (((v) << 8) & 0x7f00)
+#define BP_AUDIOOUT_HPVOL_RSRVD1                    7
+#define BM_AUDIOOUT_HPVOL_RSRVD1                    0x80
+#define BF_AUDIOOUT_HPVOL_RSRVD1(v)                 (((v) << 7) & 0x80)
+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT                 0
+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT                 0x7f
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)              (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_AUDIOOUT_RESERVED
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_RESERVED            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x0))
+#define HW_AUDIOOUT_RESERVED_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x4))
+#define HW_AUDIOOUT_RESERVED_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x8))
+#define HW_AUDIOOUT_RESERVED_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0xc))
+#define BP_AUDIOOUT_RESERVED_RSRVD1     0
+#define BM_AUDIOOUT_RESERVED_RSRVD1     0xffffffff
+#define BF_AUDIOOUT_RESERVED_RSRVD1(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_AUDIOOUT_PWRDN
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_PWRDN               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0))
+#define HW_AUDIOOUT_PWRDN_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4))
+#define HW_AUDIOOUT_PWRDN_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8))
+#define HW_AUDIOOUT_PWRDN_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc))
+#define BP_AUDIOOUT_PWRDN_RSRVD7        25
+#define BM_AUDIOOUT_PWRDN_RSRVD7        0xfe000000
+#define BF_AUDIOOUT_PWRDN_RSRVD7(v)     (((v) << 25) & 0xfe000000)
+#define BP_AUDIOOUT_PWRDN_SPEAKER       24
+#define BM_AUDIOOUT_PWRDN_SPEAKER       0x1000000
+#define BF_AUDIOOUT_PWRDN_SPEAKER(v)    (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_PWRDN_RSRVD6        21
+#define BM_AUDIOOUT_PWRDN_RSRVD6        0xe00000
+#define BF_AUDIOOUT_PWRDN_RSRVD6(v)     (((v) << 21) & 0xe00000)
+#define BP_AUDIOOUT_PWRDN_SELFBIAS      20
+#define BM_AUDIOOUT_PWRDN_SELFBIAS      0x100000
+#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)   (((v) << 20) & 0x100000)
+#define BP_AUDIOOUT_PWRDN_RSRVD5        17
+#define BM_AUDIOOUT_PWRDN_RSRVD5        0xe0000
+#define BF_AUDIOOUT_PWRDN_RSRVD5(v)     (((v) << 17) & 0xe0000)
+#define BP_AUDIOOUT_PWRDN_RIGHT_ADC     16
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x10000
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)  (((v) << 16) & 0x10000)
+#define BP_AUDIOOUT_PWRDN_RSRVD4        13
+#define BM_AUDIOOUT_PWRDN_RSRVD4        0xe000
+#define BF_AUDIOOUT_PWRDN_RSRVD4(v)     (((v) << 13) & 0xe000)
+#define BP_AUDIOOUT_PWRDN_DAC           12
+#define BM_AUDIOOUT_PWRDN_DAC           0x1000
+#define BF_AUDIOOUT_PWRDN_DAC(v)        (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_PWRDN_RSRVD3        9
+#define BM_AUDIOOUT_PWRDN_RSRVD3        0xe00
+#define BF_AUDIOOUT_PWRDN_RSRVD3(v)     (((v) << 9) & 0xe00)
+#define BP_AUDIOOUT_PWRDN_ADC           8
+#define BM_AUDIOOUT_PWRDN_ADC           0x100
+#define BF_AUDIOOUT_PWRDN_ADC(v)        (((v) << 8) & 0x100)
+#define BP_AUDIOOUT_PWRDN_RSRVD2        5
+#define BM_AUDIOOUT_PWRDN_RSRVD2        0xe0
+#define BF_AUDIOOUT_PWRDN_RSRVD2(v)     (((v) << 5) & 0xe0)
+#define BP_AUDIOOUT_PWRDN_CAPLESS       4
+#define BM_AUDIOOUT_PWRDN_CAPLESS       0x10
+#define BF_AUDIOOUT_PWRDN_CAPLESS(v)    (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_PWRDN_RSRVD1        1
+#define BM_AUDIOOUT_PWRDN_RSRVD1        0xe
+#define BF_AUDIOOUT_PWRDN_RSRVD1(v)     (((v) << 1) & 0xe)
+#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
+#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x1
+#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_REFCTRL
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_REFCTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0))
+#define HW_AUDIOOUT_REFCTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4))
+#define HW_AUDIOOUT_REFCTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8))
+#define HW_AUDIOOUT_REFCTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc))
+#define BP_AUDIOOUT_REFCTRL_RSRVD4              27
+#define BM_AUDIOOUT_REFCTRL_RSRVD4              0xf8000000
+#define BF_AUDIOOUT_REFCTRL_RSRVD4(v)           (((v) << 27) & 0xf8000000)
+#define BP_AUDIOOUT_REFCTRL_FASTSETTLING        26
+#define BM_AUDIOOUT_REFCTRL_FASTSETTLING        0x4000000
+#define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v)     (((v) << 26) & 0x4000000)
+#define BP_AUDIOOUT_REFCTRL_RAISE_REF           25
+#define BM_AUDIOOUT_REFCTRL_RAISE_REF           0x2000000
+#define BF_AUDIOOUT_REFCTRL_RAISE_REF(v)        (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       24
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x1000000
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)    (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_REFCTRL_RSRVD3              23
+#define BM_AUDIOOUT_REFCTRL_RSRVD3              0x800000
+#define BF_AUDIOOUT_REFCTRL_RSRVD3(v)           (((v) << 23) & 0x800000)
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ             20
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ             0x700000
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)          (((v) << 20) & 0x700000)
+#define BP_AUDIOOUT_REFCTRL_LOW_PWR             19
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR             0x80000
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)          (((v) << 19) & 0x80000)
+#define BP_AUDIOOUT_REFCTRL_LW_REF              18
+#define BM_AUDIOOUT_REFCTRL_LW_REF              0x40000
+#define BF_AUDIOOUT_REFCTRL_LW_REF(v)           (((v) << 18) & 0x40000)
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL           16
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL           0x30000
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)        (((v) << 16) & 0x30000)
+#define BP_AUDIOOUT_REFCTRL_RSRVD2              15
+#define BM_AUDIOOUT_REFCTRL_RSRVD2              0x8000
+#define BF_AUDIOOUT_REFCTRL_RSRVD2(v)           (((v) << 15) & 0x8000)
+#define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     14
+#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     0x4000
+#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)  (((v) << 14) & 0x4000)
+#define BP_AUDIOOUT_REFCTRL_ADJ_ADC             13
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC             0x2000
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)          (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_REFCTRL_ADJ_VAG             12
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG             0x1000
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)          (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL          8
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL          0xf00
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)       (((v) << 8) & 0xf00)
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL             4
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL             0xf0
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)          (((v) << 4) & 0xf0)
+#define BP_AUDIOOUT_REFCTRL_RSRVD1              3
+#define BM_AUDIOOUT_REFCTRL_RSRVD1              0x8
+#define BF_AUDIOOUT_REFCTRL_RSRVD1(v)           (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ             0
+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ             0x7
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)          (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOOUT_ANACTRL
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_ANACTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0))
+#define HW_AUDIOOUT_ANACTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4))
+#define HW_AUDIOOUT_ANACTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8))
+#define HW_AUDIOOUT_ANACTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc))
+#define BP_AUDIOOUT_ANACTRL_RSRVD8              29
+#define BM_AUDIOOUT_ANACTRL_RSRVD8              0xe0000000
+#define BF_AUDIOOUT_ANACTRL_RSRVD8(v)           (((v) << 29) & 0xe0000000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_ANACTRL_RSRVD7              25
+#define BM_AUDIOOUT_ANACTRL_RSRVD7              0xe000000
+#define BF_AUDIOOUT_ANACTRL_RSRVD7(v)           (((v) << 25) & 0xe000000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_ANACTRL_RSRVD6              22
+#define BM_AUDIOOUT_ANACTRL_RSRVD6              0xc00000
+#define BF_AUDIOOUT_ANACTRL_RSRVD6(v)           (((v) << 22) & 0xc00000)
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) << 20) & 0x300000)
+#define BP_AUDIOOUT_ANACTRL_RSRVD5              19
+#define BM_AUDIOOUT_ANACTRL_RSRVD5              0x80000
+#define BF_AUDIOOUT_ANACTRL_RSRVD5(v)           (((v) << 19) & 0x80000)
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) << 17) & 0x60000)
+#define BP_AUDIOOUT_ANACTRL_RSRVD4              15
+#define BM_AUDIOOUT_ANACTRL_RSRVD4              0x18000
+#define BF_AUDIOOUT_ANACTRL_RSRVD4(v)           (((v) << 15) & 0x18000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) << 12) & 0x7000)
+#define BP_AUDIOOUT_ANACTRL_RSRVD3              11
+#define BM_AUDIOOUT_ANACTRL_RSRVD3              0x800
+#define BF_AUDIOOUT_ANACTRL_RSRVD3(v)           (((v) << 11) & 0x800)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) << 8) & 0x700)
+#define BP_AUDIOOUT_ANACTRL_RSRVD2              6
+#define BM_AUDIOOUT_ANACTRL_RSRVD2              0xc0
+#define BF_AUDIOOUT_ANACTRL_RSRVD2(v)           (((v) << 6) & 0xc0)
+#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_ANACTRL_RSRVD1              0
+#define BM_AUDIOOUT_ANACTRL_RSRVD1              0xf
+#define BF_AUDIOOUT_ANACTRL_RSRVD1(v)           (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_AUDIOOUT_TEST
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_TEST                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0))
+#define HW_AUDIOOUT_TEST_SET                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4))
+#define HW_AUDIOOUT_TEST_CLR                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8))
+#define HW_AUDIOOUT_TEST_TOG                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc))
+#define BP_AUDIOOUT_TEST_RSRVD4             31
+#define BM_AUDIOOUT_TEST_RSRVD4             0x80000000
+#define BF_AUDIOOUT_TEST_RSRVD4(v)          (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_TEST_HP_ANTIPOP         28
+#define BM_AUDIOOUT_TEST_HP_ANTIPOP         0x70000000
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)      (((v) << 28) & 0x70000000)
+#define BP_AUDIOOUT_TEST_RSRVD3             27
+#define BM_AUDIOOUT_TEST_RSRVD3             0x8000000
+#define BF_AUDIOOUT_TEST_RSRVD3(v)          (((v) << 27) & 0x8000000)
+#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP      26
+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP      0x4000000
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)   (((v) << 26) & 0x4000000)
+#define BP_AUDIOOUT_TEST_TM_LOOP            25
+#define BM_AUDIOOUT_TEST_TM_LOOP            0x2000000
+#define BF_AUDIOOUT_TEST_TM_LOOP(v)         (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_TEST_TM_HPCOMMON        24
+#define BM_AUDIOOUT_TEST_TM_HPCOMMON        0x1000000
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)     (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ          22
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ          0xc00000
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)       (((v) << 22) & 0xc00000)
+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ        20
+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ        0x300000
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)     (((v) << 20) & 0x300000)
+#define BP_AUDIOOUT_TEST_RSRVD2             14
+#define BM_AUDIOOUT_TEST_RSRVD2             0xfc000
+#define BF_AUDIOOUT_TEST_RSRVD2(v)          (((v) << 14) & 0xfc000)
+#define BP_AUDIOOUT_TEST_VAG_CLASSA         13
+#define BM_AUDIOOUT_TEST_VAG_CLASSA         0x2000
+#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)      (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I       12
+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I       0x1000
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)    (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_TEST_RSRVD1             4
+#define BM_AUDIOOUT_TEST_RSRVD1             0xff0
+#define BF_AUDIOOUT_TEST_RSRVD1(v)          (((v) << 4) & 0xff0)
+#define BP_AUDIOOUT_TEST_ADCTODAC_LOOP      3
+#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP      0x8
+#define BF_AUDIOOUT_TEST_ADCTODAC_LOOP(v)   (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_TEST_DAC_CLASSA         2
+#define BM_AUDIOOUT_TEST_DAC_CLASSA         0x4
+#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)      (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I       1
+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I       0x2
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ        0
+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ        0x1
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_BISTCTRL
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_BISTCTRL            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0))
+#define HW_AUDIOOUT_BISTCTRL_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4))
+#define HW_AUDIOOUT_BISTCTRL_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8))
+#define HW_AUDIOOUT_BISTCTRL_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc))
+#define BP_AUDIOOUT_BISTCTRL_RSVD0      4
+#define BM_AUDIOOUT_BISTCTRL_RSVD0      0xfffffff0
+#define BF_AUDIOOUT_BISTCTRL_RSVD0(v)   (((v) << 4) & 0xfffffff0)
+#define BP_AUDIOOUT_BISTCTRL_FAIL       3
+#define BM_AUDIOOUT_BISTCTRL_FAIL       0x8
+#define BF_AUDIOOUT_BISTCTRL_FAIL(v)    (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_BISTCTRL_PASS       2
+#define BM_AUDIOOUT_BISTCTRL_PASS       0x4
+#define BF_AUDIOOUT_BISTCTRL_PASS(v)    (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_BISTCTRL_DONE       1
+#define BM_AUDIOOUT_BISTCTRL_DONE       0x2
+#define BF_AUDIOOUT_BISTCTRL_DONE(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_BISTCTRL_START      0
+#define BM_AUDIOOUT_BISTCTRL_START      0x1
+#define BF_AUDIOOUT_BISTCTRL_START(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_BISTSTAT0
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_BISTSTAT0           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x0))
+#define HW_AUDIOOUT_BISTSTAT0_SET       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x4))
+#define HW_AUDIOOUT_BISTSTAT0_CLR       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0x8))
+#define HW_AUDIOOUT_BISTSTAT0_TOG       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0 + 0xc))
+#define BP_AUDIOOUT_BISTSTAT0_RSVD0     24
+#define BM_AUDIOOUT_BISTSTAT0_RSVD0     0xff000000
+#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v)  (((v) << 24) & 0xff000000)
+#define BP_AUDIOOUT_BISTSTAT0_DATA      0
+#define BM_AUDIOOUT_BISTSTAT0_DATA      0xffffff
+#define BF_AUDIOOUT_BISTSTAT0_DATA(v)   (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_AUDIOOUT_BISTSTAT1
+ * Address: 0xd0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_BISTSTAT1           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x0))
+#define HW_AUDIOOUT_BISTSTAT1_SET       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x4))
+#define HW_AUDIOOUT_BISTSTAT1_CLR       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0x8))
+#define HW_AUDIOOUT_BISTSTAT1_TOG       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0 + 0xc))
+#define BP_AUDIOOUT_BISTSTAT1_RSVD1     29
+#define BM_AUDIOOUT_BISTSTAT1_RSVD1     0xe0000000
+#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v)  (((v) << 29) & 0xe0000000)
+#define BP_AUDIOOUT_BISTSTAT1_STATE     24
+#define BM_AUDIOOUT_BISTSTAT1_STATE     0x1f000000
+#define BF_AUDIOOUT_BISTSTAT1_STATE(v)  (((v) << 24) & 0x1f000000)
+#define BP_AUDIOOUT_BISTSTAT1_RSVD0     8
+#define BM_AUDIOOUT_BISTSTAT1_RSVD0     0xffff00
+#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v)  (((v) << 8) & 0xffff00)
+#define BP_AUDIOOUT_BISTSTAT1_ADDR      0
+#define BM_AUDIOOUT_BISTSTAT1_ADDR      0xff
+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOOUT_ANACLKCTRL
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_ANACLKCTRL                  (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0))
+#define HW_AUDIOOUT_ANACLKCTRL_SET              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4))
+#define HW_AUDIOOUT_ANACLKCTRL_CLR              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8))
+#define HW_AUDIOOUT_ANACLKCTRL_TOG              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc))
+#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE          31
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE          0x80000000
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3           5
+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3           0x7fffffe0
+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v)        (((v) << 5) & 0x7fffffe0)
+#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    4
+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    0x10
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_ANACLKCTRL_RSRVD2           3
+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2           0x8
+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD2(v)        (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV           0
+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV           0x7
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)        (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOOUT_DATA
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DATA            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0))
+#define HW_AUDIOOUT_DATA_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4))
+#define HW_AUDIOOUT_DATA_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8))
+#define HW_AUDIOOUT_DATA_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc))
+#define BP_AUDIOOUT_DATA_HIGH       16
+#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
+#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) << 16) & 0xffff0000)
+#define BP_AUDIOOUT_DATA_LOW        0
+#define BM_AUDIOOUT_DATA_LOW        0xffff
+#define BF_AUDIOOUT_DATA_LOW(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_AUDIOOUT_SPEAKERCTRL
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_SPEAKERCTRL                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x0))
+#define HW_AUDIOOUT_SPEAKERCTRL_SET             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x4))
+#define HW_AUDIOOUT_SPEAKERCTRL_CLR             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x8))
+#define HW_AUDIOOUT_SPEAKERCTRL_TOG             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0xc))
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2          25
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2          0xfe000000
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v)       (((v) << 25) & 0xfe000000)
+#define BP_AUDIOOUT_SPEAKERCTRL_MUTE            24
+#define BM_AUDIOOUT_SPEAKERCTRL_MUTE            0x1000000
+#define BF_AUDIOOUT_SPEAKERCTRL_MUTE(v)         (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ          22
+#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ          0xc00000
+#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v)       (((v) << 22) & 0xc00000)
+#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ        20
+#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ        0x300000
+#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v)     (((v) << 20) & 0x300000)
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1          16
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1          0xf0000
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v)       (((v) << 16) & 0xf0000)
+#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER       14
+#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER       0xc000
+#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v)    (((v) << 14) & 0xc000)
+#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER       12
+#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER       0x3000
+#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v)    (((v) << 12) & 0x3000)
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0          0
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0          0xfff
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v)       (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_AUDIOOUT_VERSION
+ * Address: 0x200
+ * SCT: no
+*/
+#define HW_AUDIOOUT_VERSION             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x200))
+#define BP_AUDIOOUT_VERSION_MAJOR       24
+#define BM_AUDIOOUT_VERSION_MAJOR       0xff000000
+#define BF_AUDIOOUT_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_AUDIOOUT_VERSION_MINOR       16
+#define BM_AUDIOOUT_VERSION_MINOR       0xff0000
+#define BF_AUDIOOUT_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_AUDIOOUT_VERSION_STEP        0
+#define BM_AUDIOOUT_VERSION_STEP        0xffff
+#define BF_AUDIOOUT_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-bch.h b/firmware/target/arm/imx233/regs/imx233/regs-bch.h
new file mode 100644
index 0000000000..d8ecf4297c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-bch.h
@@ -0,0 +1,606 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__BCH__H__
+#define __HEADERGEN__IMX233__BCH__H__
+
+#define REGS_BCH_BASE (0x8000a000)
+
+#define REGS_BCH_VERSION "3.2.0"
+
+/**
+ * Register: HW_BCH_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_BCH_CTRL                         (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x0))
+#define HW_BCH_CTRL_SET                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x4))
+#define HW_BCH_CTRL_CLR                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0x8))
+#define HW_BCH_CTRL_TOG                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x0 + 0xc))
+#define BP_BCH_CTRL_SFTRST                  31
+#define BM_BCH_CTRL_SFTRST                  0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN             0x0
+#define BV_BCH_CTRL_SFTRST__RESET           0x1
+#define BF_BCH_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BF_BCH_CTRL_SFTRST_V(v)             ((BV_BCH_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_BCH_CTRL_CLKGATE                 30
+#define BM_BCH_CTRL_CLKGATE                 0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN            0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS        0x1
+#define BF_BCH_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BF_BCH_CTRL_CLKGATE_V(v)            ((BV_BCH_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_BCH_CTRL_RSVD5                   23
+#define BM_BCH_CTRL_RSVD5                   0x3f800000
+#define BF_BCH_CTRL_RSVD5(v)                (((v) << 23) & 0x3f800000)
+#define BP_BCH_CTRL_DEBUGSYNDROME           22
+#define BM_BCH_CTRL_DEBUGSYNDROME           0x400000
+#define BF_BCH_CTRL_DEBUGSYNDROME(v)        (((v) << 22) & 0x400000)
+#define BP_BCH_CTRL_RSVD4                   20
+#define BM_BCH_CTRL_RSVD4                   0x300000
+#define BF_BCH_CTRL_RSVD4(v)                (((v) << 20) & 0x300000)
+#define BP_BCH_CTRL_M2M_LAYOUT              18
+#define BM_BCH_CTRL_M2M_LAYOUT              0xc0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v)           (((v) << 18) & 0xc0000)
+#define BP_BCH_CTRL_M2M_ENCODE              17
+#define BM_BCH_CTRL_M2M_ENCODE              0x20000
+#define BF_BCH_CTRL_M2M_ENCODE(v)           (((v) << 17) & 0x20000)
+#define BP_BCH_CTRL_M2M_ENABLE              16
+#define BM_BCH_CTRL_M2M_ENABLE              0x10000
+#define BF_BCH_CTRL_M2M_ENABLE(v)           (((v) << 16) & 0x10000)
+#define BP_BCH_CTRL_RSVD3                   11
+#define BM_BCH_CTRL_RSVD3                   0xf800
+#define BF_BCH_CTRL_RSVD3(v)                (((v) << 11) & 0xf800)
+#define BP_BCH_CTRL_DEBUG_STALL_IRQ_EN      10
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN      0x400
+#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(v)   (((v) << 10) & 0x400)
+#define BP_BCH_CTRL_RSVD2                   9
+#define BM_BCH_CTRL_RSVD2                   0x200
+#define BF_BCH_CTRL_RSVD2(v)                (((v) << 9) & 0x200)
+#define BP_BCH_CTRL_COMPLETE_IRQ_EN         8
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN         0x100
+#define BF_BCH_CTRL_COMPLETE_IRQ_EN(v)      (((v) << 8) & 0x100)
+#define BP_BCH_CTRL_RSVD1                   4
+#define BM_BCH_CTRL_RSVD1                   0xf0
+#define BF_BCH_CTRL_RSVD1(v)                (((v) << 4) & 0xf0)
+#define BP_BCH_CTRL_BM_ERROR_IRQ            3
+#define BM_BCH_CTRL_BM_ERROR_IRQ            0x8
+#define BF_BCH_CTRL_BM_ERROR_IRQ(v)         (((v) << 3) & 0x8)
+#define BP_BCH_CTRL_DEBUG_STALL_IRQ         2
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ         0x4
+#define BF_BCH_CTRL_DEBUG_STALL_IRQ(v)      (((v) << 2) & 0x4)
+#define BP_BCH_CTRL_RSVD0                   1
+#define BM_BCH_CTRL_RSVD0                   0x2
+#define BF_BCH_CTRL_RSVD0(v)                (((v) << 1) & 0x2)
+#define BP_BCH_CTRL_COMPLETE_IRQ            0
+#define BM_BCH_CTRL_COMPLETE_IRQ            0x1
+#define BF_BCH_CTRL_COMPLETE_IRQ(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_BCH_STATUS0
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_BCH_STATUS0                              (*(volatile unsigned long *)(REGS_BCH_BASE + 0x10))
+#define BP_BCH_STATUS0_HANDLE                       20
+#define BM_BCH_STATUS0_HANDLE                       0xfff00000
+#define BF_BCH_STATUS0_HANDLE(v)                    (((v) << 20) & 0xfff00000)
+#define BP_BCH_STATUS0_COMPLETED_CE                 16
+#define BM_BCH_STATUS0_COMPLETED_CE                 0xf0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v)              (((v) << 16) & 0xf0000)
+#define BP_BCH_STATUS0_STATUS_BLK0                  8
+#define BM_BCH_STATUS0_STATUS_BLK0                  0xff00
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO            0x0
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1          0x1
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2          0x2
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3          0x3
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4          0x4
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE   0xfe
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED          0xff
+#define BF_BCH_STATUS0_STATUS_BLK0(v)               (((v) << 8) & 0xff00)
+#define BF_BCH_STATUS0_STATUS_BLK0_V(v)             ((BV_BCH_STATUS0_STATUS_BLK0__##v << 8) & 0xff00)
+#define BP_BCH_STATUS0_RSVD1                        5
+#define BM_BCH_STATUS0_RSVD1                        0xe0
+#define BF_BCH_STATUS0_RSVD1(v)                     (((v) << 5) & 0xe0)
+#define BP_BCH_STATUS0_ALLONES                      4
+#define BM_BCH_STATUS0_ALLONES                      0x10
+#define BF_BCH_STATUS0_ALLONES(v)                   (((v) << 4) & 0x10)
+#define BP_BCH_STATUS0_CORRECTED                    3
+#define BM_BCH_STATUS0_CORRECTED                    0x8
+#define BF_BCH_STATUS0_CORRECTED(v)                 (((v) << 3) & 0x8)
+#define BP_BCH_STATUS0_UNCORRECTABLE                2
+#define BM_BCH_STATUS0_UNCORRECTABLE                0x4
+#define BF_BCH_STATUS0_UNCORRECTABLE(v)             (((v) << 2) & 0x4)
+#define BP_BCH_STATUS0_RSVD0                        0
+#define BM_BCH_STATUS0_RSVD0                        0x3
+#define BF_BCH_STATUS0_RSVD0(v)                     (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_BCH_MODE
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_BCH_MODE                     (*(volatile unsigned long *)(REGS_BCH_BASE + 0x20))
+#define BP_BCH_MODE_RSVD                8
+#define BM_BCH_MODE_RSVD                0xffffff00
+#define BF_BCH_MODE_RSVD(v)             (((v) << 8) & 0xffffff00)
+#define BP_BCH_MODE_ERASE_THRESHOLD     0
+#define BM_BCH_MODE_ERASE_THRESHOLD     0xff
+#define BF_BCH_MODE_ERASE_THRESHOLD(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_BCH_ENCODEPTR
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_BCH_ENCODEPTR            (*(volatile unsigned long *)(REGS_BCH_BASE + 0x30))
+#define BP_BCH_ENCODEPTR_ADDR       0
+#define BM_BCH_ENCODEPTR_ADDR       0xffffffff
+#define BF_BCH_ENCODEPTR_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_DATAPTR
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_BCH_DATAPTR          (*(volatile unsigned long *)(REGS_BCH_BASE + 0x40))
+#define BP_BCH_DATAPTR_ADDR     0
+#define BM_BCH_DATAPTR_ADDR     0xffffffff
+#define BF_BCH_DATAPTR_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_METAPTR
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_BCH_METAPTR          (*(volatile unsigned long *)(REGS_BCH_BASE + 0x50))
+#define BP_BCH_METAPTR_ADDR     0
+#define BM_BCH_METAPTR_ADDR     0xffffffff
+#define BF_BCH_METAPTR_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_LAYOUTSELECT
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_BCH_LAYOUTSELECT                 (*(volatile unsigned long *)(REGS_BCH_BASE + 0x70))
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT     30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT     0xc0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v)  (((v) << 30) & 0xc0000000)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT     28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT     0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v)  (((v) << 28) & 0x30000000)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT     26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT     0xc000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v)  (((v) << 26) & 0xc000000)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT     24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT     0x3000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v)  (((v) << 24) & 0x3000000)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT     22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT     0xc00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v)  (((v) << 22) & 0xc00000)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT     20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT     0x300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v)  (((v) << 20) & 0x300000)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT      18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT      0xc0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v)   (((v) << 18) & 0xc0000)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT      16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT      0x30000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v)   (((v) << 16) & 0x30000)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT      14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT      0xc000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v)   (((v) << 14) & 0xc000)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT      12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT      0x3000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v)   (((v) << 12) & 0x3000)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT      10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT      0xc00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v)   (((v) << 10) & 0xc00)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT      8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT      0x300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v)   (((v) << 8) & 0x300)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT      6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT      0xc0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v)   (((v) << 6) & 0xc0)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT      4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT      0x30
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v)   (((v) << 4) & 0x30)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT      2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT      0xc
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v)   (((v) << 2) & 0xc)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT      0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT      0x3
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v)   (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_BCH_FLASH0LAYOUT0
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_BCH_FLASH0LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0x80))
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS        24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS        0xff000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE      0xff0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
+#define BP_BCH_FLASH0LAYOUT0_ECC0           12
+#define BM_BCH_FLASH0LAYOUT0_ECC0           0xf000
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE     0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2     0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4     0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6     0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8     0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10    0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12    0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14    0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16    0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18    0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20    0xa
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH0LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH0LAYOUT0_ECC0__##v << 12) & 0xf000)
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE     0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE     0xfff
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_FLASH0LAYOUT1
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_BCH_FLASH0LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0x90))
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE      0xffff0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
+#define BP_BCH_FLASH0LAYOUT1_ECCN           12
+#define BM_BCH_FLASH0LAYOUT1_ECCN           0xf000
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE     0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2     0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4     0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6     0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8     0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10    0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12    0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14    0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16    0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18    0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20    0xa
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH0LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH0LAYOUT1_ECCN__##v << 12) & 0xf000)
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE     0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE     0xfff
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_FLASH1LAYOUT0
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_BCH_FLASH1LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xa0))
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS        24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS        0xff000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE      0xff0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
+#define BP_BCH_FLASH1LAYOUT0_ECC0           12
+#define BM_BCH_FLASH1LAYOUT0_ECC0           0xf000
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE     0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2     0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4     0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6     0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8     0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10    0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12    0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14    0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16    0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18    0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20    0xa
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH1LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH1LAYOUT0_ECC0__##v << 12) & 0xf000)
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE     0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE     0xfff
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_FLASH1LAYOUT1
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_BCH_FLASH1LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xb0))
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE      0xffff0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
+#define BP_BCH_FLASH1LAYOUT1_ECCN           12
+#define BM_BCH_FLASH1LAYOUT1_ECCN           0xf000
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE     0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2     0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4     0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6     0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8     0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10    0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12    0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14    0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16    0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18    0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20    0xa
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH1LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH1LAYOUT1_ECCN__##v << 12) & 0xf000)
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE     0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE     0xfff
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_FLASH2LAYOUT0
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_BCH_FLASH2LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xc0))
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS        24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS        0xff000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE      0xff0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
+#define BP_BCH_FLASH2LAYOUT0_ECC0           12
+#define BM_BCH_FLASH2LAYOUT0_ECC0           0xf000
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE     0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2     0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4     0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6     0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8     0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10    0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12    0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14    0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16    0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18    0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20    0xa
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH2LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH2LAYOUT0_ECC0__##v << 12) & 0xf000)
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE     0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE     0xfff
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_FLASH2LAYOUT1
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_BCH_FLASH2LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xd0))
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE      0xffff0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
+#define BP_BCH_FLASH2LAYOUT1_ECCN           12
+#define BM_BCH_FLASH2LAYOUT1_ECCN           0xf000
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE     0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2     0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4     0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6     0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8     0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10    0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12    0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14    0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16    0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18    0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20    0xa
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH2LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH2LAYOUT1_ECCN__##v << 12) & 0xf000)
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE     0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE     0xfff
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_FLASH3LAYOUT0
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_BCH_FLASH3LAYOUT0                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xe0))
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS        24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS        0xff000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v)     (((v) << 24) & 0xff000000)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE      16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE      0xff0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v)   (((v) << 16) & 0xff0000)
+#define BP_BCH_FLASH3LAYOUT0_ECC0           12
+#define BM_BCH_FLASH3LAYOUT0_ECC0           0xf000
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE     0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2     0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4     0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6     0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8     0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10    0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12    0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14    0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16    0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18    0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20    0xa
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH3LAYOUT0_ECC0_V(v)      ((BV_BCH_FLASH3LAYOUT0_ECC0__##v << 12) & 0xf000)
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE     0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE     0xfff
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_FLASH3LAYOUT1
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_BCH_FLASH3LAYOUT1                (*(volatile unsigned long *)(REGS_BCH_BASE + 0xf0))
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE      16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE      0xffff0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v)   (((v) << 16) & 0xffff0000)
+#define BP_BCH_FLASH3LAYOUT1_ECCN           12
+#define BM_BCH_FLASH3LAYOUT1_ECCN           0xf000
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE     0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2     0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4     0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6     0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8     0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10    0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12    0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14    0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16    0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18    0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20    0xa
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v)        (((v) << 12) & 0xf000)
+#define BF_BCH_FLASH3LAYOUT1_ECCN_V(v)      ((BV_BCH_FLASH3LAYOUT1_ECCN__##v << 12) & 0xf000)
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE     0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE     0xfff
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_BCH_DEBUG0
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_BCH_DEBUG0                                       (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x0))
+#define HW_BCH_DEBUG0_SET                                   (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x4))
+#define HW_BCH_DEBUG0_CLR                                   (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0x8))
+#define HW_BCH_DEBUG0_TOG                                   (*(volatile unsigned long *)(REGS_BCH_BASE + 0x100 + 0xc))
+#define BP_BCH_DEBUG0_RSVD1                                 27
+#define BM_BCH_DEBUG0_RSVD1                                 0xf8000000
+#define BF_BCH_DEBUG0_RSVD1(v)                              (((v) << 27) & 0xf8000000)
+#define BP_BCH_DEBUG0_ROM_BIST_ENABLE                       26
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE                       0x4000000
+#define BF_BCH_DEBUG0_ROM_BIST_ENABLE(v)                    (((v) << 26) & 0x4000000)
+#define BP_BCH_DEBUG0_ROM_BIST_COMPLETE                     25
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE                     0x2000000
+#define BF_BCH_DEBUG0_ROM_BIST_COMPLETE(v)                  (((v) << 25) & 0x2000000)
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL             16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL             0x1ff0000
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL     0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE  0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)          (((v) << 16) & 0x1ff0000)
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)        ((BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000)
+#define BP_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND                  15
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND                  0x8000
+#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v)               (((v) << 15) & 0x8000)
+#define BP_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG                14
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG                0x4000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA          0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX           0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)             (((v) << 14) & 0x4000)
+#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)           ((BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000)
+#define BP_BCH_DEBUG0_KES_DEBUG_MODE4K                      13
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K                      0x2000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k                  0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k                  0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K(v)                   (((v) << 13) & 0x2000)
+#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K_V(v)                 ((BV_BCH_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000)
+#define BP_BCH_DEBUG0_KES_DEBUG_KICK                        12
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK                        0x1000
+#define BF_BCH_DEBUG0_KES_DEBUG_KICK(v)                     (((v) << 12) & 0x1000)
+#define BP_BCH_DEBUG0_KES_STANDALONE                        11
+#define BM_BCH_DEBUG0_KES_STANDALONE                        0x800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL                0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE             0x1
+#define BF_BCH_DEBUG0_KES_STANDALONE(v)                     (((v) << 11) & 0x800)
+#define BF_BCH_DEBUG0_KES_STANDALONE_V(v)                   ((BV_BCH_DEBUG0_KES_STANDALONE__##v << 11) & 0x800)
+#define BP_BCH_DEBUG0_KES_DEBUG_STEP                        10
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP                        0x400
+#define BF_BCH_DEBUG0_KES_DEBUG_STEP(v)                     (((v) << 10) & 0x400)
+#define BP_BCH_DEBUG0_KES_DEBUG_STALL                       9
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL                       0x200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL               0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT                 0x1
+#define BF_BCH_DEBUG0_KES_DEBUG_STALL(v)                    (((v) << 9) & 0x200)
+#define BF_BCH_DEBUG0_KES_DEBUG_STALL_V(v)                  ((BV_BCH_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200)
+#define BP_BCH_DEBUG0_BM_KES_TEST_BYPASS                    8
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS                    0x100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL            0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE         0x1
+#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(v)                 (((v) << 8) & 0x100)
+#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS_V(v)               ((BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100)
+#define BP_BCH_DEBUG0_RSVD0                                 6
+#define BM_BCH_DEBUG0_RSVD0                                 0xc0
+#define BF_BCH_DEBUG0_RSVD0(v)                              (((v) << 6) & 0xc0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT                      0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT                      0x3f
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v)                   (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_BCH_DBGKESREAD
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_BCH_DBGKESREAD           (*(volatile unsigned long *)(REGS_BCH_BASE + 0x110))
+#define BP_BCH_DBGKESREAD_VALUES    0
+#define BM_BCH_DBGKESREAD_VALUES    0xffffffff
+#define BF_BCH_DBGKESREAD_VALUES(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_DBGCSFEREAD
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_BCH_DBGCSFEREAD              (*(volatile unsigned long *)(REGS_BCH_BASE + 0x120))
+#define BP_BCH_DBGCSFEREAD_VALUES       0
+#define BM_BCH_DBGCSFEREAD_VALUES       0xffffffff
+#define BF_BCH_DBGCSFEREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_DBGSYNDGENREAD
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_BCH_DBGSYNDGENREAD           (*(volatile unsigned long *)(REGS_BCH_BASE + 0x130))
+#define BP_BCH_DBGSYNDGENREAD_VALUES    0
+#define BM_BCH_DBGSYNDGENREAD_VALUES    0xffffffff
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_DBGAHBMREAD
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_BCH_DBGAHBMREAD              (*(volatile unsigned long *)(REGS_BCH_BASE + 0x140))
+#define BP_BCH_DBGAHBMREAD_VALUES       0
+#define BM_BCH_DBGAHBMREAD_VALUES       0xffffffff
+#define BF_BCH_DBGAHBMREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_BLOCKNAME
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_BCH_BLOCKNAME            (*(volatile unsigned long *)(REGS_BCH_BASE + 0x150))
+#define BP_BCH_BLOCKNAME_NAME       0
+#define BM_BCH_BLOCKNAME_NAME       0xffffffff
+#define BF_BCH_BLOCKNAME_NAME(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_BCH_VERSION
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_BCH_VERSION          (*(volatile unsigned long *)(REGS_BCH_BASE + 0x160))
+#define BP_BCH_VERSION_MAJOR    24
+#define BM_BCH_VERSION_MAJOR    0xff000000
+#define BF_BCH_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_BCH_VERSION_MINOR    16
+#define BM_BCH_VERSION_MINOR    0xff0000
+#define BF_BCH_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_BCH_VERSION_STEP     0
+#define BM_BCH_VERSION_STEP     0xffff
+#define BF_BCH_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__BCH__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h
new file mode 100644
index 0000000000..0dca5dbe62
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-clkctrl.h
@@ -0,0 +1,655 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__CLKCTRL__H__
+#define __HEADERGEN__IMX233__CLKCTRL__H__
+
+#define REGS_CLKCTRL_BASE (0x80040000)
+
+#define REGS_CLKCTRL_VERSION "3.2.0"
+
+/**
+ * Register: HW_CLKCTRL_PLLCTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_CLKCTRL_PLLCTRL0                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0))
+#define HW_CLKCTRL_PLLCTRL0_SET                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4))
+#define HW_CLKCTRL_PLLCTRL0_CLR                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8))
+#define HW_CLKCTRL_PLLCTRL0_TOG                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc))
+#define BP_CLKCTRL_PLLCTRL0_RSRVD6              30
+#define BM_CLKCTRL_PLLCTRL0_RSRVD6              0xc0000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v)           (((v) << 30) & 0xc0000000)
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL             28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL             0x30000000
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2    0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05   0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)          (((v) << 28) & 0x30000000)
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000)
+#define BP_CLKCTRL_PLLCTRL0_RSRVD5              26
+#define BM_CLKCTRL_PLLCTRL0_RSRVD5              0xc000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)           (((v) << 26) & 0xc000000)
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL              24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL              0x3000000
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT     0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2     0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05    0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED   0x3
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)           (((v) << 24) & 0x3000000)
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v)         ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000)
+#define BP_CLKCTRL_PLLCTRL0_RSRVD4              22
+#define BM_CLKCTRL_PLLCTRL0_RSRVD4              0xc00000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)           (((v) << 22) & 0xc00000)
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL             20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL             0x300000
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER      0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST     0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)          (((v) << 20) & 0x300000)
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000)
+#define BP_CLKCTRL_PLLCTRL0_RSRVD3              19
+#define BM_CLKCTRL_PLLCTRL0_RSRVD3              0x80000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD3(v)           (((v) << 19) & 0x80000)
+#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS         18
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS         0x40000
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)      (((v) << 18) & 0x40000)
+#define BP_CLKCTRL_PLLCTRL0_RSRVD2              17
+#define BM_CLKCTRL_PLLCTRL0_RSRVD2              0x20000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD2(v)           (((v) << 17) & 0x20000)
+#define BP_CLKCTRL_PLLCTRL0_POWER               16
+#define BM_CLKCTRL_PLLCTRL0_POWER               0x10000
+#define BF_CLKCTRL_PLLCTRL0_POWER(v)            (((v) << 16) & 0x10000)
+#define BP_CLKCTRL_PLLCTRL0_RSRVD1              0
+#define BM_CLKCTRL_PLLCTRL0_RSRVD1              0xffff
+#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)           (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_CLKCTRL_PLLCTRL1
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_CLKCTRL_PLLCTRL1                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10))
+#define BP_CLKCTRL_PLLCTRL1_LOCK            31
+#define BM_CLKCTRL_PLLCTRL1_LOCK            0x80000000
+#define BF_CLKCTRL_PLLCTRL1_LOCK(v)         (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK      30
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK      0x40000000
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)   (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_PLLCTRL1_RSRVD1          16
+#define BM_CLKCTRL_PLLCTRL1_RSRVD1          0x3fff0000
+#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)       (((v) << 16) & 0x3fff0000)
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT      0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT      0xffff
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_CLKCTRL_CPU
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_CLKCTRL_CPU                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0))
+#define HW_CLKCTRL_CPU_SET                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4))
+#define HW_CLKCTRL_CPU_CLR                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8))
+#define HW_CLKCTRL_CPU_TOG                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc))
+#define BP_CLKCTRL_CPU_RSRVD5               30
+#define BM_CLKCTRL_CPU_RSRVD5               0xc0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v)            (((v) << 30) & 0xc0000000)
+#define BP_CLKCTRL_CPU_BUSY_REF_XTAL        29
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL        0x20000000
+#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_CPU_BUSY_REF_CPU         28
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU         0x10000000
+#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v)      (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_CPU_RSRVD4               27
+#define BM_CLKCTRL_CPU_RSRVD4               0x8000000
+#define BF_CLKCTRL_CPU_RSRVD4(v)            (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     26
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     0x4000000
+#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)  (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_CPU_DIV_XTAL             16
+#define BM_CLKCTRL_CPU_DIV_XTAL             0x3ff0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)          (((v) << 16) & 0x3ff0000)
+#define BP_CLKCTRL_CPU_RSRVD3               13
+#define BM_CLKCTRL_CPU_RSRVD3               0xe000
+#define BF_CLKCTRL_CPU_RSRVD3(v)            (((v) << 13) & 0xe000)
+#define BP_CLKCTRL_CPU_INTERRUPT_WAIT       12
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT       0x1000
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)    (((v) << 12) & 0x1000)
+#define BP_CLKCTRL_CPU_RSRVD2               11
+#define BM_CLKCTRL_CPU_RSRVD2               0x800
+#define BF_CLKCTRL_CPU_RSRVD2(v)            (((v) << 11) & 0x800)
+#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN      10
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN      0x400
+#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)   (((v) << 10) & 0x400)
+#define BP_CLKCTRL_CPU_RSRVD1               6
+#define BM_CLKCTRL_CPU_RSRVD1               0x3c0
+#define BF_CLKCTRL_CPU_RSRVD1(v)            (((v) << 6) & 0x3c0)
+#define BP_CLKCTRL_CPU_DIV_CPU              0
+#define BM_CLKCTRL_CPU_DIV_CPU              0x3f
+#define BF_CLKCTRL_CPU_DIV_CPU(v)           (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_CLKCTRL_HBUS
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_CLKCTRL_HBUS                             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0))
+#define HW_CLKCTRL_HBUS_SET                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4))
+#define HW_CLKCTRL_HBUS_CLR                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8))
+#define HW_CLKCTRL_HBUS_TOG                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc))
+#define BP_CLKCTRL_HBUS_RSRVD4                      30
+#define BM_CLKCTRL_HBUS_RSRVD4                      0xc0000000
+#define BF_CLKCTRL_HBUS_RSRVD4(v)                   (((v) << 30) & 0xc0000000)
+#define BP_CLKCTRL_HBUS_BUSY                        29
+#define BM_CLKCTRL_HBUS_BUSY                        0x20000000
+#define BF_CLKCTRL_HBUS_BUSY(v)                     (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_HBUS_DCP_AS_ENABLE               28
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE               0x10000000
+#define BF_CLKCTRL_HBUS_DCP_AS_ENABLE(v)            (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_HBUS_PXP_AS_ENABLE               27
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE               0x8000000
+#define BF_CLKCTRL_HBUS_PXP_AS_ENABLE(v)            (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           26
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           0x4000000
+#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)        (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           25
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           0x2000000
+#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)        (((v) << 25) & 0x2000000)
+#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       24
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       0x1000000
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)    (((v) << 24) & 0x1000000)
+#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           23
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           0x800000
+#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)        (((v) << 23) & 0x800000)
+#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          22
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          0x400000
+#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)       (((v) << 22) & 0x400000)
+#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         21
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         0x200000
+#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)      (((v) << 21) & 0x200000)
+#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE              20
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE              0x100000
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)           (((v) << 20) & 0x100000)
+#define BP_CLKCTRL_HBUS_RSRVD2                      19
+#define BM_CLKCTRL_HBUS_RSRVD2                      0x80000
+#define BF_CLKCTRL_HBUS_RSRVD2(v)                   (((v) << 19) & 0x80000)
+#define BP_CLKCTRL_HBUS_SLOW_DIV                    16
+#define BM_CLKCTRL_HBUS_SLOW_DIV                    0x70000
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1               0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2               0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4               0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8               0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16              0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32              0x5
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)                 (((v) << 16) & 0x70000)
+#define BF_CLKCTRL_HBUS_SLOW_DIV_V(v)               ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000)
+#define BP_CLKCTRL_HBUS_RSRVD1                      6
+#define BM_CLKCTRL_HBUS_RSRVD1                      0xffc0
+#define BF_CLKCTRL_HBUS_RSRVD1(v)                   (((v) << 6) & 0xffc0)
+#define BP_CLKCTRL_HBUS_DIV_FRAC_EN                 5
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN                 0x20
+#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v)              (((v) << 5) & 0x20)
+#define BP_CLKCTRL_HBUS_DIV                         0
+#define BM_CLKCTRL_HBUS_DIV                         0x1f
+#define BF_CLKCTRL_HBUS_DIV(v)                      (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_CLKCTRL_XBUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_CLKCTRL_XBUS                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40))
+#define BP_CLKCTRL_XBUS_BUSY            31
+#define BM_CLKCTRL_XBUS_BUSY            0x80000000
+#define BF_CLKCTRL_XBUS_BUSY(v)         (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_XBUS_RSRVD1          11
+#define BM_CLKCTRL_XBUS_RSRVD1          0x7ffff800
+#define BF_CLKCTRL_XBUS_RSRVD1(v)       (((v) << 11) & 0x7ffff800)
+#define BP_CLKCTRL_XBUS_DIV_FRAC_EN     10
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x400
+#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
+#define BP_CLKCTRL_XBUS_DIV             0
+#define BM_CLKCTRL_XBUS_DIV             0x3ff
+#define BF_CLKCTRL_XBUS_DIV(v)          (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_XTAL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_CLKCTRL_XTAL                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0))
+#define HW_CLKCTRL_XTAL_SET                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4))
+#define HW_CLKCTRL_XTAL_CLR                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8))
+#define HW_CLKCTRL_XTAL_TOG                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc))
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE           31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE           0x80000000
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)        (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)     (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE         29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE         0x20000000
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)      (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE         28
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE         0x10000000
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)      (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      27
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x8000000
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)   (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x4000000
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)   (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_XTAL_RSRVD1                  2
+#define BM_CLKCTRL_XTAL_RSRVD1                  0x3fffffc
+#define BF_CLKCTRL_XTAL_RSRVD1(v)               (((v) << 2) & 0x3fffffc)
+#define BP_CLKCTRL_XTAL_DIV_UART                0
+#define BM_CLKCTRL_XTAL_DIV_UART                0x3
+#define BF_CLKCTRL_XTAL_DIV_UART(v)             (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_CLKCTRL_PIX
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_CLKCTRL_PIX                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60))
+#define BP_CLKCTRL_PIX_CLKGATE          31
+#define BM_CLKCTRL_PIX_CLKGATE          0x80000000
+#define BF_CLKCTRL_PIX_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_PIX_RSRVD2           30
+#define BM_CLKCTRL_PIX_RSRVD2           0x40000000
+#define BF_CLKCTRL_PIX_RSRVD2(v)        (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_PIX_BUSY             29
+#define BM_CLKCTRL_PIX_BUSY             0x20000000
+#define BF_CLKCTRL_PIX_BUSY(v)          (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_PIX_RSRVD1           13
+#define BM_CLKCTRL_PIX_RSRVD1           0x1fffe000
+#define BF_CLKCTRL_PIX_RSRVD1(v)        (((v) << 13) & 0x1fffe000)
+#define BP_CLKCTRL_PIX_DIV_FRAC_EN      12
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x1000
+#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v)   (((v) << 12) & 0x1000)
+#define BP_CLKCTRL_PIX_DIV              0
+#define BM_CLKCTRL_PIX_DIV              0xfff
+#define BF_CLKCTRL_PIX_DIV(v)           (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_CLKCTRL_SSP
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_CLKCTRL_SSP                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70))
+#define BP_CLKCTRL_SSP_CLKGATE          31
+#define BM_CLKCTRL_SSP_CLKGATE          0x80000000
+#define BF_CLKCTRL_SSP_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_SSP_RSRVD2           30
+#define BM_CLKCTRL_SSP_RSRVD2           0x40000000
+#define BF_CLKCTRL_SSP_RSRVD2(v)        (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_SSP_BUSY             29
+#define BM_CLKCTRL_SSP_BUSY             0x20000000
+#define BF_CLKCTRL_SSP_BUSY(v)          (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_SSP_RSRVD1           10
+#define BM_CLKCTRL_SSP_RSRVD1           0x1ffffc00
+#define BF_CLKCTRL_SSP_RSRVD1(v)        (((v) << 10) & 0x1ffffc00)
+#define BP_CLKCTRL_SSP_DIV_FRAC_EN      9
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x200
+#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v)   (((v) << 9) & 0x200)
+#define BP_CLKCTRL_SSP_DIV              0
+#define BM_CLKCTRL_SSP_DIV              0x1ff
+#define BF_CLKCTRL_SSP_DIV(v)           (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_CLKCTRL_GPMI
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_CLKCTRL_GPMI                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80))
+#define BP_CLKCTRL_GPMI_CLKGATE         31
+#define BM_CLKCTRL_GPMI_CLKGATE         0x80000000
+#define BF_CLKCTRL_GPMI_CLKGATE(v)      (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_GPMI_RSRVD2          30
+#define BM_CLKCTRL_GPMI_RSRVD2          0x40000000
+#define BF_CLKCTRL_GPMI_RSRVD2(v)       (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_GPMI_BUSY            29
+#define BM_CLKCTRL_GPMI_BUSY            0x20000000
+#define BF_CLKCTRL_GPMI_BUSY(v)         (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_GPMI_RSRVD1          11
+#define BM_CLKCTRL_GPMI_RSRVD1          0x1ffff800
+#define BF_CLKCTRL_GPMI_RSRVD1(v)       (((v) << 11) & 0x1ffff800)
+#define BP_CLKCTRL_GPMI_DIV_FRAC_EN     10
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x400
+#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
+#define BP_CLKCTRL_GPMI_DIV             0
+#define BM_CLKCTRL_GPMI_DIV             0x3ff
+#define BF_CLKCTRL_GPMI_DIV(v)          (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_SPDIF
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_CLKCTRL_SPDIF            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90))
+#define BP_CLKCTRL_SPDIF_CLKGATE    31
+#define BM_CLKCTRL_SPDIF_CLKGATE    0x80000000
+#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_SPDIF_RSRVD      0
+#define BM_CLKCTRL_SPDIF_RSRVD      0x7fffffff
+#define BF_CLKCTRL_SPDIF_RSRVD(v)   (((v) << 0) & 0x7fffffff)
+
+/**
+ * Register: HW_CLKCTRL_EMI
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_CLKCTRL_EMI                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0))
+#define BP_CLKCTRL_EMI_CLKGATE              31
+#define BM_CLKCTRL_EMI_CLKGATE              0x80000000
+#define BF_CLKCTRL_EMI_CLKGATE(v)           (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_EMI_SYNC_MODE_EN         30
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN         0x40000000
+#define BF_CLKCTRL_EMI_SYNC_MODE_EN(v)      (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_EMI_BUSY_REF_XTAL        29
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL        0x20000000
+#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_EMI_BUSY_REF_EMI         28
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI         0x10000000
+#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v)      (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_EMI_BUSY_REF_CPU         27
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU         0x8000000
+#define BF_CLKCTRL_EMI_BUSY_REF_CPU(v)      (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_EMI_BUSY_SYNC_MODE       26
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE       0x4000000
+#define BF_CLKCTRL_EMI_BUSY_SYNC_MODE(v)    (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_EMI_RSRVD3               18
+#define BM_CLKCTRL_EMI_RSRVD3               0x3fc0000
+#define BF_CLKCTRL_EMI_RSRVD3(v)            (((v) << 18) & 0x3fc0000)
+#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC      17
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC      0x20000
+#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)   (((v) << 17) & 0x20000)
+#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE    16
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE    0x10000
+#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000)
+#define BP_CLKCTRL_EMI_RSRVD2               12
+#define BM_CLKCTRL_EMI_RSRVD2               0xf000
+#define BF_CLKCTRL_EMI_RSRVD2(v)            (((v) << 12) & 0xf000)
+#define BP_CLKCTRL_EMI_DIV_XTAL             8
+#define BM_CLKCTRL_EMI_DIV_XTAL             0xf00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)          (((v) << 8) & 0xf00)
+#define BP_CLKCTRL_EMI_RSRVD1               6
+#define BM_CLKCTRL_EMI_RSRVD1               0xc0
+#define BF_CLKCTRL_EMI_RSRVD1(v)            (((v) << 6) & 0xc0)
+#define BP_CLKCTRL_EMI_DIV_EMI              0
+#define BM_CLKCTRL_EMI_DIV_EMI              0x3f
+#define BF_CLKCTRL_EMI_DIV_EMI(v)           (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_CLKCTRL_IR
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_CLKCTRL_IR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0))
+#define BP_CLKCTRL_IR_CLKGATE       31
+#define BM_CLKCTRL_IR_CLKGATE       0x80000000
+#define BF_CLKCTRL_IR_CLKGATE(v)    (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_IR_RSRVD3        30
+#define BM_CLKCTRL_IR_RSRVD3        0x40000000
+#define BF_CLKCTRL_IR_RSRVD3(v)     (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_IR_AUTO_DIV      29
+#define BM_CLKCTRL_IR_AUTO_DIV      0x20000000
+#define BF_CLKCTRL_IR_AUTO_DIV(v)   (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_IR_IR_BUSY       28
+#define BM_CLKCTRL_IR_IR_BUSY       0x10000000
+#define BF_CLKCTRL_IR_IR_BUSY(v)    (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_IR_IROV_BUSY     27
+#define BM_CLKCTRL_IR_IROV_BUSY     0x8000000
+#define BF_CLKCTRL_IR_IROV_BUSY(v)  (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_IR_RSRVD2        25
+#define BM_CLKCTRL_IR_RSRVD2        0x6000000
+#define BF_CLKCTRL_IR_RSRVD2(v)     (((v) << 25) & 0x6000000)
+#define BP_CLKCTRL_IR_IROV_DIV      16
+#define BM_CLKCTRL_IR_IROV_DIV      0x1ff0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)   (((v) << 16) & 0x1ff0000)
+#define BP_CLKCTRL_IR_RSRVD1        10
+#define BM_CLKCTRL_IR_RSRVD1        0xfc00
+#define BF_CLKCTRL_IR_RSRVD1(v)     (((v) << 10) & 0xfc00)
+#define BP_CLKCTRL_IR_IR_DIV        0
+#define BM_CLKCTRL_IR_IR_DIV        0x3ff
+#define BF_CLKCTRL_IR_IR_DIV(v)     (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_SAIF
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_CLKCTRL_SAIF                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0))
+#define BP_CLKCTRL_SAIF_CLKGATE         31
+#define BM_CLKCTRL_SAIF_CLKGATE         0x80000000
+#define BF_CLKCTRL_SAIF_CLKGATE(v)      (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_SAIF_RSRVD2          30
+#define BM_CLKCTRL_SAIF_RSRVD2          0x40000000
+#define BF_CLKCTRL_SAIF_RSRVD2(v)       (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_SAIF_BUSY            29
+#define BM_CLKCTRL_SAIF_BUSY            0x20000000
+#define BF_CLKCTRL_SAIF_BUSY(v)         (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_SAIF_RSRVD1          17
+#define BM_CLKCTRL_SAIF_RSRVD1          0x1ffe0000
+#define BF_CLKCTRL_SAIF_RSRVD1(v)       (((v) << 17) & 0x1ffe0000)
+#define BP_CLKCTRL_SAIF_DIV_FRAC_EN     16
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x10000
+#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v)  (((v) << 16) & 0x10000)
+#define BP_CLKCTRL_SAIF_DIV             0
+#define BM_CLKCTRL_SAIF_DIV             0xffff
+#define BF_CLKCTRL_SAIF_DIV(v)          (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_CLKCTRL_TV
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_CLKCTRL_TV                       (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0))
+#define BP_CLKCTRL_TV_CLK_TV108M_GATE       31
+#define BM_CLKCTRL_TV_CLK_TV108M_GATE       0x80000000
+#define BF_CLKCTRL_TV_CLK_TV108M_GATE(v)    (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_TV_CLK_TV_GATE           30
+#define BM_CLKCTRL_TV_CLK_TV_GATE           0x40000000
+#define BF_CLKCTRL_TV_CLK_TV_GATE(v)        (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_TV_RSRVD                 0
+#define BM_CLKCTRL_TV_RSRVD                 0x3fffffff
+#define BF_CLKCTRL_TV_RSRVD(v)              (((v) << 0) & 0x3fffffff)
+
+/**
+ * Register: HW_CLKCTRL_ETM
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_CLKCTRL_ETM                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0))
+#define BP_CLKCTRL_ETM_CLKGATE          31
+#define BM_CLKCTRL_ETM_CLKGATE          0x80000000
+#define BF_CLKCTRL_ETM_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_ETM_RSRVD2           30
+#define BM_CLKCTRL_ETM_RSRVD2           0x40000000
+#define BF_CLKCTRL_ETM_RSRVD2(v)        (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_ETM_BUSY             29
+#define BM_CLKCTRL_ETM_BUSY             0x20000000
+#define BF_CLKCTRL_ETM_BUSY(v)          (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_ETM_RSRVD1           7
+#define BM_CLKCTRL_ETM_RSRVD1           0x1fffff80
+#define BF_CLKCTRL_ETM_RSRVD1(v)        (((v) << 7) & 0x1fffff80)
+#define BP_CLKCTRL_ETM_DIV_FRAC_EN      6
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x40
+#define BF_CLKCTRL_ETM_DIV_FRAC_EN(v)   (((v) << 6) & 0x40)
+#define BP_CLKCTRL_ETM_DIV              0
+#define BM_CLKCTRL_ETM_DIV              0x3f
+#define BF_CLKCTRL_ETM_DIV(v)           (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_CLKCTRL_FRAC
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_CLKCTRL_FRAC                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x0))
+#define HW_CLKCTRL_FRAC_SET             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x4))
+#define HW_CLKCTRL_FRAC_CLR             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0x8))
+#define HW_CLKCTRL_FRAC_TOG             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0 + 0xc))
+#define BP_CLKCTRL_FRAC_CLKGATEIO       31
+#define BM_CLKCTRL_FRAC_CLKGATEIO       0x80000000
+#define BF_CLKCTRL_FRAC_CLKGATEIO(v)    (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_FRAC_IO_STABLE       30
+#define BM_CLKCTRL_FRAC_IO_STABLE       0x40000000
+#define BF_CLKCTRL_FRAC_IO_STABLE(v)    (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_FRAC_IOFRAC          24
+#define BM_CLKCTRL_FRAC_IOFRAC          0x3f000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v)       (((v) << 24) & 0x3f000000)
+#define BP_CLKCTRL_FRAC_CLKGATEPIX      23
+#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x800000
+#define BF_CLKCTRL_FRAC_CLKGATEPIX(v)   (((v) << 23) & 0x800000)
+#define BP_CLKCTRL_FRAC_PIX_STABLE      22
+#define BM_CLKCTRL_FRAC_PIX_STABLE      0x400000
+#define BF_CLKCTRL_FRAC_PIX_STABLE(v)   (((v) << 22) & 0x400000)
+#define BP_CLKCTRL_FRAC_PIXFRAC         16
+#define BM_CLKCTRL_FRAC_PIXFRAC         0x3f0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v)      (((v) << 16) & 0x3f0000)
+#define BP_CLKCTRL_FRAC_CLKGATEEMI      15
+#define BM_CLKCTRL_FRAC_CLKGATEEMI      0x8000
+#define BF_CLKCTRL_FRAC_CLKGATEEMI(v)   (((v) << 15) & 0x8000)
+#define BP_CLKCTRL_FRAC_EMI_STABLE      14
+#define BM_CLKCTRL_FRAC_EMI_STABLE      0x4000
+#define BF_CLKCTRL_FRAC_EMI_STABLE(v)   (((v) << 14) & 0x4000)
+#define BP_CLKCTRL_FRAC_EMIFRAC         8
+#define BM_CLKCTRL_FRAC_EMIFRAC         0x3f00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v)      (((v) << 8) & 0x3f00)
+#define BP_CLKCTRL_FRAC_CLKGATECPU      7
+#define BM_CLKCTRL_FRAC_CLKGATECPU      0x80
+#define BF_CLKCTRL_FRAC_CLKGATECPU(v)   (((v) << 7) & 0x80)
+#define BP_CLKCTRL_FRAC_CPU_STABLE      6
+#define BM_CLKCTRL_FRAC_CPU_STABLE      0x40
+#define BF_CLKCTRL_FRAC_CPU_STABLE(v)   (((v) << 6) & 0x40)
+#define BP_CLKCTRL_FRAC_CPUFRAC         0
+#define BM_CLKCTRL_FRAC_CPUFRAC         0x3f
+#define BF_CLKCTRL_FRAC_CPUFRAC(v)      (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_CLKCTRL_FRAC1
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_CLKCTRL_FRAC1                (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x0))
+#define HW_CLKCTRL_FRAC1_SET            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x4))
+#define HW_CLKCTRL_FRAC1_CLR            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0x8))
+#define HW_CLKCTRL_FRAC1_TOG            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100 + 0xc))
+#define BP_CLKCTRL_FRAC1_CLKGATEVID     31
+#define BM_CLKCTRL_FRAC1_CLKGATEVID     0x80000000
+#define BF_CLKCTRL_FRAC1_CLKGATEVID(v)  (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_FRAC1_VID_STABLE     30
+#define BM_CLKCTRL_FRAC1_VID_STABLE     0x40000000
+#define BF_CLKCTRL_FRAC1_VID_STABLE(v)  (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_FRAC1_RSRVD1         0
+#define BM_CLKCTRL_FRAC1_RSRVD1         0x3fffffff
+#define BF_CLKCTRL_FRAC1_RSRVD1(v)      (((v) << 0) & 0x3fffffff)
+
+/**
+ * Register: HW_CLKCTRL_CLKSEQ
+ * Address: 0x110
+ * SCT: yes
+*/
+#define HW_CLKCTRL_CLKSEQ                   (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x0))
+#define HW_CLKCTRL_CLKSEQ_SET               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x4))
+#define HW_CLKCTRL_CLKSEQ_CLR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0x8))
+#define HW_CLKCTRL_CLKSEQ_TOG               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x110 + 0xc))
+#define BP_CLKCTRL_CLKSEQ_RSRVD1            9
+#define BM_CLKCTRL_CLKSEQ_RSRVD1            0xfffffe00
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v)         (((v) << 9) & 0xfffffe00)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_ETM        8
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM        0x100
+#define BF_CLKCTRL_CLKSEQ_BYPASS_ETM(v)     (((v) << 8) & 0x100)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU        7
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU        0x80
+#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v)     (((v) << 7) & 0x80)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI        6
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI        0x40
+#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v)     (((v) << 6) & 0x40)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP        5
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP        0x20
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v)     (((v) << 5) & 0x20)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI       4
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI       0x10
+#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)    (((v) << 4) & 0x10)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_IR         3
+#define BM_CLKCTRL_CLKSEQ_BYPASS_IR         0x8
+#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v)      (((v) << 3) & 0x8)
+#define BP_CLKCTRL_CLKSEQ_RSRVD0            2
+#define BM_CLKCTRL_CLKSEQ_RSRVD0            0x4
+#define BF_CLKCTRL_CLKSEQ_RSRVD0(v)         (((v) << 2) & 0x4)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX        1
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX        0x2
+#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v)     (((v) << 1) & 0x2)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF       0
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF       0x1
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_CLKCTRL_RESET
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_CLKCTRL_RESET            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x120))
+#define BP_CLKCTRL_RESET_RSRVD      2
+#define BM_CLKCTRL_RESET_RSRVD      0xfffffffc
+#define BF_CLKCTRL_RESET_RSRVD(v)   (((v) << 2) & 0xfffffffc)
+#define BP_CLKCTRL_RESET_CHIP       1
+#define BM_CLKCTRL_RESET_CHIP       0x2
+#define BF_CLKCTRL_RESET_CHIP(v)    (((v) << 1) & 0x2)
+#define BP_CLKCTRL_RESET_DIG        0
+#define BM_CLKCTRL_RESET_DIG        0x1
+#define BF_CLKCTRL_RESET_DIG(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_CLKCTRL_STATUS
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_CLKCTRL_STATUS               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x130))
+#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xc0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v)  (((v) << 30) & 0xc0000000)
+#define BP_CLKCTRL_STATUS_RSRVD         0
+#define BM_CLKCTRL_STATUS_RSRVD         0x3fffffff
+#define BF_CLKCTRL_STATUS_RSRVD(v)      (((v) << 0) & 0x3fffffff)
+
+/**
+ * Register: HW_CLKCTRL_VERSION
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_CLKCTRL_VERSION          (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x140))
+#define BP_CLKCTRL_VERSION_MAJOR    24
+#define BM_CLKCTRL_VERSION_MAJOR    0xff000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_CLKCTRL_VERSION_MINOR    16
+#define BM_CLKCTRL_VERSION_MINOR    0xff0000
+#define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_CLKCTRL_VERSION_STEP     0
+#define BM_CLKCTRL_VERSION_STEP     0xffff
+#define BF_CLKCTRL_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dcp.h b/firmware/target/arm/imx233/regs/imx233/regs-dcp.h
new file mode 100644
index 0000000000..9428f97898
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-dcp.h
@@ -0,0 +1,851 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__DCP__H__
+#define __HEADERGEN__IMX233__DCP__H__
+
+#define REGS_DCP_BASE (0x80028000)
+
+#define REGS_DCP_VERSION "3.2.0"
+
+/**
+ * Register: HW_DCP_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DCP_CTRL                                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0))
+#define HW_DCP_CTRL_SET                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4))
+#define HW_DCP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8))
+#define HW_DCP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc))
+#define BP_DCP_CTRL_SFTRST                          31
+#define BM_DCP_CTRL_SFTRST                          0x80000000
+#define BF_DCP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
+#define BP_DCP_CTRL_CLKGATE                         30
+#define BM_DCP_CTRL_CLKGATE                         0x40000000
+#define BF_DCP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
+#define BP_DCP_CTRL_PRESENT_CRYPTO                  29
+#define BM_DCP_CTRL_PRESENT_CRYPTO                  0x20000000
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Present         0x1
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent          0x0
+#define BF_DCP_CTRL_PRESENT_CRYPTO(v)               (((v) << 29) & 0x20000000)
+#define BF_DCP_CTRL_PRESENT_CRYPTO_V(v)             ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000)
+#define BP_DCP_CTRL_PRESENT_CSC                     28
+#define BM_DCP_CTRL_PRESENT_CSC                     0x10000000
+#define BV_DCP_CTRL_PRESENT_CSC__Present            0x1
+#define BV_DCP_CTRL_PRESENT_CSC__Absent             0x0
+#define BF_DCP_CTRL_PRESENT_CSC(v)                  (((v) << 28) & 0x10000000)
+#define BF_DCP_CTRL_PRESENT_CSC_V(v)                ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000)
+#define BP_DCP_CTRL_RSVD1                           24
+#define BM_DCP_CTRL_RSVD1                           0xf000000
+#define BF_DCP_CTRL_RSVD1(v)                        (((v) << 24) & 0xf000000)
+#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES          23
+#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES          0x800000
+#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)       (((v) << 23) & 0x800000)
+#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING          22
+#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING          0x400000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)       (((v) << 22) & 0x400000)
+#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        21
+#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        0x200000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)     (((v) << 21) & 0x200000)
+#define BP_DCP_CTRL_RSVD0                           9
+#define BM_DCP_CTRL_RSVD0                           0x1ffe00
+#define BF_DCP_CTRL_RSVD0(v)                        (((v) << 9) & 0x1ffe00)
+#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE            8
+#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE            0x100
+#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)         (((v) << 8) & 0x100)
+#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0
+#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0xff
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0   0x1
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1   0x2
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2   0x4
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3   0x8
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)     (((v) << 0) & 0xff)
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v)   ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_DCP_STAT                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0))
+#define HW_DCP_STAT_SET                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4))
+#define HW_DCP_STAT_CLR                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8))
+#define HW_DCP_STAT_TOG                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc))
+#define BP_DCP_STAT_RSVD2               29
+#define BM_DCP_STAT_RSVD2               0xe0000000
+#define BF_DCP_STAT_RSVD2(v)            (((v) << 29) & 0xe0000000)
+#define BP_DCP_STAT_OTP_KEY_READY       28
+#define BM_DCP_STAT_OTP_KEY_READY       0x10000000
+#define BF_DCP_STAT_OTP_KEY_READY(v)    (((v) << 28) & 0x10000000)
+#define BP_DCP_STAT_CUR_CHANNEL         24
+#define BM_DCP_STAT_CUR_CHANNEL         0xf000000
+#define BV_DCP_STAT_CUR_CHANNEL__None   0x0
+#define BV_DCP_STAT_CUR_CHANNEL__CH0    0x1
+#define BV_DCP_STAT_CUR_CHANNEL__CH1    0x2
+#define BV_DCP_STAT_CUR_CHANNEL__CH2    0x3
+#define BV_DCP_STAT_CUR_CHANNEL__CH3    0x4
+#define BV_DCP_STAT_CUR_CHANNEL__CSC    0x8
+#define BF_DCP_STAT_CUR_CHANNEL(v)      (((v) << 24) & 0xf000000)
+#define BF_DCP_STAT_CUR_CHANNEL_V(v)    ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000)
+#define BP_DCP_STAT_READY_CHANNELS      16
+#define BM_DCP_STAT_READY_CHANNELS      0xff0000
+#define BV_DCP_STAT_READY_CHANNELS__CH0 0x1
+#define BV_DCP_STAT_READY_CHANNELS__CH1 0x2
+#define BV_DCP_STAT_READY_CHANNELS__CH2 0x4
+#define BV_DCP_STAT_READY_CHANNELS__CH3 0x8
+#define BF_DCP_STAT_READY_CHANNELS(v)   (((v) << 16) & 0xff0000)
+#define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000)
+#define BP_DCP_STAT_RSVD1               9
+#define BM_DCP_STAT_RSVD1               0xfe00
+#define BF_DCP_STAT_RSVD1(v)            (((v) << 9) & 0xfe00)
+#define BP_DCP_STAT_CSCIRQ              8
+#define BM_DCP_STAT_CSCIRQ              0x100
+#define BF_DCP_STAT_CSCIRQ(v)           (((v) << 8) & 0x100)
+#define BP_DCP_STAT_RSVD0               4
+#define BM_DCP_STAT_RSVD0               0xf0
+#define BF_DCP_STAT_RSVD0(v)            (((v) << 4) & 0xf0)
+#define BP_DCP_STAT_IRQ                 0
+#define BM_DCP_STAT_IRQ                 0xf
+#define BF_DCP_STAT_IRQ(v)              (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DCP_CHANNELCTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_DCP_CHANNELCTRL                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0))
+#define HW_DCP_CHANNELCTRL_SET                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4))
+#define HW_DCP_CHANNELCTRL_CLR                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8))
+#define HW_DCP_CHANNELCTRL_TOG                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc))
+#define BP_DCP_CHANNELCTRL_RSVD                         19
+#define BM_DCP_CHANNELCTRL_RSVD                         0xfff80000
+#define BF_DCP_CHANNELCTRL_RSVD(v)                      (((v) << 19) & 0xfff80000)
+#define BP_DCP_CHANNELCTRL_CSC_PRIORITY                 17
+#define BM_DCP_CHANNELCTRL_CSC_PRIORITY                 0x60000
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH           0x3
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED            0x2
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW            0x1
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND     0x0
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)              (((v) << 17) & 0x60000)
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v)            ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000)
+#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED               16
+#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED               0x10000
+#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)            (((v) << 16) & 0x10000)
+#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        8
+#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        0xff00
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0   0x1
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1   0x2
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2   0x4
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3   0x8
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)     (((v) << 8) & 0xff00)
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v)   ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00)
+#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL               0
+#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL               0xff
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0          0x1
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1          0x2
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2          0x4
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3          0x8
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)            (((v) << 0) & 0xff)
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v)          ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CAPABILITY0
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_DCP_CAPABILITY0                      (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30))
+#define BP_DCP_CAPABILITY0_DISABLE_DECRYPT      31
+#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT      0x80000000
+#define BF_DCP_CAPABILITY0_DISABLE_DECRYPT(v)   (((v) << 31) & 0x80000000)
+#define BP_DCP_CAPABILITY0_ENABLE_TZONE         30
+#define BM_DCP_CAPABILITY0_ENABLE_TZONE         0x40000000
+#define BF_DCP_CAPABILITY0_ENABLE_TZONE(v)      (((v) << 30) & 0x40000000)
+#define BP_DCP_CAPABILITY0_RSVD                 12
+#define BM_DCP_CAPABILITY0_RSVD                 0x3ffff000
+#define BF_DCP_CAPABILITY0_RSVD(v)              (((v) << 12) & 0x3ffff000)
+#define BP_DCP_CAPABILITY0_NUM_CHANNELS         8
+#define BM_DCP_CAPABILITY0_NUM_CHANNELS         0xf00
+#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)      (((v) << 8) & 0xf00)
+#define BP_DCP_CAPABILITY0_NUM_KEYS             0
+#define BM_DCP_CAPABILITY0_NUM_KEYS             0xff
+#define BF_DCP_CAPABILITY0_NUM_KEYS(v)          (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CAPABILITY1
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_DCP_CAPABILITY1                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40))
+#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS              16
+#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS              0xffff0000
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1        0x1
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32       0x2
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v)           (((v) << 16) & 0xffff0000)
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v)         ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000)
+#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0
+#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0xffff
+#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128    0x1
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)         (((v) << 0) & 0xffff)
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v)       ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff)
+
+/**
+ * Register: HW_DCP_CONTEXT
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_DCP_CONTEXT          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50))
+#define BP_DCP_CONTEXT_ADDR     0
+#define BM_DCP_CONTEXT_ADDR     0xffffffff
+#define BF_DCP_CONTEXT_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_KEY
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DCP_KEY                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60))
+#define BP_DCP_KEY_RSVD             8
+#define BM_DCP_KEY_RSVD             0xffffff00
+#define BF_DCP_KEY_RSVD(v)          (((v) << 8) & 0xffffff00)
+#define BP_DCP_KEY_RSVD_INDEX       6
+#define BM_DCP_KEY_RSVD_INDEX       0xc0
+#define BF_DCP_KEY_RSVD_INDEX(v)    (((v) << 6) & 0xc0)
+#define BP_DCP_KEY_INDEX            4
+#define BM_DCP_KEY_INDEX            0x30
+#define BF_DCP_KEY_INDEX(v)         (((v) << 4) & 0x30)
+#define BP_DCP_KEY_RSVD_SUBWORD     2
+#define BM_DCP_KEY_RSVD_SUBWORD     0xc
+#define BF_DCP_KEY_RSVD_SUBWORD(v)  (((v) << 2) & 0xc)
+#define BP_DCP_KEY_SUBWORD          0
+#define BM_DCP_KEY_SUBWORD          0x3
+#define BF_DCP_KEY_SUBWORD(v)       (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DCP_KEYDATA
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_DCP_KEYDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70))
+#define BP_DCP_KEYDATA_DATA     0
+#define BM_DCP_KEYDATA_DATA     0xffffffff
+#define BF_DCP_KEYDATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET0
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_DCP_PACKET0          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80))
+#define BP_DCP_PACKET0_ADDR     0
+#define BM_DCP_PACKET0_ADDR     0xffffffff
+#define BF_DCP_PACKET0_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET1
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DCP_PACKET1                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90))
+#define BP_DCP_PACKET1_TAG                      24
+#define BM_DCP_PACKET1_TAG                      0xff000000
+#define BF_DCP_PACKET1_TAG(v)                   (((v) << 24) & 0xff000000)
+#define BP_DCP_PACKET1_OUTPUT_WORDSWAP          23
+#define BM_DCP_PACKET1_OUTPUT_WORDSWAP          0x800000
+#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v)       (((v) << 23) & 0x800000)
+#define BP_DCP_PACKET1_OUTPUT_BYTESWAP          22
+#define BM_DCP_PACKET1_OUTPUT_BYTESWAP          0x400000
+#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v)       (((v) << 22) & 0x400000)
+#define BP_DCP_PACKET1_INPUT_WORDSWAP           21
+#define BM_DCP_PACKET1_INPUT_WORDSWAP           0x200000
+#define BF_DCP_PACKET1_INPUT_WORDSWAP(v)        (((v) << 21) & 0x200000)
+#define BP_DCP_PACKET1_INPUT_BYTESWAP           20
+#define BM_DCP_PACKET1_INPUT_BYTESWAP           0x100000
+#define BF_DCP_PACKET1_INPUT_BYTESWAP(v)        (((v) << 20) & 0x100000)
+#define BP_DCP_PACKET1_KEY_WORDSWAP             19
+#define BM_DCP_PACKET1_KEY_WORDSWAP             0x80000
+#define BF_DCP_PACKET1_KEY_WORDSWAP(v)          (((v) << 19) & 0x80000)
+#define BP_DCP_PACKET1_KEY_BYTESWAP             18
+#define BM_DCP_PACKET1_KEY_BYTESWAP             0x40000
+#define BF_DCP_PACKET1_KEY_BYTESWAP(v)          (((v) << 18) & 0x40000)
+#define BP_DCP_PACKET1_TEST_SEMA_IRQ            17
+#define BM_DCP_PACKET1_TEST_SEMA_IRQ            0x20000
+#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v)         (((v) << 17) & 0x20000)
+#define BP_DCP_PACKET1_CONSTANT_FILL            16
+#define BM_DCP_PACKET1_CONSTANT_FILL            0x10000
+#define BF_DCP_PACKET1_CONSTANT_FILL(v)         (((v) << 16) & 0x10000)
+#define BP_DCP_PACKET1_HASH_OUTPUT              15
+#define BM_DCP_PACKET1_HASH_OUTPUT              0x8000
+#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT       0x0
+#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT      0x1
+#define BF_DCP_PACKET1_HASH_OUTPUT(v)           (((v) << 15) & 0x8000)
+#define BF_DCP_PACKET1_HASH_OUTPUT_V(v)         ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000)
+#define BP_DCP_PACKET1_CHECK_HASH               14
+#define BM_DCP_PACKET1_CHECK_HASH               0x4000
+#define BF_DCP_PACKET1_CHECK_HASH(v)            (((v) << 14) & 0x4000)
+#define BP_DCP_PACKET1_HASH_TERM                13
+#define BM_DCP_PACKET1_HASH_TERM                0x2000
+#define BF_DCP_PACKET1_HASH_TERM(v)             (((v) << 13) & 0x2000)
+#define BP_DCP_PACKET1_HASH_INIT                12
+#define BM_DCP_PACKET1_HASH_INIT                0x1000
+#define BF_DCP_PACKET1_HASH_INIT(v)             (((v) << 12) & 0x1000)
+#define BP_DCP_PACKET1_PAYLOAD_KEY              11
+#define BM_DCP_PACKET1_PAYLOAD_KEY              0x800
+#define BF_DCP_PACKET1_PAYLOAD_KEY(v)           (((v) << 11) & 0x800)
+#define BP_DCP_PACKET1_OTP_KEY                  10
+#define BM_DCP_PACKET1_OTP_KEY                  0x400
+#define BF_DCP_PACKET1_OTP_KEY(v)               (((v) << 10) & 0x400)
+#define BP_DCP_PACKET1_CIPHER_INIT              9
+#define BM_DCP_PACKET1_CIPHER_INIT              0x200
+#define BF_DCP_PACKET1_CIPHER_INIT(v)           (((v) << 9) & 0x200)
+#define BP_DCP_PACKET1_CIPHER_ENCRYPT           8
+#define BM_DCP_PACKET1_CIPHER_ENCRYPT           0x100
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT  0x1
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT  0x0
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v)        (((v) << 8) & 0x100)
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v)      ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100)
+#define BP_DCP_PACKET1_ENABLE_BLIT              7
+#define BM_DCP_PACKET1_ENABLE_BLIT              0x80
+#define BF_DCP_PACKET1_ENABLE_BLIT(v)           (((v) << 7) & 0x80)
+#define BP_DCP_PACKET1_ENABLE_HASH              6
+#define BM_DCP_PACKET1_ENABLE_HASH              0x40
+#define BF_DCP_PACKET1_ENABLE_HASH(v)           (((v) << 6) & 0x40)
+#define BP_DCP_PACKET1_ENABLE_CIPHER            5
+#define BM_DCP_PACKET1_ENABLE_CIPHER            0x20
+#define BF_DCP_PACKET1_ENABLE_CIPHER(v)         (((v) << 5) & 0x20)
+#define BP_DCP_PACKET1_ENABLE_MEMCOPY           4
+#define BM_DCP_PACKET1_ENABLE_MEMCOPY           0x10
+#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v)        (((v) << 4) & 0x10)
+#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS         3
+#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS         0x8
+#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v)      (((v) << 3) & 0x8)
+#define BP_DCP_PACKET1_CHAIN                    2
+#define BM_DCP_PACKET1_CHAIN                    0x4
+#define BF_DCP_PACKET1_CHAIN(v)                 (((v) << 2) & 0x4)
+#define BP_DCP_PACKET1_DECR_SEMAPHORE           1
+#define BM_DCP_PACKET1_DECR_SEMAPHORE           0x2
+#define BF_DCP_PACKET1_DECR_SEMAPHORE(v)        (((v) << 1) & 0x2)
+#define BP_DCP_PACKET1_INTERRUPT                0
+#define BM_DCP_PACKET1_INTERRUPT                0x1
+#define BF_DCP_PACKET1_INTERRUPT(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_PACKET2
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DCP_PACKET2                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0))
+#define BP_DCP_PACKET2_CIPHER_CFG               24
+#define BM_DCP_PACKET2_CIPHER_CFG               0xff000000
+#define BF_DCP_PACKET2_CIPHER_CFG(v)            (((v) << 24) & 0xff000000)
+#define BP_DCP_PACKET2_RSVD                     20
+#define BM_DCP_PACKET2_RSVD                     0xf00000
+#define BF_DCP_PACKET2_RSVD(v)                  (((v) << 20) & 0xf00000)
+#define BP_DCP_PACKET2_HASH_SELECT              16
+#define BM_DCP_PACKET2_HASH_SELECT              0xf0000
+#define BV_DCP_PACKET2_HASH_SELECT__SHA1        0x0
+#define BV_DCP_PACKET2_HASH_SELECT__CRC32       0x1
+#define BF_DCP_PACKET2_HASH_SELECT(v)           (((v) << 16) & 0xf0000)
+#define BF_DCP_PACKET2_HASH_SELECT_V(v)         ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000)
+#define BP_DCP_PACKET2_KEY_SELECT               8
+#define BM_DCP_PACKET2_KEY_SELECT               0xff00
+#define BF_DCP_PACKET2_KEY_SELECT(v)            (((v) << 8) & 0xff00)
+#define BP_DCP_PACKET2_CIPHER_MODE              4
+#define BM_DCP_PACKET2_CIPHER_MODE              0xf0
+#define BV_DCP_PACKET2_CIPHER_MODE__ECB         0x0
+#define BV_DCP_PACKET2_CIPHER_MODE__CBC         0x1
+#define BF_DCP_PACKET2_CIPHER_MODE(v)           (((v) << 4) & 0xf0)
+#define BF_DCP_PACKET2_CIPHER_MODE_V(v)         ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0)
+#define BP_DCP_PACKET2_CIPHER_SELECT            0
+#define BM_DCP_PACKET2_CIPHER_SELECT            0xf
+#define BV_DCP_PACKET2_CIPHER_SELECT__AES128    0x0
+#define BF_DCP_PACKET2_CIPHER_SELECT(v)         (((v) << 0) & 0xf)
+#define BF_DCP_PACKET2_CIPHER_SELECT_V(v)       ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_DCP_PACKET3
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_DCP_PACKET3          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0))
+#define BP_DCP_PACKET3_ADDR     0
+#define BM_DCP_PACKET3_ADDR     0xffffffff
+#define BF_DCP_PACKET3_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET4
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_DCP_PACKET4          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0))
+#define BP_DCP_PACKET4_ADDR     0
+#define BM_DCP_PACKET4_ADDR     0xffffffff
+#define BF_DCP_PACKET4_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET5
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_DCP_PACKET5          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0))
+#define BP_DCP_PACKET5_COUNT    0
+#define BM_DCP_PACKET5_COUNT    0xffffffff
+#define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET6
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_DCP_PACKET6          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0))
+#define BP_DCP_PACKET6_ADDR     0
+#define BM_DCP_PACKET6_ADDR     0xffffffff
+#define BF_DCP_PACKET6_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CHnCMDPTR
+ * Address: 0x100+n*0x40
+ * SCT: no
+*/
+#define HW_DCP_CHnCMDPTR(n)         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40))
+#define BP_DCP_CHnCMDPTR_ADDR       0
+#define BM_DCP_CHnCMDPTR_ADDR       0xffffffff
+#define BF_DCP_CHnCMDPTR_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CHnSEMA
+ * Address: 0x110+n*0x40
+ * SCT: no
+*/
+#define HW_DCP_CHnSEMA(n)           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40))
+#define BP_DCP_CHnSEMA_RSVD2        24
+#define BM_DCP_CHnSEMA_RSVD2        0xff000000
+#define BF_DCP_CHnSEMA_RSVD2(v)     (((v) << 24) & 0xff000000)
+#define BP_DCP_CHnSEMA_VALUE        16
+#define BM_DCP_CHnSEMA_VALUE        0xff0000
+#define BF_DCP_CHnSEMA_VALUE(v)     (((v) << 16) & 0xff0000)
+#define BP_DCP_CHnSEMA_RSVD1        8
+#define BM_DCP_CHnSEMA_RSVD1        0xff00
+#define BF_DCP_CHnSEMA_RSVD1(v)     (((v) << 8) & 0xff00)
+#define BP_DCP_CHnSEMA_INCREMENT    0
+#define BM_DCP_CHnSEMA_INCREMENT    0xff
+#define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CHnSTAT
+ * Address: 0x120+n*0x40
+ * SCT: yes
+*/
+#define HW_DCP_CHnSTAT(n)                           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0))
+#define HW_DCP_CHnSTAT_SET(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4))
+#define HW_DCP_CHnSTAT_CLR(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8))
+#define HW_DCP_CHnSTAT_TOG(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc))
+#define BP_DCP_CHnSTAT_TAG                          24
+#define BM_DCP_CHnSTAT_TAG                          0xff000000
+#define BF_DCP_CHnSTAT_TAG(v)                       (((v) << 24) & 0xff000000)
+#define BP_DCP_CHnSTAT_ERROR_CODE                   16
+#define BM_DCP_CHnSTAT_ERROR_CODE                   0xff0000
+#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0  0x1
+#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN         0x2
+#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR    0x3
+#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR    0x4
+#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE     0x5
+#define BF_DCP_CHnSTAT_ERROR_CODE(v)                (((v) << 16) & 0xff0000)
+#define BF_DCP_CHnSTAT_ERROR_CODE_V(v)              ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000)
+#define BP_DCP_CHnSTAT_RSVD0                        7
+#define BM_DCP_CHnSTAT_RSVD0                        0xff80
+#define BF_DCP_CHnSTAT_RSVD0(v)                     (((v) << 7) & 0xff80)
+#define BP_DCP_CHnSTAT_ERROR_PAGEFAULT              6
+#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT              0x40
+#define BF_DCP_CHnSTAT_ERROR_PAGEFAULT(v)           (((v) << 6) & 0x40)
+#define BP_DCP_CHnSTAT_ERROR_DST                    5
+#define BM_DCP_CHnSTAT_ERROR_DST                    0x20
+#define BF_DCP_CHnSTAT_ERROR_DST(v)                 (((v) << 5) & 0x20)
+#define BP_DCP_CHnSTAT_ERROR_SRC                    4
+#define BM_DCP_CHnSTAT_ERROR_SRC                    0x10
+#define BF_DCP_CHnSTAT_ERROR_SRC(v)                 (((v) << 4) & 0x10)
+#define BP_DCP_CHnSTAT_ERROR_PACKET                 3
+#define BM_DCP_CHnSTAT_ERROR_PACKET                 0x8
+#define BF_DCP_CHnSTAT_ERROR_PACKET(v)              (((v) << 3) & 0x8)
+#define BP_DCP_CHnSTAT_ERROR_SETUP                  2
+#define BM_DCP_CHnSTAT_ERROR_SETUP                  0x4
+#define BF_DCP_CHnSTAT_ERROR_SETUP(v)               (((v) << 2) & 0x4)
+#define BP_DCP_CHnSTAT_HASH_MISMATCH                1
+#define BM_DCP_CHnSTAT_HASH_MISMATCH                0x2
+#define BF_DCP_CHnSTAT_HASH_MISMATCH(v)             (((v) << 1) & 0x2)
+#define BP_DCP_CHnSTAT_RSVD_COMPLETE                0
+#define BM_DCP_CHnSTAT_RSVD_COMPLETE                0x1
+#define BF_DCP_CHnSTAT_RSVD_COMPLETE(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_CHnOPTS
+ * Address: 0x130+n*0x40
+ * SCT: yes
+*/
+#define HW_DCP_CHnOPTS(n)                   (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0))
+#define HW_DCP_CHnOPTS_SET(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4))
+#define HW_DCP_CHnOPTS_CLR(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8))
+#define HW_DCP_CHnOPTS_TOG(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc))
+#define BP_DCP_CHnOPTS_RSVD                 16
+#define BM_DCP_CHnOPTS_RSVD                 0xffff0000
+#define BF_DCP_CHnOPTS_RSVD(v)              (((v) << 16) & 0xffff0000)
+#define BP_DCP_CHnOPTS_RECOVERY_TIMER       0
+#define BM_DCP_CHnOPTS_RECOVERY_TIMER       0xffff
+#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DCP_CSCCTRL0
+ * Address: 0x300
+ * SCT: yes
+*/
+#define HW_DCP_CSCCTRL0                         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0))
+#define HW_DCP_CSCCTRL0_SET                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4))
+#define HW_DCP_CSCCTRL0_CLR                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8))
+#define HW_DCP_CSCCTRL0_TOG                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc))
+#define BP_DCP_CSCCTRL0_RSVD1                   16
+#define BM_DCP_CSCCTRL0_RSVD1                   0xffff0000
+#define BF_DCP_CSCCTRL0_RSVD1(v)                (((v) << 16) & 0xffff0000)
+#define BP_DCP_CSCCTRL0_CLIP                    15
+#define BM_DCP_CSCCTRL0_CLIP                    0x8000
+#define BF_DCP_CSCCTRL0_CLIP(v)                 (((v) << 15) & 0x8000)
+#define BP_DCP_CSCCTRL0_UPSAMPLE                14
+#define BM_DCP_CSCCTRL0_UPSAMPLE                0x4000
+#define BF_DCP_CSCCTRL0_UPSAMPLE(v)             (((v) << 14) & 0x4000)
+#define BP_DCP_CSCCTRL0_SCALE                   13
+#define BM_DCP_CSCCTRL0_SCALE                   0x2000
+#define BF_DCP_CSCCTRL0_SCALE(v)                (((v) << 13) & 0x2000)
+#define BP_DCP_CSCCTRL0_ROTATE                  12
+#define BM_DCP_CSCCTRL0_ROTATE                  0x1000
+#define BF_DCP_CSCCTRL0_ROTATE(v)               (((v) << 12) & 0x1000)
+#define BP_DCP_CSCCTRL0_SUBSAMPLE               11
+#define BM_DCP_CSCCTRL0_SUBSAMPLE               0x800
+#define BF_DCP_CSCCTRL0_SUBSAMPLE(v)            (((v) << 11) & 0x800)
+#define BP_DCP_CSCCTRL0_DELTA                   10
+#define BM_DCP_CSCCTRL0_DELTA                   0x400
+#define BF_DCP_CSCCTRL0_DELTA(v)                (((v) << 10) & 0x400)
+#define BP_DCP_CSCCTRL0_RGB_FORMAT              8
+#define BM_DCP_CSCCTRL0_RGB_FORMAT              0x300
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565   0x0
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI      0x1
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24       0x2
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I     0x3
+#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)           (((v) << 8) & 0x300)
+#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300)
+#define BP_DCP_CSCCTRL0_YUV_FORMAT              4
+#define BM_DCP_CSCCTRL0_YUV_FORMAT              0xf0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420      0x0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422      0x2
+#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)           (((v) << 4) & 0xf0)
+#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0)
+#define BP_DCP_CSCCTRL0_RSVD0                   1
+#define BM_DCP_CSCCTRL0_RSVD0                   0xe
+#define BF_DCP_CSCCTRL0_RSVD0(v)                (((v) << 1) & 0xe)
+#define BP_DCP_CSCCTRL0_ENABLE                  0
+#define BM_DCP_CSCCTRL0_ENABLE                  0x1
+#define BF_DCP_CSCCTRL0_ENABLE(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_CSCSTAT
+ * Address: 0x310
+ * SCT: yes
+*/
+#define HW_DCP_CSCSTAT                                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0))
+#define HW_DCP_CSCSTAT_SET                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4))
+#define HW_DCP_CSCSTAT_CLR                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8))
+#define HW_DCP_CSCSTAT_TOG                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc))
+#define BP_DCP_CSCSTAT_RSVD3                            24
+#define BM_DCP_CSCSTAT_RSVD3                            0xff000000
+#define BF_DCP_CSCSTAT_RSVD3(v)                         (((v) << 24) & 0xff000000)
+#define BP_DCP_CSCSTAT_ERROR_CODE                       16
+#define BM_DCP_CSCSTAT_ERROR_CODE                       0xff0000
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4
+#define BF_DCP_CSCSTAT_ERROR_CODE(v)                    (((v) << 16) & 0xff0000)
+#define BF_DCP_CSCSTAT_ERROR_CODE_V(v)                  ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000)
+#define BP_DCP_CSCSTAT_RSVD2                            7
+#define BM_DCP_CSCSTAT_RSVD2                            0xff80
+#define BF_DCP_CSCSTAT_RSVD2(v)                         (((v) << 7) & 0xff80)
+#define BP_DCP_CSCSTAT_ERROR_PAGEFAULT                  6
+#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT                  0x40
+#define BF_DCP_CSCSTAT_ERROR_PAGEFAULT(v)               (((v) << 6) & 0x40)
+#define BP_DCP_CSCSTAT_ERROR_DST                        5
+#define BM_DCP_CSCSTAT_ERROR_DST                        0x20
+#define BF_DCP_CSCSTAT_ERROR_DST(v)                     (((v) << 5) & 0x20)
+#define BP_DCP_CSCSTAT_ERROR_SRC                        4
+#define BM_DCP_CSCSTAT_ERROR_SRC                        0x10
+#define BF_DCP_CSCSTAT_ERROR_SRC(v)                     (((v) << 4) & 0x10)
+#define BP_DCP_CSCSTAT_RSVD1                            3
+#define BM_DCP_CSCSTAT_RSVD1                            0x8
+#define BF_DCP_CSCSTAT_RSVD1(v)                         (((v) << 3) & 0x8)
+#define BP_DCP_CSCSTAT_ERROR_SETUP                      2
+#define BM_DCP_CSCSTAT_ERROR_SETUP                      0x4
+#define BF_DCP_CSCSTAT_ERROR_SETUP(v)                   (((v) << 2) & 0x4)
+#define BP_DCP_CSCSTAT_RSVD0                            1
+#define BM_DCP_CSCSTAT_RSVD0                            0x2
+#define BF_DCP_CSCSTAT_RSVD0(v)                         (((v) << 1) & 0x2)
+#define BP_DCP_CSCSTAT_COMPLETE                         0
+#define BM_DCP_CSCSTAT_COMPLETE                         0x1
+#define BF_DCP_CSCSTAT_COMPLETE(v)                      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_CSCOUTBUFPARAM
+ * Address: 0x320
+ * SCT: no
+*/
+#define HW_DCP_CSCOUTBUFPARAM               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320))
+#define BP_DCP_CSCOUTBUFPARAM_RSVD1         24
+#define BM_DCP_CSCOUTBUFPARAM_RSVD1         0xff000000
+#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v)      (((v) << 24) & 0xff000000)
+#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE    12
+#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE    0xfff000
+#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000)
+#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE     0
+#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE     0xfff
+#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_CSCINBUFPARAM
+ * Address: 0x330
+ * SCT: no
+*/
+#define HW_DCP_CSCINBUFPARAM                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330))
+#define BP_DCP_CSCINBUFPARAM_RSVD1          12
+#define BM_DCP_CSCINBUFPARAM_RSVD1          0xfffff000
+#define BF_DCP_CSCINBUFPARAM_RSVD1(v)       (((v) << 12) & 0xfffff000)
+#define BP_DCP_CSCINBUFPARAM_LINE_SIZE      0
+#define BM_DCP_CSCINBUFPARAM_LINE_SIZE      0xfff
+#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_CSCRGB
+ * Address: 0x340
+ * SCT: no
+*/
+#define HW_DCP_CSCRGB           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340))
+#define BP_DCP_CSCRGB_ADDR      0
+#define BM_DCP_CSCRGB_ADDR      0xffffffff
+#define BF_DCP_CSCRGB_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCLUMA
+ * Address: 0x350
+ * SCT: no
+*/
+#define HW_DCP_CSCLUMA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350))
+#define BP_DCP_CSCLUMA_ADDR     0
+#define BM_DCP_CSCLUMA_ADDR     0xffffffff
+#define BF_DCP_CSCLUMA_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCCHROMAU
+ * Address: 0x360
+ * SCT: no
+*/
+#define HW_DCP_CSCCHROMAU           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360))
+#define BP_DCP_CSCCHROMAU_ADDR      0
+#define BM_DCP_CSCCHROMAU_ADDR      0xffffffff
+#define BF_DCP_CSCCHROMAU_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCCHROMAV
+ * Address: 0x370
+ * SCT: no
+*/
+#define HW_DCP_CSCCHROMAV           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370))
+#define BP_DCP_CSCCHROMAV_ADDR      0
+#define BM_DCP_CSCCHROMAV_ADDR      0xffffffff
+#define BF_DCP_CSCCHROMAV_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCCOEFF0
+ * Address: 0x380
+ * SCT: no
+*/
+#define HW_DCP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380))
+#define BP_DCP_CSCCOEFF0_RSVD1          26
+#define BM_DCP_CSCCOEFF0_RSVD1          0xfc000000
+#define BF_DCP_CSCCOEFF0_RSVD1(v)       (((v) << 26) & 0xfc000000)
+#define BP_DCP_CSCCOEFF0_C0             16
+#define BM_DCP_CSCCOEFF0_C0             0x3ff0000
+#define BF_DCP_CSCCOEFF0_C0(v)          (((v) << 16) & 0x3ff0000)
+#define BP_DCP_CSCCOEFF0_UV_OFFSET      8
+#define BM_DCP_CSCCOEFF0_UV_OFFSET      0xff00
+#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 8) & 0xff00)
+#define BP_DCP_CSCCOEFF0_Y_OFFSET       0
+#define BM_DCP_CSCCOEFF0_Y_OFFSET       0xff
+#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CSCCOEFF1
+ * Address: 0x390
+ * SCT: no
+*/
+#define HW_DCP_CSCCOEFF1            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390))
+#define BP_DCP_CSCCOEFF1_RSVD1      26
+#define BM_DCP_CSCCOEFF1_RSVD1      0xfc000000
+#define BF_DCP_CSCCOEFF1_RSVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_DCP_CSCCOEFF1_C1         16
+#define BM_DCP_CSCCOEFF1_C1         0x3ff0000
+#define BF_DCP_CSCCOEFF1_C1(v)      (((v) << 16) & 0x3ff0000)
+#define BP_DCP_CSCCOEFF1_RSVD0      10
+#define BM_DCP_CSCCOEFF1_RSVD0      0xfc00
+#define BF_DCP_CSCCOEFF1_RSVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_DCP_CSCCOEFF1_C4         0
+#define BM_DCP_CSCCOEFF1_C4         0x3ff
+#define BF_DCP_CSCCOEFF1_C4(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_DCP_CSCCOEFF2
+ * Address: 0x3a0
+ * SCT: no
+*/
+#define HW_DCP_CSCCOEFF2            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0))
+#define BP_DCP_CSCCOEFF2_RSVD1      26
+#define BM_DCP_CSCCOEFF2_RSVD1      0xfc000000
+#define BF_DCP_CSCCOEFF2_RSVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_DCP_CSCCOEFF2_C2         16
+#define BM_DCP_CSCCOEFF2_C2         0x3ff0000
+#define BF_DCP_CSCCOEFF2_C2(v)      (((v) << 16) & 0x3ff0000)
+#define BP_DCP_CSCCOEFF2_RSVD0      10
+#define BM_DCP_CSCCOEFF2_RSVD0      0xfc00
+#define BF_DCP_CSCCOEFF2_RSVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_DCP_CSCCOEFF2_C3         0
+#define BM_DCP_CSCCOEFF2_C3         0x3ff
+#define BF_DCP_CSCCOEFF2_C3(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_DCP_CSCCLIP
+ * Address: 0x3d0
+ * SCT: no
+*/
+#define HW_DCP_CSCCLIP              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3d0))
+#define BP_DCP_CSCCLIP_RSVD1        24
+#define BM_DCP_CSCCLIP_RSVD1        0xff000000
+#define BF_DCP_CSCCLIP_RSVD1(v)     (((v) << 24) & 0xff000000)
+#define BP_DCP_CSCCLIP_HEIGHT       12
+#define BM_DCP_CSCCLIP_HEIGHT       0xfff000
+#define BF_DCP_CSCCLIP_HEIGHT(v)    (((v) << 12) & 0xfff000)
+#define BP_DCP_CSCCLIP_WIDTH        0
+#define BM_DCP_CSCCLIP_WIDTH        0xfff
+#define BF_DCP_CSCCLIP_WIDTH(v)     (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_CSCXSCALE
+ * Address: 0x3e0
+ * SCT: no
+*/
+#define HW_DCP_CSCXSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0))
+#define BP_DCP_CSCXSCALE_RSVD1      26
+#define BM_DCP_CSCXSCALE_RSVD1      0xfc000000
+#define BF_DCP_CSCXSCALE_RSVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_DCP_CSCXSCALE_INT        24
+#define BM_DCP_CSCXSCALE_INT        0x3000000
+#define BF_DCP_CSCXSCALE_INT(v)     (((v) << 24) & 0x3000000)
+#define BP_DCP_CSCXSCALE_FRAC       12
+#define BM_DCP_CSCXSCALE_FRAC       0xfff000
+#define BF_DCP_CSCXSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
+#define BP_DCP_CSCXSCALE_WIDTH      0
+#define BM_DCP_CSCXSCALE_WIDTH      0xfff
+#define BF_DCP_CSCXSCALE_WIDTH(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_CSCYSCALE
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_DCP_CSCYSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0))
+#define BP_DCP_CSCYSCALE_RSVD1      26
+#define BM_DCP_CSCYSCALE_RSVD1      0xfc000000
+#define BF_DCP_CSCYSCALE_RSVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_DCP_CSCYSCALE_INT        24
+#define BM_DCP_CSCYSCALE_INT        0x3000000
+#define BF_DCP_CSCYSCALE_INT(v)     (((v) << 24) & 0x3000000)
+#define BP_DCP_CSCYSCALE_FRAC       12
+#define BM_DCP_CSCYSCALE_FRAC       0xfff000
+#define BF_DCP_CSCYSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
+#define BP_DCP_CSCYSCALE_HEIGHT     0
+#define BM_DCP_CSCYSCALE_HEIGHT     0xfff
+#define BF_DCP_CSCYSCALE_HEIGHT(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_DBGSELECT
+ * Address: 0x400
+ * SCT: no
+*/
+#define HW_DCP_DBGSELECT                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400))
+#define BP_DCP_DBGSELECT_RSVD           8
+#define BM_DCP_DBGSELECT_RSVD           0xffffff00
+#define BF_DCP_DBGSELECT_RSVD(v)        (((v) << 8) & 0xffffff00)
+#define BP_DCP_DBGSELECT_INDEX          0
+#define BM_DCP_DBGSELECT_INDEX          0xff
+#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
+#define BF_DCP_DBGSELECT_INDEX(v)       (((v) << 0) & 0xff)
+#define BF_DCP_DBGSELECT_INDEX_V(v)     ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_DBGDATA
+ * Address: 0x410
+ * SCT: no
+*/
+#define HW_DCP_DBGDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410))
+#define BP_DCP_DBGDATA_DATA     0
+#define BM_DCP_DBGDATA_DATA     0xffffffff
+#define BF_DCP_DBGDATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PAGETABLE
+ * Address: 0x420
+ * SCT: no
+*/
+#define HW_DCP_PAGETABLE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420))
+#define BP_DCP_PAGETABLE_BASE       2
+#define BM_DCP_PAGETABLE_BASE       0xfffffffc
+#define BF_DCP_PAGETABLE_BASE(v)    (((v) << 2) & 0xfffffffc)
+#define BP_DCP_PAGETABLE_FLUSH      1
+#define BM_DCP_PAGETABLE_FLUSH      0x2
+#define BF_DCP_PAGETABLE_FLUSH(v)   (((v) << 1) & 0x2)
+#define BP_DCP_PAGETABLE_ENABLE     0
+#define BM_DCP_PAGETABLE_ENABLE     0x1
+#define BF_DCP_PAGETABLE_ENABLE(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_VERSION
+ * Address: 0x430
+ * SCT: no
+*/
+#define HW_DCP_VERSION          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x430))
+#define BP_DCP_VERSION_MAJOR    24
+#define BM_DCP_VERSION_MAJOR    0xff000000
+#define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_DCP_VERSION_MINOR    16
+#define BM_DCP_VERSION_MINOR    0xff0000
+#define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_DCP_VERSION_STEP     0
+#define BM_DCP_VERSION_STEP     0xffff
+#define BF_DCP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__DCP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-digctl.h b/firmware/target/arm/imx233/regs/imx233/regs-digctl.h
new file mode 100644
index 0000000000..a709d296c8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-digctl.h
@@ -0,0 +1,966 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__DIGCTL__H__
+#define __HEADERGEN__IMX233__DIGCTL__H__
+
+#define REGS_DIGCTL_BASE (0x8001c000)
+
+#define REGS_DIGCTL_VERSION "3.2.0"
+
+/**
+ * Register: HW_DIGCTL_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DIGCTL_CTRL                                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0))
+#define HW_DIGCTL_CTRL_SET                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4))
+#define HW_DIGCTL_CTRL_CLR                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8))
+#define HW_DIGCTL_CTRL_TOG                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc))
+#define BP_DIGCTL_CTRL_RSVD3                                31
+#define BM_DIGCTL_CTRL_RSVD3                                0x80000000
+#define BF_DIGCTL_CTRL_RSVD3(v)                             (((v) << 31) & 0x80000000)
+#define BP_DIGCTL_CTRL_XTAL24M_GATE                         30
+#define BM_DIGCTL_CTRL_XTAL24M_GATE                         0x40000000
+#define BF_DIGCTL_CTRL_XTAL24M_GATE(v)                      (((v) << 30) & 0x40000000)
+#define BP_DIGCTL_CTRL_TRAP_IRQ                             29
+#define BM_DIGCTL_CTRL_TRAP_IRQ                             0x20000000
+#define BF_DIGCTL_CTRL_TRAP_IRQ(v)                          (((v) << 29) & 0x20000000)
+#define BP_DIGCTL_CTRL_RSVD2                                27
+#define BM_DIGCTL_CTRL_RSVD2                                0x18000000
+#define BF_DIGCTL_CTRL_RSVD2(v)                             (((v) << 27) & 0x18000000)
+#define BP_DIGCTL_CTRL_CACHE_BIST_TMODE                     26
+#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE                     0x4000000
+#define BF_DIGCTL_CTRL_CACHE_BIST_TMODE(v)                  (((v) << 26) & 0x4000000)
+#define BP_DIGCTL_CTRL_LCD_BIST_CLKEN                       25
+#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN                       0x2000000
+#define BF_DIGCTL_CTRL_LCD_BIST_CLKEN(v)                    (((v) << 25) & 0x2000000)
+#define BP_DIGCTL_CTRL_LCD_BIST_START                       24
+#define BM_DIGCTL_CTRL_LCD_BIST_START                       0x1000000
+#define BF_DIGCTL_CTRL_LCD_BIST_START(v)                    (((v) << 24) & 0x1000000)
+#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN                       23
+#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN                       0x800000
+#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                    (((v) << 23) & 0x800000)
+#define BP_DIGCTL_CTRL_DCP_BIST_START                       22
+#define BM_DIGCTL_CTRL_DCP_BIST_START                       0x400000
+#define BF_DIGCTL_CTRL_DCP_BIST_START(v)                    (((v) << 22) & 0x400000)
+#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN                       21
+#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN                       0x200000
+#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                    (((v) << 21) & 0x200000)
+#define BP_DIGCTL_CTRL_USB_TESTMODE                         20
+#define BM_DIGCTL_CTRL_USB_TESTMODE                         0x100000
+#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                      (((v) << 20) & 0x100000)
+#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                      19
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                      0x80000
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)                   (((v) << 19) & 0x80000)
+#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                     18
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                     0x40000
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                  (((v) << 18) & 0x40000)
+#define BP_DIGCTL_CTRL_ARM_BIST_START                       17
+#define BM_DIGCTL_CTRL_ARM_BIST_START                       0x20000
+#define BF_DIGCTL_CTRL_ARM_BIST_START(v)                    (((v) << 17) & 0x20000)
+#define BP_DIGCTL_CTRL_UART_LOOPBACK                        16
+#define BM_DIGCTL_CTRL_UART_LOOPBACK                        0x10000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                     (((v) << 16) & 0x10000)
+#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000)
+#define BP_DIGCTL_CTRL_SAIF_LOOPBACK                        15
+#define BM_DIGCTL_CTRL_SAIF_LOOPBACK                        0x8000
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v)                     (((v) << 15) & 0x8000)
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000)
+#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      13
+#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      0x6000
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                   (((v) << 13) & 0x6000)
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000)
+#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL                      12
+#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL                      0x1000
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST           0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST           0x1
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                   (((v) << 12) & 0x1000)
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000)
+#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  11
+#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  0x800
+#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)               (((v) << 11) & 0x800)
+#define BP_DIGCTL_CTRL_RSVD1                                10
+#define BM_DIGCTL_CTRL_RSVD1                                0x400
+#define BF_DIGCTL_CTRL_RSVD1(v)                             (((v) << 10) & 0x400)
+#define BP_DIGCTL_CTRL_SY_ENDIAN                            9
+#define BM_DIGCTL_CTRL_SY_ENDIAN                            0x200
+#define BF_DIGCTL_CTRL_SY_ENDIAN(v)                         (((v) << 9) & 0x200)
+#define BP_DIGCTL_CTRL_SY_SFTRST                            8
+#define BM_DIGCTL_CTRL_SY_SFTRST                            0x100
+#define BF_DIGCTL_CTRL_SY_SFTRST(v)                         (((v) << 8) & 0x100)
+#define BP_DIGCTL_CTRL_SY_CLKGATE                           7
+#define BM_DIGCTL_CTRL_SY_CLKGATE                           0x80
+#define BF_DIGCTL_CTRL_SY_CLKGATE(v)                        (((v) << 7) & 0x80)
+#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG                      6
+#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG                      0x40
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG            0x0
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG         0x1
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                   (((v) << 6) & 0x40)
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v)                 ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40)
+#define BP_DIGCTL_CTRL_TRAP_IN_RANGE                        5
+#define BM_DIGCTL_CTRL_TRAP_IN_RANGE                        0x20
+#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v)                     (((v) << 5) & 0x20)
+#define BP_DIGCTL_CTRL_TRAP_ENABLE                          4
+#define BM_DIGCTL_CTRL_TRAP_ENABLE                          0x10
+#define BF_DIGCTL_CTRL_TRAP_ENABLE(v)                       (((v) << 4) & 0x10)
+#define BP_DIGCTL_CTRL_DEBUG_DISABLE                        3
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE                        0x8
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                     (((v) << 3) & 0x8)
+#define BP_DIGCTL_CTRL_USB_CLKGATE                          2
+#define BM_DIGCTL_CTRL_USB_CLKGATE                          0x4
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                     0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS                 0x1
+#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                       (((v) << 2) & 0x4)
+#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v)                     ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4)
+#define BP_DIGCTL_CTRL_JTAG_SHIELD                          1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD                          0x2
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL                  0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP              0x1
+#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                       (((v) << 1) & 0x2)
+#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v)                     ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2)
+#define BP_DIGCTL_CTRL_LATCH_ENTROPY                        0
+#define BM_DIGCTL_CTRL_LATCH_ENTROPY                        0x1
+#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v)                     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_STATUS
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_DIGCTL_STATUS                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x0))
+#define HW_DIGCTL_STATUS_SET                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x4))
+#define HW_DIGCTL_STATUS_CLR                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0x8))
+#define HW_DIGCTL_STATUS_TOG                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10 + 0xc))
+#define BP_DIGCTL_STATUS_USB_HS_PRESENT         31
+#define BM_DIGCTL_STATUS_USB_HS_PRESENT         0x80000000
+#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v)      (((v) << 31) & 0x80000000)
+#define BP_DIGCTL_STATUS_USB_OTG_PRESENT        30
+#define BM_DIGCTL_STATUS_USB_OTG_PRESENT        0x40000000
+#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v)     (((v) << 30) & 0x40000000)
+#define BP_DIGCTL_STATUS_USB_HOST_PRESENT       29
+#define BM_DIGCTL_STATUS_USB_HOST_PRESENT       0x20000000
+#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v)    (((v) << 29) & 0x20000000)
+#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT     28
+#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT     0x10000000
+#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)  (((v) << 28) & 0x10000000)
+#define BP_DIGCTL_STATUS_RSVD2                  11
+#define BM_DIGCTL_STATUS_RSVD2                  0xffff800
+#define BF_DIGCTL_STATUS_RSVD2(v)               (((v) << 11) & 0xffff800)
+#define BP_DIGCTL_STATUS_DCP_BIST_FAIL          10
+#define BM_DIGCTL_STATUS_DCP_BIST_FAIL          0x400
+#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v)       (((v) << 10) & 0x400)
+#define BP_DIGCTL_STATUS_DCP_BIST_PASS          9
+#define BM_DIGCTL_STATUS_DCP_BIST_PASS          0x200
+#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v)       (((v) << 9) & 0x200)
+#define BP_DIGCTL_STATUS_DCP_BIST_DONE          8
+#define BM_DIGCTL_STATUS_DCP_BIST_DONE          0x100
+#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v)       (((v) << 8) & 0x100)
+#define BP_DIGCTL_STATUS_LCD_BIST_FAIL          7
+#define BM_DIGCTL_STATUS_LCD_BIST_FAIL          0x80
+#define BF_DIGCTL_STATUS_LCD_BIST_FAIL(v)       (((v) << 7) & 0x80)
+#define BP_DIGCTL_STATUS_LCD_BIST_PASS          6
+#define BM_DIGCTL_STATUS_LCD_BIST_PASS          0x40
+#define BF_DIGCTL_STATUS_LCD_BIST_PASS(v)       (((v) << 6) & 0x40)
+#define BP_DIGCTL_STATUS_LCD_BIST_DONE          5
+#define BM_DIGCTL_STATUS_LCD_BIST_DONE          0x20
+#define BF_DIGCTL_STATUS_LCD_BIST_DONE(v)       (((v) << 5) & 0x20)
+#define BP_DIGCTL_STATUS_JTAG_IN_USE            4
+#define BM_DIGCTL_STATUS_JTAG_IN_USE            0x10
+#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)         (((v) << 4) & 0x10)
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE           1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE           0xe
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)        (((v) << 1) & 0xe)
+#define BP_DIGCTL_STATUS_WRITTEN                0
+#define BM_DIGCTL_STATUS_WRITTEN                0x1
+#define BF_DIGCTL_STATUS_WRITTEN(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_HCLKCOUNT
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_DIGCTL_HCLKCOUNT             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x0))
+#define HW_DIGCTL_HCLKCOUNT_SET         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x4))
+#define HW_DIGCTL_HCLKCOUNT_CLR         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0x8))
+#define HW_DIGCTL_HCLKCOUNT_TOG         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20 + 0xc))
+#define BP_DIGCTL_HCLKCOUNT_COUNT       0
+#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_RAMCTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMCTRL                   (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0))
+#define HW_DIGCTL_RAMCTRL_SET               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4))
+#define HW_DIGCTL_RAMCTRL_CLR               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8))
+#define HW_DIGCTL_RAMCTRL_TOG               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc))
+#define BP_DIGCTL_RAMCTRL_RSVD1             12
+#define BM_DIGCTL_RAMCTRL_RSVD1             0xfffff000
+#define BF_DIGCTL_RAMCTRL_RSVD1(v)          (((v) << 12) & 0xfffff000)
+#define BP_DIGCTL_RAMCTRL_SPEED_SELECT      8
+#define BM_DIGCTL_RAMCTRL_SPEED_SELECT      0xf00
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)   (((v) << 8) & 0xf00)
+#define BP_DIGCTL_RAMCTRL_RSVD0             1
+#define BM_DIGCTL_RAMCTRL_RSVD0             0xfe
+#define BF_DIGCTL_RAMCTRL_RSVD0(v)          (((v) << 1) & 0xfe)
+#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0
+#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0x1
+#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_RAMREPAIR
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMREPAIR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0))
+#define HW_DIGCTL_RAMREPAIR_SET         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4))
+#define HW_DIGCTL_RAMREPAIR_CLR         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8))
+#define HW_DIGCTL_RAMREPAIR_TOG         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc))
+#define BP_DIGCTL_RAMREPAIR_RSVD1       16
+#define BM_DIGCTL_RAMREPAIR_RSVD1       0xffff0000
+#define BF_DIGCTL_RAMREPAIR_RSVD1(v)    (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_RAMREPAIR_ADDR        0
+#define BM_DIGCTL_RAMREPAIR_ADDR        0xffff
+#define BF_DIGCTL_RAMREPAIR_ADDR(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_ROMCTRL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_DIGCTL_ROMCTRL               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0))
+#define HW_DIGCTL_ROMCTRL_SET           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4))
+#define HW_DIGCTL_ROMCTRL_CLR           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8))
+#define HW_DIGCTL_ROMCTRL_TOG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc))
+#define BP_DIGCTL_ROMCTRL_RSVD0         4
+#define BM_DIGCTL_ROMCTRL_RSVD0         0xfffffff0
+#define BF_DIGCTL_ROMCTRL_RSVD0(v)      (((v) << 4) & 0xfffffff0)
+#define BP_DIGCTL_ROMCTRL_RD_MARGIN     0
+#define BM_DIGCTL_ROMCTRL_RD_MARGIN     0xf
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)  (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_WRITEONCE
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DIGCTL_WRITEONCE         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60))
+#define BP_DIGCTL_WRITEONCE_BITS    0
+#define BM_DIGCTL_WRITEONCE_BITS    0xffffffff
+#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ENTROPY
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DIGCTL_ENTROPY           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90))
+#define BP_DIGCTL_ENTROPY_VALUE     0
+#define BM_DIGCTL_ENTROPY_VALUE     0xffffffff
+#define BF_DIGCTL_ENTROPY_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ENTROPY_LATCHED
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DIGCTL_ENTROPY_LATCHED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0))
+#define BP_DIGCTL_ENTROPY_LATCHED_VALUE     0
+#define BM_DIGCTL_ENTROPY_LATCHED_VALUE     0xffffffff
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SJTAGDBG
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_DIGCTL_SJTAGDBG                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0))
+#define HW_DIGCTL_SJTAGDBG_SET                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4))
+#define HW_DIGCTL_SJTAGDBG_CLR                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8))
+#define HW_DIGCTL_SJTAGDBG_TOG                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc))
+#define BP_DIGCTL_SJTAGDBG_RSVD2                27
+#define BM_DIGCTL_SJTAGDBG_RSVD2                0xf8000000
+#define BF_DIGCTL_SJTAGDBG_RSVD2(v)             (((v) << 27) & 0xf8000000)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE          16
+#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE          0x7ff0000
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)       (((v) << 16) & 0x7ff0000)
+#define BP_DIGCTL_SJTAGDBG_RSVD1                11
+#define BM_DIGCTL_SJTAGDBG_RSVD1                0xf800
+#define BF_DIGCTL_SJTAGDBG_RSVD1(v)             (((v) << 11) & 0xf800)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO            10
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO            0x400
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v)         (((v) << 10) & 0x400)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI            9
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI            0x200
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v)         (((v) << 9) & 0x200)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE           8
+#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE           0x100
+#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v)        (((v) << 8) & 0x100)
+#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       4
+#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       0xf0
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)    (((v) << 4) & 0xf0)
+#define BP_DIGCTL_SJTAGDBG_ACTIVE               3
+#define BM_DIGCTL_SJTAGDBG_ACTIVE               0x8
+#define BF_DIGCTL_SJTAGDBG_ACTIVE(v)            (((v) << 3) & 0x8)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      2
+#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      0x4
+#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)   (((v) << 2) & 0x4)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     1
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     0x2
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)  (((v) << 1) & 0x2)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0x1
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_MICROSECONDS
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_DIGCTL_MICROSECONDS          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0))
+#define HW_DIGCTL_MICROSECONDS_SET      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4))
+#define HW_DIGCTL_MICROSECONDS_CLR      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8))
+#define HW_DIGCTL_MICROSECONDS_TOG      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc))
+#define BP_DIGCTL_MICROSECONDS_VALUE    0
+#define BM_DIGCTL_MICROSECONDS_VALUE    0xffffffff
+#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBGRD
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBGRD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0))
+#define BP_DIGCTL_DBGRD_COMPLEMENT      0
+#define BM_DIGCTL_DBGRD_COMPLEMENT      0xffffffff
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBG
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0))
+#define BP_DIGCTL_DBG_VALUE     0
+#define BM_DIGCTL_DBG_VALUE     0xffffffff
+#define BF_DIGCTL_DBG_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_BIST_CSR
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_BIST_CSR                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0))
+#define HW_DIGCTL_OCRAM_BIST_CSR_SET                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4))
+#define HW_DIGCTL_OCRAM_BIST_CSR_CLR                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8))
+#define HW_DIGCTL_OCRAM_BIST_CSR_TOG                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc))
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1                  11
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1                  0xfffff800
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v)               (((v) << 11) & 0xfffff800)
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE        10
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE        0x400
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(v)     (((v) << 10) & 0x400)
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       9
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       0x200
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)    (((v) << 9) & 0x200)
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             8
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             0x100
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)          (((v) << 8) & 0x100)
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0                  4
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0                  0xf0
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v)               (((v) << 4) & 0xf0)
+#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL                   3
+#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL                   0x8
+#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v)                (((v) << 3) & 0x8)
+#define BP_DIGCTL_OCRAM_BIST_CSR_PASS                   2
+#define BM_DIGCTL_OCRAM_BIST_CSR_PASS                   0x4
+#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v)                (((v) << 2) & 0x4)
+#define BP_DIGCTL_OCRAM_BIST_CSR_DONE                   1
+#define BM_DIGCTL_OCRAM_BIST_CSR_DONE                   0x2
+#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v)                (((v) << 1) & 0x2)
+#define BP_DIGCTL_OCRAM_BIST_CSR_START                  0
+#define BM_DIGCTL_OCRAM_BIST_CSR_START                  0x1
+#define BF_DIGCTL_OCRAM_BIST_CSR_START(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS0
+ * Address: 0x110
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS0                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS0_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS0_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS0_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00      0
+#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS1
+ * Address: 0x120
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS1                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS1_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS1_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS1_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01      0
+#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS2
+ * Address: 0x130
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS2                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS2_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS2_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS2_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10      0
+#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS3
+ * Address: 0x140
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS3                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS3_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS3_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS3_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11      0
+#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS4
+ * Address: 0x150
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS4                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS4_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS4_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS4_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20      0
+#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS5
+ * Address: 0x160
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS5                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS5_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS5_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS5_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21      0
+#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS6
+ * Address: 0x170
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS6                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS6_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS6_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS6_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30      0
+#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS7
+ * Address: 0x180
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS7                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS7_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS7_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS7_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31      0
+#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS8
+ * Address: 0x190
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS8                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS8_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS8_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS8_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD3           29
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD3           0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v)        (((v) << 29) & 0xe0000000)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01      16
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01      0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)   (((v) << 16) & 0x1fff0000)
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD2           13
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD2           0xe000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v)        (((v) << 13) & 0xe000)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00      0
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00      0x1fff
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS9
+ * Address: 0x1a0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS9                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS9_SET             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS9_CLR             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS9_TOG             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD3           29
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD3           0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v)        (((v) << 29) & 0xe0000000)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11      16
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11      0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)   (((v) << 16) & 0x1fff0000)
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD2           13
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD2           0xe000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v)        (((v) << 13) & 0xe000)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10      0
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10      0x1fff
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS10
+ * Address: 0x1b0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS10                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS10_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS10_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS10_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD3          29
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD3          0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v)       (((v) << 29) & 0xe0000000)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21     16
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21     0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)  (((v) << 16) & 0x1fff0000)
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD2          13
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD2          0xe000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v)       (((v) << 13) & 0xe000)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20     0
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20     0x1fff
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)  (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS11
+ * Address: 0x1c0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS11                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS11_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS11_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS11_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD3          29
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD3          0xe0000000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v)       (((v) << 29) & 0xe0000000)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31     16
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31     0x1fff0000
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)  (((v) << 16) & 0x1fff0000)
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD2          13
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD2          0xe000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v)       (((v) << 13) & 0xe000)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30     0
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30     0x1fff
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)  (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS12
+ * Address: 0x1d0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS12                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS12_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS12_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS12_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD3          28
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD3          0xf0000000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v)       (((v) << 28) & 0xf0000000)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11    24
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11    0xf000000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0xf000000)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD2          20
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD2          0xf00000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v)       (((v) << 20) & 0xf00000)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10    16
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10    0xf0000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0xf0000)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD1          12
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD1          0xf000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v)       (((v) << 12) & 0xf000)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01    8
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01    0xf00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0xf00)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD0          4
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD0          0xf0
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v)       (((v) << 4) & 0xf0)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0xf
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS13
+ * Address: 0x1e0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_STATUS13                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x0))
+#define HW_DIGCTL_OCRAM_STATUS13_SET            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x4))
+#define HW_DIGCTL_OCRAM_STATUS13_CLR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0x8))
+#define HW_DIGCTL_OCRAM_STATUS13_TOG            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0 + 0xc))
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD3          28
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD3          0xf0000000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v)       (((v) << 28) & 0xf0000000)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31    24
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31    0xf000000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0xf000000)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD2          20
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD2          0xf00000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v)       (((v) << 20) & 0xf00000)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30    16
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30    0xf0000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0xf0000)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD1          12
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD1          0xf000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v)       (((v) << 12) & 0xf000)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21    8
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21    0xf00
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0xf00)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD0          4
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD0          0xf0
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v)       (((v) << 4) & 0xf0)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0xf
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH0
+ * Address: 0x290
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH0          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290))
+#define BP_DIGCTL_SCRATCH0_PTR      0
+#define BM_DIGCTL_SCRATCH0_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH0_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH1
+ * Address: 0x2a0
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH1          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0))
+#define BP_DIGCTL_SCRATCH1_PTR      0
+#define BM_DIGCTL_SCRATCH1_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH1_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ARMCACHE
+ * Address: 0x2b0
+ * SCT: no
+*/
+#define HW_DIGCTL_ARMCACHE              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0))
+#define BP_DIGCTL_ARMCACHE_RSVD4        18
+#define BM_DIGCTL_ARMCACHE_RSVD4        0xfffc0000
+#define BF_DIGCTL_ARMCACHE_RSVD4(v)     (((v) << 18) & 0xfffc0000)
+#define BP_DIGCTL_ARMCACHE_VALID_SS     16
+#define BM_DIGCTL_ARMCACHE_VALID_SS     0x30000
+#define BF_DIGCTL_ARMCACHE_VALID_SS(v)  (((v) << 16) & 0x30000)
+#define BP_DIGCTL_ARMCACHE_RSVD3        14
+#define BM_DIGCTL_ARMCACHE_RSVD3        0xc000
+#define BF_DIGCTL_ARMCACHE_RSVD3(v)     (((v) << 14) & 0xc000)
+#define BP_DIGCTL_ARMCACHE_DRTY_SS      12
+#define BM_DIGCTL_ARMCACHE_DRTY_SS      0x3000
+#define BF_DIGCTL_ARMCACHE_DRTY_SS(v)   (((v) << 12) & 0x3000)
+#define BP_DIGCTL_ARMCACHE_RSVD2        10
+#define BM_DIGCTL_ARMCACHE_RSVD2        0xc00
+#define BF_DIGCTL_ARMCACHE_RSVD2(v)     (((v) << 10) & 0xc00)
+#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  (((v) << 8) & 0x300)
+#define BP_DIGCTL_ARMCACHE_RSVD1        6
+#define BM_DIGCTL_ARMCACHE_RSVD1        0xc0
+#define BF_DIGCTL_ARMCACHE_RSVD1(v)     (((v) << 6) & 0xc0)
+#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x30
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)   (((v) << 4) & 0x30)
+#define BP_DIGCTL_ARMCACHE_RSVD0        2
+#define BM_DIGCTL_ARMCACHE_RSVD0        0xc
+#define BF_DIGCTL_ARMCACHE_RSVD0(v)     (((v) << 2) & 0xc)
+#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x3
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)   (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW
+ * Address: 0x2c0
+ * SCT: no
+*/
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0))
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH
+ * Address: 0x2d0
+ * SCT: no
+*/
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0))
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SGTL
+ * Address: 0x300
+ * SCT: no
+*/
+#define HW_DIGCTL_SGTL              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300))
+#define BP_DIGCTL_SGTL_COPYRIGHT    0
+#define BM_DIGCTL_SGTL_COPYRIGHT    0xffffffff
+#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_CHIPID
+ * Address: 0x310
+ * SCT: no
+*/
+#define HW_DIGCTL_CHIPID                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310))
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_CHIPID_RSVD0              8
+#define BM_DIGCTL_CHIPID_RSVD0              0xff00
+#define BF_DIGCTL_CHIPID_RSVD0(v)           (((v) << 8) & 0xff00)
+#define BP_DIGCTL_CHIPID_REVISION           0
+#define BM_DIGCTL_CHIPID_REVISION           0xff
+#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DIGCTL_AHB_STATS_SELECT
+ * Address: 0x330
+ * SCT: no
+*/
+#define HW_DIGCTL_AHB_STATS_SELECT                          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330))
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3                    28
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3                    0xf0000000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v)                 (((v) << 28) & 0xf0000000)
+#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         24
+#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         0xf000000
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX   0x2
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB    0x4
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)      (((v) << 24) & 0xf000000)
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000)
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2                    20
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2                    0xf00000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v)                 (((v) << 20) & 0xf00000)
+#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         16
+#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         0xf0000
+#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)      (((v) << 16) & 0xf0000)
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000)
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1                    12
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1                    0xf000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v)                 (((v) << 12) & 0xf000)
+#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         8
+#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         0xf00
+#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)      (((v) << 8) & 0xf00)
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00)
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0                    4
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0                    0xf0
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v)                 (((v) << 4) & 0xf0)
+#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0
+#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0xf
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)      (((v) << 0) & 0xf)
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES
+ * Address: 0x340
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340))
+#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_DATA_STALLED
+ * Address: 0x350
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350))
+#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES
+ * Address: 0x360
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360))
+#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES
+ * Address: 0x370
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370))
+#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_DATA_STALLED
+ * Address: 0x380
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380))
+#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES
+ * Address: 0x390
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390))
+#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES
+ * Address: 0x3a0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0))
+#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_DATA_STALLED
+ * Address: 0x3b0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0))
+#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES
+ * Address: 0x3c0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0))
+#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES
+ * Address: 0x3d0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0))
+#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_DATA_STALLED
+ * Address: 0x3e0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0))
+#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0))
+#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_MPTEn_LOC
+ * Address: 0x400+n*0x10
+ * SCT: no
+*/
+#define HW_DIGCTL_MPTEn_LOC(n)          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10))
+#define BP_DIGCTL_MPTEn_LOC_RSVD0       12
+#define BM_DIGCTL_MPTEn_LOC_RSVD0       0xfffff000
+#define BF_DIGCTL_MPTEn_LOC_RSVD0(v)    (((v) << 12) & 0xfffff000)
+#define BP_DIGCTL_MPTEn_LOC_LOC         0
+#define BM_DIGCTL_MPTEn_LOC_LOC         0xfff
+#define BF_DIGCTL_MPTEn_LOC_LOC(v)      (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DIGCTL_EMICLK_DELAY
+ * Address: 0x500
+ * SCT: no
+*/
+#define HW_DIGCTL_EMICLK_DELAY              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x500))
+#define BP_DIGCTL_EMICLK_DELAY_RSVD0        5
+#define BM_DIGCTL_EMICLK_DELAY_RSVD0        0xffffffe0
+#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v)     (((v) << 5) & 0xffffffe0)
+#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS     0
+#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS     0x1f
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)  (((v) << 0) & 0x1f)
+
+#endif /* __HEADERGEN__IMX233__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dram.h b/firmware/target/arm/imx233/regs/imx233/regs-dram.h
new file mode 100644
index 0000000000..144861d2fd
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-dram.h
@@ -0,0 +1,980 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__DRAM__H__
+#define __HEADERGEN__IMX233__DRAM__H__
+
+#define REGS_DRAM_BASE (0x800e0000)
+
+#define REGS_DRAM_VERSION "3.2.0"
+
+/**
+ * Register: HW_DRAM_CTL00
+ * Address: 0
+ * SCT: no
+*/
+#define HW_DRAM_CTL00                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0))
+#define BP_DRAM_CTL00_RSVD4                 25
+#define BM_DRAM_CTL00_RSVD4                 0xfe000000
+#define BF_DRAM_CTL00_RSVD4(v)              (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL00_AHB0_W_PRIORITY       24
+#define BM_DRAM_CTL00_AHB0_W_PRIORITY       0x1000000
+#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL00_RSVD3                 17
+#define BM_DRAM_CTL00_RSVD3                 0xfe0000
+#define BF_DRAM_CTL00_RSVD3(v)              (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL00_AHB0_R_PRIORITY       16
+#define BM_DRAM_CTL00_AHB0_R_PRIORITY       0x10000
+#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v)    (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL00_RSVD2                 9
+#define BM_DRAM_CTL00_RSVD2                 0xfe00
+#define BF_DRAM_CTL00_RSVD2(v)              (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG    8
+#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG    0x100
+#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100)
+#define BP_DRAM_CTL00_RSVD1                 1
+#define BM_DRAM_CTL00_RSVD1                 0xfe
+#define BF_DRAM_CTL00_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL00_ADDR_CMP_EN           0
+#define BM_DRAM_CTL00_ADDR_CMP_EN           0x1
+#define BF_DRAM_CTL00_ADDR_CMP_EN(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL01
+ * Address: 0x4
+ * SCT: no
+*/
+#define HW_DRAM_CTL01                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4))
+#define BP_DRAM_CTL01_RSVD4                 25
+#define BM_DRAM_CTL01_RSVD4                 0xfe000000
+#define BF_DRAM_CTL01_RSVD4(v)              (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG    24
+#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG    0x1000000
+#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL01_RSVD3                 17
+#define BM_DRAM_CTL01_RSVD3                 0xfe0000
+#define BF_DRAM_CTL01_RSVD3(v)              (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL01_AHB1_W_PRIORITY       16
+#define BM_DRAM_CTL01_AHB1_W_PRIORITY       0x10000
+#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v)    (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL01_RSVD2                 9
+#define BM_DRAM_CTL01_RSVD2                 0xfe00
+#define BF_DRAM_CTL01_RSVD2(v)              (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL01_AHB1_R_PRIORITY       8
+#define BM_DRAM_CTL01_AHB1_R_PRIORITY       0x100
+#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v)    (((v) << 8) & 0x100)
+#define BP_DRAM_CTL01_RSVD1                 1
+#define BM_DRAM_CTL01_RSVD1                 0xfe
+#define BF_DRAM_CTL01_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0
+#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0x1
+#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL02
+ * Address: 0x8
+ * SCT: no
+*/
+#define HW_DRAM_CTL02                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8))
+#define BP_DRAM_CTL02_RSVD4                 25
+#define BM_DRAM_CTL02_RSVD4                 0xfe000000
+#define BF_DRAM_CTL02_RSVD4(v)              (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL02_AHB3_R_PRIORITY       24
+#define BM_DRAM_CTL02_AHB3_R_PRIORITY       0x1000000
+#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL02_RSVD3                 17
+#define BM_DRAM_CTL02_RSVD3                 0xfe0000
+#define BF_DRAM_CTL02_RSVD3(v)              (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG    16
+#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG    0x10000
+#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL02_RSVD2                 9
+#define BM_DRAM_CTL02_RSVD2                 0xfe00
+#define BF_DRAM_CTL02_RSVD2(v)              (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL02_AHB2_W_PRIORITY       8
+#define BM_DRAM_CTL02_AHB2_W_PRIORITY       0x100
+#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v)    (((v) << 8) & 0x100)
+#define BP_DRAM_CTL02_RSVD1                 1
+#define BM_DRAM_CTL02_RSVD1                 0xfe
+#define BF_DRAM_CTL02_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL02_AHB2_R_PRIORITY       0
+#define BM_DRAM_CTL02_AHB2_R_PRIORITY       0x1
+#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL03
+ * Address: 0xc
+ * SCT: no
+*/
+#define HW_DRAM_CTL03                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc))
+#define BP_DRAM_CTL03_RSVD4                 25
+#define BM_DRAM_CTL03_RSVD4                 0xfe000000
+#define BF_DRAM_CTL03_RSVD4(v)              (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL03_AUTO_REFRESH_MODE     24
+#define BM_DRAM_CTL03_AUTO_REFRESH_MODE     0x1000000
+#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v)  (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL03_RSVD3                 17
+#define BM_DRAM_CTL03_RSVD3                 0xfe0000
+#define BF_DRAM_CTL03_RSVD3(v)              (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL03_AREFRESH              16
+#define BM_DRAM_CTL03_AREFRESH              0x10000
+#define BF_DRAM_CTL03_AREFRESH(v)           (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL03_RSVD2                 9
+#define BM_DRAM_CTL03_RSVD2                 0xfe00
+#define BF_DRAM_CTL03_RSVD2(v)              (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL03_AP                    8
+#define BM_DRAM_CTL03_AP                    0x100
+#define BF_DRAM_CTL03_AP(v)                 (((v) << 8) & 0x100)
+#define BP_DRAM_CTL03_RSVD1                 1
+#define BM_DRAM_CTL03_RSVD1                 0xfe
+#define BF_DRAM_CTL03_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL03_AHB3_W_PRIORITY       0
+#define BM_DRAM_CTL03_AHB3_W_PRIORITY       0x1
+#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL04
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DRAM_CTL04                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10))
+#define BP_DRAM_CTL04_RSVD4                 25
+#define BM_DRAM_CTL04_RSVD4                 0xfe000000
+#define BF_DRAM_CTL04_RSVD4(v)              (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL04_DLL_BYPASS_MODE       24
+#define BM_DRAM_CTL04_DLL_BYPASS_MODE       0x1000000
+#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL04_RSVD3                 17
+#define BM_DRAM_CTL04_RSVD3                 0xfe0000
+#define BF_DRAM_CTL04_RSVD3(v)              (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL04_DLLLOCKREG            16
+#define BM_DRAM_CTL04_DLLLOCKREG            0x10000
+#define BF_DRAM_CTL04_DLLLOCKREG(v)         (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL04_RSVD2                 9
+#define BM_DRAM_CTL04_RSVD2                 0xfe00
+#define BF_DRAM_CTL04_RSVD2(v)              (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL04_CONCURRENTAP          8
+#define BM_DRAM_CTL04_CONCURRENTAP          0x100
+#define BF_DRAM_CTL04_CONCURRENTAP(v)       (((v) << 8) & 0x100)
+#define BP_DRAM_CTL04_RSVD1                 1
+#define BM_DRAM_CTL04_RSVD1                 0xfe
+#define BF_DRAM_CTL04_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL04_BANK_SPLIT_EN         0
+#define BM_DRAM_CTL04_BANK_SPLIT_EN         0x1
+#define BF_DRAM_CTL04_BANK_SPLIT_EN(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL05
+ * Address: 0x14
+ * SCT: no
+*/
+#define HW_DRAM_CTL05                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14))
+#define BP_DRAM_CTL05_RSVD4                 25
+#define BM_DRAM_CTL05_RSVD4                 0xfe000000
+#define BF_DRAM_CTL05_RSVD4(v)              (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL05_INTRPTREADA           24
+#define BM_DRAM_CTL05_INTRPTREADA           0x1000000
+#define BF_DRAM_CTL05_INTRPTREADA(v)        (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL05_RSVD3                 17
+#define BM_DRAM_CTL05_RSVD3                 0xfe0000
+#define BF_DRAM_CTL05_RSVD3(v)              (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL05_INTRPTAPBURST         16
+#define BM_DRAM_CTL05_INTRPTAPBURST         0x10000
+#define BF_DRAM_CTL05_INTRPTAPBURST(v)      (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL05_RSVD2                 9
+#define BM_DRAM_CTL05_RSVD2                 0xfe00
+#define BF_DRAM_CTL05_RSVD2(v)              (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL05_FAST_WRITE            8
+#define BM_DRAM_CTL05_FAST_WRITE            0x100
+#define BF_DRAM_CTL05_FAST_WRITE(v)         (((v) << 8) & 0x100)
+#define BP_DRAM_CTL05_RSVD1                 1
+#define BM_DRAM_CTL05_RSVD1                 0xfe
+#define BF_DRAM_CTL05_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL05_EN_LOWPOWER_MODE      0
+#define BM_DRAM_CTL05_EN_LOWPOWER_MODE      0x1
+#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL06
+ * Address: 0x18
+ * SCT: no
+*/
+#define HW_DRAM_CTL06                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18))
+#define BP_DRAM_CTL06_RSVD4             25
+#define BM_DRAM_CTL06_RSVD4             0xfe000000
+#define BF_DRAM_CTL06_RSVD4(v)          (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL06_POWER_DOWN        24
+#define BM_DRAM_CTL06_POWER_DOWN        0x1000000
+#define BF_DRAM_CTL06_POWER_DOWN(v)     (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL06_RSVD3             17
+#define BM_DRAM_CTL06_RSVD3             0xfe0000
+#define BF_DRAM_CTL06_RSVD3(v)          (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL06_PLACEMENT_EN      16
+#define BM_DRAM_CTL06_PLACEMENT_EN      0x10000
+#define BF_DRAM_CTL06_PLACEMENT_EN(v)   (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL06_RSVD2             9
+#define BM_DRAM_CTL06_RSVD2             0xfe00
+#define BF_DRAM_CTL06_RSVD2(v)          (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL06_NO_CMD_INIT       8
+#define BM_DRAM_CTL06_NO_CMD_INIT       0x100
+#define BF_DRAM_CTL06_NO_CMD_INIT(v)    (((v) << 8) & 0x100)
+#define BP_DRAM_CTL06_RSVD1             1
+#define BM_DRAM_CTL06_RSVD1             0xfe
+#define BF_DRAM_CTL06_RSVD1(v)          (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL06_INTRPTWRITEA      0
+#define BM_DRAM_CTL06_INTRPTWRITEA      0x1
+#define BF_DRAM_CTL06_INTRPTWRITEA(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL07
+ * Address: 0x1c
+ * SCT: no
+*/
+#define HW_DRAM_CTL07                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c))
+#define BP_DRAM_CTL07_RSVD4                 25
+#define BM_DRAM_CTL07_RSVD4                 0xfe000000
+#define BF_DRAM_CTL07_RSVD4(v)              (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL07_RW_SAME_EN            24
+#define BM_DRAM_CTL07_RW_SAME_EN            0x1000000
+#define BF_DRAM_CTL07_RW_SAME_EN(v)         (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL07_RSVD3                 17
+#define BM_DRAM_CTL07_RSVD3                 0xfe0000
+#define BF_DRAM_CTL07_RSVD3(v)              (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL07_REG_DIMM_ENABLE       16
+#define BM_DRAM_CTL07_REG_DIMM_ENABLE       0x10000
+#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v)    (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL07_RSVD2                 9
+#define BM_DRAM_CTL07_RSVD2                 0xfe00
+#define BF_DRAM_CTL07_RSVD2(v)              (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL07_RD2RD_TURN            8
+#define BM_DRAM_CTL07_RD2RD_TURN            0x100
+#define BF_DRAM_CTL07_RD2RD_TURN(v)         (((v) << 8) & 0x100)
+#define BP_DRAM_CTL07_RSVD1                 1
+#define BM_DRAM_CTL07_RSVD1                 0xfe
+#define BF_DRAM_CTL07_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL07_PRIORITY_EN           0
+#define BM_DRAM_CTL07_PRIORITY_EN           0x1
+#define BF_DRAM_CTL07_PRIORITY_EN(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL08
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DRAM_CTL08                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20))
+#define BP_DRAM_CTL08_RSVD4             25
+#define BM_DRAM_CTL08_RSVD4             0xfe000000
+#define BF_DRAM_CTL08_RSVD4(v)          (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL08_TRAS_LOCKOUT      24
+#define BM_DRAM_CTL08_TRAS_LOCKOUT      0x1000000
+#define BF_DRAM_CTL08_TRAS_LOCKOUT(v)   (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL08_RSVD3             17
+#define BM_DRAM_CTL08_RSVD3             0xfe0000
+#define BF_DRAM_CTL08_RSVD3(v)          (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL08_START             16
+#define BM_DRAM_CTL08_START             0x10000
+#define BF_DRAM_CTL08_START(v)          (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL08_RSVD2             9
+#define BM_DRAM_CTL08_RSVD2             0xfe00
+#define BF_DRAM_CTL08_RSVD2(v)          (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL08_SREFRESH          8
+#define BM_DRAM_CTL08_SREFRESH          0x100
+#define BF_DRAM_CTL08_SREFRESH(v)       (((v) << 8) & 0x100)
+#define BP_DRAM_CTL08_RSVD1             1
+#define BM_DRAM_CTL08_RSVD1             0xfe
+#define BF_DRAM_CTL08_RSVD1(v)          (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL08_SDR_MODE          0
+#define BM_DRAM_CTL08_SDR_MODE          0x1
+#define BF_DRAM_CTL08_SDR_MODE(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL09
+ * Address: 0x24
+ * SCT: no
+*/
+#define HW_DRAM_CTL09                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24))
+#define BP_DRAM_CTL09_RSVD4                     26
+#define BM_DRAM_CTL09_RSVD4                     0xfc000000
+#define BF_DRAM_CTL09_RSVD4(v)                  (((v) << 26) & 0xfc000000)
+#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE         24
+#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE         0x3000000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)      (((v) << 24) & 0x3000000)
+#define BP_DRAM_CTL09_RSVD3                     18
+#define BM_DRAM_CTL09_RSVD3                     0xfc0000
+#define BF_DRAM_CTL09_RSVD3(v)                  (((v) << 18) & 0xfc0000)
+#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    16
+#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    0x30000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000)
+#define BP_DRAM_CTL09_RSVD2                     9
+#define BM_DRAM_CTL09_RSVD2                     0xfe00
+#define BF_DRAM_CTL09_RSVD2(v)                  (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL09_WRITE_MODEREG             8
+#define BM_DRAM_CTL09_WRITE_MODEREG             0x100
+#define BF_DRAM_CTL09_WRITE_MODEREG(v)          (((v) << 8) & 0x100)
+#define BP_DRAM_CTL09_RSVD1                     1
+#define BM_DRAM_CTL09_RSVD1                     0xfe
+#define BF_DRAM_CTL09_RSVD1(v)                  (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL09_WRITEINTERP               0
+#define BM_DRAM_CTL09_WRITEINTERP               0x1
+#define BF_DRAM_CTL09_WRITEINTERP(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL10
+ * Address: 0x28
+ * SCT: no
+*/
+#define HW_DRAM_CTL10               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28))
+#define BP_DRAM_CTL10_RSVD4         27
+#define BM_DRAM_CTL10_RSVD4         0xf8000000
+#define BF_DRAM_CTL10_RSVD4(v)      (((v) << 27) & 0xf8000000)
+#define BP_DRAM_CTL10_AGE_COUNT     24
+#define BM_DRAM_CTL10_AGE_COUNT     0x7000000
+#define BF_DRAM_CTL10_AGE_COUNT(v)  (((v) << 24) & 0x7000000)
+#define BP_DRAM_CTL10_RSVD3         19
+#define BM_DRAM_CTL10_RSVD3         0xf80000
+#define BF_DRAM_CTL10_RSVD3(v)      (((v) << 19) & 0xf80000)
+#define BP_DRAM_CTL10_ADDR_PINS     16
+#define BM_DRAM_CTL10_ADDR_PINS     0x70000
+#define BF_DRAM_CTL10_ADDR_PINS(v)  (((v) << 16) & 0x70000)
+#define BP_DRAM_CTL10_RSVD2         10
+#define BM_DRAM_CTL10_RSVD2         0xfc00
+#define BF_DRAM_CTL10_RSVD2(v)      (((v) << 10) & 0xfc00)
+#define BP_DRAM_CTL10_TEMRS         8
+#define BM_DRAM_CTL10_TEMRS         0x300
+#define BF_DRAM_CTL10_TEMRS(v)      (((v) << 8) & 0x300)
+#define BP_DRAM_CTL10_RSVD1         2
+#define BM_DRAM_CTL10_RSVD1         0xfc
+#define BF_DRAM_CTL10_RSVD1(v)      (((v) << 2) & 0xfc)
+#define BP_DRAM_CTL10_Q_FULLNESS    0
+#define BM_DRAM_CTL10_Q_FULLNESS    0x3
+#define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DRAM_CTL11
+ * Address: 0x2c
+ * SCT: no
+*/
+#define HW_DRAM_CTL11                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c))
+#define BP_DRAM_CTL11_RSVD4                 27
+#define BM_DRAM_CTL11_RSVD4                 0xf8000000
+#define BF_DRAM_CTL11_RSVD4(v)              (((v) << 27) & 0xf8000000)
+#define BP_DRAM_CTL11_MAX_CS_REG            24
+#define BM_DRAM_CTL11_MAX_CS_REG            0x7000000
+#define BF_DRAM_CTL11_MAX_CS_REG(v)         (((v) << 24) & 0x7000000)
+#define BP_DRAM_CTL11_RSVD3                 19
+#define BM_DRAM_CTL11_RSVD3                 0xf80000
+#define BF_DRAM_CTL11_RSVD3(v)              (((v) << 19) & 0xf80000)
+#define BP_DRAM_CTL11_COMMAND_AGE_COUNT     16
+#define BM_DRAM_CTL11_COMMAND_AGE_COUNT     0x70000
+#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v)  (((v) << 16) & 0x70000)
+#define BP_DRAM_CTL11_RSVD2                 11
+#define BM_DRAM_CTL11_RSVD2                 0xf800
+#define BF_DRAM_CTL11_RSVD2(v)              (((v) << 11) & 0xf800)
+#define BP_DRAM_CTL11_COLUMN_SIZE           8
+#define BM_DRAM_CTL11_COLUMN_SIZE           0x700
+#define BF_DRAM_CTL11_COLUMN_SIZE(v)        (((v) << 8) & 0x700)
+#define BP_DRAM_CTL11_RSVD1                 3
+#define BM_DRAM_CTL11_RSVD1                 0xf8
+#define BF_DRAM_CTL11_RSVD1(v)              (((v) << 3) & 0xf8)
+#define BP_DRAM_CTL11_CASLAT                0
+#define BM_DRAM_CTL11_CASLAT                0x7
+#define BF_DRAM_CTL11_CASLAT(v)             (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_DRAM_CTL12
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_DRAM_CTL12               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30))
+#define BP_DRAM_CTL12_RSVD3         27
+#define BM_DRAM_CTL12_RSVD3         0xf8000000
+#define BF_DRAM_CTL12_RSVD3(v)      (((v) << 27) & 0xf8000000)
+#define BP_DRAM_CTL12_TWR_INT       24
+#define BM_DRAM_CTL12_TWR_INT       0x7000000
+#define BF_DRAM_CTL12_TWR_INT(v)    (((v) << 24) & 0x7000000)
+#define BP_DRAM_CTL12_RSVD2         19
+#define BM_DRAM_CTL12_RSVD2         0xf80000
+#define BF_DRAM_CTL12_RSVD2(v)      (((v) << 19) & 0xf80000)
+#define BP_DRAM_CTL12_TRRD          16
+#define BM_DRAM_CTL12_TRRD          0x70000
+#define BF_DRAM_CTL12_TRRD(v)       (((v) << 16) & 0x70000)
+#define BP_DRAM_CTL12_OBSOLETE      8
+#define BM_DRAM_CTL12_OBSOLETE      0xff00
+#define BF_DRAM_CTL12_OBSOLETE(v)   (((v) << 8) & 0xff00)
+#define BP_DRAM_CTL12_RSVD1         3
+#define BM_DRAM_CTL12_RSVD1         0xf8
+#define BF_DRAM_CTL12_RSVD1(v)      (((v) << 3) & 0xf8)
+#define BP_DRAM_CTL12_TCKE          0
+#define BM_DRAM_CTL12_TCKE          0x7
+#define BF_DRAM_CTL12_TCKE(v)       (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_DRAM_CTL13
+ * Address: 0x34
+ * SCT: no
+*/
+#define HW_DRAM_CTL13                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34))
+#define BP_DRAM_CTL13_RSVD4                 28
+#define BM_DRAM_CTL13_RSVD4                 0xf0000000
+#define BF_DRAM_CTL13_RSVD4(v)              (((v) << 28) & 0xf0000000)
+#define BP_DRAM_CTL13_CASLAT_LIN_GATE       24
+#define BM_DRAM_CTL13_CASLAT_LIN_GATE       0xf000000
+#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v)    (((v) << 24) & 0xf000000)
+#define BP_DRAM_CTL13_RSVD3                 20
+#define BM_DRAM_CTL13_RSVD3                 0xf00000
+#define BF_DRAM_CTL13_RSVD3(v)              (((v) << 20) & 0xf00000)
+#define BP_DRAM_CTL13_CASLAT_LIN            16
+#define BM_DRAM_CTL13_CASLAT_LIN            0xf0000
+#define BF_DRAM_CTL13_CASLAT_LIN(v)         (((v) << 16) & 0xf0000)
+#define BP_DRAM_CTL13_RSVD2                 12
+#define BM_DRAM_CTL13_RSVD2                 0xf000
+#define BF_DRAM_CTL13_RSVD2(v)              (((v) << 12) & 0xf000)
+#define BP_DRAM_CTL13_APREBIT               8
+#define BM_DRAM_CTL13_APREBIT               0xf00
+#define BF_DRAM_CTL13_APREBIT(v)            (((v) << 8) & 0xf00)
+#define BP_DRAM_CTL13_RSVD1                 3
+#define BM_DRAM_CTL13_RSVD1                 0xf8
+#define BF_DRAM_CTL13_RSVD1(v)              (((v) << 3) & 0xf8)
+#define BP_DRAM_CTL13_TWTR                  0
+#define BM_DRAM_CTL13_TWTR                  0x7
+#define BF_DRAM_CTL13_TWTR(v)               (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_DRAM_CTL14
+ * Address: 0x38
+ * SCT: no
+*/
+#define HW_DRAM_CTL14                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38))
+#define BP_DRAM_CTL14_RSVD4                         28
+#define BM_DRAM_CTL14_RSVD4                         0xf0000000
+#define BF_DRAM_CTL14_RSVD4(v)                      (((v) << 28) & 0xf0000000)
+#define BP_DRAM_CTL14_MAX_COL_REG                   24
+#define BM_DRAM_CTL14_MAX_COL_REG                   0xf000000
+#define BF_DRAM_CTL14_MAX_COL_REG(v)                (((v) << 24) & 0xf000000)
+#define BP_DRAM_CTL14_RSVD3                         20
+#define BM_DRAM_CTL14_RSVD3                         0xf00000
+#define BF_DRAM_CTL14_RSVD3(v)                      (((v) << 20) & 0xf00000)
+#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       16
+#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       0xf0000
+#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)    (((v) << 16) & 0xf0000)
+#define BP_DRAM_CTL14_RSVD2                         12
+#define BM_DRAM_CTL14_RSVD2                         0xf000
+#define BF_DRAM_CTL14_RSVD2(v)                      (((v) << 12) & 0xf000)
+#define BP_DRAM_CTL14_INITAREF                      8
+#define BM_DRAM_CTL14_INITAREF                      0xf00
+#define BF_DRAM_CTL14_INITAREF(v)                   (((v) << 8) & 0xf00)
+#define BP_DRAM_CTL14_RSVD1                         4
+#define BM_DRAM_CTL14_RSVD1                         0xf0
+#define BF_DRAM_CTL14_RSVD1(v)                      (((v) << 4) & 0xf0)
+#define BP_DRAM_CTL14_CS_MAP                        0
+#define BM_DRAM_CTL14_CS_MAP                        0xf
+#define BF_DRAM_CTL14_CS_MAP(v)                     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DRAM_CTL15
+ * Address: 0x3c
+ * SCT: no
+*/
+#define HW_DRAM_CTL15                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c))
+#define BP_DRAM_CTL15_RSVD4             28
+#define BM_DRAM_CTL15_RSVD4             0xf0000000
+#define BF_DRAM_CTL15_RSVD4(v)          (((v) << 28) & 0xf0000000)
+#define BP_DRAM_CTL15_TRP               24
+#define BM_DRAM_CTL15_TRP               0xf000000
+#define BF_DRAM_CTL15_TRP(v)            (((v) << 24) & 0xf000000)
+#define BP_DRAM_CTL15_RSVD3             20
+#define BM_DRAM_CTL15_RSVD3             0xf00000
+#define BF_DRAM_CTL15_RSVD3(v)          (((v) << 20) & 0xf00000)
+#define BP_DRAM_CTL15_TDAL              16
+#define BM_DRAM_CTL15_TDAL              0xf0000
+#define BF_DRAM_CTL15_TDAL(v)           (((v) << 16) & 0xf0000)
+#define BP_DRAM_CTL15_RSVD2             12
+#define BM_DRAM_CTL15_RSVD2             0xf000
+#define BF_DRAM_CTL15_RSVD2(v)          (((v) << 12) & 0xf000)
+#define BP_DRAM_CTL15_PORT_BUSY         8
+#define BM_DRAM_CTL15_PORT_BUSY         0xf00
+#define BF_DRAM_CTL15_PORT_BUSY(v)      (((v) << 8) & 0xf00)
+#define BP_DRAM_CTL15_RSVD1             4
+#define BM_DRAM_CTL15_RSVD1             0xf0
+#define BF_DRAM_CTL15_RSVD1(v)          (((v) << 4) & 0xf0)
+#define BP_DRAM_CTL15_MAX_ROW_REG       0
+#define BM_DRAM_CTL15_MAX_ROW_REG       0xf
+#define BF_DRAM_CTL15_MAX_ROW_REG(v)    (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DRAM_CTL16
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_DRAM_CTL16                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40))
+#define BP_DRAM_CTL16_RSVD4                     29
+#define BM_DRAM_CTL16_RSVD4                     0xe0000000
+#define BF_DRAM_CTL16_RSVD4(v)                  (((v) << 29) & 0xe0000000)
+#define BP_DRAM_CTL16_TMRD                      24
+#define BM_DRAM_CTL16_TMRD                      0x1f000000
+#define BF_DRAM_CTL16_TMRD(v)                   (((v) << 24) & 0x1f000000)
+#define BP_DRAM_CTL16_RSVD3                     21
+#define BM_DRAM_CTL16_RSVD3                     0xe00000
+#define BF_DRAM_CTL16_RSVD3(v)                  (((v) << 21) & 0xe00000)
+#define BP_DRAM_CTL16_LOWPOWER_CONTROL          16
+#define BM_DRAM_CTL16_LOWPOWER_CONTROL          0x1f0000
+#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v)       (((v) << 16) & 0x1f0000)
+#define BP_DRAM_CTL16_RSVD2                     13
+#define BM_DRAM_CTL16_RSVD2                     0xe000
+#define BF_DRAM_CTL16_RSVD2(v)                  (((v) << 13) & 0xe000)
+#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      8
+#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      0x1f00
+#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)   (((v) << 8) & 0x1f00)
+#define BP_DRAM_CTL16_RSVD1                     4
+#define BM_DRAM_CTL16_RSVD1                     0xf0
+#define BF_DRAM_CTL16_RSVD1(v)                  (((v) << 4) & 0xf0)
+#define BP_DRAM_CTL16_INT_ACK                   0
+#define BM_DRAM_CTL16_INT_ACK                   0xf
+#define BF_DRAM_CTL16_INT_ACK(v)                (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DRAM_CTL17
+ * Address: 0x44
+ * SCT: no
+*/
+#define HW_DRAM_CTL17                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44))
+#define BP_DRAM_CTL17_DLL_START_POINT       24
+#define BM_DRAM_CTL17_DLL_START_POINT       0xff000000
+#define BF_DRAM_CTL17_DLL_START_POINT(v)    (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL17_DLL_LOCK              16
+#define BM_DRAM_CTL17_DLL_LOCK              0xff0000
+#define BF_DRAM_CTL17_DLL_LOCK(v)           (((v) << 16) & 0xff0000)
+#define BP_DRAM_CTL17_DLL_INCREMENT         8
+#define BM_DRAM_CTL17_DLL_INCREMENT         0xff00
+#define BF_DRAM_CTL17_DLL_INCREMENT(v)      (((v) << 8) & 0xff00)
+#define BP_DRAM_CTL17_RSVD1                 5
+#define BM_DRAM_CTL17_RSVD1                 0xe0
+#define BF_DRAM_CTL17_RSVD1(v)              (((v) << 5) & 0xe0)
+#define BP_DRAM_CTL17_TRC                   0
+#define BM_DRAM_CTL17_TRC                   0x1f
+#define BF_DRAM_CTL17_TRC(v)                (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DRAM_CTL18
+ * Address: 0x48
+ * SCT: no
+*/
+#define HW_DRAM_CTL18                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48))
+#define BP_DRAM_CTL18_RSVD4                 31
+#define BM_DRAM_CTL18_RSVD4                 0x80000000
+#define BF_DRAM_CTL18_RSVD4(v)              (((v) << 31) & 0x80000000)
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_1       24
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_1       0x7f000000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v)    (((v) << 24) & 0x7f000000)
+#define BP_DRAM_CTL18_RSVD3                 23
+#define BM_DRAM_CTL18_RSVD3                 0x800000
+#define BF_DRAM_CTL18_RSVD3(v)              (((v) << 23) & 0x800000)
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_0       16
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_0       0x7f0000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v)    (((v) << 16) & 0x7f0000)
+#define BP_DRAM_CTL18_RSVD2                 13
+#define BM_DRAM_CTL18_RSVD2                 0xe000
+#define BF_DRAM_CTL18_RSVD2(v)              (((v) << 13) & 0xe000)
+#define BP_DRAM_CTL18_INT_STATUS            8
+#define BM_DRAM_CTL18_INT_STATUS            0x1f00
+#define BF_DRAM_CTL18_INT_STATUS(v)         (((v) << 8) & 0x1f00)
+#define BP_DRAM_CTL18_RSVD1                 5
+#define BM_DRAM_CTL18_RSVD1                 0xe0
+#define BF_DRAM_CTL18_RSVD1(v)              (((v) << 5) & 0xe0)
+#define BP_DRAM_CTL18_INT_MASK              0
+#define BM_DRAM_CTL18_INT_MASK              0x1f
+#define BF_DRAM_CTL18_INT_MASK(v)           (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DRAM_CTL19
+ * Address: 0x4c
+ * SCT: no
+*/
+#define HW_DRAM_CTL19                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c))
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      24
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      0xff000000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)   (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL19_RSVD1                     23
+#define BM_DRAM_CTL19_RSVD1                     0x800000
+#define BF_DRAM_CTL19_RSVD1(v)                  (((v) << 23) & 0x800000)
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT             16
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT             0x7f0000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v)          (((v) << 16) & 0x7f0000)
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    8
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    0xff00
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00)
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0xff
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DRAM_CTL20
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_DRAM_CTL20                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50))
+#define BP_DRAM_CTL20_TRCD_INT                  24
+#define BM_DRAM_CTL20_TRCD_INT                  0xff000000
+#define BF_DRAM_CTL20_TRCD_INT(v)               (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL20_TRAS_MIN                  16
+#define BM_DRAM_CTL20_TRAS_MIN                  0xff0000
+#define BF_DRAM_CTL20_TRAS_MIN(v)               (((v) << 16) & 0xff0000)
+#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       8
+#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       0xff00
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)    (((v) << 8) & 0xff00)
+#define BP_DRAM_CTL20_RSVD1                     7
+#define BM_DRAM_CTL20_RSVD1                     0x80
+#define BF_DRAM_CTL20_RSVD1(v)                  (((v) << 7) & 0x80)
+#define BP_DRAM_CTL20_WR_DQS_SHIFT              0
+#define BM_DRAM_CTL20_WR_DQS_SHIFT              0x7f
+#define BF_DRAM_CTL20_WR_DQS_SHIFT(v)           (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_DRAM_CTL21
+ * Address: 0x54
+ * SCT: no
+*/
+#define HW_DRAM_CTL21                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54))
+#define BP_DRAM_CTL21_OBSOLETE                  24
+#define BM_DRAM_CTL21_OBSOLETE                  0xff000000
+#define BF_DRAM_CTL21_OBSOLETE(v)               (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL21_RSVD1                     18
+#define BM_DRAM_CTL21_RSVD1                     0xfc0000
+#define BF_DRAM_CTL21_RSVD1(v)                  (((v) << 18) & 0xfc0000)
+#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH       8
+#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH       0x3ff00
+#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)    (((v) << 8) & 0x3ff00)
+#define BP_DRAM_CTL21_TRFC                      0
+#define BM_DRAM_CTL21_TRFC                      0xff
+#define BF_DRAM_CTL21_TRFC(v)                   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DRAM_CTL22
+ * Address: 0x58
+ * SCT: no
+*/
+#define HW_DRAM_CTL22               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58))
+#define BP_DRAM_CTL22_RSVD2         27
+#define BM_DRAM_CTL22_RSVD2         0xf8000000
+#define BF_DRAM_CTL22_RSVD2(v)      (((v) << 27) & 0xf8000000)
+#define BP_DRAM_CTL22_AHB0_WRCNT    16
+#define BM_DRAM_CTL22_AHB0_WRCNT    0x7ff0000
+#define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL22_RSVD1         11
+#define BM_DRAM_CTL22_RSVD1         0xf800
+#define BF_DRAM_CTL22_RSVD1(v)      (((v) << 11) & 0xf800)
+#define BP_DRAM_CTL22_AHB0_RDCNT    0
+#define BM_DRAM_CTL22_AHB0_RDCNT    0x7ff
+#define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL23
+ * Address: 0x5c
+ * SCT: no
+*/
+#define HW_DRAM_CTL23               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c))
+#define BP_DRAM_CTL23_RSVD2         27
+#define BM_DRAM_CTL23_RSVD2         0xf8000000
+#define BF_DRAM_CTL23_RSVD2(v)      (((v) << 27) & 0xf8000000)
+#define BP_DRAM_CTL23_AHB1_WRCNT    16
+#define BM_DRAM_CTL23_AHB1_WRCNT    0x7ff0000
+#define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL23_RSVD1         11
+#define BM_DRAM_CTL23_RSVD1         0xf800
+#define BF_DRAM_CTL23_RSVD1(v)      (((v) << 11) & 0xf800)
+#define BP_DRAM_CTL23_AHB1_RDCNT    0
+#define BM_DRAM_CTL23_AHB1_RDCNT    0x7ff
+#define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL24
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DRAM_CTL24               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60))
+#define BP_DRAM_CTL24_RSVD2         27
+#define BM_DRAM_CTL24_RSVD2         0xf8000000
+#define BF_DRAM_CTL24_RSVD2(v)      (((v) << 27) & 0xf8000000)
+#define BP_DRAM_CTL24_AHB2_WRCNT    16
+#define BM_DRAM_CTL24_AHB2_WRCNT    0x7ff0000
+#define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL24_RSVD1         11
+#define BM_DRAM_CTL24_RSVD1         0xf800
+#define BF_DRAM_CTL24_RSVD1(v)      (((v) << 11) & 0xf800)
+#define BP_DRAM_CTL24_AHB2_RDCNT    0
+#define BM_DRAM_CTL24_AHB2_RDCNT    0x7ff
+#define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL25
+ * Address: 0x64
+ * SCT: no
+*/
+#define HW_DRAM_CTL25               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64))
+#define BP_DRAM_CTL25_RSVD2         27
+#define BM_DRAM_CTL25_RSVD2         0xf8000000
+#define BF_DRAM_CTL25_RSVD2(v)      (((v) << 27) & 0xf8000000)
+#define BP_DRAM_CTL25_AHB3_WRCNT    16
+#define BM_DRAM_CTL25_AHB3_WRCNT    0x7ff0000
+#define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL25_RSVD1         11
+#define BM_DRAM_CTL25_RSVD1         0xf800
+#define BF_DRAM_CTL25_RSVD1(v)      (((v) << 11) & 0xf800)
+#define BP_DRAM_CTL25_AHB3_RDCNT    0
+#define BM_DRAM_CTL25_AHB3_RDCNT    0x7ff
+#define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL26
+ * Address: 0x68
+ * SCT: no
+*/
+#define HW_DRAM_CTL26               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68))
+#define BP_DRAM_CTL26_OBSOLETE      16
+#define BM_DRAM_CTL26_OBSOLETE      0xffff0000
+#define BF_DRAM_CTL26_OBSOLETE(v)   (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL26_RSVD1         12
+#define BM_DRAM_CTL26_RSVD1         0xf000
+#define BF_DRAM_CTL26_RSVD1(v)      (((v) << 12) & 0xf000)
+#define BP_DRAM_CTL26_TREF          0
+#define BM_DRAM_CTL26_TREF          0xfff
+#define BF_DRAM_CTL26_TREF(v)       (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DRAM_CTL27
+ * Address: 0x6c
+ * SCT: no
+*/
+#define HW_DRAM_CTL27               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c))
+#define BP_DRAM_CTL27_OBSOLETE      0
+#define BM_DRAM_CTL27_OBSOLETE      0xffffffff
+#define BF_DRAM_CTL27_OBSOLETE(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DRAM_CTL28
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_DRAM_CTL28               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70))
+#define BP_DRAM_CTL28_OBSOLETE      0
+#define BM_DRAM_CTL28_OBSOLETE      0xffffffff
+#define BF_DRAM_CTL28_OBSOLETE(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DRAM_CTL29
+ * Address: 0x74
+ * SCT: no
+*/
+#define HW_DRAM_CTL29                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74))
+#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     16
+#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     0xffff0000
+#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)  (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0
+#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0xffff
+#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL30
+ * Address: 0x78
+ * SCT: no
+*/
+#define HW_DRAM_CTL30                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78))
+#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         16
+#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         0xffff0000
+#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)      (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0
+#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0xffff
+#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL31
+ * Address: 0x7c
+ * SCT: no
+*/
+#define HW_DRAM_CTL31                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c))
+#define BP_DRAM_CTL31_TDLL                          16
+#define BM_DRAM_CTL31_TDLL                          0xffff0000
+#define BF_DRAM_CTL31_TDLL(v)                       (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0
+#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0xffff
+#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL32
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_DRAM_CTL32               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80))
+#define BP_DRAM_CTL32_TXSNR         16
+#define BM_DRAM_CTL32_TXSNR         0xffff0000
+#define BF_DRAM_CTL32_TXSNR(v)      (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL32_TRAS_MAX      0
+#define BM_DRAM_CTL32_TRAS_MAX      0xffff
+#define BF_DRAM_CTL32_TRAS_MAX(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL33
+ * Address: 0x84
+ * SCT: no
+*/
+#define HW_DRAM_CTL33               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84))
+#define BP_DRAM_CTL33_VERSION       16
+#define BM_DRAM_CTL33_VERSION       0xffff0000
+#define BF_DRAM_CTL33_VERSION(v)    (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL33_TXSR          0
+#define BM_DRAM_CTL33_TXSR          0xffff
+#define BF_DRAM_CTL33_TXSR(v)       (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL34
+ * Address: 0x88
+ * SCT: no
+*/
+#define HW_DRAM_CTL34           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88))
+#define BP_DRAM_CTL34_RSVD1     24
+#define BM_DRAM_CTL34_RSVD1     0xff000000
+#define BF_DRAM_CTL34_RSVD1(v)  (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL34_TINIT     0
+#define BM_DRAM_CTL34_TINIT     0xffffff
+#define BF_DRAM_CTL34_TINIT(v)  (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_DRAM_CTL35
+ * Address: 0x8c
+ * SCT: no
+*/
+#define HW_DRAM_CTL35                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c))
+#define BP_DRAM_CTL35_RSVD1                 31
+#define BM_DRAM_CTL35_RSVD1                 0x80000000
+#define BF_DRAM_CTL35_RSVD1(v)              (((v) << 31) & 0x80000000)
+#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR     0
+#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR     0x7fffffff
+#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)  (((v) << 0) & 0x7fffffff)
+
+/**
+ * Register: HW_DRAM_CTL36
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DRAM_CTL36                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90))
+#define BP_DRAM_CTL36_RSVD4                     25
+#define BM_DRAM_CTL36_RSVD4                     0xfe000000
+#define BF_DRAM_CTL36_RSVD4(v)                  (((v) << 25) & 0xfe000000)
+#define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT       24
+#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT       0x1000000
+#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL36_RSVD3                     17
+#define BM_DRAM_CTL36_RSVD3                     0xfe0000
+#define BF_DRAM_CTL36_RSVD3(v)                  (((v) << 17) & 0xfe0000)
+#define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH     16
+#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH     0x10000
+#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)  (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL36_RSVD2                     9
+#define BM_DRAM_CTL36_RSVD2                     0xfe00
+#define BF_DRAM_CTL36_RSVD2(v)                  (((v) << 9) & 0xfe00)
+#define BP_DRAM_CTL36_BUS_SHARE_ENABLE          8
+#define BM_DRAM_CTL36_BUS_SHARE_ENABLE          0x100
+#define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v)       (((v) << 8) & 0x100)
+#define BP_DRAM_CTL36_RSVD1                     1
+#define BM_DRAM_CTL36_RSVD1                     0xfe
+#define BF_DRAM_CTL36_RSVD1(v)                  (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL36_ACTIVE_AGING              0
+#define BM_DRAM_CTL36_ACTIVE_AGING              0x1
+#define BF_DRAM_CTL36_ACTIVE_AGING(v)           (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL37
+ * Address: 0x94
+ * SCT: no
+*/
+#define HW_DRAM_CTL37                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94))
+#define BP_DRAM_CTL37_OBSOLETE              24
+#define BM_DRAM_CTL37_OBSOLETE              0xff000000
+#define BF_DRAM_CTL37_OBSOLETE(v)           (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL37_RSVD2                 18
+#define BM_DRAM_CTL37_RSVD2                 0xfc0000
+#define BF_DRAM_CTL37_RSVD2(v)              (((v) << 18) & 0xfc0000)
+#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT     8
+#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT     0x3ff00
+#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)  (((v) << 8) & 0x3ff00)
+#define BP_DRAM_CTL37_RSVD1                 1
+#define BM_DRAM_CTL37_RSVD1                 0xfe
+#define BF_DRAM_CTL37_RSVD1(v)              (((v) << 1) & 0xfe)
+#define BP_DRAM_CTL37_TREF_ENABLE           0
+#define BM_DRAM_CTL37_TREF_ENABLE           0x1
+#define BF_DRAM_CTL37_TREF_ENABLE(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL38
+ * Address: 0x98
+ * SCT: no
+*/
+#define HW_DRAM_CTL38                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98))
+#define BP_DRAM_CTL38_RSVD2             29
+#define BM_DRAM_CTL38_RSVD2             0xe0000000
+#define BF_DRAM_CTL38_RSVD2(v)          (((v) << 29) & 0xe0000000)
+#define BP_DRAM_CTL38_EMRS2_DATA_0      16
+#define BM_DRAM_CTL38_EMRS2_DATA_0      0x1fff0000
+#define BF_DRAM_CTL38_EMRS2_DATA_0(v)   (((v) << 16) & 0x1fff0000)
+#define BP_DRAM_CTL38_RSVD1             13
+#define BM_DRAM_CTL38_RSVD1             0xe000
+#define BF_DRAM_CTL38_RSVD1(v)          (((v) << 13) & 0xe000)
+#define BP_DRAM_CTL38_EMRS1_DATA        0
+#define BM_DRAM_CTL38_EMRS1_DATA        0x1fff
+#define BF_DRAM_CTL38_EMRS1_DATA(v)     (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DRAM_CTL39
+ * Address: 0x9c
+ * SCT: no
+*/
+#define HW_DRAM_CTL39                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c))
+#define BP_DRAM_CTL39_RSVD2             29
+#define BM_DRAM_CTL39_RSVD2             0xe0000000
+#define BF_DRAM_CTL39_RSVD2(v)          (((v) << 29) & 0xe0000000)
+#define BP_DRAM_CTL39_EMRS2_DATA_2      16
+#define BM_DRAM_CTL39_EMRS2_DATA_2      0x1fff0000
+#define BF_DRAM_CTL39_EMRS2_DATA_2(v)   (((v) << 16) & 0x1fff0000)
+#define BP_DRAM_CTL39_RSVD1             13
+#define BM_DRAM_CTL39_RSVD1             0xe000
+#define BF_DRAM_CTL39_RSVD1(v)          (((v) << 13) & 0xe000)
+#define BP_DRAM_CTL39_EMRS2_DATA_1      0
+#define BM_DRAM_CTL39_EMRS2_DATA_1      0x1fff
+#define BF_DRAM_CTL39_EMRS2_DATA_1(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DRAM_CTL40
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DRAM_CTL40                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0))
+#define BP_DRAM_CTL40_TPDEX             16
+#define BM_DRAM_CTL40_TPDEX             0xffff0000
+#define BF_DRAM_CTL40_TPDEX(v)          (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL40_RSVD1             13
+#define BM_DRAM_CTL40_RSVD1             0xe000
+#define BF_DRAM_CTL40_RSVD1(v)          (((v) << 13) & 0xe000)
+#define BP_DRAM_CTL40_EMRS2_DATA_3      0
+#define BM_DRAM_CTL40_EMRS2_DATA_3      0x1fff
+#define BF_DRAM_CTL40_EMRS2_DATA_3(v)   (((v) << 0) & 0x1fff)
+
+#endif /* __HEADERGEN__IMX233__DRAM__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-dri.h b/firmware/target/arm/imx233/regs/imx233/regs-dri.h
new file mode 100644
index 0000000000..4802b28c12
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-dri.h
@@ -0,0 +1,304 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__DRI__H__
+#define __HEADERGEN__IMX233__DRI__H__
+
+#define REGS_DRI_BASE (0x80074000)
+
+#define REGS_DRI_VERSION "3.2.0"
+
+/**
+ * Register: HW_DRI_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DRI_CTRL                                     (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
+#define HW_DRI_CTRL_SET                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
+#define HW_DRI_CTRL_CLR                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
+#define HW_DRI_CTRL_TOG                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
+#define BP_DRI_CTRL_SFTRST                              31
+#define BM_DRI_CTRL_SFTRST                              0x80000000
+#define BV_DRI_CTRL_SFTRST__RUN                         0x0
+#define BV_DRI_CTRL_SFTRST__RESET                       0x1
+#define BF_DRI_CTRL_SFTRST(v)                           (((v) << 31) & 0x80000000)
+#define BF_DRI_CTRL_SFTRST_V(v)                         ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_DRI_CTRL_CLKGATE                             30
+#define BM_DRI_CTRL_CLKGATE                             0x40000000
+#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
+#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
+#define BF_DRI_CTRL_CLKGATE(v)                          (((v) << 30) & 0x40000000)
+#define BF_DRI_CTRL_CLKGATE_V(v)                        ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_DRI_CTRL_ENABLE_INPUTS                       29
+#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
+#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
+#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
+#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) << 29) & 0x20000000)
+#define BF_DRI_CTRL_ENABLE_INPUTS_V(v)                  ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
+#define BP_DRI_CTRL_RSVD4                               27
+#define BM_DRI_CTRL_RSVD4                               0x18000000
+#define BF_DRI_CTRL_RSVD4(v)                            (((v) << 27) & 0x18000000)
+#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
+#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) << 26) & 0x4000000)
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
+#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
+#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) << 25) & 0x2000000)
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
+#define BP_DRI_CTRL_RSVD3                               21
+#define BM_DRI_CTRL_RSVD3                               0x1e00000
+#define BF_DRI_CTRL_RSVD3(v)                            (((v) << 21) & 0x1e00000)
+#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
+#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
+#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) << 16) & 0x1f0000)
+#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
+#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
+#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) << 15) & 0x8000)
+#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v)                ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
+#define BP_DRI_CTRL_RSVD2                               12
+#define BM_DRI_CTRL_RSVD2                               0x7000
+#define BF_DRI_CTRL_RSVD2(v)                            (((v) << 12) & 0x7000)
+#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
+#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) << 11) & 0x800)
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)                ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) << 10) & 0x400)
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)         ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
+#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
+#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) << 9) & 0x200)
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v)               ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
+#define BP_DRI_CTRL_RSVD1                               4
+#define BM_DRI_CTRL_RSVD1                               0x1f0
+#define BF_DRI_CTRL_RSVD1(v)                            (((v) << 4) & 0x1f0)
+#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
+#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
+#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) << 3) & 0x8)
+#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v)                   ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) << 2) & 0x4)
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)            ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
+#define BP_DRI_CTRL_ATTENTION_IRQ                       1
+#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
+#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) << 1) & 0x2)
+#define BF_DRI_CTRL_ATTENTION_IRQ_V(v)                  ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
+#define BP_DRI_CTRL_RUN                                 0
+#define BM_DRI_CTRL_RUN                                 0x1
+#define BV_DRI_CTRL_RUN__HALT                           0x0
+#define BV_DRI_CTRL_RUN__RUN                            0x1
+#define BF_DRI_CTRL_RUN(v)                              (((v) << 0) & 0x1)
+#define BF_DRI_CTRL_RUN_V(v)                            ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
+
+/**
+ * Register: HW_DRI_TIMING
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DRI_TIMING                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
+#define BP_DRI_TIMING_RSVD2                     20
+#define BM_DRI_TIMING_RSVD2                     0xfff00000
+#define BF_DRI_TIMING_RSVD2(v)                  (((v) << 20) & 0xfff00000)
+#define BP_DRI_TIMING_PILOT_REP_RATE            16
+#define BM_DRI_TIMING_PILOT_REP_RATE            0xf0000
+#define BF_DRI_TIMING_PILOT_REP_RATE(v)         (((v) << 16) & 0xf0000)
+#define BP_DRI_TIMING_RSVD1                     8
+#define BM_DRI_TIMING_RSVD1                     0xff00
+#define BF_DRI_TIMING_RSVD1(v)                  (((v) << 8) & 0xff00)
+#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL    0
+#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL    0xff
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DRI_STAT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DRI_STAT                                         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
+#define BP_DRI_STAT_DRI_PRESENT                             31
+#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
+#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
+#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
+#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) << 31) & 0x80000000)
+#define BF_DRI_STAT_DRI_PRESENT_V(v)                        ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
+#define BP_DRI_STAT_RSVD3                                   20
+#define BM_DRI_STAT_RSVD3                                   0x7ff00000
+#define BF_DRI_STAT_RSVD3(v)                                (((v) << 20) & 0x7ff00000)
+#define BP_DRI_STAT_PILOT_PHASE                             16
+#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
+#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) << 16) & 0xf0000)
+#define BP_DRI_STAT_RSVD2                                   4
+#define BM_DRI_STAT_RSVD2                                   0xfff0
+#define BF_DRI_STAT_RSVD2(v)                                (((v) << 4) & 0xfff0)
+#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
+#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) << 3) & 0x8)
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)               ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
+#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
+#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) << 2) & 0x4)
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)        ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
+#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
+#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) << 1) & 0x2)
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)              ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
+#define BP_DRI_STAT_RSVD1                                   0
+#define BM_DRI_STAT_RSVD1                                   0x1
+#define BF_DRI_STAT_RSVD1(v)                                (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRI_DATA
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_DRI_DATA         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
+#define BP_DRI_DATA_DATA    0
+#define BM_DRI_DATA_DATA    0xffffffff
+#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DRI_DEBUG0
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_DRI_DEBUG0                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
+#define HW_DRI_DEBUG0_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
+#define HW_DRI_DEBUG0_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
+#define HW_DRI_DEBUG0_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
+#define BP_DRI_DEBUG0_DMAREQ                        31
+#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
+#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) << 31) & 0x80000000)
+#define BP_DRI_DEBUG0_DMACMDKICK                    30
+#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
+#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) << 30) & 0x40000000)
+#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
+#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) << 29) & 0x20000000)
+#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
+#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) << 28) & 0x10000000)
+#define BP_DRI_DEBUG0_TEST_MODE                     27
+#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
+#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) << 27) & 0x8000000)
+#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
+#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
+#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) << 26) & 0x4000000)
+#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v)           ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
+#define BP_DRI_DEBUG0_SPARE                         18
+#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
+#define BF_DRI_DEBUG0_SPARE(v)                      (((v) << 18) & 0x3fc0000)
+#define BP_DRI_DEBUG0_FRAME                         0
+#define BM_DRI_DEBUG0_FRAME                         0x3ffff
+#define BF_DRI_DEBUG0_FRAME(v)                      (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_DRI_DEBUG1
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_DRI_DEBUG1                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
+#define HW_DRI_DEBUG1_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
+#define HW_DRI_DEBUG1_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
+#define HW_DRI_DEBUG1_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
+#define BP_DRI_DEBUG1_INVERT_PILOT                  31
+#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
+#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
+#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
+#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) << 31) & 0x80000000)
+#define BF_DRI_DEBUG1_INVERT_PILOT_V(v)             ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
+#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
+#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) << 30) & 0x40000000)
+#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v)         ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
+#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
+#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) << 29) & 0x20000000)
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v)          ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
+#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
+#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) << 28) & 0x10000000)
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)         ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
+#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
+#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
+#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
+#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
+#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) << 27) & 0x8000000)
+#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v)            ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
+#define BP_DRI_DEBUG1_RSVD1                         18
+#define BM_DRI_DEBUG1_RSVD1                         0x7fc0000
+#define BF_DRI_DEBUG1_RSVD1(v)                      (((v) << 18) & 0x7fc0000)
+#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
+#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_DRI_VERSION
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DRI_VERSION          (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60))
+#define BP_DRI_VERSION_MAJOR    24
+#define BM_DRI_VERSION_MAJOR    0xff000000
+#define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_DRI_VERSION_MINOR    16
+#define BM_DRI_VERSION_MINOR    0xff0000
+#define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_DRI_VERSION_STEP     0
+#define BM_DRI_VERSION_STEP     0xffff
+#define BF_DRI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h b/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h
new file mode 100644
index 0000000000..0cdb62a096
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-ecc8.h
@@ -0,0 +1,408 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__ECC8__H__
+#define __HEADERGEN__IMX233__ECC8__H__
+
+#define REGS_ECC8_BASE (0x80008000)
+
+#define REGS_ECC8_VERSION "3.2.0"
+
+/**
+ * Register: HW_ECC8_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_ECC8_CTRL                        (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x0))
+#define HW_ECC8_CTRL_SET                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x4))
+#define HW_ECC8_CTRL_CLR                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x8))
+#define HW_ECC8_CTRL_TOG                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0xc))
+#define BP_ECC8_CTRL_SFTRST                 31
+#define BM_ECC8_CTRL_SFTRST                 0x80000000
+#define BV_ECC8_CTRL_SFTRST__RUN            0x0
+#define BV_ECC8_CTRL_SFTRST__RESET          0x1
+#define BF_ECC8_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BF_ECC8_CTRL_SFTRST_V(v)            ((BV_ECC8_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_ECC8_CTRL_CLKGATE                30
+#define BM_ECC8_CTRL_CLKGATE                0x40000000
+#define BV_ECC8_CTRL_CLKGATE__RUN           0x0
+#define BV_ECC8_CTRL_CLKGATE__NO_CLKS       0x1
+#define BF_ECC8_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BF_ECC8_CTRL_CLKGATE_V(v)           ((BV_ECC8_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_ECC8_CTRL_AHBM_SFTRST            29
+#define BM_ECC8_CTRL_AHBM_SFTRST            0x20000000
+#define BV_ECC8_CTRL_AHBM_SFTRST__RUN       0x0
+#define BV_ECC8_CTRL_AHBM_SFTRST__RESET     0x1
+#define BF_ECC8_CTRL_AHBM_SFTRST(v)         (((v) << 29) & 0x20000000)
+#define BF_ECC8_CTRL_AHBM_SFTRST_V(v)       ((BV_ECC8_CTRL_AHBM_SFTRST__##v << 29) & 0x20000000)
+#define BP_ECC8_CTRL_RSRVD2                 28
+#define BM_ECC8_CTRL_RSRVD2                 0x10000000
+#define BF_ECC8_CTRL_RSRVD2(v)              (((v) << 28) & 0x10000000)
+#define BP_ECC8_CTRL_THROTTLE               24
+#define BM_ECC8_CTRL_THROTTLE               0xf000000
+#define BF_ECC8_CTRL_THROTTLE(v)            (((v) << 24) & 0xf000000)
+#define BP_ECC8_CTRL_RSRVD1                 11
+#define BM_ECC8_CTRL_RSRVD1                 0xfff800
+#define BF_ECC8_CTRL_RSRVD1(v)              (((v) << 11) & 0xfff800)
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN     10
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN     0x400
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)  (((v) << 10) & 0x400)
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     9
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     0x200
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)  (((v) << 9) & 0x200)
+#define BP_ECC8_CTRL_COMPLETE_IRQ_EN        8
+#define BM_ECC8_CTRL_COMPLETE_IRQ_EN        0x100
+#define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v)     (((v) << 8) & 0x100)
+#define BP_ECC8_CTRL_RSRVD0                 4
+#define BM_ECC8_CTRL_RSRVD0                 0xf0
+#define BF_ECC8_CTRL_RSRVD0(v)              (((v) << 4) & 0xf0)
+#define BP_ECC8_CTRL_BM_ERROR_IRQ           3
+#define BM_ECC8_CTRL_BM_ERROR_IRQ           0x8
+#define BF_ECC8_CTRL_BM_ERROR_IRQ(v)        (((v) << 3) & 0x8)
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ        2
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ        0x4
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v)     (((v) << 2) & 0x4)
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ        1
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ        0x2
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v)     (((v) << 1) & 0x2)
+#define BP_ECC8_CTRL_COMPLETE_IRQ           0
+#define BM_ECC8_CTRL_COMPLETE_IRQ           0x1
+#define BF_ECC8_CTRL_COMPLETE_IRQ(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_ECC8_STATUS0
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_ECC8_STATUS0                                 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x10))
+#define BP_ECC8_STATUS0_HANDLE                          20
+#define BM_ECC8_STATUS0_HANDLE                          0xfff00000
+#define BF_ECC8_STATUS0_HANDLE(v)                       (((v) << 20) & 0xfff00000)
+#define BP_ECC8_STATUS0_COMPLETED_CE                    16
+#define BM_ECC8_STATUS0_COMPLETED_CE                    0xf0000
+#define BF_ECC8_STATUS0_COMPLETED_CE(v)                 (((v) << 16) & 0xf0000)
+#define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT              15
+#define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT              0x8000
+#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)           (((v) << 15) & 0x8000)
+#define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT              14
+#define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT              0x4000
+#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)           (((v) << 14) & 0x4000)
+#define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT              13
+#define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT              0x2000
+#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)           (((v) << 13) & 0x2000)
+#define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT              12
+#define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT              0x1000
+#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)           (((v) << 12) & 0x1000)
+#define BP_ECC8_STATUS0_STATUS_AUX                      8
+#define BM_ECC8_STATUS0_STATUS_AUX                      0xf00
+#define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS           0x0
+#define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE     0x1
+#define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE     0x2
+#define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE   0x3
+#define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE    0x4
+#define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED         0xc
+#define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE       0xe
+#define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES            0xf
+#define BF_ECC8_STATUS0_STATUS_AUX(v)                   (((v) << 8) & 0xf00)
+#define BF_ECC8_STATUS0_STATUS_AUX_V(v)                 ((BV_ECC8_STATUS0_STATUS_AUX__##v << 8) & 0xf00)
+#define BP_ECC8_STATUS0_RSVD1                           5
+#define BM_ECC8_STATUS0_RSVD1                           0xe0
+#define BF_ECC8_STATUS0_RSVD1(v)                        (((v) << 5) & 0xe0)
+#define BP_ECC8_STATUS0_ALLONES                         4
+#define BM_ECC8_STATUS0_ALLONES                         0x10
+#define BF_ECC8_STATUS0_ALLONES(v)                      (((v) << 4) & 0x10)
+#define BP_ECC8_STATUS0_CORRECTED                       3
+#define BM_ECC8_STATUS0_CORRECTED                       0x8
+#define BF_ECC8_STATUS0_CORRECTED(v)                    (((v) << 3) & 0x8)
+#define BP_ECC8_STATUS0_UNCORRECTABLE                   2
+#define BM_ECC8_STATUS0_UNCORRECTABLE                   0x4
+#define BF_ECC8_STATUS0_UNCORRECTABLE(v)                (((v) << 2) & 0x4)
+#define BP_ECC8_STATUS0_RSVD0                           0
+#define BM_ECC8_STATUS0_RSVD0                           0x3
+#define BF_ECC8_STATUS0_RSVD0(v)                        (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_ECC8_STATUS1
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_ECC8_STATUS1                                     (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x20))
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD7                     28
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD7                     0xf0000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v)                  (((v) << 28) & 0xf0000000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD7__##v << 28) & 0xf0000000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD6                     24
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD6                     0xf000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v)                  (((v) << 24) & 0xf000000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD6__##v << 24) & 0xf000000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD5                     20
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD5                     0xf00000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v)                  (((v) << 20) & 0xf00000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD5__##v << 20) & 0xf00000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD4                     16
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD4                     0xf0000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v)                  (((v) << 16) & 0xf0000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD4__##v << 16) & 0xf0000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD3                     12
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD3                     0xf000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v)                  (((v) << 12) & 0xf000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD3__##v << 12) & 0xf000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD2                     8
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD2                     0xf00
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v)                  (((v) << 8) & 0xf00)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD2__##v << 8) & 0xf00)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD1                     4
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD1                     0xf0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v)                  (((v) << 4) & 0xf0)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD1__##v << 4) & 0xf0)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD0                     0
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD0                     0xf
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v)                  (((v) << 0) & 0xf)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD0__##v << 0) & 0xf)
+
+/**
+ * Register: HW_ECC8_DEBUG0
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_ECC8_DEBUG0                                      (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x0))
+#define HW_ECC8_DEBUG0_SET                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x4))
+#define HW_ECC8_DEBUG0_CLR                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x8))
+#define HW_ECC8_DEBUG0_TOG                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0xc))
+#define BP_ECC8_DEBUG0_RSRVD1                               25
+#define BM_ECC8_DEBUG0_RSRVD1                               0xfe000000
+#define BF_ECC8_DEBUG0_RSRVD1(v)                            (((v) << 25) & 0xfe000000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            16
+#define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            0x1ff0000
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)         (((v) << 16) & 0x1ff0000)
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)       ((BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 15
+#define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 0x8000
+#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)              (((v) << 15) & 0x8000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               14
+#define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               0x4000
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA         0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX          0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)            (((v) << 14) & 0x4000)
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)          ((BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K                     13
+#define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K                     0x2000
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k                 0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k                 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                  (((v) << 13) & 0x2000)
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v)                ((BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_KICK                       12
+#define BM_ECC8_DEBUG0_KES_DEBUG_KICK                       0x1000
+#define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v)                    (((v) << 12) & 0x1000)
+#define BP_ECC8_DEBUG0_KES_STANDALONE                       11
+#define BM_ECC8_DEBUG0_KES_STANDALONE                       0x800
+#define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL               0x0
+#define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE            0x1
+#define BF_ECC8_DEBUG0_KES_STANDALONE(v)                    (((v) << 11) & 0x800)
+#define BF_ECC8_DEBUG0_KES_STANDALONE_V(v)                  ((BV_ECC8_DEBUG0_KES_STANDALONE__##v << 11) & 0x800)
+#define BP_ECC8_DEBUG0_KES_DEBUG_STEP                       10
+#define BM_ECC8_DEBUG0_KES_DEBUG_STEP                       0x400
+#define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v)                    (((v) << 10) & 0x400)
+#define BP_ECC8_DEBUG0_KES_DEBUG_STALL                      9
+#define BM_ECC8_DEBUG0_KES_DEBUG_STALL                      0x200
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL              0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT                0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v)                   (((v) << 9) & 0x200)
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(v)                 ((BV_ECC8_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200)
+#define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   8
+#define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   0x100
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL           0x0
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE        0x1
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)                (((v) << 8) & 0x100)
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v)              ((BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100)
+#define BP_ECC8_DEBUG0_RSRVD0                               6
+#define BM_ECC8_DEBUG0_RSRVD0                               0xc0
+#define BF_ECC8_DEBUG0_RSRVD0(v)                            (((v) << 6) & 0xc0)
+#define BP_ECC8_DEBUG0_DEBUG_REG_SELECT                     0
+#define BM_ECC8_DEBUG0_DEBUG_REG_SELECT                     0x3f
+#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                  (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_ECC8_DBGKESREAD
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_ECC8_DBGKESREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x40))
+#define BP_ECC8_DBGKESREAD_VALUES       0
+#define BM_ECC8_DBGKESREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGKESREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_DBGCSFEREAD
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_ECC8_DBGCSFEREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x50))
+#define BP_ECC8_DBGCSFEREAD_VALUES      0
+#define BM_ECC8_DBGCSFEREAD_VALUES      0xffffffff
+#define BF_ECC8_DBGCSFEREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_DBGSYNDGENREAD
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_ECC8_DBGSYNDGENREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x60))
+#define BP_ECC8_DBGSYNDGENREAD_VALUES       0
+#define BM_ECC8_DBGSYNDGENREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGSYNDGENREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_DBGAHBMREAD
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_ECC8_DBGAHBMREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x70))
+#define BP_ECC8_DBGAHBMREAD_VALUES      0
+#define BM_ECC8_DBGAHBMREAD_VALUES      0xffffffff
+#define BF_ECC8_DBGAHBMREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_BLOCKNAME
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_ECC8_BLOCKNAME           (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x80))
+#define BP_ECC8_BLOCKNAME_NAME      0
+#define BM_ECC8_BLOCKNAME_NAME      0xffffffff
+#define BF_ECC8_BLOCKNAME_NAME(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_VERSION
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_ECC8_VERSION             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0xa0))
+#define BP_ECC8_VERSION_MAJOR       24
+#define BM_ECC8_VERSION_MAJOR       0xff000000
+#define BF_ECC8_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_ECC8_VERSION_MINOR       16
+#define BM_ECC8_VERSION_MINOR       0xff0000
+#define BF_ECC8_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_ECC8_VERSION_STEP        0
+#define BM_ECC8_VERSION_STEP        0xffff
+#define BF_ECC8_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__ECC8__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-emi.h b/firmware/target/arm/imx233/regs/imx233/regs-emi.h
new file mode 100644
index 0000000000..4a2106e9be
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-emi.h
@@ -0,0 +1,296 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__EMI__H__
+#define __HEADERGEN__IMX233__EMI__H__
+
+#define REGS_EMI_BASE (0x80020000)
+
+#define REGS_EMI_VERSION "3.2.0"
+
+/**
+ * Register: HW_EMI_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_EMI_CTRL                                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0))
+#define HW_EMI_CTRL_SET                             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4))
+#define HW_EMI_CTRL_CLR                             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8))
+#define HW_EMI_CTRL_TOG                             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc))
+#define BP_EMI_CTRL_SFTRST                          31
+#define BM_EMI_CTRL_SFTRST                          0x80000000
+#define BF_EMI_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
+#define BP_EMI_CTRL_CLKGATE                         30
+#define BM_EMI_CTRL_CLKGATE                         0x40000000
+#define BF_EMI_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
+#define BP_EMI_CTRL_TRAP_SR                         29
+#define BM_EMI_CTRL_TRAP_SR                         0x20000000
+#define BF_EMI_CTRL_TRAP_SR(v)                      (((v) << 29) & 0x20000000)
+#define BP_EMI_CTRL_TRAP_INIT                       28
+#define BM_EMI_CTRL_TRAP_INIT                       0x10000000
+#define BF_EMI_CTRL_TRAP_INIT(v)                    (((v) << 28) & 0x10000000)
+#define BP_EMI_CTRL_AXI_DEPTH                       26
+#define BM_EMI_CTRL_AXI_DEPTH                       0xc000000
+#define BV_EMI_CTRL_AXI_DEPTH__ONE                  0x0
+#define BV_EMI_CTRL_AXI_DEPTH__TWO                  0x1
+#define BV_EMI_CTRL_AXI_DEPTH__THREE                0x2
+#define BV_EMI_CTRL_AXI_DEPTH__FOUR                 0x3
+#define BF_EMI_CTRL_AXI_DEPTH(v)                    (((v) << 26) & 0xc000000)
+#define BF_EMI_CTRL_AXI_DEPTH_V(v)                  ((BV_EMI_CTRL_AXI_DEPTH__##v << 26) & 0xc000000)
+#define BP_EMI_CTRL_DLL_SHIFT_RESET                 25
+#define BM_EMI_CTRL_DLL_SHIFT_RESET                 0x2000000
+#define BF_EMI_CTRL_DLL_SHIFT_RESET(v)              (((v) << 25) & 0x2000000)
+#define BP_EMI_CTRL_DLL_RESET                       24
+#define BM_EMI_CTRL_DLL_RESET                       0x1000000
+#define BF_EMI_CTRL_DLL_RESET(v)                    (((v) << 24) & 0x1000000)
+#define BP_EMI_CTRL_ARB_MODE                        22
+#define BM_EMI_CTRL_ARB_MODE                        0xc00000
+#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP             0x0
+#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID          0x1
+#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY         0x2
+#define BF_EMI_CTRL_ARB_MODE(v)                     (((v) << 22) & 0xc00000)
+#define BF_EMI_CTRL_ARB_MODE_V(v)                   ((BV_EMI_CTRL_ARB_MODE__##v << 22) & 0xc00000)
+#define BP_EMI_CTRL_RSVD3                           21
+#define BM_EMI_CTRL_RSVD3                           0x200000
+#define BF_EMI_CTRL_RSVD3(v)                        (((v) << 21) & 0x200000)
+#define BP_EMI_CTRL_PORT_PRIORITY_ORDER             16
+#define BM_EMI_CTRL_PORT_PRIORITY_ORDER             0x1f0000
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123   0x0
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312   0x1
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231   0x2
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321   0x3
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213   0x4
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132   0x5
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023   0x6
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302   0x7
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230   0x8
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320   0x9
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203   0xa
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032   0xb
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013   0xc
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301   0xd
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130   0xe
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310   0xf
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103   0x10
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031   0x11
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012   0x12
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201   0x13
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120   0x14
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210   0x15
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102   0x16
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021   0x17
+#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v)          (((v) << 16) & 0x1f0000)
+#define BF_EMI_CTRL_PORT_PRIORITY_ORDER_V(v)        ((BV_EMI_CTRL_PORT_PRIORITY_ORDER__##v << 16) & 0x1f0000)
+#define BP_EMI_CTRL_RSVD2                           15
+#define BM_EMI_CTRL_RSVD2                           0x8000
+#define BF_EMI_CTRL_RSVD2(v)                        (((v) << 15) & 0x8000)
+#define BP_EMI_CTRL_PRIORITY_WRITE_ITER             12
+#define BM_EMI_CTRL_PRIORITY_WRITE_ITER             0x7000
+#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v)          (((v) << 12) & 0x7000)
+#define BP_EMI_CTRL_RSVD1                           11
+#define BM_EMI_CTRL_RSVD1                           0x800
+#define BF_EMI_CTRL_RSVD1(v)                        (((v) << 11) & 0x800)
+#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE             8
+#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE             0x700
+#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v)          (((v) << 8) & 0x700)
+#define BP_EMI_CTRL_RSVD0                           7
+#define BM_EMI_CTRL_RSVD0                           0x80
+#define BF_EMI_CTRL_RSVD0(v)                        (((v) << 7) & 0x80)
+#define BP_EMI_CTRL_MEM_WIDTH                       6
+#define BM_EMI_CTRL_MEM_WIDTH                       0x40
+#define BF_EMI_CTRL_MEM_WIDTH(v)                    (((v) << 6) & 0x40)
+#define BP_EMI_CTRL_WRITE_PROTECT                   5
+#define BM_EMI_CTRL_WRITE_PROTECT                   0x20
+#define BF_EMI_CTRL_WRITE_PROTECT(v)                (((v) << 5) & 0x20)
+#define BP_EMI_CTRL_RESET_OUT                       4
+#define BM_EMI_CTRL_RESET_OUT                       0x10
+#define BF_EMI_CTRL_RESET_OUT(v)                    (((v) << 4) & 0x10)
+#define BP_EMI_CTRL_CE_SELECT                       0
+#define BM_EMI_CTRL_CE_SELECT                       0xf
+#define BV_EMI_CTRL_CE_SELECT__NONE                 0x0
+#define BV_EMI_CTRL_CE_SELECT__CE0                  0x1
+#define BV_EMI_CTRL_CE_SELECT__CE1                  0x2
+#define BV_EMI_CTRL_CE_SELECT__CE2                  0x4
+#define BV_EMI_CTRL_CE_SELECT__CE3                  0x8
+#define BF_EMI_CTRL_CE_SELECT(v)                    (((v) << 0) & 0xf)
+#define BF_EMI_CTRL_CE_SELECT_V(v)                  ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_EMI_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_EMI_STAT                         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10))
+#define BP_EMI_STAT_DRAM_PRESENT            31
+#define BM_EMI_STAT_DRAM_PRESENT            0x80000000
+#define BF_EMI_STAT_DRAM_PRESENT(v)         (((v) << 31) & 0x80000000)
+#define BP_EMI_STAT_NOR_PRESENT             30
+#define BM_EMI_STAT_NOR_PRESENT             0x40000000
+#define BF_EMI_STAT_NOR_PRESENT(v)          (((v) << 30) & 0x40000000)
+#define BP_EMI_STAT_LARGE_DRAM_ENABLED      29
+#define BM_EMI_STAT_LARGE_DRAM_ENABLED      0x20000000
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)   (((v) << 29) & 0x20000000)
+#define BP_EMI_STAT_RSVD0                   2
+#define BM_EMI_STAT_RSVD0                   0x1ffffffc
+#define BF_EMI_STAT_RSVD0(v)                (((v) << 2) & 0x1ffffffc)
+#define BP_EMI_STAT_DRAM_HALTED             1
+#define BM_EMI_STAT_DRAM_HALTED             0x2
+#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
+#define BV_EMI_STAT_DRAM_HALTED__HALTED     0x1
+#define BF_EMI_STAT_DRAM_HALTED(v)          (((v) << 1) & 0x2)
+#define BF_EMI_STAT_DRAM_HALTED_V(v)        ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2)
+#define BP_EMI_STAT_NOR_BUSY                0
+#define BM_EMI_STAT_NOR_BUSY                0x1
+#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY      0x0
+#define BV_EMI_STAT_NOR_BUSY__BUSY          0x1
+#define BF_EMI_STAT_NOR_BUSY(v)             (((v) << 0) & 0x1)
+#define BF_EMI_STAT_NOR_BUSY_V(v)           ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1)
+
+/**
+ * Register: HW_EMI_TIME
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_EMI_TIME             (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0))
+#define HW_EMI_TIME_SET         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4))
+#define HW_EMI_TIME_CLR         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8))
+#define HW_EMI_TIME_TOG         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc))
+#define BP_EMI_TIME_RSVD4       28
+#define BM_EMI_TIME_RSVD4       0xf0000000
+#define BF_EMI_TIME_RSVD4(v)    (((v) << 28) & 0xf0000000)
+#define BP_EMI_TIME_THZ         24
+#define BM_EMI_TIME_THZ         0xf000000
+#define BF_EMI_TIME_THZ(v)      (((v) << 24) & 0xf000000)
+#define BP_EMI_TIME_RSVD2       20
+#define BM_EMI_TIME_RSVD2       0xf00000
+#define BF_EMI_TIME_RSVD2(v)    (((v) << 20) & 0xf00000)
+#define BP_EMI_TIME_TDH         16
+#define BM_EMI_TIME_TDH         0xf0000
+#define BF_EMI_TIME_TDH(v)      (((v) << 16) & 0xf0000)
+#define BP_EMI_TIME_RSVD1       13
+#define BM_EMI_TIME_RSVD1       0xe000
+#define BF_EMI_TIME_RSVD1(v)    (((v) << 13) & 0xe000)
+#define BP_EMI_TIME_TDS         8
+#define BM_EMI_TIME_TDS         0x1f00
+#define BF_EMI_TIME_TDS(v)      (((v) << 8) & 0x1f00)
+#define BP_EMI_TIME_RSVD0       4
+#define BM_EMI_TIME_RSVD0       0xf0
+#define BF_EMI_TIME_RSVD0(v)    (((v) << 4) & 0xf0)
+#define BP_EMI_TIME_TAS         0
+#define BM_EMI_TIME_TAS         0xf
+#define BF_EMI_TIME_TAS(v)      (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_CSR
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_EMI_DDR_TEST_MODE_CSR            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0))
+#define HW_EMI_DDR_TEST_MODE_CSR_SET        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4))
+#define HW_EMI_DDR_TEST_MODE_CSR_CLR        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8))
+#define HW_EMI_DDR_TEST_MODE_CSR_TOG        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc))
+#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1      2
+#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1      0xfffffffc
+#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v)   (((v) << 2) & 0xfffffffc)
+#define BP_EMI_DDR_TEST_MODE_CSR_DONE       1
+#define BM_EMI_DDR_TEST_MODE_CSR_DONE       0x2
+#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v)    (((v) << 1) & 0x2)
+#define BP_EMI_DDR_TEST_MODE_CSR_START      0
+#define BM_EMI_DDR_TEST_MODE_CSR_START      0x1
+#define BF_EMI_DDR_TEST_MODE_CSR_START(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_EMI_DEBUG
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_EMI_DEBUG                (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80))
+#define BP_EMI_DEBUG_RSVD1          4
+#define BM_EMI_DEBUG_RSVD1          0xfffffff0
+#define BF_EMI_DEBUG_RSVD1(v)       (((v) << 4) & 0xfffffff0)
+#define BP_EMI_DEBUG_NOR_STATE      0
+#define BM_EMI_DEBUG_NOR_STATE      0xf
+#define BF_EMI_DEBUG_NOR_STATE(v)   (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS0
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS0            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90))
+#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1      13
+#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1      0xffffe000
+#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v)   (((v) << 13) & 0xffffe000)
+#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0
+#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS1
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS1            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0))
+#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1      13
+#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1      0xffffe000
+#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v)   (((v) << 13) & 0xffffe000)
+#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0
+#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS2
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS2            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0))
+#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0      0
+#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0      0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS3
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS3            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0))
+#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1      0
+#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1      0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_EMI_VERSION
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_EMI_VERSION          (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0))
+#define BP_EMI_VERSION_MAJOR    24
+#define BM_EMI_VERSION_MAJOR    0xff000000
+#define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_EMI_VERSION_MINOR    16
+#define BM_EMI_VERSION_MINOR    0xff0000
+#define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_EMI_VERSION_STEP     0
+#define BM_EMI_VERSION_STEP     0xffff
+#define BF_EMI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__EMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h b/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h
new file mode 100644
index 0000000000..895057db69
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-gpmi.h
@@ -0,0 +1,561 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__GPMI__H__
+#define __HEADERGEN__IMX233__GPMI__H__
+
+#define REGS_GPMI_BASE (0x8000c000)
+
+#define REGS_GPMI_VERSION "3.2.0"
+
+/**
+ * Register: HW_GPMI_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL0                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
+#define HW_GPMI_CTRL0_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
+#define HW_GPMI_CTRL0_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
+#define HW_GPMI_CTRL0_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
+#define BP_GPMI_CTRL0_SFTRST                            31
+#define BM_GPMI_CTRL0_SFTRST                            0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
+#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) << 31) & 0x80000000)
+#define BF_GPMI_CTRL0_SFTRST_V(v)                       ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
+#define BP_GPMI_CTRL0_CLKGATE                           30
+#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
+#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) << 30) & 0x40000000)
+#define BF_GPMI_CTRL0_CLKGATE_V(v)                      ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
+#define BP_GPMI_CTRL0_RUN                               29
+#define BM_GPMI_CTRL0_RUN                               0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
+#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
+#define BF_GPMI_CTRL0_RUN(v)                            (((v) << 29) & 0x20000000)
+#define BF_GPMI_CTRL0_RUN_V(v)                          ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
+#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
+#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
+#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) << 28) & 0x10000000)
+#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) << 27) & 0x8000000)
+#define BP_GPMI_CTRL0_UDMA                              26
+#define BM_GPMI_CTRL0_UDMA                              0x4000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
+#define BF_GPMI_CTRL0_UDMA(v)                           (((v) << 26) & 0x4000000)
+#define BF_GPMI_CTRL0_UDMA_V(v)                         ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
+#define BP_GPMI_CTRL0_COMMAND_MODE                      24
+#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) << 24) & 0x3000000)
+#define BF_GPMI_CTRL0_COMMAND_MODE_V(v)                 ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
+#define BP_GPMI_CTRL0_WORD_LENGTH                       23
+#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
+#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) << 23) & 0x800000)
+#define BF_GPMI_CTRL0_WORD_LENGTH_V(v)                  ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
+#define BP_GPMI_CTRL0_LOCK_CS                           22
+#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
+#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) << 22) & 0x400000)
+#define BF_GPMI_CTRL0_LOCK_CS_V(v)                      ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
+#define BP_GPMI_CTRL0_CS                                20
+#define BM_GPMI_CTRL0_CS                                0x300000
+#define BF_GPMI_CTRL0_CS(v)                             (((v) << 20) & 0x300000)
+#define BP_GPMI_CTRL0_ADDRESS                           17
+#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
+#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) << 17) & 0xe0000)
+#define BF_GPMI_CTRL0_ADDRESS_V(v)                      ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
+#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) << 16) & 0x10000)
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)            ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
+#define BP_GPMI_CTRL0_XFER_COUNT                        0
+#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
+#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_COMPARE
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_GPMI_COMPARE                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
+#define BP_GPMI_COMPARE_MASK            16
+#define BM_GPMI_COMPARE_MASK            0xffff0000
+#define BF_GPMI_COMPARE_MASK(v)         (((v) << 16) & 0xffff0000)
+#define BP_GPMI_COMPARE_REFERENCE       0
+#define BM_GPMI_COMPARE_REFERENCE       0xffff
+#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_ECCCTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_GPMI_ECCCTRL                             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
+#define HW_GPMI_ECCCTRL_SET                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
+#define HW_GPMI_ECCCTRL_CLR                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
+#define HW_GPMI_ECCCTRL_TOG                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
+#define BP_GPMI_ECCCTRL_HANDLE                      16
+#define BM_GPMI_ECCCTRL_HANDLE                      0xffff0000
+#define BF_GPMI_ECCCTRL_HANDLE(v)                   (((v) << 16) & 0xffff0000)
+#define BP_GPMI_ECCCTRL_RSVD2                       15
+#define BM_GPMI_ECCCTRL_RSVD2                       0x8000
+#define BF_GPMI_ECCCTRL_RSVD2(v)                    (((v) << 15) & 0x8000)
+#define BP_GPMI_ECCCTRL_ECC_CMD                     13
+#define BM_GPMI_ECCCTRL_ECC_CMD                     0x6000
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT       0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT       0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT       0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT       0x3
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)                  (((v) << 13) & 0x6000)
+#define BF_GPMI_ECCCTRL_ECC_CMD_V(v)                ((BV_GPMI_ECCCTRL_ECC_CMD__##v << 13) & 0x6000)
+#define BP_GPMI_ECCCTRL_ENABLE_ECC                  12
+#define BM_GPMI_ECCCTRL_ENABLE_ECC                  0x1000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE          0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE         0x0
+#define BF_GPMI_ECCCTRL_ENABLE_ECC(v)               (((v) << 12) & 0x1000)
+#define BF_GPMI_ECCCTRL_ENABLE_ECC_V(v)             ((BV_GPMI_ECCCTRL_ENABLE_ECC__##v << 12) & 0x1000)
+#define BP_GPMI_ECCCTRL_RSVD1                       9
+#define BM_GPMI_ECCCTRL_RSVD1                       0xe00
+#define BF_GPMI_ECCCTRL_RSVD1(v)                    (((v) << 9) & 0xe00)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK                 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK                 0x1ff
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY    0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE       0x1ff
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY      0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7        0x80
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6        0x40
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5        0x20
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4        0x10
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3        0x8
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2        0x4
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1        0x2
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0        0x1
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)              (((v) << 0) & 0x1ff)
+#define BF_GPMI_ECCCTRL_BUFFER_MASK_V(v)            ((BV_GPMI_ECCCTRL_BUFFER_MASK__##v << 0) & 0x1ff)
+
+/**
+ * Register: HW_GPMI_ECCCOUNT
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_GPMI_ECCCOUNT            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
+#define BP_GPMI_ECCCOUNT_RSVD2      16
+#define BM_GPMI_ECCCOUNT_RSVD2      0xffff0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v)   (((v) << 16) & 0xffff0000)
+#define BP_GPMI_ECCCOUNT_COUNT      0
+#define BM_GPMI_ECCCOUNT_COUNT      0xffff
+#define BF_GPMI_ECCCOUNT_COUNT(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_PAYLOAD
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_GPMI_PAYLOAD             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
+#define BP_GPMI_PAYLOAD_ADDRESS     2
+#define BM_GPMI_PAYLOAD_ADDRESS     0xfffffffc
+#define BF_GPMI_PAYLOAD_ADDRESS(v)  (((v) << 2) & 0xfffffffc)
+#define BP_GPMI_PAYLOAD_RSVD0       0
+#define BM_GPMI_PAYLOAD_RSVD0       0x3
+#define BF_GPMI_PAYLOAD_RSVD0(v)    (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_GPMI_AUXILIARY
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_GPMI_AUXILIARY               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
+#define BP_GPMI_AUXILIARY_ADDRESS       2
+#define BM_GPMI_AUXILIARY_ADDRESS       0xfffffffc
+#define BF_GPMI_AUXILIARY_ADDRESS(v)    (((v) << 2) & 0xfffffffc)
+#define BP_GPMI_AUXILIARY_RSVD0         0
+#define BM_GPMI_AUXILIARY_RSVD0         0x3
+#define BF_GPMI_AUXILIARY_RSVD0(v)      (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_GPMI_CTRL1
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL1                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x0))
+#define HW_GPMI_CTRL1_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x4))
+#define HW_GPMI_CTRL1_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x8))
+#define HW_GPMI_CTRL1_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0xc))
+#define BP_GPMI_CTRL1_RSVD2                             24
+#define BM_GPMI_CTRL1_RSVD2                             0xff000000
+#define BF_GPMI_CTRL1_RSVD2(v)                          (((v) << 24) & 0xff000000)
+#define BP_GPMI_CTRL1_CE3_SEL                           23
+#define BM_GPMI_CTRL1_CE3_SEL                           0x800000
+#define BF_GPMI_CTRL1_CE3_SEL(v)                        (((v) << 23) & 0x800000)
+#define BP_GPMI_CTRL1_CE2_SEL                           22
+#define BM_GPMI_CTRL1_CE2_SEL                           0x400000
+#define BF_GPMI_CTRL1_CE2_SEL(v)                        (((v) << 22) & 0x400000)
+#define BP_GPMI_CTRL1_CE1_SEL                           21
+#define BM_GPMI_CTRL1_CE1_SEL                           0x200000
+#define BF_GPMI_CTRL1_CE1_SEL(v)                        (((v) << 21) & 0x200000)
+#define BP_GPMI_CTRL1_CE0_SEL                           20
+#define BM_GPMI_CTRL1_CE0_SEL                           0x100000
+#define BF_GPMI_CTRL1_CE0_SEL(v)                        (((v) << 20) & 0x100000)
+#define BP_GPMI_CTRL1_GANGED_RDYBUSY                    19
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY                    0x80000
+#define BF_GPMI_CTRL1_GANGED_RDYBUSY(v)                 (((v) << 19) & 0x80000)
+#define BP_GPMI_CTRL1_BCH_MODE                          18
+#define BM_GPMI_CTRL1_BCH_MODE                          0x40000
+#define BF_GPMI_CTRL1_BCH_MODE(v)                       (((v) << 18) & 0x40000)
+#define BP_GPMI_CTRL1_DLL_ENABLE                        17
+#define BM_GPMI_CTRL1_DLL_ENABLE                        0x20000
+#define BF_GPMI_CTRL1_DLL_ENABLE(v)                     (((v) << 17) & 0x20000)
+#define BP_GPMI_CTRL1_HALF_PERIOD                       16
+#define BM_GPMI_CTRL1_HALF_PERIOD                       0x10000
+#define BF_GPMI_CTRL1_HALF_PERIOD(v)                    (((v) << 16) & 0x10000)
+#define BP_GPMI_CTRL1_RDN_DELAY                         12
+#define BM_GPMI_CTRL1_RDN_DELAY                         0xf000
+#define BF_GPMI_CTRL1_RDN_DELAY(v)                      (((v) << 12) & 0xf000)
+#define BP_GPMI_CTRL1_DMA2ECC_MODE                      11
+#define BM_GPMI_CTRL1_DMA2ECC_MODE                      0x800
+#define BF_GPMI_CTRL1_DMA2ECC_MODE(v)                   (((v) << 11) & 0x800)
+#define BP_GPMI_CTRL1_DEV_IRQ                           10
+#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
+#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) << 10) & 0x400)
+#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) << 9) & 0x200)
+#define BP_GPMI_CTRL1_BURST_EN                          8
+#define BM_GPMI_CTRL1_BURST_EN                          0x100
+#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) << 8) & 0x100)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) << 7) & 0x80)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) << 6) & 0x40)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) << 5) & 0x20)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) << 4) & 0x10)
+#define BP_GPMI_CTRL1_DEV_RESET                         3
+#define BM_GPMI_CTRL1_DEV_RESET                         0x8
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
+#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) << 3) & 0x8)
+#define BF_GPMI_CTRL1_DEV_RESET_V(v)                    ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
+#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) << 2) & 0x4)
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)          ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
+#define BP_GPMI_CTRL1_CAMERA_MODE                       1
+#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
+#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) << 1) & 0x2)
+#define BP_GPMI_CTRL1_GPMI_MODE                         0
+#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
+#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) << 0) & 0x1)
+#define BF_GPMI_CTRL1_GPMI_MODE_V(v)                    ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
+
+/**
+ * Register: HW_GPMI_TIMING0
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_GPMI_TIMING0                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
+#define BP_GPMI_TIMING0_RSVD1               24
+#define BM_GPMI_TIMING0_RSVD1               0xff000000
+#define BF_GPMI_TIMING0_RSVD1(v)            (((v) << 24) & 0xff000000)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING0_DATA_HOLD           8
+#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING0_DATA_SETUP          0
+#define BM_GPMI_TIMING0_DATA_SETUP          0xff
+#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_GPMI_TIMING1
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_GPMI_TIMING1                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xffff0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)  (((v) << 16) & 0xffff0000)
+#define BP_GPMI_TIMING1_RSVD1                   0
+#define BM_GPMI_TIMING1_RSVD1                   0xffff
+#define BF_GPMI_TIMING1_RSVD1(v)                (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_TIMING2
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_GPMI_TIMING2                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x90))
+#define BP_GPMI_TIMING2_UDMA_TRP        24
+#define BM_GPMI_TIMING2_UDMA_TRP        0xff000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v)     (((v) << 24) & 0xff000000)
+#define BP_GPMI_TIMING2_UDMA_ENV        16
+#define BM_GPMI_TIMING2_UDMA_ENV        0xff0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)     (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING2_UDMA_HOLD       8
+#define BM_GPMI_TIMING2_UDMA_HOLD       0xff00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING2_UDMA_SETUP      0
+#define BM_GPMI_TIMING2_UDMA_SETUP      0xff
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_GPMI_DATA
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_GPMI_DATA            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xa0))
+#define BP_GPMI_DATA_DATA       0
+#define BM_GPMI_DATA_DATA       0xffffffff
+#define BF_GPMI_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPMI_STAT
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_GPMI_STAT                        (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xb0))
+#define BP_GPMI_STAT_PRESENT                31
+#define BM_GPMI_STAT_PRESENT                0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
+#define BF_GPMI_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
+#define BF_GPMI_STAT_PRESENT_V(v)           ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_GPMI_STAT_RSVD1                  12
+#define BM_GPMI_STAT_RSVD1                  0x7ffff000
+#define BF_GPMI_STAT_RSVD1(v)               (((v) << 12) & 0x7ffff000)
+#define BP_GPMI_STAT_RDY_TIMEOUT            8
+#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) << 8) & 0xf00)
+#define BP_GPMI_STAT_ATA_IRQ                7
+#define BM_GPMI_STAT_ATA_IRQ                0x80
+#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) << 7) & 0x80)
+#define BP_GPMI_STAT_INVALID_BUFFER_MASK    6
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK    0x40
+#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & 0x40)
+#define BP_GPMI_STAT_FIFO_EMPTY             5
+#define BM_GPMI_STAT_FIFO_EMPTY             0x20
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
+#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) << 5) & 0x20)
+#define BF_GPMI_STAT_FIFO_EMPTY_V(v)        ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
+#define BP_GPMI_STAT_FIFO_FULL              4
+#define BM_GPMI_STAT_FIFO_FULL              0x10
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
+#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) << 4) & 0x10)
+#define BF_GPMI_STAT_FIFO_FULL_V(v)         ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
+#define BP_GPMI_STAT_DEV3_ERROR             3
+#define BM_GPMI_STAT_DEV3_ERROR             0x8
+#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) << 3) & 0x8)
+#define BP_GPMI_STAT_DEV2_ERROR             2
+#define BM_GPMI_STAT_DEV2_ERROR             0x4
+#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) << 2) & 0x4)
+#define BP_GPMI_STAT_DEV1_ERROR             1
+#define BM_GPMI_STAT_DEV1_ERROR             0x2
+#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) << 1) & 0x2)
+#define BP_GPMI_STAT_DEV0_ERROR             0
+#define BM_GPMI_STAT_DEV0_ERROR             0x1
+#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_GPMI_DEBUG
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_GPMI_DEBUG                           (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xc0))
+#define BP_GPMI_DEBUG_READY3                    31
+#define BM_GPMI_DEBUG_READY3                    0x80000000
+#define BF_GPMI_DEBUG_READY3(v)                 (((v) << 31) & 0x80000000)
+#define BP_GPMI_DEBUG_READY2                    30
+#define BM_GPMI_DEBUG_READY2                    0x40000000
+#define BF_GPMI_DEBUG_READY2(v)                 (((v) << 30) & 0x40000000)
+#define BP_GPMI_DEBUG_READY1                    29
+#define BM_GPMI_DEBUG_READY1                    0x20000000
+#define BF_GPMI_DEBUG_READY1(v)                 (((v) << 29) & 0x20000000)
+#define BP_GPMI_DEBUG_READY0                    28
+#define BM_GPMI_DEBUG_READY0                    0x10000000
+#define BF_GPMI_DEBUG_READY0(v)                 (((v) << 28) & 0x10000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) << 27) & 0x8000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) << 26) & 0x4000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) << 25) & 0x2000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) << 24) & 0x1000000)
+#define BP_GPMI_DEBUG_SENSE3                    23
+#define BM_GPMI_DEBUG_SENSE3                    0x800000
+#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) << 23) & 0x800000)
+#define BP_GPMI_DEBUG_SENSE2                    22
+#define BM_GPMI_DEBUG_SENSE2                    0x400000
+#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) << 22) & 0x400000)
+#define BP_GPMI_DEBUG_SENSE1                    21
+#define BM_GPMI_DEBUG_SENSE1                    0x200000
+#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) << 21) & 0x200000)
+#define BP_GPMI_DEBUG_SENSE0                    20
+#define BM_GPMI_DEBUG_SENSE0                    0x100000
+#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) << 20) & 0x100000)
+#define BP_GPMI_DEBUG_DMAREQ3                   19
+#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
+#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) << 19) & 0x80000)
+#define BP_GPMI_DEBUG_DMAREQ2                   18
+#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
+#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) << 18) & 0x40000)
+#define BP_GPMI_DEBUG_DMAREQ1                   17
+#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
+#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) << 17) & 0x20000)
+#define BP_GPMI_DEBUG_DMAREQ0                   16
+#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
+#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) << 16) & 0x10000)
+#define BP_GPMI_DEBUG_CMD_END                   12
+#define BM_GPMI_DEBUG_CMD_END                   0xf000
+#define BF_GPMI_DEBUG_CMD_END(v)                (((v) << 12) & 0xf000)
+#define BP_GPMI_DEBUG_UDMA_STATE                8
+#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) << 8) & 0xf00)
+#define BP_GPMI_DEBUG_BUSY                      7
+#define BM_GPMI_DEBUG_BUSY                      0x80
+#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
+#define BF_GPMI_DEBUG_BUSY(v)                   (((v) << 7) & 0x80)
+#define BF_GPMI_DEBUG_BUSY_V(v)                 ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
+#define BP_GPMI_DEBUG_PIN_STATE                 4
+#define BM_GPMI_DEBUG_PIN_STATE                 0x70
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
+#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) << 4) & 0x70)
+#define BF_GPMI_DEBUG_PIN_STATE_V(v)            ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
+#define BP_GPMI_DEBUG_MAIN_STATE                0
+#define BM_GPMI_DEBUG_MAIN_STATE                0xf
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
+#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) << 0) & 0xf)
+#define BF_GPMI_DEBUG_MAIN_STATE_V(v)           ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
+
+/**
+ * Register: HW_GPMI_VERSION
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_GPMI_VERSION             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xd0))
+#define BP_GPMI_VERSION_MAJOR       24
+#define BM_GPMI_VERSION_MAJOR       0xff000000
+#define BF_GPMI_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_GPMI_VERSION_MINOR       16
+#define BM_GPMI_VERSION_MINOR       0xff0000
+#define BF_GPMI_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_GPMI_VERSION_STEP        0
+#define BM_GPMI_VERSION_STEP        0xffff
+#define BF_GPMI_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_DEBUG2
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_GPMI_DEBUG2                      (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xe0))
+#define BP_GPMI_DEBUG2_RSVD1                16
+#define BM_GPMI_DEBUG2_RSVD1                0xffff0000
+#define BF_GPMI_DEBUG2_RSVD1(v)             (((v) << 16) & 0xffff0000)
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE         12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE         0xf000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v)      (((v) << 12) & 0xf000)
+#define BP_GPMI_DEBUG2_GPMI2SYND_VALID      11
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID      0x800
+#define BF_GPMI_DEBUG2_GPMI2SYND_VALID(v)   (((v) << 11) & 0x800)
+#define BP_GPMI_DEBUG2_GPMI2SYND_READY      10
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY      0x400
+#define BF_GPMI_DEBUG2_GPMI2SYND_READY(v)   (((v) << 10) & 0x400)
+#define BP_GPMI_DEBUG2_SYND2GPMI_VALID      9
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID      0x200
+#define BF_GPMI_DEBUG2_SYND2GPMI_VALID(v)   (((v) << 9) & 0x200)
+#define BP_GPMI_DEBUG2_SYND2GPMI_READY      8
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY      0x100
+#define BF_GPMI_DEBUG2_SYND2GPMI_READY(v)   (((v) << 8) & 0x100)
+#define BP_GPMI_DEBUG2_VIEW_DELAYED_RDN     7
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN     0x80
+#define BF_GPMI_DEBUG2_VIEW_DELAYED_RDN(v)  (((v) << 7) & 0x80)
+#define BP_GPMI_DEBUG2_UPDATE_WINDOW        6
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW        0x40
+#define BF_GPMI_DEBUG2_UPDATE_WINDOW(v)     (((v) << 6) & 0x40)
+#define BP_GPMI_DEBUG2_RDN_TAP              0
+#define BM_GPMI_DEBUG2_RDN_TAP              0x3f
+#define BF_GPMI_DEBUG2_RDN_TAP(v)           (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_GPMI_DEBUG3
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_GPMI_DEBUG3                  (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xf0))
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR    16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR    0xffff0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << 16) & 0xffff0000)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR    0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR    0xffff
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-i2c.h b/firmware/target/arm/imx233/regs/imx233/regs-i2c.h
new file mode 100644
index 0000000000..593a3ed04b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-i2c.h
@@ -0,0 +1,597 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__I2C__H__
+#define __HEADERGEN__IMX233__I2C__H__
+
+#define REGS_I2C_BASE (0x80058000)
+
+#define REGS_I2C_VERSION "3.2.0"
+
+/**
+ * Register: HW_I2C_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_I2C_CTRL0                                (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0))
+#define HW_I2C_CTRL0_SET                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4))
+#define HW_I2C_CTRL0_CLR                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8))
+#define HW_I2C_CTRL0_TOG                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc))
+#define BP_I2C_CTRL0_SFTRST                         31
+#define BM_I2C_CTRL0_SFTRST                         0x80000000
+#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
+#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
+#define BF_I2C_CTRL0_SFTRST(v)                      (((v) << 31) & 0x80000000)
+#define BF_I2C_CTRL0_SFTRST_V(v)                    ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000)
+#define BP_I2C_CTRL0_CLKGATE                        30
+#define BM_I2C_CTRL0_CLKGATE                        0x40000000
+#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
+#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
+#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) << 30) & 0x40000000)
+#define BF_I2C_CTRL0_CLKGATE_V(v)                   ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000)
+#define BP_I2C_CTRL0_RUN                            29
+#define BM_I2C_CTRL0_RUN                            0x20000000
+#define BV_I2C_CTRL0_RUN__HALT                      0x0
+#define BV_I2C_CTRL0_RUN__RUN                       0x1
+#define BF_I2C_CTRL0_RUN(v)                         (((v) << 29) & 0x20000000)
+#define BF_I2C_CTRL0_RUN_V(v)                       ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000)
+#define BP_I2C_CTRL0_RSVD1                          28
+#define BM_I2C_CTRL0_RSVD1                          0x10000000
+#define BF_I2C_CTRL0_RSVD1(v)                       (((v) << 28) & 0x10000000)
+#define BP_I2C_CTRL0_PRE_ACK                        27
+#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
+#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) << 27) & 0x8000000)
+#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
+#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
+#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
+#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
+#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) << 26) & 0x4000000)
+#define BF_I2C_CTRL0_ACKNOWLEDGE_V(v)               ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000)
+#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) << 25) & 0x2000000)
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)          ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000)
+#define BP_I2C_CTRL0_PIO_MODE                       24
+#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
+#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) << 24) & 0x1000000)
+#define BP_I2C_CTRL0_MULTI_MASTER                   23
+#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
+#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
+#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
+#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) << 23) & 0x800000)
+#define BF_I2C_CTRL0_MULTI_MASTER_V(v)              ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000)
+#define BP_I2C_CTRL0_CLOCK_HELD                     22
+#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
+#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
+#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
+#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) << 22) & 0x400000)
+#define BF_I2C_CTRL0_CLOCK_HELD_V(v)                ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000)
+#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
+#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
+#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
+#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
+#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) << 21) & 0x200000)
+#define BF_I2C_CTRL0_RETAIN_CLOCK_V(v)              ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000)
+#define BP_I2C_CTRL0_POST_SEND_STOP                 20
+#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
+#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
+#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
+#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) << 20) & 0x100000)
+#define BF_I2C_CTRL0_POST_SEND_STOP_V(v)            ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000)
+#define BP_I2C_CTRL0_PRE_SEND_START                 19
+#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
+#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
+#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
+#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) << 19) & 0x80000)
+#define BF_I2C_CTRL0_PRE_SEND_START_V(v)            ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000)
+#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
+#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) << 18) & 0x40000)
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)      ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000)
+#define BP_I2C_CTRL0_MASTER_MODE                    17
+#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
+#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
+#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
+#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) << 17) & 0x20000)
+#define BF_I2C_CTRL0_MASTER_MODE_V(v)               ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000)
+#define BP_I2C_CTRL0_DIRECTION                      16
+#define BM_I2C_CTRL0_DIRECTION                      0x10000
+#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
+#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
+#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) << 16) & 0x10000)
+#define BF_I2C_CTRL0_DIRECTION_V(v)                 ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000)
+#define BP_I2C_CTRL0_XFER_COUNT                     0
+#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
+#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_I2C_TIMING0
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_I2C_TIMING0                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0))
+#define HW_I2C_TIMING0_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4))
+#define HW_I2C_TIMING0_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8))
+#define HW_I2C_TIMING0_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc))
+#define BP_I2C_TIMING0_RSVD2            26
+#define BM_I2C_TIMING0_RSVD2            0xfc000000
+#define BF_I2C_TIMING0_RSVD2(v)         (((v) << 26) & 0xfc000000)
+#define BP_I2C_TIMING0_HIGH_COUNT       16
+#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
+#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING0_RSVD1            10
+#define BM_I2C_TIMING0_RSVD1            0xfc00
+#define BF_I2C_TIMING0_RSVD1(v)         (((v) << 10) & 0xfc00)
+#define BP_I2C_TIMING0_RCV_COUNT        0
+#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
+#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_TIMING1
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_I2C_TIMING1                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0))
+#define HW_I2C_TIMING1_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4))
+#define HW_I2C_TIMING1_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8))
+#define HW_I2C_TIMING1_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc))
+#define BP_I2C_TIMING1_RSVD2            26
+#define BM_I2C_TIMING1_RSVD2            0xfc000000
+#define BF_I2C_TIMING1_RSVD2(v)         (((v) << 26) & 0xfc000000)
+#define BP_I2C_TIMING1_LOW_COUNT        16
+#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
+#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING1_RSVD1            10
+#define BM_I2C_TIMING1_RSVD1            0xfc00
+#define BF_I2C_TIMING1_RSVD1(v)         (((v) << 10) & 0xfc00)
+#define BP_I2C_TIMING1_XMIT_COUNT       0
+#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
+#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_TIMING2
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_I2C_TIMING2                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0))
+#define HW_I2C_TIMING2_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4))
+#define HW_I2C_TIMING2_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8))
+#define HW_I2C_TIMING2_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc))
+#define BP_I2C_TIMING2_RSVD2            26
+#define BM_I2C_TIMING2_RSVD2            0xfc000000
+#define BF_I2C_TIMING2_RSVD2(v)         (((v) << 26) & 0xfc000000)
+#define BP_I2C_TIMING2_BUS_FREE         16
+#define BM_I2C_TIMING2_BUS_FREE         0x3ff0000
+#define BF_I2C_TIMING2_BUS_FREE(v)      (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING2_RSVD1            10
+#define BM_I2C_TIMING2_RSVD1            0xfc00
+#define BF_I2C_TIMING2_RSVD1(v)         (((v) << 10) & 0xfc00)
+#define BP_I2C_TIMING2_LEADIN_COUNT     0
+#define BM_I2C_TIMING2_LEADIN_COUNT     0x3ff
+#define BF_I2C_TIMING2_LEADIN_COUNT(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_CTRL1
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_I2C_CTRL1                                        (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0))
+#define HW_I2C_CTRL1_SET                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4))
+#define HW_I2C_CTRL1_CLR                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8))
+#define HW_I2C_CTRL1_TOG                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc))
+#define BP_I2C_CTRL1_RSVD1                                  29
+#define BM_I2C_CTRL1_RSVD1                                  0xe0000000
+#define BF_I2C_CTRL1_RSVD1(v)                               (((v) << 29) & 0xe0000000)
+#define BP_I2C_CTRL1_CLR_GOT_A_NAK                          28
+#define BM_I2C_CTRL1_CLR_GOT_A_NAK                          0x10000000
+#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING              0x0
+#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR                   0x1
+#define BF_I2C_CTRL1_CLR_GOT_A_NAK(v)                       (((v) << 28) & 0x10000000)
+#define BF_I2C_CTRL1_CLR_GOT_A_NAK_V(v)                     ((BV_I2C_CTRL1_CLR_GOT_A_NAK__##v << 28) & 0x10000000)
+#define BP_I2C_CTRL1_ACK_MODE                               27
+#define BM_I2C_CTRL1_ACK_MODE                               0x8000000
+#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW           0x0
+#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW          0x1
+#define BF_I2C_CTRL1_ACK_MODE(v)                            (((v) << 27) & 0x8000000)
+#define BF_I2C_CTRL1_ACK_MODE_V(v)                          ((BV_I2C_CTRL1_ACK_MODE__##v << 27) & 0x8000000)
+#define BP_I2C_CTRL1_FORCE_DATA_IDLE                        26
+#define BM_I2C_CTRL1_FORCE_DATA_IDLE                        0x4000000
+#define BF_I2C_CTRL1_FORCE_DATA_IDLE(v)                     (((v) << 26) & 0x4000000)
+#define BP_I2C_CTRL1_FORCE_CLK_IDLE                         25
+#define BM_I2C_CTRL1_FORCE_CLK_IDLE                         0x2000000
+#define BF_I2C_CTRL1_FORCE_CLK_IDLE(v)                      (((v) << 25) & 0x2000000)
+#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
+#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) << 24) & 0x1000000)
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                    ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000)
+#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
+#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) << 16) & 0xff0000)
+#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
+#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) << 15) & 0x8000)
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                   ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000)
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) << 14) & 0x4000)
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)          ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000)
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) << 13) & 0x2000)
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)               ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000)
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) << 12) & 0x1000)
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)         ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000)
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) << 11) & 0x800)
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800)
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) << 10) & 0x400)
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)                ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400)
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) << 9) & 0x200)
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200)
+#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
+#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) << 8) & 0x100)
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                      ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100)
+#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
+#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) << 7) & 0x80)
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v)                      ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80)
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) << 6) & 0x40)
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)             ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40)
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) << 5) & 0x20)
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                  ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20)
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) << 4) & 0x10)
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)            ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10)
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) << 3) & 0x8)
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                    ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8)
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) << 2) & 0x4)
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                   ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4)
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) << 1) & 0x2)
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                    ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2)
+#define BP_I2C_CTRL1_SLAVE_IRQ                              0
+#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
+#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) << 0) & 0x1)
+#define BF_I2C_CTRL1_SLAVE_IRQ_V(v)                         ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_STAT
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_I2C_STAT                                             (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50))
+#define BP_I2C_STAT_MASTER_PRESENT                              31
+#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
+#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
+#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
+#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) << 31) & 0x80000000)
+#define BF_I2C_STAT_MASTER_PRESENT_V(v)                         ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000)
+#define BP_I2C_STAT_SLAVE_PRESENT                               30
+#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
+#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
+#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
+#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) << 30) & 0x40000000)
+#define BF_I2C_STAT_SLAVE_PRESENT_V(v)                          ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000)
+#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
+#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
+#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) << 29) & 0x20000000)
+#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v)                        ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000)
+#define BP_I2C_STAT_GOT_A_NAK                                   28
+#define BM_I2C_STAT_GOT_A_NAK                                   0x10000000
+#define BV_I2C_STAT_GOT_A_NAK__NO_NAK                           0x0
+#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK                     0x1
+#define BF_I2C_STAT_GOT_A_NAK(v)                                (((v) << 28) & 0x10000000)
+#define BF_I2C_STAT_GOT_A_NAK_V(v)                              ((BV_I2C_STAT_GOT_A_NAK__##v << 28) & 0x10000000)
+#define BP_I2C_STAT_RSVD1                                       24
+#define BM_I2C_STAT_RSVD1                                       0xf000000
+#define BF_I2C_STAT_RSVD1(v)                                    (((v) << 24) & 0xf000000)
+#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
+#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) << 16) & 0xff0000)
+#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
+#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) << 15) & 0x8000)
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                     ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000)
+#define BP_I2C_STAT_SLAVE_FOUND                                 14
+#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
+#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
+#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
+#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) << 14) & 0x4000)
+#define BF_I2C_STAT_SLAVE_FOUND_V(v)                            ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000)
+#define BP_I2C_STAT_SLAVE_SEARCHING                             13
+#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
+#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
+#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
+#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) << 13) & 0x2000)
+#define BF_I2C_STAT_SLAVE_SEARCHING_V(v)                        ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000)
+#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
+#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) << 12) & 0x1000)
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                   ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000)
+#define BP_I2C_STAT_BUS_BUSY                                    11
+#define BM_I2C_STAT_BUS_BUSY                                    0x800
+#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
+#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
+#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) << 11) & 0x800)
+#define BF_I2C_STAT_BUS_BUSY_V(v)                               ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800)
+#define BP_I2C_STAT_CLK_GEN_BUSY                                10
+#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
+#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
+#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
+#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) << 10) & 0x400)
+#define BF_I2C_STAT_CLK_GEN_BUSY_V(v)                           ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400)
+#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
+#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
+#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) << 9) & 0x200)
+#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v)                       ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200)
+#define BP_I2C_STAT_SLAVE_BUSY                                  8
+#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
+#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
+#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
+#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) << 8) & 0x100)
+#define BF_I2C_STAT_SLAVE_BUSY_V(v)                             ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100)
+#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
+#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) << 7) & 0x80)
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                   ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80)
+#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
+#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) << 6) & 0x40)
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)          ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40)
+#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
+#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) << 5) & 0x20)
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)               ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20)
+#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
+#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) << 4) & 0x10)
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)         ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10)
+#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
+#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) << 3) & 0x8)
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8)
+#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
+#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) << 2) & 0x4)
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)                ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
+#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
+#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) << 1) & 0x2)
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2)
+#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
+#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) << 0) & 0x1)
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                      ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_DATA
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_I2C_DATA         (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60))
+#define BP_I2C_DATA_DATA    0
+#define BM_I2C_DATA_DATA    0xffffffff
+#define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_I2C_DEBUG0
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_I2C_DEBUG0                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0))
+#define HW_I2C_DEBUG0_SET               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4))
+#define HW_I2C_DEBUG0_CLR               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8))
+#define HW_I2C_DEBUG0_TOG               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc))
+#define BP_I2C_DEBUG0_DMAREQ            31
+#define BM_I2C_DEBUG0_DMAREQ            0x80000000
+#define BF_I2C_DEBUG0_DMAREQ(v)         (((v) << 31) & 0x80000000)
+#define BP_I2C_DEBUG0_DMAENDCMD         30
+#define BM_I2C_DEBUG0_DMAENDCMD         0x40000000
+#define BF_I2C_DEBUG0_DMAENDCMD(v)      (((v) << 30) & 0x40000000)
+#define BP_I2C_DEBUG0_DMAKICK           29
+#define BM_I2C_DEBUG0_DMAKICK           0x20000000
+#define BF_I2C_DEBUG0_DMAKICK(v)        (((v) << 29) & 0x20000000)
+#define BP_I2C_DEBUG0_DMATERMINATE      28
+#define BM_I2C_DEBUG0_DMATERMINATE      0x10000000
+#define BF_I2C_DEBUG0_DMATERMINATE(v)   (((v) << 28) & 0x10000000)
+#define BP_I2C_DEBUG0_TBD               26
+#define BM_I2C_DEBUG0_TBD               0xc000000
+#define BF_I2C_DEBUG0_TBD(v)            (((v) << 26) & 0xc000000)
+#define BP_I2C_DEBUG0_DMA_STATE         16
+#define BM_I2C_DEBUG0_DMA_STATE         0x3ff0000
+#define BF_I2C_DEBUG0_DMA_STATE(v)      (((v) << 16) & 0x3ff0000)
+#define BP_I2C_DEBUG0_START_TOGGLE      15
+#define BM_I2C_DEBUG0_START_TOGGLE      0x8000
+#define BF_I2C_DEBUG0_START_TOGGLE(v)   (((v) << 15) & 0x8000)
+#define BP_I2C_DEBUG0_STOP_TOGGLE       14
+#define BM_I2C_DEBUG0_STOP_TOGGLE       0x4000
+#define BF_I2C_DEBUG0_STOP_TOGGLE(v)    (((v) << 14) & 0x4000)
+#define BP_I2C_DEBUG0_GRAB_TOGGLE       13
+#define BM_I2C_DEBUG0_GRAB_TOGGLE       0x2000
+#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)    (((v) << 13) & 0x2000)
+#define BP_I2C_DEBUG0_CHANGE_TOGGLE     12
+#define BM_I2C_DEBUG0_CHANGE_TOGGLE     0x1000
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)  (((v) << 12) & 0x1000)
+#define BP_I2C_DEBUG0_TESTMODE          11
+#define BM_I2C_DEBUG0_TESTMODE          0x800
+#define BF_I2C_DEBUG0_TESTMODE(v)       (((v) << 11) & 0x800)
+#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK    10
+#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK    0x400
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400)
+#define BP_I2C_DEBUG0_SLAVE_STATE       0
+#define BM_I2C_DEBUG0_SLAVE_STATE       0x3ff
+#define BF_I2C_DEBUG0_SLAVE_STATE(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_DEBUG1
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_I2C_DEBUG1                       (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0))
+#define HW_I2C_DEBUG1_SET                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4))
+#define HW_I2C_DEBUG1_CLR                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8))
+#define HW_I2C_DEBUG1_TOG                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc))
+#define BP_I2C_DEBUG1_I2C_CLK_IN            31
+#define BM_I2C_DEBUG1_I2C_CLK_IN            0x80000000
+#define BF_I2C_DEBUG1_I2C_CLK_IN(v)         (((v) << 31) & 0x80000000)
+#define BP_I2C_DEBUG1_I2C_DATA_IN           30
+#define BM_I2C_DEBUG1_I2C_DATA_IN           0x40000000
+#define BF_I2C_DEBUG1_I2C_DATA_IN(v)        (((v) << 30) & 0x40000000)
+#define BP_I2C_DEBUG1_RSVD4                 28
+#define BM_I2C_DEBUG1_RSVD4                 0x30000000
+#define BF_I2C_DEBUG1_RSVD4(v)              (((v) << 28) & 0x30000000)
+#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES      24
+#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES      0xf000000
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)   (((v) << 24) & 0xf000000)
+#define BP_I2C_DEBUG1_CLK_GEN_STATE         16
+#define BM_I2C_DEBUG1_CLK_GEN_STATE         0xff0000
+#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)      (((v) << 16) & 0xff0000)
+#define BP_I2C_DEBUG1_RSVD2                 11
+#define BM_I2C_DEBUG1_RSVD2                 0xf800
+#define BF_I2C_DEBUG1_RSVD2(v)              (((v) << 11) & 0xf800)
+#define BP_I2C_DEBUG1_LST_MODE              9
+#define BM_I2C_DEBUG1_LST_MODE              0x600
+#define BV_I2C_DEBUG1_LST_MODE__BCAST       0x0
+#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE    0x1
+#define BV_I2C_DEBUG1_LST_MODE__MY_READ     0x2
+#define BV_I2C_DEBUG1_LST_MODE__NOT_ME      0x3
+#define BF_I2C_DEBUG1_LST_MODE(v)           (((v) << 9) & 0x600)
+#define BF_I2C_DEBUG1_LST_MODE_V(v)         ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600)
+#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST      8
+#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST      0x100
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)   (((v) << 8) & 0x100)
+#define BP_I2C_DEBUG1_RSVD1                 5
+#define BM_I2C_DEBUG1_RSVD1                 0xe0
+#define BF_I2C_DEBUG1_RSVD1(v)              (((v) << 5) & 0xe0)
+#define BP_I2C_DEBUG1_FORCE_CLK_ON          4
+#define BM_I2C_DEBUG1_FORCE_CLK_ON          0x10
+#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)       (((v) << 4) & 0x10)
+#define BP_I2C_DEBUG1_FORCE_ARB_LOSS        3
+#define BM_I2C_DEBUG1_FORCE_ARB_LOSS        0x8
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)     (((v) << 3) & 0x8)
+#define BP_I2C_DEBUG1_FORCE_RCV_ACK         2
+#define BM_I2C_DEBUG1_FORCE_RCV_ACK         0x4
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)      (((v) << 2) & 0x4)
+#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE     1
+#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE     0x2
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)  (((v) << 1) & 0x2)
+#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE      0
+#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE      0x1
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_VERSION
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_I2C_VERSION          (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90))
+#define BP_I2C_VERSION_MAJOR    24
+#define BM_I2C_VERSION_MAJOR    0xff000000
+#define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_I2C_VERSION_MINOR    16
+#define BM_I2C_VERSION_MINOR    0xff0000
+#define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_I2C_VERSION_STEP     0
+#define BM_I2C_VERSION_STEP     0xffff
+#define BF_I2C_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-icoll.h b/firmware/target/arm/imx233/regs/imx233/regs-icoll.h
new file mode 100644
index 0000000000..e110c52ba1
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-icoll.h
@@ -0,0 +1,350 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__ICOLL__H__
+#define __HEADERGEN__IMX233__ICOLL__H__
+
+#define REGS_ICOLL_BASE (0x80000000)
+
+#define REGS_ICOLL_VERSION "3.2.0"
+
+/**
+ * Register: HW_ICOLL_VECTOR
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_ICOLL_VECTOR                 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0))
+#define HW_ICOLL_VECTOR_SET             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4))
+#define HW_ICOLL_VECTOR_CLR             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8))
+#define HW_ICOLL_VECTOR_TOG             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc))
+#define BP_ICOLL_VECTOR_IRQVECTOR       2
+#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
+#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) << 2) & 0xfffffffc)
+#define BP_ICOLL_VECTOR_RSRVD1          0
+#define BM_ICOLL_VECTOR_RSRVD1          0x3
+#define BF_ICOLL_VECTOR_RSRVD1(v)       (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_ICOLL_LEVELACK
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_ICOLL_LEVELACK                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10))
+#define BP_ICOLL_LEVELACK_RSRVD1                4
+#define BM_ICOLL_LEVELACK_RSRVD1                0xfffffff0
+#define BF_ICOLL_LEVELACK_RSRVD1(v)             (((v) << 4) & 0xfffffff0)
+#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
+#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
+#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) << 0) & 0xf)
+#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v)      ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf)
+
+/**
+ * Register: HW_ICOLL_CTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_ICOLL_CTRL                           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0))
+#define HW_ICOLL_CTRL_SET                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4))
+#define HW_ICOLL_CTRL_CLR                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8))
+#define HW_ICOLL_CTRL_TOG                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc))
+#define BP_ICOLL_CTRL_SFTRST                    31
+#define BM_ICOLL_CTRL_SFTRST                    0x80000000
+#define BV_ICOLL_CTRL_SFTRST__RUN               0x0
+#define BV_ICOLL_CTRL_SFTRST__IN_RESET          0x1
+#define BF_ICOLL_CTRL_SFTRST(v)                 (((v) << 31) & 0x80000000)
+#define BF_ICOLL_CTRL_SFTRST_V(v)               ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_ICOLL_CTRL_CLKGATE                   30
+#define BM_ICOLL_CTRL_CLKGATE                   0x40000000
+#define BV_ICOLL_CTRL_CLKGATE__RUN              0x0
+#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS        0x1
+#define BF_ICOLL_CTRL_CLKGATE(v)                (((v) << 30) & 0x40000000)
+#define BF_ICOLL_CTRL_CLKGATE_V(v)              ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_ICOLL_CTRL_RSRVD3                    24
+#define BM_ICOLL_CTRL_RSRVD3                    0x3f000000
+#define BF_ICOLL_CTRL_RSRVD3(v)                 (((v) << 24) & 0x3f000000)
+#define BP_ICOLL_CTRL_VECTOR_PITCH              21
+#define BM_ICOLL_CTRL_VECTOR_PITCH              0xe00000
+#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4         0x1
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8         0x2
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12        0x3
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16        0x4
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20        0x5
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24        0x6
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28        0x7
+#define BF_ICOLL_CTRL_VECTOR_PITCH(v)           (((v) << 21) & 0xe00000)
+#define BF_ICOLL_CTRL_VECTOR_PITCH_V(v)         ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000)
+#define BP_ICOLL_CTRL_BYPASS_FSM                20
+#define BM_ICOLL_CTRL_BYPASS_FSM                0x100000
+#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL        0x0
+#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS        0x1
+#define BF_ICOLL_CTRL_BYPASS_FSM(v)             (((v) << 20) & 0x100000)
+#define BF_ICOLL_CTRL_BYPASS_FSM_V(v)           ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000)
+#define BP_ICOLL_CTRL_NO_NESTING                19
+#define BM_ICOLL_CTRL_NO_NESTING                0x80000
+#define BV_ICOLL_CTRL_NO_NESTING__NORMAL        0x0
+#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST       0x1
+#define BF_ICOLL_CTRL_NO_NESTING(v)             (((v) << 19) & 0x80000)
+#define BF_ICOLL_CTRL_NO_NESTING_V(v)           ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000)
+#define BP_ICOLL_CTRL_ARM_RSE_MODE              18
+#define BM_ICOLL_CTRL_ARM_RSE_MODE              0x40000
+#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)           (((v) << 18) & 0x40000)
+#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE          17
+#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE          0x20000
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE  0x1
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)       (((v) << 17) & 0x20000)
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)     ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000)
+#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE          16
+#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE          0x10000
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE  0x1
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)       (((v) << 16) & 0x10000)
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)     ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000)
+#define BP_ICOLL_CTRL_RSRVD1                    0
+#define BM_ICOLL_CTRL_RSRVD1                    0xffff
+#define BF_ICOLL_CTRL_RSRVD1(v)                 (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_ICOLL_VBASE
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_ICOLL_VBASE                  (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x0))
+#define HW_ICOLL_VBASE_SET              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x4))
+#define HW_ICOLL_VBASE_CLR              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0x8))
+#define HW_ICOLL_VBASE_TOG              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40 + 0xc))
+#define BP_ICOLL_VBASE_TABLE_ADDRESS    2
+#define BM_ICOLL_VBASE_TABLE_ADDRESS    0xfffffffc
+#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc)
+#define BP_ICOLL_VBASE_RSRVD1           0
+#define BM_ICOLL_VBASE_RSRVD1           0x3
+#define BF_ICOLL_VBASE_RSRVD1(v)        (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_ICOLL_STAT
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_ICOLL_STAT                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x70))
+#define BP_ICOLL_STAT_RSRVD1            7
+#define BM_ICOLL_STAT_RSRVD1            0xffffff80
+#define BF_ICOLL_STAT_RSRVD1(v)         (((v) << 7) & 0xffffff80)
+#define BP_ICOLL_STAT_VECTOR_NUMBER     0
+#define BM_ICOLL_STAT_VECTOR_NUMBER     0x7f
+#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_ICOLL_RAWn
+ * Address: 0xa0+n*0x10
+ * SCT: yes
+*/
+#define HW_ICOLL_RAWn(n)            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x0))
+#define HW_ICOLL_RAWn_SET(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x4))
+#define HW_ICOLL_RAWn_CLR(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0x8))
+#define HW_ICOLL_RAWn_TOG(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0xa0+(n)*0x10 + 0xc))
+#define BP_ICOLL_RAWn_RAW_IRQS      0
+#define BM_ICOLL_RAWn_RAW_IRQS      0xffffffff
+#define BF_ICOLL_RAWn_RAW_IRQS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_INTERRUPTn
+ * Address: 0x120+n*0x10
+ * SCT: yes
+*/
+#define HW_ICOLL_INTERRUPTn(n)                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x0))
+#define HW_ICOLL_INTERRUPTn_SET(n)                      (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x4))
+#define HW_ICOLL_INTERRUPTn_CLR(n)                      (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0x8))
+#define HW_ICOLL_INTERRUPTn_TOG(n)                      (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x120+(n)*0x10 + 0xc))
+#define BP_ICOLL_INTERRUPTn_RSRVD1                      5
+#define BM_ICOLL_INTERRUPTn_RSRVD1                      0xffffffe0
+#define BF_ICOLL_INTERRUPTn_RSRVD1(v)                   (((v) << 5) & 0xffffffe0)
+#define BP_ICOLL_INTERRUPTn_ENFIQ                       4
+#define BM_ICOLL_INTERRUPTn_ENFIQ                       0x10
+#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE              0x0
+#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE               0x1
+#define BF_ICOLL_INTERRUPTn_ENFIQ(v)                    (((v) << 4) & 0x10)
+#define BF_ICOLL_INTERRUPTn_ENFIQ_V(v)                  ((BV_ICOLL_INTERRUPTn_ENFIQ__##v << 4) & 0x10)
+#define BP_ICOLL_INTERRUPTn_SOFTIRQ                     3
+#define BM_ICOLL_INTERRUPTn_SOFTIRQ                     0x8
+#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT       0x0
+#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_INTERRUPTn_SOFTIRQ(v)                  (((v) << 3) & 0x8)
+#define BF_ICOLL_INTERRUPTn_SOFTIRQ_V(v)                ((BV_ICOLL_INTERRUPTn_SOFTIRQ__##v << 3) & 0x8)
+#define BP_ICOLL_INTERRUPTn_ENABLE                      2
+#define BM_ICOLL_INTERRUPTn_ENABLE                      0x4
+#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE             0x0
+#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE              0x1
+#define BF_ICOLL_INTERRUPTn_ENABLE(v)                   (((v) << 2) & 0x4)
+#define BF_ICOLL_INTERRUPTn_ENABLE_V(v)                 ((BV_ICOLL_INTERRUPTn_ENABLE__##v << 2) & 0x4)
+#define BP_ICOLL_INTERRUPTn_PRIORITY                    0
+#define BM_ICOLL_INTERRUPTn_PRIORITY                    0x3
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0            0x0
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1            0x1
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2            0x2
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3            0x3
+#define BF_ICOLL_INTERRUPTn_PRIORITY(v)                 (((v) << 0) & 0x3)
+#define BF_ICOLL_INTERRUPTn_PRIORITY_V(v)               ((BV_ICOLL_INTERRUPTn_PRIORITY__##v << 0) & 0x3)
+
+/**
+ * Register: HW_ICOLL_DEBUG
+ * Address: 0x1120
+ * SCT: yes
+*/
+#define HW_ICOLL_DEBUG                              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x0))
+#define HW_ICOLL_DEBUG_SET                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x4))
+#define HW_ICOLL_DEBUG_CLR                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0x8))
+#define HW_ICOLL_DEBUG_TOG                          (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1120 + 0xc))
+#define BP_ICOLL_DEBUG_INSERVICE                    28
+#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
+#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) << 28) & 0xf0000000)
+#define BF_ICOLL_DEBUG_INSERVICE_V(v)               ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000)
+#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
+#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) << 24) & 0xf000000)
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)          ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000)
+#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
+#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) << 20) & 0xf00000)
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)       ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000)
+#define BP_ICOLL_DEBUG_RSRVD2                       18
+#define BM_ICOLL_DEBUG_RSRVD2                       0xc0000
+#define BF_ICOLL_DEBUG_RSRVD2(v)                    (((v) << 18) & 0xc0000)
+#define BP_ICOLL_DEBUG_FIQ                          17
+#define BM_ICOLL_DEBUG_FIQ                          0x20000
+#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) << 17) & 0x20000)
+#define BF_ICOLL_DEBUG_FIQ_V(v)                     ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000)
+#define BP_ICOLL_DEBUG_IRQ                          16
+#define BM_ICOLL_DEBUG_IRQ                          0x10000
+#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) << 16) & 0x10000)
+#define BF_ICOLL_DEBUG_IRQ_V(v)                     ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000)
+#define BP_ICOLL_DEBUG_RSRVD1                       10
+#define BM_ICOLL_DEBUG_RSRVD1                       0xfc00
+#define BF_ICOLL_DEBUG_RSRVD1(v)                    (((v) << 10) & 0xfc00)
+#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
+#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
+#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) << 0) & 0x3ff)
+#define BF_ICOLL_DEBUG_VECTOR_FSM_V(v)              ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff)
+
+/**
+ * Register: HW_ICOLL_DBGREAD0
+ * Address: 0x1130
+ * SCT: yes
+*/
+#define HW_ICOLL_DBGREAD0           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x0))
+#define HW_ICOLL_DBGREAD0_SET       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x4))
+#define HW_ICOLL_DBGREAD0_CLR       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0x8))
+#define HW_ICOLL_DBGREAD0_TOG       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1130 + 0xc))
+#define BP_ICOLL_DBGREAD0_VALUE     0
+#define BM_ICOLL_DBGREAD0_VALUE     0xffffffff
+#define BF_ICOLL_DBGREAD0_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_DBGREAD1
+ * Address: 0x1140
+ * SCT: yes
+*/
+#define HW_ICOLL_DBGREAD1           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x0))
+#define HW_ICOLL_DBGREAD1_SET       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x4))
+#define HW_ICOLL_DBGREAD1_CLR       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0x8))
+#define HW_ICOLL_DBGREAD1_TOG       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1140 + 0xc))
+#define BP_ICOLL_DBGREAD1_VALUE     0
+#define BM_ICOLL_DBGREAD1_VALUE     0xffffffff
+#define BF_ICOLL_DBGREAD1_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_DBGFLAG
+ * Address: 0x1150
+ * SCT: yes
+*/
+#define HW_ICOLL_DBGFLAG            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x0))
+#define HW_ICOLL_DBGFLAG_SET        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x4))
+#define HW_ICOLL_DBGFLAG_CLR        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0x8))
+#define HW_ICOLL_DBGFLAG_TOG        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1150 + 0xc))
+#define BP_ICOLL_DBGFLAG_RSRVD1     16
+#define BM_ICOLL_DBGFLAG_RSRVD1     0xffff0000
+#define BF_ICOLL_DBGFLAG_RSRVD1(v)  (((v) << 16) & 0xffff0000)
+#define BP_ICOLL_DBGFLAG_FLAG       0
+#define BM_ICOLL_DBGFLAG_FLAG       0xffff
+#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_ICOLL_DBGREQUESTn
+ * Address: 0x1160+n*0x10
+ * SCT: yes
+*/
+#define HW_ICOLL_DBGREQUESTn(n)         (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x0))
+#define HW_ICOLL_DBGREQUESTn_SET(n)     (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x4))
+#define HW_ICOLL_DBGREQUESTn_CLR(n)     (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0x8))
+#define HW_ICOLL_DBGREQUESTn_TOG(n)     (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1160+(n)*0x10 + 0xc))
+#define BP_ICOLL_DBGREQUESTn_BITS       0
+#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
+#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_VERSION
+ * Address: 0x11e0
+ * SCT: no
+*/
+#define HW_ICOLL_VERSION            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x11e0))
+#define BP_ICOLL_VERSION_MAJOR      24
+#define BM_ICOLL_VERSION_MAJOR      0xff000000
+#define BF_ICOLL_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_ICOLL_VERSION_MINOR      16
+#define BM_ICOLL_VERSION_MINOR      0xff0000
+#define BF_ICOLL_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_ICOLL_VERSION_STEP       0
+#define BM_ICOLL_VERSION_STEP       0xffff
+#define BF_ICOLL_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ir.h b/firmware/target/arm/imx233/regs/imx233/regs-ir.h
new file mode 100644
index 0000000000..e744b00298
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-ir.h
@@ -0,0 +1,529 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__IR__H__
+#define __HEADERGEN__IMX233__IR__H__
+
+#define REGS_IR_BASE (0x80078000)
+
+#define REGS_IR_VERSION "3.2.0"
+
+/**
+ * Register: HW_IR_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_IR_CTRL                  (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0))
+#define HW_IR_CTRL_SET              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4))
+#define HW_IR_CTRL_CLR              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8))
+#define HW_IR_CTRL_TOG              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc))
+#define BP_IR_CTRL_SFTRST           31
+#define BM_IR_CTRL_SFTRST           0x80000000
+#define BV_IR_CTRL_SFTRST__RUN      0x0
+#define BV_IR_CTRL_SFTRST__RESET    0x1
+#define BF_IR_CTRL_SFTRST(v)        (((v) << 31) & 0x80000000)
+#define BF_IR_CTRL_SFTRST_V(v)      ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_IR_CTRL_CLKGATE          30
+#define BM_IR_CTRL_CLKGATE          0x40000000
+#define BF_IR_CTRL_CLKGATE(v)       (((v) << 30) & 0x40000000)
+#define BP_IR_CTRL_RSVD2            27
+#define BM_IR_CTRL_RSVD2            0x38000000
+#define BF_IR_CTRL_RSVD2(v)         (((v) << 27) & 0x38000000)
+#define BP_IR_CTRL_MTA              24
+#define BM_IR_CTRL_MTA              0x7000000
+#define BV_IR_CTRL_MTA__MTA_10MS    0x0
+#define BV_IR_CTRL_MTA__MTA_5MS     0x1
+#define BV_IR_CTRL_MTA__MTA_1MS     0x2
+#define BV_IR_CTRL_MTA__MTA_500US   0x3
+#define BV_IR_CTRL_MTA__MTA_100US   0x4
+#define BV_IR_CTRL_MTA__MTA_50US    0x5
+#define BV_IR_CTRL_MTA__MTA_10US    0x6
+#define BV_IR_CTRL_MTA__MTA_0       0x7
+#define BF_IR_CTRL_MTA(v)           (((v) << 24) & 0x7000000)
+#define BF_IR_CTRL_MTA_V(v)         ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000)
+#define BP_IR_CTRL_MODE             22
+#define BM_IR_CTRL_MODE             0xc00000
+#define BV_IR_CTRL_MODE__SIR        0x0
+#define BV_IR_CTRL_MODE__MIR        0x1
+#define BV_IR_CTRL_MODE__FIR        0x2
+#define BV_IR_CTRL_MODE__VFIR       0x3
+#define BF_IR_CTRL_MODE(v)          (((v) << 22) & 0xc00000)
+#define BF_IR_CTRL_MODE_V(v)        ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000)
+#define BP_IR_CTRL_SPEED            19
+#define BM_IR_CTRL_SPEED            0x380000
+#define BV_IR_CTRL_SPEED__SPD000    0x0
+#define BV_IR_CTRL_SPEED__SPD001    0x1
+#define BV_IR_CTRL_SPEED__SPD010    0x2
+#define BV_IR_CTRL_SPEED__SPD011    0x3
+#define BV_IR_CTRL_SPEED__SPD100    0x4
+#define BV_IR_CTRL_SPEED__SPD101    0x5
+#define BF_IR_CTRL_SPEED(v)         (((v) << 19) & 0x380000)
+#define BF_IR_CTRL_SPEED_V(v)       ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000)
+#define BP_IR_CTRL_RSVD1            14
+#define BM_IR_CTRL_RSVD1            0x7c000
+#define BF_IR_CTRL_RSVD1(v)         (((v) << 14) & 0x7c000)
+#define BP_IR_CTRL_TC_TIME_DIV      8
+#define BM_IR_CTRL_TC_TIME_DIV      0x3f00
+#define BF_IR_CTRL_TC_TIME_DIV(v)   (((v) << 8) & 0x3f00)
+#define BP_IR_CTRL_TC_TYPE          7
+#define BM_IR_CTRL_TC_TYPE          0x80
+#define BF_IR_CTRL_TC_TYPE(v)       (((v) << 7) & 0x80)
+#define BP_IR_CTRL_SIR_GAP          4
+#define BM_IR_CTRL_SIR_GAP          0x70
+#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
+#define BV_IR_CTRL_SIR_GAP__GAP_5K  0x1
+#define BV_IR_CTRL_SIR_GAP__GAP_1K  0x2
+#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
+#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
+#define BV_IR_CTRL_SIR_GAP__GAP_50  0x5
+#define BV_IR_CTRL_SIR_GAP__GAP_10  0x6
+#define BV_IR_CTRL_SIR_GAP__GAP_0   0x7
+#define BF_IR_CTRL_SIR_GAP(v)       (((v) << 4) & 0x70)
+#define BF_IR_CTRL_SIR_GAP_V(v)     ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70)
+#define BP_IR_CTRL_SIPEN            3
+#define BM_IR_CTRL_SIPEN            0x8
+#define BF_IR_CTRL_SIPEN(v)         (((v) << 3) & 0x8)
+#define BP_IR_CTRL_TCEN             2
+#define BM_IR_CTRL_TCEN             0x4
+#define BF_IR_CTRL_TCEN(v)          (((v) << 2) & 0x4)
+#define BP_IR_CTRL_TXEN             1
+#define BM_IR_CTRL_TXEN             0x2
+#define BF_IR_CTRL_TXEN(v)          (((v) << 1) & 0x2)
+#define BP_IR_CTRL_RXEN             0
+#define BM_IR_CTRL_RXEN             0x1
+#define BF_IR_CTRL_RXEN(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_TXDMA
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_IR_TXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0))
+#define HW_IR_TXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4))
+#define HW_IR_TXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8))
+#define HW_IR_TXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc))
+#define BP_IR_TXDMA_RUN             31
+#define BM_IR_TXDMA_RUN             0x80000000
+#define BF_IR_TXDMA_RUN(v)          (((v) << 31) & 0x80000000)
+#define BP_IR_TXDMA_RSVD2           30
+#define BM_IR_TXDMA_RSVD2           0x40000000
+#define BF_IR_TXDMA_RSVD2(v)        (((v) << 30) & 0x40000000)
+#define BP_IR_TXDMA_EMPTY           29
+#define BM_IR_TXDMA_EMPTY           0x20000000
+#define BF_IR_TXDMA_EMPTY(v)        (((v) << 29) & 0x20000000)
+#define BP_IR_TXDMA_INT             28
+#define BM_IR_TXDMA_INT             0x10000000
+#define BF_IR_TXDMA_INT(v)          (((v) << 28) & 0x10000000)
+#define BP_IR_TXDMA_CHANGE          27
+#define BM_IR_TXDMA_CHANGE          0x8000000
+#define BF_IR_TXDMA_CHANGE(v)       (((v) << 27) & 0x8000000)
+#define BP_IR_TXDMA_NEW_MTA         24
+#define BM_IR_TXDMA_NEW_MTA         0x7000000
+#define BF_IR_TXDMA_NEW_MTA(v)      (((v) << 24) & 0x7000000)
+#define BP_IR_TXDMA_NEW_MODE        22
+#define BM_IR_TXDMA_NEW_MODE        0xc00000
+#define BF_IR_TXDMA_NEW_MODE(v)     (((v) << 22) & 0xc00000)
+#define BP_IR_TXDMA_NEW_SPEED       19
+#define BM_IR_TXDMA_NEW_SPEED       0x380000
+#define BF_IR_TXDMA_NEW_SPEED(v)    (((v) << 19) & 0x380000)
+#define BP_IR_TXDMA_BOF_TYPE        18
+#define BM_IR_TXDMA_BOF_TYPE        0x40000
+#define BF_IR_TXDMA_BOF_TYPE(v)     (((v) << 18) & 0x40000)
+#define BP_IR_TXDMA_XBOFS           12
+#define BM_IR_TXDMA_XBOFS           0x3f000
+#define BF_IR_TXDMA_XBOFS(v)        (((v) << 12) & 0x3f000)
+#define BP_IR_TXDMA_XFER_COUNT      0
+#define BM_IR_TXDMA_XFER_COUNT      0xfff
+#define BF_IR_TXDMA_XFER_COUNT(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_IR_RXDMA
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_IR_RXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0))
+#define HW_IR_RXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4))
+#define HW_IR_RXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8))
+#define HW_IR_RXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc))
+#define BP_IR_RXDMA_RUN             31
+#define BM_IR_RXDMA_RUN             0x80000000
+#define BF_IR_RXDMA_RUN(v)          (((v) << 31) & 0x80000000)
+#define BP_IR_RXDMA_RSVD            10
+#define BM_IR_RXDMA_RSVD            0x7ffffc00
+#define BF_IR_RXDMA_RSVD(v)         (((v) << 10) & 0x7ffffc00)
+#define BP_IR_RXDMA_XFER_COUNT      0
+#define BM_IR_RXDMA_XFER_COUNT      0x3ff
+#define BF_IR_RXDMA_XFER_COUNT(v)   (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_IR_DBGCTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_IR_DBGCTRL                   (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0))
+#define HW_IR_DBGCTRL_SET               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4))
+#define HW_IR_DBGCTRL_CLR               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8))
+#define HW_IR_DBGCTRL_TOG               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc))
+#define BP_IR_DBGCTRL_RSVD2             13
+#define BM_IR_DBGCTRL_RSVD2             0xffffe000
+#define BF_IR_DBGCTRL_RSVD2(v)          (((v) << 13) & 0xffffe000)
+#define BP_IR_DBGCTRL_VFIRSWZ           12
+#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
+#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
+#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
+#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) << 12) & 0x1000)
+#define BF_IR_DBGCTRL_VFIRSWZ_V(v)      ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000)
+#define BP_IR_DBGCTRL_RXFRMOFF          11
+#define BM_IR_DBGCTRL_RXFRMOFF          0x800
+#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) << 11) & 0x800)
+#define BP_IR_DBGCTRL_RXCRCOFF          10
+#define BM_IR_DBGCTRL_RXCRCOFF          0x400
+#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) << 10) & 0x400)
+#define BP_IR_DBGCTRL_RXINVERT          9
+#define BM_IR_DBGCTRL_RXINVERT          0x200
+#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) << 9) & 0x200)
+#define BP_IR_DBGCTRL_TXFRMOFF          8
+#define BM_IR_DBGCTRL_TXFRMOFF          0x100
+#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) << 8) & 0x100)
+#define BP_IR_DBGCTRL_TXCRCOFF          7
+#define BM_IR_DBGCTRL_TXCRCOFF          0x80
+#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) << 7) & 0x80)
+#define BP_IR_DBGCTRL_TXINVERT          6
+#define BM_IR_DBGCTRL_TXINVERT          0x40
+#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) << 6) & 0x40)
+#define BP_IR_DBGCTRL_INTLOOPBACK       5
+#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
+#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) << 5) & 0x20)
+#define BP_IR_DBGCTRL_DUPLEX            4
+#define BM_IR_DBGCTRL_DUPLEX            0x10
+#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) << 4) & 0x10)
+#define BP_IR_DBGCTRL_MIO_RX            3
+#define BM_IR_DBGCTRL_MIO_RX            0x8
+#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) << 3) & 0x8)
+#define BP_IR_DBGCTRL_MIO_TX            2
+#define BM_IR_DBGCTRL_MIO_TX            0x4
+#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) << 2) & 0x4)
+#define BP_IR_DBGCTRL_MIO_SCLK          1
+#define BM_IR_DBGCTRL_MIO_SCLK          0x2
+#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) << 1) & 0x2)
+#define BP_IR_DBGCTRL_MIO_EN            0
+#define BM_IR_DBGCTRL_MIO_EN            0x1
+#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_INTR
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_IR_INTR                          (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0))
+#define HW_IR_INTR_SET                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4))
+#define HW_IR_INTR_CLR                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8))
+#define HW_IR_INTR_TOG                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc))
+#define BP_IR_INTR_RSVD2                    23
+#define BM_IR_INTR_RSVD2                    0xff800000
+#define BF_IR_INTR_RSVD2(v)                 (((v) << 23) & 0xff800000)
+#define BP_IR_INTR_RXABORT_IRQ_EN           22
+#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
+#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
+#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
+#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) << 22) & 0x400000)
+#define BF_IR_INTR_RXABORT_IRQ_EN_V(v)      ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000)
+#define BP_IR_INTR_SPEED_IRQ_EN             21
+#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
+#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
+#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
+#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) << 21) & 0x200000)
+#define BF_IR_INTR_SPEED_IRQ_EN_V(v)        ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000)
+#define BP_IR_INTR_RXOF_IRQ_EN              20
+#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
+#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) << 20) & 0x100000)
+#define BF_IR_INTR_RXOF_IRQ_EN_V(v)         ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000)
+#define BP_IR_INTR_TXUF_IRQ_EN              19
+#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
+#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) << 19) & 0x80000)
+#define BF_IR_INTR_TXUF_IRQ_EN_V(v)         ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000)
+#define BP_IR_INTR_TC_IRQ_EN                18
+#define BM_IR_INTR_TC_IRQ_EN                0x40000
+#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) << 18) & 0x40000)
+#define BF_IR_INTR_TC_IRQ_EN_V(v)           ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000)
+#define BP_IR_INTR_RX_IRQ_EN                17
+#define BM_IR_INTR_RX_IRQ_EN                0x20000
+#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) << 17) & 0x20000)
+#define BF_IR_INTR_RX_IRQ_EN_V(v)           ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000)
+#define BP_IR_INTR_TX_IRQ_EN                16
+#define BM_IR_INTR_TX_IRQ_EN                0x10000
+#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) << 16) & 0x10000)
+#define BF_IR_INTR_TX_IRQ_EN_V(v)           ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000)
+#define BP_IR_INTR_RSVD1                    7
+#define BM_IR_INTR_RSVD1                    0xff80
+#define BF_IR_INTR_RSVD1(v)                 (((v) << 7) & 0xff80)
+#define BP_IR_INTR_RXABORT_IRQ              6
+#define BM_IR_INTR_RXABORT_IRQ              0x40
+#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
+#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
+#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) << 6) & 0x40)
+#define BF_IR_INTR_RXABORT_IRQ_V(v)         ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40)
+#define BP_IR_INTR_SPEED_IRQ                5
+#define BM_IR_INTR_SPEED_IRQ                0x20
+#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
+#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
+#define BF_IR_INTR_SPEED_IRQ(v)             (((v) << 5) & 0x20)
+#define BF_IR_INTR_SPEED_IRQ_V(v)           ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20)
+#define BP_IR_INTR_RXOF_IRQ                 4
+#define BM_IR_INTR_RXOF_IRQ                 0x10
+#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_RXOF_IRQ(v)              (((v) << 4) & 0x10)
+#define BF_IR_INTR_RXOF_IRQ_V(v)            ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10)
+#define BP_IR_INTR_TXUF_IRQ                 3
+#define BM_IR_INTR_TXUF_IRQ                 0x8
+#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_TXUF_IRQ(v)              (((v) << 3) & 0x8)
+#define BF_IR_INTR_TXUF_IRQ_V(v)            ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8)
+#define BP_IR_INTR_TC_IRQ                   2
+#define BM_IR_INTR_TC_IRQ                   0x4
+#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TC_IRQ(v)                (((v) << 2) & 0x4)
+#define BF_IR_INTR_TC_IRQ_V(v)              ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4)
+#define BP_IR_INTR_RX_IRQ                   1
+#define BM_IR_INTR_RX_IRQ                   0x2
+#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_RX_IRQ(v)                (((v) << 1) & 0x2)
+#define BF_IR_INTR_RX_IRQ_V(v)              ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2)
+#define BP_IR_INTR_TX_IRQ                   0
+#define BM_IR_INTR_TX_IRQ                   0x1
+#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TX_IRQ(v)                (((v) << 0) & 0x1)
+#define BF_IR_INTR_TX_IRQ_V(v)              ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_IR_DATA
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_IR_DATA          (*(volatile unsigned long *)(REGS_IR_BASE + 0x50))
+#define BP_IR_DATA_DATA     0
+#define BM_IR_DATA_DATA     0xffffffff
+#define BF_IR_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_IR_STAT
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_IR_STAT                              (*(volatile unsigned long *)(REGS_IR_BASE + 0x60))
+#define BP_IR_STAT_PRESENT                      31
+#define BM_IR_STAT_PRESENT                      0x80000000
+#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
+#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
+#define BF_IR_STAT_PRESENT(v)                   (((v) << 31) & 0x80000000)
+#define BF_IR_STAT_PRESENT_V(v)                 ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_IR_STAT_MODE_ALLOWED                 29
+#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
+#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
+#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
+#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
+#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
+#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) << 29) & 0x60000000)
+#define BF_IR_STAT_MODE_ALLOWED_V(v)            ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000)
+#define BP_IR_STAT_ANY_IRQ                      28
+#define BM_IR_STAT_ANY_IRQ                      0x10000000
+#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
+#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
+#define BF_IR_STAT_ANY_IRQ(v)                   (((v) << 28) & 0x10000000)
+#define BF_IR_STAT_ANY_IRQ_V(v)                 ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000)
+#define BP_IR_STAT_RSVD2                        23
+#define BM_IR_STAT_RSVD2                        0xf800000
+#define BF_IR_STAT_RSVD2(v)                     (((v) << 23) & 0xf800000)
+#define BP_IR_STAT_RXABORT_SUMMARY              22
+#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
+#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
+#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
+#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) << 22) & 0x400000)
+#define BF_IR_STAT_RXABORT_SUMMARY_V(v)         ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000)
+#define BP_IR_STAT_SPEED_SUMMARY                21
+#define BM_IR_STAT_SPEED_SUMMARY                0x200000
+#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
+#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
+#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) << 21) & 0x200000)
+#define BF_IR_STAT_SPEED_SUMMARY_V(v)           ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000)
+#define BP_IR_STAT_RXOF_SUMMARY                 20
+#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
+#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) << 20) & 0x100000)
+#define BF_IR_STAT_RXOF_SUMMARY_V(v)            ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000)
+#define BP_IR_STAT_TXUF_SUMMARY                 19
+#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
+#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) << 19) & 0x80000)
+#define BF_IR_STAT_TXUF_SUMMARY_V(v)            ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000)
+#define BP_IR_STAT_TC_SUMMARY                   18
+#define BM_IR_STAT_TC_SUMMARY                   0x40000
+#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TC_SUMMARY(v)                (((v) << 18) & 0x40000)
+#define BF_IR_STAT_TC_SUMMARY_V(v)              ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000)
+#define BP_IR_STAT_RX_SUMMARY                   17
+#define BM_IR_STAT_RX_SUMMARY                   0x20000
+#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_RX_SUMMARY(v)                (((v) << 17) & 0x20000)
+#define BF_IR_STAT_RX_SUMMARY_V(v)              ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000)
+#define BP_IR_STAT_TX_SUMMARY                   16
+#define BM_IR_STAT_TX_SUMMARY                   0x10000
+#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TX_SUMMARY(v)                (((v) << 16) & 0x10000)
+#define BF_IR_STAT_TX_SUMMARY_V(v)              ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000)
+#define BP_IR_STAT_RSVD1                        3
+#define BM_IR_STAT_RSVD1                        0xfff8
+#define BF_IR_STAT_RSVD1(v)                     (((v) << 3) & 0xfff8)
+#define BP_IR_STAT_MEDIA_BUSY                   2
+#define BM_IR_STAT_MEDIA_BUSY                   0x4
+#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) << 2) & 0x4)
+#define BP_IR_STAT_RX_ACTIVE                    1
+#define BM_IR_STAT_RX_ACTIVE                    0x2
+#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) << 1) & 0x2)
+#define BP_IR_STAT_TX_ACTIVE                    0
+#define BM_IR_STAT_TX_ACTIVE                    0x1
+#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_TCCTRL
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_IR_TCCTRL                (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0))
+#define HW_IR_TCCTRL_SET            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4))
+#define HW_IR_TCCTRL_CLR            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8))
+#define HW_IR_TCCTRL_TOG            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc))
+#define BP_IR_TCCTRL_INIT           31
+#define BM_IR_TCCTRL_INIT           0x80000000
+#define BF_IR_TCCTRL_INIT(v)        (((v) << 31) & 0x80000000)
+#define BP_IR_TCCTRL_GO             30
+#define BM_IR_TCCTRL_GO             0x40000000
+#define BF_IR_TCCTRL_GO(v)          (((v) << 30) & 0x40000000)
+#define BP_IR_TCCTRL_BUSY           29
+#define BM_IR_TCCTRL_BUSY           0x20000000
+#define BF_IR_TCCTRL_BUSY(v)        (((v) << 29) & 0x20000000)
+#define BP_IR_TCCTRL_RSVD           25
+#define BM_IR_TCCTRL_RSVD           0x1e000000
+#define BF_IR_TCCTRL_RSVD(v)        (((v) << 25) & 0x1e000000)
+#define BP_IR_TCCTRL_TEMIC          24
+#define BM_IR_TCCTRL_TEMIC          0x1000000
+#define BV_IR_TCCTRL_TEMIC__LOW     0x0
+#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
+#define BF_IR_TCCTRL_TEMIC(v)       (((v) << 24) & 0x1000000)
+#define BF_IR_TCCTRL_TEMIC_V(v)     ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000)
+#define BP_IR_TCCTRL_EXT_DATA       16
+#define BM_IR_TCCTRL_EXT_DATA       0xff0000
+#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) << 16) & 0xff0000)
+#define BP_IR_TCCTRL_DATA           8
+#define BM_IR_TCCTRL_DATA           0xff00
+#define BF_IR_TCCTRL_DATA(v)        (((v) << 8) & 0xff00)
+#define BP_IR_TCCTRL_ADDR           5
+#define BM_IR_TCCTRL_ADDR           0xe0
+#define BF_IR_TCCTRL_ADDR(v)        (((v) << 5) & 0xe0)
+#define BP_IR_TCCTRL_INDX           1
+#define BM_IR_TCCTRL_INDX           0x1e
+#define BF_IR_TCCTRL_INDX(v)        (((v) << 1) & 0x1e)
+#define BP_IR_TCCTRL_C              0
+#define BM_IR_TCCTRL_C              0x1
+#define BF_IR_TCCTRL_C(v)           (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_SI_READ
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_IR_SI_READ           (*(volatile unsigned long *)(REGS_IR_BASE + 0x80))
+#define BP_IR_SI_READ_RSVD1     9
+#define BM_IR_SI_READ_RSVD1     0xfffffe00
+#define BF_IR_SI_READ_RSVD1(v)  (((v) << 9) & 0xfffffe00)
+#define BP_IR_SI_READ_ABORT     8
+#define BM_IR_SI_READ_ABORT     0x100
+#define BF_IR_SI_READ_ABORT(v)  (((v) << 8) & 0x100)
+#define BP_IR_SI_READ_DATA      0
+#define BM_IR_SI_READ_DATA      0xff
+#define BF_IR_SI_READ_DATA(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_IR_DEBUG
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_IR_DEBUG                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x90))
+#define BP_IR_DEBUG_RSVD1           6
+#define BM_IR_DEBUG_RSVD1           0xffffffc0
+#define BF_IR_DEBUG_RSVD1(v)        (((v) << 6) & 0xffffffc0)
+#define BP_IR_DEBUG_TXDMAKICK       5
+#define BM_IR_DEBUG_TXDMAKICK       0x20
+#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) << 5) & 0x20)
+#define BP_IR_DEBUG_RXDMAKICK       4
+#define BM_IR_DEBUG_RXDMAKICK       0x10
+#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) << 4) & 0x10)
+#define BP_IR_DEBUG_TXDMAEND        3
+#define BM_IR_DEBUG_TXDMAEND        0x8
+#define BF_IR_DEBUG_TXDMAEND(v)     (((v) << 3) & 0x8)
+#define BP_IR_DEBUG_RXDMAEND        2
+#define BM_IR_DEBUG_RXDMAEND        0x4
+#define BF_IR_DEBUG_RXDMAEND(v)     (((v) << 2) & 0x4)
+#define BP_IR_DEBUG_TXDMAREQ        1
+#define BM_IR_DEBUG_TXDMAREQ        0x2
+#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) << 1) & 0x2)
+#define BP_IR_DEBUG_RXDMAREQ        0
+#define BM_IR_DEBUG_RXDMAREQ        0x1
+#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_VERSION
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_IR_VERSION           (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0))
+#define BP_IR_VERSION_MAJOR     24
+#define BM_IR_VERSION_MAJOR     0xff000000
+#define BF_IR_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
+#define BP_IR_VERSION_MINOR     16
+#define BM_IR_VERSION_MINOR     0xff0000
+#define BF_IR_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
+#define BP_IR_VERSION_STEP      0
+#define BM_IR_VERSION_STEP      0xffff
+#define BF_IR_VERSION_STEP(v)   (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h b/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h
new file mode 100644
index 0000000000..2e56999191
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h
@@ -0,0 +1,886 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__LCDIF__H__
+#define __HEADERGEN__IMX233__LCDIF__H__
+
+#define REGS_LCDIF_BASE (0x80030000)
+
+#define REGS_LCDIF_VERSION "3.2.0"
+
+/**
+ * Register: HW_LCDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL                                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
+#define HW_LCDIF_CTRL_SET                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
+#define HW_LCDIF_CTRL_CLR                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
+#define HW_LCDIF_CTRL_TOG                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
+#define BP_LCDIF_CTRL_SFTRST                                            31
+#define BM_LCDIF_CTRL_SFTRST                                            0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                                         (((v) << 31) & 0x80000000)
+#define BP_LCDIF_CTRL_CLKGATE                                           30
+#define BM_LCDIF_CTRL_CLKGATE                                           0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                                        (((v) << 30) & 0x40000000)
+#define BP_LCDIF_CTRL_YCBCR422_INPUT                                    29
+#define BM_LCDIF_CTRL_YCBCR422_INPUT                                    0x20000000
+#define BF_LCDIF_CTRL_YCBCR422_INPUT(v)                                 (((v) << 29) & 0x20000000)
+#define BP_LCDIF_CTRL_RSRVD0                                            28
+#define BM_LCDIF_CTRL_RSRVD0                                            0x10000000
+#define BF_LCDIF_CTRL_RSRVD0(v)                                         (((v) << 28) & 0x10000000)
+#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               27
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               0x8000000
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                            (((v) << 27) & 0x8000000)
+#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                                    26
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                                    0x4000000
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT                 0x0
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT                0x1
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                                 (((v) << 26) & 0x4000000)
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                               ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 26) & 0x4000000)
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                                    21
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                                    0x3e00000
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                                 (((v) << 21) & 0x3e00000)
+#define BP_LCDIF_CTRL_DVI_MODE                                          20
+#define BM_LCDIF_CTRL_DVI_MODE                                          0x100000
+#define BF_LCDIF_CTRL_DVI_MODE(v)                                       (((v) << 20) & 0x100000)
+#define BP_LCDIF_CTRL_BYPASS_COUNT                                      19
+#define BM_LCDIF_CTRL_BYPASS_COUNT                                      0x80000
+#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                                   (((v) << 19) & 0x80000)
+#define BP_LCDIF_CTRL_VSYNC_MODE                                        18
+#define BM_LCDIF_CTRL_VSYNC_MODE                                        0x40000
+#define BF_LCDIF_CTRL_VSYNC_MODE(v)                                     (((v) << 18) & 0x40000)
+#define BP_LCDIF_CTRL_DOTCLK_MODE                                       17
+#define BM_LCDIF_CTRL_DOTCLK_MODE                                       0x20000
+#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                                    (((v) << 17) & 0x20000)
+#define BP_LCDIF_CTRL_DATA_SELECT                                       16
+#define BM_LCDIF_CTRL_DATA_SELECT                                       0x10000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                             0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                            0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                                    (((v) << 16) & 0x10000)
+#define BF_LCDIF_CTRL_DATA_SELECT_V(v)                                  ((BV_LCDIF_CTRL_DATA_SELECT__##v << 16) & 0x10000)
+#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                14
+#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                0xc000
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP                       0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN                 0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP               0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES                0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP                      0x2
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP                 0x3
+#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v)                             (((v) << 14) & 0xc000)
+#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE_V(v)                           ((BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__##v << 14) & 0xc000)
+#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  12
+#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  0x3000
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP                         0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN                   0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP                 0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES                  0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP                        0x2
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP                   0x3
+#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v)                               (((v) << 12) & 0x3000)
+#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE_V(v)                             ((BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__##v << 12) & 0x3000)
+#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 10
+#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 0xc00
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT                         0x0
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT                          0x1
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT                         0x2
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT                         0x3
+#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v)                              (((v) << 10) & 0xc00)
+#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH_V(v)                            ((BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__##v << 10) & 0xc00)
+#define BP_LCDIF_CTRL_WORD_LENGTH                                       8
+#define BM_LCDIF_CTRL_WORD_LENGTH                                       0x300
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                               0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                                0x1
+#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT                               0x2
+#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT                               0x3
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                                    (((v) << 8) & 0x300)
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)                                  ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 8) & 0x300)
+#define BP_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               7
+#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               0x80
+#define BF_LCDIF_CTRL_RGB_TO_YCBCR422_CSC(v)                            (((v) << 7) & 0x80)
+#define BP_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              6
+#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              0x40
+#define BF_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(v)                           (((v) << 6) & 0x40)
+#define BP_LCDIF_CTRL_LCDIF_MASTER                                      5
+#define BM_LCDIF_CTRL_LCDIF_MASTER                                      0x20
+#define BF_LCDIF_CTRL_LCDIF_MASTER(v)                                   (((v) << 5) & 0x20)
+#define BP_LCDIF_CTRL_DMA_BURST_LENGTH                                  4
+#define BM_LCDIF_CTRL_DMA_BURST_LENGTH                                  0x10
+#define BF_LCDIF_CTRL_DMA_BURST_LENGTH(v)                               (((v) << 4) & 0x10)
+#define BP_LCDIF_CTRL_DATA_FORMAT_16_BIT                                3
+#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT                                0x8
+#define BF_LCDIF_CTRL_DATA_FORMAT_16_BIT(v)                             (((v) << 3) & 0x8)
+#define BP_LCDIF_CTRL_DATA_FORMAT_18_BIT                                2
+#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT                                0x4
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID           0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID           0x1
+#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT(v)                             (((v) << 2) & 0x4)
+#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT_V(v)                           ((BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__##v << 2) & 0x4)
+#define BP_LCDIF_CTRL_DATA_FORMAT_24_BIT                                1
+#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT                                0x2
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID             0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE    0x1
+#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT(v)                             (((v) << 1) & 0x2)
+#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT_V(v)                           ((BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__##v << 1) & 0x2)
+#define BP_LCDIF_CTRL_RUN                                               0
+#define BM_LCDIF_CTRL_RUN                                               0x1
+#define BF_LCDIF_CTRL_RUN(v)                                            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_LCDIF_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL1                                      (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0))
+#define HW_LCDIF_CTRL1_SET                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4))
+#define HW_LCDIF_CTRL1_CLR                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8))
+#define HW_LCDIF_CTRL1_TOG                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc))
+#define BP_LCDIF_CTRL1_RSRVD1                               27
+#define BM_LCDIF_CTRL1_RSRVD1                               0xf8000000
+#define BF_LCDIF_CTRL1_RSRVD1(v)                            (((v) << 27) & 0xf8000000)
+#define BP_LCDIF_CTRL1_BM_ERROR_IRQ_EN                      26
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN                      0x4000000
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_EN(v)                   (((v) << 26) & 0x4000000)
+#define BP_LCDIF_CTRL1_BM_ERROR_IRQ                         25
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ                         0x2000000
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST             0x0
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST                0x1
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ(v)                      (((v) << 25) & 0x2000000)
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_V(v)                    ((BV_LCDIF_CTRL1_BM_ERROR_IRQ__##v << 25) & 0x2000000)
+#define BP_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                 24
+#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                 0x1000000
+#define BF_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(v)              (((v) << 24) & 0x1000000)
+#define BP_LCDIF_CTRL1_INTERLACE_FIELDS                     23
+#define BM_LCDIF_CTRL1_INTERLACE_FIELDS                     0x800000
+#define BF_LCDIF_CTRL1_INTERLACE_FIELDS(v)                  (((v) << 23) & 0x800000)
+#define BP_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD    22
+#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD    0x400000
+#define BF_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(v) (((v) << 22) & 0x400000)
+#define BP_LCDIF_CTRL1_FIFO_CLEAR                           21
+#define BM_LCDIF_CTRL1_FIFO_CLEAR                           0x200000
+#define BF_LCDIF_CTRL1_FIFO_CLEAR(v)                        (((v) << 21) & 0x200000)
+#define BP_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS              20
+#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS              0x100000
+#define BF_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(v)           (((v) << 20) & 0x100000)
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  16
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  0xf0000
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)               (((v) << 16) & 0xf0000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      15
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      0x8000
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)                   (((v) << 15) & 0x8000)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     14
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     0x4000
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)                  (((v) << 14) & 0x4000)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                13
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                0x2000
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)             (((v) << 13) & 0x2000)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    12
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    0x1000
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)                 (((v) << 12) & 0x1000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                         11
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                         0x800
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST             0x0
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST                0x1
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                      (((v) << 11) & 0x800)
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                    ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                        10
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                        0x400
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST               0x1
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                     (((v) << 10) & 0x400)
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)                   ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   9
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   0x200
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST       0x0
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST          0x1
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)                (((v) << 9) & 0x200)
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)              ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       8
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       0x100
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST           0x0
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST              0x1
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                    (((v) << 8) & 0x100)
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)                  ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100)
+#define BP_LCDIF_CTRL1_RSRVD0                               7
+#define BM_LCDIF_CTRL1_RSRVD0                               0x80
+#define BF_LCDIF_CTRL1_RSRVD0(v)                            (((v) << 7) & 0x80)
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER                       6
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER                       0x40
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER(v)                    (((v) << 6) & 0x40)
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                5
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                0x20
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN(v)             (((v) << 5) & 0x20)
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                   4
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                   0x10
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST       0x0
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST          0x1
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ(v)                (((v) << 4) & 0x10)
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_V(v)              ((BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__##v << 4) & 0x10)
+#define BP_LCDIF_CTRL1_LCD_CS_CTRL                          3
+#define BM_LCDIF_CTRL1_LCD_CS_CTRL                          0x8
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                       (((v) << 3) & 0x8)
+#define BP_LCDIF_CTRL1_BUSY_ENABLE                          2
+#define BM_LCDIF_CTRL1_BUSY_ENABLE                          0x4
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED           0x0
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED            0x1
+#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                       (((v) << 2) & 0x4)
+#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v)                     ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4)
+#define BP_LCDIF_CTRL1_MODE86                               1
+#define BM_LCDIF_CTRL1_MODE86                               0x2
+#define BV_LCDIF_CTRL1_MODE86__8080_MODE                    0x0
+#define BV_LCDIF_CTRL1_MODE86__6800_MODE                    0x1
+#define BF_LCDIF_CTRL1_MODE86(v)                            (((v) << 1) & 0x2)
+#define BF_LCDIF_CTRL1_MODE86_V(v)                          ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2)
+#define BP_LCDIF_CTRL1_RESET                                0
+#define BM_LCDIF_CTRL1_RESET                                0x1
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW                  0x0
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH                 0x1
+#define BF_LCDIF_CTRL1_RESET(v)                             (((v) << 0) & 0x1)
+#define BF_LCDIF_CTRL1_RESET_V(v)                           ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LCDIF_TRANSFER_COUNT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_LCDIF_TRANSFER_COUNT             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
+#define BP_LCDIF_TRANSFER_COUNT_V_COUNT     16
+#define BM_LCDIF_TRANSFER_COUNT_V_COUNT     0xffff0000
+#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v)  (((v) << 16) & 0xffff0000)
+#define BP_LCDIF_TRANSFER_COUNT_H_COUNT     0
+#define BM_LCDIF_TRANSFER_COUNT_H_COUNT     0xffff
+#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_CUR_BUF
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_LCDIF_CUR_BUF            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30))
+#define BP_LCDIF_CUR_BUF_ADDR       0
+#define BM_LCDIF_CUR_BUF_ADDR       0xffffffff
+#define BF_LCDIF_CUR_BUF_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_LCDIF_NEXT_BUF
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_LCDIF_NEXT_BUF           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40))
+#define BP_LCDIF_NEXT_BUF_ADDR      0
+#define BM_LCDIF_NEXT_BUF_ADDR      0xffffffff
+#define BF_LCDIF_NEXT_BUF_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_LCDIF_PAGETABLE
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_LCDIF_PAGETABLE              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50))
+#define BP_LCDIF_PAGETABLE_BASE         14
+#define BM_LCDIF_PAGETABLE_BASE         0xffffc000
+#define BF_LCDIF_PAGETABLE_BASE(v)      (((v) << 14) & 0xffffc000)
+#define BP_LCDIF_PAGETABLE_RSVD1        2
+#define BM_LCDIF_PAGETABLE_RSVD1        0x3ffc
+#define BF_LCDIF_PAGETABLE_RSVD1(v)     (((v) << 2) & 0x3ffc)
+#define BP_LCDIF_PAGETABLE_FLUSH        1
+#define BM_LCDIF_PAGETABLE_FLUSH        0x2
+#define BF_LCDIF_PAGETABLE_FLUSH(v)     (((v) << 1) & 0x2)
+#define BP_LCDIF_PAGETABLE_ENABLE       0
+#define BM_LCDIF_PAGETABLE_ENABLE       0x1
+#define BF_LCDIF_PAGETABLE_ENABLE(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_LCDIF_TIMING
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60))
+#define BP_LCDIF_TIMING_CMD_HOLD        24
+#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
+#define BP_LCDIF_TIMING_CMD_SETUP       16
+#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_LCDIF_TIMING_DATA_HOLD       8
+#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_LCDIF_TIMING_DATA_SETUP      0
+#define BM_LCDIF_TIMING_DATA_SETUP      0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL0
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_LCDIF_VDCTRL0                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x0))
+#define HW_LCDIF_VDCTRL0_SET                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x4))
+#define HW_LCDIF_VDCTRL0_CLR                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x8))
+#define HW_LCDIF_VDCTRL0_TOG                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0xc))
+#define BP_LCDIF_VDCTRL0_RSRVD2                     30
+#define BM_LCDIF_VDCTRL0_RSRVD2                     0xc0000000
+#define BF_LCDIF_VDCTRL0_RSRVD2(v)                  (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_OEB                  29
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB                  0x20000000
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT    0x0
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT     0x1
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)               (((v) << 29) & 0x20000000)
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v)             ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT             28
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT             0x10000000
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)          (((v) << 28) & 0x10000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_POL                  27
+#define BM_LCDIF_VDCTRL0_VSYNC_POL                  0x8000000
+#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)               (((v) << 27) & 0x8000000)
+#define BP_LCDIF_VDCTRL0_HSYNC_POL                  26
+#define BM_LCDIF_VDCTRL0_HSYNC_POL                  0x4000000
+#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)               (((v) << 26) & 0x4000000)
+#define BP_LCDIF_VDCTRL0_DOTCLK_POL                 25
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL                 0x2000000
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)              (((v) << 25) & 0x2000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_POL                 24
+#define BM_LCDIF_VDCTRL0_ENABLE_POL                 0x1000000
+#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)              (((v) << 24) & 0x1000000)
+#define BP_LCDIF_VDCTRL0_RSRVD1                     22
+#define BM_LCDIF_VDCTRL0_RSRVD1                     0xc00000
+#define BF_LCDIF_VDCTRL0_RSRVD1(v)                  (((v) << 22) & 0xc00000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          21
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          0x200000
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)       (((v) << 21) & 0x200000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     20
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     0x100000
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)  (((v) << 20) & 0x100000)
+#define BP_LCDIF_VDCTRL0_HALF_LINE                  19
+#define BM_LCDIF_VDCTRL0_HALF_LINE                  0x80000
+#define BF_LCDIF_VDCTRL0_HALF_LINE(v)               (((v) << 19) & 0x80000)
+#define BP_LCDIF_VDCTRL0_HALF_LINE_MODE             18
+#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE             0x40000
+#define BF_LCDIF_VDCTRL0_HALF_LINE_MODE(v)          (((v) << 18) & 0x40000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH          0
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH          0x3ffff
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v)       (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL1
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL1                    (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80))
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD       0
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD       0xffffffff
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL2
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL2                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90))
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      24
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      0xff000000
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_VDCTRL2_RSRVD0                 18
+#define BM_LCDIF_VDCTRL2_RSRVD0                 0xfc0000
+#define BF_LCDIF_VDCTRL2_RSRVD0(v)              (((v) << 18) & 0xfc0000)
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD           0
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD           0x3ffff
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)        (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL3
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL3                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0))
+#define BP_LCDIF_VDCTRL3_RSRVD0                 30
+#define BM_LCDIF_VDCTRL3_RSRVD0                 0xc0000000
+#define BF_LCDIF_VDCTRL3_RSRVD0(v)              (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS       29
+#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS       0x20000000
+#define BF_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(v)    (((v) << 29) & 0x20000000)
+#define BP_LCDIF_VDCTRL3_VSYNC_ONLY             28
+#define BM_LCDIF_VDCTRL3_VSYNC_ONLY             0x10000000
+#define BF_LCDIF_VDCTRL3_VSYNC_ONLY(v)          (((v) << 28) & 0x10000000)
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    16
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0xfff0000
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 16) & 0xfff0000)
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0xffff
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL4
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL4                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0))
+#define BP_LCDIF_VDCTRL4_RSRVD0                     19
+#define BM_LCDIF_VDCTRL4_RSRVD0                     0xfff80000
+#define BF_LCDIF_VDCTRL4_RSRVD0(v)                  (((v) << 19) & 0xfff80000)
+#define BP_LCDIF_VDCTRL4_SYNC_SIGNALS_ON            18
+#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON            0x40000
+#define BF_LCDIF_VDCTRL4_SYNC_SIGNALS_ON(v)         (((v) << 18) & 0x40000)
+#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT    0
+#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT    0x3ffff
+#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL0
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL0                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0))
+#define BP_LCDIF_DVICTRL0_START_TRS         31
+#define BM_LCDIF_DVICTRL0_START_TRS         0x80000000
+#define BF_LCDIF_DVICTRL0_START_TRS(v)      (((v) << 31) & 0x80000000)
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT      20
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT      0x7ff00000
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)   (((v) << 20) & 0x7ff00000)
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT    10
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT    0xffc00
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT       0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT       0x3ff
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL1
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL1                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0))
+#define BP_LCDIF_DVICTRL1_RSRVD0            30
+#define BM_LCDIF_DVICTRL1_RSRVD0            0xc0000000
+#define BF_LCDIF_DVICTRL1_RSRVD0(v)         (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_DVICTRL1_F1_START_LINE     20
+#define BM_LCDIF_DVICTRL1_F1_START_LINE     0x3ff00000
+#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)  (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL1_F1_END_LINE       10
+#define BM_LCDIF_DVICTRL1_F1_END_LINE       0xffc00
+#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL1_F2_START_LINE     0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE     0x3ff
+#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL2
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL2                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0))
+#define BP_LCDIF_DVICTRL2_RSRVD0                    30
+#define BM_LCDIF_DVICTRL2_RSRVD0                    0xc0000000
+#define BF_LCDIF_DVICTRL2_RSRVD0(v)                 (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
+#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
+#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL3
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL3                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xf0))
+#define BP_LCDIF_DVICTRL3_RSRVD1                    26
+#define BM_LCDIF_DVICTRL3_RSRVD1                    0xfc000000
+#define BF_LCDIF_DVICTRL3_RSRVD1(v)                 (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_DVICTRL3_RSRVD0                    10
+#define BM_LCDIF_DVICTRL3_RSRVD0                    0xfc00
+#define BF_LCDIF_DVICTRL3_RSRVD0(v)                 (((v) << 10) & 0xfc00)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL4
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL4                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x100))
+#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE      24
+#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE      0xff000000
+#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE     16
+#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE     0xff0000
+#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v)  (((v) << 16) & 0xff0000)
+#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE     8
+#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE     0xff00
+#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v)  (((v) << 8) & 0xff00)
+#define BP_LCDIF_DVICTRL4_H_FILL_CNT        0
+#define BM_LCDIF_DVICTRL4_H_FILL_CNT        0xff
+#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v)     (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_CSC_COEFF0
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF0                                         (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x110))
+#define BP_LCDIF_CSC_COEFF0_RSRVD1                                  26
+#define BM_LCDIF_CSC_COEFF0_RSRVD1                                  0xfc000000
+#define BF_LCDIF_CSC_COEFF0_RSRVD1(v)                               (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF0_C0                                      16
+#define BM_LCDIF_CSC_COEFF0_C0                                      0x3ff0000
+#define BF_LCDIF_CSC_COEFF0_C0(v)                                   (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF0_RSRVD0                                  2
+#define BM_LCDIF_CSC_COEFF0_RSRVD0                                  0xfffc
+#define BF_LCDIF_CSC_COEFF0_RSRVD0(v)                               (((v) << 2) & 0xfffc)
+#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0
+#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0x3
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD   0x0
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD             0x1
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL      0x2
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED           0x3
+#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v)                 (((v) << 0) & 0x3)
+#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_V(v)               ((BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__##v << 0) & 0x3)
+
+/**
+ * Register: HW_LCDIF_CSC_COEFF1
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF1             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x120))
+#define BP_LCDIF_CSC_COEFF1_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF1_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF1_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF1_C2          16
+#define BM_LCDIF_CSC_COEFF1_C2          0x3ff0000
+#define BF_LCDIF_CSC_COEFF1_C2(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF1_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF1_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF1_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF1_C1          0
+#define BM_LCDIF_CSC_COEFF1_C1          0x3ff
+#define BF_LCDIF_CSC_COEFF1_C1(v)       (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_CSC_COEFF2
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF2             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x130))
+#define BP_LCDIF_CSC_COEFF2_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF2_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF2_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF2_C4          16
+#define BM_LCDIF_CSC_COEFF2_C4          0x3ff0000
+#define BF_LCDIF_CSC_COEFF2_C4(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF2_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF2_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF2_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF2_C3          0
+#define BM_LCDIF_CSC_COEFF2_C3          0x3ff
+#define BF_LCDIF_CSC_COEFF2_C3(v)       (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_CSC_COEFF3
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF3             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x140))
+#define BP_LCDIF_CSC_COEFF3_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF3_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF3_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF3_C6          16
+#define BM_LCDIF_CSC_COEFF3_C6          0x3ff0000
+#define BF_LCDIF_CSC_COEFF3_C6(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF3_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF3_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF3_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF3_C5          0
+#define BM_LCDIF_CSC_COEFF3_C5          0x3ff
+#define BF_LCDIF_CSC_COEFF3_C5(v)       (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_CSC_COEFF4
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF4             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x150))
+#define BP_LCDIF_CSC_COEFF4_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF4_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF4_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF4_C8          16
+#define BM_LCDIF_CSC_COEFF4_C8          0x3ff0000
+#define BF_LCDIF_CSC_COEFF4_C8(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF4_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF4_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF4_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF4_C7          0
+#define BM_LCDIF_CSC_COEFF4_C7          0x3ff
+#define BF_LCDIF_CSC_COEFF4_C7(v)       (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_CSC_OFFSET
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_OFFSET                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x160))
+#define BP_LCDIF_CSC_OFFSET_RSRVD1          25
+#define BM_LCDIF_CSC_OFFSET_RSRVD1          0xfe000000
+#define BF_LCDIF_CSC_OFFSET_RSRVD1(v)       (((v) << 25) & 0xfe000000)
+#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET     16
+#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET     0x1ff0000
+#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v)  (((v) << 16) & 0x1ff0000)
+#define BP_LCDIF_CSC_OFFSET_RSRVD0          9
+#define BM_LCDIF_CSC_OFFSET_RSRVD0          0xfe00
+#define BF_LCDIF_CSC_OFFSET_RSRVD0(v)       (((v) << 9) & 0xfe00)
+#define BP_LCDIF_CSC_OFFSET_Y_OFFSET        0
+#define BM_LCDIF_CSC_OFFSET_Y_OFFSET        0x1ff
+#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v)     (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_LCDIF_CSC_LIMIT
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_LIMIT              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x170))
+#define BP_LCDIF_CSC_LIMIT_CBCR_MIN     24
+#define BM_LCDIF_CSC_LIMIT_CBCR_MIN     0xff000000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v)  (((v) << 24) & 0xff000000)
+#define BP_LCDIF_CSC_LIMIT_CBCR_MAX     16
+#define BM_LCDIF_CSC_LIMIT_CBCR_MAX     0xff0000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v)  (((v) << 16) & 0xff0000)
+#define BP_LCDIF_CSC_LIMIT_Y_MIN        8
+#define BM_LCDIF_CSC_LIMIT_Y_MIN        0xff00
+#define BF_LCDIF_CSC_LIMIT_Y_MIN(v)     (((v) << 8) & 0xff00)
+#define BP_LCDIF_CSC_LIMIT_Y_MAX        0
+#define BM_LCDIF_CSC_LIMIT_Y_MAX        0xff
+#define BF_LCDIF_CSC_LIMIT_Y_MAX(v)     (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_PIN_SHARING_CTRL0
+ * Address: 0x180
+ * SCT: yes
+*/
+#define HW_LCDIF_PIN_SHARING_CTRL0                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x0))
+#define HW_LCDIF_PIN_SHARING_CTRL0_SET                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x4))
+#define HW_LCDIF_PIN_SHARING_CTRL0_CLR                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x8))
+#define HW_LCDIF_PIN_SHARING_CTRL0_TOG                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0xc))
+#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       6
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       0xffffffc0
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v)                    (((v) << 6) & 0xffffffc0)
+#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 4
+#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 0x30
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE    0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD          0x1
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL      0x2
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL       0x3
+#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v)              (((v) << 4) & 0x30)
+#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE_V(v)            ((BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__##v << 4) & 0x30)
+#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       3
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       0x8
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD0(v)                    (((v) << 3) & 0x8)
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           2
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           0x4
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN(v)        (((v) << 2) & 0x4)
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              1
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              0x2
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST  0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST     0x1
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ(v)           (((v) << 1) & 0x2)
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_V(v)         ((BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__##v << 1) & 0x2)
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0x1
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_LCDIF_PIN_SHARING_CTRL1
+ * Address: 0x190
+ * SCT: no
+*/
+#define HW_LCDIF_PIN_SHARING_CTRL1                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x190))
+#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0
+#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0xffffffff
+#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_LCDIF_PIN_SHARING_CTRL2
+ * Address: 0x1a0
+ * SCT: no
+*/
+#define HW_LCDIF_PIN_SHARING_CTRL2                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1a0))
+#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0
+#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0xffffffff
+#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_LCDIF_DATA
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1b0))
+#define BP_LCDIF_DATA_DATA_THREE    24
+#define BM_LCDIF_DATA_DATA_THREE    0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
+#define BP_LCDIF_DATA_DATA_TWO      16
+#define BM_LCDIF_DATA_DATA_TWO      0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_DATA_DATA_ONE      8
+#define BM_LCDIF_DATA_DATA_ONE      0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
+#define BP_LCDIF_DATA_DATA_ZERO     0
+#define BM_LCDIF_DATA_DATA_ZERO     0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_BM_ERROR_STAT
+ * Address: 0x1c0
+ * SCT: no
+*/
+#define HW_LCDIF_BM_ERROR_STAT          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1c0))
+#define BP_LCDIF_BM_ERROR_STAT_ADDR     0
+#define BM_LCDIF_BM_ERROR_STAT_ADDR     0xffffffff
+#define BF_LCDIF_BM_ERROR_STAT_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_LCDIF_STAT
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_LCDIF_STAT                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1d0))
+#define BP_LCDIF_STAT_PRESENT               31
+#define BM_LCDIF_STAT_PRESENT               0x80000000
+#define BF_LCDIF_STAT_PRESENT(v)            (((v) << 31) & 0x80000000)
+#define BP_LCDIF_STAT_DMA_REQ               30
+#define BM_LCDIF_STAT_DMA_REQ               0x40000000
+#define BF_LCDIF_STAT_DMA_REQ(v)            (((v) << 30) & 0x40000000)
+#define BP_LCDIF_STAT_LFIFO_FULL            29
+#define BM_LCDIF_STAT_LFIFO_FULL            0x20000000
+#define BF_LCDIF_STAT_LFIFO_FULL(v)         (((v) << 29) & 0x20000000)
+#define BP_LCDIF_STAT_LFIFO_EMPTY           28
+#define BM_LCDIF_STAT_LFIFO_EMPTY           0x10000000
+#define BF_LCDIF_STAT_LFIFO_EMPTY(v)        (((v) << 28) & 0x10000000)
+#define BP_LCDIF_STAT_TXFIFO_FULL           27
+#define BM_LCDIF_STAT_TXFIFO_FULL           0x8000000
+#define BF_LCDIF_STAT_TXFIFO_FULL(v)        (((v) << 27) & 0x8000000)
+#define BP_LCDIF_STAT_TXFIFO_EMPTY          26
+#define BM_LCDIF_STAT_TXFIFO_EMPTY          0x4000000
+#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)       (((v) << 26) & 0x4000000)
+#define BP_LCDIF_STAT_BUSY                  25
+#define BM_LCDIF_STAT_BUSY                  0x2000000
+#define BF_LCDIF_STAT_BUSY(v)               (((v) << 25) & 0x2000000)
+#define BP_LCDIF_STAT_DVI_CURRENT_FIELD     24
+#define BM_LCDIF_STAT_DVI_CURRENT_FIELD     0x1000000
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)  (((v) << 24) & 0x1000000)
+#define BP_LCDIF_STAT_RSRVD0                0
+#define BM_LCDIF_STAT_RSRVD0                0xffffff
+#define BF_LCDIF_STAT_RSRVD0(v)             (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_LCDIF_VERSION
+ * Address: 0x1e0
+ * SCT: no
+*/
+#define HW_LCDIF_VERSION            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1e0))
+#define BP_LCDIF_VERSION_MAJOR      24
+#define BM_LCDIF_VERSION_MAJOR      0xff000000
+#define BF_LCDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_VERSION_MINOR      16
+#define BM_LCDIF_VERSION_MINOR      0xff0000
+#define BF_LCDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_VERSION_STEP       0
+#define BM_LCDIF_VERSION_STEP       0xffff
+#define BF_LCDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_DEBUG0
+ * Address: 0x1f0
+ * SCT: no
+*/
+#define HW_LCDIF_DEBUG0                             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1f0))
+#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED      31
+#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED      0x80000000
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)   (((v) << 31) & 0x80000000)
+#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     30
+#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     0x40000000
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)  (((v) << 30) & 0x40000000)
+#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         29
+#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         0x20000000
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)      (((v) << 29) & 0x20000000)
+#define BP_LCDIF_DEBUG0_DMACMDKICK                  28
+#define BM_LCDIF_DEBUG0_DMACMDKICK                  0x10000000
+#define BF_LCDIF_DEBUG0_DMACMDKICK(v)               (((v) << 28) & 0x10000000)
+#define BP_LCDIF_DEBUG0_ENABLE                      27
+#define BM_LCDIF_DEBUG0_ENABLE                      0x8000000
+#define BF_LCDIF_DEBUG0_ENABLE(v)                   (((v) << 27) & 0x8000000)
+#define BP_LCDIF_DEBUG0_HSYNC                       26
+#define BM_LCDIF_DEBUG0_HSYNC                       0x4000000
+#define BF_LCDIF_DEBUG0_HSYNC(v)                    (((v) << 26) & 0x4000000)
+#define BP_LCDIF_DEBUG0_VSYNC                       25
+#define BM_LCDIF_DEBUG0_VSYNC                       0x2000000
+#define BF_LCDIF_DEBUG0_VSYNC(v)                    (((v) << 25) & 0x2000000)
+#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                24
+#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                0x1000000
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)             (((v) << 24) & 0x1000000)
+#define BP_LCDIF_DEBUG0_EMPTY_WORD                  23
+#define BM_LCDIF_DEBUG0_EMPTY_WORD                  0x800000
+#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)               (((v) << 23) & 0x800000)
+#define BP_LCDIF_DEBUG0_CUR_STATE                   16
+#define BM_LCDIF_DEBUG0_CUR_STATE                   0x7f0000
+#define BF_LCDIF_DEBUG0_CUR_STATE(v)                (((v) << 16) & 0x7f0000)
+#define BP_LCDIF_DEBUG0_PXP_LCDIF_B0_READY          15
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY          0x8000
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B0_READY(v)       (((v) << 15) & 0x8000)
+#define BP_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE           14
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE           0x4000
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE(v)        (((v) << 14) & 0x4000)
+#define BP_LCDIF_DEBUG0_PXP_LCDIF_B1_READY          13
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY          0x2000
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B1_READY(v)       (((v) << 13) & 0x2000)
+#define BP_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE           12
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE           0x1000
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE(v)        (((v) << 12) & 0x1000)
+#define BP_LCDIF_DEBUG0_GPMI_LCDIF_REQ              11
+#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ              0x800
+#define BF_LCDIF_DEBUG0_GPMI_LCDIF_REQ(v)           (((v) << 11) & 0x800)
+#define BP_LCDIF_DEBUG0_LCDIF_GPMI_GRANT            10
+#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT            0x400
+#define BF_LCDIF_DEBUG0_LCDIF_GPMI_GRANT(v)         (((v) << 10) & 0x400)
+#define BP_LCDIF_DEBUG0_RSRVD0                      0
+#define BM_LCDIF_DEBUG0_RSRVD0                      0x3ff
+#define BF_LCDIF_DEBUG0_RSRVD0(v)                   (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DEBUG1
+ * Address: 0x200
+ * SCT: no
+*/
+#define HW_LCDIF_DEBUG1                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x200))
+#define BP_LCDIF_DEBUG1_H_DATA_COUNT    16
+#define BM_LCDIF_DEBUG1_H_DATA_COUNT    0xffff0000
+#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) (((v) << 16) & 0xffff0000)
+#define BP_LCDIF_DEBUG1_V_DATA_COUNT    0
+#define BM_LCDIF_DEBUG1_V_DATA_COUNT    0xffff
+#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-lradc.h b/firmware/target/arm/imx233/regs/imx233/regs-lradc.h
new file mode 100644
index 0000000000..0948e0fe75
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-lradc.h
@@ -0,0 +1,783 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__LRADC__H__
+#define __HEADERGEN__IMX233__LRADC__H__
+
+#define REGS_LRADC_BASE (0x80050000)
+
+#define REGS_LRADC_VERSION "3.2.0"
+
+/**
+ * Register: HW_LRADC_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL0                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0))
+#define HW_LRADC_CTRL0_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4))
+#define HW_LRADC_CTRL0_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8))
+#define HW_LRADC_CTRL0_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc))
+#define BP_LRADC_CTRL0_SFTRST                   31
+#define BM_LRADC_CTRL0_SFTRST                   0x80000000
+#define BF_LRADC_CTRL0_SFTRST(v)                (((v) << 31) & 0x80000000)
+#define BP_LRADC_CTRL0_CLKGATE                  30
+#define BM_LRADC_CTRL0_CLKGATE                  0x40000000
+#define BF_LRADC_CTRL0_CLKGATE(v)               (((v) << 30) & 0x40000000)
+#define BP_LRADC_CTRL0_RSRVD2                   22
+#define BM_LRADC_CTRL0_RSRVD2                   0x3fc00000
+#define BF_LRADC_CTRL0_RSRVD2(v)                (((v) << 22) & 0x3fc00000)
+#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF         21
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF         0x200000
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF    0x0
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON     0x1
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)      (((v) << 21) & 0x200000)
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)    ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000)
+#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE      20
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x100000
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON  0x1
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)   (((v) << 20) & 0x100000)
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000)
+#define BP_LRADC_CTRL0_YMINUS_ENABLE            19
+#define BM_LRADC_CTRL0_YMINUS_ENABLE            0x80000
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF       0x0
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON        0x1
+#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)         (((v) << 19) & 0x80000)
+#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000)
+#define BP_LRADC_CTRL0_XMINUS_ENABLE            18
+#define BM_LRADC_CTRL0_XMINUS_ENABLE            0x40000
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF       0x0
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON        0x1
+#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)         (((v) << 18) & 0x40000)
+#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000)
+#define BP_LRADC_CTRL0_YPLUS_ENABLE             17
+#define BM_LRADC_CTRL0_YPLUS_ENABLE             0x20000
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF        0x0
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON         0x1
+#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)          (((v) << 17) & 0x20000)
+#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000)
+#define BP_LRADC_CTRL0_XPLUS_ENABLE             16
+#define BM_LRADC_CTRL0_XPLUS_ENABLE             0x10000
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF        0x0
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON         0x1
+#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)          (((v) << 16) & 0x10000)
+#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000)
+#define BP_LRADC_CTRL0_RSRVD1                   8
+#define BM_LRADC_CTRL0_RSRVD1                   0xff00
+#define BF_LRADC_CTRL0_RSRVD1(v)                (((v) << 8) & 0xff00)
+#define BP_LRADC_CTRL0_SCHEDULE                 0
+#define BM_LRADC_CTRL0_SCHEDULE                 0xff
+#define BF_LRADC_CTRL0_SCHEDULE(v)              (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LRADC_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL1                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0))
+#define HW_LRADC_CTRL1_SET                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4))
+#define HW_LRADC_CTRL1_CLR                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8))
+#define HW_LRADC_CTRL1_TOG                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc))
+#define BP_LRADC_CTRL1_RSRVD2                       25
+#define BM_LRADC_CTRL1_RSRVD2                       0xfe000000
+#define BF_LRADC_CTRL1_RSRVD2(v)                    (((v) << 25) & 0xfe000000)
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) << 24) & 0x1000000)
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)     ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000)
+#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
+#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
+#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) << 22) & 0x400000)
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000)
+#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) << 21) & 0x200000)
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000)
+#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
+#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) << 20) & 0x100000)
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000)
+#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
+#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) << 19) & 0x80000)
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000)
+#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
+#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) << 18) & 0x40000)
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000)
+#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
+#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) << 17) & 0x20000)
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000)
+#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) << 16) & 0x10000)
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000)
+#define BP_LRADC_CTRL1_RSRVD1                       9
+#define BM_LRADC_CTRL1_RSRVD1                       0xfe00
+#define BF_LRADC_CTRL1_RSRVD1(v)                    (((v) << 9) & 0xfe00)
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) << 8) & 0x100)
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)        ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100)
+#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
+#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
+#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) << 7) & 0x80)
+#define BF_LRADC_CTRL1_LRADC7_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80)
+#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
+#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
+#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) << 6) & 0x40)
+#define BF_LRADC_CTRL1_LRADC6_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40)
+#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
+#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
+#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) << 5) & 0x20)
+#define BF_LRADC_CTRL1_LRADC5_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20)
+#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
+#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
+#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) << 4) & 0x10)
+#define BF_LRADC_CTRL1_LRADC4_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10)
+#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
+#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
+#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) << 3) & 0x8)
+#define BF_LRADC_CTRL1_LRADC3_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8)
+#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
+#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
+#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) << 2) & 0x4)
+#define BF_LRADC_CTRL1_LRADC2_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4)
+#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
+#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
+#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) << 1) & 0x2)
+#define BF_LRADC_CTRL1_LRADC1_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2)
+#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
+#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
+#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) << 0) & 0x1)
+#define BF_LRADC_CTRL1_LRADC0_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL2                                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0))
+#define HW_LRADC_CTRL2_SET                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4))
+#define HW_LRADC_CTRL2_CLR                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8))
+#define HW_LRADC_CTRL2_TOG                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc))
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) << 24) & 0xff000000)
+#define BP_LRADC_CTRL2_BL_AMP_BYPASS                    23
+#define BM_LRADC_CTRL2_BL_AMP_BYPASS                    0x800000
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE           0x0
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE            0x1
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS(v)                 (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v)               ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL2_BL_ENABLE                        22
+#define BM_LRADC_CTRL2_BL_ENABLE                        0x400000
+#define BF_LRADC_CTRL2_BL_ENABLE(v)                     (((v) << 22) & 0x400000)
+#define BP_LRADC_CTRL2_BL_MUX_SELECT                    21
+#define BM_LRADC_CTRL2_BL_MUX_SELECT                    0x200000
+#define BF_LRADC_CTRL2_BL_MUX_SELECT(v)                 (((v) << 21) & 0x200000)
+#define BP_LRADC_CTRL2_BL_BRIGHTNESS                    16
+#define BM_LRADC_CTRL2_BL_BRIGHTNESS                    0x1f0000
+#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v)                 (((v) << 16) & 0x1f0000)
+#define BP_LRADC_CTRL2_TEMPSENSE_PWD                    15
+#define BM_LRADC_CTRL2_TEMPSENSE_PWD                    0x8000
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE            0x0
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE           0x1
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD(v)                 (((v) << 15) & 0x8000)
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v)               ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000)
+#define BP_LRADC_CTRL2_RSRVD1                           14
+#define BM_LRADC_CTRL2_RSRVD1                           0x4000
+#define BF_LRADC_CTRL2_RSRVD1(v)                        (((v) << 14) & 0x4000)
+#define BP_LRADC_CTRL2_EXT_EN1                          13
+#define BM_LRADC_CTRL2_EXT_EN1                          0x2000
+#define BV_LRADC_CTRL2_EXT_EN1__DISABLE                 0x0
+#define BV_LRADC_CTRL2_EXT_EN1__ENABLE                  0x1
+#define BF_LRADC_CTRL2_EXT_EN1(v)                       (((v) << 13) & 0x2000)
+#define BF_LRADC_CTRL2_EXT_EN1_V(v)                     ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000)
+#define BP_LRADC_CTRL2_EXT_EN0                          12
+#define BM_LRADC_CTRL2_EXT_EN0                          0x1000
+#define BF_LRADC_CTRL2_EXT_EN0(v)                       (((v) << 12) & 0x1000)
+#define BP_LRADC_CTRL2_RSRVD2                           10
+#define BM_LRADC_CTRL2_RSRVD2                           0xc00
+#define BF_LRADC_CTRL2_RSRVD2(v)                        (((v) << 10) & 0xc00)
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) << 9) & 0x200)
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200)
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) << 8) & 0x100)
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100)
+#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
+#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
+#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) << 4) & 0xf0)
+#define BF_LRADC_CTRL2_TEMP_ISRC1_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0)
+#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
+#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) << 0) & 0xf)
+#define BF_LRADC_CTRL2_TEMP_ISRC0_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf)
+
+/**
+ * Register: HW_LRADC_CTRL3
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL3                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0))
+#define HW_LRADC_CTRL3_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4))
+#define HW_LRADC_CTRL3_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8))
+#define HW_LRADC_CTRL3_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc))
+#define BP_LRADC_CTRL3_RSRVD5                   26
+#define BM_LRADC_CTRL3_RSRVD5                   0xfc000000
+#define BF_LRADC_CTRL3_RSRVD5(v)                (((v) << 26) & 0xfc000000)
+#define BP_LRADC_CTRL3_DISCARD                  24
+#define BM_LRADC_CTRL3_DISCARD                  0x3000000
+#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
+#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
+#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
+#define BF_LRADC_CTRL3_DISCARD(v)               (((v) << 24) & 0x3000000)
+#define BF_LRADC_CTRL3_DISCARD_V(v)             ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000)
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) << 22) & 0x400000)
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000)
+#define BP_LRADC_CTRL3_RSRVD4                   14
+#define BM_LRADC_CTRL3_RSRVD4                   0x3fc000
+#define BF_LRADC_CTRL3_RSRVD4(v)                (((v) << 14) & 0x3fc000)
+#define BP_LRADC_CTRL3_RSRVD3                   10
+#define BM_LRADC_CTRL3_RSRVD3                   0x3c00
+#define BF_LRADC_CTRL3_RSRVD3(v)                (((v) << 10) & 0x3c00)
+#define BP_LRADC_CTRL3_CYCLE_TIME               8
+#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
+#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
+#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
+#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
+#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
+#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) << 8) & 0x300)
+#define BF_LRADC_CTRL3_CYCLE_TIME_V(v)          ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300)
+#define BP_LRADC_CTRL3_RSRVD2                   6
+#define BM_LRADC_CTRL3_RSRVD2                   0xc0
+#define BF_LRADC_CTRL3_RSRVD2(v)                (((v) << 6) & 0xc0)
+#define BP_LRADC_CTRL3_HIGH_TIME                4
+#define BM_LRADC_CTRL3_HIGH_TIME                0x30
+#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
+#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
+#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
+#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
+#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) << 4) & 0x30)
+#define BF_LRADC_CTRL3_HIGH_TIME_V(v)           ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30)
+#define BP_LRADC_CTRL3_RSRVD1                   2
+#define BM_LRADC_CTRL3_RSRVD1                   0xc
+#define BF_LRADC_CTRL3_RSRVD1(v)                (((v) << 2) & 0xc)
+#define BP_LRADC_CTRL3_DELAY_CLOCK              1
+#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
+#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
+#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
+#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) << 1) & 0x2)
+#define BF_LRADC_CTRL3_DELAY_CLOCK_V(v)         ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2)
+#define BP_LRADC_CTRL3_INVERT_CLOCK             0
+#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
+#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
+#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
+#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) << 0) & 0x1)
+#define BF_LRADC_CTRL3_INVERT_CLOCK_V(v)        ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_STATUS
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_LRADC_STATUS                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x0))
+#define HW_LRADC_STATUS_SET                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x4))
+#define HW_LRADC_STATUS_CLR                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0x8))
+#define HW_LRADC_STATUS_TOG                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40 + 0xc))
+#define BP_LRADC_STATUS_RSRVD3                  27
+#define BM_LRADC_STATUS_RSRVD3                  0xf8000000
+#define BF_LRADC_STATUS_RSRVD3(v)               (((v) << 27) & 0xf8000000)
+#define BP_LRADC_STATUS_TEMP1_PRESENT           26
+#define BM_LRADC_STATUS_TEMP1_PRESENT           0x4000000
+#define BF_LRADC_STATUS_TEMP1_PRESENT(v)        (((v) << 26) & 0x4000000)
+#define BP_LRADC_STATUS_TEMP0_PRESENT           25
+#define BM_LRADC_STATUS_TEMP0_PRESENT           0x2000000
+#define BF_LRADC_STATUS_TEMP0_PRESENT(v)        (((v) << 25) & 0x2000000)
+#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT     24
+#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT     0x1000000
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)  (((v) << 24) & 0x1000000)
+#define BP_LRADC_STATUS_CHANNEL7_PRESENT        23
+#define BM_LRADC_STATUS_CHANNEL7_PRESENT        0x800000
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)     (((v) << 23) & 0x800000)
+#define BP_LRADC_STATUS_CHANNEL6_PRESENT        22
+#define BM_LRADC_STATUS_CHANNEL6_PRESENT        0x400000
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)     (((v) << 22) & 0x400000)
+#define BP_LRADC_STATUS_CHANNEL5_PRESENT        21
+#define BM_LRADC_STATUS_CHANNEL5_PRESENT        0x200000
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)     (((v) << 21) & 0x200000)
+#define BP_LRADC_STATUS_CHANNEL4_PRESENT        20
+#define BM_LRADC_STATUS_CHANNEL4_PRESENT        0x100000
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)     (((v) << 20) & 0x100000)
+#define BP_LRADC_STATUS_CHANNEL3_PRESENT        19
+#define BM_LRADC_STATUS_CHANNEL3_PRESENT        0x80000
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)     (((v) << 19) & 0x80000)
+#define BP_LRADC_STATUS_CHANNEL2_PRESENT        18
+#define BM_LRADC_STATUS_CHANNEL2_PRESENT        0x40000
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)     (((v) << 18) & 0x40000)
+#define BP_LRADC_STATUS_CHANNEL1_PRESENT        17
+#define BM_LRADC_STATUS_CHANNEL1_PRESENT        0x20000
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)     (((v) << 17) & 0x20000)
+#define BP_LRADC_STATUS_CHANNEL0_PRESENT        16
+#define BM_LRADC_STATUS_CHANNEL0_PRESENT        0x10000
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)     (((v) << 16) & 0x10000)
+#define BP_LRADC_STATUS_RSRVD2                  1
+#define BM_LRADC_STATUS_RSRVD2                  0xfffe
+#define BF_LRADC_STATUS_RSRVD2(v)               (((v) << 1) & 0xfffe)
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x1
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN  0x0
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT   0x1
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)     (((v) << 0) & 0x1)
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)   ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CHn
+ * Address: 0x50+n*0x10
+ * SCT: yes
+*/
+#define HW_LRADC_CHn(n)             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0))
+#define HW_LRADC_CHn_SET(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4))
+#define HW_LRADC_CHn_CLR(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8))
+#define HW_LRADC_CHn_TOG(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc))
+#define BP_LRADC_CHn_TOGGLE         31
+#define BM_LRADC_CHn_TOGGLE         0x80000000
+#define BF_LRADC_CHn_TOGGLE(v)      (((v) << 31) & 0x80000000)
+#define BP_LRADC_CHn_RSRVD2         30
+#define BM_LRADC_CHn_RSRVD2         0x40000000
+#define BF_LRADC_CHn_RSRVD2(v)      (((v) << 30) & 0x40000000)
+#define BP_LRADC_CHn_ACCUMULATE     29
+#define BM_LRADC_CHn_ACCUMULATE     0x20000000
+#define BF_LRADC_CHn_ACCUMULATE(v)  (((v) << 29) & 0x20000000)
+#define BP_LRADC_CHn_NUM_SAMPLES    24
+#define BM_LRADC_CHn_NUM_SAMPLES    0x1f000000
+#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000)
+#define BP_LRADC_CHn_RSRVD1         18
+#define BM_LRADC_CHn_RSRVD1         0xfc0000
+#define BF_LRADC_CHn_RSRVD1(v)      (((v) << 18) & 0xfc0000)
+#define BP_LRADC_CHn_VALUE          0
+#define BM_LRADC_CHn_VALUE          0x3ffff
+#define BF_LRADC_CHn_VALUE(v)       (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_LRADC_DELAYn
+ * Address: 0xd0+n*0x10
+ * SCT: yes
+*/
+#define HW_LRADC_DELAYn(n)                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0))
+#define HW_LRADC_DELAYn_SET(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4))
+#define HW_LRADC_DELAYn_CLR(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8))
+#define HW_LRADC_DELAYn_TOG(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc))
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS      24
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS      0xff000000
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)   (((v) << 24) & 0xff000000)
+#define BP_LRADC_DELAYn_RSRVD2              21
+#define BM_LRADC_DELAYn_RSRVD2              0xe00000
+#define BF_LRADC_DELAYn_RSRVD2(v)           (((v) << 21) & 0xe00000)
+#define BP_LRADC_DELAYn_KICK                20
+#define BM_LRADC_DELAYn_KICK                0x100000
+#define BF_LRADC_DELAYn_KICK(v)             (((v) << 20) & 0x100000)
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS      16
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS      0xf0000
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)   (((v) << 16) & 0xf0000)
+#define BP_LRADC_DELAYn_LOOP_COUNT          11
+#define BM_LRADC_DELAYn_LOOP_COUNT          0xf800
+#define BF_LRADC_DELAYn_LOOP_COUNT(v)       (((v) << 11) & 0xf800)
+#define BP_LRADC_DELAYn_DELAY               0
+#define BM_LRADC_DELAYn_DELAY               0x7ff
+#define BF_LRADC_DELAYn_DELAY(v)            (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_LRADC_DEBUG0
+ * Address: 0x110
+ * SCT: yes
+*/
+#define HW_LRADC_DEBUG0             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x0))
+#define HW_LRADC_DEBUG0_SET         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x4))
+#define HW_LRADC_DEBUG0_CLR         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0x8))
+#define HW_LRADC_DEBUG0_TOG         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110 + 0xc))
+#define BP_LRADC_DEBUG0_READONLY    16
+#define BM_LRADC_DEBUG0_READONLY    0xffff0000
+#define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000)
+#define BP_LRADC_DEBUG0_RSRVD1      12
+#define BM_LRADC_DEBUG0_RSRVD1      0xf000
+#define BF_LRADC_DEBUG0_RSRVD1(v)   (((v) << 12) & 0xf000)
+#define BP_LRADC_DEBUG0_STATE       0
+#define BM_LRADC_DEBUG0_STATE       0xfff
+#define BF_LRADC_DEBUG0_STATE(v)    (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_LRADC_DEBUG1
+ * Address: 0x120
+ * SCT: yes
+*/
+#define HW_LRADC_DEBUG1                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0))
+#define HW_LRADC_DEBUG1_SET                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4))
+#define HW_LRADC_DEBUG1_CLR                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8))
+#define HW_LRADC_DEBUG1_TOG                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc))
+#define BP_LRADC_DEBUG1_RSRVD3              24
+#define BM_LRADC_DEBUG1_RSRVD3              0xff000000
+#define BF_LRADC_DEBUG1_RSRVD3(v)           (((v) << 24) & 0xff000000)
+#define BP_LRADC_DEBUG1_REQUEST             16
+#define BM_LRADC_DEBUG1_REQUEST             0xff0000
+#define BF_LRADC_DEBUG1_REQUEST(v)          (((v) << 16) & 0xff0000)
+#define BP_LRADC_DEBUG1_RSRVD2              13
+#define BM_LRADC_DEBUG1_RSRVD2              0xe000
+#define BF_LRADC_DEBUG1_RSRVD2(v)           (((v) << 13) & 0xe000)
+#define BP_LRADC_DEBUG1_TESTMODE_COUNT      8
+#define BM_LRADC_DEBUG1_TESTMODE_COUNT      0x1f00
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)   (((v) << 8) & 0x1f00)
+#define BP_LRADC_DEBUG1_RSRVD1              3
+#define BM_LRADC_DEBUG1_RSRVD1              0xf8
+#define BF_LRADC_DEBUG1_RSRVD1(v)           (((v) << 3) & 0xf8)
+#define BP_LRADC_DEBUG1_TESTMODE6           2
+#define BM_LRADC_DEBUG1_TESTMODE6           0x4
+#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL   0x0
+#define BV_LRADC_DEBUG1_TESTMODE6__TEST     0x1
+#define BF_LRADC_DEBUG1_TESTMODE6(v)        (((v) << 2) & 0x4)
+#define BF_LRADC_DEBUG1_TESTMODE6_V(v)      ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4)
+#define BP_LRADC_DEBUG1_TESTMODE5           1
+#define BM_LRADC_DEBUG1_TESTMODE5           0x2
+#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL   0x0
+#define BV_LRADC_DEBUG1_TESTMODE5__TEST     0x1
+#define BF_LRADC_DEBUG1_TESTMODE5(v)        (((v) << 1) & 0x2)
+#define BF_LRADC_DEBUG1_TESTMODE5_V(v)      ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2)
+#define BP_LRADC_DEBUG1_TESTMODE            0
+#define BM_LRADC_DEBUG1_TESTMODE            0x1
+#define BV_LRADC_DEBUG1_TESTMODE__NORMAL    0x0
+#define BV_LRADC_DEBUG1_TESTMODE__TEST      0x1
+#define BF_LRADC_DEBUG1_TESTMODE(v)         (((v) << 0) & 0x1)
+#define BF_LRADC_DEBUG1_TESTMODE_V(v)       ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CONVERSION
+ * Address: 0x130
+ * SCT: yes
+*/
+#define HW_LRADC_CONVERSION                             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0))
+#define HW_LRADC_CONVERSION_SET                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4))
+#define HW_LRADC_CONVERSION_CLR                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8))
+#define HW_LRADC_CONVERSION_TOG                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc))
+#define BP_LRADC_CONVERSION_RSRVD3                      21
+#define BM_LRADC_CONVERSION_RSRVD3                      0xffe00000
+#define BF_LRADC_CONVERSION_RSRVD3(v)                   (((v) << 21) & 0xffe00000)
+#define BP_LRADC_CONVERSION_AUTOMATIC                   20
+#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
+#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
+#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
+#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) << 20) & 0x100000)
+#define BF_LRADC_CONVERSION_AUTOMATIC_V(v)              ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000)
+#define BP_LRADC_CONVERSION_RSRVD2                      18
+#define BM_LRADC_CONVERSION_RSRVD2                      0xc0000
+#define BF_LRADC_CONVERSION_RSRVD2(v)                   (((v) << 18) & 0xc0000)
+#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
+#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
+#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) << 16) & 0x30000)
+#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v)           ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000)
+#define BP_LRADC_CONVERSION_RSRVD1                      10
+#define BM_LRADC_CONVERSION_RSRVD1                      0xfc00
+#define BF_LRADC_CONVERSION_RSRVD1(v)                   (((v) << 10) & 0xfc00)
+#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
+#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LRADC_CTRL4
+ * Address: 0x140
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL4                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0))
+#define HW_LRADC_CTRL4_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4))
+#define HW_LRADC_CTRL4_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8))
+#define HW_LRADC_CTRL4_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc))
+#define BP_LRADC_CTRL4_LRADC7SELECT             28
+#define BM_LRADC_CTRL4_LRADC7SELECT             0xf0000000
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC7SELECT(v)          (((v) << 28) & 0xf0000000)
+#define BF_LRADC_CTRL4_LRADC7SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000)
+#define BP_LRADC_CTRL4_LRADC6SELECT             24
+#define BM_LRADC_CTRL4_LRADC6SELECT             0xf000000
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC6SELECT(v)          (((v) << 24) & 0xf000000)
+#define BF_LRADC_CTRL4_LRADC6SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000)
+#define BP_LRADC_CTRL4_LRADC5SELECT             20
+#define BM_LRADC_CTRL4_LRADC5SELECT             0xf00000
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC5SELECT(v)          (((v) << 20) & 0xf00000)
+#define BF_LRADC_CTRL4_LRADC5SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000)
+#define BP_LRADC_CTRL4_LRADC4SELECT             16
+#define BM_LRADC_CTRL4_LRADC4SELECT             0xf0000
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC4SELECT(v)          (((v) << 16) & 0xf0000)
+#define BF_LRADC_CTRL4_LRADC4SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000)
+#define BP_LRADC_CTRL4_LRADC3SELECT             12
+#define BM_LRADC_CTRL4_LRADC3SELECT             0xf000
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC3SELECT(v)          (((v) << 12) & 0xf000)
+#define BF_LRADC_CTRL4_LRADC3SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000)
+#define BP_LRADC_CTRL4_LRADC2SELECT             8
+#define BM_LRADC_CTRL4_LRADC2SELECT             0xf00
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC2SELECT(v)          (((v) << 8) & 0xf00)
+#define BF_LRADC_CTRL4_LRADC2SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00)
+#define BP_LRADC_CTRL4_LRADC1SELECT             4
+#define BM_LRADC_CTRL4_LRADC1SELECT             0xf0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC1SELECT(v)          (((v) << 4) & 0xf0)
+#define BF_LRADC_CTRL4_LRADC1SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0)
+#define BP_LRADC_CTRL4_LRADC0SELECT             0
+#define BM_LRADC_CTRL4_LRADC0SELECT             0xf
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC0SELECT(v)          (((v) << 0) & 0xf)
+#define BF_LRADC_CTRL4_LRADC0SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_LRADC_VERSION
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_LRADC_VERSION            (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150))
+#define BP_LRADC_VERSION_MAJOR      24
+#define BM_LRADC_VERSION_MAJOR      0xff000000
+#define BF_LRADC_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_LRADC_VERSION_MINOR      16
+#define BM_LRADC_VERSION_MINOR      0xff0000
+#define BF_LRADC_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_LRADC_VERSION_STEP       0
+#define BM_LRADC_VERSION_STEP       0xffff
+#define BF_LRADC_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h b/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h
new file mode 100644
index 0000000000..a9066895fc
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-ocotp.h
@@ -0,0 +1,287 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__OCOTP__H__
+#define __HEADERGEN__IMX233__OCOTP__H__
+
+#define REGS_OCOTP_BASE (0x8002c000)
+
+#define REGS_OCOTP_VERSION "3.2.0"
+
+/**
+ * Register: HW_OCOTP_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_OCOTP_CTRL                   (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x0))
+#define HW_OCOTP_CTRL_SET               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x4))
+#define HW_OCOTP_CTRL_CLR               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x8))
+#define HW_OCOTP_CTRL_TOG               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0xc))
+#define BP_OCOTP_CTRL_WR_UNLOCK         16
+#define BM_OCOTP_CTRL_WR_UNLOCK         0xffff0000
+#define BV_OCOTP_CTRL_WR_UNLOCK__KEY    0x3e77
+#define BF_OCOTP_CTRL_WR_UNLOCK(v)      (((v) << 16) & 0xffff0000)
+#define BF_OCOTP_CTRL_WR_UNLOCK_V(v)    ((BV_OCOTP_CTRL_WR_UNLOCK__##v << 16) & 0xffff0000)
+#define BP_OCOTP_CTRL_RSRVD2            14
+#define BM_OCOTP_CTRL_RSRVD2            0xc000
+#define BF_OCOTP_CTRL_RSRVD2(v)         (((v) << 14) & 0xc000)
+#define BP_OCOTP_CTRL_RELOAD_SHADOWS    13
+#define BM_OCOTP_CTRL_RELOAD_SHADOWS    0x2000
+#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) (((v) << 13) & 0x2000)
+#define BP_OCOTP_CTRL_RD_BANK_OPEN      12
+#define BM_OCOTP_CTRL_RD_BANK_OPEN      0x1000
+#define BF_OCOTP_CTRL_RD_BANK_OPEN(v)   (((v) << 12) & 0x1000)
+#define BP_OCOTP_CTRL_RSRVD1            10
+#define BM_OCOTP_CTRL_RSRVD1            0xc00
+#define BF_OCOTP_CTRL_RSRVD1(v)         (((v) << 10) & 0xc00)
+#define BP_OCOTP_CTRL_ERROR             9
+#define BM_OCOTP_CTRL_ERROR             0x200
+#define BF_OCOTP_CTRL_ERROR(v)          (((v) << 9) & 0x200)
+#define BP_OCOTP_CTRL_BUSY              8
+#define BM_OCOTP_CTRL_BUSY              0x100
+#define BF_OCOTP_CTRL_BUSY(v)           (((v) << 8) & 0x100)
+#define BP_OCOTP_CTRL_RSRVD0            5
+#define BM_OCOTP_CTRL_RSRVD0            0xe0
+#define BF_OCOTP_CTRL_RSRVD0(v)         (((v) << 5) & 0xe0)
+#define BP_OCOTP_CTRL_ADDR              0
+#define BM_OCOTP_CTRL_ADDR              0x1f
+#define BF_OCOTP_CTRL_ADDR(v)           (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_OCOTP_DATA
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_OCOTP_DATA           (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x10))
+#define BP_OCOTP_DATA_DATA      0
+#define BM_OCOTP_DATA_DATA      0xffffffff
+#define BF_OCOTP_DATA_DATA(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_CUSTn
+ * Address: 0x20+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_CUSTn(n)       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x20+(n)*0x10))
+#define BP_OCOTP_CUSTn_BITS     0
+#define BM_OCOTP_CUSTn_BITS     0xffffffff
+#define BF_OCOTP_CUSTn_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_CRYPTOn
+ * Address: 0x60+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_CRYPTOn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x60+(n)*0x10))
+#define BP_OCOTP_CRYPTOn_BITS       0
+#define BM_OCOTP_CRYPTOn_BITS       0xffffffff
+#define BF_OCOTP_CRYPTOn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_HWCAPn
+ * Address: 0xa0+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_HWCAPn(n)      (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0xa0+(n)*0x10))
+#define BP_OCOTP_HWCAPn_BITS    0
+#define BM_OCOTP_HWCAPn_BITS    0xffffffff
+#define BF_OCOTP_HWCAPn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_SWCAP
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_OCOTP_SWCAP          (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x100))
+#define BP_OCOTP_SWCAP_BITS     0
+#define BM_OCOTP_SWCAP_BITS     0xffffffff
+#define BF_OCOTP_SWCAP_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_CUSTCAP
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_OCOTP_CUSTCAP                            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x110))
+#define BP_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9       31
+#define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9       0x80000000
+#define BF_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9(v)    (((v) << 31) & 0x80000000)
+#define BP_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10    30
+#define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10    0x40000000
+#define BF_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10(v) (((v) << 30) & 0x40000000)
+#define BP_OCOTP_CUSTCAP_RSRVD1                     5
+#define BM_OCOTP_CUSTCAP_RSRVD1                     0x3fffffe0
+#define BF_OCOTP_CUSTCAP_RSRVD1(v)                  (((v) << 5) & 0x3fffffe0)
+#define BP_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE    4
+#define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE    0x10
+#define BF_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE(v) (((v) << 4) & 0x10)
+#define BP_OCOTP_CUSTCAP_USE_PARALLEL_JTAG          3
+#define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG          0x8
+#define BF_OCOTP_CUSTCAP_USE_PARALLEL_JTAG(v)       (((v) << 3) & 0x8)
+#define BP_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT     2
+#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT     0x4
+#define BF_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT(v)  (((v) << 2) & 0x4)
+#define BP_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT     1
+#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT     0x2
+#define BF_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT(v)  (((v) << 1) & 0x2)
+#define BP_OCOTP_CUSTCAP_RSRVD0                     0
+#define BM_OCOTP_CUSTCAP_RSRVD0                     0x1
+#define BF_OCOTP_CUSTCAP_RSRVD0(v)                  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_OCOTP_LOCK
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_OCOTP_LOCK                       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x120))
+#define BP_OCOTP_LOCK_ROM7                  31
+#define BM_OCOTP_LOCK_ROM7                  0x80000000
+#define BF_OCOTP_LOCK_ROM7(v)               (((v) << 31) & 0x80000000)
+#define BP_OCOTP_LOCK_ROM6                  30
+#define BM_OCOTP_LOCK_ROM6                  0x40000000
+#define BF_OCOTP_LOCK_ROM6(v)               (((v) << 30) & 0x40000000)
+#define BP_OCOTP_LOCK_ROM5                  29
+#define BM_OCOTP_LOCK_ROM5                  0x20000000
+#define BF_OCOTP_LOCK_ROM5(v)               (((v) << 29) & 0x20000000)
+#define BP_OCOTP_LOCK_ROM4                  28
+#define BM_OCOTP_LOCK_ROM4                  0x10000000
+#define BF_OCOTP_LOCK_ROM4(v)               (((v) << 28) & 0x10000000)
+#define BP_OCOTP_LOCK_ROM3                  27
+#define BM_OCOTP_LOCK_ROM3                  0x8000000
+#define BF_OCOTP_LOCK_ROM3(v)               (((v) << 27) & 0x8000000)
+#define BP_OCOTP_LOCK_ROM2                  26
+#define BM_OCOTP_LOCK_ROM2                  0x4000000
+#define BF_OCOTP_LOCK_ROM2(v)               (((v) << 26) & 0x4000000)
+#define BP_OCOTP_LOCK_ROM1                  25
+#define BM_OCOTP_LOCK_ROM1                  0x2000000
+#define BF_OCOTP_LOCK_ROM1(v)               (((v) << 25) & 0x2000000)
+#define BP_OCOTP_LOCK_ROM0                  24
+#define BM_OCOTP_LOCK_ROM0                  0x1000000
+#define BF_OCOTP_LOCK_ROM0(v)               (((v) << 24) & 0x1000000)
+#define BP_OCOTP_LOCK_HWSW_SHADOW_ALT       23
+#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT       0x800000
+#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v)    (((v) << 23) & 0x800000)
+#define BP_OCOTP_LOCK_CRYPTODCP_ALT         22
+#define BM_OCOTP_LOCK_CRYPTODCP_ALT         0x400000
+#define BF_OCOTP_LOCK_CRYPTODCP_ALT(v)      (((v) << 22) & 0x400000)
+#define BP_OCOTP_LOCK_CRYPTOKEY_ALT         21
+#define BM_OCOTP_LOCK_CRYPTOKEY_ALT         0x200000
+#define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v)      (((v) << 21) & 0x200000)
+#define BP_OCOTP_LOCK_PIN                   20
+#define BM_OCOTP_LOCK_PIN                   0x100000
+#define BF_OCOTP_LOCK_PIN(v)                (((v) << 20) & 0x100000)
+#define BP_OCOTP_LOCK_OPS                   19
+#define BM_OCOTP_LOCK_OPS                   0x80000
+#define BF_OCOTP_LOCK_OPS(v)                (((v) << 19) & 0x80000)
+#define BP_OCOTP_LOCK_UN2                   18
+#define BM_OCOTP_LOCK_UN2                   0x40000
+#define BF_OCOTP_LOCK_UN2(v)                (((v) << 18) & 0x40000)
+#define BP_OCOTP_LOCK_UN1                   17
+#define BM_OCOTP_LOCK_UN1                   0x20000
+#define BF_OCOTP_LOCK_UN1(v)                (((v) << 17) & 0x20000)
+#define BP_OCOTP_LOCK_UN0                   16
+#define BM_OCOTP_LOCK_UN0                   0x10000
+#define BF_OCOTP_LOCK_UN0(v)                (((v) << 16) & 0x10000)
+#define BP_OCOTP_LOCK_UNALLOCATED           11
+#define BM_OCOTP_LOCK_UNALLOCATED           0xf800
+#define BF_OCOTP_LOCK_UNALLOCATED(v)        (((v) << 11) & 0xf800)
+#define BP_OCOTP_LOCK_ROM_SHADOW            10
+#define BM_OCOTP_LOCK_ROM_SHADOW            0x400
+#define BF_OCOTP_LOCK_ROM_SHADOW(v)         (((v) << 10) & 0x400)
+#define BP_OCOTP_LOCK_CUSTCAP               9
+#define BM_OCOTP_LOCK_CUSTCAP               0x200
+#define BF_OCOTP_LOCK_CUSTCAP(v)            (((v) << 9) & 0x200)
+#define BP_OCOTP_LOCK_HWSW                  8
+#define BM_OCOTP_LOCK_HWSW                  0x100
+#define BF_OCOTP_LOCK_HWSW(v)               (((v) << 8) & 0x100)
+#define BP_OCOTP_LOCK_CUSTCAP_SHADOW        7
+#define BM_OCOTP_LOCK_CUSTCAP_SHADOW        0x80
+#define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v)     (((v) << 7) & 0x80)
+#define BP_OCOTP_LOCK_HWSW_SHADOW           6
+#define BM_OCOTP_LOCK_HWSW_SHADOW           0x40
+#define BF_OCOTP_LOCK_HWSW_SHADOW(v)        (((v) << 6) & 0x40)
+#define BP_OCOTP_LOCK_CRYPTODCP             5
+#define BM_OCOTP_LOCK_CRYPTODCP             0x20
+#define BF_OCOTP_LOCK_CRYPTODCP(v)          (((v) << 5) & 0x20)
+#define BP_OCOTP_LOCK_CRYPTOKEY             4
+#define BM_OCOTP_LOCK_CRYPTOKEY             0x10
+#define BF_OCOTP_LOCK_CRYPTOKEY(v)          (((v) << 4) & 0x10)
+#define BP_OCOTP_LOCK_CUST3                 3
+#define BM_OCOTP_LOCK_CUST3                 0x8
+#define BF_OCOTP_LOCK_CUST3(v)              (((v) << 3) & 0x8)
+#define BP_OCOTP_LOCK_CUST2                 2
+#define BM_OCOTP_LOCK_CUST2                 0x4
+#define BF_OCOTP_LOCK_CUST2(v)              (((v) << 2) & 0x4)
+#define BP_OCOTP_LOCK_CUST1                 1
+#define BM_OCOTP_LOCK_CUST1                 0x2
+#define BF_OCOTP_LOCK_CUST1(v)              (((v) << 1) & 0x2)
+#define BP_OCOTP_LOCK_CUST0                 0
+#define BM_OCOTP_LOCK_CUST0                 0x1
+#define BF_OCOTP_LOCK_CUST0(v)              (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_OCOTP_OPSn
+ * Address: 0x130+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_OPSn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x130+(n)*0x10))
+#define BP_OCOTP_OPSn_BITS      0
+#define BM_OCOTP_OPSn_BITS      0xffffffff
+#define BF_OCOTP_OPSn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_UNn
+ * Address: 0x170+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_UNn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x170+(n)*0x10))
+#define BP_OCOTP_UNn_BITS       0
+#define BM_OCOTP_UNn_BITS       0xffffffff
+#define BF_OCOTP_UNn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_ROMn
+ * Address: 0x1a0+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_ROMn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x1a0+(n)*0x10))
+#define BP_OCOTP_ROMn_BITS      0
+#define BM_OCOTP_ROMn_BITS      0xffffffff
+#define BF_OCOTP_ROMn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_VERSION
+ * Address: 0x220
+ * SCT: no
+*/
+#define HW_OCOTP_VERSION            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x220))
+#define BP_OCOTP_VERSION_MAJOR      24
+#define BM_OCOTP_VERSION_MAJOR      0xff000000
+#define BF_OCOTP_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_OCOTP_VERSION_MINOR      16
+#define BM_OCOTP_VERSION_MINOR      0xff0000
+#define BF_OCOTP_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_OCOTP_VERSION_STEP       0
+#define BM_OCOTP_VERSION_STEP       0xffff
+#define BF_OCOTP_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__OCOTP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h
new file mode 100644
index 0000000000..a8faa358c5
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-pinctrl.h
@@ -0,0 +1,216 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__PINCTRL__H__
+#define __HEADERGEN__IMX233__PINCTRL__H__
+
+#define REGS_PINCTRL_BASE (0x80018000)
+
+#define REGS_PINCTRL_VERSION "3.2.0"
+
+/**
+ * Register: HW_PINCTRL_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_PINCTRL_CTRL             (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
+#define HW_PINCTRL_CTRL_SET         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
+#define HW_PINCTRL_CTRL_CLR         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
+#define HW_PINCTRL_CTRL_TOG         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
+#define BP_PINCTRL_CTRL_SFTRST      31
+#define BM_PINCTRL_CTRL_SFTRST      0x80000000
+#define BF_PINCTRL_CTRL_SFTRST(v)   (((v) << 31) & 0x80000000)
+#define BP_PINCTRL_CTRL_CLKGATE     30
+#define BM_PINCTRL_CTRL_CLKGATE     0x40000000
+#define BF_PINCTRL_CTRL_CLKGATE(v)  (((v) << 30) & 0x40000000)
+#define BP_PINCTRL_CTRL_RSRVD2      28
+#define BM_PINCTRL_CTRL_RSRVD2      0x30000000
+#define BF_PINCTRL_CTRL_RSRVD2(v)   (((v) << 28) & 0x30000000)
+#define BP_PINCTRL_CTRL_PRESENT3    27
+#define BM_PINCTRL_CTRL_PRESENT3    0x8000000
+#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 27) & 0x8000000)
+#define BP_PINCTRL_CTRL_PRESENT2    26
+#define BM_PINCTRL_CTRL_PRESENT2    0x4000000
+#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 26) & 0x4000000)
+#define BP_PINCTRL_CTRL_PRESENT1    25
+#define BM_PINCTRL_CTRL_PRESENT1    0x2000000
+#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 25) & 0x2000000)
+#define BP_PINCTRL_CTRL_PRESENT0    24
+#define BM_PINCTRL_CTRL_PRESENT0    0x1000000
+#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 24) & 0x1000000)
+#define BP_PINCTRL_CTRL_RSRVD1      3
+#define BM_PINCTRL_CTRL_RSRVD1      0xfffff8
+#define BF_PINCTRL_CTRL_RSRVD1(v)   (((v) << 3) & 0xfffff8)
+#define BP_PINCTRL_CTRL_IRQOUT2     2
+#define BM_PINCTRL_CTRL_IRQOUT2     0x4
+#define BF_PINCTRL_CTRL_IRQOUT2(v)  (((v) << 2) & 0x4)
+#define BP_PINCTRL_CTRL_IRQOUT1     1
+#define BM_PINCTRL_CTRL_IRQOUT1     0x2
+#define BF_PINCTRL_CTRL_IRQOUT1(v)  (((v) << 1) & 0x2)
+#define BP_PINCTRL_CTRL_IRQOUT0     0
+#define BM_PINCTRL_CTRL_IRQOUT0     0x1
+#define BF_PINCTRL_CTRL_IRQOUT0(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PINCTRL_MUXSELn
+ * Address: 0x100+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_MUXSELn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0))
+#define HW_PINCTRL_MUXSELn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4))
+#define HW_PINCTRL_MUXSELn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8))
+#define HW_PINCTRL_MUXSELn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc))
+#define BP_PINCTRL_MUXSELn_BITS     0
+#define BM_PINCTRL_MUXSELn_BITS     0xffffffff
+#define BF_PINCTRL_MUXSELn_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DRIVEn
+ * Address: 0x200+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DRIVEn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DRIVEn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DRIVEn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DRIVEn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DRIVEn_BITS      0
+#define BM_PINCTRL_DRIVEn_BITS      0xffffffff
+#define BF_PINCTRL_DRIVEn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_PULLn
+ * Address: 0x400+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_PULLn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0))
+#define HW_PINCTRL_PULLn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4))
+#define HW_PINCTRL_PULLn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8))
+#define HW_PINCTRL_PULLn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc))
+#define BP_PINCTRL_PULLn_BITS       0
+#define BM_PINCTRL_PULLn_BITS       0xffffffff
+#define BF_PINCTRL_PULLn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DOUTn
+ * Address: 0x500+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DOUTn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DOUTn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DOUTn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DOUTn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DOUTn_BITS       0
+#define BM_PINCTRL_DOUTn_BITS       0xffffffff
+#define BF_PINCTRL_DOUTn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DINn
+ * Address: 0x600+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DINn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DINn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DINn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DINn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DINn_BITS    0
+#define BM_PINCTRL_DINn_BITS    0xffffffff
+#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DOEn
+ * Address: 0x700+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DOEn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DOEn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DOEn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DOEn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DOEn_BITS    0
+#define BM_PINCTRL_DOEn_BITS    0xffffffff
+#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_PIN2IRQn
+ * Address: 0x800+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_PIN2IRQn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0))
+#define HW_PINCTRL_PIN2IRQn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4))
+#define HW_PINCTRL_PIN2IRQn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8))
+#define HW_PINCTRL_PIN2IRQn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc))
+#define BP_PINCTRL_PIN2IRQn_BITS    0
+#define BM_PINCTRL_PIN2IRQn_BITS    0xffffffff
+#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQENn
+ * Address: 0x900+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQENn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQENn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQENn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQENn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQENn_BITS      0
+#define BM_PINCTRL_IRQENn_BITS      0xffffffff
+#define BF_PINCTRL_IRQENn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQLEVELn
+ * Address: 0xa00+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQLEVELn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQLEVELn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQLEVELn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQLEVELn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQLEVELn_BITS       0
+#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
+#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQPOLn
+ * Address: 0xb00+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQPOLn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQPOLn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQPOLn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQPOLn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQPOLn_BITS     0
+#define BM_PINCTRL_IRQPOLn_BITS     0xffffffff
+#define BF_PINCTRL_IRQPOLn_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQSTATn
+ * Address: 0xc00+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQSTATn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQSTATn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQSTATn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQSTATn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc00+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQSTATn_BITS    0
+#define BM_PINCTRL_IRQSTATn_BITS    0xffffffff
+#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__IMX233__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-power.h b/firmware/target/arm/imx233/regs/imx233/regs-power.h
new file mode 100644
index 0000000000..27357c9fe2
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-power.h
@@ -0,0 +1,807 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__POWER__H__
+#define __HEADERGEN__IMX233__POWER__H__
+
+#define REGS_POWER_BASE (0x80044000)
+
+#define REGS_POWER_VERSION "3.2.0"
+
+/**
+ * Register: HW_POWER_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_POWER_CTRL                               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0))
+#define HW_POWER_CTRL_SET                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4))
+#define HW_POWER_CTRL_CLR                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8))
+#define HW_POWER_CTRL_TOG                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc))
+#define BP_POWER_CTRL_RSRVD3                        31
+#define BM_POWER_CTRL_RSRVD3                        0x80000000
+#define BF_POWER_CTRL_RSRVD3(v)                     (((v) << 31) & 0x80000000)
+#define BP_POWER_CTRL_CLKGATE                       30
+#define BM_POWER_CTRL_CLKGATE                       0x40000000
+#define BF_POWER_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
+#define BP_POWER_CTRL_RSRVD2                        28
+#define BM_POWER_CTRL_RSRVD2                        0x30000000
+#define BF_POWER_CTRL_RSRVD2(v)                     (((v) << 28) & 0x30000000)
+#define BP_POWER_CTRL_PSWITCH_MID_TRAN              27
+#define BM_POWER_CTRL_PSWITCH_MID_TRAN              0x8000000
+#define BF_POWER_CTRL_PSWITCH_MID_TRAN(v)           (((v) << 27) & 0x8000000)
+#define BP_POWER_CTRL_RSRVD1                        25
+#define BM_POWER_CTRL_RSRVD1                        0x6000000
+#define BF_POWER_CTRL_RSRVD1(v)                     (((v) << 25) & 0x6000000)
+#define BP_POWER_CTRL_DCDC4P2_BO_IRQ                24
+#define BM_POWER_CTRL_DCDC4P2_BO_IRQ                0x1000000
+#define BF_POWER_CTRL_DCDC4P2_BO_IRQ(v)             (((v) << 24) & 0x1000000)
+#define BP_POWER_CTRL_ENIRQ_DCDC4P2_BO              23
+#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO              0x800000
+#define BF_POWER_CTRL_ENIRQ_DCDC4P2_BO(v)           (((v) << 23) & 0x800000)
+#define BP_POWER_CTRL_VDD5V_DROOP_IRQ               22
+#define BM_POWER_CTRL_VDD5V_DROOP_IRQ               0x400000
+#define BF_POWER_CTRL_VDD5V_DROOP_IRQ(v)            (((v) << 22) & 0x400000)
+#define BP_POWER_CTRL_ENIRQ_VDD5V_DROOP             21
+#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP             0x200000
+#define BF_POWER_CTRL_ENIRQ_VDD5V_DROOP(v)          (((v) << 21) & 0x200000)
+#define BP_POWER_CTRL_PSWITCH_IRQ                   20
+#define BM_POWER_CTRL_PSWITCH_IRQ                   0x100000
+#define BF_POWER_CTRL_PSWITCH_IRQ(v)                (((v) << 20) & 0x100000)
+#define BP_POWER_CTRL_PSWITCH_IRQ_SRC               19
+#define BM_POWER_CTRL_PSWITCH_IRQ_SRC               0x80000
+#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v)            (((v) << 19) & 0x80000)
+#define BP_POWER_CTRL_POLARITY_PSWITCH              18
+#define BM_POWER_CTRL_POLARITY_PSWITCH              0x40000
+#define BF_POWER_CTRL_POLARITY_PSWITCH(v)           (((v) << 18) & 0x40000)
+#define BP_POWER_CTRL_ENIRQ_PSWITCH                 17
+#define BM_POWER_CTRL_ENIRQ_PSWITCH                 0x20000
+#define BF_POWER_CTRL_ENIRQ_PSWITCH(v)              (((v) << 17) & 0x20000)
+#define BP_POWER_CTRL_POLARITY_DC_OK                16
+#define BM_POWER_CTRL_POLARITY_DC_OK                0x10000
+#define BF_POWER_CTRL_POLARITY_DC_OK(v)             (((v) << 16) & 0x10000)
+#define BP_POWER_CTRL_DC_OK_IRQ                     15
+#define BM_POWER_CTRL_DC_OK_IRQ                     0x8000
+#define BF_POWER_CTRL_DC_OK_IRQ(v)                  (((v) << 15) & 0x8000)
+#define BP_POWER_CTRL_ENIRQ_DC_OK                   14
+#define BM_POWER_CTRL_ENIRQ_DC_OK                   0x4000
+#define BF_POWER_CTRL_ENIRQ_DC_OK(v)                (((v) << 14) & 0x4000)
+#define BP_POWER_CTRL_BATT_BO_IRQ                   13
+#define BM_POWER_CTRL_BATT_BO_IRQ                   0x2000
+#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) << 13) & 0x2000)
+#define BP_POWER_CTRL_ENIRQBATT_BO                  12
+#define BM_POWER_CTRL_ENIRQBATT_BO                  0x1000
+#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) << 12) & 0x1000)
+#define BP_POWER_CTRL_VDDIO_BO_IRQ                  11
+#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x800
+#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) << 11) & 0x800)
+#define BP_POWER_CTRL_ENIRQ_VDDIO_BO                10
+#define BM_POWER_CTRL_ENIRQ_VDDIO_BO                0x400
+#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v)             (((v) << 10) & 0x400)
+#define BP_POWER_CTRL_VDDA_BO_IRQ                   9
+#define BM_POWER_CTRL_VDDA_BO_IRQ                   0x200
+#define BF_POWER_CTRL_VDDA_BO_IRQ(v)                (((v) << 9) & 0x200)
+#define BP_POWER_CTRL_ENIRQ_VDDA_BO                 8
+#define BM_POWER_CTRL_ENIRQ_VDDA_BO                 0x100
+#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v)              (((v) << 8) & 0x100)
+#define BP_POWER_CTRL_VDDD_BO_IRQ                   7
+#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x80
+#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) << 7) & 0x80)
+#define BP_POWER_CTRL_ENIRQ_VDDD_BO                 6
+#define BM_POWER_CTRL_ENIRQ_VDDD_BO                 0x40
+#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v)              (((v) << 6) & 0x40)
+#define BP_POWER_CTRL_POLARITY_VBUSVALID            5
+#define BM_POWER_CTRL_POLARITY_VBUSVALID            0x20
+#define BF_POWER_CTRL_POLARITY_VBUSVALID(v)         (((v) << 5) & 0x20)
+#define BP_POWER_CTRL_VBUSVALID_IRQ                 4
+#define BM_POWER_CTRL_VBUSVALID_IRQ                 0x10
+#define BF_POWER_CTRL_VBUSVALID_IRQ(v)              (((v) << 4) & 0x10)
+#define BP_POWER_CTRL_ENIRQ_VBUS_VALID              3
+#define BM_POWER_CTRL_ENIRQ_VBUS_VALID              0x8
+#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v)           (((v) << 3) & 0x8)
+#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) << 2) & 0x4)
+#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) << 1) & 0x2)
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_5VCTRL
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_POWER_5VCTRL                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0))
+#define HW_POWER_5VCTRL_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4))
+#define HW_POWER_5VCTRL_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8))
+#define HW_POWER_5VCTRL_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc))
+#define BP_POWER_5VCTRL_RSRVD6                  30
+#define BM_POWER_5VCTRL_RSRVD6                  0xc0000000
+#define BF_POWER_5VCTRL_RSRVD6(v)               (((v) << 30) & 0xc0000000)
+#define BP_POWER_5VCTRL_VBUSDROOP_TRSH          28
+#define BM_POWER_5VCTRL_VBUSDROOP_TRSH          0x30000000
+#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v)       (((v) << 28) & 0x30000000)
+#define BP_POWER_5VCTRL_RSRVD5                  27
+#define BM_POWER_5VCTRL_RSRVD5                  0x8000000
+#define BF_POWER_5VCTRL_RSRVD5(v)               (((v) << 27) & 0x8000000)
+#define BP_POWER_5VCTRL_HEADROOM_ADJ            24
+#define BM_POWER_5VCTRL_HEADROOM_ADJ            0x7000000
+#define BF_POWER_5VCTRL_HEADROOM_ADJ(v)         (((v) << 24) & 0x7000000)
+#define BP_POWER_5VCTRL_RSRVD4                  21
+#define BM_POWER_5VCTRL_RSRVD4                  0xe00000
+#define BF_POWER_5VCTRL_RSRVD4(v)               (((v) << 21) & 0xe00000)
+#define BP_POWER_5VCTRL_PWD_CHARGE_4P2          20
+#define BM_POWER_5VCTRL_PWD_CHARGE_4P2          0x100000
+#define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v)       (((v) << 20) & 0x100000)
+#define BP_POWER_5VCTRL_RSRVD3                  18
+#define BM_POWER_5VCTRL_RSRVD3                  0xc0000
+#define BF_POWER_5VCTRL_RSRVD3(v)               (((v) << 18) & 0xc0000)
+#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT       12
+#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT       0x3f000
+#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v)    (((v) << 12) & 0x3f000)
+#define BP_POWER_5VCTRL_RSRVD2                  11
+#define BM_POWER_5VCTRL_RSRVD2                  0x800
+#define BF_POWER_5VCTRL_RSRVD2(v)               (((v) << 11) & 0x800)
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH          8
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH          0x700
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)       (((v) << 8) & 0x700)
+#define BP_POWER_5VCTRL_PWDN_5VBRNOUT           7
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT           0x80
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)        (((v) << 7) & 0x80)
+#define BP_POWER_5VCTRL_ENABLE_LINREG_ILIMIT    6
+#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT    0x40
+#define BF_POWER_5VCTRL_ENABLE_LINREG_ILIMIT(v) (((v) << 6) & 0x40)
+#define BP_POWER_5VCTRL_DCDC_XFER               5
+#define BM_POWER_5VCTRL_DCDC_XFER               0x20
+#define BF_POWER_5VCTRL_DCDC_XFER(v)            (((v) << 5) & 0x20)
+#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT      4
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT      0x10
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)   (((v) << 4) & 0x10)
+#define BP_POWER_5VCTRL_VBUSVALID_TO_B          3
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B          0x8
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)       (((v) << 3) & 0x8)
+#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO          2
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO          0x4
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)       (((v) << 2) & 0x4)
+#define BP_POWER_5VCTRL_PWRUP_VBUS_CMPS         1
+#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS         0x2
+#define BF_POWER_5VCTRL_PWRUP_VBUS_CMPS(v)      (((v) << 1) & 0x2)
+#define BP_POWER_5VCTRL_ENABLE_DCDC             0
+#define BM_POWER_5VCTRL_ENABLE_DCDC             0x1
+#define BF_POWER_5VCTRL_ENABLE_DCDC(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_MINPWR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_POWER_MINPWR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0))
+#define HW_POWER_MINPWR_SET                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4))
+#define HW_POWER_MINPWR_CLR                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8))
+#define HW_POWER_MINPWR_TOG                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc))
+#define BP_POWER_MINPWR_RSRVD1              15
+#define BM_POWER_MINPWR_RSRVD1              0xffff8000
+#define BF_POWER_MINPWR_RSRVD1(v)           (((v) << 15) & 0xffff8000)
+#define BP_POWER_MINPWR_LOWPWR_4P2          14
+#define BM_POWER_MINPWR_LOWPWR_4P2          0x4000
+#define BF_POWER_MINPWR_LOWPWR_4P2(v)       (((v) << 14) & 0x4000)
+#define BP_POWER_MINPWR_VDAC_DUMP_CTRL      13
+#define BM_POWER_MINPWR_VDAC_DUMP_CTRL      0x2000
+#define BF_POWER_MINPWR_VDAC_DUMP_CTRL(v)   (((v) << 13) & 0x2000)
+#define BP_POWER_MINPWR_PWD_BO              12
+#define BM_POWER_MINPWR_PWD_BO              0x1000
+#define BF_POWER_MINPWR_PWD_BO(v)           (((v) << 12) & 0x1000)
+#define BP_POWER_MINPWR_USE_VDDXTAL_VBG     11
+#define BM_POWER_MINPWR_USE_VDDXTAL_VBG     0x800
+#define BF_POWER_MINPWR_USE_VDDXTAL_VBG(v)  (((v) << 11) & 0x800)
+#define BP_POWER_MINPWR_PWD_ANA_CMPS        10
+#define BM_POWER_MINPWR_PWD_ANA_CMPS        0x400
+#define BF_POWER_MINPWR_PWD_ANA_CMPS(v)     (((v) << 10) & 0x400)
+#define BP_POWER_MINPWR_ENABLE_OSC          9
+#define BM_POWER_MINPWR_ENABLE_OSC          0x200
+#define BF_POWER_MINPWR_ENABLE_OSC(v)       (((v) << 9) & 0x200)
+#define BP_POWER_MINPWR_SELECT_OSC          8
+#define BM_POWER_MINPWR_SELECT_OSC          0x100
+#define BF_POWER_MINPWR_SELECT_OSC(v)       (((v) << 8) & 0x100)
+#define BP_POWER_MINPWR_VBG_OFF             7
+#define BM_POWER_MINPWR_VBG_OFF             0x80
+#define BF_POWER_MINPWR_VBG_OFF(v)          (((v) << 7) & 0x80)
+#define BP_POWER_MINPWR_DOUBLE_FETS         6
+#define BM_POWER_MINPWR_DOUBLE_FETS         0x40
+#define BF_POWER_MINPWR_DOUBLE_FETS(v)      (((v) << 6) & 0x40)
+#define BP_POWER_MINPWR_HALF_FETS           5
+#define BM_POWER_MINPWR_HALF_FETS           0x20
+#define BF_POWER_MINPWR_HALF_FETS(v)        (((v) << 5) & 0x20)
+#define BP_POWER_MINPWR_LESSANA_I           4
+#define BM_POWER_MINPWR_LESSANA_I           0x10
+#define BF_POWER_MINPWR_LESSANA_I(v)        (((v) << 4) & 0x10)
+#define BP_POWER_MINPWR_PWD_XTAL24          3
+#define BM_POWER_MINPWR_PWD_XTAL24          0x8
+#define BF_POWER_MINPWR_PWD_XTAL24(v)       (((v) << 3) & 0x8)
+#define BP_POWER_MINPWR_DC_STOPCLK          2
+#define BM_POWER_MINPWR_DC_STOPCLK          0x4
+#define BF_POWER_MINPWR_DC_STOPCLK(v)       (((v) << 2) & 0x4)
+#define BP_POWER_MINPWR_EN_DC_PFM           1
+#define BM_POWER_MINPWR_EN_DC_PFM           0x2
+#define BF_POWER_MINPWR_EN_DC_PFM(v)        (((v) << 1) & 0x2)
+#define BP_POWER_MINPWR_DC_HALFCLK          0
+#define BM_POWER_MINPWR_DC_HALFCLK          0x1
+#define BF_POWER_MINPWR_DC_HALFCLK(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_CHARGE
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_POWER_CHARGE                             (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0))
+#define HW_POWER_CHARGE_SET                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4))
+#define HW_POWER_CHARGE_CLR                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8))
+#define HW_POWER_CHARGE_TOG                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc))
+#define BP_POWER_CHARGE_RSRVD4                      27
+#define BM_POWER_CHARGE_RSRVD4                      0xf8000000
+#define BF_POWER_CHARGE_RSRVD4(v)                   (((v) << 27) & 0xf8000000)
+#define BP_POWER_CHARGE_ADJ_VOLT                    24
+#define BM_POWER_CHARGE_ADJ_VOLT                    0x7000000
+#define BF_POWER_CHARGE_ADJ_VOLT(v)                 (((v) << 24) & 0x7000000)
+#define BP_POWER_CHARGE_RSRVD3                      23
+#define BM_POWER_CHARGE_RSRVD3                      0x800000
+#define BF_POWER_CHARGE_RSRVD3(v)                   (((v) << 23) & 0x800000)
+#define BP_POWER_CHARGE_ENABLE_LOAD                 22
+#define BM_POWER_CHARGE_ENABLE_LOAD                 0x400000
+#define BF_POWER_CHARGE_ENABLE_LOAD(v)              (((v) << 22) & 0x400000)
+#define BP_POWER_CHARGE_ENABLE_CHARGER_RESISTORS    21
+#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS    0x200000
+#define BF_POWER_CHARGE_ENABLE_CHARGER_RESISTORS(v) (((v) << 21) & 0x200000)
+#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT         20
+#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT         0x100000
+#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v)      (((v) << 20) & 0x100000)
+#define BP_POWER_CHARGE_CHRG_STS_OFF                19
+#define BM_POWER_CHARGE_CHRG_STS_OFF                0x80000
+#define BF_POWER_CHARGE_CHRG_STS_OFF(v)             (((v) << 19) & 0x80000)
+#define BP_POWER_CHARGE_LIION_4P1                   18
+#define BM_POWER_CHARGE_LIION_4P1                   0x40000
+#define BF_POWER_CHARGE_LIION_4P1(v)                (((v) << 18) & 0x40000)
+#define BP_POWER_CHARGE_USE_EXTERN_R                17
+#define BM_POWER_CHARGE_USE_EXTERN_R                0x20000
+#define BF_POWER_CHARGE_USE_EXTERN_R(v)             (((v) << 17) & 0x20000)
+#define BP_POWER_CHARGE_PWD_BATTCHRG                16
+#define BM_POWER_CHARGE_PWD_BATTCHRG                0x10000
+#define BF_POWER_CHARGE_PWD_BATTCHRG(v)             (((v) << 16) & 0x10000)
+#define BP_POWER_CHARGE_RSRVD2                      12
+#define BM_POWER_CHARGE_RSRVD2                      0xf000
+#define BF_POWER_CHARGE_RSRVD2(v)                   (((v) << 12) & 0xf000)
+#define BP_POWER_CHARGE_STOP_ILIMIT                 8
+#define BM_POWER_CHARGE_STOP_ILIMIT                 0xf00
+#define BF_POWER_CHARGE_STOP_ILIMIT(v)              (((v) << 8) & 0xf00)
+#define BP_POWER_CHARGE_RSRVD1                      6
+#define BM_POWER_CHARGE_RSRVD1                      0xc0
+#define BF_POWER_CHARGE_RSRVD1(v)                   (((v) << 6) & 0xc0)
+#define BP_POWER_CHARGE_BATTCHRG_I                  0
+#define BM_POWER_CHARGE_BATTCHRG_I                  0x3f
+#define BF_POWER_CHARGE_BATTCHRG_I(v)               (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_POWER_VDDDCTRL
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_POWER_VDDDCTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40))
+#define BP_POWER_VDDDCTRL_ADJTN                 28
+#define BM_POWER_VDDDCTRL_ADJTN                 0xf0000000
+#define BF_POWER_VDDDCTRL_ADJTN(v)              (((v) << 28) & 0xf0000000)
+#define BP_POWER_VDDDCTRL_RSRVD4                24
+#define BM_POWER_VDDDCTRL_RSRVD4                0xf000000
+#define BF_POWER_VDDDCTRL_RSRVD4(v)             (((v) << 24) & 0xf000000)
+#define BP_POWER_VDDDCTRL_PWDN_BRNOUT           23
+#define BM_POWER_VDDDCTRL_PWDN_BRNOUT           0x800000
+#define BF_POWER_VDDDCTRL_PWDN_BRNOUT(v)        (((v) << 23) & 0x800000)
+#define BP_POWER_VDDDCTRL_DISABLE_STEPPING      22
+#define BM_POWER_VDDDCTRL_DISABLE_STEPPING      0x400000
+#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v)   (((v) << 22) & 0x400000)
+#define BP_POWER_VDDDCTRL_ENABLE_LINREG         21
+#define BM_POWER_VDDDCTRL_ENABLE_LINREG         0x200000
+#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v)      (((v) << 21) & 0x200000)
+#define BP_POWER_VDDDCTRL_DISABLE_FET           20
+#define BM_POWER_VDDDCTRL_DISABLE_FET           0x100000
+#define BF_POWER_VDDDCTRL_DISABLE_FET(v)        (((v) << 20) & 0x100000)
+#define BP_POWER_VDDDCTRL_RSRVD3                18
+#define BM_POWER_VDDDCTRL_RSRVD3                0xc0000
+#define BF_POWER_VDDDCTRL_RSRVD3(v)             (((v) << 18) & 0xc0000)
+#define BP_POWER_VDDDCTRL_LINREG_OFFSET         16
+#define BM_POWER_VDDDCTRL_LINREG_OFFSET         0x30000
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)      (((v) << 16) & 0x30000)
+#define BP_POWER_VDDDCTRL_RSRVD2                11
+#define BM_POWER_VDDDCTRL_RSRVD2                0xf800
+#define BF_POWER_VDDDCTRL_RSRVD2(v)             (((v) << 11) & 0xf800)
+#define BP_POWER_VDDDCTRL_BO_OFFSET             8
+#define BM_POWER_VDDDCTRL_BO_OFFSET             0x700
+#define BF_POWER_VDDDCTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
+#define BP_POWER_VDDDCTRL_RSRVD1                5
+#define BM_POWER_VDDDCTRL_RSRVD1                0xe0
+#define BF_POWER_VDDDCTRL_RSRVD1(v)             (((v) << 5) & 0xe0)
+#define BP_POWER_VDDDCTRL_TRG                   0
+#define BM_POWER_VDDDCTRL_TRG                   0x1f
+#define BF_POWER_VDDDCTRL_TRG(v)                (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_VDDACTRL
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_POWER_VDDACTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50))
+#define BP_POWER_VDDACTRL_RSRVD4                20
+#define BM_POWER_VDDACTRL_RSRVD4                0xfff00000
+#define BF_POWER_VDDACTRL_RSRVD4(v)             (((v) << 20) & 0xfff00000)
+#define BP_POWER_VDDACTRL_PWDN_BRNOUT           19
+#define BM_POWER_VDDACTRL_PWDN_BRNOUT           0x80000
+#define BF_POWER_VDDACTRL_PWDN_BRNOUT(v)        (((v) << 19) & 0x80000)
+#define BP_POWER_VDDACTRL_DISABLE_STEPPING      18
+#define BM_POWER_VDDACTRL_DISABLE_STEPPING      0x40000
+#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v)   (((v) << 18) & 0x40000)
+#define BP_POWER_VDDACTRL_ENABLE_LINREG         17
+#define BM_POWER_VDDACTRL_ENABLE_LINREG         0x20000
+#define BF_POWER_VDDACTRL_ENABLE_LINREG(v)      (((v) << 17) & 0x20000)
+#define BP_POWER_VDDACTRL_DISABLE_FET           16
+#define BM_POWER_VDDACTRL_DISABLE_FET           0x10000
+#define BF_POWER_VDDACTRL_DISABLE_FET(v)        (((v) << 16) & 0x10000)
+#define BP_POWER_VDDACTRL_RSRVD3                14
+#define BM_POWER_VDDACTRL_RSRVD3                0xc000
+#define BF_POWER_VDDACTRL_RSRVD3(v)             (((v) << 14) & 0xc000)
+#define BP_POWER_VDDACTRL_LINREG_OFFSET         12
+#define BM_POWER_VDDACTRL_LINREG_OFFSET         0x3000
+#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)      (((v) << 12) & 0x3000)
+#define BP_POWER_VDDACTRL_RSRVD2                11
+#define BM_POWER_VDDACTRL_RSRVD2                0x800
+#define BF_POWER_VDDACTRL_RSRVD2(v)             (((v) << 11) & 0x800)
+#define BP_POWER_VDDACTRL_BO_OFFSET             8
+#define BM_POWER_VDDACTRL_BO_OFFSET             0x700
+#define BF_POWER_VDDACTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
+#define BP_POWER_VDDACTRL_RSRVD1                5
+#define BM_POWER_VDDACTRL_RSRVD1                0xe0
+#define BF_POWER_VDDACTRL_RSRVD1(v)             (((v) << 5) & 0xe0)
+#define BP_POWER_VDDACTRL_TRG                   0
+#define BM_POWER_VDDACTRL_TRG                   0x1f
+#define BF_POWER_VDDACTRL_TRG(v)                (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_VDDIOCTRL
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_POWER_VDDIOCTRL                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60))
+#define BP_POWER_VDDIOCTRL_RSRVD5               24
+#define BM_POWER_VDDIOCTRL_RSRVD5               0xff000000
+#define BF_POWER_VDDIOCTRL_RSRVD5(v)            (((v) << 24) & 0xff000000)
+#define BP_POWER_VDDIOCTRL_ADJTN                20
+#define BM_POWER_VDDIOCTRL_ADJTN                0xf00000
+#define BF_POWER_VDDIOCTRL_ADJTN(v)             (((v) << 20) & 0xf00000)
+#define BP_POWER_VDDIOCTRL_RSRVD4               19
+#define BM_POWER_VDDIOCTRL_RSRVD4               0x80000
+#define BF_POWER_VDDIOCTRL_RSRVD4(v)            (((v) << 19) & 0x80000)
+#define BP_POWER_VDDIOCTRL_PWDN_BRNOUT          18
+#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT          0x40000
+#define BF_POWER_VDDIOCTRL_PWDN_BRNOUT(v)       (((v) << 18) & 0x40000)
+#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING     17
+#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING     0x20000
+#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v)  (((v) << 17) & 0x20000)
+#define BP_POWER_VDDIOCTRL_DISABLE_FET          16
+#define BM_POWER_VDDIOCTRL_DISABLE_FET          0x10000
+#define BF_POWER_VDDIOCTRL_DISABLE_FET(v)       (((v) << 16) & 0x10000)
+#define BP_POWER_VDDIOCTRL_RSRVD3               14
+#define BM_POWER_VDDIOCTRL_RSRVD3               0xc000
+#define BF_POWER_VDDIOCTRL_RSRVD3(v)            (((v) << 14) & 0xc000)
+#define BP_POWER_VDDIOCTRL_LINREG_OFFSET        12
+#define BM_POWER_VDDIOCTRL_LINREG_OFFSET        0x3000
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)     (((v) << 12) & 0x3000)
+#define BP_POWER_VDDIOCTRL_RSRVD2               11
+#define BM_POWER_VDDIOCTRL_RSRVD2               0x800
+#define BF_POWER_VDDIOCTRL_RSRVD2(v)            (((v) << 11) & 0x800)
+#define BP_POWER_VDDIOCTRL_BO_OFFSET            8
+#define BM_POWER_VDDIOCTRL_BO_OFFSET            0x700
+#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)         (((v) << 8) & 0x700)
+#define BP_POWER_VDDIOCTRL_RSRVD1               5
+#define BM_POWER_VDDIOCTRL_RSRVD1               0xe0
+#define BF_POWER_VDDIOCTRL_RSRVD1(v)            (((v) << 5) & 0xe0)
+#define BP_POWER_VDDIOCTRL_TRG                  0
+#define BM_POWER_VDDIOCTRL_TRG                  0x1f
+#define BF_POWER_VDDIOCTRL_TRG(v)               (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_VDDMEMCTRL
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_POWER_VDDMEMCTRL                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70))
+#define BP_POWER_VDDMEMCTRL_RSRVD2              11
+#define BM_POWER_VDDMEMCTRL_RSRVD2              0xfffff800
+#define BF_POWER_VDDMEMCTRL_RSRVD2(v)           (((v) << 11) & 0xfffff800)
+#define BP_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE     10
+#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE     0x400
+#define BF_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE(v)  (((v) << 10) & 0x400)
+#define BP_POWER_VDDMEMCTRL_ENABLE_ILIMIT       9
+#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT       0x200
+#define BF_POWER_VDDMEMCTRL_ENABLE_ILIMIT(v)    (((v) << 9) & 0x200)
+#define BP_POWER_VDDMEMCTRL_ENABLE_LINREG       8
+#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG       0x100
+#define BF_POWER_VDDMEMCTRL_ENABLE_LINREG(v)    (((v) << 8) & 0x100)
+#define BP_POWER_VDDMEMCTRL_RSRVD1              5
+#define BM_POWER_VDDMEMCTRL_RSRVD1              0xe0
+#define BF_POWER_VDDMEMCTRL_RSRVD1(v)           (((v) << 5) & 0xe0)
+#define BP_POWER_VDDMEMCTRL_TRG                 0
+#define BM_POWER_VDDMEMCTRL_TRG                 0x1f
+#define BF_POWER_VDDMEMCTRL_TRG(v)              (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_DCDC4P2
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_POWER_DCDC4P2                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80))
+#define BP_POWER_DCDC4P2_DROPOUT_CTRL       28
+#define BM_POWER_DCDC4P2_DROPOUT_CTRL       0xf0000000
+#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v)    (((v) << 28) & 0xf0000000)
+#define BP_POWER_DCDC4P2_RSRVD5             26
+#define BM_POWER_DCDC4P2_RSRVD5             0xc000000
+#define BF_POWER_DCDC4P2_RSRVD5(v)          (((v) << 26) & 0xc000000)
+#define BP_POWER_DCDC4P2_ISTEAL_THRESH      24
+#define BM_POWER_DCDC4P2_ISTEAL_THRESH      0x3000000
+#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v)   (((v) << 24) & 0x3000000)
+#define BP_POWER_DCDC4P2_ENABLE_4P2         23
+#define BM_POWER_DCDC4P2_ENABLE_4P2         0x800000
+#define BF_POWER_DCDC4P2_ENABLE_4P2(v)      (((v) << 23) & 0x800000)
+#define BP_POWER_DCDC4P2_ENABLE_DCDC        22
+#define BM_POWER_DCDC4P2_ENABLE_DCDC        0x400000
+#define BF_POWER_DCDC4P2_ENABLE_DCDC(v)     (((v) << 22) & 0x400000)
+#define BP_POWER_DCDC4P2_HYST_DIR           21
+#define BM_POWER_DCDC4P2_HYST_DIR           0x200000
+#define BF_POWER_DCDC4P2_HYST_DIR(v)        (((v) << 21) & 0x200000)
+#define BP_POWER_DCDC4P2_HYST_THRESH        20
+#define BM_POWER_DCDC4P2_HYST_THRESH        0x100000
+#define BF_POWER_DCDC4P2_HYST_THRESH(v)     (((v) << 20) & 0x100000)
+#define BP_POWER_DCDC4P2_RSRVD3             19
+#define BM_POWER_DCDC4P2_RSRVD3             0x80000
+#define BF_POWER_DCDC4P2_RSRVD3(v)          (((v) << 19) & 0x80000)
+#define BP_POWER_DCDC4P2_TRG                16
+#define BM_POWER_DCDC4P2_TRG                0x70000
+#define BF_POWER_DCDC4P2_TRG(v)             (((v) << 16) & 0x70000)
+#define BP_POWER_DCDC4P2_RSRVD2             13
+#define BM_POWER_DCDC4P2_RSRVD2             0xe000
+#define BF_POWER_DCDC4P2_RSRVD2(v)          (((v) << 13) & 0xe000)
+#define BP_POWER_DCDC4P2_BO                 8
+#define BM_POWER_DCDC4P2_BO                 0x1f00
+#define BF_POWER_DCDC4P2_BO(v)              (((v) << 8) & 0x1f00)
+#define BP_POWER_DCDC4P2_RSRVD1             5
+#define BM_POWER_DCDC4P2_RSRVD1             0xe0
+#define BF_POWER_DCDC4P2_RSRVD1(v)          (((v) << 5) & 0xe0)
+#define BP_POWER_DCDC4P2_CMPTRIP            0
+#define BM_POWER_DCDC4P2_CMPTRIP            0x1f
+#define BF_POWER_DCDC4P2_CMPTRIP(v)         (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_MISC
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_POWER_MISC                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90))
+#define BP_POWER_MISC_RSRVD2            7
+#define BM_POWER_MISC_RSRVD2            0xffffff80
+#define BF_POWER_MISC_RSRVD2(v)         (((v) << 7) & 0xffffff80)
+#define BP_POWER_MISC_FREQSEL           4
+#define BM_POWER_MISC_FREQSEL           0x70
+#define BF_POWER_MISC_FREQSEL(v)        (((v) << 4) & 0x70)
+#define BP_POWER_MISC_RSRVD1            3
+#define BM_POWER_MISC_RSRVD1            0x8
+#define BF_POWER_MISC_RSRVD1(v)         (((v) << 3) & 0x8)
+#define BP_POWER_MISC_DELAY_TIMING      2
+#define BM_POWER_MISC_DELAY_TIMING      0x4
+#define BF_POWER_MISC_DELAY_TIMING(v)   (((v) << 2) & 0x4)
+#define BP_POWER_MISC_TEST              1
+#define BM_POWER_MISC_TEST              0x2
+#define BF_POWER_MISC_TEST(v)           (((v) << 1) & 0x2)
+#define BP_POWER_MISC_SEL_PLLCLK        0
+#define BM_POWER_MISC_SEL_PLLCLK        0x1
+#define BF_POWER_MISC_SEL_PLLCLK(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_DCLIMITS
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_POWER_DCLIMITS                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0))
+#define BP_POWER_DCLIMITS_RSRVD3            16
+#define BM_POWER_DCLIMITS_RSRVD3            0xffff0000
+#define BF_POWER_DCLIMITS_RSRVD3(v)         (((v) << 16) & 0xffff0000)
+#define BP_POWER_DCLIMITS_RSRVD2            15
+#define BM_POWER_DCLIMITS_RSRVD2            0x8000
+#define BF_POWER_DCLIMITS_RSRVD2(v)         (((v) << 15) & 0x8000)
+#define BP_POWER_DCLIMITS_POSLIMIT_BUCK     8
+#define BM_POWER_DCLIMITS_POSLIMIT_BUCK     0x7f00
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)  (((v) << 8) & 0x7f00)
+#define BP_POWER_DCLIMITS_RSRVD1            7
+#define BM_POWER_DCLIMITS_RSRVD1            0x80
+#define BF_POWER_DCLIMITS_RSRVD1(v)         (((v) << 7) & 0x80)
+#define BP_POWER_DCLIMITS_NEGLIMIT          0
+#define BM_POWER_DCLIMITS_NEGLIMIT          0x7f
+#define BF_POWER_DCLIMITS_NEGLIMIT(v)       (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_POWER_LOOPCTRL
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_POWER_LOOPCTRL                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x0))
+#define HW_POWER_LOOPCTRL_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x4))
+#define HW_POWER_LOOPCTRL_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0x8))
+#define HW_POWER_LOOPCTRL_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0 + 0xc))
+#define BP_POWER_LOOPCTRL_RSRVD3            21
+#define BM_POWER_LOOPCTRL_RSRVD3            0xffe00000
+#define BF_POWER_LOOPCTRL_RSRVD3(v)         (((v) << 21) & 0xffe00000)
+#define BP_POWER_LOOPCTRL_TOGGLE_DIF        20
+#define BM_POWER_LOOPCTRL_TOGGLE_DIF        0x100000
+#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v)     (((v) << 20) & 0x100000)
+#define BP_POWER_LOOPCTRL_HYST_SIGN         19
+#define BM_POWER_LOOPCTRL_HYST_SIGN         0x80000
+#define BF_POWER_LOOPCTRL_HYST_SIGN(v)      (((v) << 19) & 0x80000)
+#define BP_POWER_LOOPCTRL_EN_CM_HYST        18
+#define BM_POWER_LOOPCTRL_EN_CM_HYST        0x40000
+#define BF_POWER_LOOPCTRL_EN_CM_HYST(v)     (((v) << 18) & 0x40000)
+#define BP_POWER_LOOPCTRL_EN_DF_HYST        17
+#define BM_POWER_LOOPCTRL_EN_DF_HYST        0x20000
+#define BF_POWER_LOOPCTRL_EN_DF_HYST(v)     (((v) << 17) & 0x20000)
+#define BP_POWER_LOOPCTRL_CM_HYST_THRESH    16
+#define BM_POWER_LOOPCTRL_CM_HYST_THRESH    0x10000
+#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000)
+#define BP_POWER_LOOPCTRL_DF_HYST_THRESH    15
+#define BM_POWER_LOOPCTRL_DF_HYST_THRESH    0x8000
+#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000)
+#define BP_POWER_LOOPCTRL_RCSCALE_THRESH    14
+#define BM_POWER_LOOPCTRL_RCSCALE_THRESH    0x4000
+#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000)
+#define BP_POWER_LOOPCTRL_EN_RCSCALE        12
+#define BM_POWER_LOOPCTRL_EN_RCSCALE        0x3000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)     (((v) << 12) & 0x3000)
+#define BP_POWER_LOOPCTRL_RSRVD2            11
+#define BM_POWER_LOOPCTRL_RSRVD2            0x800
+#define BF_POWER_LOOPCTRL_RSRVD2(v)         (((v) << 11) & 0x800)
+#define BP_POWER_LOOPCTRL_DC_FF             8
+#define BM_POWER_LOOPCTRL_DC_FF             0x700
+#define BF_POWER_LOOPCTRL_DC_FF(v)          (((v) << 8) & 0x700)
+#define BP_POWER_LOOPCTRL_DC_R              4
+#define BM_POWER_LOOPCTRL_DC_R              0xf0
+#define BF_POWER_LOOPCTRL_DC_R(v)           (((v) << 4) & 0xf0)
+#define BP_POWER_LOOPCTRL_RSRVD1            2
+#define BM_POWER_LOOPCTRL_RSRVD1            0xc
+#define BF_POWER_LOOPCTRL_RSRVD1(v)         (((v) << 2) & 0xc)
+#define BP_POWER_LOOPCTRL_DC_C              0
+#define BM_POWER_LOOPCTRL_DC_C              0x3
+#define BF_POWER_LOOPCTRL_DC_C(v)           (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_POWER_STS
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_POWER_STS                        (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0))
+#define BP_POWER_STS_RSRVD3                 30
+#define BM_POWER_STS_RSRVD3                 0xc0000000
+#define BF_POWER_STS_RSRVD3(v)              (((v) << 30) & 0xc0000000)
+#define BP_POWER_STS_PWRUP_SOURCE           24
+#define BM_POWER_STS_PWRUP_SOURCE           0x3f000000
+#define BF_POWER_STS_PWRUP_SOURCE(v)        (((v) << 24) & 0x3f000000)
+#define BP_POWER_STS_RSRVD2                 22
+#define BM_POWER_STS_RSRVD2                 0xc00000
+#define BF_POWER_STS_RSRVD2(v)              (((v) << 22) & 0xc00000)
+#define BP_POWER_STS_PSWITCH                20
+#define BM_POWER_STS_PSWITCH                0x300000
+#define BF_POWER_STS_PSWITCH(v)             (((v) << 20) & 0x300000)
+#define BP_POWER_STS_RSRVD1                 18
+#define BM_POWER_STS_RSRVD1                 0xc0000
+#define BF_POWER_STS_RSRVD1(v)              (((v) << 18) & 0xc0000)
+#define BP_POWER_STS_AVALID_STATUS          17
+#define BM_POWER_STS_AVALID_STATUS          0x20000
+#define BF_POWER_STS_AVALID_STATUS(v)       (((v) << 17) & 0x20000)
+#define BP_POWER_STS_BVALID_STATUS          16
+#define BM_POWER_STS_BVALID_STATUS          0x10000
+#define BF_POWER_STS_BVALID_STATUS(v)       (((v) << 16) & 0x10000)
+#define BP_POWER_STS_VBUSVALID_STATUS       15
+#define BM_POWER_STS_VBUSVALID_STATUS       0x8000
+#define BF_POWER_STS_VBUSVALID_STATUS(v)    (((v) << 15) & 0x8000)
+#define BP_POWER_STS_SESSEND_STATUS         14
+#define BM_POWER_STS_SESSEND_STATUS         0x4000
+#define BF_POWER_STS_SESSEND_STATUS(v)      (((v) << 14) & 0x4000)
+#define BP_POWER_STS_BATT_BO                13
+#define BM_POWER_STS_BATT_BO                0x2000
+#define BF_POWER_STS_BATT_BO(v)             (((v) << 13) & 0x2000)
+#define BP_POWER_STS_VDD5V_FAULT            12
+#define BM_POWER_STS_VDD5V_FAULT            0x1000
+#define BF_POWER_STS_VDD5V_FAULT(v)         (((v) << 12) & 0x1000)
+#define BP_POWER_STS_CHRGSTS                11
+#define BM_POWER_STS_CHRGSTS                0x800
+#define BF_POWER_STS_CHRGSTS(v)             (((v) << 11) & 0x800)
+#define BP_POWER_STS_DCDC_4P2_BO            10
+#define BM_POWER_STS_DCDC_4P2_BO            0x400
+#define BF_POWER_STS_DCDC_4P2_BO(v)         (((v) << 10) & 0x400)
+#define BP_POWER_STS_DC_OK                  9
+#define BM_POWER_STS_DC_OK                  0x200
+#define BF_POWER_STS_DC_OK(v)               (((v) << 9) & 0x200)
+#define BP_POWER_STS_VDDIO_BO               8
+#define BM_POWER_STS_VDDIO_BO               0x100
+#define BF_POWER_STS_VDDIO_BO(v)            (((v) << 8) & 0x100)
+#define BP_POWER_STS_VDDA_BO                7
+#define BM_POWER_STS_VDDA_BO                0x80
+#define BF_POWER_STS_VDDA_BO(v)             (((v) << 7) & 0x80)
+#define BP_POWER_STS_VDDD_BO                6
+#define BM_POWER_STS_VDDD_BO                0x40
+#define BF_POWER_STS_VDDD_BO(v)             (((v) << 6) & 0x40)
+#define BP_POWER_STS_VDD5V_GT_VDDIO         5
+#define BM_POWER_STS_VDD5V_GT_VDDIO         0x20
+#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) << 5) & 0x20)
+#define BP_POWER_STS_VDD5V_DROOP            4
+#define BM_POWER_STS_VDD5V_DROOP            0x10
+#define BF_POWER_STS_VDD5V_DROOP(v)         (((v) << 4) & 0x10)
+#define BP_POWER_STS_AVALID                 3
+#define BM_POWER_STS_AVALID                 0x8
+#define BF_POWER_STS_AVALID(v)              (((v) << 3) & 0x8)
+#define BP_POWER_STS_BVALID                 2
+#define BM_POWER_STS_BVALID                 0x4
+#define BF_POWER_STS_BVALID(v)              (((v) << 2) & 0x4)
+#define BP_POWER_STS_VBUSVALID              1
+#define BM_POWER_STS_VBUSVALID              0x2
+#define BF_POWER_STS_VBUSVALID(v)           (((v) << 1) & 0x2)
+#define BP_POWER_STS_SESSEND                0
+#define BM_POWER_STS_SESSEND                0x1
+#define BF_POWER_STS_SESSEND(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_SPEED
+ * Address: 0xd0
+ * SCT: yes
+*/
+#define HW_POWER_SPEED              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0))
+#define HW_POWER_SPEED_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4))
+#define HW_POWER_SPEED_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8))
+#define HW_POWER_SPEED_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc))
+#define BP_POWER_SPEED_RSRVD1       24
+#define BM_POWER_SPEED_RSRVD1       0xff000000
+#define BF_POWER_SPEED_RSRVD1(v)    (((v) << 24) & 0xff000000)
+#define BP_POWER_SPEED_STATUS       16
+#define BM_POWER_SPEED_STATUS       0xff0000
+#define BF_POWER_SPEED_STATUS(v)    (((v) << 16) & 0xff0000)
+#define BP_POWER_SPEED_RSRVD0       2
+#define BM_POWER_SPEED_RSRVD0       0xfffc
+#define BF_POWER_SPEED_RSRVD0(v)    (((v) << 2) & 0xfffc)
+#define BP_POWER_SPEED_CTRL         0
+#define BM_POWER_SPEED_CTRL         0x3
+#define BF_POWER_SPEED_CTRL(v)      (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_POWER_BATTMONITOR
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_POWER_BATTMONITOR                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0))
+#define BP_POWER_BATTMONITOR_RSRVD3             26
+#define BM_POWER_BATTMONITOR_RSRVD3             0xfc000000
+#define BF_POWER_BATTMONITOR_RSRVD3(v)          (((v) << 26) & 0xfc000000)
+#define BP_POWER_BATTMONITOR_BATT_VAL           16
+#define BM_POWER_BATTMONITOR_BATT_VAL           0x3ff0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)        (((v) << 16) & 0x3ff0000)
+#define BP_POWER_BATTMONITOR_RSRVD2             11
+#define BM_POWER_BATTMONITOR_RSRVD2             0xf800
+#define BF_POWER_BATTMONITOR_RSRVD2(v)          (((v) << 11) & 0xf800)
+#define BP_POWER_BATTMONITOR_EN_BATADJ          10
+#define BM_POWER_BATTMONITOR_EN_BATADJ          0x400
+#define BF_POWER_BATTMONITOR_EN_BATADJ(v)       (((v) << 10) & 0x400)
+#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT    9
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT    0x200
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200)
+#define BP_POWER_BATTMONITOR_BRWNOUT_PWD        8
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD        0x100
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)     (((v) << 8) & 0x100)
+#define BP_POWER_BATTMONITOR_RSRVD1             5
+#define BM_POWER_BATTMONITOR_RSRVD1             0xe0
+#define BF_POWER_BATTMONITOR_RSRVD1(v)          (((v) << 5) & 0xe0)
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL        0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL        0x1f
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)     (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_RESET
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_POWER_RESET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0))
+#define HW_POWER_RESET_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4))
+#define HW_POWER_RESET_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8))
+#define HW_POWER_RESET_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc))
+#define BP_POWER_RESET_UNLOCK       16
+#define BM_POWER_RESET_UNLOCK       0xffff0000
+#define BV_POWER_RESET_UNLOCK__KEY  0x3e77
+#define BF_POWER_RESET_UNLOCK(v)    (((v) << 16) & 0xffff0000)
+#define BF_POWER_RESET_UNLOCK_V(v)  ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000)
+#define BP_POWER_RESET_RSRVD1       2
+#define BM_POWER_RESET_RSRVD1       0xfffc
+#define BF_POWER_RESET_RSRVD1(v)    (((v) << 2) & 0xfffc)
+#define BP_POWER_RESET_PWD_OFF      1
+#define BM_POWER_RESET_PWD_OFF      0x2
+#define BF_POWER_RESET_PWD_OFF(v)   (((v) << 1) & 0x2)
+#define BP_POWER_RESET_PWD          0
+#define BM_POWER_RESET_PWD          0x1
+#define BF_POWER_RESET_PWD(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_DEBUG
+ * Address: 0x110
+ * SCT: yes
+*/
+#define HW_POWER_DEBUG                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x0))
+#define HW_POWER_DEBUG_SET                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x4))
+#define HW_POWER_DEBUG_CLR                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0x8))
+#define HW_POWER_DEBUG_TOG                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110 + 0xc))
+#define BP_POWER_DEBUG_RSRVD0               4
+#define BM_POWER_DEBUG_RSRVD0               0xfffffff0
+#define BF_POWER_DEBUG_RSRVD0(v)            (((v) << 4) & 0xfffffff0)
+#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK     3
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK     0x8
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)  (((v) << 3) & 0x8)
+#define BP_POWER_DEBUG_AVALIDPIOLOCK        2
+#define BM_POWER_DEBUG_AVALIDPIOLOCK        0x4
+#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)     (((v) << 2) & 0x4)
+#define BP_POWER_DEBUG_BVALIDPIOLOCK        1
+#define BM_POWER_DEBUG_BVALIDPIOLOCK        0x2
+#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)     (((v) << 1) & 0x2)
+#define BP_POWER_DEBUG_SESSENDPIOLOCK       0
+#define BM_POWER_DEBUG_SESSENDPIOLOCK       0x1
+#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_SPECIAL
+ * Address: 0x120
+ * SCT: yes
+*/
+#define HW_POWER_SPECIAL            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x0))
+#define HW_POWER_SPECIAL_SET        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x4))
+#define HW_POWER_SPECIAL_CLR        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0x8))
+#define HW_POWER_SPECIAL_TOG        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x120 + 0xc))
+#define BP_POWER_SPECIAL_TEST       0
+#define BM_POWER_SPECIAL_TEST       0xffffffff
+#define BF_POWER_SPECIAL_TEST(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_POWER_VERSION
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_POWER_VERSION            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x130))
+#define BP_POWER_VERSION_MAJOR      24
+#define BM_POWER_VERSION_MAJOR      0xff000000
+#define BF_POWER_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_POWER_VERSION_MINOR      16
+#define BM_POWER_VERSION_MINOR      0xff0000
+#define BF_POWER_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_POWER_VERSION_STEP       0
+#define BM_POWER_VERSION_STEP       0xffff
+#define BF_POWER_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pwm.h b/firmware/target/arm/imx233/regs/imx233/regs-pwm.h
new file mode 100644
index 0000000000..2a822714d8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-pwm.h
@@ -0,0 +1,165 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__PWM__H__
+#define __HEADERGEN__IMX233__PWM__H__
+
+#define REGS_PWM_BASE (0x80064000)
+
+#define REGS_PWM_VERSION "3.2.0"
+
+/**
+ * Register: HW_PWM_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_PWM_CTRL                         (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0))
+#define HW_PWM_CTRL_SET                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4))
+#define HW_PWM_CTRL_CLR                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8))
+#define HW_PWM_CTRL_TOG                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc))
+#define BP_PWM_CTRL_SFTRST                  31
+#define BM_PWM_CTRL_SFTRST                  0x80000000
+#define BF_PWM_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BP_PWM_CTRL_CLKGATE                 30
+#define BM_PWM_CTRL_CLKGATE                 0x40000000
+#define BF_PWM_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_PWM_CTRL_PWM4_PRESENT            29
+#define BM_PWM_CTRL_PWM4_PRESENT            0x20000000
+#define BF_PWM_CTRL_PWM4_PRESENT(v)         (((v) << 29) & 0x20000000)
+#define BP_PWM_CTRL_PWM3_PRESENT            28
+#define BM_PWM_CTRL_PWM3_PRESENT            0x10000000
+#define BF_PWM_CTRL_PWM3_PRESENT(v)         (((v) << 28) & 0x10000000)
+#define BP_PWM_CTRL_PWM2_PRESENT            27
+#define BM_PWM_CTRL_PWM2_PRESENT            0x8000000
+#define BF_PWM_CTRL_PWM2_PRESENT(v)         (((v) << 27) & 0x8000000)
+#define BP_PWM_CTRL_PWM1_PRESENT            26
+#define BM_PWM_CTRL_PWM1_PRESENT            0x4000000
+#define BF_PWM_CTRL_PWM1_PRESENT(v)         (((v) << 26) & 0x4000000)
+#define BP_PWM_CTRL_PWM0_PRESENT            25
+#define BM_PWM_CTRL_PWM0_PRESENT            0x2000000
+#define BF_PWM_CTRL_PWM0_PRESENT(v)         (((v) << 25) & 0x2000000)
+#define BP_PWM_CTRL_RSRVD1                  7
+#define BM_PWM_CTRL_RSRVD1                  0x1ffff80
+#define BF_PWM_CTRL_RSRVD1(v)               (((v) << 7) & 0x1ffff80)
+#define BP_PWM_CTRL_OUTPUT_CUTOFF_EN        6
+#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN        0x40
+#define BF_PWM_CTRL_OUTPUT_CUTOFF_EN(v)     (((v) << 6) & 0x40)
+#define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    5
+#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    0x20
+#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v) (((v) << 5) & 0x20)
+#define BP_PWM_CTRL_PWM4_ENABLE             4
+#define BM_PWM_CTRL_PWM4_ENABLE             0x10
+#define BF_PWM_CTRL_PWM4_ENABLE(v)          (((v) << 4) & 0x10)
+#define BP_PWM_CTRL_PWM3_ENABLE             3
+#define BM_PWM_CTRL_PWM3_ENABLE             0x8
+#define BF_PWM_CTRL_PWM3_ENABLE(v)          (((v) << 3) & 0x8)
+#define BP_PWM_CTRL_PWM2_ENABLE             2
+#define BM_PWM_CTRL_PWM2_ENABLE             0x4
+#define BF_PWM_CTRL_PWM2_ENABLE(v)          (((v) << 2) & 0x4)
+#define BP_PWM_CTRL_PWM1_ENABLE             1
+#define BM_PWM_CTRL_PWM1_ENABLE             0x2
+#define BF_PWM_CTRL_PWM1_ENABLE(v)          (((v) << 1) & 0x2)
+#define BP_PWM_CTRL_PWM0_ENABLE             0
+#define BM_PWM_CTRL_PWM0_ENABLE             0x1
+#define BF_PWM_CTRL_PWM0_ENABLE(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PWM_ACTIVEn
+ * Address: 0x10+n*0x20
+ * SCT: yes
+*/
+#define HW_PWM_ACTIVEn(n)           (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0))
+#define HW_PWM_ACTIVEn_SET(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4))
+#define HW_PWM_ACTIVEn_CLR(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8))
+#define HW_PWM_ACTIVEn_TOG(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc))
+#define BP_PWM_ACTIVEn_INACTIVE     16
+#define BM_PWM_ACTIVEn_INACTIVE     0xffff0000
+#define BF_PWM_ACTIVEn_INACTIVE(v)  (((v) << 16) & 0xffff0000)
+#define BP_PWM_ACTIVEn_ACTIVE       0
+#define BM_PWM_ACTIVEn_ACTIVE       0xffff
+#define BF_PWM_ACTIVEn_ACTIVE(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_PWM_PERIODn
+ * Address: 0x20+n*0x20
+ * SCT: yes
+*/
+#define HW_PWM_PERIODn(n)                   (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0))
+#define HW_PWM_PERIODn_SET(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4))
+#define HW_PWM_PERIODn_CLR(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8))
+#define HW_PWM_PERIODn_TOG(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc))
+#define BP_PWM_PERIODn_RSRVD2               25
+#define BM_PWM_PERIODn_RSRVD2               0xfe000000
+#define BF_PWM_PERIODn_RSRVD2(v)            (((v) << 25) & 0xfe000000)
+#define BP_PWM_PERIODn_MATT_SEL             24
+#define BM_PWM_PERIODn_MATT_SEL             0x1000000
+#define BF_PWM_PERIODn_MATT_SEL(v)          (((v) << 24) & 0x1000000)
+#define BP_PWM_PERIODn_MATT                 23
+#define BM_PWM_PERIODn_MATT                 0x800000
+#define BF_PWM_PERIODn_MATT(v)              (((v) << 23) & 0x800000)
+#define BP_PWM_PERIODn_CDIV                 20
+#define BM_PWM_PERIODn_CDIV                 0x700000
+#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
+#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
+#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
+#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
+#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
+#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
+#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
+#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
+#define BF_PWM_PERIODn_CDIV(v)              (((v) << 20) & 0x700000)
+#define BF_PWM_PERIODn_CDIV_V(v)            ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000)
+#define BP_PWM_PERIODn_INACTIVE_STATE       18
+#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
+#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
+#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
+#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) << 18) & 0xc0000)
+#define BF_PWM_PERIODn_INACTIVE_STATE_V(v)  ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000)
+#define BP_PWM_PERIODn_ACTIVE_STATE         16
+#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
+#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
+#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
+#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
+#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) << 16) & 0x30000)
+#define BF_PWM_PERIODn_ACTIVE_STATE_V(v)    ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000)
+#define BP_PWM_PERIODn_PERIOD               0
+#define BM_PWM_PERIODn_PERIOD               0xffff
+#define BF_PWM_PERIODn_PERIOD(v)            (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_PWM_VERSION
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_PWM_VERSION          (*(volatile unsigned long *)(REGS_PWM_BASE + 0xb0))
+#define BP_PWM_VERSION_MAJOR    24
+#define BM_PWM_VERSION_MAJOR    0xff000000
+#define BF_PWM_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_PWM_VERSION_MINOR    16
+#define BM_PWM_VERSION_MINOR    0xff0000
+#define BF_PWM_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_PWM_VERSION_STEP     0
+#define BM_PWM_VERSION_STEP     0xffff
+#define BF_PWM_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-pxp.h b/firmware/target/arm/imx233/regs/imx233/regs-pxp.h
new file mode 100644
index 0000000000..839998a2d1
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-pxp.h
@@ -0,0 +1,612 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__PXP__H__
+#define __HEADERGEN__IMX233__PXP__H__
+
+#define REGS_PXP_BASE (0x8002a000)
+
+#define REGS_PXP_VERSION "3.2.0"
+
+/**
+ * Register: HW_PXP_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_PXP_CTRL                                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x0))
+#define HW_PXP_CTRL_SET                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x4))
+#define HW_PXP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0x8))
+#define HW_PXP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x0 + 0xc))
+#define BP_PXP_CTRL_SFTRST                          31
+#define BM_PXP_CTRL_SFTRST                          0x80000000
+#define BF_PXP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
+#define BP_PXP_CTRL_CLKGATE                         30
+#define BM_PXP_CTRL_CLKGATE                         0x40000000
+#define BF_PXP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
+#define BP_PXP_CTRL_RSVD2                           28
+#define BM_PXP_CTRL_RSVD2                           0x30000000
+#define BF_PXP_CTRL_RSVD2(v)                        (((v) << 28) & 0x30000000)
+#define BP_PXP_CTRL_INTERLACED_OUTPUT               26
+#define BM_PXP_CTRL_INTERLACED_OUTPUT               0xc000000
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE  0x0
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0       0x1
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1       0x2
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED   0x3
+#define BF_PXP_CTRL_INTERLACED_OUTPUT(v)            (((v) << 26) & 0xc000000)
+#define BF_PXP_CTRL_INTERLACED_OUTPUT_V(v)          ((BV_PXP_CTRL_INTERLACED_OUTPUT__##v << 26) & 0xc000000)
+#define BP_PXP_CTRL_INTERLACED_INPUT                24
+#define BM_PXP_CTRL_INTERLACED_INPUT                0x3000000
+#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE   0x0
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0        0x2
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1        0x3
+#define BF_PXP_CTRL_INTERLACED_INPUT(v)             (((v) << 24) & 0x3000000)
+#define BF_PXP_CTRL_INTERLACED_INPUT_V(v)           ((BV_PXP_CTRL_INTERLACED_INPUT__##v << 24) & 0x3000000)
+#define BP_PXP_CTRL_RSVD1                           23
+#define BM_PXP_CTRL_RSVD1                           0x800000
+#define BF_PXP_CTRL_RSVD1(v)                        (((v) << 23) & 0x800000)
+#define BP_PXP_CTRL_ALPHA_OUTPUT                    22
+#define BM_PXP_CTRL_ALPHA_OUTPUT                    0x400000
+#define BF_PXP_CTRL_ALPHA_OUTPUT(v)                 (((v) << 22) & 0x400000)
+#define BP_PXP_CTRL_IN_PLACE                        21
+#define BM_PXP_CTRL_IN_PLACE                        0x200000
+#define BF_PXP_CTRL_IN_PLACE(v)                     (((v) << 21) & 0x200000)
+#define BP_PXP_CTRL_DELTA                           20
+#define BM_PXP_CTRL_DELTA                           0x100000
+#define BF_PXP_CTRL_DELTA(v)                        (((v) << 20) & 0x100000)
+#define BP_PXP_CTRL_CROP                            19
+#define BM_PXP_CTRL_CROP                            0x80000
+#define BF_PXP_CTRL_CROP(v)                         (((v) << 19) & 0x80000)
+#define BP_PXP_CTRL_SCALE                           18
+#define BM_PXP_CTRL_SCALE                           0x40000
+#define BF_PXP_CTRL_SCALE(v)                        (((v) << 18) & 0x40000)
+#define BP_PXP_CTRL_UPSAMPLE                        17
+#define BM_PXP_CTRL_UPSAMPLE                        0x20000
+#define BF_PXP_CTRL_UPSAMPLE(v)                     (((v) << 17) & 0x20000)
+#define BP_PXP_CTRL_SUBSAMPLE                       16
+#define BM_PXP_CTRL_SUBSAMPLE                       0x10000
+#define BF_PXP_CTRL_SUBSAMPLE(v)                    (((v) << 16) & 0x10000)
+#define BP_PXP_CTRL_S0_FORMAT                       12
+#define BM_PXP_CTRL_S0_FORMAT                       0xf000
+#define BV_PXP_CTRL_S0_FORMAT__RGB888               0x1
+#define BV_PXP_CTRL_S0_FORMAT__RGB565               0x4
+#define BV_PXP_CTRL_S0_FORMAT__RGB555               0x5
+#define BV_PXP_CTRL_S0_FORMAT__YUV422               0x8
+#define BV_PXP_CTRL_S0_FORMAT__YUV420               0x9
+#define BF_PXP_CTRL_S0_FORMAT(v)                    (((v) << 12) & 0xf000)
+#define BF_PXP_CTRL_S0_FORMAT_V(v)                  ((BV_PXP_CTRL_S0_FORMAT__##v << 12) & 0xf000)
+#define BP_PXP_CTRL_VFLIP                           11
+#define BM_PXP_CTRL_VFLIP                           0x800
+#define BF_PXP_CTRL_VFLIP(v)                        (((v) << 11) & 0x800)
+#define BP_PXP_CTRL_HFLIP                           10
+#define BM_PXP_CTRL_HFLIP                           0x400
+#define BF_PXP_CTRL_HFLIP(v)                        (((v) << 10) & 0x400)
+#define BP_PXP_CTRL_ROTATE                          8
+#define BM_PXP_CTRL_ROTATE                          0x300
+#define BV_PXP_CTRL_ROTATE__ROT_0                   0x0
+#define BV_PXP_CTRL_ROTATE__ROT_90                  0x1
+#define BV_PXP_CTRL_ROTATE__ROT_180                 0x2
+#define BV_PXP_CTRL_ROTATE__ROT_270                 0x3
+#define BF_PXP_CTRL_ROTATE(v)                       (((v) << 8) & 0x300)
+#define BF_PXP_CTRL_ROTATE_V(v)                     ((BV_PXP_CTRL_ROTATE__##v << 8) & 0x300)
+#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT               4
+#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT               0xf0
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888     0x0
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888       0x1
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P      0x2
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555     0x3
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565       0x4
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555       0x5
+#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v)            (((v) << 4) & 0xf0)
+#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT_V(v)          ((BV_PXP_CTRL_OUTPUT_RGB_FORMAT__##v << 4) & 0xf0)
+#define BP_PXP_CTRL_RSVD0                           3
+#define BM_PXP_CTRL_RSVD0                           0x8
+#define BF_PXP_CTRL_RSVD0(v)                        (((v) << 3) & 0x8)
+#define BP_PXP_CTRL_ENABLE_LCD_HANDSHAKE            2
+#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE            0x4
+#define BF_PXP_CTRL_ENABLE_LCD_HANDSHAKE(v)         (((v) << 2) & 0x4)
+#define BP_PXP_CTRL_IRQ_ENABLE                      1
+#define BM_PXP_CTRL_IRQ_ENABLE                      0x2
+#define BF_PXP_CTRL_IRQ_ENABLE(v)                   (((v) << 1) & 0x2)
+#define BP_PXP_CTRL_ENABLE                          0
+#define BM_PXP_CTRL_ENABLE                          0x1
+#define BF_PXP_CTRL_ENABLE(v)                       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PXP_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_PXP_STAT                     (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x0))
+#define HW_PXP_STAT_SET                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x4))
+#define HW_PXP_STAT_CLR                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0x8))
+#define HW_PXP_STAT_TOG                 (*(volatile unsigned long *)(REGS_PXP_BASE + 0x10 + 0xc))
+#define BP_PXP_STAT_BLOCKX              24
+#define BM_PXP_STAT_BLOCKX              0xff000000
+#define BF_PXP_STAT_BLOCKX(v)           (((v) << 24) & 0xff000000)
+#define BP_PXP_STAT_BLOCKY              16
+#define BM_PXP_STAT_BLOCKY              0xff0000
+#define BF_PXP_STAT_BLOCKY(v)           (((v) << 16) & 0xff0000)
+#define BP_PXP_STAT_RSVD2               8
+#define BM_PXP_STAT_RSVD2               0xff00
+#define BF_PXP_STAT_RSVD2(v)            (((v) << 8) & 0xff00)
+#define BP_PXP_STAT_AXI_ERROR_ID        4
+#define BM_PXP_STAT_AXI_ERROR_ID        0xf0
+#define BF_PXP_STAT_AXI_ERROR_ID(v)     (((v) << 4) & 0xf0)
+#define BP_PXP_STAT_RSVD1               3
+#define BM_PXP_STAT_RSVD1               0x8
+#define BF_PXP_STAT_RSVD1(v)            (((v) << 3) & 0x8)
+#define BP_PXP_STAT_AXI_READ_ERROR      2
+#define BM_PXP_STAT_AXI_READ_ERROR      0x4
+#define BF_PXP_STAT_AXI_READ_ERROR(v)   (((v) << 2) & 0x4)
+#define BP_PXP_STAT_AXI_WRITE_ERROR     1
+#define BM_PXP_STAT_AXI_WRITE_ERROR     0x2
+#define BF_PXP_STAT_AXI_WRITE_ERROR(v)  (((v) << 1) & 0x2)
+#define BP_PXP_STAT_IRQ                 0
+#define BM_PXP_STAT_IRQ                 0x1
+#define BF_PXP_STAT_IRQ(v)              (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PXP_RGBBUF
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_PXP_RGBBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x20))
+#define BP_PXP_RGBBUF_ADDR      0
+#define BM_PXP_RGBBUF_ADDR      0xffffffff
+#define BF_PXP_RGBBUF_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_RGBBUF2
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_PXP_RGBBUF2          (*(volatile unsigned long *)(REGS_PXP_BASE + 0x30))
+#define BP_PXP_RGBBUF2_ADDR     0
+#define BM_PXP_RGBBUF2_ADDR     0xffffffff
+#define BF_PXP_RGBBUF2_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_RGBSIZE
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_PXP_RGBSIZE              (*(volatile unsigned long *)(REGS_PXP_BASE + 0x40))
+#define BP_PXP_RGBSIZE_ALPHA        24
+#define BM_PXP_RGBSIZE_ALPHA        0xff000000
+#define BF_PXP_RGBSIZE_ALPHA(v)     (((v) << 24) & 0xff000000)
+#define BP_PXP_RGBSIZE_WIDTH        12
+#define BM_PXP_RGBSIZE_WIDTH        0xfff000
+#define BF_PXP_RGBSIZE_WIDTH(v)     (((v) << 12) & 0xfff000)
+#define BP_PXP_RGBSIZE_HEIGHT       0
+#define BM_PXP_RGBSIZE_HEIGHT       0xfff
+#define BF_PXP_RGBSIZE_HEIGHT(v)    (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_PXP_S0BUF
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_PXP_S0BUF            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x50))
+#define BP_PXP_S0BUF_ADDR       0
+#define BM_PXP_S0BUF_ADDR       0xffffffff
+#define BF_PXP_S0BUF_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_S0UBUF
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_PXP_S0UBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x60))
+#define BP_PXP_S0UBUF_ADDR      0
+#define BM_PXP_S0UBUF_ADDR      0xffffffff
+#define BF_PXP_S0UBUF_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_S0VBUF
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_PXP_S0VBUF           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x70))
+#define BP_PXP_S0VBUF_ADDR      0
+#define BM_PXP_S0VBUF_ADDR      0xffffffff
+#define BF_PXP_S0VBUF_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_S0PARAM
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_PXP_S0PARAM              (*(volatile unsigned long *)(REGS_PXP_BASE + 0x80))
+#define BP_PXP_S0PARAM_XBASE        24
+#define BM_PXP_S0PARAM_XBASE        0xff000000
+#define BF_PXP_S0PARAM_XBASE(v)     (((v) << 24) & 0xff000000)
+#define BP_PXP_S0PARAM_YBASE        16
+#define BM_PXP_S0PARAM_YBASE        0xff0000
+#define BF_PXP_S0PARAM_YBASE(v)     (((v) << 16) & 0xff0000)
+#define BP_PXP_S0PARAM_WIDTH        8
+#define BM_PXP_S0PARAM_WIDTH        0xff00
+#define BF_PXP_S0PARAM_WIDTH(v)     (((v) << 8) & 0xff00)
+#define BP_PXP_S0PARAM_HEIGHT       0
+#define BM_PXP_S0PARAM_HEIGHT       0xff
+#define BF_PXP_S0PARAM_HEIGHT(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_PXP_S0BACKGROUND
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_PXP_S0BACKGROUND             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x90))
+#define BP_PXP_S0BACKGROUND_COLOR       0
+#define BM_PXP_S0BACKGROUND_COLOR       0xffffffff
+#define BF_PXP_S0BACKGROUND_COLOR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_S0CROP
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_PXP_S0CROP           (*(volatile unsigned long *)(REGS_PXP_BASE + 0xa0))
+#define BP_PXP_S0CROP_XBASE     24
+#define BM_PXP_S0CROP_XBASE     0xff000000
+#define BF_PXP_S0CROP_XBASE(v)  (((v) << 24) & 0xff000000)
+#define BP_PXP_S0CROP_YBASE     16
+#define BM_PXP_S0CROP_YBASE     0xff0000
+#define BF_PXP_S0CROP_YBASE(v)  (((v) << 16) & 0xff0000)
+#define BP_PXP_S0CROP_WIDTH     8
+#define BM_PXP_S0CROP_WIDTH     0xff00
+#define BF_PXP_S0CROP_WIDTH(v)  (((v) << 8) & 0xff00)
+#define BP_PXP_S0CROP_HEIGHT    0
+#define BM_PXP_S0CROP_HEIGHT    0xff
+#define BF_PXP_S0CROP_HEIGHT(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_PXP_S0SCALE
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_PXP_S0SCALE              (*(volatile unsigned long *)(REGS_PXP_BASE + 0xb0))
+#define BP_PXP_S0SCALE_RSVD2        30
+#define BM_PXP_S0SCALE_RSVD2        0xc0000000
+#define BF_PXP_S0SCALE_RSVD2(v)     (((v) << 30) & 0xc0000000)
+#define BP_PXP_S0SCALE_YSCALE       16
+#define BM_PXP_S0SCALE_YSCALE       0x3fff0000
+#define BF_PXP_S0SCALE_YSCALE(v)    (((v) << 16) & 0x3fff0000)
+#define BP_PXP_S0SCALE_RSVD1        14
+#define BM_PXP_S0SCALE_RSVD1        0xc000
+#define BF_PXP_S0SCALE_RSVD1(v)     (((v) << 14) & 0xc000)
+#define BP_PXP_S0SCALE_XSCALE       0
+#define BM_PXP_S0SCALE_XSCALE       0x3fff
+#define BF_PXP_S0SCALE_XSCALE(v)    (((v) << 0) & 0x3fff)
+
+/**
+ * Register: HW_PXP_S0OFFSET
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_PXP_S0OFFSET             (*(volatile unsigned long *)(REGS_PXP_BASE + 0xc0))
+#define BP_PXP_S0OFFSET_RSVD2       28
+#define BM_PXP_S0OFFSET_RSVD2       0xf0000000
+#define BF_PXP_S0OFFSET_RSVD2(v)    (((v) << 28) & 0xf0000000)
+#define BP_PXP_S0OFFSET_YOFFSET     16
+#define BM_PXP_S0OFFSET_YOFFSET     0xfff0000
+#define BF_PXP_S0OFFSET_YOFFSET(v)  (((v) << 16) & 0xfff0000)
+#define BP_PXP_S0OFFSET_RSVD1       12
+#define BM_PXP_S0OFFSET_RSVD1       0xf000
+#define BF_PXP_S0OFFSET_RSVD1(v)    (((v) << 12) & 0xf000)
+#define BP_PXP_S0OFFSET_XOFFSET     0
+#define BM_PXP_S0OFFSET_XOFFSET     0xfff
+#define BF_PXP_S0OFFSET_XOFFSET(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_PXP_CSCCOEFF0
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_PXP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_PXP_BASE + 0xd0))
+#define BP_PXP_CSCCOEFF0_YCBCR_MODE     31
+#define BM_PXP_CSCCOEFF0_YCBCR_MODE     0x80000000
+#define BF_PXP_CSCCOEFF0_YCBCR_MODE(v)  (((v) << 31) & 0x80000000)
+#define BP_PXP_CSCCOEFF0_RSVD1          29
+#define BM_PXP_CSCCOEFF0_RSVD1          0x60000000
+#define BF_PXP_CSCCOEFF0_RSVD1(v)       (((v) << 29) & 0x60000000)
+#define BP_PXP_CSCCOEFF0_C0             18
+#define BM_PXP_CSCCOEFF0_C0             0x1ffc0000
+#define BF_PXP_CSCCOEFF0_C0(v)          (((v) << 18) & 0x1ffc0000)
+#define BP_PXP_CSCCOEFF0_UV_OFFSET      9
+#define BM_PXP_CSCCOEFF0_UV_OFFSET      0x3fe00
+#define BF_PXP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 9) & 0x3fe00)
+#define BP_PXP_CSCCOEFF0_Y_OFFSET       0
+#define BM_PXP_CSCCOEFF0_Y_OFFSET       0x1ff
+#define BF_PXP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_PXP_CSCCOEFF1
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_PXP_CSCCOEFF1            (*(volatile unsigned long *)(REGS_PXP_BASE + 0xe0))
+#define BP_PXP_CSCCOEFF1_RSVD1      27
+#define BM_PXP_CSCCOEFF1_RSVD1      0xf8000000
+#define BF_PXP_CSCCOEFF1_RSVD1(v)   (((v) << 27) & 0xf8000000)
+#define BP_PXP_CSCCOEFF1_C1         16
+#define BM_PXP_CSCCOEFF1_C1         0x7ff0000
+#define BF_PXP_CSCCOEFF1_C1(v)      (((v) << 16) & 0x7ff0000)
+#define BP_PXP_CSCCOEFF1_RSVD0      11
+#define BM_PXP_CSCCOEFF1_RSVD0      0xf800
+#define BF_PXP_CSCCOEFF1_RSVD0(v)   (((v) << 11) & 0xf800)
+#define BP_PXP_CSCCOEFF1_C4         0
+#define BM_PXP_CSCCOEFF1_C4         0x7ff
+#define BF_PXP_CSCCOEFF1_C4(v)      (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_PXP_CSCCOEFF2
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_PXP_CSCCOEFF2            (*(volatile unsigned long *)(REGS_PXP_BASE + 0xf0))
+#define BP_PXP_CSCCOEFF2_RSVD1      27
+#define BM_PXP_CSCCOEFF2_RSVD1      0xf8000000
+#define BF_PXP_CSCCOEFF2_RSVD1(v)   (((v) << 27) & 0xf8000000)
+#define BP_PXP_CSCCOEFF2_C2         16
+#define BM_PXP_CSCCOEFF2_C2         0x7ff0000
+#define BF_PXP_CSCCOEFF2_C2(v)      (((v) << 16) & 0x7ff0000)
+#define BP_PXP_CSCCOEFF2_RSVD0      11
+#define BM_PXP_CSCCOEFF2_RSVD0      0xf800
+#define BF_PXP_CSCCOEFF2_RSVD0(v)   (((v) << 11) & 0xf800)
+#define BP_PXP_CSCCOEFF2_C3         0
+#define BM_PXP_CSCCOEFF2_C3         0x7ff
+#define BF_PXP_CSCCOEFF2_C3(v)      (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_PXP_NEXT
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_PXP_NEXT             (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x0))
+#define HW_PXP_NEXT_SET         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x4))
+#define HW_PXP_NEXT_CLR         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0x8))
+#define HW_PXP_NEXT_TOG         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x100 + 0xc))
+#define BP_PXP_NEXT_POINTER     2
+#define BM_PXP_NEXT_POINTER     0xfffffffc
+#define BF_PXP_NEXT_POINTER(v)  (((v) << 2) & 0xfffffffc)
+#define BP_PXP_NEXT_RSVD        1
+#define BM_PXP_NEXT_RSVD        0x2
+#define BF_PXP_NEXT_RSVD(v)     (((v) << 1) & 0x2)
+#define BP_PXP_NEXT_ENABLED     0
+#define BM_PXP_NEXT_ENABLED     0x1
+#define BF_PXP_NEXT_ENABLED(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PXP_PAGETABLE
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_PXP_PAGETABLE            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x170))
+#define BP_PXP_PAGETABLE_BASE       14
+#define BM_PXP_PAGETABLE_BASE       0xffffc000
+#define BF_PXP_PAGETABLE_BASE(v)    (((v) << 14) & 0xffffc000)
+#define BP_PXP_PAGETABLE_RSVD1      2
+#define BM_PXP_PAGETABLE_RSVD1      0x3ffc
+#define BF_PXP_PAGETABLE_RSVD1(v)   (((v) << 2) & 0x3ffc)
+#define BP_PXP_PAGETABLE_FLUSH      1
+#define BM_PXP_PAGETABLE_FLUSH      0x2
+#define BF_PXP_PAGETABLE_FLUSH(v)   (((v) << 1) & 0x2)
+#define BP_PXP_PAGETABLE_ENABLE     0
+#define BM_PXP_PAGETABLE_ENABLE     0x1
+#define BF_PXP_PAGETABLE_ENABLE(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PXP_S0COLORKEYLOW
+ * Address: 0x180
+ * SCT: no
+*/
+#define HW_PXP_S0COLORKEYLOW            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x180))
+#define BP_PXP_S0COLORKEYLOW_RSVD1      24
+#define BM_PXP_S0COLORKEYLOW_RSVD1      0xff000000
+#define BF_PXP_S0COLORKEYLOW_RSVD1(v)   (((v) << 24) & 0xff000000)
+#define BP_PXP_S0COLORKEYLOW_PIXEL      0
+#define BM_PXP_S0COLORKEYLOW_PIXEL      0xffffff
+#define BF_PXP_S0COLORKEYLOW_PIXEL(v)   (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_PXP_S0COLORKEYHIGH
+ * Address: 0x190
+ * SCT: no
+*/
+#define HW_PXP_S0COLORKEYHIGH           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x190))
+#define BP_PXP_S0COLORKEYHIGH_RSVD1     24
+#define BM_PXP_S0COLORKEYHIGH_RSVD1     0xff000000
+#define BF_PXP_S0COLORKEYHIGH_RSVD1(v)  (((v) << 24) & 0xff000000)
+#define BP_PXP_S0COLORKEYHIGH_PIXEL     0
+#define BM_PXP_S0COLORKEYHIGH_PIXEL     0xffffff
+#define BF_PXP_S0COLORKEYHIGH_PIXEL(v)  (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_PXP_OLCOLORKEYLOW
+ * Address: 0x1a0
+ * SCT: no
+*/
+#define HW_PXP_OLCOLORKEYLOW            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1a0))
+#define BP_PXP_OLCOLORKEYLOW_RSVD1      24
+#define BM_PXP_OLCOLORKEYLOW_RSVD1      0xff000000
+#define BF_PXP_OLCOLORKEYLOW_RSVD1(v)   (((v) << 24) & 0xff000000)
+#define BP_PXP_OLCOLORKEYLOW_PIXEL      0
+#define BM_PXP_OLCOLORKEYLOW_PIXEL      0xffffff
+#define BF_PXP_OLCOLORKEYLOW_PIXEL(v)   (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_PXP_OLCOLORKEYHIGH
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_PXP_OLCOLORKEYHIGH           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1b0))
+#define BP_PXP_OLCOLORKEYHIGH_RSVD1     24
+#define BM_PXP_OLCOLORKEYHIGH_RSVD1     0xff000000
+#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v)  (((v) << 24) & 0xff000000)
+#define BP_PXP_OLCOLORKEYHIGH_PIXEL     0
+#define BM_PXP_OLCOLORKEYHIGH_PIXEL     0xffffff
+#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v)  (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_PXP_DEBUGCTRL
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_PXP_DEBUGCTRL                    (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1d0))
+#define BP_PXP_DEBUGCTRL_RSVD               9
+#define BM_PXP_DEBUGCTRL_RSVD               0xfffffe00
+#define BF_PXP_DEBUGCTRL_RSVD(v)            (((v) << 9) & 0xfffffe00)
+#define BP_PXP_DEBUGCTRL_RESET_TLB_STATS    8
+#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS    0x100
+#define BF_PXP_DEBUGCTRL_RESET_TLB_STATS(v) (((v) << 8) & 0x100)
+#define BP_PXP_DEBUGCTRL_SELECT             0
+#define BM_PXP_DEBUGCTRL_SELECT             0xff
+#define BV_PXP_DEBUGCTRL_SELECT__NONE       0x0
+#define BV_PXP_DEBUGCTRL_SELECT__CTRL       0x1
+#define BV_PXP_DEBUGCTRL_SELECT__S0REGS     0x2
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAX      0x3
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAY      0x4
+#define BV_PXP_DEBUGCTRL_SELECT__PXBUF      0x5
+#define BV_PXP_DEBUGCTRL_SELECT__ROTATION   0x6
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0    0x7
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1    0x8
+#define BF_PXP_DEBUGCTRL_SELECT(v)          (((v) << 0) & 0xff)
+#define BF_PXP_DEBUGCTRL_SELECT_V(v)        ((BV_PXP_DEBUGCTRL_SELECT__##v << 0) & 0xff)
+
+/**
+ * Register: HW_PXP_DEBUG
+ * Address: 0x1e0
+ * SCT: no
+*/
+#define HW_PXP_DEBUG            (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1e0))
+#define BP_PXP_DEBUG_DATA       0
+#define BM_PXP_DEBUG_DATA       0xffffffff
+#define BF_PXP_DEBUG_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_VERSION
+ * Address: 0x1f0
+ * SCT: no
+*/
+#define HW_PXP_VERSION          (*(volatile unsigned long *)(REGS_PXP_BASE + 0x1f0))
+#define BP_PXP_VERSION_MAJOR    24
+#define BM_PXP_VERSION_MAJOR    0xff000000
+#define BF_PXP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_PXP_VERSION_MINOR    16
+#define BM_PXP_VERSION_MINOR    0xff0000
+#define BF_PXP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_PXP_VERSION_STEP     0
+#define BM_PXP_VERSION_STEP     0xffff
+#define BF_PXP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_PXP_OLn
+ * Address: 0x200+n*0x40
+ * SCT: no
+*/
+#define HW_PXP_OLn(n)       (*(volatile unsigned long *)(REGS_PXP_BASE + 0x200+(n)*0x40))
+#define BP_PXP_OLn_ADDR     0
+#define BM_PXP_OLn_ADDR     0xffffffff
+#define BF_PXP_OLn_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PXP_OLnSIZE
+ * Address: 0x210+n*0x40
+ * SCT: no
+*/
+#define HW_PXP_OLnSIZE(n)           (*(volatile unsigned long *)(REGS_PXP_BASE + 0x210+(n)*0x40))
+#define BP_PXP_OLnSIZE_XBASE        24
+#define BM_PXP_OLnSIZE_XBASE        0xff000000
+#define BF_PXP_OLnSIZE_XBASE(v)     (((v) << 24) & 0xff000000)
+#define BP_PXP_OLnSIZE_YBASE        16
+#define BM_PXP_OLnSIZE_YBASE        0xff0000
+#define BF_PXP_OLnSIZE_YBASE(v)     (((v) << 16) & 0xff0000)
+#define BP_PXP_OLnSIZE_WIDTH        8
+#define BM_PXP_OLnSIZE_WIDTH        0xff00
+#define BF_PXP_OLnSIZE_WIDTH(v)     (((v) << 8) & 0xff00)
+#define BP_PXP_OLnSIZE_HEIGHT       0
+#define BM_PXP_OLnSIZE_HEIGHT       0xff
+#define BF_PXP_OLnSIZE_HEIGHT(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_PXP_OLnPARAM
+ * Address: 0x220+n*0x40
+ * SCT: no
+*/
+#define HW_PXP_OLnPARAM(n)                      (*(volatile unsigned long *)(REGS_PXP_BASE + 0x220+(n)*0x40))
+#define BP_PXP_OLnPARAM_RSVD1                   20
+#define BM_PXP_OLnPARAM_RSVD1                   0xfff00000
+#define BF_PXP_OLnPARAM_RSVD1(v)                (((v) << 20) & 0xfff00000)
+#define BP_PXP_OLnPARAM_ROP                     16
+#define BM_PXP_OLnPARAM_ROP                     0xf0000
+#define BV_PXP_OLnPARAM_ROP__MASKOL             0x0
+#define BV_PXP_OLnPARAM_ROP__MASKNOTOL          0x1
+#define BV_PXP_OLnPARAM_ROP__MASKOLNOT          0x2
+#define BV_PXP_OLnPARAM_ROP__MERGEOL            0x3
+#define BV_PXP_OLnPARAM_ROP__MERGENOTOL         0x4
+#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT         0x5
+#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL          0x6
+#define BV_PXP_OLnPARAM_ROP__NOT                0x7
+#define BV_PXP_OLnPARAM_ROP__NOTMASKOL          0x8
+#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL         0x9
+#define BV_PXP_OLnPARAM_ROP__XOROL              0xa
+#define BV_PXP_OLnPARAM_ROP__NOTXOROL           0xb
+#define BF_PXP_OLnPARAM_ROP(v)                  (((v) << 16) & 0xf0000)
+#define BF_PXP_OLnPARAM_ROP_V(v)                ((BV_PXP_OLnPARAM_ROP__##v << 16) & 0xf0000)
+#define BP_PXP_OLnPARAM_ALPHA                   8
+#define BM_PXP_OLnPARAM_ALPHA                   0xff00
+#define BF_PXP_OLnPARAM_ALPHA(v)                (((v) << 8) & 0xff00)
+#define BP_PXP_OLnPARAM_FORMAT                  4
+#define BM_PXP_OLnPARAM_FORMAT                  0xf0
+#define BV_PXP_OLnPARAM_FORMAT__ARGB8888        0x0
+#define BV_PXP_OLnPARAM_FORMAT__RGB888          0x1
+#define BV_PXP_OLnPARAM_FORMAT__ARGB1555        0x3
+#define BV_PXP_OLnPARAM_FORMAT__RGB565          0x4
+#define BV_PXP_OLnPARAM_FORMAT__RGB555          0x5
+#define BF_PXP_OLnPARAM_FORMAT(v)               (((v) << 4) & 0xf0)
+#define BF_PXP_OLnPARAM_FORMAT_V(v)             ((BV_PXP_OLnPARAM_FORMAT__##v << 4) & 0xf0)
+#define BP_PXP_OLnPARAM_ENABLE_COLORKEY         3
+#define BM_PXP_OLnPARAM_ENABLE_COLORKEY         0x8
+#define BF_PXP_OLnPARAM_ENABLE_COLORKEY(v)      (((v) << 3) & 0x8)
+#define BP_PXP_OLnPARAM_ALPHA_CNTL              1
+#define BM_PXP_OLnPARAM_ALPHA_CNTL              0x6
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded    0x0
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override    0x1
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply    0x2
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs        0x3
+#define BF_PXP_OLnPARAM_ALPHA_CNTL(v)           (((v) << 1) & 0x6)
+#define BF_PXP_OLnPARAM_ALPHA_CNTL_V(v)         ((BV_PXP_OLnPARAM_ALPHA_CNTL__##v << 1) & 0x6)
+#define BP_PXP_OLnPARAM_ENABLE                  0
+#define BM_PXP_OLnPARAM_ENABLE                  0x1
+#define BF_PXP_OLnPARAM_ENABLE(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PXP_OLnPARAM2
+ * Address: 0x230+n*0x40
+ * SCT: no
+*/
+#define HW_PXP_OLnPARAM2(n)         (*(volatile unsigned long *)(REGS_PXP_BASE + 0x230+(n)*0x40))
+#define BP_PXP_OLnPARAM2_RSVD       0
+#define BM_PXP_OLnPARAM2_RSVD       0xffffffff
+#define BF_PXP_OLnPARAM2_RSVD(v)    (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__IMX233__PXP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-rtc.h b/firmware/target/arm/imx233/regs/imx233/regs-rtc.h
new file mode 100644
index 0000000000..fbca279a54
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-rtc.h
@@ -0,0 +1,318 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__RTC__H__
+#define __HEADERGEN__IMX233__RTC__H__
+
+#define REGS_RTC_BASE (0x8005c000)
+
+#define REGS_RTC_VERSION "3.2.0"
+
+/**
+ * Register: HW_RTC_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_RTC_CTRL                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0))
+#define HW_RTC_CTRL_SET                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4))
+#define HW_RTC_CTRL_CLR                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8))
+#define HW_RTC_CTRL_TOG                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc))
+#define BP_RTC_CTRL_SFTRST                  31
+#define BM_RTC_CTRL_SFTRST                  0x80000000
+#define BF_RTC_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BP_RTC_CTRL_CLKGATE                 30
+#define BM_RTC_CTRL_CLKGATE                 0x40000000
+#define BF_RTC_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_RTC_CTRL_RSVD0                   7
+#define BM_RTC_CTRL_RSVD0                   0x3fffff80
+#define BF_RTC_CTRL_RSVD0(v)                (((v) << 7) & 0x3fffff80)
+#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG    6
+#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG    0x40
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40)
+#define BP_RTC_CTRL_FORCE_UPDATE            5
+#define BM_RTC_CTRL_FORCE_UPDATE            0x20
+#define BF_RTC_CTRL_FORCE_UPDATE(v)         (((v) << 5) & 0x20)
+#define BP_RTC_CTRL_WATCHDOGEN              4
+#define BM_RTC_CTRL_WATCHDOGEN              0x10
+#define BF_RTC_CTRL_WATCHDOGEN(v)           (((v) << 4) & 0x10)
+#define BP_RTC_CTRL_ONEMSEC_IRQ             3
+#define BM_RTC_CTRL_ONEMSEC_IRQ             0x8
+#define BF_RTC_CTRL_ONEMSEC_IRQ(v)          (((v) << 3) & 0x8)
+#define BP_RTC_CTRL_ALARM_IRQ               2
+#define BM_RTC_CTRL_ALARM_IRQ               0x4
+#define BF_RTC_CTRL_ALARM_IRQ(v)            (((v) << 2) & 0x4)
+#define BP_RTC_CTRL_ONEMSEC_IRQ_EN          1
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN          0x2
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)       (((v) << 1) & 0x2)
+#define BP_RTC_CTRL_ALARM_IRQ_EN            0
+#define BM_RTC_CTRL_ALARM_IRQ_EN            0x1
+#define BF_RTC_CTRL_ALARM_IRQ_EN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_RTC_STAT                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x0))
+#define HW_RTC_STAT_SET                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x4))
+#define HW_RTC_STAT_CLR                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0x8))
+#define HW_RTC_STAT_TOG                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10 + 0xc))
+#define BP_RTC_STAT_RTC_PRESENT             31
+#define BM_RTC_STAT_RTC_PRESENT             0x80000000
+#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) << 31) & 0x80000000)
+#define BP_RTC_STAT_ALARM_PRESENT           30
+#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
+#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) << 30) & 0x40000000)
+#define BP_RTC_STAT_WATCHDOG_PRESENT        29
+#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
+#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) << 29) & 0x20000000)
+#define BP_RTC_STAT_XTAL32000_PRESENT       28
+#define BM_RTC_STAT_XTAL32000_PRESENT       0x10000000
+#define BF_RTC_STAT_XTAL32000_PRESENT(v)    (((v) << 28) & 0x10000000)
+#define BP_RTC_STAT_XTAL32768_PRESENT       27
+#define BM_RTC_STAT_XTAL32768_PRESENT       0x8000000
+#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) << 27) & 0x8000000)
+#define BP_RTC_STAT_RSVD1                   24
+#define BM_RTC_STAT_RSVD1                   0x7000000
+#define BF_RTC_STAT_RSVD1(v)                (((v) << 24) & 0x7000000)
+#define BP_RTC_STAT_STALE_REGS              16
+#define BM_RTC_STAT_STALE_REGS              0xff0000
+#define BF_RTC_STAT_STALE_REGS(v)           (((v) << 16) & 0xff0000)
+#define BP_RTC_STAT_NEW_REGS                8
+#define BM_RTC_STAT_NEW_REGS                0xff00
+#define BF_RTC_STAT_NEW_REGS(v)             (((v) << 8) & 0xff00)
+#define BP_RTC_STAT_RSVD0                   0
+#define BM_RTC_STAT_RSVD0                   0xff
+#define BF_RTC_STAT_RSVD0(v)                (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_RTC_MILLISECONDS
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_RTC_MILLISECONDS             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0))
+#define HW_RTC_MILLISECONDS_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4))
+#define HW_RTC_MILLISECONDS_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8))
+#define HW_RTC_MILLISECONDS_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc))
+#define BP_RTC_MILLISECONDS_COUNT       0
+#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
+#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_SECONDS
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_RTC_SECONDS          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0))
+#define HW_RTC_SECONDS_SET      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4))
+#define HW_RTC_SECONDS_CLR      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8))
+#define HW_RTC_SECONDS_TOG      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc))
+#define BP_RTC_SECONDS_COUNT    0
+#define BM_RTC_SECONDS_COUNT    0xffffffff
+#define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_ALARM
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_RTC_ALARM            (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0))
+#define HW_RTC_ALARM_SET        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4))
+#define HW_RTC_ALARM_CLR        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8))
+#define HW_RTC_ALARM_TOG        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc))
+#define BP_RTC_ALARM_VALUE      0
+#define BM_RTC_ALARM_VALUE      0xffffffff
+#define BF_RTC_ALARM_VALUE(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_WATCHDOG
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_RTC_WATCHDOG             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0))
+#define HW_RTC_WATCHDOG_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4))
+#define HW_RTC_WATCHDOG_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8))
+#define HW_RTC_WATCHDOG_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc))
+#define BP_RTC_WATCHDOG_COUNT       0
+#define BM_RTC_WATCHDOG_COUNT       0xffffffff
+#define BF_RTC_WATCHDOG_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT0
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT0                      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0))
+#define HW_RTC_PERSISTENT0_SET                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4))
+#define HW_RTC_PERSISTENT0_CLR                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8))
+#define HW_RTC_PERSISTENT0_TOG                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc))
+#define BP_RTC_PERSISTENT0_SPARE_ANALOG         18
+#define BM_RTC_PERSISTENT0_SPARE_ANALOG         0xfffc0000
+#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v)      (((v) << 18) & 0xfffc0000)
+#define BP_RTC_PERSISTENT0_AUTO_RESTART         17
+#define BM_RTC_PERSISTENT0_AUTO_RESTART         0x20000
+#define BF_RTC_PERSISTENT0_AUTO_RESTART(v)      (((v) << 17) & 0x20000)
+#define BP_RTC_PERSISTENT0_DISABLE_PSWITCH      16
+#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH      0x10000
+#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v)   (((v) << 16) & 0x10000)
+#define BP_RTC_PERSISTENT0_LOWERBIAS            14
+#define BM_RTC_PERSISTENT0_LOWERBIAS            0xc000
+#define BF_RTC_PERSISTENT0_LOWERBIAS(v)         (((v) << 14) & 0xc000)
+#define BP_RTC_PERSISTENT0_DISABLE_XTALOK       13
+#define BM_RTC_PERSISTENT0_DISABLE_XTALOK       0x2000
+#define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v)    (((v) << 13) & 0x2000)
+#define BP_RTC_PERSISTENT0_MSEC_RES             8
+#define BM_RTC_PERSISTENT0_MSEC_RES             0x1f00
+#define BF_RTC_PERSISTENT0_MSEC_RES(v)          (((v) << 8) & 0x1f00)
+#define BP_RTC_PERSISTENT0_ALARM_WAKE           7
+#define BM_RTC_PERSISTENT0_ALARM_WAKE           0x80
+#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)        (((v) << 7) & 0x80)
+#define BP_RTC_PERSISTENT0_XTAL32_FREQ          6
+#define BM_RTC_PERSISTENT0_XTAL32_FREQ          0x40
+#define BF_RTC_PERSISTENT0_XTAL32_FREQ(v)       (((v) << 6) & 0x40)
+#define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      5
+#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      0x20
+#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)   (((v) << 5) & 0x20)
+#define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      4
+#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      0x10
+#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)   (((v) << 4) & 0x10)
+#define BP_RTC_PERSISTENT0_LCK_SECS             3
+#define BM_RTC_PERSISTENT0_LCK_SECS             0x8
+#define BF_RTC_PERSISTENT0_LCK_SECS(v)          (((v) << 3) & 0x8)
+#define BP_RTC_PERSISTENT0_ALARM_EN             2
+#define BM_RTC_PERSISTENT0_ALARM_EN             0x4
+#define BF_RTC_PERSISTENT0_ALARM_EN(v)          (((v) << 2) & 0x4)
+#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN        1
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN        0x2
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)     (((v) << 1) & 0x2)
+#define BP_RTC_PERSISTENT0_CLOCKSOURCE          0
+#define BM_RTC_PERSISTENT0_CLOCKSOURCE          0x1
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_PERSISTENT1
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT1                                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0))
+#define HW_RTC_PERSISTENT1_SET                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4))
+#define HW_RTC_PERSISTENT1_CLR                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8))
+#define HW_RTC_PERSISTENT1_TOG                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc))
+#define BP_RTC_PERSISTENT1_GENERAL                          0
+#define BM_RTC_PERSISTENT1_GENERAL                          0xffffffff
+#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE   0x1000
+#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE    0x800
+#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK          0x400
+#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE      0x200
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT             0x100
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT        0x80
+#define BF_RTC_PERSISTENT1_GENERAL(v)                       (((v) << 0) & 0xffffffff)
+#define BF_RTC_PERSISTENT1_GENERAL_V(v)                     ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT2
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT2              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0))
+#define HW_RTC_PERSISTENT2_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4))
+#define HW_RTC_PERSISTENT2_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8))
+#define HW_RTC_PERSISTENT2_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc))
+#define BP_RTC_PERSISTENT2_GENERAL      0
+#define BM_RTC_PERSISTENT2_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT2_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT3
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT3              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0))
+#define HW_RTC_PERSISTENT3_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4))
+#define HW_RTC_PERSISTENT3_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8))
+#define HW_RTC_PERSISTENT3_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc))
+#define BP_RTC_PERSISTENT3_GENERAL      0
+#define BM_RTC_PERSISTENT3_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT3_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT4
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT4              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0))
+#define HW_RTC_PERSISTENT4_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4))
+#define HW_RTC_PERSISTENT4_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8))
+#define HW_RTC_PERSISTENT4_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc))
+#define BP_RTC_PERSISTENT4_GENERAL      0
+#define BM_RTC_PERSISTENT4_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT4_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT5
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT5              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0))
+#define HW_RTC_PERSISTENT5_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4))
+#define HW_RTC_PERSISTENT5_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8))
+#define HW_RTC_PERSISTENT5_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc))
+#define BP_RTC_PERSISTENT5_GENERAL      0
+#define BM_RTC_PERSISTENT5_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT5_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_DEBUG
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_RTC_DEBUG                        (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0))
+#define HW_RTC_DEBUG_SET                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4))
+#define HW_RTC_DEBUG_CLR                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8))
+#define HW_RTC_DEBUG_TOG                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc))
+#define BP_RTC_DEBUG_RSVD0                  2
+#define BM_RTC_DEBUG_RSVD0                  0xfffffffc
+#define BF_RTC_DEBUG_RSVD0(v)               (((v) << 2) & 0xfffffffc)
+#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK    1
+#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK    0x2
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2)
+#define BP_RTC_DEBUG_WATCHDOG_RESET         0
+#define BM_RTC_DEBUG_WATCHDOG_RESET         0x1
+#define BF_RTC_DEBUG_WATCHDOG_RESET(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_VERSION
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_RTC_VERSION          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0))
+#define BP_RTC_VERSION_MAJOR    24
+#define BM_RTC_VERSION_MAJOR    0xff000000
+#define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_RTC_VERSION_MINOR    16
+#define BM_RTC_VERSION_MINOR    0xff0000
+#define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_RTC_VERSION_STEP     0
+#define BM_RTC_VERSION_STEP     0xffff
+#define BF_RTC_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-saif.h b/firmware/target/arm/imx233/regs/imx233/regs-saif.h
new file mode 100644
index 0000000000..21171f4c18
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-saif.h
@@ -0,0 +1,169 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__SAIF__H__
+#define __HEADERGEN__IMX233__SAIF__H__
+
+#define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000)
+
+#define REGS_SAIF_VERSION "3.2.0"
+
+/**
+ * Register: HW_SAIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SAIF_CTRL(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0))
+#define HW_SAIF_CTRL_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4))
+#define HW_SAIF_CTRL_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8))
+#define HW_SAIF_CTRL_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc))
+#define BP_SAIF_CTRL_SFTRST                 31
+#define BM_SAIF_CTRL_SFTRST                 0x80000000
+#define BF_SAIF_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_SAIF_CTRL_CLKGATE                30
+#define BM_SAIF_CTRL_CLKGATE                0x40000000
+#define BF_SAIF_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_SAIF_CTRL_BITCLK_MULT_RATE       27
+#define BM_SAIF_CTRL_BITCLK_MULT_RATE       0x38000000
+#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v)    (((v) << 27) & 0x38000000)
+#define BP_SAIF_CTRL_BITCLK_BASE_RATE       26
+#define BM_SAIF_CTRL_BITCLK_BASE_RATE       0x4000000
+#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v)    (((v) << 26) & 0x4000000)
+#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN      25
+#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN      0x2000000
+#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 25) & 0x2000000)
+#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    24
+#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    0x1000000
+#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000)
+#define BP_SAIF_CTRL_RSRVD2                 21
+#define BM_SAIF_CTRL_RSRVD2                 0xe00000
+#define BF_SAIF_CTRL_RSRVD2(v)              (((v) << 21) & 0xe00000)
+#define BP_SAIF_CTRL_DMAWAIT_COUNT          16
+#define BM_SAIF_CTRL_DMAWAIT_COUNT          0x1f0000
+#define BF_SAIF_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
+#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT     14
+#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT     0xc000
+#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v)  (((v) << 14) & 0xc000)
+#define BP_SAIF_CTRL_RSRVD1                 13
+#define BM_SAIF_CTRL_RSRVD1                 0x2000
+#define BF_SAIF_CTRL_RSRVD1(v)              (((v) << 13) & 0x2000)
+#define BP_SAIF_CTRL_BIT_ORDER              12
+#define BM_SAIF_CTRL_BIT_ORDER              0x1000
+#define BF_SAIF_CTRL_BIT_ORDER(v)           (((v) << 12) & 0x1000)
+#define BP_SAIF_CTRL_DELAY                  11
+#define BM_SAIF_CTRL_DELAY                  0x800
+#define BF_SAIF_CTRL_DELAY(v)               (((v) << 11) & 0x800)
+#define BP_SAIF_CTRL_JUSTIFY                10
+#define BM_SAIF_CTRL_JUSTIFY                0x400
+#define BF_SAIF_CTRL_JUSTIFY(v)             (((v) << 10) & 0x400)
+#define BP_SAIF_CTRL_LRCLK_POLARITY         9
+#define BM_SAIF_CTRL_LRCLK_POLARITY         0x200
+#define BF_SAIF_CTRL_LRCLK_POLARITY(v)      (((v) << 9) & 0x200)
+#define BP_SAIF_CTRL_BITCLK_EDGE            8
+#define BM_SAIF_CTRL_BITCLK_EDGE            0x100
+#define BF_SAIF_CTRL_BITCLK_EDGE(v)         (((v) << 8) & 0x100)
+#define BP_SAIF_CTRL_WORD_LENGTH            4
+#define BM_SAIF_CTRL_WORD_LENGTH            0xf0
+#define BF_SAIF_CTRL_WORD_LENGTH(v)         (((v) << 4) & 0xf0)
+#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE    3
+#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE    0x8
+#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8)
+#define BP_SAIF_CTRL_SLAVE_MODE             2
+#define BM_SAIF_CTRL_SLAVE_MODE             0x4
+#define BF_SAIF_CTRL_SLAVE_MODE(v)          (((v) << 2) & 0x4)
+#define BP_SAIF_CTRL_READ_MODE              1
+#define BM_SAIF_CTRL_READ_MODE              0x2
+#define BF_SAIF_CTRL_READ_MODE(v)           (((v) << 1) & 0x2)
+#define BP_SAIF_CTRL_RUN                    0
+#define BM_SAIF_CTRL_RUN                    0x1
+#define BF_SAIF_CTRL_RUN(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SAIF_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SAIF_STAT(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0))
+#define HW_SAIF_STAT_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4))
+#define HW_SAIF_STAT_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8))
+#define HW_SAIF_STAT_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc))
+#define BP_SAIF_STAT_PRESENT                31
+#define BM_SAIF_STAT_PRESENT                0x80000000
+#define BF_SAIF_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
+#define BP_SAIF_STAT_RSRVD2                 17
+#define BM_SAIF_STAT_RSRVD2                 0x7ffe0000
+#define BF_SAIF_STAT_RSRVD2(v)              (((v) << 17) & 0x7ffe0000)
+#define BP_SAIF_STAT_DMA_PREQ               16
+#define BM_SAIF_STAT_DMA_PREQ               0x10000
+#define BF_SAIF_STAT_DMA_PREQ(v)            (((v) << 16) & 0x10000)
+#define BP_SAIF_STAT_RSRVD1                 7
+#define BM_SAIF_STAT_RSRVD1                 0xff80
+#define BF_SAIF_STAT_RSRVD1(v)              (((v) << 7) & 0xff80)
+#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ     6
+#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ     0x40
+#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)  (((v) << 6) & 0x40)
+#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ      5
+#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ      0x20
+#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)   (((v) << 5) & 0x20)
+#define BP_SAIF_STAT_FIFO_SERVICE_IRQ       4
+#define BM_SAIF_STAT_FIFO_SERVICE_IRQ       0x10
+#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v)    (((v) << 4) & 0x10)
+#define BP_SAIF_STAT_RSRVD0                 1
+#define BM_SAIF_STAT_RSRVD0                 0xe
+#define BF_SAIF_STAT_RSRVD0(v)              (((v) << 1) & 0xe)
+#define BP_SAIF_STAT_BUSY                   0
+#define BM_SAIF_STAT_BUSY                   0x1
+#define BF_SAIF_STAT_BUSY(v)                (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SAIF_DATA
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_SAIF_DATA(d)             (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0))
+#define HW_SAIF_DATA_SET(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4))
+#define HW_SAIF_DATA_CLR(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8))
+#define HW_SAIF_DATA_TOG(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc))
+#define BP_SAIF_DATA_PCM_RIGHT      16
+#define BM_SAIF_DATA_PCM_RIGHT      0xffff0000
+#define BF_SAIF_DATA_PCM_RIGHT(v)   (((v) << 16) & 0xffff0000)
+#define BP_SAIF_DATA_PCM_LEFT       0
+#define BM_SAIF_DATA_PCM_LEFT       0xffff
+#define BF_SAIF_DATA_PCM_LEFT(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_SAIF_VERSION
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_SAIF_VERSION(d)          (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30))
+#define BP_SAIF_VERSION_MAJOR       24
+#define BM_SAIF_VERSION_MAJOR       0xff000000
+#define BF_SAIF_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_SAIF_VERSION_MINOR       16
+#define BM_SAIF_VERSION_MINOR       0xff0000
+#define BF_SAIF_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_SAIF_VERSION_STEP        0
+#define BM_SAIF_VERSION_STEP        0xffff
+#define BF_SAIF_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__SAIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-spdif.h b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h
new file mode 100644
index 0000000000..168e88bdb0
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-spdif.h
@@ -0,0 +1,214 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__SPDIF__H__
+#define __HEADERGEN__IMX233__SPDIF__H__
+
+#define REGS_SPDIF_BASE (0x80054000)
+
+#define REGS_SPDIF_VERSION "3.2.0"
+
+/**
+ * Register: HW_SPDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SPDIF_CTRL                       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0))
+#define HW_SPDIF_CTRL_SET                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4))
+#define HW_SPDIF_CTRL_CLR                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8))
+#define HW_SPDIF_CTRL_TOG                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc))
+#define BP_SPDIF_CTRL_SFTRST                31
+#define BM_SPDIF_CTRL_SFTRST                0x80000000
+#define BF_SPDIF_CTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
+#define BP_SPDIF_CTRL_CLKGATE               30
+#define BM_SPDIF_CTRL_CLKGATE               0x40000000
+#define BF_SPDIF_CTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
+#define BP_SPDIF_CTRL_RSRVD1                21
+#define BM_SPDIF_CTRL_RSRVD1                0x3fe00000
+#define BF_SPDIF_CTRL_RSRVD1(v)             (((v) << 21) & 0x3fe00000)
+#define BP_SPDIF_CTRL_DMAWAIT_COUNT         16
+#define BM_SPDIF_CTRL_DMAWAIT_COUNT         0x1f0000
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)      (((v) << 16) & 0x1f0000)
+#define BP_SPDIF_CTRL_RSRVD0                6
+#define BM_SPDIF_CTRL_RSRVD0                0xffc0
+#define BF_SPDIF_CTRL_RSRVD0(v)             (((v) << 6) & 0xffc0)
+#define BP_SPDIF_CTRL_WAIT_END_XFER         5
+#define BM_SPDIF_CTRL_WAIT_END_XFER         0x20
+#define BF_SPDIF_CTRL_WAIT_END_XFER(v)      (((v) << 5) & 0x20)
+#define BP_SPDIF_CTRL_WORD_LENGTH           4
+#define BM_SPDIF_CTRL_WORD_LENGTH           0x10
+#define BF_SPDIF_CTRL_WORD_LENGTH(v)        (((v) << 4) & 0x10)
+#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    3
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    0x8
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
+#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     2
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     0x4
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)  (((v) << 2) & 0x4)
+#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     1
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     0x2
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)  (((v) << 1) & 0x2)
+#define BP_SPDIF_CTRL_RUN                   0
+#define BM_SPDIF_CTRL_RUN                   0x1
+#define BF_SPDIF_CTRL_RUN(v)                (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SPDIF_STAT               (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x0))
+#define HW_SPDIF_STAT_SET           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x4))
+#define HW_SPDIF_STAT_CLR           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0x8))
+#define HW_SPDIF_STAT_TOG           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10 + 0xc))
+#define BP_SPDIF_STAT_PRESENT       31
+#define BM_SPDIF_STAT_PRESENT       0x80000000
+#define BF_SPDIF_STAT_PRESENT(v)    (((v) << 31) & 0x80000000)
+#define BP_SPDIF_STAT_RSRVD1        1
+#define BM_SPDIF_STAT_RSRVD1        0x7ffffffe
+#define BF_SPDIF_STAT_RSRVD1(v)     (((v) << 1) & 0x7ffffffe)
+#define BP_SPDIF_STAT_END_XFER      0
+#define BM_SPDIF_STAT_END_XFER      0x1
+#define BF_SPDIF_STAT_END_XFER(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_FRAMECTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_SPDIF_FRAMECTRL              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0))
+#define HW_SPDIF_FRAMECTRL_SET          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4))
+#define HW_SPDIF_FRAMECTRL_CLR          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8))
+#define HW_SPDIF_FRAMECTRL_TOG          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc))
+#define BP_SPDIF_FRAMECTRL_RSRVD2       18
+#define BM_SPDIF_FRAMECTRL_RSRVD2       0xfffc0000
+#define BF_SPDIF_FRAMECTRL_RSRVD2(v)    (((v) << 18) & 0xfffc0000)
+#define BP_SPDIF_FRAMECTRL_V_CONFIG     17
+#define BM_SPDIF_FRAMECTRL_V_CONFIG     0x20000
+#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)  (((v) << 17) & 0x20000)
+#define BP_SPDIF_FRAMECTRL_AUTO_MUTE    16
+#define BM_SPDIF_FRAMECTRL_AUTO_MUTE    0x10000
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
+#define BP_SPDIF_FRAMECTRL_RSRVD1       15
+#define BM_SPDIF_FRAMECTRL_RSRVD1       0x8000
+#define BF_SPDIF_FRAMECTRL_RSRVD1(v)    (((v) << 15) & 0x8000)
+#define BP_SPDIF_FRAMECTRL_USER_DATA    14
+#define BM_SPDIF_FRAMECTRL_USER_DATA    0x4000
+#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
+#define BP_SPDIF_FRAMECTRL_V            13
+#define BM_SPDIF_FRAMECTRL_V            0x2000
+#define BF_SPDIF_FRAMECTRL_V(v)         (((v) << 13) & 0x2000)
+#define BP_SPDIF_FRAMECTRL_L            12
+#define BM_SPDIF_FRAMECTRL_L            0x1000
+#define BF_SPDIF_FRAMECTRL_L(v)         (((v) << 12) & 0x1000)
+#define BP_SPDIF_FRAMECTRL_RSRVD0       11
+#define BM_SPDIF_FRAMECTRL_RSRVD0       0x800
+#define BF_SPDIF_FRAMECTRL_RSRVD0(v)    (((v) << 11) & 0x800)
+#define BP_SPDIF_FRAMECTRL_CC           4
+#define BM_SPDIF_FRAMECTRL_CC           0x7f0
+#define BF_SPDIF_FRAMECTRL_CC(v)        (((v) << 4) & 0x7f0)
+#define BP_SPDIF_FRAMECTRL_PRE          3
+#define BM_SPDIF_FRAMECTRL_PRE          0x8
+#define BF_SPDIF_FRAMECTRL_PRE(v)       (((v) << 3) & 0x8)
+#define BP_SPDIF_FRAMECTRL_COPY         2
+#define BM_SPDIF_FRAMECTRL_COPY         0x4
+#define BF_SPDIF_FRAMECTRL_COPY(v)      (((v) << 2) & 0x4)
+#define BP_SPDIF_FRAMECTRL_AUDIO        1
+#define BM_SPDIF_FRAMECTRL_AUDIO        0x2
+#define BF_SPDIF_FRAMECTRL_AUDIO(v)     (((v) << 1) & 0x2)
+#define BP_SPDIF_FRAMECTRL_PRO          0
+#define BM_SPDIF_FRAMECTRL_PRO          0x1
+#define BF_SPDIF_FRAMECTRL_PRO(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_SRR
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_SPDIF_SRR                (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0))
+#define HW_SPDIF_SRR_SET            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4))
+#define HW_SPDIF_SRR_CLR            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8))
+#define HW_SPDIF_SRR_TOG            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc))
+#define BP_SPDIF_SRR_RSRVD1         31
+#define BM_SPDIF_SRR_RSRVD1         0x80000000
+#define BF_SPDIF_SRR_RSRVD1(v)      (((v) << 31) & 0x80000000)
+#define BP_SPDIF_SRR_BASEMULT       28
+#define BM_SPDIF_SRR_BASEMULT       0x70000000
+#define BF_SPDIF_SRR_BASEMULT(v)    (((v) << 28) & 0x70000000)
+#define BP_SPDIF_SRR_RSRVD0         20
+#define BM_SPDIF_SRR_RSRVD0         0xff00000
+#define BF_SPDIF_SRR_RSRVD0(v)      (((v) << 20) & 0xff00000)
+#define BP_SPDIF_SRR_RATE           0
+#define BM_SPDIF_SRR_RATE           0xfffff
+#define BF_SPDIF_SRR_RATE(v)        (((v) << 0) & 0xfffff)
+
+/**
+ * Register: HW_SPDIF_DEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_SPDIF_DEBUG                  (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x0))
+#define HW_SPDIF_DEBUG_SET              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x4))
+#define HW_SPDIF_DEBUG_CLR              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0x8))
+#define HW_SPDIF_DEBUG_TOG              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40 + 0xc))
+#define BP_SPDIF_DEBUG_RSRVD1           2
+#define BM_SPDIF_DEBUG_RSRVD1           0xfffffffc
+#define BF_SPDIF_DEBUG_RSRVD1(v)        (((v) << 2) & 0xfffffffc)
+#define BP_SPDIF_DEBUG_DMA_PREQ         1
+#define BM_SPDIF_DEBUG_DMA_PREQ         0x2
+#define BF_SPDIF_DEBUG_DMA_PREQ(v)      (((v) << 1) & 0x2)
+#define BP_SPDIF_DEBUG_FIFO_STATUS      0
+#define BM_SPDIF_DEBUG_FIFO_STATUS      0x1
+#define BF_SPDIF_DEBUG_FIFO_STATUS(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_DATA
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_SPDIF_DATA           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0))
+#define HW_SPDIF_DATA_SET       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4))
+#define HW_SPDIF_DATA_CLR       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8))
+#define HW_SPDIF_DATA_TOG       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc))
+#define BP_SPDIF_DATA_HIGH      16
+#define BM_SPDIF_DATA_HIGH      0xffff0000
+#define BF_SPDIF_DATA_HIGH(v)   (((v) << 16) & 0xffff0000)
+#define BP_SPDIF_DATA_LOW       0
+#define BM_SPDIF_DATA_LOW       0xffff
+#define BF_SPDIF_DATA_LOW(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_SPDIF_VERSION
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_SPDIF_VERSION            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60))
+#define BP_SPDIF_VERSION_MAJOR      24
+#define BM_SPDIF_VERSION_MAJOR      0xff000000
+#define BF_SPDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_SPDIF_VERSION_MINOR      16
+#define BM_SPDIF_VERSION_MINOR      0xff0000
+#define BF_SPDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_SPDIF_VERSION_STEP       0
+#define BM_SPDIF_VERSION_STEP       0xffff
+#define BF_SPDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-ssp.h b/firmware/target/arm/imx233/regs/imx233/regs-ssp.h
new file mode 100644
index 0000000000..012b251bcc
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-ssp.h
@@ -0,0 +1,576 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__SSP__H__
+#define __HEADERGEN__IMX233__SSP__H__
+
+#define REGS_SSP_BASE(i) ((i) == 1 ? 0x80010000 : 0x80034000)
+
+#define REGS_SSP_VERSION "3.2.0"
+
+/**
+ * Register: HW_SSP_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SSP_CTRL0(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x0))
+#define HW_SSP_CTRL0_SET(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x4))
+#define HW_SSP_CTRL0_CLR(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x8))
+#define HW_SSP_CTRL0_TOG(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0xc))
+#define BP_SSP_CTRL0_SFTRST                 31
+#define BM_SSP_CTRL0_SFTRST                 0x80000000
+#define BF_SSP_CTRL0_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_SSP_CTRL0_CLKGATE                30
+#define BM_SSP_CTRL0_CLKGATE                0x40000000
+#define BF_SSP_CTRL0_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_SSP_CTRL0_RUN                    29
+#define BM_SSP_CTRL0_RUN                    0x20000000
+#define BF_SSP_CTRL0_RUN(v)                 (((v) << 29) & 0x20000000)
+#define BP_SSP_CTRL0_SDIO_IRQ_CHECK         28
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK         0x10000000
+#define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v)      (((v) << 28) & 0x10000000)
+#define BP_SSP_CTRL0_LOCK_CS                27
+#define BM_SSP_CTRL0_LOCK_CS                0x8000000
+#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) << 27) & 0x8000000)
+#define BP_SSP_CTRL0_IGNORE_CRC             26
+#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
+#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) << 26) & 0x4000000)
+#define BP_SSP_CTRL0_READ                   25
+#define BM_SSP_CTRL0_READ                   0x2000000
+#define BF_SSP_CTRL0_READ(v)                (((v) << 25) & 0x2000000)
+#define BP_SSP_CTRL0_DATA_XFER              24
+#define BM_SSP_CTRL0_DATA_XFER              0x1000000
+#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) << 24) & 0x1000000)
+#define BP_SSP_CTRL0_BUS_WIDTH              22
+#define BM_SSP_CTRL0_BUS_WIDTH              0xc00000
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
+#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT   0x2
+#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) << 22) & 0xc00000)
+#define BF_SSP_CTRL0_BUS_WIDTH_V(v)         ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0xc00000)
+#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) << 21) & 0x200000)
+#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
+#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
+#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) << 20) & 0x100000)
+#define BP_SSP_CTRL0_LONG_RESP              19
+#define BM_SSP_CTRL0_LONG_RESP              0x80000
+#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) << 19) & 0x80000)
+#define BP_SSP_CTRL0_CHECK_RESP             18
+#define BM_SSP_CTRL0_CHECK_RESP             0x40000
+#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) << 18) & 0x40000)
+#define BP_SSP_CTRL0_GET_RESP               17
+#define BM_SSP_CTRL0_GET_RESP               0x20000
+#define BF_SSP_CTRL0_GET_RESP(v)            (((v) << 17) & 0x20000)
+#define BP_SSP_CTRL0_ENABLE                 16
+#define BM_SSP_CTRL0_ENABLE                 0x10000
+#define BF_SSP_CTRL0_ENABLE(v)              (((v) << 16) & 0x10000)
+#define BP_SSP_CTRL0_XFER_COUNT             0
+#define BM_SSP_CTRL0_XFER_COUNT             0xffff
+#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_SSP_CMD0
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SSP_CMD0(d)                              (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x0))
+#define HW_SSP_CMD0_SET(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x4))
+#define HW_SSP_CMD0_CLR(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x8))
+#define HW_SSP_CMD0_TOG(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0xc))
+#define BP_SSP_CMD0_RSVD0                           23
+#define BM_SSP_CMD0_RSVD0                           0xff800000
+#define BF_SSP_CMD0_RSVD0(v)                        (((v) << 23) & 0xff800000)
+#define BP_SSP_CMD0_SLOW_CLKING_EN                  22
+#define BM_SSP_CMD0_SLOW_CLKING_EN                  0x400000
+#define BF_SSP_CMD0_SLOW_CLKING_EN(v)               (((v) << 22) & 0x400000)
+#define BP_SSP_CMD0_CONT_CLKING_EN                  21
+#define BM_SSP_CMD0_CONT_CLKING_EN                  0x200000
+#define BF_SSP_CMD0_CONT_CLKING_EN(v)               (((v) << 21) & 0x200000)
+#define BP_SSP_CMD0_APPEND_8CYC                     20
+#define BM_SSP_CMD0_APPEND_8CYC                     0x100000
+#define BF_SSP_CMD0_APPEND_8CYC(v)                  (((v) << 20) & 0x100000)
+#define BP_SSP_CMD0_BLOCK_SIZE                      16
+#define BM_SSP_CMD0_BLOCK_SIZE                      0xf0000
+#define BF_SSP_CMD0_BLOCK_SIZE(v)                   (((v) << 16) & 0xf0000)
+#define BP_SSP_CMD0_BLOCK_COUNT                     8
+#define BM_SSP_CMD0_BLOCK_COUNT                     0xff00
+#define BF_SSP_CMD0_BLOCK_COUNT(v)                  (((v) << 8) & 0xff00)
+#define BP_SSP_CMD0_CMD                             0
+#define BM_SSP_CMD0_CMD                             0xff
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
+#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
+#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
+#define BF_SSP_CMD0_CMD(v)                          (((v) << 0) & 0xff)
+#define BF_SSP_CMD0_CMD_V(v)                        ((BV_SSP_CMD0_CMD__##v << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_CMD1
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_SSP_CMD1(d)          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x20))
+#define BP_SSP_CMD1_CMD_ARG     0
+#define BM_SSP_CMD1_CMD_ARG     0xffffffff
+#define BF_SSP_CMD1_CMD_ARG(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_COMPREF
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_SSP_COMPREF(d)           (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x30))
+#define BP_SSP_COMPREF_REFERENCE    0
+#define BM_SSP_COMPREF_REFERENCE    0xffffffff
+#define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_COMPMASK
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_SSP_COMPMASK(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x40))
+#define BP_SSP_COMPMASK_MASK    0
+#define BM_SSP_COMPMASK_MASK    0xffffffff
+#define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_TIMING
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_SSP_TIMING(d)                (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x50))
+#define BP_SSP_TIMING_TIMEOUT           16
+#define BM_SSP_TIMING_TIMEOUT           0xffff0000
+#define BF_SSP_TIMING_TIMEOUT(v)        (((v) << 16) & 0xffff0000)
+#define BP_SSP_TIMING_CLOCK_DIVIDE      8
+#define BM_SSP_TIMING_CLOCK_DIVIDE      0xff00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v)   (((v) << 8) & 0xff00)
+#define BP_SSP_TIMING_CLOCK_RATE        0
+#define BM_SSP_TIMING_CLOCK_RATE        0xff
+#define BF_SSP_TIMING_CLOCK_RATE(v)     (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_CTRL1
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_SSP_CTRL1(d)                         (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x0))
+#define HW_SSP_CTRL1_SET(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x4))
+#define HW_SSP_CTRL1_CLR(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x8))
+#define HW_SSP_CTRL1_TOG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0xc))
+#define BP_SSP_CTRL1_SDIO_IRQ                   31
+#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
+#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) << 31) & 0x80000000)
+#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
+#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
+#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) << 30) & 0x40000000)
+#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
+#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) << 29) & 0x20000000)
+#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) << 28) & 0x10000000)
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) << 27) & 0x8000000)
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) << 26) & 0x4000000)
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) << 25) & 0x2000000)
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) << 24) & 0x1000000)
+#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
+#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) << 23) & 0x800000)
+#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) << 22) & 0x400000)
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ          21
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ          0x200000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)       (((v) << 21) & 0x200000)
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_EN           20
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN           0x100000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v)        (((v) << 20) & 0x100000)
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ          19
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ          0x80000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)       (((v) << 19) & 0x80000)
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       18
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       0x40000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)    (((v) << 18) & 0x40000)
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) << 17) & 0x20000)
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) << 16) & 0x10000)
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ           15
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ           0x8000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)        (((v) << 15) & 0x8000)
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        14
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        0x4000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)     (((v) << 14) & 0x4000)
+#define BP_SSP_CTRL1_DMA_ENABLE                 13
+#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
+#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) << 13) & 0x2000)
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_EN           12
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN           0x1000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v)        (((v) << 12) & 0x1000)
+#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) << 11) & 0x800)
+#define BP_SSP_CTRL1_PHASE                      10
+#define BM_SSP_CTRL1_PHASE                      0x400
+#define BF_SSP_CTRL1_PHASE(v)                   (((v) << 10) & 0x400)
+#define BP_SSP_CTRL1_POLARITY                   9
+#define BM_SSP_CTRL1_POLARITY                   0x200
+#define BF_SSP_CTRL1_POLARITY(v)                (((v) << 9) & 0x200)
+#define BP_SSP_CTRL1_SLAVE_MODE                 8
+#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
+#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) << 8) & 0x100)
+#define BP_SSP_CTRL1_WORD_LENGTH                4
+#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
+#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) << 4) & 0xf0)
+#define BF_SSP_CTRL1_WORD_LENGTH_V(v)           ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0)
+#define BP_SSP_CTRL1_SSP_MODE                   0
+#define BM_SSP_CTRL1_SSP_MODE                   0xf
+#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
+#define BV_SSP_CTRL1_SSP_MODE__CE_ATA           0x7
+#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) << 0) & 0xf)
+#define BF_SSP_CTRL1_SSP_MODE_V(v)              ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf)
+
+/**
+ * Register: HW_SSP_DATA
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_SSP_DATA(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x70))
+#define BP_SSP_DATA_DATA    0
+#define BM_SSP_DATA_DATA    0xffffffff
+#define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP0
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_SSP_SDRESP0(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x80))
+#define BP_SSP_SDRESP0_RESP0    0
+#define BM_SSP_SDRESP0_RESP0    0xffffffff
+#define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP1
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_SSP_SDRESP1(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x90))
+#define BP_SSP_SDRESP1_RESP1    0
+#define BM_SSP_SDRESP1_RESP1    0xffffffff
+#define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP2
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_SSP_SDRESP2(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xa0))
+#define BP_SSP_SDRESP2_RESP2    0
+#define BM_SSP_SDRESP2_RESP2    0xffffffff
+#define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP3
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_SSP_SDRESP3(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xb0))
+#define BP_SSP_SDRESP3_RESP3    0
+#define BM_SSP_SDRESP3_RESP3    0xffffffff
+#define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_STATUS
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_SSP_STATUS(d)                    (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xc0))
+#define BP_SSP_STATUS_PRESENT               31
+#define BM_SSP_STATUS_PRESENT               0x80000000
+#define BF_SSP_STATUS_PRESENT(v)            (((v) << 31) & 0x80000000)
+#define BP_SSP_STATUS_MS_PRESENT            30
+#define BM_SSP_STATUS_MS_PRESENT            0x40000000
+#define BF_SSP_STATUS_MS_PRESENT(v)         (((v) << 30) & 0x40000000)
+#define BP_SSP_STATUS_SD_PRESENT            29
+#define BM_SSP_STATUS_SD_PRESENT            0x20000000
+#define BF_SSP_STATUS_SD_PRESENT(v)         (((v) << 29) & 0x20000000)
+#define BP_SSP_STATUS_CARD_DETECT           28
+#define BM_SSP_STATUS_CARD_DETECT           0x10000000
+#define BF_SSP_STATUS_CARD_DETECT(v)        (((v) << 28) & 0x10000000)
+#define BP_SSP_STATUS_RSVD3                 22
+#define BM_SSP_STATUS_RSVD3                 0xfc00000
+#define BF_SSP_STATUS_RSVD3(v)              (((v) << 22) & 0xfc00000)
+#define BP_SSP_STATUS_DMASENSE              21
+#define BM_SSP_STATUS_DMASENSE              0x200000
+#define BF_SSP_STATUS_DMASENSE(v)           (((v) << 21) & 0x200000)
+#define BP_SSP_STATUS_DMATERM               20
+#define BM_SSP_STATUS_DMATERM               0x100000
+#define BF_SSP_STATUS_DMATERM(v)            (((v) << 20) & 0x100000)
+#define BP_SSP_STATUS_DMAREQ                19
+#define BM_SSP_STATUS_DMAREQ                0x80000
+#define BF_SSP_STATUS_DMAREQ(v)             (((v) << 19) & 0x80000)
+#define BP_SSP_STATUS_DMAEND                18
+#define BM_SSP_STATUS_DMAEND                0x40000
+#define BF_SSP_STATUS_DMAEND(v)             (((v) << 18) & 0x40000)
+#define BP_SSP_STATUS_SDIO_IRQ              17
+#define BM_SSP_STATUS_SDIO_IRQ              0x20000
+#define BF_SSP_STATUS_SDIO_IRQ(v)           (((v) << 17) & 0x20000)
+#define BP_SSP_STATUS_RESP_CRC_ERR          16
+#define BM_SSP_STATUS_RESP_CRC_ERR          0x10000
+#define BF_SSP_STATUS_RESP_CRC_ERR(v)       (((v) << 16) & 0x10000)
+#define BP_SSP_STATUS_RESP_ERR              15
+#define BM_SSP_STATUS_RESP_ERR              0x8000
+#define BF_SSP_STATUS_RESP_ERR(v)           (((v) << 15) & 0x8000)
+#define BP_SSP_STATUS_RESP_TIMEOUT          14
+#define BM_SSP_STATUS_RESP_TIMEOUT          0x4000
+#define BF_SSP_STATUS_RESP_TIMEOUT(v)       (((v) << 14) & 0x4000)
+#define BP_SSP_STATUS_DATA_CRC_ERR          13
+#define BM_SSP_STATUS_DATA_CRC_ERR          0x2000
+#define BF_SSP_STATUS_DATA_CRC_ERR(v)       (((v) << 13) & 0x2000)
+#define BP_SSP_STATUS_TIMEOUT               12
+#define BM_SSP_STATUS_TIMEOUT               0x1000
+#define BF_SSP_STATUS_TIMEOUT(v)            (((v) << 12) & 0x1000)
+#define BP_SSP_STATUS_RECV_TIMEOUT_STAT     11
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT     0x800
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)  (((v) << 11) & 0x800)
+#define BP_SSP_STATUS_CEATA_CCS_ERR         10
+#define BM_SSP_STATUS_CEATA_CCS_ERR         0x400
+#define BF_SSP_STATUS_CEATA_CCS_ERR(v)      (((v) << 10) & 0x400)
+#define BP_SSP_STATUS_FIFO_OVRFLW           9
+#define BM_SSP_STATUS_FIFO_OVRFLW           0x200
+#define BF_SSP_STATUS_FIFO_OVRFLW(v)        (((v) << 9) & 0x200)
+#define BP_SSP_STATUS_FIFO_FULL             8
+#define BM_SSP_STATUS_FIFO_FULL             0x100
+#define BF_SSP_STATUS_FIFO_FULL(v)          (((v) << 8) & 0x100)
+#define BP_SSP_STATUS_RSVD1                 6
+#define BM_SSP_STATUS_RSVD1                 0xc0
+#define BF_SSP_STATUS_RSVD1(v)              (((v) << 6) & 0xc0)
+#define BP_SSP_STATUS_FIFO_EMPTY            5
+#define BM_SSP_STATUS_FIFO_EMPTY            0x20
+#define BF_SSP_STATUS_FIFO_EMPTY(v)         (((v) << 5) & 0x20)
+#define BP_SSP_STATUS_FIFO_UNDRFLW          4
+#define BM_SSP_STATUS_FIFO_UNDRFLW          0x10
+#define BF_SSP_STATUS_FIFO_UNDRFLW(v)       (((v) << 4) & 0x10)
+#define BP_SSP_STATUS_CMD_BUSY              3
+#define BM_SSP_STATUS_CMD_BUSY              0x8
+#define BF_SSP_STATUS_CMD_BUSY(v)           (((v) << 3) & 0x8)
+#define BP_SSP_STATUS_DATA_BUSY             2
+#define BM_SSP_STATUS_DATA_BUSY             0x4
+#define BF_SSP_STATUS_DATA_BUSY(v)          (((v) << 2) & 0x4)
+#define BP_SSP_STATUS_RSVD0                 1
+#define BM_SSP_STATUS_RSVD0                 0x2
+#define BF_SSP_STATUS_RSVD0(v)              (((v) << 1) & 0x2)
+#define BP_SSP_STATUS_BUSY                  0
+#define BM_SSP_STATUS_BUSY                  0x1
+#define BF_SSP_STATUS_BUSY(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SSP_DEBUG
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_SSP_DEBUG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x100))
+#define BP_SSP_DEBUG_DATACRC_ERR            28
+#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) << 28) & 0xf0000000)
+#define BP_SSP_DEBUG_DATA_STALL             27
+#define BM_SSP_DEBUG_DATA_STALL             0x8000000
+#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) << 27) & 0x8000000)
+#define BP_SSP_DEBUG_DAT_SM                 24
+#define BM_SSP_DEBUG_DAT_SM                 0x7000000
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
+#define BF_SSP_DEBUG_DAT_SM(v)              (((v) << 24) & 0x7000000)
+#define BF_SSP_DEBUG_DAT_SM_V(v)            ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000)
+#define BP_SSP_DEBUG_MSTK_SM                20
+#define BM_SSP_DEBUG_MSTK_SM                0xf00000
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1     0xb
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W    0xc
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R    0xd
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xe
+#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) << 20) & 0xf00000)
+#define BF_SSP_DEBUG_MSTK_SM_V(v)           ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000)
+#define BP_SSP_DEBUG_CMD_OE                 19
+#define BM_SSP_DEBUG_CMD_OE                 0x80000
+#define BF_SSP_DEBUG_CMD_OE(v)              (((v) << 19) & 0x80000)
+#define BP_SSP_DEBUG_DMA_SM                 16
+#define BM_SSP_DEBUG_DMA_SM                 0x70000
+#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE       0x0
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ     0x1
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK     0x2
+#define BV_SSP_DEBUG_DMA_SM__DMA_STALL      0x3
+#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY       0x4
+#define BV_SSP_DEBUG_DMA_SM__DMA_DONE       0x5
+#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT      0x6
+#define BF_SSP_DEBUG_DMA_SM(v)              (((v) << 16) & 0x70000)
+#define BF_SSP_DEBUG_DMA_SM_V(v)            ((BV_SSP_DEBUG_DMA_SM__##v << 16) & 0x70000)
+#define BP_SSP_DEBUG_MMC_SM                 12
+#define BM_SSP_DEBUG_MMC_SM                 0xf000
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
+#define BV_SSP_DEBUG_MMC_SM__MMC_CCS        0x8
+#define BV_SSP_DEBUG_MMC_SM__MMC_PUP        0x9
+#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT       0xa
+#define BF_SSP_DEBUG_MMC_SM(v)              (((v) << 12) & 0xf000)
+#define BF_SSP_DEBUG_MMC_SM_V(v)            ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0xf000)
+#define BP_SSP_DEBUG_CMD_SM                 10
+#define BM_SSP_DEBUG_CMD_SM                 0xc00
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
+#define BF_SSP_DEBUG_CMD_SM(v)              (((v) << 10) & 0xc00)
+#define BF_SSP_DEBUG_CMD_SM_V(v)            ((BV_SSP_DEBUG_CMD_SM__##v << 10) & 0xc00)
+#define BP_SSP_DEBUG_SSP_CMD                9
+#define BM_SSP_DEBUG_SSP_CMD                0x200
+#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) << 9) & 0x200)
+#define BP_SSP_DEBUG_SSP_RESP               8
+#define BM_SSP_DEBUG_SSP_RESP               0x100
+#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) << 8) & 0x100)
+#define BP_SSP_DEBUG_SSP_RXD                0
+#define BM_SSP_DEBUG_SSP_RXD                0xff
+#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_VERSION
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_SSP_VERSION(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x110))
+#define BP_SSP_VERSION_MAJOR    24
+#define BM_SSP_VERSION_MAJOR    0xff000000
+#define BF_SSP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_SSP_VERSION_MINOR    16
+#define BM_SSP_VERSION_MINOR    0xff0000
+#define BF_SSP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_SSP_VERSION_STEP     0
+#define BM_SSP_VERSION_STEP     0xffff
+#define BF_SSP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-sydma.h b/firmware/target/arm/imx233/regs/imx233/regs-sydma.h
new file mode 100644
index 0000000000..ec0a4bc959
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-sydma.h
@@ -0,0 +1,194 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__SYDMA__H__
+#define __HEADERGEN__IMX233__SYDMA__H__
+
+#define REGS_SYDMA_BASE (0x80026000)
+
+#define REGS_SYDMA_VERSION "3.2.0"
+
+/**
+ * Register: HW_SYDMA_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SYDMA_CTRL                           (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x0))
+#define HW_SYDMA_CTRL_SET                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x4))
+#define HW_SYDMA_CTRL_CLR                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0x8))
+#define HW_SYDMA_CTRL_TOG                       (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x0 + 0xc))
+#define BP_SYDMA_CTRL_SFTRST                    31
+#define BM_SYDMA_CTRL_SFTRST                    0x80000000
+#define BV_SYDMA_CTRL_SFTRST__RUN               0x0
+#define BV_SYDMA_CTRL_SFTRST__RESET             0x1
+#define BF_SYDMA_CTRL_SFTRST(v)                 (((v) << 31) & 0x80000000)
+#define BF_SYDMA_CTRL_SFTRST_V(v)               ((BV_SYDMA_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_SYDMA_CTRL_CLKGATE                   30
+#define BM_SYDMA_CTRL_CLKGATE                   0x40000000
+#define BV_SYDMA_CTRL_CLKGATE__RUN              0x0
+#define BV_SYDMA_CTRL_CLKGATE__NO_CLKS          0x1
+#define BF_SYDMA_CTRL_CLKGATE(v)                (((v) << 30) & 0x40000000)
+#define BF_SYDMA_CTRL_CLKGATE_V(v)              ((BV_SYDMA_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_SYDMA_CTRL_RSVD1                     10
+#define BM_SYDMA_CTRL_RSVD1                     0x3ffffc00
+#define BF_SYDMA_CTRL_RSVD1(v)                  (((v) << 10) & 0x3ffffc00)
+#define BP_SYDMA_CTRL_COMPLETE_IRQ_EN           9
+#define BM_SYDMA_CTRL_COMPLETE_IRQ_EN           0x200
+#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0
+#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED  0x1
+#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN(v)        (((v) << 9) & 0x200)
+#define BF_SYDMA_CTRL_COMPLETE_IRQ_EN_V(v)      ((BV_SYDMA_CTRL_COMPLETE_IRQ_EN__##v << 9) & 0x200)
+#define BP_SYDMA_CTRL_RSVD0                     3
+#define BM_SYDMA_CTRL_RSVD0                     0x1f8
+#define BF_SYDMA_CTRL_RSVD0(v)                  (((v) << 3) & 0x1f8)
+#define BP_SYDMA_CTRL_ERROR_IRQ                 2
+#define BM_SYDMA_CTRL_ERROR_IRQ                 0x4
+#define BF_SYDMA_CTRL_ERROR_IRQ(v)              (((v) << 2) & 0x4)
+#define BP_SYDMA_CTRL_COMPLETE_IRQ              1
+#define BM_SYDMA_CTRL_COMPLETE_IRQ              0x2
+#define BF_SYDMA_CTRL_COMPLETE_IRQ(v)           (((v) << 1) & 0x2)
+#define BP_SYDMA_CTRL_RUN                       0
+#define BM_SYDMA_CTRL_RUN                       0x1
+#define BV_SYDMA_CTRL_RUN__HALT                 0x0
+#define BV_SYDMA_CTRL_RUN__RUN                  0x1
+#define BF_SYDMA_CTRL_RUN(v)                    (((v) << 0) & 0x1)
+#define BF_SYDMA_CTRL_RUN_V(v)                  ((BV_SYDMA_CTRL_RUN__##v << 0) & 0x1)
+
+/**
+ * Register: HW_SYDMA_RADDR
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_SYDMA_RADDR              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x10))
+#define BP_SYDMA_RADDR_RSRC_ADDR    0
+#define BM_SYDMA_RADDR_RSRC_ADDR    0xffffffff
+#define BF_SYDMA_RADDR_RSRC_ADDR(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SYDMA_WADDR
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_SYDMA_WADDR              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x20))
+#define BP_SYDMA_WADDR_WSRC_ADDR    0
+#define BM_SYDMA_WADDR_WSRC_ADDR    0xffffffff
+#define BF_SYDMA_WADDR_WSRC_ADDR(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SYDMA_XFER_COUNT
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_SYDMA_XFER_COUNT         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x30))
+#define BP_SYDMA_XFER_COUNT_SIZE    0
+#define BM_SYDMA_XFER_COUNT_SIZE    0xffffffff
+#define BF_SYDMA_XFER_COUNT_SIZE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SYDMA_BURST
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_SYDMA_BURST              (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x40))
+#define BP_SYDMA_BURST_RSVD0        4
+#define BM_SYDMA_BURST_RSVD0        0xfffffff0
+#define BF_SYDMA_BURST_RSVD0(v)     (((v) << 4) & 0xfffffff0)
+#define BP_SYDMA_BURST_WLEN         2
+#define BM_SYDMA_BURST_WLEN         0xc
+#define BV_SYDMA_BURST_WLEN__1      0x0
+#define BV_SYDMA_BURST_WLEN__2      0x1
+#define BV_SYDMA_BURST_WLEN__4      0x2
+#define BV_SYDMA_BURST_WLEN__8      0x3
+#define BF_SYDMA_BURST_WLEN(v)      (((v) << 2) & 0xc)
+#define BF_SYDMA_BURST_WLEN_V(v)    ((BV_SYDMA_BURST_WLEN__##v << 2) & 0xc)
+#define BP_SYDMA_BURST_RLEN         0
+#define BM_SYDMA_BURST_RLEN         0x3
+#define BV_SYDMA_BURST_RLEN__1      0x0
+#define BV_SYDMA_BURST_RLEN__2      0x1
+#define BV_SYDMA_BURST_RLEN__4      0x2
+#define BV_SYDMA_BURST_RLEN__8      0x3
+#define BF_SYDMA_BURST_RLEN(v)      (((v) << 0) & 0x3)
+#define BF_SYDMA_BURST_RLEN_V(v)    ((BV_SYDMA_BURST_RLEN__##v << 0) & 0x3)
+
+/**
+ * Register: HW_SYDMA_DACK
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_SYDMA_DACK           (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x50))
+#define BP_SYDMA_DACK_RSVD0     8
+#define BM_SYDMA_DACK_RSVD0     0xffffff00
+#define BF_SYDMA_DACK_RSVD0(v)  (((v) << 8) & 0xffffff00)
+#define BP_SYDMA_DACK_WDELAY    4
+#define BM_SYDMA_DACK_WDELAY    0xf0
+#define BF_SYDMA_DACK_WDELAY(v) (((v) << 4) & 0xf0)
+#define BP_SYDMA_DACK_RDELAY    0
+#define BM_SYDMA_DACK_RDELAY    0xf
+#define BF_SYDMA_DACK_RDELAY(v) (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_SYDMA_DEBUG0
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_SYDMA_DEBUG0         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x100))
+#define BP_SYDMA_DEBUG0_DATA    0
+#define BM_SYDMA_DEBUG0_DATA    0xffffffff
+#define BF_SYDMA_DEBUG0_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SYDMA_DEBUG1
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_SYDMA_DEBUG1         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x110))
+#define BP_SYDMA_DEBUG1_DATA    0
+#define BM_SYDMA_DEBUG1_DATA    0xffffffff
+#define BF_SYDMA_DEBUG1_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SYDMA_DEBUG2
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_SYDMA_DEBUG2         (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x120))
+#define BP_SYDMA_DEBUG2_DATA    0
+#define BM_SYDMA_DEBUG2_DATA    0xffffffff
+#define BF_SYDMA_DEBUG2_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SYDMA_VERSION
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_SYDMA_VERSION            (*(volatile unsigned long *)(REGS_SYDMA_BASE + 0x130))
+#define BP_SYDMA_VERSION_MAJOR      24
+#define BM_SYDMA_VERSION_MAJOR      0xff000000
+#define BF_SYDMA_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_SYDMA_VERSION_MINOR      16
+#define BM_SYDMA_VERSION_MINOR      0xff0000
+#define BF_SYDMA_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_SYDMA_VERSION_STEP       0
+#define BM_SYDMA_VERSION_STEP       0xffff
+#define BF_SYDMA_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__SYDMA__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-timrot.h b/firmware/target/arm/imx233/regs/imx233/regs-timrot.h
new file mode 100644
index 0000000000..f6c24f4ef8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-timrot.h
@@ -0,0 +1,307 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__TIMROT__H__
+#define __HEADERGEN__IMX233__TIMROT__H__
+
+#define REGS_TIMROT_BASE (0x80068000)
+
+#define REGS_TIMROT_VERSION "3.2.0"
+
+/**
+ * Register: HW_TIMROT_ROTCTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_TIMROT_ROTCTRL                       (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0))
+#define HW_TIMROT_ROTCTRL_SET                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4))
+#define HW_TIMROT_ROTCTRL_CLR                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8))
+#define HW_TIMROT_ROTCTRL_TOG                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc))
+#define BP_TIMROT_ROTCTRL_SFTRST                31
+#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
+#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
+#define BP_TIMROT_ROTCTRL_CLKGATE               30
+#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
+#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
+#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) << 29) & 0x20000000)
+#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) << 28) & 0x10000000)
+#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) << 27) & 0x8000000)
+#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) << 26) & 0x4000000)
+#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) << 25) & 0x2000000)
+#define BP_TIMROT_ROTCTRL_STATE                 22
+#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
+#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) << 22) & 0x1c00000)
+#define BP_TIMROT_ROTCTRL_DIVIDER               16
+#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) << 16) & 0x3f0000)
+#define BP_TIMROT_ROTCTRL_RSRVD3                13
+#define BM_TIMROT_ROTCTRL_RSRVD3                0xe000
+#define BF_TIMROT_ROTCTRL_RSRVD3(v)             (((v) << 13) & 0xe000)
+#define BP_TIMROT_ROTCTRL_RELATIVE              12
+#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
+#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) << 12) & 0x1000)
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) << 10) & 0xc00)
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v)       ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00)
+#define BP_TIMROT_ROTCTRL_POLARITY_B            9
+#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
+#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) << 9) & 0x200)
+#define BP_TIMROT_ROTCTRL_POLARITY_A            8
+#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
+#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) << 8) & 0x100)
+#define BP_TIMROT_ROTCTRL_RSRVD2                7
+#define BM_TIMROT_ROTCTRL_RSRVD2                0x80
+#define BF_TIMROT_ROTCTRL_RSRVD2(v)             (((v) << 7) & 0x80)
+#define BP_TIMROT_ROTCTRL_SELECT_B              4
+#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) << 4) & 0x70)
+#define BF_TIMROT_ROTCTRL_SELECT_B_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70)
+#define BP_TIMROT_ROTCTRL_RSRVD1                3
+#define BM_TIMROT_ROTCTRL_RSRVD1                0x8
+#define BF_TIMROT_ROTCTRL_RSRVD1(v)             (((v) << 3) & 0x8)
+#define BP_TIMROT_ROTCTRL_SELECT_A              0
+#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) << 0) & 0x7)
+#define BF_TIMROT_ROTCTRL_SELECT_A_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7)
+
+/**
+ * Register: HW_TIMROT_ROTCOUNT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_TIMROT_ROTCOUNT              (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10))
+#define BP_TIMROT_ROTCOUNT_RSRVD1       16
+#define BM_TIMROT_ROTCOUNT_RSRVD1       0xffff0000
+#define BF_TIMROT_ROTCOUNT_RSRVD1(v)    (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_ROTCOUNT_UPDOWN       0
+#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_TIMCTRLn
+ * Address: 0x20+n*0x20
+ * SCT: yes
+*/
+#define HW_TIMROT_TIMCTRLn(n)                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0))
+#define HW_TIMROT_TIMCTRLn_SET(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4))
+#define HW_TIMROT_TIMCTRLn_CLR(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8))
+#define HW_TIMROT_TIMCTRLn_TOG(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc))
+#define BP_TIMROT_TIMCTRLn_RSRVD2               16
+#define BM_TIMROT_TIMCTRLn_RSRVD2               0xffff0000
+#define BF_TIMROT_TIMCTRLn_RSRVD2(v)            (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_TIMCTRLn_IRQ                  15
+#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
+#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) << 15) & 0x8000)
+#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
+#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
+#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) << 14) & 0x4000)
+#define BP_TIMROT_TIMCTRLn_RSRVD1               9
+#define BM_TIMROT_TIMCTRLn_RSRVD1               0x3e00
+#define BF_TIMROT_TIMCTRLn_RSRVD1(v)            (((v) << 9) & 0x3e00)
+#define BP_TIMROT_TIMCTRLn_POLARITY             8
+#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
+#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) << 8) & 0x100)
+#define BP_TIMROT_TIMCTRLn_UPDATE               7
+#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
+#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) << 7) & 0x80)
+#define BP_TIMROT_TIMCTRLn_RELOAD               6
+#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
+#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) << 6) & 0x40)
+#define BP_TIMROT_TIMCTRLn_PRESCALE             4
+#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) << 4) & 0x30)
+#define BF_TIMROT_TIMCTRLn_PRESCALE_V(v)        ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30)
+#define BP_TIMROT_TIMCTRLn_SELECT               0
+#define BM_TIMROT_TIMCTRLn_SELECT               0xf
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
+#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) << 0) & 0xf)
+#define BF_TIMROT_TIMCTRLn_SELECT_V(v)          ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_TIMROT_TIMCOUNTn
+ * Address: 0x30+n*0x20
+ * SCT: no
+*/
+#define HW_TIMROT_TIMCOUNTn(n)                  (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20))
+#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
+#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_TIMCTRL3
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_TIMROT_TIMCTRL3                          (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0))
+#define HW_TIMROT_TIMCTRL3_SET                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4))
+#define HW_TIMROT_TIMCTRL3_CLR                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8))
+#define HW_TIMROT_TIMCTRL3_TOG                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc))
+#define BP_TIMROT_TIMCTRL3_RSRVD2                   20
+#define BM_TIMROT_TIMCTRL3_RSRVD2                   0xfff00000
+#define BF_TIMROT_TIMCTRL3_RSRVD2(v)                (((v) << 20) & 0xfff00000)
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) << 16) & 0xf0000)
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)         ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000)
+#define BP_TIMROT_TIMCTRL3_IRQ                      15
+#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
+#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) << 15) & 0x8000)
+#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
+#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
+#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) << 14) & 0x4000)
+#define BP_TIMROT_TIMCTRL3_RSRVD1                   11
+#define BM_TIMROT_TIMCTRL3_RSRVD1                   0x3800
+#define BF_TIMROT_TIMCTRL3_RSRVD1(v)                (((v) << 11) & 0x3800)
+#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) << 10) & 0x400)
+#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) << 9) & 0x200)
+#define BP_TIMROT_TIMCTRL3_POLARITY                 8
+#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
+#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) << 8) & 0x100)
+#define BP_TIMROT_TIMCTRL3_UPDATE                   7
+#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
+#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) << 7) & 0x80)
+#define BP_TIMROT_TIMCTRL3_RELOAD                   6
+#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
+#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) << 6) & 0x40)
+#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) << 4) & 0x30)
+#define BF_TIMROT_TIMCTRL3_PRESCALE_V(v)            ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30)
+#define BP_TIMROT_TIMCTRL3_SELECT                   0
+#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
+#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) << 0) & 0xf)
+#define BF_TIMROT_TIMCTRL3_SELECT_V(v)              ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_TIMROT_TIMCOUNT3
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_TIMROT_TIMCOUNT3                         (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90))
+#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
+#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_VERSION
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_TIMROT_VERSION           (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0xa0))
+#define BP_TIMROT_VERSION_MAJOR     24
+#define BM_TIMROT_VERSION_MAJOR     0xff000000
+#define BF_TIMROT_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
+#define BP_TIMROT_VERSION_MINOR     16
+#define BM_TIMROT_VERSION_MINOR     0xff0000
+#define BF_TIMROT_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
+#define BP_TIMROT_VERSION_STEP      0
+#define BM_TIMROT_VERSION_STEP      0xffff
+#define BF_TIMROT_VERSION_STEP(v)   (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h b/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h
new file mode 100644
index 0000000000..c587f5f7fa
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-tvenc.h
@@ -0,0 +1,776 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__TVENC__H__
+#define __HEADERGEN__IMX233__TVENC__H__
+
+#define REGS_TVENC_BASE (0x80038000)
+
+#define REGS_TVENC_VERSION "3.2.0"
+
+/**
+ * Register: HW_TVENC_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_TVENC_CTRL                               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x0))
+#define HW_TVENC_CTRL_SET                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x4))
+#define HW_TVENC_CTRL_CLR                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0x8))
+#define HW_TVENC_CTRL_TOG                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x0 + 0xc))
+#define BP_TVENC_CTRL_SFTRST                        31
+#define BM_TVENC_CTRL_SFTRST                        0x80000000
+#define BF_TVENC_CTRL_SFTRST(v)                     (((v) << 31) & 0x80000000)
+#define BP_TVENC_CTRL_CLKGATE                       30
+#define BM_TVENC_CTRL_CLKGATE                       0x40000000
+#define BF_TVENC_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
+#define BP_TVENC_CTRL_TVENC_MACROVISION_PRESENT     29
+#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT     0x20000000
+#define BF_TVENC_CTRL_TVENC_MACROVISION_PRESENT(v)  (((v) << 29) & 0x20000000)
+#define BP_TVENC_CTRL_TVENC_COMPOSITE_PRESENT       28
+#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT       0x10000000
+#define BF_TVENC_CTRL_TVENC_COMPOSITE_PRESENT(v)    (((v) << 28) & 0x10000000)
+#define BP_TVENC_CTRL_TVENC_SVIDEO_PRESENT          27
+#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT          0x8000000
+#define BF_TVENC_CTRL_TVENC_SVIDEO_PRESENT(v)       (((v) << 27) & 0x8000000)
+#define BP_TVENC_CTRL_TVENC_COMPONENT_PRESENT       26
+#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT       0x4000000
+#define BF_TVENC_CTRL_TVENC_COMPONENT_PRESENT(v)    (((v) << 26) & 0x4000000)
+#define BP_TVENC_CTRL_RSRVD1                        6
+#define BM_TVENC_CTRL_RSRVD1                        0x3ffffc0
+#define BF_TVENC_CTRL_RSRVD1(v)                     (((v) << 6) & 0x3ffffc0)
+#define BP_TVENC_CTRL_DAC_FIFO_NO_WRITE             5
+#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE             0x20
+#define BF_TVENC_CTRL_DAC_FIFO_NO_WRITE(v)          (((v) << 5) & 0x20)
+#define BP_TVENC_CTRL_DAC_FIFO_NO_READ              4
+#define BM_TVENC_CTRL_DAC_FIFO_NO_READ              0x10
+#define BF_TVENC_CTRL_DAC_FIFO_NO_READ(v)           (((v) << 4) & 0x10)
+#define BP_TVENC_CTRL_DAC_DATA_FIFO_RST             3
+#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST             0x8
+#define BF_TVENC_CTRL_DAC_DATA_FIFO_RST(v)          (((v) << 3) & 0x8)
+#define BP_TVENC_CTRL_RSRVD2                        1
+#define BM_TVENC_CTRL_RSRVD2                        0x6
+#define BF_TVENC_CTRL_RSRVD2(v)                     (((v) << 1) & 0x6)
+#define BP_TVENC_CTRL_DAC_MUX_MODE                  0
+#define BM_TVENC_CTRL_DAC_MUX_MODE                  0x1
+#define BF_TVENC_CTRL_DAC_MUX_MODE(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_TVENC_CONFIG
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_TVENC_CONFIG                     (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x0))
+#define HW_TVENC_CONFIG_SET                 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x4))
+#define HW_TVENC_CONFIG_CLR                 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0x8))
+#define HW_TVENC_CONFIG_TOG                 (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x10 + 0xc))
+#define BP_TVENC_CONFIG_RSRVD5              28
+#define BM_TVENC_CONFIG_RSRVD5              0xf0000000
+#define BF_TVENC_CONFIG_RSRVD5(v)           (((v) << 28) & 0xf0000000)
+#define BP_TVENC_CONFIG_DEFAULT_PICFORM     27
+#define BM_TVENC_CONFIG_DEFAULT_PICFORM     0x8000000
+#define BF_TVENC_CONFIG_DEFAULT_PICFORM(v)  (((v) << 27) & 0x8000000)
+#define BP_TVENC_CONFIG_YDEL_ADJ            24
+#define BM_TVENC_CONFIG_YDEL_ADJ            0x7000000
+#define BF_TVENC_CONFIG_YDEL_ADJ(v)         (((v) << 24) & 0x7000000)
+#define BP_TVENC_CONFIG_RSRVD4              23
+#define BM_TVENC_CONFIG_RSRVD4              0x800000
+#define BF_TVENC_CONFIG_RSRVD4(v)           (((v) << 23) & 0x800000)
+#define BP_TVENC_CONFIG_RSRVD3              22
+#define BM_TVENC_CONFIG_RSRVD3              0x400000
+#define BF_TVENC_CONFIG_RSRVD3(v)           (((v) << 22) & 0x400000)
+#define BP_TVENC_CONFIG_ADD_YPBPR_PED       21
+#define BM_TVENC_CONFIG_ADD_YPBPR_PED       0x200000
+#define BF_TVENC_CONFIG_ADD_YPBPR_PED(v)    (((v) << 21) & 0x200000)
+#define BP_TVENC_CONFIG_PAL_SHAPE           20
+#define BM_TVENC_CONFIG_PAL_SHAPE           0x100000
+#define BF_TVENC_CONFIG_PAL_SHAPE(v)        (((v) << 20) & 0x100000)
+#define BP_TVENC_CONFIG_NO_PED              19
+#define BM_TVENC_CONFIG_NO_PED              0x80000
+#define BF_TVENC_CONFIG_NO_PED(v)           (((v) << 19) & 0x80000)
+#define BP_TVENC_CONFIG_COLOR_BAR_EN        18
+#define BM_TVENC_CONFIG_COLOR_BAR_EN        0x40000
+#define BF_TVENC_CONFIG_COLOR_BAR_EN(v)     (((v) << 18) & 0x40000)
+#define BP_TVENC_CONFIG_YGAIN_SEL           16
+#define BM_TVENC_CONFIG_YGAIN_SEL           0x30000
+#define BF_TVENC_CONFIG_YGAIN_SEL(v)        (((v) << 16) & 0x30000)
+#define BP_TVENC_CONFIG_CGAIN               14
+#define BM_TVENC_CONFIG_CGAIN               0xc000
+#define BF_TVENC_CONFIG_CGAIN(v)            (((v) << 14) & 0xc000)
+#define BP_TVENC_CONFIG_CLK_PHS             12
+#define BM_TVENC_CONFIG_CLK_PHS             0x3000
+#define BF_TVENC_CONFIG_CLK_PHS(v)          (((v) << 12) & 0x3000)
+#define BP_TVENC_CONFIG_RSRVD2              11
+#define BM_TVENC_CONFIG_RSRVD2              0x800
+#define BF_TVENC_CONFIG_RSRVD2(v)           (((v) << 11) & 0x800)
+#define BP_TVENC_CONFIG_FSYNC_ENBL          10
+#define BM_TVENC_CONFIG_FSYNC_ENBL          0x400
+#define BF_TVENC_CONFIG_FSYNC_ENBL(v)       (((v) << 10) & 0x400)
+#define BP_TVENC_CONFIG_FSYNC_PHS           9
+#define BM_TVENC_CONFIG_FSYNC_PHS           0x200
+#define BF_TVENC_CONFIG_FSYNC_PHS(v)        (((v) << 9) & 0x200)
+#define BP_TVENC_CONFIG_HSYNC_PHS           8
+#define BM_TVENC_CONFIG_HSYNC_PHS           0x100
+#define BF_TVENC_CONFIG_HSYNC_PHS(v)        (((v) << 8) & 0x100)
+#define BP_TVENC_CONFIG_VSYNC_PHS           7
+#define BM_TVENC_CONFIG_VSYNC_PHS           0x80
+#define BF_TVENC_CONFIG_VSYNC_PHS(v)        (((v) << 7) & 0x80)
+#define BP_TVENC_CONFIG_SYNC_MODE           4
+#define BM_TVENC_CONFIG_SYNC_MODE           0x70
+#define BF_TVENC_CONFIG_SYNC_MODE(v)        (((v) << 4) & 0x70)
+#define BP_TVENC_CONFIG_RSRVD1              3
+#define BM_TVENC_CONFIG_RSRVD1              0x8
+#define BF_TVENC_CONFIG_RSRVD1(v)           (((v) << 3) & 0x8)
+#define BP_TVENC_CONFIG_ENCD_MODE           0
+#define BM_TVENC_CONFIG_ENCD_MODE           0x7
+#define BF_TVENC_CONFIG_ENCD_MODE(v)        (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_TVENC_FILTCTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_TVENC_FILTCTRL                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x0))
+#define HW_TVENC_FILTCTRL_SET               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x4))
+#define HW_TVENC_FILTCTRL_CLR               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0x8))
+#define HW_TVENC_FILTCTRL_TOG               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x20 + 0xc))
+#define BP_TVENC_FILTCTRL_RSRVD1            20
+#define BM_TVENC_FILTCTRL_RSRVD1            0xfff00000
+#define BF_TVENC_FILTCTRL_RSRVD1(v)         (((v) << 20) & 0xfff00000)
+#define BP_TVENC_FILTCTRL_YSHARP_BW         19
+#define BM_TVENC_FILTCTRL_YSHARP_BW         0x80000
+#define BF_TVENC_FILTCTRL_YSHARP_BW(v)      (((v) << 19) & 0x80000)
+#define BP_TVENC_FILTCTRL_YD_OFFSETSEL      18
+#define BM_TVENC_FILTCTRL_YD_OFFSETSEL      0x40000
+#define BF_TVENC_FILTCTRL_YD_OFFSETSEL(v)   (((v) << 18) & 0x40000)
+#define BP_TVENC_FILTCTRL_SEL_YLPF          17
+#define BM_TVENC_FILTCTRL_SEL_YLPF          0x20000
+#define BF_TVENC_FILTCTRL_SEL_YLPF(v)       (((v) << 17) & 0x20000)
+#define BP_TVENC_FILTCTRL_SEL_CLPF          16
+#define BM_TVENC_FILTCTRL_SEL_CLPF          0x10000
+#define BF_TVENC_FILTCTRL_SEL_CLPF(v)       (((v) << 16) & 0x10000)
+#define BP_TVENC_FILTCTRL_SEL_YSHARP        15
+#define BM_TVENC_FILTCTRL_SEL_YSHARP        0x8000
+#define BF_TVENC_FILTCTRL_SEL_YSHARP(v)     (((v) << 15) & 0x8000)
+#define BP_TVENC_FILTCTRL_YLPF_COEFSEL      14
+#define BM_TVENC_FILTCTRL_YLPF_COEFSEL      0x4000
+#define BF_TVENC_FILTCTRL_YLPF_COEFSEL(v)   (((v) << 14) & 0x4000)
+#define BP_TVENC_FILTCTRL_COEFSEL_CLPF      13
+#define BM_TVENC_FILTCTRL_COEFSEL_CLPF      0x2000
+#define BF_TVENC_FILTCTRL_COEFSEL_CLPF(v)   (((v) << 13) & 0x2000)
+#define BP_TVENC_FILTCTRL_YS_GAINSGN        12
+#define BM_TVENC_FILTCTRL_YS_GAINSGN        0x1000
+#define BF_TVENC_FILTCTRL_YS_GAINSGN(v)     (((v) << 12) & 0x1000)
+#define BP_TVENC_FILTCTRL_YS_GAINSEL        10
+#define BM_TVENC_FILTCTRL_YS_GAINSEL        0xc00
+#define BF_TVENC_FILTCTRL_YS_GAINSEL(v)     (((v) << 10) & 0xc00)
+#define BP_TVENC_FILTCTRL_RSRVD2            9
+#define BM_TVENC_FILTCTRL_RSRVD2            0x200
+#define BF_TVENC_FILTCTRL_RSRVD2(v)         (((v) << 9) & 0x200)
+#define BP_TVENC_FILTCTRL_RSRVD3            8
+#define BM_TVENC_FILTCTRL_RSRVD3            0x100
+#define BF_TVENC_FILTCTRL_RSRVD3(v)         (((v) << 8) & 0x100)
+#define BP_TVENC_FILTCTRL_RSRVD4            0
+#define BM_TVENC_FILTCTRL_RSRVD4            0xff
+#define BF_TVENC_FILTCTRL_RSRVD4(v)         (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_TVENC_SYNCOFFSET
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_TVENC_SYNCOFFSET             (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x0))
+#define HW_TVENC_SYNCOFFSET_SET         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x4))
+#define HW_TVENC_SYNCOFFSET_CLR         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0x8))
+#define HW_TVENC_SYNCOFFSET_TOG         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x30 + 0xc))
+#define BP_TVENC_SYNCOFFSET_RSRVD1      31
+#define BM_TVENC_SYNCOFFSET_RSRVD1      0x80000000
+#define BF_TVENC_SYNCOFFSET_RSRVD1(v)   (((v) << 31) & 0x80000000)
+#define BP_TVENC_SYNCOFFSET_HSO         20
+#define BM_TVENC_SYNCOFFSET_HSO         0x7ff00000
+#define BF_TVENC_SYNCOFFSET_HSO(v)      (((v) << 20) & 0x7ff00000)
+#define BP_TVENC_SYNCOFFSET_VSO         10
+#define BM_TVENC_SYNCOFFSET_VSO         0xffc00
+#define BF_TVENC_SYNCOFFSET_VSO(v)      (((v) << 10) & 0xffc00)
+#define BP_TVENC_SYNCOFFSET_HLC         0
+#define BM_TVENC_SYNCOFFSET_HLC         0x3ff
+#define BF_TVENC_SYNCOFFSET_HLC(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_HTIMINGSYNC0
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_TVENC_HTIMINGSYNC0               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x0))
+#define HW_TVENC_HTIMINGSYNC0_SET           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x4))
+#define HW_TVENC_HTIMINGSYNC0_CLR           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0x8))
+#define HW_TVENC_HTIMINGSYNC0_TOG           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x40 + 0xc))
+#define BP_TVENC_HTIMINGSYNC0_RSRVD2        26
+#define BM_TVENC_HTIMINGSYNC0_RSRVD2        0xfc000000
+#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v)     (((v) << 26) & 0xfc000000)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_END      16
+#define BM_TVENC_HTIMINGSYNC0_SYNC_END      0x3ff0000
+#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v)   (((v) << 16) & 0x3ff0000)
+#define BP_TVENC_HTIMINGSYNC0_RSRVD1        10
+#define BM_TVENC_HTIMINGSYNC0_RSRVD1        0xfc00
+#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v)     (((v) << 10) & 0xfc00)
+#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT     0
+#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT     0x3ff
+#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_HTIMINGSYNC1
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_TVENC_HTIMINGSYNC1               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x0))
+#define HW_TVENC_HTIMINGSYNC1_SET           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x4))
+#define HW_TVENC_HTIMINGSYNC1_CLR           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0x8))
+#define HW_TVENC_HTIMINGSYNC1_TOG           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x50 + 0xc))
+#define BP_TVENC_HTIMINGSYNC1_RSRVD2        26
+#define BM_TVENC_HTIMINGSYNC1_RSRVD2        0xfc000000
+#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v)     (((v) << 26) & 0xfc000000)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND    16
+#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND    0x3ff0000
+#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v) (((v) << 16) & 0x3ff0000)
+#define BP_TVENC_HTIMINGSYNC1_RSRVD1        10
+#define BM_TVENC_HTIMINGSYNC1_RSRVD1        0xfc00
+#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v)     (((v) << 10) & 0xfc00)
+#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND    0
+#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND    0x3ff
+#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v) (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_HTIMINGACTIVE
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_TVENC_HTIMINGACTIVE              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x0))
+#define HW_TVENC_HTIMINGACTIVE_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x4))
+#define HW_TVENC_HTIMINGACTIVE_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0x8))
+#define HW_TVENC_HTIMINGACTIVE_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x60 + 0xc))
+#define BP_TVENC_HTIMINGACTIVE_RSRVD2       26
+#define BM_TVENC_HTIMINGACTIVE_RSRVD2       0xfc000000
+#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v)    (((v) << 26) & 0xfc000000)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_END     16
+#define BM_TVENC_HTIMINGACTIVE_ACTV_END     0x3ff0000
+#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v)  (((v) << 16) & 0x3ff0000)
+#define BP_TVENC_HTIMINGACTIVE_RSRVD1       10
+#define BM_TVENC_HTIMINGACTIVE_RSRVD1       0xfc00
+#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v)    (((v) << 10) & 0xfc00)
+#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT    0
+#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT    0x3ff
+#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v) (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_HTIMINGBURST0
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_TVENC_HTIMINGBURST0                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x0))
+#define HW_TVENC_HTIMINGBURST0_SET              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x4))
+#define HW_TVENC_HTIMINGBURST0_CLR              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0x8))
+#define HW_TVENC_HTIMINGBURST0_TOG              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x70 + 0xc))
+#define BP_TVENC_HTIMINGBURST0_RSRVD2           26
+#define BM_TVENC_HTIMINGBURST0_RSRVD2           0xfc000000
+#define BF_TVENC_HTIMINGBURST0_RSRVD2(v)        (((v) << 26) & 0xfc000000)
+#define BP_TVENC_HTIMINGBURST0_WBRST_STRT       16
+#define BM_TVENC_HTIMINGBURST0_WBRST_STRT       0x3ff0000
+#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v)    (((v) << 16) & 0x3ff0000)
+#define BP_TVENC_HTIMINGBURST0_RSRVD1           10
+#define BM_TVENC_HTIMINGBURST0_RSRVD1           0xfc00
+#define BF_TVENC_HTIMINGBURST0_RSRVD1(v)        (((v) << 10) & 0xfc00)
+#define BP_TVENC_HTIMINGBURST0_NBRST_STRT       0
+#define BM_TVENC_HTIMINGBURST0_NBRST_STRT       0x3ff
+#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_HTIMINGBURST1
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_TVENC_HTIMINGBURST1              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x0))
+#define HW_TVENC_HTIMINGBURST1_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x4))
+#define HW_TVENC_HTIMINGBURST1_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0x8))
+#define HW_TVENC_HTIMINGBURST1_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x80 + 0xc))
+#define BP_TVENC_HTIMINGBURST1_RSRVD1       10
+#define BM_TVENC_HTIMINGBURST1_RSRVD1       0xfffffc00
+#define BF_TVENC_HTIMINGBURST1_RSRVD1(v)    (((v) << 10) & 0xfffffc00)
+#define BP_TVENC_HTIMINGBURST1_BRST_END     0
+#define BM_TVENC_HTIMINGBURST1_BRST_END     0x3ff
+#define BF_TVENC_HTIMINGBURST1_BRST_END(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_VTIMING0
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_TVENC_VTIMING0                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x0))
+#define HW_TVENC_VTIMING0_SET               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x4))
+#define HW_TVENC_VTIMING0_CLR               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0x8))
+#define HW_TVENC_VTIMING0_TOG               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x90 + 0xc))
+#define BP_TVENC_VTIMING0_RSRVD3            26
+#define BM_TVENC_VTIMING0_RSRVD3            0xfc000000
+#define BF_TVENC_VTIMING0_RSRVD3(v)         (((v) << 26) & 0xfc000000)
+#define BP_TVENC_VTIMING0_VSTRT_PREEQ       16
+#define BM_TVENC_VTIMING0_VSTRT_PREEQ       0x3ff0000
+#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v)    (((v) << 16) & 0x3ff0000)
+#define BP_TVENC_VTIMING0_RSRVD2            14
+#define BM_TVENC_VTIMING0_RSRVD2            0xc000
+#define BF_TVENC_VTIMING0_RSRVD2(v)         (((v) << 14) & 0xc000)
+#define BP_TVENC_VTIMING0_VSTRT_ACTV        8
+#define BM_TVENC_VTIMING0_VSTRT_ACTV        0x3f00
+#define BF_TVENC_VTIMING0_VSTRT_ACTV(v)     (((v) << 8) & 0x3f00)
+#define BP_TVENC_VTIMING0_RSRVD1            6
+#define BM_TVENC_VTIMING0_RSRVD1            0xc0
+#define BF_TVENC_VTIMING0_RSRVD1(v)         (((v) << 6) & 0xc0)
+#define BP_TVENC_VTIMING0_VSTRT_SUBPH       0
+#define BM_TVENC_VTIMING0_VSTRT_SUBPH       0x3f
+#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v)    (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_TVENC_VTIMING1
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_TVENC_VTIMING1                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x0))
+#define HW_TVENC_VTIMING1_SET               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x4))
+#define HW_TVENC_VTIMING1_CLR               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0x8))
+#define HW_TVENC_VTIMING1_TOG               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xa0 + 0xc))
+#define BP_TVENC_VTIMING1_RSRVD3            30
+#define BM_TVENC_VTIMING1_RSRVD3            0xc0000000
+#define BF_TVENC_VTIMING1_RSRVD3(v)         (((v) << 30) & 0xc0000000)
+#define BP_TVENC_VTIMING1_VSTRT_POSTEQ      24
+#define BM_TVENC_VTIMING1_VSTRT_POSTEQ      0x3f000000
+#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v)   (((v) << 24) & 0x3f000000)
+#define BP_TVENC_VTIMING1_RSRVD2            22
+#define BM_TVENC_VTIMING1_RSRVD2            0xc00000
+#define BF_TVENC_VTIMING1_RSRVD2(v)         (((v) << 22) & 0xc00000)
+#define BP_TVENC_VTIMING1_VSTRT_SERRA       16
+#define BM_TVENC_VTIMING1_VSTRT_SERRA       0x3f0000
+#define BF_TVENC_VTIMING1_VSTRT_SERRA(v)    (((v) << 16) & 0x3f0000)
+#define BP_TVENC_VTIMING1_RSRVD1            10
+#define BM_TVENC_VTIMING1_RSRVD1            0xfc00
+#define BF_TVENC_VTIMING1_RSRVD1(v)         (((v) << 10) & 0xfc00)
+#define BP_TVENC_VTIMING1_LAST_FLD_LN       0
+#define BM_TVENC_VTIMING1_LAST_FLD_LN       0x3ff
+#define BF_TVENC_VTIMING1_LAST_FLD_LN(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_MISC
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_TVENC_MISC                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x0))
+#define HW_TVENC_MISC_SET                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x4))
+#define HW_TVENC_MISC_CLR                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0x8))
+#define HW_TVENC_MISC_TOG                   (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xb0 + 0xc))
+#define BP_TVENC_MISC_RSRVD3                25
+#define BM_TVENC_MISC_RSRVD3                0xfe000000
+#define BF_TVENC_MISC_RSRVD3(v)             (((v) << 25) & 0xfe000000)
+#define BP_TVENC_MISC_LPF_RST_OFF           16
+#define BM_TVENC_MISC_LPF_RST_OFF           0x1ff0000
+#define BF_TVENC_MISC_LPF_RST_OFF(v)        (((v) << 16) & 0x1ff0000)
+#define BP_TVENC_MISC_RSRVD2                12
+#define BM_TVENC_MISC_RSRVD2                0xf000
+#define BF_TVENC_MISC_RSRVD2(v)             (((v) << 12) & 0xf000)
+#define BP_TVENC_MISC_NTSC_LN_CNT           11
+#define BM_TVENC_MISC_NTSC_LN_CNT           0x800
+#define BF_TVENC_MISC_NTSC_LN_CNT(v)        (((v) << 11) & 0x800)
+#define BP_TVENC_MISC_PAL_FSC_PHASE_ALT     10
+#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT     0x400
+#define BF_TVENC_MISC_PAL_FSC_PHASE_ALT(v)  (((v) << 10) & 0x400)
+#define BP_TVENC_MISC_FSC_PHASE_RST         8
+#define BM_TVENC_MISC_FSC_PHASE_RST         0x300
+#define BF_TVENC_MISC_FSC_PHASE_RST(v)      (((v) << 8) & 0x300)
+#define BP_TVENC_MISC_BRUCHB                6
+#define BM_TVENC_MISC_BRUCHB                0xc0
+#define BF_TVENC_MISC_BRUCHB(v)             (((v) << 6) & 0xc0)
+#define BP_TVENC_MISC_AGC_LVL_CTRL          4
+#define BM_TVENC_MISC_AGC_LVL_CTRL          0x30
+#define BF_TVENC_MISC_AGC_LVL_CTRL(v)       (((v) << 4) & 0x30)
+#define BP_TVENC_MISC_RSRVD1                3
+#define BM_TVENC_MISC_RSRVD1                0x8
+#define BF_TVENC_MISC_RSRVD1(v)             (((v) << 3) & 0x8)
+#define BP_TVENC_MISC_CS_INVERT_CTRL        2
+#define BM_TVENC_MISC_CS_INVERT_CTRL        0x4
+#define BF_TVENC_MISC_CS_INVERT_CTRL(v)     (((v) << 2) & 0x4)
+#define BP_TVENC_MISC_Y_BLANK_CTRL          0
+#define BM_TVENC_MISC_Y_BLANK_CTRL          0x3
+#define BF_TVENC_MISC_Y_BLANK_CTRL(v)       (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_TVENC_COLORSUB0
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_TVENC_COLORSUB0              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x0))
+#define HW_TVENC_COLORSUB0_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x4))
+#define HW_TVENC_COLORSUB0_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0x8))
+#define HW_TVENC_COLORSUB0_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xc0 + 0xc))
+#define BP_TVENC_COLORSUB0_PHASE_INC    0
+#define BM_TVENC_COLORSUB0_PHASE_INC    0xffffffff
+#define BF_TVENC_COLORSUB0_PHASE_INC(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_TVENC_COLORSUB1
+ * Address: 0xd0
+ * SCT: yes
+*/
+#define HW_TVENC_COLORSUB1                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x0))
+#define HW_TVENC_COLORSUB1_SET              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x4))
+#define HW_TVENC_COLORSUB1_CLR              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0x8))
+#define HW_TVENC_COLORSUB1_TOG              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xd0 + 0xc))
+#define BP_TVENC_COLORSUB1_PHASE_OFFSET     0
+#define BM_TVENC_COLORSUB1_PHASE_OFFSET     0xffffffff
+#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_TVENC_COPYPROTECT
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_TVENC_COPYPROTECT                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x0))
+#define HW_TVENC_COPYPROTECT_SET                (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x4))
+#define HW_TVENC_COPYPROTECT_CLR                (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0x8))
+#define HW_TVENC_COPYPROTECT_TOG                (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xe0 + 0xc))
+#define BP_TVENC_COPYPROTECT_RSRVD1             16
+#define BM_TVENC_COPYPROTECT_RSRVD1             0xffff0000
+#define BF_TVENC_COPYPROTECT_RSRVD1(v)          (((v) << 16) & 0xffff0000)
+#define BP_TVENC_COPYPROTECT_WSS_ENBL           15
+#define BM_TVENC_COPYPROTECT_WSS_ENBL           0x8000
+#define BF_TVENC_COPYPROTECT_WSS_ENBL(v)        (((v) << 15) & 0x8000)
+#define BP_TVENC_COPYPROTECT_CGMS_ENBL          14
+#define BM_TVENC_COPYPROTECT_CGMS_ENBL          0x4000
+#define BF_TVENC_COPYPROTECT_CGMS_ENBL(v)       (((v) << 14) & 0x4000)
+#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA      0
+#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA      0x3fff
+#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v)   (((v) << 0) & 0x3fff)
+
+/**
+ * Register: HW_TVENC_CLOSEDCAPTION
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_TVENC_CLOSEDCAPTION              (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x0))
+#define HW_TVENC_CLOSEDCAPTION_SET          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x4))
+#define HW_TVENC_CLOSEDCAPTION_CLR          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0x8))
+#define HW_TVENC_CLOSEDCAPTION_TOG          (*(volatile unsigned long *)(REGS_TVENC_BASE + 0xf0 + 0xc))
+#define BP_TVENC_CLOSEDCAPTION_RSRVD1       20
+#define BM_TVENC_CLOSEDCAPTION_RSRVD1       0xfff00000
+#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v)    (((v) << 20) & 0xfff00000)
+#define BP_TVENC_CLOSEDCAPTION_CC_ENBL      18
+#define BM_TVENC_CLOSEDCAPTION_CC_ENBL      0xc0000
+#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v)   (((v) << 18) & 0xc0000)
+#define BP_TVENC_CLOSEDCAPTION_CC_FILL      16
+#define BM_TVENC_CLOSEDCAPTION_CC_FILL      0x30000
+#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v)   (((v) << 16) & 0x30000)
+#define BP_TVENC_CLOSEDCAPTION_CC_DATA      0
+#define BM_TVENC_CLOSEDCAPTION_CC_DATA      0xffff
+#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TVENC_COLORBURST
+ * Address: 0x140
+ * SCT: yes
+*/
+#define HW_TVENC_COLORBURST             (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x0))
+#define HW_TVENC_COLORBURST_SET         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x4))
+#define HW_TVENC_COLORBURST_CLR         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0x8))
+#define HW_TVENC_COLORBURST_TOG         (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x140 + 0xc))
+#define BP_TVENC_COLORBURST_NBA         24
+#define BM_TVENC_COLORBURST_NBA         0xff000000
+#define BF_TVENC_COLORBURST_NBA(v)      (((v) << 24) & 0xff000000)
+#define BP_TVENC_COLORBURST_PBA         16
+#define BM_TVENC_COLORBURST_PBA         0xff0000
+#define BF_TVENC_COLORBURST_PBA(v)      (((v) << 16) & 0xff0000)
+#define BP_TVENC_COLORBURST_RSRVD1      12
+#define BM_TVENC_COLORBURST_RSRVD1      0xf000
+#define BF_TVENC_COLORBURST_RSRVD1(v)   (((v) << 12) & 0xf000)
+#define BP_TVENC_COLORBURST_RSRVD2      0
+#define BM_TVENC_COLORBURST_RSRVD2      0xfff
+#define BF_TVENC_COLORBURST_RSRVD2(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_TVENC_MACROVISION0
+ * Address: 0x150
+ * SCT: yes
+*/
+#define HW_TVENC_MACROVISION0           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x0))
+#define HW_TVENC_MACROVISION0_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x4))
+#define HW_TVENC_MACROVISION0_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0x8))
+#define HW_TVENC_MACROVISION0_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x150 + 0xc))
+#define BP_TVENC_MACROVISION0_DATA      0
+#define BM_TVENC_MACROVISION0_DATA      0xffffffff
+#define BF_TVENC_MACROVISION0_DATA(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_TVENC_MACROVISION1
+ * Address: 0x160
+ * SCT: yes
+*/
+#define HW_TVENC_MACROVISION1           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x0))
+#define HW_TVENC_MACROVISION1_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x4))
+#define HW_TVENC_MACROVISION1_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0x8))
+#define HW_TVENC_MACROVISION1_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x160 + 0xc))
+#define BP_TVENC_MACROVISION1_DATA      0
+#define BM_TVENC_MACROVISION1_DATA      0xffffffff
+#define BF_TVENC_MACROVISION1_DATA(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_TVENC_MACROVISION2
+ * Address: 0x170
+ * SCT: yes
+*/
+#define HW_TVENC_MACROVISION2           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x0))
+#define HW_TVENC_MACROVISION2_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x4))
+#define HW_TVENC_MACROVISION2_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0x8))
+#define HW_TVENC_MACROVISION2_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x170 + 0xc))
+#define BP_TVENC_MACROVISION2_DATA      0
+#define BM_TVENC_MACROVISION2_DATA      0xffffffff
+#define BF_TVENC_MACROVISION2_DATA(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_TVENC_MACROVISION3
+ * Address: 0x180
+ * SCT: yes
+*/
+#define HW_TVENC_MACROVISION3           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x0))
+#define HW_TVENC_MACROVISION3_SET       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x4))
+#define HW_TVENC_MACROVISION3_CLR       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0x8))
+#define HW_TVENC_MACROVISION3_TOG       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x180 + 0xc))
+#define BP_TVENC_MACROVISION3_DATA      0
+#define BM_TVENC_MACROVISION3_DATA      0xffffffff
+#define BF_TVENC_MACROVISION3_DATA(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_TVENC_MACROVISION4
+ * Address: 0x190
+ * SCT: yes
+*/
+#define HW_TVENC_MACROVISION4               (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x0))
+#define HW_TVENC_MACROVISION4_SET           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x4))
+#define HW_TVENC_MACROVISION4_CLR           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0x8))
+#define HW_TVENC_MACROVISION4_TOG           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x190 + 0xc))
+#define BP_TVENC_MACROVISION4_RSRVD2        24
+#define BM_TVENC_MACROVISION4_RSRVD2        0xff000000
+#define BF_TVENC_MACROVISION4_RSRVD2(v)     (((v) << 24) & 0xff000000)
+#define BP_TVENC_MACROVISION4_MACV_TST      16
+#define BM_TVENC_MACROVISION4_MACV_TST      0xff0000
+#define BF_TVENC_MACROVISION4_MACV_TST(v)   (((v) << 16) & 0xff0000)
+#define BP_TVENC_MACROVISION4_RSRVD1        11
+#define BM_TVENC_MACROVISION4_RSRVD1        0xf800
+#define BF_TVENC_MACROVISION4_RSRVD1(v)     (((v) << 11) & 0xf800)
+#define BP_TVENC_MACROVISION4_DATA          0
+#define BM_TVENC_MACROVISION4_DATA          0x7ff
+#define BF_TVENC_MACROVISION4_DATA(v)       (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_TVENC_DACCTRL
+ * Address: 0x1a0
+ * SCT: yes
+*/
+#define HW_TVENC_DACCTRL                        (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x0))
+#define HW_TVENC_DACCTRL_SET                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x4))
+#define HW_TVENC_DACCTRL_CLR                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0x8))
+#define HW_TVENC_DACCTRL_TOG                    (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1a0 + 0xc))
+#define BP_TVENC_DACCTRL_TEST3                  31
+#define BM_TVENC_DACCTRL_TEST3                  0x80000000
+#define BF_TVENC_DACCTRL_TEST3(v)               (((v) << 31) & 0x80000000)
+#define BP_TVENC_DACCTRL_RSRVD1                 30
+#define BM_TVENC_DACCTRL_RSRVD1                 0x40000000
+#define BF_TVENC_DACCTRL_RSRVD1(v)              (((v) << 30) & 0x40000000)
+#define BP_TVENC_DACCTRL_RSRVD2                 29
+#define BM_TVENC_DACCTRL_RSRVD2                 0x20000000
+#define BF_TVENC_DACCTRL_RSRVD2(v)              (((v) << 29) & 0x20000000)
+#define BP_TVENC_DACCTRL_JACK1_DIS_DET_EN       28
+#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN       0x10000000
+#define BF_TVENC_DACCTRL_JACK1_DIS_DET_EN(v)    (((v) << 28) & 0x10000000)
+#define BP_TVENC_DACCTRL_TEST2                  27
+#define BM_TVENC_DACCTRL_TEST2                  0x8000000
+#define BF_TVENC_DACCTRL_TEST2(v)               (((v) << 27) & 0x8000000)
+#define BP_TVENC_DACCTRL_RSRVD3                 26
+#define BM_TVENC_DACCTRL_RSRVD3                 0x4000000
+#define BF_TVENC_DACCTRL_RSRVD3(v)              (((v) << 26) & 0x4000000)
+#define BP_TVENC_DACCTRL_RSRVD4                 25
+#define BM_TVENC_DACCTRL_RSRVD4                 0x2000000
+#define BF_TVENC_DACCTRL_RSRVD4(v)              (((v) << 25) & 0x2000000)
+#define BP_TVENC_DACCTRL_JACK1_DET_EN           24
+#define BM_TVENC_DACCTRL_JACK1_DET_EN           0x1000000
+#define BF_TVENC_DACCTRL_JACK1_DET_EN(v)        (((v) << 24) & 0x1000000)
+#define BP_TVENC_DACCTRL_TEST1                  23
+#define BM_TVENC_DACCTRL_TEST1                  0x800000
+#define BF_TVENC_DACCTRL_TEST1(v)               (((v) << 23) & 0x800000)
+#define BP_TVENC_DACCTRL_DISABLE_GND_DETECT     22
+#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT     0x400000
+#define BF_TVENC_DACCTRL_DISABLE_GND_DETECT(v)  (((v) << 22) & 0x400000)
+#define BP_TVENC_DACCTRL_JACK_DIS_ADJ           20
+#define BM_TVENC_DACCTRL_JACK_DIS_ADJ           0x300000
+#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v)        (((v) << 20) & 0x300000)
+#define BP_TVENC_DACCTRL_GAINDN                 19
+#define BM_TVENC_DACCTRL_GAINDN                 0x80000
+#define BF_TVENC_DACCTRL_GAINDN(v)              (((v) << 19) & 0x80000)
+#define BP_TVENC_DACCTRL_GAINUP                 18
+#define BM_TVENC_DACCTRL_GAINUP                 0x40000
+#define BF_TVENC_DACCTRL_GAINUP(v)              (((v) << 18) & 0x40000)
+#define BP_TVENC_DACCTRL_INVERT_CLK             17
+#define BM_TVENC_DACCTRL_INVERT_CLK             0x20000
+#define BF_TVENC_DACCTRL_INVERT_CLK(v)          (((v) << 17) & 0x20000)
+#define BP_TVENC_DACCTRL_SELECT_CLK             16
+#define BM_TVENC_DACCTRL_SELECT_CLK             0x10000
+#define BF_TVENC_DACCTRL_SELECT_CLK(v)          (((v) << 16) & 0x10000)
+#define BP_TVENC_DACCTRL_BYPASS_ACT_CASCODE     15
+#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE     0x8000
+#define BF_TVENC_DACCTRL_BYPASS_ACT_CASCODE(v)  (((v) << 15) & 0x8000)
+#define BP_TVENC_DACCTRL_RSRVD5                 14
+#define BM_TVENC_DACCTRL_RSRVD5                 0x4000
+#define BF_TVENC_DACCTRL_RSRVD5(v)              (((v) << 14) & 0x4000)
+#define BP_TVENC_DACCTRL_RSRVD6                 13
+#define BM_TVENC_DACCTRL_RSRVD6                 0x2000
+#define BF_TVENC_DACCTRL_RSRVD6(v)              (((v) << 13) & 0x2000)
+#define BP_TVENC_DACCTRL_PWRUP1                 12
+#define BM_TVENC_DACCTRL_PWRUP1                 0x1000
+#define BF_TVENC_DACCTRL_PWRUP1(v)              (((v) << 12) & 0x1000)
+#define BP_TVENC_DACCTRL_WELL_TOVDD             11
+#define BM_TVENC_DACCTRL_WELL_TOVDD             0x800
+#define BF_TVENC_DACCTRL_WELL_TOVDD(v)          (((v) << 11) & 0x800)
+#define BP_TVENC_DACCTRL_RSRVD7                 10
+#define BM_TVENC_DACCTRL_RSRVD7                 0x400
+#define BF_TVENC_DACCTRL_RSRVD7(v)              (((v) << 10) & 0x400)
+#define BP_TVENC_DACCTRL_RSRVD8                 9
+#define BM_TVENC_DACCTRL_RSRVD8                 0x200
+#define BF_TVENC_DACCTRL_RSRVD8(v)              (((v) << 9) & 0x200)
+#define BP_TVENC_DACCTRL_DUMP_TOVDD1            8
+#define BM_TVENC_DACCTRL_DUMP_TOVDD1            0x100
+#define BF_TVENC_DACCTRL_DUMP_TOVDD1(v)         (((v) << 8) & 0x100)
+#define BP_TVENC_DACCTRL_LOWER_SIGNAL           7
+#define BM_TVENC_DACCTRL_LOWER_SIGNAL           0x80
+#define BF_TVENC_DACCTRL_LOWER_SIGNAL(v)        (((v) << 7) & 0x80)
+#define BP_TVENC_DACCTRL_RVAL                   4
+#define BM_TVENC_DACCTRL_RVAL                   0x70
+#define BF_TVENC_DACCTRL_RVAL(v)                (((v) << 4) & 0x70)
+#define BP_TVENC_DACCTRL_NO_INTERNAL_TERM       3
+#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM       0x8
+#define BF_TVENC_DACCTRL_NO_INTERNAL_TERM(v)    (((v) << 3) & 0x8)
+#define BP_TVENC_DACCTRL_HALF_CURRENT           2
+#define BM_TVENC_DACCTRL_HALF_CURRENT           0x4
+#define BF_TVENC_DACCTRL_HALF_CURRENT(v)        (((v) << 2) & 0x4)
+#define BP_TVENC_DACCTRL_CASC_ADJ               0
+#define BM_TVENC_DACCTRL_CASC_ADJ               0x3
+#define BF_TVENC_DACCTRL_CASC_ADJ(v)            (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_TVENC_DACSTATUS
+ * Address: 0x1b0
+ * SCT: yes
+*/
+#define HW_TVENC_DACSTATUS                      (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x0))
+#define HW_TVENC_DACSTATUS_SET                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x4))
+#define HW_TVENC_DACSTATUS_CLR                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0x8))
+#define HW_TVENC_DACSTATUS_TOG                  (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1b0 + 0xc))
+#define BP_TVENC_DACSTATUS_RSRVD1               13
+#define BM_TVENC_DACSTATUS_RSRVD1               0xffffe000
+#define BF_TVENC_DACSTATUS_RSRVD1(v)            (((v) << 13) & 0xffffe000)
+#define BP_TVENC_DACSTATUS_RSRVD2               12
+#define BM_TVENC_DACSTATUS_RSRVD2               0x1000
+#define BF_TVENC_DACSTATUS_RSRVD2(v)            (((v) << 12) & 0x1000)
+#define BP_TVENC_DACSTATUS_RSRVD3               11
+#define BM_TVENC_DACSTATUS_RSRVD3               0x800
+#define BF_TVENC_DACSTATUS_RSRVD3(v)            (((v) << 11) & 0x800)
+#define BP_TVENC_DACSTATUS_JACK1_DET_STATUS     10
+#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS     0x400
+#define BF_TVENC_DACSTATUS_JACK1_DET_STATUS(v)  (((v) << 10) & 0x400)
+#define BP_TVENC_DACSTATUS_RSRVD4               9
+#define BM_TVENC_DACSTATUS_RSRVD4               0x200
+#define BF_TVENC_DACSTATUS_RSRVD4(v)            (((v) << 9) & 0x200)
+#define BP_TVENC_DACSTATUS_RSRVD5               8
+#define BM_TVENC_DACSTATUS_RSRVD5               0x100
+#define BF_TVENC_DACSTATUS_RSRVD5(v)            (((v) << 8) & 0x100)
+#define BP_TVENC_DACSTATUS_JACK1_GROUNDED       7
+#define BM_TVENC_DACSTATUS_JACK1_GROUNDED       0x80
+#define BF_TVENC_DACSTATUS_JACK1_GROUNDED(v)    (((v) << 7) & 0x80)
+#define BP_TVENC_DACSTATUS_RSRVD6               6
+#define BM_TVENC_DACSTATUS_RSRVD6               0x40
+#define BF_TVENC_DACSTATUS_RSRVD6(v)            (((v) << 6) & 0x40)
+#define BP_TVENC_DACSTATUS_RSRVD7               5
+#define BM_TVENC_DACSTATUS_RSRVD7               0x20
+#define BF_TVENC_DACSTATUS_RSRVD7(v)            (((v) << 5) & 0x20)
+#define BP_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ    4
+#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ    0x10
+#define BF_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ(v) (((v) << 4) & 0x10)
+#define BP_TVENC_DACSTATUS_RSRVD8               3
+#define BM_TVENC_DACSTATUS_RSRVD8               0x8
+#define BF_TVENC_DACSTATUS_RSRVD8(v)            (((v) << 3) & 0x8)
+#define BP_TVENC_DACSTATUS_RSRVD9               2
+#define BM_TVENC_DACSTATUS_RSRVD9               0x4
+#define BF_TVENC_DACSTATUS_RSRVD9(v)            (((v) << 2) & 0x4)
+#define BP_TVENC_DACSTATUS_JACK1_DET_IRQ        1
+#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ        0x2
+#define BF_TVENC_DACSTATUS_JACK1_DET_IRQ(v)     (((v) << 1) & 0x2)
+#define BP_TVENC_DACSTATUS_ENIRQ_JACK           0
+#define BM_TVENC_DACSTATUS_ENIRQ_JACK           0x1
+#define BF_TVENC_DACSTATUS_ENIRQ_JACK(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_TVENC_VDACTEST
+ * Address: 0x1c0
+ * SCT: yes
+*/
+#define HW_TVENC_VDACTEST                           (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x0))
+#define HW_TVENC_VDACTEST_SET                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x4))
+#define HW_TVENC_VDACTEST_CLR                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0x8))
+#define HW_TVENC_VDACTEST_TOG                       (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1c0 + 0xc))
+#define BP_TVENC_VDACTEST_RSRVD1                    14
+#define BM_TVENC_VDACTEST_RSRVD1                    0xffffc000
+#define BF_TVENC_VDACTEST_RSRVD1(v)                 (((v) << 14) & 0xffffc000)
+#define BP_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN       13
+#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN       0x2000
+#define BF_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN(v)    (((v) << 13) & 0x2000)
+#define BP_TVENC_VDACTEST_BYPASS_PIX_INT            12
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT            0x1000
+#define BF_TVENC_VDACTEST_BYPASS_PIX_INT(v)         (((v) << 12) & 0x1000)
+#define BP_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP      11
+#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP      0x800
+#define BF_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP(v)   (((v) << 11) & 0x800)
+#define BP_TVENC_VDACTEST_TEST_FIFO_FULL            10
+#define BM_TVENC_VDACTEST_TEST_FIFO_FULL            0x400
+#define BF_TVENC_VDACTEST_TEST_FIFO_FULL(v)         (((v) << 10) & 0x400)
+#define BP_TVENC_VDACTEST_DATA                      0
+#define BM_TVENC_VDACTEST_DATA                      0x3ff
+#define BF_TVENC_VDACTEST_DATA(v)                   (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_TVENC_VERSION
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_TVENC_VERSION            (*(volatile unsigned long *)(REGS_TVENC_BASE + 0x1d0))
+#define BP_TVENC_VERSION_MAJOR      24
+#define BM_TVENC_VERSION_MAJOR      0xff000000
+#define BF_TVENC_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_TVENC_VERSION_MINOR      16
+#define BM_TVENC_VERSION_MINOR      0xff0000
+#define BF_TVENC_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_TVENC_VERSION_STEP       0
+#define BM_TVENC_VERSION_STEP       0xffff
+#define BF_TVENC_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__IMX233__TVENC__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h b/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h
new file mode 100644
index 0000000000..11cf8316a6
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-uartapp.h
@@ -0,0 +1,497 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__UARTAPP__H__
+#define __HEADERGEN__IMX233__UARTAPP__H__
+
+#define REGS_UARTAPP_BASE(i) ((i) == 1 ? 0x8006c000 : 0x8006e000)
+
+#define REGS_UARTAPP_VERSION "3.2.0"
+
+/**
+ * Register: HW_UARTAPP_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL0(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x0))
+#define HW_UARTAPP_CTRL0_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x4))
+#define HW_UARTAPP_CTRL0_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x8))
+#define HW_UARTAPP_CTRL0_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0xc))
+#define BP_UARTAPP_CTRL0_SFTRST         31
+#define BM_UARTAPP_CTRL0_SFTRST         0x80000000
+#define BF_UARTAPP_CTRL0_SFTRST(v)      (((v) << 31) & 0x80000000)
+#define BP_UARTAPP_CTRL0_CLKGATE        30
+#define BM_UARTAPP_CTRL0_CLKGATE        0x40000000
+#define BF_UARTAPP_CTRL0_CLKGATE(v)     (((v) << 30) & 0x40000000)
+#define BP_UARTAPP_CTRL0_RUN            29
+#define BM_UARTAPP_CTRL0_RUN            0x20000000
+#define BF_UARTAPP_CTRL0_RUN(v)         (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_CTRL0_RX_SOURCE      28
+#define BM_UARTAPP_CTRL0_RX_SOURCE      0x10000000
+#define BF_UARTAPP_CTRL0_RX_SOURCE(v)   (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL0_RXTO_ENABLE    27
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x8000000
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 27) & 0x8000000)
+#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
+#define BM_UARTAPP_CTRL0_RXTIMEOUT      0x7ff0000
+#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)   (((v) << 16) & 0x7ff0000)
+#define BP_UARTAPP_CTRL0_XFER_COUNT     0
+#define BM_UARTAPP_CTRL0_XFER_COUNT     0xffff
+#define BF_UARTAPP_CTRL0_XFER_COUNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL1(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x0))
+#define HW_UARTAPP_CTRL1_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x4))
+#define HW_UARTAPP_CTRL1_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x8))
+#define HW_UARTAPP_CTRL1_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0xc))
+#define BP_UARTAPP_CTRL1_RSVD2          29
+#define BM_UARTAPP_CTRL1_RSVD2          0xe0000000
+#define BF_UARTAPP_CTRL1_RSVD2(v)       (((v) << 29) & 0xe0000000)
+#define BP_UARTAPP_CTRL1_RUN            28
+#define BM_UARTAPP_CTRL1_RUN            0x10000000
+#define BF_UARTAPP_CTRL1_RUN(v)         (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL1_RSVD1          16
+#define BM_UARTAPP_CTRL1_RSVD1          0xfff0000
+#define BF_UARTAPP_CTRL1_RSVD1(v)       (((v) << 16) & 0xfff0000)
+#define BP_UARTAPP_CTRL1_XFER_COUNT     0
+#define BM_UARTAPP_CTRL1_XFER_COUNT     0xffff
+#define BF_UARTAPP_CTRL1_XFER_COUNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL2(d)                         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x0))
+#define HW_UARTAPP_CTRL2_SET(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x4))
+#define HW_UARTAPP_CTRL2_CLR(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x8))
+#define HW_UARTAPP_CTRL2_TOG(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0xc))
+#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
+#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
+#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) << 31) & 0x80000000)
+#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
+#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
+#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) << 30) & 0x40000000)
+#define BP_UARTAPP_CTRL2_INVERT_TX                  29
+#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
+#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_CTRL2_INVERT_RX                  28
+#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
+#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL2_RTS_SEMAPHORE              27
+#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE              0x8000000
+#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v)           (((v) << 27) & 0x8000000)
+#define BP_UARTAPP_CTRL2_DMAONERR                   26
+#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
+#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_CTRL2_TXDMAE                     25
+#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
+#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_CTRL2_RXDMAE                     24
+#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
+#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_CTRL2_RSVD2                      23
+#define BM_UARTAPP_CTRL2_RSVD2                      0x800000
+#define BF_UARTAPP_CTRL2_RSVD2(v)                   (((v) << 23) & 0x800000)
+#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
+#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
+#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) << 20) & 0x700000)
+#define BF_UARTAPP_CTRL2_RXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000)
+#define BP_UARTAPP_CTRL2_RSVD3                      19
+#define BM_UARTAPP_CTRL2_RSVD3                      0x80000
+#define BF_UARTAPP_CTRL2_RSVD3(v)                   (((v) << 19) & 0x80000)
+#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
+#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
+#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) << 16) & 0x70000)
+#define BF_UARTAPP_CTRL2_TXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000)
+#define BP_UARTAPP_CTRL2_CTSEN                      15
+#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
+#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) << 15) & 0x8000)
+#define BP_UARTAPP_CTRL2_RTSEN                      14
+#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
+#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) << 14) & 0x4000)
+#define BP_UARTAPP_CTRL2_OUT2                       13
+#define BM_UARTAPP_CTRL2_OUT2                       0x2000
+#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) << 13) & 0x2000)
+#define BP_UARTAPP_CTRL2_OUT1                       12
+#define BM_UARTAPP_CTRL2_OUT1                       0x1000
+#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) << 12) & 0x1000)
+#define BP_UARTAPP_CTRL2_RTS                        11
+#define BM_UARTAPP_CTRL2_RTS                        0x800
+#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) << 11) & 0x800)
+#define BP_UARTAPP_CTRL2_DTR                        10
+#define BM_UARTAPP_CTRL2_DTR                        0x400
+#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) << 10) & 0x400)
+#define BP_UARTAPP_CTRL2_RXE                        9
+#define BM_UARTAPP_CTRL2_RXE                        0x200
+#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) << 9) & 0x200)
+#define BP_UARTAPP_CTRL2_TXE                        8
+#define BM_UARTAPP_CTRL2_TXE                        0x100
+#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) << 8) & 0x100)
+#define BP_UARTAPP_CTRL2_LBE                        7
+#define BM_UARTAPP_CTRL2_LBE                        0x80
+#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) << 7) & 0x80)
+#define BP_UARTAPP_CTRL2_USE_LCR2                   6
+#define BM_UARTAPP_CTRL2_USE_LCR2                   0x40
+#define BF_UARTAPP_CTRL2_USE_LCR2(v)                (((v) << 6) & 0x40)
+#define BP_UARTAPP_CTRL2_RSVD4                      3
+#define BM_UARTAPP_CTRL2_RSVD4                      0x38
+#define BF_UARTAPP_CTRL2_RSVD4(v)                   (((v) << 3) & 0x38)
+#define BP_UARTAPP_CTRL2_SIRLP                      2
+#define BM_UARTAPP_CTRL2_SIRLP                      0x4
+#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) << 2) & 0x4)
+#define BP_UARTAPP_CTRL2_SIREN                      1
+#define BM_UARTAPP_CTRL2_SIREN                      0x2
+#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) << 1) & 0x2)
+#define BP_UARTAPP_CTRL2_UARTEN                     0
+#define BM_UARTAPP_CTRL2_UARTEN                     0x1
+#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_LINECTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_UARTAPP_LINECTRL(d)              (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x0))
+#define HW_UARTAPP_LINECTRL_SET(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x4))
+#define HW_UARTAPP_LINECTRL_CLR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x8))
+#define HW_UARTAPP_LINECTRL_TOG(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0xc))
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT     16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT     0xffff0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTAPP_LINECTRL_RSVD            14
+#define BM_UARTAPP_LINECTRL_RSVD            0xc000
+#define BF_UARTAPP_LINECTRL_RSVD(v)         (((v) << 14) & 0xc000)
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC    8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC    0x3f00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00)
+#define BP_UARTAPP_LINECTRL_SPS             7
+#define BM_UARTAPP_LINECTRL_SPS             0x80
+#define BF_UARTAPP_LINECTRL_SPS(v)          (((v) << 7) & 0x80)
+#define BP_UARTAPP_LINECTRL_WLEN            5
+#define BM_UARTAPP_LINECTRL_WLEN            0x60
+#define BF_UARTAPP_LINECTRL_WLEN(v)         (((v) << 5) & 0x60)
+#define BP_UARTAPP_LINECTRL_FEN             4
+#define BM_UARTAPP_LINECTRL_FEN             0x10
+#define BF_UARTAPP_LINECTRL_FEN(v)          (((v) << 4) & 0x10)
+#define BP_UARTAPP_LINECTRL_STP2            3
+#define BM_UARTAPP_LINECTRL_STP2            0x8
+#define BF_UARTAPP_LINECTRL_STP2(v)         (((v) << 3) & 0x8)
+#define BP_UARTAPP_LINECTRL_EPS             2
+#define BM_UARTAPP_LINECTRL_EPS             0x4
+#define BF_UARTAPP_LINECTRL_EPS(v)          (((v) << 2) & 0x4)
+#define BP_UARTAPP_LINECTRL_PEN             1
+#define BM_UARTAPP_LINECTRL_PEN             0x2
+#define BF_UARTAPP_LINECTRL_PEN(v)          (((v) << 1) & 0x2)
+#define BP_UARTAPP_LINECTRL_BRK             0
+#define BM_UARTAPP_LINECTRL_BRK             0x1
+#define BF_UARTAPP_LINECTRL_BRK(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_LINECTRL2
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_UARTAPP_LINECTRL2(d)                 (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x0))
+#define HW_UARTAPP_LINECTRL2_SET(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x4))
+#define HW_UARTAPP_LINECTRL2_CLR(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x8))
+#define HW_UARTAPP_LINECTRL2_TOG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0xc))
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT        16
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT        0xffff0000
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v)     (((v) << 16) & 0xffff0000)
+#define BP_UARTAPP_LINECTRL2_RSVD               14
+#define BM_UARTAPP_LINECTRL2_RSVD               0xc000
+#define BF_UARTAPP_LINECTRL2_RSVD(v)            (((v) << 14) & 0xc000)
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC       8
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC       0x3f00
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)    (((v) << 8) & 0x3f00)
+#define BP_UARTAPP_LINECTRL2_SPS                7
+#define BM_UARTAPP_LINECTRL2_SPS                0x80
+#define BF_UARTAPP_LINECTRL2_SPS(v)             (((v) << 7) & 0x80)
+#define BP_UARTAPP_LINECTRL2_WLEN               5
+#define BM_UARTAPP_LINECTRL2_WLEN               0x60
+#define BF_UARTAPP_LINECTRL2_WLEN(v)            (((v) << 5) & 0x60)
+#define BP_UARTAPP_LINECTRL2_FEN                4
+#define BM_UARTAPP_LINECTRL2_FEN                0x10
+#define BF_UARTAPP_LINECTRL2_FEN(v)             (((v) << 4) & 0x10)
+#define BP_UARTAPP_LINECTRL2_STP2               3
+#define BM_UARTAPP_LINECTRL2_STP2               0x8
+#define BF_UARTAPP_LINECTRL2_STP2(v)            (((v) << 3) & 0x8)
+#define BP_UARTAPP_LINECTRL2_EPS                2
+#define BM_UARTAPP_LINECTRL2_EPS                0x4
+#define BF_UARTAPP_LINECTRL2_EPS(v)             (((v) << 2) & 0x4)
+#define BP_UARTAPP_LINECTRL2_PEN                1
+#define BM_UARTAPP_LINECTRL2_PEN                0x2
+#define BF_UARTAPP_LINECTRL2_PEN(v)             (((v) << 1) & 0x2)
+#define BP_UARTAPP_LINECTRL2_RSVD1              0
+#define BM_UARTAPP_LINECTRL2_RSVD1              0x1
+#define BF_UARTAPP_LINECTRL2_RSVD1(v)           (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_INTR
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_UARTAPP_INTR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x0))
+#define HW_UARTAPP_INTR_SET(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x4))
+#define HW_UARTAPP_INTR_CLR(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x8))
+#define HW_UARTAPP_INTR_TOG(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0xc))
+#define BP_UARTAPP_INTR_RSVD1       27
+#define BM_UARTAPP_INTR_RSVD1       0xf8000000
+#define BF_UARTAPP_INTR_RSVD1(v)    (((v) << 27) & 0xf8000000)
+#define BP_UARTAPP_INTR_OEIEN       26
+#define BM_UARTAPP_INTR_OEIEN       0x4000000
+#define BF_UARTAPP_INTR_OEIEN(v)    (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_INTR_BEIEN       25
+#define BM_UARTAPP_INTR_BEIEN       0x2000000
+#define BF_UARTAPP_INTR_BEIEN(v)    (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_INTR_PEIEN       24
+#define BM_UARTAPP_INTR_PEIEN       0x1000000
+#define BF_UARTAPP_INTR_PEIEN(v)    (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_INTR_FEIEN       23
+#define BM_UARTAPP_INTR_FEIEN       0x800000
+#define BF_UARTAPP_INTR_FEIEN(v)    (((v) << 23) & 0x800000)
+#define BP_UARTAPP_INTR_RTIEN       22
+#define BM_UARTAPP_INTR_RTIEN       0x400000
+#define BF_UARTAPP_INTR_RTIEN(v)    (((v) << 22) & 0x400000)
+#define BP_UARTAPP_INTR_TXIEN       21
+#define BM_UARTAPP_INTR_TXIEN       0x200000
+#define BF_UARTAPP_INTR_TXIEN(v)    (((v) << 21) & 0x200000)
+#define BP_UARTAPP_INTR_RXIEN       20
+#define BM_UARTAPP_INTR_RXIEN       0x100000
+#define BF_UARTAPP_INTR_RXIEN(v)    (((v) << 20) & 0x100000)
+#define BP_UARTAPP_INTR_DSRMIEN     19
+#define BM_UARTAPP_INTR_DSRMIEN     0x80000
+#define BF_UARTAPP_INTR_DSRMIEN(v)  (((v) << 19) & 0x80000)
+#define BP_UARTAPP_INTR_DCDMIEN     18
+#define BM_UARTAPP_INTR_DCDMIEN     0x40000
+#define BF_UARTAPP_INTR_DCDMIEN(v)  (((v) << 18) & 0x40000)
+#define BP_UARTAPP_INTR_CTSMIEN     17
+#define BM_UARTAPP_INTR_CTSMIEN     0x20000
+#define BF_UARTAPP_INTR_CTSMIEN(v)  (((v) << 17) & 0x20000)
+#define BP_UARTAPP_INTR_RIMIEN      16
+#define BM_UARTAPP_INTR_RIMIEN      0x10000
+#define BF_UARTAPP_INTR_RIMIEN(v)   (((v) << 16) & 0x10000)
+#define BP_UARTAPP_INTR_RSVD2       11
+#define BM_UARTAPP_INTR_RSVD2       0xf800
+#define BF_UARTAPP_INTR_RSVD2(v)    (((v) << 11) & 0xf800)
+#define BP_UARTAPP_INTR_OEIS        10
+#define BM_UARTAPP_INTR_OEIS        0x400
+#define BF_UARTAPP_INTR_OEIS(v)     (((v) << 10) & 0x400)
+#define BP_UARTAPP_INTR_BEIS        9
+#define BM_UARTAPP_INTR_BEIS        0x200
+#define BF_UARTAPP_INTR_BEIS(v)     (((v) << 9) & 0x200)
+#define BP_UARTAPP_INTR_PEIS        8
+#define BM_UARTAPP_INTR_PEIS        0x100
+#define BF_UARTAPP_INTR_PEIS(v)     (((v) << 8) & 0x100)
+#define BP_UARTAPP_INTR_FEIS        7
+#define BM_UARTAPP_INTR_FEIS        0x80
+#define BF_UARTAPP_INTR_FEIS(v)     (((v) << 7) & 0x80)
+#define BP_UARTAPP_INTR_RTIS        6
+#define BM_UARTAPP_INTR_RTIS        0x40
+#define BF_UARTAPP_INTR_RTIS(v)     (((v) << 6) & 0x40)
+#define BP_UARTAPP_INTR_TXIS        5
+#define BM_UARTAPP_INTR_TXIS        0x20
+#define BF_UARTAPP_INTR_TXIS(v)     (((v) << 5) & 0x20)
+#define BP_UARTAPP_INTR_RXIS        4
+#define BM_UARTAPP_INTR_RXIS        0x10
+#define BF_UARTAPP_INTR_RXIS(v)     (((v) << 4) & 0x10)
+#define BP_UARTAPP_INTR_DSRMIS      3
+#define BM_UARTAPP_INTR_DSRMIS      0x8
+#define BF_UARTAPP_INTR_DSRMIS(v)   (((v) << 3) & 0x8)
+#define BP_UARTAPP_INTR_DCDMIS      2
+#define BM_UARTAPP_INTR_DCDMIS      0x4
+#define BF_UARTAPP_INTR_DCDMIS(v)   (((v) << 2) & 0x4)
+#define BP_UARTAPP_INTR_CTSMIS      1
+#define BM_UARTAPP_INTR_CTSMIS      0x2
+#define BF_UARTAPP_INTR_CTSMIS(v)   (((v) << 1) & 0x2)
+#define BP_UARTAPP_INTR_RIMIS       0
+#define BM_UARTAPP_INTR_RIMIS       0x1
+#define BF_UARTAPP_INTR_RIMIS(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_DATA
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_UARTAPP_DATA(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x60))
+#define BP_UARTAPP_DATA_DATA    0
+#define BM_UARTAPP_DATA_DATA    0xffffffff
+#define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_UARTAPP_STAT
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_UARTAPP_STAT(d)                      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x70))
+#define BP_UARTAPP_STAT_PRESENT                 31
+#define BM_UARTAPP_STAT_PRESENT                 0x80000000
+#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_PRESENT(v)              (((v) << 31) & 0x80000000)
+#define BF_UARTAPP_STAT_PRESENT_V(v)            ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_UARTAPP_STAT_HISPEED                 30
+#define BM_UARTAPP_STAT_HISPEED                 0x40000000
+#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_HISPEED(v)              (((v) << 30) & 0x40000000)
+#define BF_UARTAPP_STAT_HISPEED_V(v)            ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000)
+#define BP_UARTAPP_STAT_BUSY                    29
+#define BM_UARTAPP_STAT_BUSY                    0x20000000
+#define BF_UARTAPP_STAT_BUSY(v)                 (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_STAT_CTS                     28
+#define BM_UARTAPP_STAT_CTS                     0x10000000
+#define BF_UARTAPP_STAT_CTS(v)                  (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_STAT_TXFE                    27
+#define BM_UARTAPP_STAT_TXFE                    0x8000000
+#define BF_UARTAPP_STAT_TXFE(v)                 (((v) << 27) & 0x8000000)
+#define BP_UARTAPP_STAT_RXFF                    26
+#define BM_UARTAPP_STAT_RXFF                    0x4000000
+#define BF_UARTAPP_STAT_RXFF(v)                 (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_STAT_TXFF                    25
+#define BM_UARTAPP_STAT_TXFF                    0x2000000
+#define BF_UARTAPP_STAT_TXFF(v)                 (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_STAT_RXFE                    24
+#define BM_UARTAPP_STAT_RXFE                    0x1000000
+#define BF_UARTAPP_STAT_RXFE(v)                 (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
+#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
+#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) << 20) & 0xf00000)
+#define BP_UARTAPP_STAT_OERR                    19
+#define BM_UARTAPP_STAT_OERR                    0x80000
+#define BF_UARTAPP_STAT_OERR(v)                 (((v) << 19) & 0x80000)
+#define BP_UARTAPP_STAT_BERR                    18
+#define BM_UARTAPP_STAT_BERR                    0x40000
+#define BF_UARTAPP_STAT_BERR(v)                 (((v) << 18) & 0x40000)
+#define BP_UARTAPP_STAT_PERR                    17
+#define BM_UARTAPP_STAT_PERR                    0x20000
+#define BF_UARTAPP_STAT_PERR(v)                 (((v) << 17) & 0x20000)
+#define BP_UARTAPP_STAT_FERR                    16
+#define BM_UARTAPP_STAT_FERR                    0x10000
+#define BF_UARTAPP_STAT_FERR(v)                 (((v) << 16) & 0x10000)
+#define BP_UARTAPP_STAT_RXCOUNT                 0
+#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
+#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_DEBUG
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_UARTAPP_DEBUG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x80))
+#define BP_UARTAPP_DEBUG_RXIBAUD_DIV    16
+#define BM_UARTAPP_DEBUG_RXIBAUD_DIV    0xffff0000
+#define BF_UARTAPP_DEBUG_RXIBAUD_DIV(v) (((v) << 16) & 0xffff0000)
+#define BP_UARTAPP_DEBUG_RXFBAUD_DIV    10
+#define BM_UARTAPP_DEBUG_RXFBAUD_DIV    0xfc00
+#define BF_UARTAPP_DEBUG_RXFBAUD_DIV(v) (((v) << 10) & 0xfc00)
+#define BP_UARTAPP_DEBUG_RSVD1          6
+#define BM_UARTAPP_DEBUG_RSVD1          0x3c0
+#define BF_UARTAPP_DEBUG_RSVD1(v)       (((v) << 6) & 0x3c0)
+#define BP_UARTAPP_DEBUG_TXDMARUN       5
+#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
+#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) << 5) & 0x20)
+#define BP_UARTAPP_DEBUG_RXDMARUN       4
+#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
+#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) << 4) & 0x10)
+#define BP_UARTAPP_DEBUG_TXCMDEND       3
+#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
+#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) << 3) & 0x8)
+#define BP_UARTAPP_DEBUG_RXCMDEND       2
+#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
+#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) << 2) & 0x4)
+#define BP_UARTAPP_DEBUG_TXDMARQ        1
+#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
+#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) << 1) & 0x2)
+#define BP_UARTAPP_DEBUG_RXDMARQ        0
+#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
+#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_VERSION
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_UARTAPP_VERSION(d)       (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x90))
+#define BP_UARTAPP_VERSION_MAJOR    24
+#define BM_UARTAPP_VERSION_MAJOR    0xff000000
+#define BF_UARTAPP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_UARTAPP_VERSION_MINOR    16
+#define BM_UARTAPP_VERSION_MINOR    0xff0000
+#define BF_UARTAPP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_UARTAPP_VERSION_STEP     0
+#define BM_UARTAPP_VERSION_STEP     0xffff
+#define BF_UARTAPP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_AUTOBAUD
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_UARTAPP_AUTOBAUD(d)                      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0xa0))
+#define BP_UARTAPP_AUTOBAUD_REFCHAR1                24
+#define BM_UARTAPP_AUTOBAUD_REFCHAR1                0xff000000
+#define BF_UARTAPP_AUTOBAUD_REFCHAR1(v)             (((v) << 24) & 0xff000000)
+#define BP_UARTAPP_AUTOBAUD_REFCHAR0                16
+#define BM_UARTAPP_AUTOBAUD_REFCHAR0                0xff0000
+#define BF_UARTAPP_AUTOBAUD_REFCHAR0(v)             (((v) << 16) & 0xff0000)
+#define BP_UARTAPP_AUTOBAUD_RSVD1                   5
+#define BM_UARTAPP_AUTOBAUD_RSVD1                   0xffe0
+#define BF_UARTAPP_AUTOBAUD_RSVD1(v)                (((v) << 5) & 0xffe0)
+#define BP_UARTAPP_AUTOBAUD_UPDATE_TX               4
+#define BM_UARTAPP_AUTOBAUD_UPDATE_TX               0x10
+#define BF_UARTAPP_AUTOBAUD_UPDATE_TX(v)            (((v) << 4) & 0x10)
+#define BP_UARTAPP_AUTOBAUD_TWO_REF_CHARS           3
+#define BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS           0x8
+#define BF_UARTAPP_AUTOBAUD_TWO_REF_CHARS(v)        (((v) << 3) & 0x8)
+#define BP_UARTAPP_AUTOBAUD_START_WITH_RUNBIT       2
+#define BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT       0x4
+#define BF_UARTAPP_AUTOBAUD_START_WITH_RUNBIT(v)    (((v) << 2) & 0x4)
+#define BP_UARTAPP_AUTOBAUD_START_BAUD_DETECT       1
+#define BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT       0x2
+#define BF_UARTAPP_AUTOBAUD_START_BAUD_DETECT(v)    (((v) << 1) & 0x2)
+#define BP_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE      0
+#define BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE      0x1
+#define BF_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE(v)   (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__IMX233__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h b/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h
new file mode 100644
index 0000000000..a92bc288d3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-uartdbg.h
@@ -0,0 +1,491 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__UARTDBG__H__
+#define __HEADERGEN__IMX233__UARTDBG__H__
+
+#define REGS_UARTDBG_BASE (0x80070000)
+
+#define REGS_UARTDBG_VERSION "3.2.0"
+
+/**
+ * Register: HW_UARTDBG_DR
+ * Address: 0
+ * SCT: no
+*/
+#define HW_UARTDBG_DR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0))
+#define BP_UARTDBG_DR_UNAVAILABLE       16
+#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_DR_RESERVED          12
+#define BM_UARTDBG_DR_RESERVED          0xf000
+#define BF_UARTDBG_DR_RESERVED(v)       (((v) << 12) & 0xf000)
+#define BP_UARTDBG_DR_OE                11
+#define BM_UARTDBG_DR_OE                0x800
+#define BF_UARTDBG_DR_OE(v)             (((v) << 11) & 0x800)
+#define BP_UARTDBG_DR_BE                10
+#define BM_UARTDBG_DR_BE                0x400
+#define BF_UARTDBG_DR_BE(v)             (((v) << 10) & 0x400)
+#define BP_UARTDBG_DR_PE                9
+#define BM_UARTDBG_DR_PE                0x200
+#define BF_UARTDBG_DR_PE(v)             (((v) << 9) & 0x200)
+#define BP_UARTDBG_DR_FE                8
+#define BM_UARTDBG_DR_FE                0x100
+#define BF_UARTDBG_DR_FE(v)             (((v) << 8) & 0x100)
+#define BP_UARTDBG_DR_DATA              0
+#define BM_UARTDBG_DR_DATA              0xff
+#define BF_UARTDBG_DR_DATA(v)           (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_UARTDBG_RSR_ECR
+ * Address: 0x4
+ * SCT: no
+*/
+#define HW_UARTDBG_RSR_ECR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4))
+#define BP_UARTDBG_RSR_ECR_UNAVAILABLE      8
+#define BM_UARTDBG_RSR_ECR_UNAVAILABLE      0xffffff00
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)   (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_RSR_ECR_EC               4
+#define BM_UARTDBG_RSR_ECR_EC               0xf0
+#define BF_UARTDBG_RSR_ECR_EC(v)            (((v) << 4) & 0xf0)
+#define BP_UARTDBG_RSR_ECR_OE               3
+#define BM_UARTDBG_RSR_ECR_OE               0x8
+#define BF_UARTDBG_RSR_ECR_OE(v)            (((v) << 3) & 0x8)
+#define BP_UARTDBG_RSR_ECR_BE               2
+#define BM_UARTDBG_RSR_ECR_BE               0x4
+#define BF_UARTDBG_RSR_ECR_BE(v)            (((v) << 2) & 0x4)
+#define BP_UARTDBG_RSR_ECR_PE               1
+#define BM_UARTDBG_RSR_ECR_PE               0x2
+#define BF_UARTDBG_RSR_ECR_PE(v)            (((v) << 1) & 0x2)
+#define BP_UARTDBG_RSR_ECR_FE               0
+#define BM_UARTDBG_RSR_ECR_FE               0x1
+#define BF_UARTDBG_RSR_ECR_FE(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_FR
+ * Address: 0x18
+ * SCT: no
+*/
+#define HW_UARTDBG_FR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18))
+#define BP_UARTDBG_FR_UNAVAILABLE       16
+#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_FR_RESERVED          9
+#define BM_UARTDBG_FR_RESERVED          0xfe00
+#define BF_UARTDBG_FR_RESERVED(v)       (((v) << 9) & 0xfe00)
+#define BP_UARTDBG_FR_RI                8
+#define BM_UARTDBG_FR_RI                0x100
+#define BF_UARTDBG_FR_RI(v)             (((v) << 8) & 0x100)
+#define BP_UARTDBG_FR_TXFE              7
+#define BM_UARTDBG_FR_TXFE              0x80
+#define BF_UARTDBG_FR_TXFE(v)           (((v) << 7) & 0x80)
+#define BP_UARTDBG_FR_RXFF              6
+#define BM_UARTDBG_FR_RXFF              0x40
+#define BF_UARTDBG_FR_RXFF(v)           (((v) << 6) & 0x40)
+#define BP_UARTDBG_FR_TXFF              5
+#define BM_UARTDBG_FR_TXFF              0x20
+#define BF_UARTDBG_FR_TXFF(v)           (((v) << 5) & 0x20)
+#define BP_UARTDBG_FR_RXFE              4
+#define BM_UARTDBG_FR_RXFE              0x10
+#define BF_UARTDBG_FR_RXFE(v)           (((v) << 4) & 0x10)
+#define BP_UARTDBG_FR_BUSY              3
+#define BM_UARTDBG_FR_BUSY              0x8
+#define BF_UARTDBG_FR_BUSY(v)           (((v) << 3) & 0x8)
+#define BP_UARTDBG_FR_DCD               2
+#define BM_UARTDBG_FR_DCD               0x4
+#define BF_UARTDBG_FR_DCD(v)            (((v) << 2) & 0x4)
+#define BP_UARTDBG_FR_DSR               1
+#define BM_UARTDBG_FR_DSR               0x2
+#define BF_UARTDBG_FR_DSR(v)            (((v) << 1) & 0x2)
+#define BP_UARTDBG_FR_CTS               0
+#define BM_UARTDBG_FR_CTS               0x1
+#define BF_UARTDBG_FR_CTS(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_ILPR
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_UARTDBG_ILPR                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20))
+#define BP_UARTDBG_ILPR_UNAVAILABLE     8
+#define BM_UARTDBG_ILPR_UNAVAILABLE     0xffffff00
+#define BF_UARTDBG_ILPR_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_ILPR_ILPDVSR         0
+#define BM_UARTDBG_ILPR_ILPDVSR         0xff
+#define BF_UARTDBG_ILPR_ILPDVSR(v)      (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_UARTDBG_IBRD
+ * Address: 0x24
+ * SCT: no
+*/
+#define HW_UARTDBG_IBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24))
+#define BP_UARTDBG_IBRD_UNAVAILABLE     16
+#define BM_UARTDBG_IBRD_UNAVAILABLE     0xffff0000
+#define BF_UARTDBG_IBRD_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IBRD_BAUD_DIVINT     0
+#define BM_UARTDBG_IBRD_BAUD_DIVINT     0xffff
+#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTDBG_FBRD
+ * Address: 0x28
+ * SCT: no
+*/
+#define HW_UARTDBG_FBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28))
+#define BP_UARTDBG_FBRD_UNAVAILABLE     8
+#define BM_UARTDBG_FBRD_UNAVAILABLE     0xffffff00
+#define BF_UARTDBG_FBRD_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_FBRD_RESERVED        6
+#define BM_UARTDBG_FBRD_RESERVED        0xc0
+#define BF_UARTDBG_FBRD_RESERVED(v)     (((v) << 6) & 0xc0)
+#define BP_UARTDBG_FBRD_BAUD_DIVFRAC    0
+#define BM_UARTDBG_FBRD_BAUD_DIVFRAC    0x3f
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_UARTDBG_LCR_H
+ * Address: 0x2c
+ * SCT: no
+*/
+#define HW_UARTDBG_LCR_H                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c))
+#define BP_UARTDBG_LCR_H_UNAVAILABLE    16
+#define BM_UARTDBG_LCR_H_UNAVAILABLE    0xffff0000
+#define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_LCR_H_RESERVED       8
+#define BM_UARTDBG_LCR_H_RESERVED       0xff00
+#define BF_UARTDBG_LCR_H_RESERVED(v)    (((v) << 8) & 0xff00)
+#define BP_UARTDBG_LCR_H_SPS            7
+#define BM_UARTDBG_LCR_H_SPS            0x80
+#define BF_UARTDBG_LCR_H_SPS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_LCR_H_WLEN           5
+#define BM_UARTDBG_LCR_H_WLEN           0x60
+#define BF_UARTDBG_LCR_H_WLEN(v)        (((v) << 5) & 0x60)
+#define BP_UARTDBG_LCR_H_FEN            4
+#define BM_UARTDBG_LCR_H_FEN            0x10
+#define BF_UARTDBG_LCR_H_FEN(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_LCR_H_STP2           3
+#define BM_UARTDBG_LCR_H_STP2           0x8
+#define BF_UARTDBG_LCR_H_STP2(v)        (((v) << 3) & 0x8)
+#define BP_UARTDBG_LCR_H_EPS            2
+#define BM_UARTDBG_LCR_H_EPS            0x4
+#define BF_UARTDBG_LCR_H_EPS(v)         (((v) << 2) & 0x4)
+#define BP_UARTDBG_LCR_H_PEN            1
+#define BM_UARTDBG_LCR_H_PEN            0x2
+#define BF_UARTDBG_LCR_H_PEN(v)         (((v) << 1) & 0x2)
+#define BP_UARTDBG_LCR_H_BRK            0
+#define BM_UARTDBG_LCR_H_BRK            0x1
+#define BF_UARTDBG_LCR_H_BRK(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_CR
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_UARTDBG_CR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30))
+#define BP_UARTDBG_CR_UNAVAILABLE       16
+#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_CR_CTSEN             15
+#define BM_UARTDBG_CR_CTSEN             0x8000
+#define BF_UARTDBG_CR_CTSEN(v)          (((v) << 15) & 0x8000)
+#define BP_UARTDBG_CR_RTSEN             14
+#define BM_UARTDBG_CR_RTSEN             0x4000
+#define BF_UARTDBG_CR_RTSEN(v)          (((v) << 14) & 0x4000)
+#define BP_UARTDBG_CR_OUT2              13
+#define BM_UARTDBG_CR_OUT2              0x2000
+#define BF_UARTDBG_CR_OUT2(v)           (((v) << 13) & 0x2000)
+#define BP_UARTDBG_CR_OUT1              12
+#define BM_UARTDBG_CR_OUT1              0x1000
+#define BF_UARTDBG_CR_OUT1(v)           (((v) << 12) & 0x1000)
+#define BP_UARTDBG_CR_RTS               11
+#define BM_UARTDBG_CR_RTS               0x800
+#define BF_UARTDBG_CR_RTS(v)            (((v) << 11) & 0x800)
+#define BP_UARTDBG_CR_DTR               10
+#define BM_UARTDBG_CR_DTR               0x400
+#define BF_UARTDBG_CR_DTR(v)            (((v) << 10) & 0x400)
+#define BP_UARTDBG_CR_RXE               9
+#define BM_UARTDBG_CR_RXE               0x200
+#define BF_UARTDBG_CR_RXE(v)            (((v) << 9) & 0x200)
+#define BP_UARTDBG_CR_TXE               8
+#define BM_UARTDBG_CR_TXE               0x100
+#define BF_UARTDBG_CR_TXE(v)            (((v) << 8) & 0x100)
+#define BP_UARTDBG_CR_LBE               7
+#define BM_UARTDBG_CR_LBE               0x80
+#define BF_UARTDBG_CR_LBE(v)            (((v) << 7) & 0x80)
+#define BP_UARTDBG_CR_RESERVED          3
+#define BM_UARTDBG_CR_RESERVED          0x78
+#define BF_UARTDBG_CR_RESERVED(v)       (((v) << 3) & 0x78)
+#define BP_UARTDBG_CR_SIRLP             2
+#define BM_UARTDBG_CR_SIRLP             0x4
+#define BF_UARTDBG_CR_SIRLP(v)          (((v) << 2) & 0x4)
+#define BP_UARTDBG_CR_SIREN             1
+#define BM_UARTDBG_CR_SIREN             0x2
+#define BF_UARTDBG_CR_SIREN(v)          (((v) << 1) & 0x2)
+#define BP_UARTDBG_CR_UARTEN            0
+#define BM_UARTDBG_CR_UARTEN            0x1
+#define BF_UARTDBG_CR_UARTEN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_IFLS
+ * Address: 0x34
+ * SCT: no
+*/
+#define HW_UARTDBG_IFLS                             (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34))
+#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
+#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
+#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IFLS_RESERVED                    6
+#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
+#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) << 6) & 0xffc0)
+#define BP_UARTDBG_IFLS_RXIFLSEL                    3
+#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
+#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) << 3) & 0x38)
+#define BF_UARTDBG_IFLS_RXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38)
+#define BP_UARTDBG_IFLS_TXIFLSEL                    0
+#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
+#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) << 0) & 0x7)
+#define BF_UARTDBG_IFLS_TXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7)
+
+/**
+ * Register: HW_UARTDBG_IMSC
+ * Address: 0x38
+ * SCT: no
+*/
+#define HW_UARTDBG_IMSC                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38))
+#define BP_UARTDBG_IMSC_UNAVAILABLE     16
+#define BM_UARTDBG_IMSC_UNAVAILABLE     0xffff0000
+#define BF_UARTDBG_IMSC_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IMSC_RESERVED        11
+#define BM_UARTDBG_IMSC_RESERVED        0xf800
+#define BF_UARTDBG_IMSC_RESERVED(v)     (((v) << 11) & 0xf800)
+#define BP_UARTDBG_IMSC_OEIM            10
+#define BM_UARTDBG_IMSC_OEIM            0x400
+#define BF_UARTDBG_IMSC_OEIM(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_IMSC_BEIM            9
+#define BM_UARTDBG_IMSC_BEIM            0x200
+#define BF_UARTDBG_IMSC_BEIM(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_IMSC_PEIM            8
+#define BM_UARTDBG_IMSC_PEIM            0x100
+#define BF_UARTDBG_IMSC_PEIM(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_IMSC_FEIM            7
+#define BM_UARTDBG_IMSC_FEIM            0x80
+#define BF_UARTDBG_IMSC_FEIM(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_IMSC_RTIM            6
+#define BM_UARTDBG_IMSC_RTIM            0x40
+#define BF_UARTDBG_IMSC_RTIM(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_IMSC_TXIM            5
+#define BM_UARTDBG_IMSC_TXIM            0x20
+#define BF_UARTDBG_IMSC_TXIM(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_IMSC_RXIM            4
+#define BM_UARTDBG_IMSC_RXIM            0x10
+#define BF_UARTDBG_IMSC_RXIM(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_IMSC_DSRMIM          3
+#define BM_UARTDBG_IMSC_DSRMIM          0x8
+#define BF_UARTDBG_IMSC_DSRMIM(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_IMSC_DCDMIM          2
+#define BM_UARTDBG_IMSC_DCDMIM          0x4
+#define BF_UARTDBG_IMSC_DCDMIM(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_IMSC_CTSMIM          1
+#define BM_UARTDBG_IMSC_CTSMIM          0x2
+#define BF_UARTDBG_IMSC_CTSMIM(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_IMSC_RIMIM           0
+#define BM_UARTDBG_IMSC_RIMIM           0x1
+#define BF_UARTDBG_IMSC_RIMIM(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_RIS
+ * Address: 0x3c
+ * SCT: no
+*/
+#define HW_UARTDBG_RIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c))
+#define BP_UARTDBG_RIS_UNAVAILABLE      16
+#define BM_UARTDBG_RIS_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_RIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_RIS_RESERVED         11
+#define BM_UARTDBG_RIS_RESERVED         0xf800
+#define BF_UARTDBG_RIS_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_RIS_OERIS            10
+#define BM_UARTDBG_RIS_OERIS            0x400
+#define BF_UARTDBG_RIS_OERIS(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_RIS_BERIS            9
+#define BM_UARTDBG_RIS_BERIS            0x200
+#define BF_UARTDBG_RIS_BERIS(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_RIS_PERIS            8
+#define BM_UARTDBG_RIS_PERIS            0x100
+#define BF_UARTDBG_RIS_PERIS(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_RIS_FERIS            7
+#define BM_UARTDBG_RIS_FERIS            0x80
+#define BF_UARTDBG_RIS_FERIS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_RIS_RTRIS            6
+#define BM_UARTDBG_RIS_RTRIS            0x40
+#define BF_UARTDBG_RIS_RTRIS(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_RIS_TXRIS            5
+#define BM_UARTDBG_RIS_TXRIS            0x20
+#define BF_UARTDBG_RIS_TXRIS(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_RIS_RXRIS            4
+#define BM_UARTDBG_RIS_RXRIS            0x10
+#define BF_UARTDBG_RIS_RXRIS(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_RIS_DSRRMIS          3
+#define BM_UARTDBG_RIS_DSRRMIS          0x8
+#define BF_UARTDBG_RIS_DSRRMIS(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_RIS_DCDRMIS          2
+#define BM_UARTDBG_RIS_DCDRMIS          0x4
+#define BF_UARTDBG_RIS_DCDRMIS(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_RIS_CTSRMIS          1
+#define BM_UARTDBG_RIS_CTSRMIS          0x2
+#define BF_UARTDBG_RIS_CTSRMIS(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_RIS_RIRMIS           0
+#define BM_UARTDBG_RIS_RIRMIS           0x1
+#define BF_UARTDBG_RIS_RIRMIS(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_MIS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_UARTDBG_MIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40))
+#define BP_UARTDBG_MIS_UNAVAILABLE      16
+#define BM_UARTDBG_MIS_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_MIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_MIS_RESERVED         11
+#define BM_UARTDBG_MIS_RESERVED         0xf800
+#define BF_UARTDBG_MIS_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_MIS_OEMIS            10
+#define BM_UARTDBG_MIS_OEMIS            0x400
+#define BF_UARTDBG_MIS_OEMIS(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_MIS_BEMIS            9
+#define BM_UARTDBG_MIS_BEMIS            0x200
+#define BF_UARTDBG_MIS_BEMIS(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_MIS_PEMIS            8
+#define BM_UARTDBG_MIS_PEMIS            0x100
+#define BF_UARTDBG_MIS_PEMIS(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_MIS_FEMIS            7
+#define BM_UARTDBG_MIS_FEMIS            0x80
+#define BF_UARTDBG_MIS_FEMIS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_MIS_RTMIS            6
+#define BM_UARTDBG_MIS_RTMIS            0x40
+#define BF_UARTDBG_MIS_RTMIS(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_MIS_TXMIS            5
+#define BM_UARTDBG_MIS_TXMIS            0x20
+#define BF_UARTDBG_MIS_TXMIS(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_MIS_RXMIS            4
+#define BM_UARTDBG_MIS_RXMIS            0x10
+#define BF_UARTDBG_MIS_RXMIS(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_MIS_DSRMMIS          3
+#define BM_UARTDBG_MIS_DSRMMIS          0x8
+#define BF_UARTDBG_MIS_DSRMMIS(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_MIS_DCDMMIS          2
+#define BM_UARTDBG_MIS_DCDMMIS          0x4
+#define BF_UARTDBG_MIS_DCDMMIS(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_MIS_CTSMMIS          1
+#define BM_UARTDBG_MIS_CTSMMIS          0x2
+#define BF_UARTDBG_MIS_CTSMMIS(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_MIS_RIMMIS           0
+#define BM_UARTDBG_MIS_RIMMIS           0x1
+#define BF_UARTDBG_MIS_RIMMIS(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_ICR
+ * Address: 0x44
+ * SCT: no
+*/
+#define HW_UARTDBG_ICR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44))
+#define BP_UARTDBG_ICR_UNAVAILABLE      16
+#define BM_UARTDBG_ICR_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_ICR_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_ICR_RESERVED         11
+#define BM_UARTDBG_ICR_RESERVED         0xf800
+#define BF_UARTDBG_ICR_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_ICR_OEIC             10
+#define BM_UARTDBG_ICR_OEIC             0x400
+#define BF_UARTDBG_ICR_OEIC(v)          (((v) << 10) & 0x400)
+#define BP_UARTDBG_ICR_BEIC             9
+#define BM_UARTDBG_ICR_BEIC             0x200
+#define BF_UARTDBG_ICR_BEIC(v)          (((v) << 9) & 0x200)
+#define BP_UARTDBG_ICR_PEIC             8
+#define BM_UARTDBG_ICR_PEIC             0x100
+#define BF_UARTDBG_ICR_PEIC(v)          (((v) << 8) & 0x100)
+#define BP_UARTDBG_ICR_FEIC             7
+#define BM_UARTDBG_ICR_FEIC             0x80
+#define BF_UARTDBG_ICR_FEIC(v)          (((v) << 7) & 0x80)
+#define BP_UARTDBG_ICR_RTIC             6
+#define BM_UARTDBG_ICR_RTIC             0x40
+#define BF_UARTDBG_ICR_RTIC(v)          (((v) << 6) & 0x40)
+#define BP_UARTDBG_ICR_TXIC             5
+#define BM_UARTDBG_ICR_TXIC             0x20
+#define BF_UARTDBG_ICR_TXIC(v)          (((v) << 5) & 0x20)
+#define BP_UARTDBG_ICR_RXIC             4
+#define BM_UARTDBG_ICR_RXIC             0x10
+#define BF_UARTDBG_ICR_RXIC(v)          (((v) << 4) & 0x10)
+#define BP_UARTDBG_ICR_DSRMIC           3
+#define BM_UARTDBG_ICR_DSRMIC           0x8
+#define BF_UARTDBG_ICR_DSRMIC(v)        (((v) << 3) & 0x8)
+#define BP_UARTDBG_ICR_DCDMIC           2
+#define BM_UARTDBG_ICR_DCDMIC           0x4
+#define BF_UARTDBG_ICR_DCDMIC(v)        (((v) << 2) & 0x4)
+#define BP_UARTDBG_ICR_CTSMIC           1
+#define BM_UARTDBG_ICR_CTSMIC           0x2
+#define BF_UARTDBG_ICR_CTSMIC(v)        (((v) << 1) & 0x2)
+#define BP_UARTDBG_ICR_RIMIC            0
+#define BM_UARTDBG_ICR_RIMIC            0x1
+#define BF_UARTDBG_ICR_RIMIC(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_DMACR
+ * Address: 0x48
+ * SCT: no
+*/
+#define HW_UARTDBG_DMACR                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48))
+#define BP_UARTDBG_DMACR_UNAVAILABLE    16
+#define BM_UARTDBG_DMACR_UNAVAILABLE    0xffff0000
+#define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_DMACR_RESERVED       3
+#define BM_UARTDBG_DMACR_RESERVED       0xfff8
+#define BF_UARTDBG_DMACR_RESERVED(v)    (((v) << 3) & 0xfff8)
+#define BP_UARTDBG_DMACR_DMAONERR       2
+#define BM_UARTDBG_DMACR_DMAONERR       0x4
+#define BF_UARTDBG_DMACR_DMAONERR(v)    (((v) << 2) & 0x4)
+#define BP_UARTDBG_DMACR_TXDMAE         1
+#define BM_UARTDBG_DMACR_TXDMAE         0x2
+#define BF_UARTDBG_DMACR_TXDMAE(v)      (((v) << 1) & 0x2)
+#define BP_UARTDBG_DMACR_RXDMAE         0
+#define BM_UARTDBG_DMACR_RXDMAE         0x1
+#define BF_UARTDBG_DMACR_RXDMAE(v)      (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__IMX233__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h b/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h
new file mode 100644
index 0000000000..1e69f3c8bc
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-usbctrl.h
@@ -0,0 +1,1234 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__USBCTRL__H__
+#define __HEADERGEN__IMX233__USBCTRL__H__
+
+#define REGS_USBCTRL_BASE (0x80080000)
+
+#define REGS_USBCTRL_VERSION "3.2.0"
+
+/**
+ * Register: HW_USBCTRL_ID
+ * Address: 0
+ * SCT: no
+*/
+#define HW_USBCTRL_ID               (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x0))
+#define BP_USBCTRL_ID_CIVERSION     29
+#define BM_USBCTRL_ID_CIVERSION     0xe0000000
+#define BF_USBCTRL_ID_CIVERSION(v)  (((v) << 29) & 0xe0000000)
+#define BP_USBCTRL_ID_VERSION       25
+#define BM_USBCTRL_ID_VERSION       0x1e000000
+#define BF_USBCTRL_ID_VERSION(v)    (((v) << 25) & 0x1e000000)
+#define BP_USBCTRL_ID_REVISION      21
+#define BM_USBCTRL_ID_REVISION      0x1e00000
+#define BF_USBCTRL_ID_REVISION(v)   (((v) << 21) & 0x1e00000)
+#define BP_USBCTRL_ID_TAG           16
+#define BM_USBCTRL_ID_TAG           0x1f0000
+#define BF_USBCTRL_ID_TAG(v)        (((v) << 16) & 0x1f0000)
+#define BP_USBCTRL_ID_RSVD1         14
+#define BM_USBCTRL_ID_RSVD1         0xc000
+#define BF_USBCTRL_ID_RSVD1(v)      (((v) << 14) & 0xc000)
+#define BP_USBCTRL_ID_NID           8
+#define BM_USBCTRL_ID_NID           0x3f00
+#define BF_USBCTRL_ID_NID(v)        (((v) << 8) & 0x3f00)
+#define BP_USBCTRL_ID_RSVD0         6
+#define BM_USBCTRL_ID_RSVD0         0xc0
+#define BF_USBCTRL_ID_RSVD0(v)      (((v) << 6) & 0xc0)
+#define BP_USBCTRL_ID_ID            0
+#define BM_USBCTRL_ID_ID            0x3f
+#define BF_USBCTRL_ID_ID(v)         (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_USBCTRL_HWGENERAL
+ * Address: 0x4
+ * SCT: no
+*/
+#define HW_USBCTRL_HWGENERAL            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x4))
+#define BP_USBCTRL_HWGENERAL_RSVD       11
+#define BM_USBCTRL_HWGENERAL_RSVD       0xfffff800
+#define BF_USBCTRL_HWGENERAL_RSVD(v)    (((v) << 11) & 0xfffff800)
+#define BP_USBCTRL_HWGENERAL_SM         9
+#define BM_USBCTRL_HWGENERAL_SM         0x600
+#define BF_USBCTRL_HWGENERAL_SM(v)      (((v) << 9) & 0x600)
+#define BP_USBCTRL_HWGENERAL_PHYM       6
+#define BM_USBCTRL_HWGENERAL_PHYM       0x1c0
+#define BF_USBCTRL_HWGENERAL_PHYM(v)    (((v) << 6) & 0x1c0)
+#define BP_USBCTRL_HWGENERAL_PHYW       4
+#define BM_USBCTRL_HWGENERAL_PHYW       0x30
+#define BF_USBCTRL_HWGENERAL_PHYW(v)    (((v) << 4) & 0x30)
+#define BP_USBCTRL_HWGENERAL_BWT        3
+#define BM_USBCTRL_HWGENERAL_BWT        0x8
+#define BF_USBCTRL_HWGENERAL_BWT(v)     (((v) << 3) & 0x8)
+#define BP_USBCTRL_HWGENERAL_CLKC       1
+#define BM_USBCTRL_HWGENERAL_CLKC       0x6
+#define BF_USBCTRL_HWGENERAL_CLKC(v)    (((v) << 1) & 0x6)
+#define BP_USBCTRL_HWGENERAL_RT         0
+#define BM_USBCTRL_HWGENERAL_RT         0x1
+#define BF_USBCTRL_HWGENERAL_RT(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_HWHOST
+ * Address: 0x8
+ * SCT: no
+*/
+#define HW_USBCTRL_HWHOST           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8))
+#define BP_USBCTRL_HWHOST_TTPER     24
+#define BM_USBCTRL_HWHOST_TTPER     0xff000000
+#define BF_USBCTRL_HWHOST_TTPER(v)  (((v) << 24) & 0xff000000)
+#define BP_USBCTRL_HWHOST_TTASY     16
+#define BM_USBCTRL_HWHOST_TTASY     0xff0000
+#define BF_USBCTRL_HWHOST_TTASY(v)  (((v) << 16) & 0xff0000)
+#define BP_USBCTRL_HWHOST_RSVD      4
+#define BM_USBCTRL_HWHOST_RSVD      0xfff0
+#define BF_USBCTRL_HWHOST_RSVD(v)   (((v) << 4) & 0xfff0)
+#define BP_USBCTRL_HWHOST_NPORT     1
+#define BM_USBCTRL_HWHOST_NPORT     0xe
+#define BF_USBCTRL_HWHOST_NPORT(v)  (((v) << 1) & 0xe)
+#define BP_USBCTRL_HWHOST_HC        0
+#define BM_USBCTRL_HWHOST_HC        0x1
+#define BF_USBCTRL_HWHOST_HC(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_HWDEVICE
+ * Address: 0xc
+ * SCT: no
+*/
+#define HW_USBCTRL_HWDEVICE             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0xc))
+#define BP_USBCTRL_HWDEVICE_RSVD        6
+#define BM_USBCTRL_HWDEVICE_RSVD        0xffffffc0
+#define BF_USBCTRL_HWDEVICE_RSVD(v)     (((v) << 6) & 0xffffffc0)
+#define BP_USBCTRL_HWDEVICE_DEVEP       1
+#define BM_USBCTRL_HWDEVICE_DEVEP       0x3e
+#define BF_USBCTRL_HWDEVICE_DEVEP(v)    (((v) << 1) & 0x3e)
+#define BP_USBCTRL_HWDEVICE_DC          0
+#define BM_USBCTRL_HWDEVICE_DC          0x1
+#define BF_USBCTRL_HWDEVICE_DC(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_HWTXBUF
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_USBCTRL_HWTXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x10))
+#define BP_USBCTRL_HWTXBUF_TXLCR        31
+#define BM_USBCTRL_HWTXBUF_TXLCR        0x80000000
+#define BF_USBCTRL_HWTXBUF_TXLCR(v)     (((v) << 31) & 0x80000000)
+#define BP_USBCTRL_HWTXBUF_RSVD         24
+#define BM_USBCTRL_HWTXBUF_RSVD         0x7f000000
+#define BF_USBCTRL_HWTXBUF_RSVD(v)      (((v) << 24) & 0x7f000000)
+#define BP_USBCTRL_HWTXBUF_TXCHANADD    16
+#define BM_USBCTRL_HWTXBUF_TXCHANADD    0xff0000
+#define BF_USBCTRL_HWTXBUF_TXCHANADD(v) (((v) << 16) & 0xff0000)
+#define BP_USBCTRL_HWTXBUF_TXADD        8
+#define BM_USBCTRL_HWTXBUF_TXADD        0xff00
+#define BF_USBCTRL_HWTXBUF_TXADD(v)     (((v) << 8) & 0xff00)
+#define BP_USBCTRL_HWTXBUF_TXBURST      0
+#define BM_USBCTRL_HWTXBUF_TXBURST      0xff
+#define BF_USBCTRL_HWTXBUF_TXBURST(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_HWRXBUF
+ * Address: 0x14
+ * SCT: no
+*/
+#define HW_USBCTRL_HWRXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14))
+#define BP_USBCTRL_HWRXBUF_RSVD         16
+#define BM_USBCTRL_HWRXBUF_RSVD         0xffff0000
+#define BF_USBCTRL_HWRXBUF_RSVD(v)      (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_HWRXBUF_RXADD        8
+#define BM_USBCTRL_HWRXBUF_RXADD        0xff00
+#define BF_USBCTRL_HWRXBUF_RXADD(v)     (((v) << 8) & 0xff00)
+#define BP_USBCTRL_HWRXBUF_RXBURST      0
+#define BM_USBCTRL_HWRXBUF_RXBURST      0xff
+#define BF_USBCTRL_HWRXBUF_RXBURST(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_GPTIMER0LD
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_USBCTRL_GPTIMER0LD           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x80))
+#define BP_USBCTRL_GPTIMER0LD_RSVD0     24
+#define BM_USBCTRL_GPTIMER0LD_RSVD0     0xff000000
+#define BF_USBCTRL_GPTIMER0LD_RSVD0(v)  (((v) << 24) & 0xff000000)
+#define BP_USBCTRL_GPTIMER0LD_GPTLD     0
+#define BM_USBCTRL_GPTIMER0LD_GPTLD     0xffffff
+#define BF_USBCTRL_GPTIMER0LD_GPTLD(v)  (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_USBCTRL_GPTIMER0CTRL
+ * Address: 0x84
+ * SCT: no
+*/
+#define HW_USBCTRL_GPTIMER0CTRL                     (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x84))
+#define BP_USBCTRL_GPTIMER0CTRL_GPTRUN              31
+#define BM_USBCTRL_GPTIMER0CTRL_GPTRUN              0x80000000
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__STOP        0x0
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__RUN         0x1
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRUN(v)           (((v) << 31) & 0x80000000)
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRUN_V(v)         ((BV_USBCTRL_GPTIMER0CTRL_GPTRUN__##v << 31) & 0x80000000)
+#define BP_USBCTRL_GPTIMER0CTRL_GPTRST              30
+#define BM_USBCTRL_GPTIMER0CTRL_GPTRST              0x40000000
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__NOACTION    0x0
+#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__LOADCOUNTER 0x1
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRST(v)           (((v) << 30) & 0x40000000)
+#define BF_USBCTRL_GPTIMER0CTRL_GPTRST_V(v)         ((BV_USBCTRL_GPTIMER0CTRL_GPTRST__##v << 30) & 0x40000000)
+#define BP_USBCTRL_GPTIMER0CTRL_RSVD0               25
+#define BM_USBCTRL_GPTIMER0CTRL_RSVD0               0x3e000000
+#define BF_USBCTRL_GPTIMER0CTRL_RSVD0(v)            (((v) << 25) & 0x3e000000)
+#define BP_USBCTRL_GPTIMER0CTRL_GPTMODE             24
+#define BM_USBCTRL_GPTIMER0CTRL_GPTMODE             0x1000000
+#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__ONESHOT    0x0
+#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__REPEAT     0x1
+#define BF_USBCTRL_GPTIMER0CTRL_GPTMODE(v)          (((v) << 24) & 0x1000000)
+#define BF_USBCTRL_GPTIMER0CTRL_GPTMODE_V(v)        ((BV_USBCTRL_GPTIMER0CTRL_GPTMODE__##v << 24) & 0x1000000)
+#define BP_USBCTRL_GPTIMER0CTRL_GPTCNT              0
+#define BM_USBCTRL_GPTIMER0CTRL_GPTCNT              0xffffff
+#define BF_USBCTRL_GPTIMER0CTRL_GPTCNT(v)           (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_USBCTRL_GPTIMER1LD
+ * Address: 0x88
+ * SCT: no
+*/
+#define HW_USBCTRL_GPTIMER1LD           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x88))
+#define BP_USBCTRL_GPTIMER1LD_RSVD0     24
+#define BM_USBCTRL_GPTIMER1LD_RSVD0     0xff000000
+#define BF_USBCTRL_GPTIMER1LD_RSVD0(v)  (((v) << 24) & 0xff000000)
+#define BP_USBCTRL_GPTIMER1LD_GPTLD     0
+#define BM_USBCTRL_GPTIMER1LD_GPTLD     0xffffff
+#define BF_USBCTRL_GPTIMER1LD_GPTLD(v)  (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_USBCTRL_GPTIMER1CTRL
+ * Address: 0x8c
+ * SCT: no
+*/
+#define HW_USBCTRL_GPTIMER1CTRL                     (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8c))
+#define BP_USBCTRL_GPTIMER1CTRL_GPTRUN              31
+#define BM_USBCTRL_GPTIMER1CTRL_GPTRUN              0x80000000
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__STOP        0x0
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__RUN         0x1
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRUN(v)           (((v) << 31) & 0x80000000)
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRUN_V(v)         ((BV_USBCTRL_GPTIMER1CTRL_GPTRUN__##v << 31) & 0x80000000)
+#define BP_USBCTRL_GPTIMER1CTRL_GPTRST              30
+#define BM_USBCTRL_GPTIMER1CTRL_GPTRST              0x40000000
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__NOACTION    0x0
+#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__LOADCOUNTER 0x1
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRST(v)           (((v) << 30) & 0x40000000)
+#define BF_USBCTRL_GPTIMER1CTRL_GPTRST_V(v)         ((BV_USBCTRL_GPTIMER1CTRL_GPTRST__##v << 30) & 0x40000000)
+#define BP_USBCTRL_GPTIMER1CTRL_RSVD0               25
+#define BM_USBCTRL_GPTIMER1CTRL_RSVD0               0x3e000000
+#define BF_USBCTRL_GPTIMER1CTRL_RSVD0(v)            (((v) << 25) & 0x3e000000)
+#define BP_USBCTRL_GPTIMER1CTRL_GPTMODE             24
+#define BM_USBCTRL_GPTIMER1CTRL_GPTMODE             0x1000000
+#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__ONESHOT    0x0
+#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__REPEAT     0x1
+#define BF_USBCTRL_GPTIMER1CTRL_GPTMODE(v)          (((v) << 24) & 0x1000000)
+#define BF_USBCTRL_GPTIMER1CTRL_GPTMODE_V(v)        ((BV_USBCTRL_GPTIMER1CTRL_GPTMODE__##v << 24) & 0x1000000)
+#define BP_USBCTRL_GPTIMER1CTRL_GPTCNT              0
+#define BM_USBCTRL_GPTIMER1CTRL_GPTCNT              0xffffff
+#define BF_USBCTRL_GPTIMER1CTRL_GPTCNT(v)           (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_USBCTRL_SBUSCFG
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_USBCTRL_SBUSCFG                      (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x90))
+#define BP_USBCTRL_SBUSCFG_RSVD                 3
+#define BM_USBCTRL_SBUSCFG_RSVD                 0xfffffff8
+#define BF_USBCTRL_SBUSCFG_RSVD(v)              (((v) << 3) & 0xfffffff8)
+#define BP_USBCTRL_SBUSCFG_AHBBRST              0
+#define BM_USBCTRL_SBUSCFG_AHBBRST              0x7
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR      0x0
+#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR4     0x1
+#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR8     0x2
+#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR16    0x3
+#define BV_USBCTRL_SBUSCFG_AHBBRST__RESERVED    0x4
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR4     0x5
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR8     0x6
+#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR16    0x7
+#define BF_USBCTRL_SBUSCFG_AHBBRST(v)           (((v) << 0) & 0x7)
+#define BF_USBCTRL_SBUSCFG_AHBBRST_V(v)         ((BV_USBCTRL_SBUSCFG_AHBBRST__##v << 0) & 0x7)
+
+/**
+ * Register: HW_USBCTRL_CAPLENGTH
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_USBCTRL_CAPLENGTH                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x100))
+#define BP_USBCTRL_CAPLENGTH_HCIVERSION     16
+#define BM_USBCTRL_CAPLENGTH_HCIVERSION     0xffff0000
+#define BF_USBCTRL_CAPLENGTH_HCIVERSION(v)  (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_CAPLENGTH_RSVD           8
+#define BM_USBCTRL_CAPLENGTH_RSVD           0xff00
+#define BF_USBCTRL_CAPLENGTH_RSVD(v)        (((v) << 8) & 0xff00)
+#define BP_USBCTRL_CAPLENGTH_CAPLENGTH      0
+#define BM_USBCTRL_CAPLENGTH_CAPLENGTH      0xff
+#define BF_USBCTRL_CAPLENGTH_CAPLENGTH(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_HCSPARAMS
+ * Address: 0x104
+ * SCT: no
+*/
+#define HW_USBCTRL_HCSPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x104))
+#define BP_USBCTRL_HCSPARAMS_RSVD2      28
+#define BM_USBCTRL_HCSPARAMS_RSVD2      0xf0000000
+#define BF_USBCTRL_HCSPARAMS_RSVD2(v)   (((v) << 28) & 0xf0000000)
+#define BP_USBCTRL_HCSPARAMS_N_TT       24
+#define BM_USBCTRL_HCSPARAMS_N_TT       0xf000000
+#define BF_USBCTRL_HCSPARAMS_N_TT(v)    (((v) << 24) & 0xf000000)
+#define BP_USBCTRL_HCSPARAMS_N_PTT      20
+#define BM_USBCTRL_HCSPARAMS_N_PTT      0xf00000
+#define BF_USBCTRL_HCSPARAMS_N_PTT(v)   (((v) << 20) & 0xf00000)
+#define BP_USBCTRL_HCSPARAMS_RSVD1      17
+#define BM_USBCTRL_HCSPARAMS_RSVD1      0xe0000
+#define BF_USBCTRL_HCSPARAMS_RSVD1(v)   (((v) << 17) & 0xe0000)
+#define BP_USBCTRL_HCSPARAMS_PI         16
+#define BM_USBCTRL_HCSPARAMS_PI         0x10000
+#define BF_USBCTRL_HCSPARAMS_PI(v)      (((v) << 16) & 0x10000)
+#define BP_USBCTRL_HCSPARAMS_N_CC       12
+#define BM_USBCTRL_HCSPARAMS_N_CC       0xf000
+#define BF_USBCTRL_HCSPARAMS_N_CC(v)    (((v) << 12) & 0xf000)
+#define BP_USBCTRL_HCSPARAMS_N_PCC      8
+#define BM_USBCTRL_HCSPARAMS_N_PCC      0xf00
+#define BF_USBCTRL_HCSPARAMS_N_PCC(v)   (((v) << 8) & 0xf00)
+#define BP_USBCTRL_HCSPARAMS_RSVD0      5
+#define BM_USBCTRL_HCSPARAMS_RSVD0      0xe0
+#define BF_USBCTRL_HCSPARAMS_RSVD0(v)   (((v) << 5) & 0xe0)
+#define BP_USBCTRL_HCSPARAMS_PPC        4
+#define BM_USBCTRL_HCSPARAMS_PPC        0x10
+#define BF_USBCTRL_HCSPARAMS_PPC(v)     (((v) << 4) & 0x10)
+#define BP_USBCTRL_HCSPARAMS_N_PORTS    0
+#define BM_USBCTRL_HCSPARAMS_N_PORTS    0xf
+#define BF_USBCTRL_HCSPARAMS_N_PORTS(v) (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_USBCTRL_HCCPARAMS
+ * Address: 0x108
+ * SCT: no
+*/
+#define HW_USBCTRL_HCCPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x108))
+#define BP_USBCTRL_HCCPARAMS_RSVD2      16
+#define BM_USBCTRL_HCCPARAMS_RSVD2      0xffff0000
+#define BF_USBCTRL_HCCPARAMS_RSVD2(v)   (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_HCCPARAMS_EECP       8
+#define BM_USBCTRL_HCCPARAMS_EECP       0xff00
+#define BF_USBCTRL_HCCPARAMS_EECP(v)    (((v) << 8) & 0xff00)
+#define BP_USBCTRL_HCCPARAMS_IST        4
+#define BM_USBCTRL_HCCPARAMS_IST        0xf0
+#define BF_USBCTRL_HCCPARAMS_IST(v)     (((v) << 4) & 0xf0)
+#define BP_USBCTRL_HCCPARAMS_RSVD0      3
+#define BM_USBCTRL_HCCPARAMS_RSVD0      0x8
+#define BF_USBCTRL_HCCPARAMS_RSVD0(v)   (((v) << 3) & 0x8)
+#define BP_USBCTRL_HCCPARAMS_ASP        2
+#define BM_USBCTRL_HCCPARAMS_ASP        0x4
+#define BF_USBCTRL_HCCPARAMS_ASP(v)     (((v) << 2) & 0x4)
+#define BP_USBCTRL_HCCPARAMS_PFL        1
+#define BM_USBCTRL_HCCPARAMS_PFL        0x2
+#define BF_USBCTRL_HCCPARAMS_PFL(v)     (((v) << 1) & 0x2)
+#define BP_USBCTRL_HCCPARAMS_ADC        0
+#define BM_USBCTRL_HCCPARAMS_ADC        0x1
+#define BF_USBCTRL_HCCPARAMS_ADC(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_DCIVERSION
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_USBCTRL_DCIVERSION               (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x120))
+#define BP_USBCTRL_DCIVERSION_RSVD          16
+#define BM_USBCTRL_DCIVERSION_RSVD          0xffff0000
+#define BF_USBCTRL_DCIVERSION_RSVD(v)       (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_DCIVERSION_DCIVERSION    0
+#define BM_USBCTRL_DCIVERSION_DCIVERSION    0xffff
+#define BF_USBCTRL_DCIVERSION_DCIVERSION(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_DCCPARAMS
+ * Address: 0x124
+ * SCT: no
+*/
+#define HW_USBCTRL_DCCPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x124))
+#define BP_USBCTRL_DCCPARAMS_RSVD1      9
+#define BM_USBCTRL_DCCPARAMS_RSVD1      0xfffffe00
+#define BF_USBCTRL_DCCPARAMS_RSVD1(v)   (((v) << 9) & 0xfffffe00)
+#define BP_USBCTRL_DCCPARAMS_HC         8
+#define BM_USBCTRL_DCCPARAMS_HC         0x100
+#define BF_USBCTRL_DCCPARAMS_HC(v)      (((v) << 8) & 0x100)
+#define BP_USBCTRL_DCCPARAMS_DC         7
+#define BM_USBCTRL_DCCPARAMS_DC         0x80
+#define BF_USBCTRL_DCCPARAMS_DC(v)      (((v) << 7) & 0x80)
+#define BP_USBCTRL_DCCPARAMS_RSVD2      5
+#define BM_USBCTRL_DCCPARAMS_RSVD2      0x60
+#define BF_USBCTRL_DCCPARAMS_RSVD2(v)   (((v) << 5) & 0x60)
+#define BP_USBCTRL_DCCPARAMS_DEN        0
+#define BM_USBCTRL_DCCPARAMS_DEN        0x1f
+#define BF_USBCTRL_DCCPARAMS_DEN(v)     (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_USBCMD
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_USBCTRL_USBCMD                       (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x140))
+#define BP_USBCTRL_USBCMD_RSVD3                 24
+#define BM_USBCTRL_USBCMD_RSVD3                 0xff000000
+#define BF_USBCTRL_USBCMD_RSVD3(v)              (((v) << 24) & 0xff000000)
+#define BP_USBCTRL_USBCMD_ITC                   16
+#define BM_USBCTRL_USBCMD_ITC                   0xff0000
+#define BV_USBCTRL_USBCMD_ITC__IMM              0x0
+#define BV_USBCTRL_USBCMD_ITC__1_MICROFRAME     0x1
+#define BV_USBCTRL_USBCMD_ITC__2_MICROFRAME     0x2
+#define BV_USBCTRL_USBCMD_ITC__4_MICROFRAME     0x4
+#define BV_USBCTRL_USBCMD_ITC__8_MICROFRAME     0x8
+#define BV_USBCTRL_USBCMD_ITC__16_MICROFRAME    0x10
+#define BV_USBCTRL_USBCMD_ITC__32_MICROFRAME    0x20
+#define BV_USBCTRL_USBCMD_ITC__64_MICROFRAME    0x40
+#define BF_USBCTRL_USBCMD_ITC(v)                (((v) << 16) & 0xff0000)
+#define BF_USBCTRL_USBCMD_ITC_V(v)              ((BV_USBCTRL_USBCMD_ITC__##v << 16) & 0xff0000)
+#define BP_USBCTRL_USBCMD_FS2                   15
+#define BM_USBCTRL_USBCMD_FS2                   0x8000
+#define BF_USBCTRL_USBCMD_FS2(v)                (((v) << 15) & 0x8000)
+#define BP_USBCTRL_USBCMD_ATDTW                 14
+#define BM_USBCTRL_USBCMD_ATDTW                 0x4000
+#define BF_USBCTRL_USBCMD_ATDTW(v)              (((v) << 14) & 0x4000)
+#define BP_USBCTRL_USBCMD_SUTW                  13
+#define BM_USBCTRL_USBCMD_SUTW                  0x2000
+#define BF_USBCTRL_USBCMD_SUTW(v)               (((v) << 13) & 0x2000)
+#define BP_USBCTRL_USBCMD_RSVD2                 12
+#define BM_USBCTRL_USBCMD_RSVD2                 0x1000
+#define BF_USBCTRL_USBCMD_RSVD2(v)              (((v) << 12) & 0x1000)
+#define BP_USBCTRL_USBCMD_ASPE                  11
+#define BM_USBCTRL_USBCMD_ASPE                  0x800
+#define BF_USBCTRL_USBCMD_ASPE(v)               (((v) << 11) & 0x800)
+#define BP_USBCTRL_USBCMD_RSVD1                 10
+#define BM_USBCTRL_USBCMD_RSVD1                 0x400
+#define BF_USBCTRL_USBCMD_RSVD1(v)              (((v) << 10) & 0x400)
+#define BP_USBCTRL_USBCMD_ASP                   8
+#define BM_USBCTRL_USBCMD_ASP                   0x300
+#define BF_USBCTRL_USBCMD_ASP(v)                (((v) << 8) & 0x300)
+#define BP_USBCTRL_USBCMD_LR                    7
+#define BM_USBCTRL_USBCMD_LR                    0x80
+#define BF_USBCTRL_USBCMD_LR(v)                 (((v) << 7) & 0x80)
+#define BP_USBCTRL_USBCMD_IAA                   6
+#define BM_USBCTRL_USBCMD_IAA                   0x40
+#define BF_USBCTRL_USBCMD_IAA(v)                (((v) << 6) & 0x40)
+#define BP_USBCTRL_USBCMD_ASE                   5
+#define BM_USBCTRL_USBCMD_ASE                   0x20
+#define BF_USBCTRL_USBCMD_ASE(v)                (((v) << 5) & 0x20)
+#define BP_USBCTRL_USBCMD_PSE                   4
+#define BM_USBCTRL_USBCMD_PSE                   0x10
+#define BF_USBCTRL_USBCMD_PSE(v)                (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBCMD_FS1                   3
+#define BM_USBCTRL_USBCMD_FS1                   0x8
+#define BF_USBCTRL_USBCMD_FS1(v)                (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBCMD_FS0                   2
+#define BM_USBCTRL_USBCMD_FS0                   0x4
+#define BF_USBCTRL_USBCMD_FS0(v)                (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBCMD_RST                   1
+#define BM_USBCTRL_USBCMD_RST                   0x2
+#define BF_USBCTRL_USBCMD_RST(v)                (((v) << 1) & 0x2)
+#define BP_USBCTRL_USBCMD_RS                    0
+#define BM_USBCTRL_USBCMD_RS                    0x1
+#define BF_USBCTRL_USBCMD_RS(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_USBSTS
+ * Address: 0x144
+ * SCT: no
+*/
+#define HW_USBCTRL_USBSTS           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x144))
+#define BP_USBCTRL_USBSTS_RSVD5     26
+#define BM_USBCTRL_USBSTS_RSVD5     0xfc000000
+#define BF_USBCTRL_USBSTS_RSVD5(v)  (((v) << 26) & 0xfc000000)
+#define BP_USBCTRL_USBSTS_TI1       25
+#define BM_USBCTRL_USBSTS_TI1       0x2000000
+#define BF_USBCTRL_USBSTS_TI1(v)    (((v) << 25) & 0x2000000)
+#define BP_USBCTRL_USBSTS_TI0       24
+#define BM_USBCTRL_USBSTS_TI0       0x1000000
+#define BF_USBCTRL_USBSTS_TI0(v)    (((v) << 24) & 0x1000000)
+#define BP_USBCTRL_USBSTS_RSVD4     20
+#define BM_USBCTRL_USBSTS_RSVD4     0xf00000
+#define BF_USBCTRL_USBSTS_RSVD4(v)  (((v) << 20) & 0xf00000)
+#define BP_USBCTRL_USBSTS_UPI       19
+#define BM_USBCTRL_USBSTS_UPI       0x80000
+#define BF_USBCTRL_USBSTS_UPI(v)    (((v) << 19) & 0x80000)
+#define BP_USBCTRL_USBSTS_UAI       18
+#define BM_USBCTRL_USBSTS_UAI       0x40000
+#define BF_USBCTRL_USBSTS_UAI(v)    (((v) << 18) & 0x40000)
+#define BP_USBCTRL_USBSTS_RSVD3     17
+#define BM_USBCTRL_USBSTS_RSVD3     0x20000
+#define BF_USBCTRL_USBSTS_RSVD3(v)  (((v) << 17) & 0x20000)
+#define BP_USBCTRL_USBSTS_NAKI      16
+#define BM_USBCTRL_USBSTS_NAKI      0x10000
+#define BF_USBCTRL_USBSTS_NAKI(v)   (((v) << 16) & 0x10000)
+#define BP_USBCTRL_USBSTS_AS        15
+#define BM_USBCTRL_USBSTS_AS        0x8000
+#define BF_USBCTRL_USBSTS_AS(v)     (((v) << 15) & 0x8000)
+#define BP_USBCTRL_USBSTS_PS        14
+#define BM_USBCTRL_USBSTS_PS        0x4000
+#define BF_USBCTRL_USBSTS_PS(v)     (((v) << 14) & 0x4000)
+#define BP_USBCTRL_USBSTS_RCL       13
+#define BM_USBCTRL_USBSTS_RCL       0x2000
+#define BF_USBCTRL_USBSTS_RCL(v)    (((v) << 13) & 0x2000)
+#define BP_USBCTRL_USBSTS_HCH       12
+#define BM_USBCTRL_USBSTS_HCH       0x1000
+#define BF_USBCTRL_USBSTS_HCH(v)    (((v) << 12) & 0x1000)
+#define BP_USBCTRL_USBSTS_RSVD2     11
+#define BM_USBCTRL_USBSTS_RSVD2     0x800
+#define BF_USBCTRL_USBSTS_RSVD2(v)  (((v) << 11) & 0x800)
+#define BP_USBCTRL_USBSTS_ULPII     10
+#define BM_USBCTRL_USBSTS_ULPII     0x400
+#define BF_USBCTRL_USBSTS_ULPII(v)  (((v) << 10) & 0x400)
+#define BP_USBCTRL_USBSTS_RSVD1     9
+#define BM_USBCTRL_USBSTS_RSVD1     0x200
+#define BF_USBCTRL_USBSTS_RSVD1(v)  (((v) << 9) & 0x200)
+#define BP_USBCTRL_USBSTS_SLI       8
+#define BM_USBCTRL_USBSTS_SLI       0x100
+#define BF_USBCTRL_USBSTS_SLI(v)    (((v) << 8) & 0x100)
+#define BP_USBCTRL_USBSTS_SRI       7
+#define BM_USBCTRL_USBSTS_SRI       0x80
+#define BF_USBCTRL_USBSTS_SRI(v)    (((v) << 7) & 0x80)
+#define BP_USBCTRL_USBSTS_URI       6
+#define BM_USBCTRL_USBSTS_URI       0x40
+#define BF_USBCTRL_USBSTS_URI(v)    (((v) << 6) & 0x40)
+#define BP_USBCTRL_USBSTS_AAI       5
+#define BM_USBCTRL_USBSTS_AAI       0x20
+#define BF_USBCTRL_USBSTS_AAI(v)    (((v) << 5) & 0x20)
+#define BP_USBCTRL_USBSTS_SEI       4
+#define BM_USBCTRL_USBSTS_SEI       0x10
+#define BF_USBCTRL_USBSTS_SEI(v)    (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBSTS_FRI       3
+#define BM_USBCTRL_USBSTS_FRI       0x8
+#define BF_USBCTRL_USBSTS_FRI(v)    (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBSTS_PCI       2
+#define BM_USBCTRL_USBSTS_PCI       0x4
+#define BF_USBCTRL_USBSTS_PCI(v)    (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBSTS_UEI       1
+#define BM_USBCTRL_USBSTS_UEI       0x2
+#define BF_USBCTRL_USBSTS_UEI(v)    (((v) << 1) & 0x2)
+#define BP_USBCTRL_USBSTS_UI        0
+#define BM_USBCTRL_USBSTS_UI        0x1
+#define BF_USBCTRL_USBSTS_UI(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_USBINTR
+ * Address: 0x148
+ * SCT: no
+*/
+#define HW_USBCTRL_USBINTR          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x148))
+#define BP_USBCTRL_USBINTR_RSVD5    26
+#define BM_USBCTRL_USBINTR_RSVD5    0xfc000000
+#define BF_USBCTRL_USBINTR_RSVD5(v) (((v) << 26) & 0xfc000000)
+#define BP_USBCTRL_USBINTR_TIE1     25
+#define BM_USBCTRL_USBINTR_TIE1     0x2000000
+#define BF_USBCTRL_USBINTR_TIE1(v)  (((v) << 25) & 0x2000000)
+#define BP_USBCTRL_USBINTR_TIE0     24
+#define BM_USBCTRL_USBINTR_TIE0     0x1000000
+#define BF_USBCTRL_USBINTR_TIE0(v)  (((v) << 24) & 0x1000000)
+#define BP_USBCTRL_USBINTR_RSVD4    20
+#define BM_USBCTRL_USBINTR_RSVD4    0xf00000
+#define BF_USBCTRL_USBINTR_RSVD4(v) (((v) << 20) & 0xf00000)
+#define BP_USBCTRL_USBINTR_UPIE     19
+#define BM_USBCTRL_USBINTR_UPIE     0x80000
+#define BF_USBCTRL_USBINTR_UPIE(v)  (((v) << 19) & 0x80000)
+#define BP_USBCTRL_USBINTR_UAIE     18
+#define BM_USBCTRL_USBINTR_UAIE     0x40000
+#define BF_USBCTRL_USBINTR_UAIE(v)  (((v) << 18) & 0x40000)
+#define BP_USBCTRL_USBINTR_RSVD3    17
+#define BM_USBCTRL_USBINTR_RSVD3    0x20000
+#define BF_USBCTRL_USBINTR_RSVD3(v) (((v) << 17) & 0x20000)
+#define BP_USBCTRL_USBINTR_NAKE     16
+#define BM_USBCTRL_USBINTR_NAKE     0x10000
+#define BF_USBCTRL_USBINTR_NAKE(v)  (((v) << 16) & 0x10000)
+#define BP_USBCTRL_USBINTR_RSVD2    11
+#define BM_USBCTRL_USBINTR_RSVD2    0xf800
+#define BF_USBCTRL_USBINTR_RSVD2(v) (((v) << 11) & 0xf800)
+#define BP_USBCTRL_USBINTR_ULPIE    10
+#define BM_USBCTRL_USBINTR_ULPIE    0x400
+#define BF_USBCTRL_USBINTR_ULPIE(v) (((v) << 10) & 0x400)
+#define BP_USBCTRL_USBINTR_RSVD1    9
+#define BM_USBCTRL_USBINTR_RSVD1    0x200
+#define BF_USBCTRL_USBINTR_RSVD1(v) (((v) << 9) & 0x200)
+#define BP_USBCTRL_USBINTR_SLE      8
+#define BM_USBCTRL_USBINTR_SLE      0x100
+#define BF_USBCTRL_USBINTR_SLE(v)   (((v) << 8) & 0x100)
+#define BP_USBCTRL_USBINTR_SRE      7
+#define BM_USBCTRL_USBINTR_SRE      0x80
+#define BF_USBCTRL_USBINTR_SRE(v)   (((v) << 7) & 0x80)
+#define BP_USBCTRL_USBINTR_URE      6
+#define BM_USBCTRL_USBINTR_URE      0x40
+#define BF_USBCTRL_USBINTR_URE(v)   (((v) << 6) & 0x40)
+#define BP_USBCTRL_USBINTR_AAE      5
+#define BM_USBCTRL_USBINTR_AAE      0x20
+#define BF_USBCTRL_USBINTR_AAE(v)   (((v) << 5) & 0x20)
+#define BP_USBCTRL_USBINTR_SEE      4
+#define BM_USBCTRL_USBINTR_SEE      0x10
+#define BF_USBCTRL_USBINTR_SEE(v)   (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBINTR_FRE      3
+#define BM_USBCTRL_USBINTR_FRE      0x8
+#define BF_USBCTRL_USBINTR_FRE(v)   (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBINTR_PCE      2
+#define BM_USBCTRL_USBINTR_PCE      0x4
+#define BF_USBCTRL_USBINTR_PCE(v)   (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBINTR_UEE      1
+#define BM_USBCTRL_USBINTR_UEE      0x2
+#define BF_USBCTRL_USBINTR_UEE(v)   (((v) << 1) & 0x2)
+#define BP_USBCTRL_USBINTR_UE       0
+#define BM_USBCTRL_USBINTR_UE       0x1
+#define BF_USBCTRL_USBINTR_UE(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_FRINDEX
+ * Address: 0x14c
+ * SCT: no
+*/
+#define HW_USBCTRL_FRINDEX                  (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14c))
+#define BP_USBCTRL_FRINDEX_RSVD             14
+#define BM_USBCTRL_FRINDEX_RSVD             0xffffc000
+#define BF_USBCTRL_FRINDEX_RSVD(v)          (((v) << 14) & 0xffffc000)
+#define BP_USBCTRL_FRINDEX_FRINDEX          3
+#define BM_USBCTRL_FRINDEX_FRINDEX          0x3ff8
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_12    0xc
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_11    0xb
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_10    0xa
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_9     0x9
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_8     0x8
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_7     0x7
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_6     0x6
+#define BV_USBCTRL_FRINDEX_FRINDEX__N_5     0x5
+#define BF_USBCTRL_FRINDEX_FRINDEX(v)       (((v) << 3) & 0x3ff8)
+#define BF_USBCTRL_FRINDEX_FRINDEX_V(v)     ((BV_USBCTRL_FRINDEX_FRINDEX__##v << 3) & 0x3ff8)
+#define BP_USBCTRL_FRINDEX_UINDEX           0
+#define BM_USBCTRL_FRINDEX_UINDEX           0x7
+#define BF_USBCTRL_FRINDEX_UINDEX(v)        (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_USBCTRL_PERIODICLISTBASE
+ * Address: 0x154
+ * SCT: no
+*/
+#define HW_USBCTRL_PERIODICLISTBASE             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154))
+#define BP_USBCTRL_PERIODICLISTBASE_PERBASE     12
+#define BM_USBCTRL_PERIODICLISTBASE_PERBASE     0xfffff000
+#define BF_USBCTRL_PERIODICLISTBASE_PERBASE(v)  (((v) << 12) & 0xfffff000)
+#define BP_USBCTRL_PERIODICLISTBASE_RSVD        0
+#define BM_USBCTRL_PERIODICLISTBASE_RSVD        0xfff
+#define BF_USBCTRL_PERIODICLISTBASE_RSVD(v)     (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_USBCTRL_DEVICEADDR
+ * Address: 0x154
+ * SCT: no
+*/
+#define HW_USBCTRL_DEVICEADDR               (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154))
+#define BP_USBCTRL_DEVICEADDR_USBADR        25
+#define BM_USBCTRL_DEVICEADDR_USBADR        0xfe000000
+#define BF_USBCTRL_DEVICEADDR_USBADR(v)     (((v) << 25) & 0xfe000000)
+#define BP_USBCTRL_DEVICEADDR_USBADRA       24
+#define BM_USBCTRL_DEVICEADDR_USBADRA       0x1000000
+#define BF_USBCTRL_DEVICEADDR_USBADRA(v)    (((v) << 24) & 0x1000000)
+#define BP_USBCTRL_DEVICEADDR_RSVD          0
+#define BM_USBCTRL_DEVICEADDR_RSVD          0xffffff
+#define BF_USBCTRL_DEVICEADDR_RSVD(v)       (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_USBCTRL_ASYNCLISTADDR
+ * Address: 0x158
+ * SCT: no
+*/
+#define HW_USBCTRL_ASYNCLISTADDR            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158))
+#define BP_USBCTRL_ASYNCLISTADDR_ASYBASE    5
+#define BM_USBCTRL_ASYNCLISTADDR_ASYBASE    0xffffffe0
+#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) (((v) << 5) & 0xffffffe0)
+#define BP_USBCTRL_ASYNCLISTADDR_RSVD       0
+#define BM_USBCTRL_ASYNCLISTADDR_RSVD       0x1f
+#define BF_USBCTRL_ASYNCLISTADDR_RSVD(v)    (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_ENDPOINTLISTADDR
+ * Address: 0x158
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPOINTLISTADDR             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158))
+#define BP_USBCTRL_ENDPOINTLISTADDR_EPBASE      11
+#define BM_USBCTRL_ENDPOINTLISTADDR_EPBASE      0xfffff800
+#define BF_USBCTRL_ENDPOINTLISTADDR_EPBASE(v)   (((v) << 11) & 0xfffff800)
+#define BP_USBCTRL_ENDPOINTLISTADDR_RSVD        0
+#define BM_USBCTRL_ENDPOINTLISTADDR_RSVD        0x7ff
+#define BF_USBCTRL_ENDPOINTLISTADDR_RSVD(v)     (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_USBCTRL_TTCTRL
+ * Address: 0x15c
+ * SCT: no
+*/
+#define HW_USBCTRL_TTCTRL           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x15c))
+#define BP_USBCTRL_TTCTRL_RSVD1     31
+#define BM_USBCTRL_TTCTRL_RSVD1     0x80000000
+#define BF_USBCTRL_TTCTRL_RSVD1(v)  (((v) << 31) & 0x80000000)
+#define BP_USBCTRL_TTCTRL_TTHA      24
+#define BM_USBCTRL_TTCTRL_TTHA      0x7f000000
+#define BF_USBCTRL_TTCTRL_TTHA(v)   (((v) << 24) & 0x7f000000)
+#define BP_USBCTRL_TTCTRL_RSVD2     0
+#define BM_USBCTRL_TTCTRL_RSVD2     0xffffff
+#define BF_USBCTRL_TTCTRL_RSVD2(v)  (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_USBCTRL_BURSTSIZE
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_USBCTRL_BURSTSIZE                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x160))
+#define BP_USBCTRL_BURSTSIZE_RSVD           16
+#define BM_USBCTRL_BURSTSIZE_RSVD           0xffff0000
+#define BF_USBCTRL_BURSTSIZE_RSVD(v)        (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_BURSTSIZE_TXPBURST       8
+#define BM_USBCTRL_BURSTSIZE_TXPBURST       0xff00
+#define BF_USBCTRL_BURSTSIZE_TXPBURST(v)    (((v) << 8) & 0xff00)
+#define BP_USBCTRL_BURSTSIZE_RXPBURST       0
+#define BM_USBCTRL_BURSTSIZE_RXPBURST       0xff
+#define BF_USBCTRL_BURSTSIZE_RXPBURST(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_TXFILLTUNING
+ * Address: 0x164
+ * SCT: no
+*/
+#define HW_USBCTRL_TXFILLTUNING                 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x164))
+#define BP_USBCTRL_TXFILLTUNING_RSVD2           22
+#define BM_USBCTRL_TXFILLTUNING_RSVD2           0xffc00000
+#define BF_USBCTRL_TXFILLTUNING_RSVD2(v)        (((v) << 22) & 0xffc00000)
+#define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES     16
+#define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES     0x3f0000
+#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)  (((v) << 16) & 0x3f0000)
+#define BP_USBCTRL_TXFILLTUNING_RSVD1           13
+#define BM_USBCTRL_TXFILLTUNING_RSVD1           0xe000
+#define BF_USBCTRL_TXFILLTUNING_RSVD1(v)        (((v) << 13) & 0xe000)
+#define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH      8
+#define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH      0x1f00
+#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)   (((v) << 8) & 0x1f00)
+#define BP_USBCTRL_TXFILLTUNING_RSVD0           7
+#define BM_USBCTRL_TXFILLTUNING_RSVD0           0x80
+#define BF_USBCTRL_TXFILLTUNING_RSVD0(v)        (((v) << 7) & 0x80)
+#define BP_USBCTRL_TXFILLTUNING_TXSCHOH         0
+#define BM_USBCTRL_TXFILLTUNING_TXSCHOH         0x7f
+#define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v)      (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_USBCTRL_IC_USB
+ * Address: 0x16c
+ * SCT: no
+*/
+#define HW_USBCTRL_IC_USB                       (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x16c))
+#define BP_USBCTRL_IC_USB_RSVD                  4
+#define BM_USBCTRL_IC_USB_RSVD                  0xfffffff0
+#define BF_USBCTRL_IC_USB_RSVD(v)               (((v) << 4) & 0xfffffff0)
+#define BP_USBCTRL_IC_USB_IC_ENABLE             3
+#define BM_USBCTRL_IC_USB_IC_ENABLE             0x8
+#define BF_USBCTRL_IC_USB_IC_ENABLE(v)          (((v) << 3) & 0x8)
+#define BP_USBCTRL_IC_USB_IC_VDD                0
+#define BM_USBCTRL_IC_USB_IC_VDD                0x7
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_NONE  0x0
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_0   0x1
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_2   0x2
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_5   0x3
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_8   0x4
+#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_3_0   0x5
+#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED0     0x6
+#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED1     0x7
+#define BF_USBCTRL_IC_USB_IC_VDD(v)             (((v) << 0) & 0x7)
+#define BF_USBCTRL_IC_USB_IC_VDD_V(v)           ((BV_USBCTRL_IC_USB_IC_VDD__##v << 0) & 0x7)
+
+/**
+ * Register: HW_USBCTRL_ULPI
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_USBCTRL_ULPI                 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x170))
+#define BP_USBCTRL_ULPI_ULPIWU          31
+#define BM_USBCTRL_ULPI_ULPIWU          0x80000000
+#define BF_USBCTRL_ULPI_ULPIWU(v)       (((v) << 31) & 0x80000000)
+#define BP_USBCTRL_ULPI_ULPIRUN         30
+#define BM_USBCTRL_ULPI_ULPIRUN         0x40000000
+#define BF_USBCTRL_ULPI_ULPIRUN(v)      (((v) << 30) & 0x40000000)
+#define BP_USBCTRL_ULPI_ULPIRW          29
+#define BM_USBCTRL_ULPI_ULPIRW          0x20000000
+#define BF_USBCTRL_ULPI_ULPIRW(v)       (((v) << 29) & 0x20000000)
+#define BP_USBCTRL_ULPI_RSVD0           28
+#define BM_USBCTRL_ULPI_RSVD0           0x10000000
+#define BF_USBCTRL_ULPI_RSVD0(v)        (((v) << 28) & 0x10000000)
+#define BP_USBCTRL_ULPI_ULPISS          27
+#define BM_USBCTRL_ULPI_ULPISS          0x8000000
+#define BF_USBCTRL_ULPI_ULPISS(v)       (((v) << 27) & 0x8000000)
+#define BP_USBCTRL_ULPI_ULPIPORT        24
+#define BM_USBCTRL_ULPI_ULPIPORT        0x7000000
+#define BF_USBCTRL_ULPI_ULPIPORT(v)     (((v) << 24) & 0x7000000)
+#define BP_USBCTRL_ULPI_ULPIADDR        16
+#define BM_USBCTRL_ULPI_ULPIADDR        0xff0000
+#define BF_USBCTRL_ULPI_ULPIADDR(v)     (((v) << 16) & 0xff0000)
+#define BP_USBCTRL_ULPI_ULPIDATRD       8
+#define BM_USBCTRL_ULPI_ULPIDATRD       0xff00
+#define BF_USBCTRL_ULPI_ULPIDATRD(v)    (((v) << 8) & 0xff00)
+#define BP_USBCTRL_ULPI_ULPIDATWR       0
+#define BM_USBCTRL_ULPI_ULPIDATWR       0xff
+#define BF_USBCTRL_ULPI_ULPIDATWR(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_ENDPTNAK
+ * Address: 0x178
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTNAK             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x178))
+#define BP_USBCTRL_ENDPTNAK_RSVD1       21
+#define BM_USBCTRL_ENDPTNAK_RSVD1       0xffe00000
+#define BF_USBCTRL_ENDPTNAK_RSVD1(v)    (((v) << 21) & 0xffe00000)
+#define BP_USBCTRL_ENDPTNAK_EPTN        16
+#define BM_USBCTRL_ENDPTNAK_EPTN        0x1f0000
+#define BF_USBCTRL_ENDPTNAK_EPTN(v)     (((v) << 16) & 0x1f0000)
+#define BP_USBCTRL_ENDPTNAK_RSVD0       5
+#define BM_USBCTRL_ENDPTNAK_RSVD0       0xffe0
+#define BF_USBCTRL_ENDPTNAK_RSVD0(v)    (((v) << 5) & 0xffe0)
+#define BP_USBCTRL_ENDPTNAK_EPRN        0
+#define BM_USBCTRL_ENDPTNAK_EPRN        0x1f
+#define BF_USBCTRL_ENDPTNAK_EPRN(v)     (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_ENDPTNAKEN
+ * Address: 0x17c
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTNAKEN           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x17c))
+#define BP_USBCTRL_ENDPTNAKEN_RSVD1     21
+#define BM_USBCTRL_ENDPTNAKEN_RSVD1     0xffe00000
+#define BF_USBCTRL_ENDPTNAKEN_RSVD1(v)  (((v) << 21) & 0xffe00000)
+#define BP_USBCTRL_ENDPTNAKEN_EPTNE     16
+#define BM_USBCTRL_ENDPTNAKEN_EPTNE     0x1f0000
+#define BF_USBCTRL_ENDPTNAKEN_EPTNE(v)  (((v) << 16) & 0x1f0000)
+#define BP_USBCTRL_ENDPTNAKEN_RSVD0     5
+#define BM_USBCTRL_ENDPTNAKEN_RSVD0     0xffe0
+#define BF_USBCTRL_ENDPTNAKEN_RSVD0(v)  (((v) << 5) & 0xffe0)
+#define BP_USBCTRL_ENDPTNAKEN_EPRNE     0
+#define BM_USBCTRL_ENDPTNAKEN_EPRNE     0x1f
+#define BF_USBCTRL_ENDPTNAKEN_EPRNE(v)  (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_PORTSC1
+ * Address: 0x184
+ * SCT: no
+*/
+#define HW_USBCTRL_PORTSC1                              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x184))
+#define BP_USBCTRL_PORTSC1_PTS                          30
+#define BM_USBCTRL_PORTSC1_PTS                          0xc0000000
+#define BV_USBCTRL_PORTSC1_PTS__UTMI                    0x0
+#define BV_USBCTRL_PORTSC1_PTS__PHIL                    0x1
+#define BV_USBCTRL_PORTSC1_PTS__ULPI                    0x2
+#define BV_USBCTRL_PORTSC1_PTS__SERIAL                  0x3
+#define BF_USBCTRL_PORTSC1_PTS(v)                       (((v) << 30) & 0xc0000000)
+#define BF_USBCTRL_PORTSC1_PTS_V(v)                     ((BV_USBCTRL_PORTSC1_PTS__##v << 30) & 0xc0000000)
+#define BP_USBCTRL_PORTSC1_STS                          29
+#define BM_USBCTRL_PORTSC1_STS                          0x20000000
+#define BF_USBCTRL_PORTSC1_STS(v)                       (((v) << 29) & 0x20000000)
+#define BP_USBCTRL_PORTSC1_PTW                          28
+#define BM_USBCTRL_PORTSC1_PTW                          0x10000000
+#define BF_USBCTRL_PORTSC1_PTW(v)                       (((v) << 28) & 0x10000000)
+#define BP_USBCTRL_PORTSC1_PSPD                         26
+#define BM_USBCTRL_PORTSC1_PSPD                         0xc000000
+#define BV_USBCTRL_PORTSC1_PSPD__FULL                   0x0
+#define BV_USBCTRL_PORTSC1_PSPD__LOW                    0x1
+#define BV_USBCTRL_PORTSC1_PSPD__HIGH                   0x2
+#define BF_USBCTRL_PORTSC1_PSPD(v)                      (((v) << 26) & 0xc000000)
+#define BF_USBCTRL_PORTSC1_PSPD_V(v)                    ((BV_USBCTRL_PORTSC1_PSPD__##v << 26) & 0xc000000)
+#define BP_USBCTRL_PORTSC1_SRT                          25
+#define BM_USBCTRL_PORTSC1_SRT                          0x2000000
+#define BF_USBCTRL_PORTSC1_SRT(v)                       (((v) << 25) & 0x2000000)
+#define BP_USBCTRL_PORTSC1_PFSC                         24
+#define BM_USBCTRL_PORTSC1_PFSC                         0x1000000
+#define BF_USBCTRL_PORTSC1_PFSC(v)                      (((v) << 24) & 0x1000000)
+#define BP_USBCTRL_PORTSC1_PHCD                         23
+#define BM_USBCTRL_PORTSC1_PHCD                         0x800000
+#define BF_USBCTRL_PORTSC1_PHCD(v)                      (((v) << 23) & 0x800000)
+#define BP_USBCTRL_PORTSC1_WKOC                         22
+#define BM_USBCTRL_PORTSC1_WKOC                         0x400000
+#define BF_USBCTRL_PORTSC1_WKOC(v)                      (((v) << 22) & 0x400000)
+#define BP_USBCTRL_PORTSC1_WKDS                         21
+#define BM_USBCTRL_PORTSC1_WKDS                         0x200000
+#define BF_USBCTRL_PORTSC1_WKDS(v)                      (((v) << 21) & 0x200000)
+#define BP_USBCTRL_PORTSC1_WKCN                         20
+#define BM_USBCTRL_PORTSC1_WKCN                         0x100000
+#define BF_USBCTRL_PORTSC1_WKCN(v)                      (((v) << 20) & 0x100000)
+#define BP_USBCTRL_PORTSC1_PTC                          16
+#define BM_USBCTRL_PORTSC1_PTC                          0xf0000
+#define BV_USBCTRL_PORTSC1_PTC__TEST_DISABLE            0x0
+#define BV_USBCTRL_PORTSC1_PTC__TEST_J_STATE            0x1
+#define BV_USBCTRL_PORTSC1_PTC__TEST_K_STATE            0x2
+#define BV_USBCTRL_PORTSC1_PTC__TEST_J_SE0_NAK          0x3
+#define BV_USBCTRL_PORTSC1_PTC__TEST_PACKET             0x4
+#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_HS    0x5
+#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_FS    0x6
+#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_LS    0x7
+#define BF_USBCTRL_PORTSC1_PTC(v)                       (((v) << 16) & 0xf0000)
+#define BF_USBCTRL_PORTSC1_PTC_V(v)                     ((BV_USBCTRL_PORTSC1_PTC__##v << 16) & 0xf0000)
+#define BP_USBCTRL_PORTSC1_PIC                          14
+#define BM_USBCTRL_PORTSC1_PIC                          0xc000
+#define BV_USBCTRL_PORTSC1_PIC__OFF                     0x0
+#define BV_USBCTRL_PORTSC1_PIC__AMBER                   0x1
+#define BV_USBCTRL_PORTSC1_PIC__GREEN                   0x2
+#define BV_USBCTRL_PORTSC1_PIC__UNDEF                   0x3
+#define BF_USBCTRL_PORTSC1_PIC(v)                       (((v) << 14) & 0xc000)
+#define BF_USBCTRL_PORTSC1_PIC_V(v)                     ((BV_USBCTRL_PORTSC1_PIC__##v << 14) & 0xc000)
+#define BP_USBCTRL_PORTSC1_PO                           13
+#define BM_USBCTRL_PORTSC1_PO                           0x2000
+#define BF_USBCTRL_PORTSC1_PO(v)                        (((v) << 13) & 0x2000)
+#define BP_USBCTRL_PORTSC1_PP                           12
+#define BM_USBCTRL_PORTSC1_PP                           0x1000
+#define BF_USBCTRL_PORTSC1_PP(v)                        (((v) << 12) & 0x1000)
+#define BP_USBCTRL_PORTSC1_LS                           10
+#define BM_USBCTRL_PORTSC1_LS                           0xc00
+#define BV_USBCTRL_PORTSC1_LS__SE0                      0x0
+#define BV_USBCTRL_PORTSC1_LS__K_STATE                  0x1
+#define BV_USBCTRL_PORTSC1_LS__J_STATE                  0x2
+#define BV_USBCTRL_PORTSC1_LS__UNDEF                    0x3
+#define BF_USBCTRL_PORTSC1_LS(v)                        (((v) << 10) & 0xc00)
+#define BF_USBCTRL_PORTSC1_LS_V(v)                      ((BV_USBCTRL_PORTSC1_LS__##v << 10) & 0xc00)
+#define BP_USBCTRL_PORTSC1_HSP                          9
+#define BM_USBCTRL_PORTSC1_HSP                          0x200
+#define BF_USBCTRL_PORTSC1_HSP(v)                       (((v) << 9) & 0x200)
+#define BP_USBCTRL_PORTSC1_PR                           8
+#define BM_USBCTRL_PORTSC1_PR                           0x100
+#define BF_USBCTRL_PORTSC1_PR(v)                        (((v) << 8) & 0x100)
+#define BP_USBCTRL_PORTSC1_SUSP                         7
+#define BM_USBCTRL_PORTSC1_SUSP                         0x80
+#define BF_USBCTRL_PORTSC1_SUSP(v)                      (((v) << 7) & 0x80)
+#define BP_USBCTRL_PORTSC1_FPR                          6
+#define BM_USBCTRL_PORTSC1_FPR                          0x40
+#define BF_USBCTRL_PORTSC1_FPR(v)                       (((v) << 6) & 0x40)
+#define BP_USBCTRL_PORTSC1_OCC                          5
+#define BM_USBCTRL_PORTSC1_OCC                          0x20
+#define BF_USBCTRL_PORTSC1_OCC(v)                       (((v) << 5) & 0x20)
+#define BP_USBCTRL_PORTSC1_OCA                          4
+#define BM_USBCTRL_PORTSC1_OCA                          0x10
+#define BF_USBCTRL_PORTSC1_OCA(v)                       (((v) << 4) & 0x10)
+#define BP_USBCTRL_PORTSC1_PEC                          3
+#define BM_USBCTRL_PORTSC1_PEC                          0x8
+#define BF_USBCTRL_PORTSC1_PEC(v)                       (((v) << 3) & 0x8)
+#define BP_USBCTRL_PORTSC1_PE                           2
+#define BM_USBCTRL_PORTSC1_PE                           0x4
+#define BF_USBCTRL_PORTSC1_PE(v)                        (((v) << 2) & 0x4)
+#define BP_USBCTRL_PORTSC1_CSC                          1
+#define BM_USBCTRL_PORTSC1_CSC                          0x2
+#define BF_USBCTRL_PORTSC1_CSC(v)                       (((v) << 1) & 0x2)
+#define BP_USBCTRL_PORTSC1_CCS                          0
+#define BM_USBCTRL_PORTSC1_CCS                          0x1
+#define BF_USBCTRL_PORTSC1_CCS(v)                       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_OTGSC
+ * Address: 0x1a4
+ * SCT: no
+*/
+#define HW_USBCTRL_OTGSC            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a4))
+#define BP_USBCTRL_OTGSC_RSVD2      31
+#define BM_USBCTRL_OTGSC_RSVD2      0x80000000
+#define BF_USBCTRL_OTGSC_RSVD2(v)   (((v) << 31) & 0x80000000)
+#define BP_USBCTRL_OTGSC_DPIE       30
+#define BM_USBCTRL_OTGSC_DPIE       0x40000000
+#define BF_USBCTRL_OTGSC_DPIE(v)    (((v) << 30) & 0x40000000)
+#define BP_USBCTRL_OTGSC_ONEMSE     29
+#define BM_USBCTRL_OTGSC_ONEMSE     0x20000000
+#define BF_USBCTRL_OTGSC_ONEMSE(v)  (((v) << 29) & 0x20000000)
+#define BP_USBCTRL_OTGSC_BSEIE      28
+#define BM_USBCTRL_OTGSC_BSEIE      0x10000000
+#define BF_USBCTRL_OTGSC_BSEIE(v)   (((v) << 28) & 0x10000000)
+#define BP_USBCTRL_OTGSC_BSVIE      27
+#define BM_USBCTRL_OTGSC_BSVIE      0x8000000
+#define BF_USBCTRL_OTGSC_BSVIE(v)   (((v) << 27) & 0x8000000)
+#define BP_USBCTRL_OTGSC_ASVIE      26
+#define BM_USBCTRL_OTGSC_ASVIE      0x4000000
+#define BF_USBCTRL_OTGSC_ASVIE(v)   (((v) << 26) & 0x4000000)
+#define BP_USBCTRL_OTGSC_AVVIE      25
+#define BM_USBCTRL_OTGSC_AVVIE      0x2000000
+#define BF_USBCTRL_OTGSC_AVVIE(v)   (((v) << 25) & 0x2000000)
+#define BP_USBCTRL_OTGSC_IDIE       24
+#define BM_USBCTRL_OTGSC_IDIE       0x1000000
+#define BF_USBCTRL_OTGSC_IDIE(v)    (((v) << 24) & 0x1000000)
+#define BP_USBCTRL_OTGSC_RSVD1      23
+#define BM_USBCTRL_OTGSC_RSVD1      0x800000
+#define BF_USBCTRL_OTGSC_RSVD1(v)   (((v) << 23) & 0x800000)
+#define BP_USBCTRL_OTGSC_DPIS       22
+#define BM_USBCTRL_OTGSC_DPIS       0x400000
+#define BF_USBCTRL_OTGSC_DPIS(v)    (((v) << 22) & 0x400000)
+#define BP_USBCTRL_OTGSC_ONEMSS     21
+#define BM_USBCTRL_OTGSC_ONEMSS     0x200000
+#define BF_USBCTRL_OTGSC_ONEMSS(v)  (((v) << 21) & 0x200000)
+#define BP_USBCTRL_OTGSC_BSEIS      20
+#define BM_USBCTRL_OTGSC_BSEIS      0x100000
+#define BF_USBCTRL_OTGSC_BSEIS(v)   (((v) << 20) & 0x100000)
+#define BP_USBCTRL_OTGSC_BSVIS      19
+#define BM_USBCTRL_OTGSC_BSVIS      0x80000
+#define BF_USBCTRL_OTGSC_BSVIS(v)   (((v) << 19) & 0x80000)
+#define BP_USBCTRL_OTGSC_ASVIS      18
+#define BM_USBCTRL_OTGSC_ASVIS      0x40000
+#define BF_USBCTRL_OTGSC_ASVIS(v)   (((v) << 18) & 0x40000)
+#define BP_USBCTRL_OTGSC_AVVIS      17
+#define BM_USBCTRL_OTGSC_AVVIS      0x20000
+#define BF_USBCTRL_OTGSC_AVVIS(v)   (((v) << 17) & 0x20000)
+#define BP_USBCTRL_OTGSC_IDIS       16
+#define BM_USBCTRL_OTGSC_IDIS       0x10000
+#define BF_USBCTRL_OTGSC_IDIS(v)    (((v) << 16) & 0x10000)
+#define BP_USBCTRL_OTGSC_RSVD0      15
+#define BM_USBCTRL_OTGSC_RSVD0      0x8000
+#define BF_USBCTRL_OTGSC_RSVD0(v)   (((v) << 15) & 0x8000)
+#define BP_USBCTRL_OTGSC_DPS        14
+#define BM_USBCTRL_OTGSC_DPS        0x4000
+#define BF_USBCTRL_OTGSC_DPS(v)     (((v) << 14) & 0x4000)
+#define BP_USBCTRL_OTGSC_ONEMST     13
+#define BM_USBCTRL_OTGSC_ONEMST     0x2000
+#define BF_USBCTRL_OTGSC_ONEMST(v)  (((v) << 13) & 0x2000)
+#define BP_USBCTRL_OTGSC_BSE        12
+#define BM_USBCTRL_OTGSC_BSE        0x1000
+#define BF_USBCTRL_OTGSC_BSE(v)     (((v) << 12) & 0x1000)
+#define BP_USBCTRL_OTGSC_BSV        11
+#define BM_USBCTRL_OTGSC_BSV        0x800
+#define BF_USBCTRL_OTGSC_BSV(v)     (((v) << 11) & 0x800)
+#define BP_USBCTRL_OTGSC_ASV        10
+#define BM_USBCTRL_OTGSC_ASV        0x400
+#define BF_USBCTRL_OTGSC_ASV(v)     (((v) << 10) & 0x400)
+#define BP_USBCTRL_OTGSC_AVV        9
+#define BM_USBCTRL_OTGSC_AVV        0x200
+#define BF_USBCTRL_OTGSC_AVV(v)     (((v) << 9) & 0x200)
+#define BP_USBCTRL_OTGSC_ID         8
+#define BM_USBCTRL_OTGSC_ID         0x100
+#define BF_USBCTRL_OTGSC_ID(v)      (((v) << 8) & 0x100)
+#define BP_USBCTRL_OTGSC_HABA       7
+#define BM_USBCTRL_OTGSC_HABA       0x80
+#define BF_USBCTRL_OTGSC_HABA(v)    (((v) << 7) & 0x80)
+#define BP_USBCTRL_OTGSC_HADP       6
+#define BM_USBCTRL_OTGSC_HADP       0x40
+#define BF_USBCTRL_OTGSC_HADP(v)    (((v) << 6) & 0x40)
+#define BP_USBCTRL_OTGSC_IDPU       5
+#define BM_USBCTRL_OTGSC_IDPU       0x20
+#define BF_USBCTRL_OTGSC_IDPU(v)    (((v) << 5) & 0x20)
+#define BP_USBCTRL_OTGSC_DP         4
+#define BM_USBCTRL_OTGSC_DP         0x10
+#define BF_USBCTRL_OTGSC_DP(v)      (((v) << 4) & 0x10)
+#define BP_USBCTRL_OTGSC_OT         3
+#define BM_USBCTRL_OTGSC_OT         0x8
+#define BF_USBCTRL_OTGSC_OT(v)      (((v) << 3) & 0x8)
+#define BP_USBCTRL_OTGSC_HAAR       2
+#define BM_USBCTRL_OTGSC_HAAR       0x4
+#define BF_USBCTRL_OTGSC_HAAR(v)    (((v) << 2) & 0x4)
+#define BP_USBCTRL_OTGSC_VC         1
+#define BM_USBCTRL_OTGSC_VC         0x2
+#define BF_USBCTRL_OTGSC_VC(v)      (((v) << 1) & 0x2)
+#define BP_USBCTRL_OTGSC_VD         0
+#define BM_USBCTRL_OTGSC_VD         0x1
+#define BF_USBCTRL_OTGSC_VD(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_USBMODE
+ * Address: 0x1a8
+ * SCT: no
+*/
+#define HW_USBCTRL_USBMODE              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a8))
+#define BP_USBCTRL_USBMODE_RSVD         6
+#define BM_USBCTRL_USBMODE_RSVD         0xffffffc0
+#define BF_USBCTRL_USBMODE_RSVD(v)      (((v) << 6) & 0xffffffc0)
+#define BP_USBCTRL_USBMODE_VBPS         5
+#define BM_USBCTRL_USBMODE_VBPS         0x20
+#define BF_USBCTRL_USBMODE_VBPS(v)      (((v) << 5) & 0x20)
+#define BP_USBCTRL_USBMODE_SDIS         4
+#define BM_USBCTRL_USBMODE_SDIS         0x10
+#define BF_USBCTRL_USBMODE_SDIS(v)      (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBMODE_SLOM         3
+#define BM_USBCTRL_USBMODE_SLOM         0x8
+#define BF_USBCTRL_USBMODE_SLOM(v)      (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBMODE_ES           2
+#define BM_USBCTRL_USBMODE_ES           0x4
+#define BF_USBCTRL_USBMODE_ES(v)        (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBMODE_CM           0
+#define BM_USBCTRL_USBMODE_CM           0x3
+#define BV_USBCTRL_USBMODE_CM__IDLE     0x0
+#define BV_USBCTRL_USBMODE_CM__DEVICE   0x2
+#define BV_USBCTRL_USBMODE_CM__HOST     0x3
+#define BF_USBCTRL_USBMODE_CM(v)        (((v) << 0) & 0x3)
+#define BF_USBCTRL_USBMODE_CM_V(v)      ((BV_USBCTRL_USBMODE_CM__##v << 0) & 0x3)
+
+/**
+ * Register: HW_USBCTRL_ENDPTSETUPSTAT
+ * Address: 0x1ac
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTSETUPSTAT                   (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1ac))
+#define BP_USBCTRL_ENDPTSETUPSTAT_RSVD              5
+#define BM_USBCTRL_ENDPTSETUPSTAT_RSVD              0xffffffe0
+#define BF_USBCTRL_ENDPTSETUPSTAT_RSVD(v)           (((v) << 5) & 0xffffffe0)
+#define BP_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT    0
+#define BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT    0x1f
+#define BF_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_ENDPTPRIME
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTPRIME           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b0))
+#define BP_USBCTRL_ENDPTPRIME_RSVD1     21
+#define BM_USBCTRL_ENDPTPRIME_RSVD1     0xffe00000
+#define BF_USBCTRL_ENDPTPRIME_RSVD1(v)  (((v) << 21) & 0xffe00000)
+#define BP_USBCTRL_ENDPTPRIME_PETB      16
+#define BM_USBCTRL_ENDPTPRIME_PETB      0x1f0000
+#define BF_USBCTRL_ENDPTPRIME_PETB(v)   (((v) << 16) & 0x1f0000)
+#define BP_USBCTRL_ENDPTPRIME_RSVD0     5
+#define BM_USBCTRL_ENDPTPRIME_RSVD0     0xffe0
+#define BF_USBCTRL_ENDPTPRIME_RSVD0(v)  (((v) << 5) & 0xffe0)
+#define BP_USBCTRL_ENDPTPRIME_PERB      0
+#define BM_USBCTRL_ENDPTPRIME_PERB      0x1f
+#define BF_USBCTRL_ENDPTPRIME_PERB(v)   (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_ENDPTFLUSH
+ * Address: 0x1b4
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTFLUSH           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b4))
+#define BP_USBCTRL_ENDPTFLUSH_RSVD1     21
+#define BM_USBCTRL_ENDPTFLUSH_RSVD1     0xffe00000
+#define BF_USBCTRL_ENDPTFLUSH_RSVD1(v)  (((v) << 21) & 0xffe00000)
+#define BP_USBCTRL_ENDPTFLUSH_FETB      16
+#define BM_USBCTRL_ENDPTFLUSH_FETB      0x1f0000
+#define BF_USBCTRL_ENDPTFLUSH_FETB(v)   (((v) << 16) & 0x1f0000)
+#define BP_USBCTRL_ENDPTFLUSH_RSVD0     5
+#define BM_USBCTRL_ENDPTFLUSH_RSVD0     0xffe0
+#define BF_USBCTRL_ENDPTFLUSH_RSVD0(v)  (((v) << 5) & 0xffe0)
+#define BP_USBCTRL_ENDPTFLUSH_FERB      0
+#define BM_USBCTRL_ENDPTFLUSH_FERB      0x1f
+#define BF_USBCTRL_ENDPTFLUSH_FERB(v)   (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_ENDPTSTAT
+ * Address: 0x1b8
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTSTAT            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b8))
+#define BP_USBCTRL_ENDPTSTAT_RSVD1      21
+#define BM_USBCTRL_ENDPTSTAT_RSVD1      0xffe00000
+#define BF_USBCTRL_ENDPTSTAT_RSVD1(v)   (((v) << 21) & 0xffe00000)
+#define BP_USBCTRL_ENDPTSTAT_ETBR       16
+#define BM_USBCTRL_ENDPTSTAT_ETBR       0x1f0000
+#define BF_USBCTRL_ENDPTSTAT_ETBR(v)    (((v) << 16) & 0x1f0000)
+#define BP_USBCTRL_ENDPTSTAT_RSVD0      5
+#define BM_USBCTRL_ENDPTSTAT_RSVD0      0xffe0
+#define BF_USBCTRL_ENDPTSTAT_RSVD0(v)   (((v) << 5) & 0xffe0)
+#define BP_USBCTRL_ENDPTSTAT_ERBR       0
+#define BM_USBCTRL_ENDPTSTAT_ERBR       0x1f
+#define BF_USBCTRL_ENDPTSTAT_ERBR(v)    (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_ENDPTCOMPLETE
+ * Address: 0x1bc
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTCOMPLETE            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1bc))
+#define BP_USBCTRL_ENDPTCOMPLETE_RSVD1      21
+#define BM_USBCTRL_ENDPTCOMPLETE_RSVD1      0xffe00000
+#define BF_USBCTRL_ENDPTCOMPLETE_RSVD1(v)   (((v) << 21) & 0xffe00000)
+#define BP_USBCTRL_ENDPTCOMPLETE_ETCE       16
+#define BM_USBCTRL_ENDPTCOMPLETE_ETCE       0x1f0000
+#define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v)    (((v) << 16) & 0x1f0000)
+#define BP_USBCTRL_ENDPTCOMPLETE_RSVD0      5
+#define BM_USBCTRL_ENDPTCOMPLETE_RSVD0      0xffe0
+#define BF_USBCTRL_ENDPTCOMPLETE_RSVD0(v)   (((v) << 5) & 0xffe0)
+#define BP_USBCTRL_ENDPTCOMPLETE_ERCE       0
+#define BM_USBCTRL_ENDPTCOMPLETE_ERCE       0x1f
+#define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v)    (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_ENDPTCTRLn
+ * Address: 0x1c0+n*0x4
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTCTRLn(n)            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c0+(n)*0x4))
+#define BP_USBCTRL_ENDPTCTRLn_RSVD6         24
+#define BM_USBCTRL_ENDPTCTRLn_RSVD6         0xff000000
+#define BF_USBCTRL_ENDPTCTRLn_RSVD6(v)      (((v) << 24) & 0xff000000)
+#define BP_USBCTRL_ENDPTCTRLn_TXE           23
+#define BM_USBCTRL_ENDPTCTRLn_TXE           0x800000
+#define BF_USBCTRL_ENDPTCTRLn_TXE(v)        (((v) << 23) & 0x800000)
+#define BP_USBCTRL_ENDPTCTRLn_TXR           22
+#define BM_USBCTRL_ENDPTCTRLn_TXR           0x400000
+#define BF_USBCTRL_ENDPTCTRLn_TXR(v)        (((v) << 22) & 0x400000)
+#define BP_USBCTRL_ENDPTCTRLn_TXI           21
+#define BM_USBCTRL_ENDPTCTRLn_TXI           0x200000
+#define BF_USBCTRL_ENDPTCTRLn_TXI(v)        (((v) << 21) & 0x200000)
+#define BP_USBCTRL_ENDPTCTRLn_RSVD5         20
+#define BM_USBCTRL_ENDPTCTRLn_RSVD5         0x100000
+#define BF_USBCTRL_ENDPTCTRLn_RSVD5(v)      (((v) << 20) & 0x100000)
+#define BP_USBCTRL_ENDPTCTRLn_TXT           18
+#define BM_USBCTRL_ENDPTCTRLn_TXT           0xc0000
+#define BV_USBCTRL_ENDPTCTRLn_TXT__CONTROL  0x0
+#define BV_USBCTRL_ENDPTCTRLn_TXT__ISO      0x1
+#define BV_USBCTRL_ENDPTCTRLn_TXT__BULK     0x2
+#define BV_USBCTRL_ENDPTCTRLn_TXT__INT      0x3
+#define BF_USBCTRL_ENDPTCTRLn_TXT(v)        (((v) << 18) & 0xc0000)
+#define BF_USBCTRL_ENDPTCTRLn_TXT_V(v)      ((BV_USBCTRL_ENDPTCTRLn_TXT__##v << 18) & 0xc0000)
+#define BP_USBCTRL_ENDPTCTRLn_TXD           17
+#define BM_USBCTRL_ENDPTCTRLn_TXD           0x20000
+#define BF_USBCTRL_ENDPTCTRLn_TXD(v)        (((v) << 17) & 0x20000)
+#define BP_USBCTRL_ENDPTCTRLn_TXS           16
+#define BM_USBCTRL_ENDPTCTRLn_TXS           0x10000
+#define BF_USBCTRL_ENDPTCTRLn_TXS(v)        (((v) << 16) & 0x10000)
+#define BP_USBCTRL_ENDPTCTRLn_RSVD3         8
+#define BM_USBCTRL_ENDPTCTRLn_RSVD3         0xff00
+#define BF_USBCTRL_ENDPTCTRLn_RSVD3(v)      (((v) << 8) & 0xff00)
+#define BP_USBCTRL_ENDPTCTRLn_RXE           7
+#define BM_USBCTRL_ENDPTCTRLn_RXE           0x80
+#define BF_USBCTRL_ENDPTCTRLn_RXE(v)        (((v) << 7) & 0x80)
+#define BP_USBCTRL_ENDPTCTRLn_RXR           6
+#define BM_USBCTRL_ENDPTCTRLn_RXR           0x40
+#define BF_USBCTRL_ENDPTCTRLn_RXR(v)        (((v) << 6) & 0x40)
+#define BP_USBCTRL_ENDPTCTRLn_RXI           5
+#define BM_USBCTRL_ENDPTCTRLn_RXI           0x20
+#define BF_USBCTRL_ENDPTCTRLn_RXI(v)        (((v) << 5) & 0x20)
+#define BP_USBCTRL_ENDPTCTRLn_RSVD2         4
+#define BM_USBCTRL_ENDPTCTRLn_RSVD2         0x10
+#define BF_USBCTRL_ENDPTCTRLn_RSVD2(v)      (((v) << 4) & 0x10)
+#define BP_USBCTRL_ENDPTCTRLn_RXT           2
+#define BM_USBCTRL_ENDPTCTRLn_RXT           0xc
+#define BV_USBCTRL_ENDPTCTRLn_RXT__CONTROL  0x0
+#define BV_USBCTRL_ENDPTCTRLn_RXT__ISO      0x1
+#define BV_USBCTRL_ENDPTCTRLn_RXT__BULK     0x2
+#define BV_USBCTRL_ENDPTCTRLn_RXT__INT      0x3
+#define BF_USBCTRL_ENDPTCTRLn_RXT(v)        (((v) << 2) & 0xc)
+#define BF_USBCTRL_ENDPTCTRLn_RXT_V(v)      ((BV_USBCTRL_ENDPTCTRLn_RXT__##v << 2) & 0xc)
+#define BP_USBCTRL_ENDPTCTRLn_RXD           1
+#define BM_USBCTRL_ENDPTCTRLn_RXD           0x2
+#define BF_USBCTRL_ENDPTCTRLn_RXD(v)        (((v) << 1) & 0x2)
+#define BP_USBCTRL_ENDPTCTRLn_RXS           0
+#define BM_USBCTRL_ENDPTCTRLn_RXS           0x1
+#define BF_USBCTRL_ENDPTCTRLn_RXS(v)        (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__IMX233__USBCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h b/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h
new file mode 100644
index 0000000000..e20871b0df
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-usbphy.h
@@ -0,0 +1,421 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__USBPHY__H__
+#define __HEADERGEN__IMX233__USBPHY__H__
+
+#define REGS_USBPHY_BASE (0x8007c000)
+
+#define REGS_USBPHY_VERSION "3.2.0"
+
+/**
+ * Register: HW_USBPHY_PWD
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_USBPHY_PWD               (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0))
+#define HW_USBPHY_PWD_SET           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4))
+#define HW_USBPHY_PWD_CLR           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8))
+#define HW_USBPHY_PWD_TOG           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc))
+#define BP_USBPHY_PWD_RSVD2         21
+#define BM_USBPHY_PWD_RSVD2         0xffe00000
+#define BF_USBPHY_PWD_RSVD2(v)      (((v) << 21) & 0xffe00000)
+#define BP_USBPHY_PWD_RXPWDRX       20
+#define BM_USBPHY_PWD_RXPWDRX       0x100000
+#define BF_USBPHY_PWD_RXPWDRX(v)    (((v) << 20) & 0x100000)
+#define BP_USBPHY_PWD_RXPWDDIFF     19
+#define BM_USBPHY_PWD_RXPWDDIFF     0x80000
+#define BF_USBPHY_PWD_RXPWDDIFF(v)  (((v) << 19) & 0x80000)
+#define BP_USBPHY_PWD_RXPWD1PT1     18
+#define BM_USBPHY_PWD_RXPWD1PT1     0x40000
+#define BF_USBPHY_PWD_RXPWD1PT1(v)  (((v) << 18) & 0x40000)
+#define BP_USBPHY_PWD_RXPWDENV      17
+#define BM_USBPHY_PWD_RXPWDENV      0x20000
+#define BF_USBPHY_PWD_RXPWDENV(v)   (((v) << 17) & 0x20000)
+#define BP_USBPHY_PWD_RSVD1         13
+#define BM_USBPHY_PWD_RSVD1         0x1e000
+#define BF_USBPHY_PWD_RSVD1(v)      (((v) << 13) & 0x1e000)
+#define BP_USBPHY_PWD_TXPWDV2I      12
+#define BM_USBPHY_PWD_TXPWDV2I      0x1000
+#define BF_USBPHY_PWD_TXPWDV2I(v)   (((v) << 12) & 0x1000)
+#define BP_USBPHY_PWD_TXPWDIBIAS    11
+#define BM_USBPHY_PWD_TXPWDIBIAS    0x800
+#define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800)
+#define BP_USBPHY_PWD_TXPWDFS       10
+#define BM_USBPHY_PWD_TXPWDFS       0x400
+#define BF_USBPHY_PWD_TXPWDFS(v)    (((v) << 10) & 0x400)
+#define BP_USBPHY_PWD_RSVD0         0
+#define BM_USBPHY_PWD_RSVD0         0x3ff
+#define BF_USBPHY_PWD_RSVD0(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_USBPHY_TX
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_USBPHY_TX                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0))
+#define HW_USBPHY_TX_SET                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4))
+#define HW_USBPHY_TX_CLR                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8))
+#define HW_USBPHY_TX_TOG                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc))
+#define BP_USBPHY_TX_RSVD5                      29
+#define BM_USBPHY_TX_RSVD5                      0xe0000000
+#define BF_USBPHY_TX_RSVD5(v)                   (((v) << 29) & 0xe0000000)
+#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL         26
+#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL         0x1c000000
+#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v)      (((v) << 26) & 0x1c000000)
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT      25
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT      0x2000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)   (((v) << 25) & 0x2000000)
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX         24
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX         0x1000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)      (((v) << 24) & 0x1000000)
+#define BP_USBPHY_TX_RSVD4                      22
+#define BM_USBPHY_TX_RSVD4                      0xc00000
+#define BF_USBPHY_TX_RSVD4(v)                   (((v) << 22) & 0xc00000)
+#define BP_USBPHY_TX_TXENCAL45DP                21
+#define BM_USBPHY_TX_TXENCAL45DP                0x200000
+#define BF_USBPHY_TX_TXENCAL45DP(v)             (((v) << 21) & 0x200000)
+#define BP_USBPHY_TX_RSVD3                      20
+#define BM_USBPHY_TX_RSVD3                      0x100000
+#define BF_USBPHY_TX_RSVD3(v)                   (((v) << 20) & 0x100000)
+#define BP_USBPHY_TX_TXCAL45DP                  16
+#define BM_USBPHY_TX_TXCAL45DP                  0xf0000
+#define BF_USBPHY_TX_TXCAL45DP(v)               (((v) << 16) & 0xf0000)
+#define BP_USBPHY_TX_RSVD2                      14
+#define BM_USBPHY_TX_RSVD2                      0xc000
+#define BF_USBPHY_TX_RSVD2(v)                   (((v) << 14) & 0xc000)
+#define BP_USBPHY_TX_TXENCAL45DN                13
+#define BM_USBPHY_TX_TXENCAL45DN                0x2000
+#define BF_USBPHY_TX_TXENCAL45DN(v)             (((v) << 13) & 0x2000)
+#define BP_USBPHY_TX_RSVD1                      12
+#define BM_USBPHY_TX_RSVD1                      0x1000
+#define BF_USBPHY_TX_RSVD1(v)                   (((v) << 12) & 0x1000)
+#define BP_USBPHY_TX_TXCAL45DN                  8
+#define BM_USBPHY_TX_TXCAL45DN                  0xf00
+#define BF_USBPHY_TX_TXCAL45DN(v)               (((v) << 8) & 0xf00)
+#define BP_USBPHY_TX_RSVD0                      4
+#define BM_USBPHY_TX_RSVD0                      0xf0
+#define BF_USBPHY_TX_RSVD0(v)                   (((v) << 4) & 0xf0)
+#define BP_USBPHY_TX_D_CAL                      0
+#define BM_USBPHY_TX_D_CAL                      0xf
+#define BF_USBPHY_TX_D_CAL(v)                   (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_USBPHY_RX
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_USBPHY_RX                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0))
+#define HW_USBPHY_RX_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4))
+#define HW_USBPHY_RX_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8))
+#define HW_USBPHY_RX_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc))
+#define BP_USBPHY_RX_RSVD2          23
+#define BM_USBPHY_RX_RSVD2          0xff800000
+#define BF_USBPHY_RX_RSVD2(v)       (((v) << 23) & 0xff800000)
+#define BP_USBPHY_RX_RXDBYPASS      22
+#define BM_USBPHY_RX_RXDBYPASS      0x400000
+#define BF_USBPHY_RX_RXDBYPASS(v)   (((v) << 22) & 0x400000)
+#define BP_USBPHY_RX_RSVD1          7
+#define BM_USBPHY_RX_RSVD1          0x3fff80
+#define BF_USBPHY_RX_RSVD1(v)       (((v) << 7) & 0x3fff80)
+#define BP_USBPHY_RX_DISCONADJ      4
+#define BM_USBPHY_RX_DISCONADJ      0x70
+#define BF_USBPHY_RX_DISCONADJ(v)   (((v) << 4) & 0x70)
+#define BP_USBPHY_RX_RSVD0          3
+#define BM_USBPHY_RX_RSVD0          0x8
+#define BF_USBPHY_RX_RSVD0(v)       (((v) << 3) & 0x8)
+#define BP_USBPHY_RX_ENVADJ         0
+#define BM_USBPHY_RX_ENVADJ         0x7
+#define BF_USBPHY_RX_ENVADJ(v)      (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_USBPHY_CTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_USBPHY_CTRL                          (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0))
+#define HW_USBPHY_CTRL_SET                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4))
+#define HW_USBPHY_CTRL_CLR                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8))
+#define HW_USBPHY_CTRL_TOG                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc))
+#define BP_USBPHY_CTRL_SFTRST                   31
+#define BM_USBPHY_CTRL_SFTRST                   0x80000000
+#define BF_USBPHY_CTRL_SFTRST(v)                (((v) << 31) & 0x80000000)
+#define BP_USBPHY_CTRL_CLKGATE                  30
+#define BM_USBPHY_CTRL_CLKGATE                  0x40000000
+#define BF_USBPHY_CTRL_CLKGATE(v)               (((v) << 30) & 0x40000000)
+#define BP_USBPHY_CTRL_UTMI_SUSPENDM            29
+#define BM_USBPHY_CTRL_UTMI_SUSPENDM            0x20000000
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)         (((v) << 29) & 0x20000000)
+#define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0        28
+#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0        0x10000000
+#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)     (((v) << 28) & 0x10000000)
+#define BP_USBPHY_CTRL_RSVD3                    14
+#define BM_USBPHY_CTRL_RSVD3                    0xfffc000
+#define BF_USBPHY_CTRL_RSVD3(v)                 (((v) << 14) & 0xfffc000)
+#define BP_USBPHY_CTRL_DATA_ON_LRADC            13
+#define BM_USBPHY_CTRL_DATA_ON_LRADC            0x2000
+#define BF_USBPHY_CTRL_DATA_ON_LRADC(v)         (((v) << 13) & 0x2000)
+#define BP_USBPHY_CTRL_DEVPLUGIN_IRQ            12
+#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ            0x1000
+#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v)         (((v) << 12) & 0x1000)
+#define BP_USBPHY_CTRL_ENIRQDEVPLUGIN           11
+#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN           0x800
+#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v)        (((v) << 11) & 0x800)
+#define BP_USBPHY_CTRL_RESUME_IRQ               10
+#define BM_USBPHY_CTRL_RESUME_IRQ               0x400
+#define BF_USBPHY_CTRL_RESUME_IRQ(v)            (((v) << 10) & 0x400)
+#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT        9
+#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT        0x200
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)     (((v) << 9) & 0x200)
+#define BP_USBPHY_CTRL_RSVD2                    8
+#define BM_USBPHY_CTRL_RSVD2                    0x100
+#define BF_USBPHY_CTRL_RSVD2(v)                 (((v) << 8) & 0x100)
+#define BP_USBPHY_CTRL_ENOTGIDDETECT            7
+#define BM_USBPHY_CTRL_ENOTGIDDETECT            0x80
+#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)         (((v) << 7) & 0x80)
+#define BP_USBPHY_CTRL_RSVD1                    6
+#define BM_USBPHY_CTRL_RSVD1                    0x40
+#define BF_USBPHY_CTRL_RSVD1(v)                 (((v) << 6) & 0x40)
+#define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY       5
+#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY       0x20
+#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)    (((v) << 5) & 0x20)
+#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT        4
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x10
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)     (((v) << 4) & 0x10)
+#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     3
+#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     0x8
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)  (((v) << 3) & 0x8)
+#define BP_USBPHY_CTRL_ENIRQHOSTDISCON          2
+#define BM_USBPHY_CTRL_ENIRQHOSTDISCON          0x4
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)       (((v) << 2) & 0x4)
+#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT       1
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x2
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)    (((v) << 1) & 0x2)
+#define BP_USBPHY_CTRL_RSVD0                    0
+#define BM_USBPHY_CTRL_RSVD0                    0x1
+#define BF_USBPHY_CTRL_RSVD0(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBPHY_STATUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_USBPHY_STATUS                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40))
+#define BP_USBPHY_STATUS_RSVD4                      11
+#define BM_USBPHY_STATUS_RSVD4                      0xfffff800
+#define BF_USBPHY_STATUS_RSVD4(v)                   (((v) << 11) & 0xfffff800)
+#define BP_USBPHY_STATUS_RESUME_STATUS              10
+#define BM_USBPHY_STATUS_RESUME_STATUS              0x400
+#define BF_USBPHY_STATUS_RESUME_STATUS(v)           (((v) << 10) & 0x400)
+#define BP_USBPHY_STATUS_RSVD3                      9
+#define BM_USBPHY_STATUS_RSVD3                      0x200
+#define BF_USBPHY_STATUS_RSVD3(v)                   (((v) << 9) & 0x200)
+#define BP_USBPHY_STATUS_OTGID_STATUS               8
+#define BM_USBPHY_STATUS_OTGID_STATUS               0x100
+#define BF_USBPHY_STATUS_OTGID_STATUS(v)            (((v) << 8) & 0x100)
+#define BP_USBPHY_STATUS_RSVD2                      7
+#define BM_USBPHY_STATUS_RSVD2                      0x80
+#define BF_USBPHY_STATUS_RSVD2(v)                   (((v) << 7) & 0x80)
+#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS           6
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS           0x40
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)        (((v) << 6) & 0x40)
+#define BP_USBPHY_STATUS_RSVD1                      4
+#define BM_USBPHY_STATUS_RSVD1                      0x30
+#define BF_USBPHY_STATUS_RSVD1(v)                   (((v) << 4) & 0x30)
+#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    3
+#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    0x8
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8)
+#define BP_USBPHY_STATUS_RSVD0                      0
+#define BM_USBPHY_STATUS_RSVD0                      0x7
+#define BF_USBPHY_STATUS_RSVD0(v)                   (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_USBPHY_DEBUG
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_USBPHY_DEBUG                         (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0))
+#define HW_USBPHY_DEBUG_SET                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4))
+#define HW_USBPHY_DEBUG_CLR                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8))
+#define HW_USBPHY_DEBUG_TOG                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc))
+#define BP_USBPHY_DEBUG_RSVD3                   31
+#define BM_USBPHY_DEBUG_RSVD3                   0x80000000
+#define BF_USBPHY_DEBUG_RSVD3(v)                (((v) << 31) & 0x80000000)
+#define BP_USBPHY_DEBUG_CLKGATE                 30
+#define BM_USBPHY_DEBUG_CLKGATE                 0x40000000
+#define BF_USBPHY_DEBUG_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG       29
+#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG       0x20000000
+#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)    (((v) << 29) & 0x20000000)
+#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH      25
+#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH      0x1e000000
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)   (((v) << 25) & 0x1e000000)
+#define BP_USBPHY_DEBUG_ENSQUELCHRESET          24
+#define BM_USBPHY_DEBUG_ENSQUELCHRESET          0x1000000
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)       (((v) << 24) & 0x1000000)
+#define BP_USBPHY_DEBUG_RSVD2                   21
+#define BM_USBPHY_DEBUG_RSVD2                   0xe00000
+#define BF_USBPHY_DEBUG_RSVD2(v)                (((v) << 21) & 0xe00000)
+#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT       16
+#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT       0x1f0000
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)    (((v) << 16) & 0x1f0000)
+#define BP_USBPHY_DEBUG_RSVD1                   13
+#define BM_USBPHY_DEBUG_RSVD1                   0xe000
+#define BF_USBPHY_DEBUG_RSVD1(v)                (((v) << 13) & 0xe000)
+#define BP_USBPHY_DEBUG_ENTX2RXCOUNT            12
+#define BM_USBPHY_DEBUG_ENTX2RXCOUNT            0x1000
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)         (((v) << 12) & 0x1000)
+#define BP_USBPHY_DEBUG_TX2RXCOUNT              8
+#define BM_USBPHY_DEBUG_TX2RXCOUNT              0xf00
+#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)           (((v) << 8) & 0xf00)
+#define BP_USBPHY_DEBUG_RSVD0                   6
+#define BM_USBPHY_DEBUG_RSVD0                   0xc0
+#define BF_USBPHY_DEBUG_RSVD0(v)                (((v) << 6) & 0xc0)
+#define BP_USBPHY_DEBUG_ENHSTPULLDOWN           4
+#define BM_USBPHY_DEBUG_ENHSTPULLDOWN           0x30
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)        (((v) << 4) & 0x30)
+#define BP_USBPHY_DEBUG_HSTPULLDOWN             2
+#define BM_USBPHY_DEBUG_HSTPULLDOWN             0xc
+#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)          (((v) << 2) & 0xc)
+#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    1
+#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    0x2
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2)
+#define BP_USBPHY_DEBUG_OTGIDPIOLOCK            0
+#define BM_USBPHY_DEBUG_OTGIDPIOLOCK            0x1
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBPHY_DEBUG0_STATUS
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG0_STATUS                             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60))
+#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               26
+#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               0xfc000000
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)            (((v) << 26) & 0xfc000000)
+#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     16
+#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     0x3ff0000
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)  (((v) << 16) & 0x3ff0000)
+#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0
+#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0xffff
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBPHY_DEBUG1
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_USBPHY_DEBUG1                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x0))
+#define HW_USBPHY_DEBUG1_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x4))
+#define HW_USBPHY_DEBUG1_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x8))
+#define HW_USBPHY_DEBUG1_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0xc))
+#define BP_USBPHY_DEBUG1_RSVD1          15
+#define BM_USBPHY_DEBUG1_RSVD1          0xffff8000
+#define BF_USBPHY_DEBUG1_RSVD1(v)       (((v) << 15) & 0xffff8000)
+#define BP_USBPHY_DEBUG1_ENTAILADJVD    13
+#define BM_USBPHY_DEBUG1_ENTAILADJVD    0x6000
+#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) (((v) << 13) & 0x6000)
+#define BP_USBPHY_DEBUG1_ENTX2TX        12
+#define BM_USBPHY_DEBUG1_ENTX2TX        0x1000
+#define BF_USBPHY_DEBUG1_ENTX2TX(v)     (((v) << 12) & 0x1000)
+#define BP_USBPHY_DEBUG1_RSVD0          4
+#define BM_USBPHY_DEBUG1_RSVD0          0xff0
+#define BF_USBPHY_DEBUG1_RSVD0(v)       (((v) << 4) & 0xff0)
+#define BP_USBPHY_DEBUG1_DBG_ADDRESS    0
+#define BM_USBPHY_DEBUG1_DBG_ADDRESS    0xf
+#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_USBPHY_VERSION
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_USBPHY_VERSION           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80))
+#define BP_USBPHY_VERSION_MAJOR     24
+#define BM_USBPHY_VERSION_MAJOR     0xff000000
+#define BF_USBPHY_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
+#define BP_USBPHY_VERSION_MINOR     16
+#define BM_USBPHY_VERSION_MINOR     0xff0000
+#define BF_USBPHY_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
+#define BP_USBPHY_VERSION_STEP      0
+#define BM_USBPHY_VERSION_STEP      0xffff
+#define BF_USBPHY_VERSION_STEP(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBPHY_IP
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_USBPHY_IP                    (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x0))
+#define HW_USBPHY_IP_SET                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x4))
+#define HW_USBPHY_IP_CLR                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0x8))
+#define HW_USBPHY_IP_TOG                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90 + 0xc))
+#define BP_USBPHY_IP_RSVD1              25
+#define BM_USBPHY_IP_RSVD1              0xfe000000
+#define BF_USBPHY_IP_RSVD1(v)           (((v) << 25) & 0xfe000000)
+#define BP_USBPHY_IP_DIV_SEL            23
+#define BM_USBPHY_IP_DIV_SEL            0x1800000
+#define BV_USBPHY_IP_DIV_SEL__DEFAULT   0x0
+#define BV_USBPHY_IP_DIV_SEL__LOWER     0x1
+#define BV_USBPHY_IP_DIV_SEL__LOWEST    0x2
+#define BV_USBPHY_IP_DIV_SEL__UNDEFINED 0x3
+#define BF_USBPHY_IP_DIV_SEL(v)         (((v) << 23) & 0x1800000)
+#define BF_USBPHY_IP_DIV_SEL_V(v)       ((BV_USBPHY_IP_DIV_SEL__##v << 23) & 0x1800000)
+#define BP_USBPHY_IP_LFR_SEL            21
+#define BM_USBPHY_IP_LFR_SEL            0x600000
+#define BV_USBPHY_IP_LFR_SEL__DEFAULT   0x0
+#define BV_USBPHY_IP_LFR_SEL__TIMES_2   0x1
+#define BV_USBPHY_IP_LFR_SEL__TIMES_05  0x2
+#define BV_USBPHY_IP_LFR_SEL__UNDEFINED 0x3
+#define BF_USBPHY_IP_LFR_SEL(v)         (((v) << 21) & 0x600000)
+#define BF_USBPHY_IP_LFR_SEL_V(v)       ((BV_USBPHY_IP_LFR_SEL__##v << 21) & 0x600000)
+#define BP_USBPHY_IP_CP_SEL             19
+#define BM_USBPHY_IP_CP_SEL             0x180000
+#define BV_USBPHY_IP_CP_SEL__DEFAULT    0x0
+#define BV_USBPHY_IP_CP_SEL__TIMES_2    0x1
+#define BV_USBPHY_IP_CP_SEL__TIMES_05   0x2
+#define BV_USBPHY_IP_CP_SEL__UNDEFINED  0x3
+#define BF_USBPHY_IP_CP_SEL(v)          (((v) << 19) & 0x180000)
+#define BF_USBPHY_IP_CP_SEL_V(v)        ((BV_USBPHY_IP_CP_SEL__##v << 19) & 0x180000)
+#define BP_USBPHY_IP_TSTI_TX_DP         18
+#define BM_USBPHY_IP_TSTI_TX_DP         0x40000
+#define BF_USBPHY_IP_TSTI_TX_DP(v)      (((v) << 18) & 0x40000)
+#define BP_USBPHY_IP_TSTI_TX_DM         17
+#define BM_USBPHY_IP_TSTI_TX_DM         0x20000
+#define BF_USBPHY_IP_TSTI_TX_DM(v)      (((v) << 17) & 0x20000)
+#define BP_USBPHY_IP_ANALOG_TESTMODE    16
+#define BM_USBPHY_IP_ANALOG_TESTMODE    0x10000
+#define BF_USBPHY_IP_ANALOG_TESTMODE(v) (((v) << 16) & 0x10000)
+#define BP_USBPHY_IP_RSVD0              3
+#define BM_USBPHY_IP_RSVD0              0xfff8
+#define BF_USBPHY_IP_RSVD0(v)           (((v) << 3) & 0xfff8)
+#define BP_USBPHY_IP_EN_USB_CLKS        2
+#define BM_USBPHY_IP_EN_USB_CLKS        0x4
+#define BF_USBPHY_IP_EN_USB_CLKS(v)     (((v) << 2) & 0x4)
+#define BP_USBPHY_IP_PLL_LOCKED         1
+#define BM_USBPHY_IP_PLL_LOCKED         0x2
+#define BF_USBPHY_IP_PLL_LOCKED(v)      (((v) << 1) & 0x2)
+#define BP_USBPHY_IP_PLL_POWER          0
+#define BM_USBPHY_IP_PLL_POWER          0x1
+#define BF_USBPHY_IP_PLL_POWER(v)       (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__IMX233__USBPHY__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-anatop.h b/firmware/target/arm/imx233/regs/regs-anatop.h
new file mode 100644
index 0000000000..760500cf16
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-anatop.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__ANATOP__H__
+#define __SELECT__ANATOP__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-anatop.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __SELECT__ANATOP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-apbh.h b/firmware/target/arm/imx233/regs/regs-apbh.h
new file mode 100644
index 0000000000..91d2976bdc
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-apbh.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__APBH__H__
+#define __SELECT__APBH__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-apbh.h"
+#define STMP3700_INCLUDE "stmp3700/regs-apbh.h"
+#define IMX233_INCLUDE "imx233/regs-apbh.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-apbx.h b/firmware/target/arm/imx233/regs/regs-apbx.h
new file mode 100644
index 0000000000..19923e5c5d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-apbx.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.1
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__APBX__H__
+#define __SELECT__APBX__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-apbx.h"
+#define STMP3700_INCLUDE "stmp3700/regs-apbx.h"
+#define IMX233_INCLUDE "imx233/regs-apbx.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-arc.h b/firmware/target/arm/imx233/regs/regs-arc.h
new file mode 100644
index 0000000000..d9050e398f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-arc.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__ARC__H__
+#define __SELECT__ARC__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-arc.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __SELECT__ARC__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-audioin.h b/firmware/target/arm/imx233/regs/regs-audioin.h
new file mode 100644
index 0000000000..c3dcfd13d8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-audioin.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.5.0 stmp3700:3.4.0 imx233:3.4.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__AUDIOIN__H__
+#define __SELECT__AUDIOIN__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-audioin.h"
+#define STMP3700_INCLUDE "stmp3700/regs-audioin.h"
+#define IMX233_INCLUDE "imx233/regs-audioin.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-audioout.h b/firmware/target/arm/imx233/regs/regs-audioout.h
new file mode 100644
index 0000000000..e9fc4adaa0
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-audioout.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__AUDIOOUT__H__
+#define __SELECT__AUDIOOUT__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-audioout.h"
+#define STMP3700_INCLUDE "stmp3700/regs-audioout.h"
+#define IMX233_INCLUDE "imx233/regs-audioout.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-bch.h b/firmware/target/arm/imx233/regs/regs-bch.h
new file mode 100644
index 0000000000..2bbd3d2eca
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-bch.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__BCH__H__
+#define __SELECT__BCH__H__
+#include "regs-macro.h"
+
+#define IMX233_INCLUDE "imx233/regs-bch.h"
+
+#include "regs-select.h"
+
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__BCH__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-brazoiocsr.h b/firmware/target/arm/imx233/regs/regs-brazoiocsr.h
new file mode 100644
index 0000000000..723e13e27b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-brazoiocsr.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__BRAZOIOCSR__H__
+#define __SELECT__BRAZOIOCSR__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-brazoiocsr.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __SELECT__BRAZOIOCSR__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-clkctrl.h b/firmware/target/arm/imx233/regs/regs-clkctrl.h
new file mode 100644
index 0000000000..dbb2765e73
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-clkctrl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__CLKCTRL__H__
+#define __SELECT__CLKCTRL__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-clkctrl.h"
+#define STMP3700_INCLUDE "stmp3700/regs-clkctrl.h"
+#define IMX233_INCLUDE "imx233/regs-clkctrl.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-dacdma.h b/firmware/target/arm/imx233/regs/regs-dacdma.h
new file mode 100644
index 0000000000..dc00b63b8a
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-dacdma.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__DACDMA__H__
+#define __SELECT__DACDMA__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-dacdma.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __SELECT__DACDMA__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-dcp.h b/firmware/target/arm/imx233/regs/regs-dcp.h
new file mode 100644
index 0000000000..7603751040
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-dcp.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__DCP__H__
+#define __SELECT__DCP__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-dcp.h"
+#define IMX233_INCLUDE "imx233/regs-dcp.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__DCP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-digctl.h b/firmware/target/arm/imx233/regs/regs-digctl.h
new file mode 100644
index 0000000000..900884a532
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-digctl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__DIGCTL__H__
+#define __SELECT__DIGCTL__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-digctl.h"
+#define STMP3700_INCLUDE "stmp3700/regs-digctl.h"
+#define IMX233_INCLUDE "imx233/regs-digctl.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-dram.h b/firmware/target/arm/imx233/regs/regs-dram.h
new file mode 100644
index 0000000000..4ebd0a7157
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-dram.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__DRAM__H__
+#define __SELECT__DRAM__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-dram.h"
+#define IMX233_INCLUDE "imx233/regs-dram.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__DRAM__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-dri.h b/firmware/target/arm/imx233/regs/regs-dri.h
new file mode 100644
index 0000000000..7d481c029c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-dri.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__DRI__H__
+#define __SELECT__DRI__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-dri.h"
+#define STMP3700_INCLUDE "stmp3700/regs-dri.h"
+#define IMX233_INCLUDE "imx233/regs-dri.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-ecc8.h b/firmware/target/arm/imx233/regs/regs-ecc8.h
new file mode 100644
index 0000000000..776d92e87d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-ecc8.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__ECC8__H__
+#define __SELECT__ECC8__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-ecc8.h"
+#define IMX233_INCLUDE "imx233/regs-ecc8.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__ECC8__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-emi.h b/firmware/target/arm/imx233/regs/regs-emi.h
new file mode 100644
index 0000000000..3f8a16ffbe
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-emi.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__EMI__H__
+#define __SELECT__EMI__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-emi.h"
+#define IMX233_INCLUDE "imx233/regs-emi.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__EMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-emictrl.h b/firmware/target/arm/imx233/regs/regs-emictrl.h
new file mode 100644
index 0000000000..f7fceb8710
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-emictrl.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__EMICTRL__H__
+#define __SELECT__EMICTRL__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-emictrl.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __SELECT__EMICTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-gpiomon.h b/firmware/target/arm/imx233/regs/regs-gpiomon.h
new file mode 100644
index 0000000000..bfd2c875e7
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-gpiomon.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__GPIOMON__H__
+#define __SELECT__GPIOMON__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-gpiomon.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+
+#endif /* __SELECT__GPIOMON__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-gpmi.h b/firmware/target/arm/imx233/regs/regs-gpmi.h
new file mode 100644
index 0000000000..7dba72387b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-gpmi.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__GPMI__H__
+#define __SELECT__GPMI__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-gpmi.h"
+#define STMP3700_INCLUDE "stmp3700/regs-gpmi.h"
+#define IMX233_INCLUDE "imx233/regs-gpmi.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-hwecc.h b/firmware/target/arm/imx233/regs/regs-hwecc.h
new file mode 100644
index 0000000000..16609045f8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-hwecc.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__HWECC__H__
+#define __SELECT__HWECC__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-hwecc.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __SELECT__HWECC__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-i2c.h b/firmware/target/arm/imx233/regs/regs-i2c.h
new file mode 100644
index 0000000000..28c6c04f95
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-i2c.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__I2C__H__
+#define __SELECT__I2C__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-i2c.h"
+#define STMP3700_INCLUDE "stmp3700/regs-i2c.h"
+#define IMX233_INCLUDE "imx233/regs-i2c.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-icoll.h b/firmware/target/arm/imx233/regs/regs-icoll.h
new file mode 100644
index 0000000000..c89f3d478f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-icoll.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__ICOLL__H__
+#define __SELECT__ICOLL__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-icoll.h"
+#define STMP3700_INCLUDE "stmp3700/regs-icoll.h"
+#define IMX233_INCLUDE "imx233/regs-icoll.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-ir.h b/firmware/target/arm/imx233/regs/regs-ir.h
new file mode 100644
index 0000000000..ebb51e4f1e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-ir.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__IR__H__
+#define __SELECT__IR__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-ir.h"
+#define STMP3700_INCLUDE "stmp3700/regs-ir.h"
+#define IMX233_INCLUDE "imx233/regs-ir.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-lcdif.h b/firmware/target/arm/imx233/regs/regs-lcdif.h
new file mode 100644
index 0000000000..79e6554d58
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-lcdif.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__LCDIF__H__
+#define __SELECT__LCDIF__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-lcdif.h"
+#define STMP3700_INCLUDE "stmp3700/regs-lcdif.h"
+#define IMX233_INCLUDE "imx233/regs-lcdif.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-lradc.h b/firmware/target/arm/imx233/regs/regs-lradc.h
new file mode 100644
index 0000000000..2b4701bb8c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-lradc.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__LRADC__H__
+#define __SELECT__LRADC__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-lradc.h"
+#define STMP3700_INCLUDE "stmp3700/regs-lradc.h"
+#define IMX233_INCLUDE "imx233/regs-lradc.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-macro.h b/firmware/target/arm/imx233/regs/regs-macro.h
new file mode 100644
index 0000000000..c53bc8609b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-macro.h
@@ -0,0 +1,496 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __REGS__MACRO__H__
+#define __REGS__MACRO__H__
+
+#ifndef REG_WRITE
+#define REG_WRITE(var,value) ((var) = (value))
+#endif /* REG_WRITE */
+
+#ifndef REG_READ
+#define REG_READ(var) (var)
+#endif /* REG_READ */
+
+#define BF_SET(reg, field)              REG_WRITE(HW_##reg##_SET, BM_##reg##_##field)
+#define BF_CLR(reg, field)              REG_WRITE(HW_##reg##_CLR, BM_##reg##_##field)
+#define BF_TOG(reg, field)              REG_WRITE(HW_##reg##_TOG, BM_##reg##_##field)
+
+#define BF_SETV(reg, field, v)          REG_WRITE(HW_##reg##_SET, BF_##reg##_##field(v))
+#define BF_CLRV(reg, field, v)          REG_WRITE(HW_##reg##_CLR, BF_##reg##_##field(v))
+#define BF_TOGV(reg, field, v)          REG_WRITE(HW_##reg##_TOG, BF_##reg##_##field(v))
+
+#define BF_RDX(val, reg, field)         ((REG_READ(val) & BM_##reg##_##field) >> BP_##reg##_##field)
+#define BF_RD(reg, field)               BF_RDX(REG_READ(HW_##reg), reg, field)
+#define BF_WRX(val, reg, field, v)      REG_WRITE(val, (REG_READ(val) & ~BM_##reg##_##field) | (((v) << BP_##reg##_##field) & BM_##reg##_##field))
+#define BF_WR(reg, field, v)            BF_WRX(HW_##reg, reg, field, v)
+#define BF_WR_V(reg, field, sy)         BF_WR(reg, field, BV_##reg##_##field##__##sy)
+#define BF_WR_VX(val, reg, field, sy)   BF_WRX(val, reg, field, BV_##reg##_##field##__##sy)
+
+#define BF_SETn(reg, n, field)          REG_WRITE(HW_##reg##_SET(n), BM_##reg##_##field)
+#define BF_CLRn(reg, n, field)          REG_WRITE(HW_##reg##_CLR(n), BM_##reg##_##field)
+#define BF_TOGn(reg, n, field)          REG_WRITE(HW_##reg##_TOG(n), BM_##reg##_##field)
+
+#define BF_SETVn(reg, n, field, v)      REG_WRITE(HW_##reg##_SET(n), BF_##reg##_##field(v))
+#define BF_CLRVn(reg, n, field, v)      REG_WRITE(HW_##reg##_CLR(n), BF_##reg##_##field(v))
+#define BF_TOGVn(reg, n, field, v)      REG_WRITE(HW_##reg##_TOG(n), BF_##reg##_##field(v))
+
+#define BF_RDn(reg, n, field)           BF_RDX(HW_##reg(n), reg, field)
+#define BF_WRn(reg, n, field, v)        BF_WRX(HW_##reg(n), reg, field, v)
+#define BF_WRn_V(reg, n, field, sy)     BF_WRn(reg, n, field, BV_##reg##_##field##__##sy)
+
+#define BM_OR1(reg, f01) \
+    (BM_##reg##_##f01)
+#define BM_OR2(reg, f01, f02) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02)
+#define BM_OR3(reg, f01, f02, f03) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03)
+#define BM_OR4(reg, f01, f02, f03, f04) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04)
+#define BM_OR5(reg, f01, f02, f03, f04, f05) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05)
+#define BM_OR6(reg, f01, f02, f03, f04, f05, f06) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06)
+#define BM_OR7(reg, f01, f02, f03, f04, f05, f06, f07) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07)
+#define BM_OR8(reg, f01, f02, f03, f04, f05, f06, f07, f08) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08)
+#define BM_OR9(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09)
+#define BM_OR10(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10)
+#define BM_OR11(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11)
+#define BM_OR12(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12)
+#define BM_OR13(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13)
+#define BM_OR14(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14)
+#define BM_OR15(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15)
+#define BM_OR16(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16)
+#define BM_OR17(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17)
+#define BM_OR18(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18)
+#define BM_OR19(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19)
+#define BM_OR20(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20)
+#define BM_OR21(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21)
+#define BM_OR22(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22)
+#define BM_OR23(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23)
+#define BM_OR24(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24)
+#define BM_OR25(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25)
+#define BM_OR26(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25 | BM_##reg##_##f26)
+#define BM_OR27(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27)
+#define BM_OR28(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28)
+#define BM_OR29(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
+     BM_##reg##_##f29)
+#define BM_OR30(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
+     BM_##reg##_##f29 | BM_##reg##_##f30)
+#define BM_OR31(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
+        f31) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
+     BM_##reg##_##f29 | BM_##reg##_##f30 | BM_##reg##_##f31)
+#define BM_OR32(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
+        f31, f32) \
+    (BM_##reg##_##f01 | BM_##reg##_##f02 | BM_##reg##_##f03 | BM_##reg##_##f04 | \
+     BM_##reg##_##f05 | BM_##reg##_##f06 | BM_##reg##_##f07 | BM_##reg##_##f08 | \
+     BM_##reg##_##f09 | BM_##reg##_##f10 | BM_##reg##_##f11 | BM_##reg##_##f12 | \
+     BM_##reg##_##f13 | BM_##reg##_##f14 | BM_##reg##_##f15 | BM_##reg##_##f16 | \
+     BM_##reg##_##f17 | BM_##reg##_##f18 | BM_##reg##_##f19 | BM_##reg##_##f20 | \
+     BM_##reg##_##f21 | BM_##reg##_##f22 | BM_##reg##_##f23 | BM_##reg##_##f24 | \
+     BM_##reg##_##f25 | BM_##reg##_##f26 | BM_##reg##_##f27 | BM_##reg##_##f28 | \
+     BM_##reg##_##f29 | BM_##reg##_##f30 | BM_##reg##_##f31 | BM_##reg##_##f32)
+
+#define BF_OR1(reg, f01) \
+    (BF_##reg##_##f01)
+#define BF_OR2(reg, f01, f02) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02)
+#define BF_OR3(reg, f01, f02, f03) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03)
+#define BF_OR4(reg, f01, f02, f03, f04) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04)
+#define BF_OR5(reg, f01, f02, f03, f04, f05) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05)
+#define BF_OR6(reg, f01, f02, f03, f04, f05, f06) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06)
+#define BF_OR7(reg, f01, f02, f03, f04, f05, f06, f07) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07)
+#define BF_OR8(reg, f01, f02, f03, f04, f05, f06, f07, f08) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08)
+#define BF_OR9(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09)
+#define BF_OR10(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10)
+#define BF_OR11(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11)
+#define BF_OR12(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12)
+#define BF_OR13(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13)
+#define BF_OR14(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14)
+#define BF_OR15(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15)
+#define BF_OR16(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16)
+#define BF_OR17(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17)
+#define BF_OR18(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18)
+#define BF_OR19(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19)
+#define BF_OR20(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20)
+#define BF_OR21(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21)
+#define BF_OR22(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22)
+#define BF_OR23(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23)
+#define BF_OR24(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24)
+#define BF_OR25(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25)
+#define BF_OR26(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25 | BF_##reg##_##f26)
+#define BF_OR27(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27)
+#define BF_OR28(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28)
+#define BF_OR29(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
+     BF_##reg##_##f29)
+#define BF_OR30(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
+     BF_##reg##_##f29 | BF_##reg##_##f30)
+#define BF_OR31(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
+        f31) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
+     BF_##reg##_##f29 | BF_##reg##_##f30 | BF_##reg##_##f31)
+#define BF_OR32(reg, f01, f02, f03, f04, f05, f06, f07, f08, f09, f10, \
+        f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, \
+        f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, \
+        f31, f32) \
+    (BF_##reg##_##f01 | BF_##reg##_##f02 | BF_##reg##_##f03 | BF_##reg##_##f04 | \
+     BF_##reg##_##f05 | BF_##reg##_##f06 | BF_##reg##_##f07 | BF_##reg##_##f08 | \
+     BF_##reg##_##f09 | BF_##reg##_##f10 | BF_##reg##_##f11 | BF_##reg##_##f12 | \
+     BF_##reg##_##f13 | BF_##reg##_##f14 | BF_##reg##_##f15 | BF_##reg##_##f16 | \
+     BF_##reg##_##f17 | BF_##reg##_##f18 | BF_##reg##_##f19 | BF_##reg##_##f20 | \
+     BF_##reg##_##f21 | BF_##reg##_##f22 | BF_##reg##_##f23 | BF_##reg##_##f24 | \
+     BF_##reg##_##f25 | BF_##reg##_##f26 | BF_##reg##_##f27 | BF_##reg##_##f28 | \
+     BF_##reg##_##f29 | BF_##reg##_##f30 | BF_##reg##_##f31 | BF_##reg##_##f32)
+
+#define REG_NARG(...) REG_NARGS_(__VA_ARGS__, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
+#define REG_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, _31, _32, N, ...) N
+
+#define REG_VARIADIC(macro, reg, ...) REG_VARIADIC_(macro, NARG(__VA_ARGS__), reg, __VA_ARGS__)
+#define REG_VARIADIC_(macro, cnt, reg, ...) REG_VARIADIC__(macro, cnt, reg, __VA_ARGS__)
+#define REG_VARIADIC__(macro, cnt, reg, ...) REG_VARIADIC___(macro##cnt, reg, ...)
+#define REG_VARIADIC___(macro, reg, ...) macro(reg, __VA_ARGS__)
+
+#define BM_OR(reg, ...) REG_VARIADIC(BM_OR, reg, __VA_ARGS__)
+#define BF_OR(reg, ...) REG_VARIADIC(BF_OR, reg, __VA_ARGS__)
+#endif /* __REGS__MACRO__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-memcpy.h b/firmware/target/arm/imx233/regs/regs-memcpy.h
new file mode 100644
index 0000000000..5abcf10e96
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-memcpy.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__MEMCPY__H__
+#define __SELECT__MEMCPY__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-memcpy.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+
+#endif /* __SELECT__MEMCPY__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-ocotp.h b/firmware/target/arm/imx233/regs/regs-ocotp.h
new file mode 100644
index 0000000000..6ddf92e05d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-ocotp.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__OCOTP__H__
+#define __SELECT__OCOTP__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-ocotp.h"
+#define IMX233_INCLUDE "imx233/regs-ocotp.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__OCOTP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-pinctrl.h b/firmware/target/arm/imx233/regs/regs-pinctrl.h
new file mode 100644
index 0000000000..c1736976f7
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-pinctrl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__PINCTRL__H__
+#define __SELECT__PINCTRL__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-pinctrl.h"
+#define STMP3700_INCLUDE "stmp3700/regs-pinctrl.h"
+#define IMX233_INCLUDE "imx233/regs-pinctrl.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-power.h b/firmware/target/arm/imx233/regs/regs-power.h
new file mode 100644
index 0000000000..ebf1e4796f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-power.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__POWER__H__
+#define __SELECT__POWER__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-power.h"
+#define STMP3700_INCLUDE "stmp3700/regs-power.h"
+#define IMX233_INCLUDE "imx233/regs-power.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-pwm.h b/firmware/target/arm/imx233/regs/regs-pwm.h
new file mode 100644
index 0000000000..ce782620be
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-pwm.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__PWM__H__
+#define __SELECT__PWM__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-pwm.h"
+#define STMP3700_INCLUDE "stmp3700/regs-pwm.h"
+#define IMX233_INCLUDE "imx233/regs-pwm.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-pxp.h b/firmware/target/arm/imx233/regs/regs-pxp.h
new file mode 100644
index 0000000000..5c5d4cffeb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-pxp.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__PXP__H__
+#define __SELECT__PXP__H__
+#include "regs-macro.h"
+
+#define IMX233_INCLUDE "imx233/regs-pxp.h"
+
+#include "regs-select.h"
+
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__PXP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-rtc.h b/firmware/target/arm/imx233/regs/regs-rtc.h
new file mode 100644
index 0000000000..c9acbdfbaa
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-rtc.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__RTC__H__
+#define __SELECT__RTC__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-rtc.h"
+#define STMP3700_INCLUDE "stmp3700/regs-rtc.h"
+#define IMX233_INCLUDE "imx233/regs-rtc.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-saif.h b/firmware/target/arm/imx233/regs/regs-saif.h
new file mode 100644
index 0000000000..234b6ed204
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-saif.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__SAIF__H__
+#define __SELECT__SAIF__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-saif.h"
+#define IMX233_INCLUDE "imx233/regs-saif.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__SAIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-spdif.h b/firmware/target/arm/imx233/regs/regs-spdif.h
new file mode 100644
index 0000000000..c5108a780b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-spdif.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__SPDIF__H__
+#define __SELECT__SPDIF__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-spdif.h"
+#define STMP3700_INCLUDE "stmp3700/regs-spdif.h"
+#define IMX233_INCLUDE "imx233/regs-spdif.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-ssp.h b/firmware/target/arm/imx233/regs/regs-ssp.h
new file mode 100644
index 0000000000..0c44e8cc3c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-ssp.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__SSP__H__
+#define __SELECT__SSP__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-ssp.h"
+#define STMP3700_INCLUDE "stmp3700/regs-ssp.h"
+#define IMX233_INCLUDE "imx233/regs-ssp.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-sydma.h b/firmware/target/arm/imx233/regs/regs-sydma.h
new file mode 100644
index 0000000000..e1480959bd
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-sydma.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__SYDMA__H__
+#define __SELECT__SYDMA__H__
+#include "regs-macro.h"
+
+#define IMX233_INCLUDE "imx233/regs-sydma.h"
+
+#include "regs-select.h"
+
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__SYDMA__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-timrot.h b/firmware/target/arm/imx233/regs/regs-timrot.h
new file mode 100644
index 0000000000..32edf163ea
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-timrot.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__TIMROT__H__
+#define __SELECT__TIMROT__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-timrot.h"
+#define STMP3700_INCLUDE "stmp3700/regs-timrot.h"
+#define IMX233_INCLUDE "imx233/regs-timrot.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-tvenc.h b/firmware/target/arm/imx233/regs/regs-tvenc.h
new file mode 100644
index 0000000000..5497c48766
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-tvenc.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__TVENC__H__
+#define __SELECT__TVENC__H__
+#include "regs-macro.h"
+
+#define IMX233_INCLUDE "imx233/regs-tvenc.h"
+
+#include "regs-select.h"
+
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__TVENC__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-uartapp.h b/firmware/target/arm/imx233/regs/regs-uartapp.h
new file mode 100644
index 0000000000..08f48348a4
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-uartapp.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__UARTAPP__H__
+#define __SELECT__UARTAPP__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-uartapp.h"
+#define STMP3700_INCLUDE "stmp3700/regs-uartapp.h"
+#define IMX233_INCLUDE "imx233/regs-uartapp.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-uartdbg.h b/firmware/target/arm/imx233/regs/regs-uartdbg.h
new file mode 100644
index 0000000000..b4080be163
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-uartdbg.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__UARTDBG__H__
+#define __SELECT__UARTDBG__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-uartdbg.h"
+#define STMP3700_INCLUDE "stmp3700/regs-uartdbg.h"
+#define IMX233_INCLUDE "imx233/regs-uartdbg.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-usbctrl.h b/firmware/target/arm/imx233/regs/regs-usbctrl.h
new file mode 100644
index 0000000000..c0552bb5eb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-usbctrl.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__USBCTRL__H__
+#define __SELECT__USBCTRL__H__
+#include "regs-macro.h"
+
+#define STMP3700_INCLUDE "stmp3700/regs-usbctrl.h"
+#define IMX233_INCLUDE "imx233/regs-usbctrl.h"
+
+#include "regs-select.h"
+
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__USBCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/regs-usbphy.h b/firmware/target/arm/imx233/regs/regs-usbphy.h
new file mode 100644
index 0000000000..08fc272a40
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/regs-usbphy.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0 stmp3700:3.2.0 imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __SELECT__USBPHY__H__
+#define __SELECT__USBPHY__H__
+#include "regs-macro.h"
+
+#define STMP3600_INCLUDE "stmp3600/regs-usbphy.h"
+#define STMP3700_INCLUDE "stmp3700/regs-usbphy.h"
+#define IMX233_INCLUDE "imx233/regs-usbphy.h"
+
+#include "regs-select.h"
+
+#undef STMP3600_INCLUDE
+#undef STMP3700_INCLUDE
+#undef IMX233_INCLUDE
+
+#endif /* __SELECT__USBPHY__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h b/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h
new file mode 100644
index 0000000000..d18835f044
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-anatop.h
@@ -0,0 +1,82 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__ANATOP__H__
+#define __HEADERGEN__STMP3600__ANATOP__H__
+
+#define REGS_ANATOP_BASE (0x8003c200)
+
+#define REGS_ANATOP_VERSION "2.3.0"
+
+/**
+ * Register: HW_ANATOP_PROBE_OUTPUT_SELECT
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_ANATOP_PROBE_OUTPUT_SELECT                   (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x0))
+#define HW_ANATOP_PROBE_OUTPUT_SELECT_SET               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x4))
+#define HW_ANATOP_PROBE_OUTPUT_SELECT_CLR               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0x8))
+#define HW_ANATOP_PROBE_OUTPUT_SELECT_TOG               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x0 + 0xc))
+#define BP_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT     0
+#define BM_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT     0xffffffff
+#define BF_ANATOP_PROBE_OUTPUT_SELECT_OUTPUT_SELECT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ANATOP_PROBE_INPUT_SELECT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_ANATOP_PROBE_INPUT_SELECT                    (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x0))
+#define HW_ANATOP_PROBE_INPUT_SELECT_SET                (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x4))
+#define HW_ANATOP_PROBE_INPUT_SELECT_CLR                (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0x8))
+#define HW_ANATOP_PROBE_INPUT_SELECT_TOG                (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x10 + 0xc))
+#define BP_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT       0
+#define BM_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT       0xffffffff
+#define BF_ANATOP_PROBE_INPUT_SELECT_INPUT_SELECT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ANATOP_PROBE_DATA
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_ANATOP_PROBE_DATA            (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x0))
+#define HW_ANATOP_PROBE_DATA_SET        (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x4))
+#define HW_ANATOP_PROBE_DATA_CLR        (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0x8))
+#define HW_ANATOP_PROBE_DATA_TOG        (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x20 + 0xc))
+#define BP_ANATOP_PROBE_DATA_DATA       0
+#define BM_ANATOP_PROBE_DATA_DATA       0xffffffff
+#define BF_ANATOP_PROBE_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ANATOP_PROBE_DIGTOP_SELECT
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_ANATOP_PROBE_DIGTOP_SELECT                   (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x0))
+#define HW_ANATOP_PROBE_DIGTOP_SELECT_SET               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x4))
+#define HW_ANATOP_PROBE_DIGTOP_SELECT_CLR               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0x8))
+#define HW_ANATOP_PROBE_DIGTOP_SELECT_TOG               (*(volatile unsigned long *)(REGS_ANATOP_BASE + 0x30 + 0xc))
+#define BP_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT     0
+#define BM_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT     0xffffffff
+#define BF_ANATOP_PROBE_DIGTOP_SELECT_DIGTOP_SELECT(v)  (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3600__ANATOP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h
new file mode 100644
index 0000000000..ab8d9e6deb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-apbh.h
@@ -0,0 +1,288 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.4.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__APBH__H__
+#define __HEADERGEN__STMP3600__APBH__H__
+
+#define REGS_APBH_BASE (0x80004000)
+
+#define REGS_APBH_VERSION "2.4.0"
+
+/**
+ * Register: HW_APBH_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_APBH_CTRL0                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0))
+#define HW_APBH_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4))
+#define HW_APBH_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8))
+#define HW_APBH_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc))
+#define BP_APBH_CTRL0_SFTRST                    31
+#define BM_APBH_CTRL0_SFTRST                    0x80000000
+#define BF_APBH_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
+#define BP_APBH_CTRL0_CLKGATE                   30
+#define BM_APBH_CTRL0_CLKGATE                   0x40000000
+#define BF_APBH_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
+#define BP_APBH_CTRL0_RESET_CHANNEL             16
+#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBH_CTRL0_RESET_CHANNEL__HWECC      0x1
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP        0x2
+#define BV_APBH_CTRL0_RESET_CHANNEL__SRC        0x4
+#define BV_APBH_CTRL0_RESET_CHANNEL__DEST       0x8
+#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x30
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x40
+#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
+#define BF_APBH_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HWECC    0x1
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP      0x2
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SRC      0x4
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__DEST     0x8
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x30
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x40
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) << 8) & 0xff00)
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v)      ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00)
+#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__HWECC     0x1
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP       0x2
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SRC       0x4
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__DEST      0x8
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x30
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x40
+#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
+#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_APBH_CTRL1                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0))
+#define HW_APBH_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4))
+#define HW_APBH_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8))
+#define HW_APBH_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc))
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    16
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff0000
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000)
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ       0
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ       0xff
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_DEVSEL
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_APBH_DEVSEL          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20))
+#define BP_APBH_DEVSEL_CH7      28
+#define BM_APBH_DEVSEL_CH7      0xf0000000
+#define BF_APBH_DEVSEL_CH7(v)   (((v) << 28) & 0xf0000000)
+#define BP_APBH_DEVSEL_CH6      24
+#define BM_APBH_DEVSEL_CH6      0xf000000
+#define BF_APBH_DEVSEL_CH6(v)   (((v) << 24) & 0xf000000)
+#define BP_APBH_DEVSEL_CH5      20
+#define BM_APBH_DEVSEL_CH5      0xf00000
+#define BF_APBH_DEVSEL_CH5(v)   (((v) << 20) & 0xf00000)
+#define BP_APBH_DEVSEL_CH4      16
+#define BM_APBH_DEVSEL_CH4      0xf0000
+#define BF_APBH_DEVSEL_CH4(v)   (((v) << 16) & 0xf0000)
+#define BP_APBH_DEVSEL_CH3      12
+#define BM_APBH_DEVSEL_CH3      0xf000
+#define BF_APBH_DEVSEL_CH3(v)   (((v) << 12) & 0xf000)
+#define BP_APBH_DEVSEL_CH2      8
+#define BM_APBH_DEVSEL_CH2      0xf00
+#define BF_APBH_DEVSEL_CH2(v)   (((v) << 8) & 0xf00)
+#define BP_APBH_DEVSEL_CH1      4
+#define BM_APBH_DEVSEL_CH1      0xf0
+#define BF_APBH_DEVSEL_CH1(v)   (((v) << 4) & 0xf0)
+#define BP_APBH_DEVSEL_CH0      0
+#define BM_APBH_DEVSEL_CH0      0xf
+#define BF_APBH_DEVSEL_CH0(v)   (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_APBH_CHn_DEBUG2
+ * Address: 0x90+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70))
+#define BP_APBH_CHn_DEBUG2_APB_BYTES    16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES    0xffff0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES    0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES    0xffff
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBH_CHn_CURCMDAR
+ * Address: 0x30+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x30+(n)*0x70))
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_BAR
+ * Address: 0x60+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70))
+#define BP_APBH_CHn_BAR_ADDRESS     0
+#define BM_APBH_CHn_BAR_ADDRESS     0xffffffff
+#define BF_APBH_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_CMD
+ * Address: 0x50+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70))
+#define BP_APBH_CHn_CMD_XFER_COUNT              16
+#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
+#define BP_APBH_CHn_CMD_CMDWORDS                12
+#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
+#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
+#define BP_APBH_CHn_CMD_SEMAPHORE               6
+#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
+#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
+#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
+#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) << 5) & 0x20)
+#define BP_APBH_CHn_CMD_NANDLOCK                4
+#define BM_APBH_CHn_CMD_NANDLOCK                0x10
+#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) << 4) & 0x10)
+#define BP_APBH_CHn_CMD_IRQONCMPLT              3
+#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
+#define BP_APBH_CHn_CMD_CHAIN                   2
+#define BM_APBH_CHn_CMD_CHAIN                   0x4
+#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
+#define BP_APBH_CHn_CMD_COMMAND                 0
+#define BM_APBH_CHn_CMD_COMMAND                 0x3
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
+#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
+#define BF_APBH_CHn_CMD_COMMAND_V(v)            ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3)
+
+/**
+ * Register: HW_APBH_CHn_NXTCMDAR
+ * Address: 0x40+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70))
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_SEMA
+ * Address: 0x70+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70))
+#define BP_APBH_CHn_SEMA_PHORE              16
+#define BM_APBH_CHn_SEMA_PHORE              0xff0000
+#define BF_APBH_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA     0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA     0xff
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_CHn_DEBUG1
+ * Address: 0x80+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70))
+#define BP_APBH_CHn_DEBUG1_REQ                          31
+#define BM_APBH_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBH_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
+#define BP_APBH_CHn_DEBUG1_BURST                        30
+#define BM_APBH_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBH_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
+#define BP_APBH_CHn_DEBUG1_KICK                         29
+#define BM_APBH_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBH_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
+#define BP_APBH_CHn_DEBUG1_END                          28
+#define BM_APBH_CHn_DEBUG1_END                          0x10000000
+#define BF_APBH_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
+#define BP_APBH_CHn_DEBUG1_RSVD2                        25
+#define BM_APBH_CHn_DEBUG1_RSVD2                        0xe000000
+#define BF_APBH_CHn_DEBUG1_RSVD2(v)                     (((v) << 25) & 0xe000000)
+#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
+#define BP_APBH_CHn_DEBUG1_RSVD1                        5
+#define BM_APBH_CHn_DEBUG1_RSVD1                        0xfffe0
+#define BF_APBH_CHn_DEBUG1_RSVD1(v)                     (((v) << 5) & 0xfffe0)
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
+
+#endif /* __HEADERGEN__STMP3600__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h
new file mode 100644
index 0000000000..fcb9949616
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-apbx.h
@@ -0,0 +1,276 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.4.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__APBX__H__
+#define __HEADERGEN__STMP3600__APBX__H__
+
+#define REGS_APBX_BASE (0x80024000)
+
+#define REGS_APBX_VERSION "2.4.0"
+
+/**
+ * Register: HW_APBX_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_APBX_CTRL0                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0))
+#define HW_APBX_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4))
+#define HW_APBX_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8))
+#define HW_APBX_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc))
+#define BP_APBX_CTRL0_SFTRST                    31
+#define BM_APBX_CTRL0_SFTRST                    0x80000000
+#define BF_APBX_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
+#define BP_APBX_CTRL0_CLKGATE                   30
+#define BM_APBX_CTRL0_CLKGATE                   0x40000000
+#define BF_APBX_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
+#define BP_APBX_CTRL0_RESET_CHANNEL             16
+#define BM_APBX_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN    0x1
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT   0x2
+#define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX   0x4
+#define BV_APBX_CTRL0_RESET_CHANNEL__I2C        0x8
+#define BV_APBX_CTRL0_RESET_CHANNEL__LCDIF      0x10
+#define BV_APBX_CTRL0_RESET_CHANNEL__DRI        0x20
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX    0x30
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX    0x30
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX    0x40
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX    0x40
+#define BF_APBX_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
+#define BF_APBX_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
+#define BP_APBX_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBX_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN   0x1
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT  0x2
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX  0x4
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C       0x8
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__LCDIF     0x10
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI       0x20
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX   0x30
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX   0x30
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX   0x40
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX   0x40
+#define BF_APBX_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
+#define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
+
+/**
+ * Register: HW_APBX_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_APBX_CTRL1                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0))
+#define HW_APBX_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4))
+#define HW_APBX_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8))
+#define HW_APBX_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc))
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    16
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff0000
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 16) & 0xff0000)
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ       0
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ       0xff
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBX_DEVSEL
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_APBX_DEVSEL                  (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20))
+#define BP_APBX_DEVSEL_CH7              28
+#define BM_APBX_DEVSEL_CH7              0xf0000000
+#define BV_APBX_DEVSEL_CH7__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH7(v)           (((v) << 28) & 0xf0000000)
+#define BF_APBX_DEVSEL_CH7_V(v)         ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000)
+#define BP_APBX_DEVSEL_CH6              24
+#define BM_APBX_DEVSEL_CH6              0xf000000
+#define BV_APBX_DEVSEL_CH6__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH6(v)           (((v) << 24) & 0xf000000)
+#define BF_APBX_DEVSEL_CH6_V(v)         ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000)
+#define BP_APBX_DEVSEL_CH5              20
+#define BM_APBX_DEVSEL_CH5              0xf00000
+#define BF_APBX_DEVSEL_CH5(v)           (((v) << 20) & 0xf00000)
+#define BP_APBX_DEVSEL_CH4              16
+#define BM_APBX_DEVSEL_CH4              0xf0000
+#define BF_APBX_DEVSEL_CH4(v)           (((v) << 16) & 0xf0000)
+#define BP_APBX_DEVSEL_CH3              12
+#define BM_APBX_DEVSEL_CH3              0xf000
+#define BF_APBX_DEVSEL_CH3(v)           (((v) << 12) & 0xf000)
+#define BP_APBX_DEVSEL_CH2              8
+#define BM_APBX_DEVSEL_CH2              0xf00
+#define BF_APBX_DEVSEL_CH2(v)           (((v) << 8) & 0xf00)
+#define BP_APBX_DEVSEL_CH1              4
+#define BM_APBX_DEVSEL_CH1              0xf0
+#define BF_APBX_DEVSEL_CH1(v)           (((v) << 4) & 0xf0)
+#define BP_APBX_DEVSEL_CH0              0
+#define BM_APBX_DEVSEL_CH0              0xf
+#define BF_APBX_DEVSEL_CH0(v)           (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_APBX_CHn_NXTCMDAR
+ * Address: 0x40+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70))
+#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_DEBUG2
+ * Address: 0x90+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70))
+#define BP_APBX_CHn_DEBUG2_APB_BYTES    16
+#define BM_APBX_CHn_DEBUG2_APB_BYTES    0xffff0000
+#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
+#define BP_APBX_CHn_DEBUG2_AHB_BYTES    0
+#define BM_APBX_CHn_DEBUG2_AHB_BYTES    0xffff
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBX_CHn_BAR
+ * Address: 0x60+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70))
+#define BP_APBX_CHn_BAR_ADDRESS     0
+#define BM_APBX_CHn_BAR_ADDRESS     0xffffffff
+#define BF_APBX_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_CMD
+ * Address: 0x50+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70))
+#define BP_APBX_CHn_CMD_XFER_COUNT              16
+#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
+#define BP_APBX_CHn_CMD_CMDWORDS                12
+#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
+#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
+#define BP_APBX_CHn_CMD_SEMAPHORE               6
+#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
+#define BP_APBX_CHn_CMD_IRQONCMPLT              3
+#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
+#define BP_APBX_CHn_CMD_CHAIN                   2
+#define BM_APBX_CHn_CMD_CHAIN                   0x4
+#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
+#define BP_APBX_CHn_CMD_COMMAND                 0
+#define BM_APBX_CHn_CMD_COMMAND                 0x3
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
+#define BF_APBX_CHn_CMD_COMMAND_V(v)            ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3)
+
+/**
+ * Register: HW_APBX_CHn_DEBUG1
+ * Address: 0x80+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70))
+#define BP_APBX_CHn_DEBUG1_REQ                          31
+#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
+#define BP_APBX_CHn_DEBUG1_BURST                        30
+#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
+#define BP_APBX_CHn_DEBUG1_KICK                         29
+#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
+#define BP_APBX_CHn_DEBUG1_END                          28
+#define BM_APBX_CHn_DEBUG1_END                          0x10000000
+#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
+#define BP_APBX_CHn_DEBUG1_RSVD2                        25
+#define BM_APBX_CHn_DEBUG1_RSVD2                        0xe000000
+#define BF_APBX_CHn_DEBUG1_RSVD2(v)                     (((v) << 25) & 0xe000000)
+#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
+#define BP_APBX_CHn_DEBUG1_RSVD1                        5
+#define BM_APBX_CHn_DEBUG1_RSVD1                        0xfffe0
+#define BF_APBX_CHn_DEBUG1_RSVD1(v)                     (((v) << 5) & 0xfffe0)
+#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
+
+/**
+ * Register: HW_APBX_CHn_SEMA
+ * Address: 0x70+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70))
+#define BP_APBX_CHn_SEMA_PHORE              16
+#define BM_APBX_CHn_SEMA_PHORE              0xff0000
+#define BF_APBX_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA     0
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA     0xff
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBX_CHn_CURCMDAR
+ * Address: 0x30+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x30+(n)*0x70))
+#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3600__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h
new file mode 100644
index 0000000000..af64d3a4ef
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-arc.h
@@ -0,0 +1,268 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__ARC__H__
+#define __HEADERGEN__STMP3600__ARC__H__
+
+#define REGS_ARC_BASE (0x80080000)
+
+#define REGS_ARC_VERSION "2.3.0"
+
+/**
+ * Register: HW_ARC_BASE
+ * Address: 0
+ * SCT: no
+*/
+#define HW_ARC_BASE (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0))
+
+/**
+ * Register: HW_ARC_ID
+ * Address: 0
+ * SCT: no
+*/
+#define HW_ARC_ID   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x0))
+
+/**
+ * Register: HW_ARC_HCSPARAMS
+ * Address: 0x104
+ * SCT: no
+*/
+#define HW_ARC_HCSPARAMS    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x104))
+
+/**
+ * Register: HW_ARC_USBCMD
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_ARC_USBCMD   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x140))
+
+/**
+ * Register: HW_ARC_USBSTS
+ * Address: 0x144
+ * SCT: no
+*/
+#define HW_ARC_USBSTS   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x144))
+
+/**
+ * Register: HW_ARC_USBINTR
+ * Address: 0x148
+ * SCT: no
+*/
+#define HW_ARC_USBINTR  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x148))
+
+/**
+ * Register: HW_ARC_FRINDEX
+ * Address: 0x14c
+ * SCT: no
+*/
+#define HW_ARC_FRINDEX  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x14c))
+
+/**
+ * Register: HW_ARC_DEVADDR
+ * Address: 0x154
+ * SCT: no
+*/
+#define HW_ARC_DEVADDR  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x154))
+
+/**
+ * Register: HW_ARC_ENDPTLISTADDR
+ * Address: 0x158
+ * SCT: no
+*/
+#define HW_ARC_ENDPTLISTADDR    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x158))
+
+/**
+ * Register: HW_ARC_PORTSC1
+ * Address: 0x184
+ * SCT: no
+*/
+#define HW_ARC_PORTSC1  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x184))
+
+/**
+ * Register: HW_ARC_OTGSC
+ * Address: 0x1a4
+ * SCT: no
+*/
+#define HW_ARC_OTGSC    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a4))
+
+/**
+ * Register: HW_ARC_USBMODE
+ * Address: 0x1a8
+ * SCT: no
+*/
+#define HW_ARC_USBMODE  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1a8))
+
+/**
+ * Register: HW_ARC_ENDPTSETUPSTAT
+ * Address: 0x1ac
+ * SCT: no
+*/
+#define HW_ARC_ENDPTSETUPSTAT   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ac))
+
+/**
+ * Register: HW_ARC_ENDPTPRIME
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_ARC_ENDPTPRIME   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b0))
+
+/**
+ * Register: HW_ARC_ENDPTFLUSH
+ * Address: 0x1b4
+ * SCT: no
+*/
+#define HW_ARC_ENDPTFLUSH   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b4))
+
+/**
+ * Register: HW_ARC_ENDPTSTATUS
+ * Address: 0x1b8
+ * SCT: no
+*/
+#define HW_ARC_ENDPTSTATUS  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1b8))
+
+/**
+ * Register: HW_ARC_ENDPTCOMPLETE
+ * Address: 0x1bc
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCOMPLETE    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1bc))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL0
+ * Address: 0x1c0
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL0   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL1
+ * Address: 0x1c4
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL1   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c4))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL2
+ * Address: 0x1c8
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL2   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c8))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL3
+ * Address: 0x1cc
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL3   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1cc))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL4
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL4   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d0))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL5
+ * Address: 0x1d4
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL5   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d4))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL6
+ * Address: 0x1d8
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL6   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1d8))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL7
+ * Address: 0x1dc
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL7   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1dc))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL8
+ * Address: 0x1e0
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL8   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e0))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL9
+ * Address: 0x1e4
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL9   (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e4))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL10
+ * Address: 0x1e8
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL10  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1e8))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL11
+ * Address: 0x1ec
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL11  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1ec))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL12
+ * Address: 0x1f0
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL12  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f0))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL13
+ * Address: 0x1f4
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL13  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f4))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL14
+ * Address: 0x1f8
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL14  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1f8))
+
+/**
+ * Register: HW_ARC_ENDPTCTRL15
+ * Address: 0x1fc
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRL15  (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1fc))
+
+/**
+ * Register: HW_ARC_ENDPTCTRLn
+ * Address: 0x1c0+n*0x4
+ * SCT: no
+*/
+#define HW_ARC_ENDPTCTRLn(n)    (*(volatile unsigned long *)(REGS_ARC_BASE + 0x1c0+(n)*0x4))
+
+#endif /* __HEADERGEN__STMP3600__ARC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h
new file mode 100644
index 0000000000..8b5fbac6ea
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-audioin.h
@@ -0,0 +1,281 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.5.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__AUDIOIN__H__
+#define __HEADERGEN__STMP3600__AUDIOIN__H__
+
+#define REGS_AUDIOIN_BASE (0x8004c000)
+
+#define REGS_AUDIOIN_VERSION "2.5.0"
+
+/**
+ * Register: HW_AUDIOIN_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_AUDIOIN_CTRL                         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0))
+#define HW_AUDIOIN_CTRL_SET                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4))
+#define HW_AUDIOIN_CTRL_CLR                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8))
+#define HW_AUDIOIN_CTRL_TOG                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc))
+#define BP_AUDIOIN_CTRL_SFTRST                  31
+#define BM_AUDIOIN_CTRL_SFTRST                  0x80000000
+#define BF_AUDIOIN_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_CTRL_CLKGATE                 30
+#define BM_AUDIOIN_CTRL_CLKGATE                 0x40000000
+#define BF_AUDIOIN_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT           16
+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT           0x1f0000
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)        (((v) << 16) & 0x1f0000)
+#define BP_AUDIOIN_CTRL_LR_SWAP                 10
+#define BM_AUDIOIN_CTRL_LR_SWAP                 0x400
+#define BF_AUDIOIN_CTRL_LR_SWAP(v)              (((v) << 10) & 0x400)
+#define BP_AUDIOIN_CTRL_EDGE_SYNC               9
+#define BM_AUDIOIN_CTRL_EDGE_SYNC               0x200
+#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)            (((v) << 9) & 0x200)
+#define BP_AUDIOIN_CTRL_INVERT_1BIT             8
+#define BM_AUDIOIN_CTRL_INVERT_1BIT             0x100
+#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)          (((v) << 8) & 0x100)
+#define BP_AUDIOIN_CTRL_OFFSET_ENABLE           7
+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE           0x80
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)        (((v) << 7) & 0x80)
+#define BP_AUDIOIN_CTRL_HPF_ENABLE              6
+#define BM_AUDIOIN_CTRL_HPF_ENABLE              0x40
+#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)           (((v) << 6) & 0x40)
+#define BP_AUDIOIN_CTRL_WORD_LENGTH             5
+#define BM_AUDIOIN_CTRL_WORD_LENGTH             0x20
+#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)          (((v) << 5) & 0x20)
+#define BP_AUDIOIN_CTRL_LOOPBACK                4
+#define BM_AUDIOIN_CTRL_LOOPBACK                0x10
+#define BF_AUDIOIN_CTRL_LOOPBACK(v)             (((v) << 4) & 0x10)
+#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      3
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x8
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)   (((v) << 3) & 0x8)
+#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       2
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x4
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)    (((v) << 2) & 0x4)
+#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       1
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x2
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOIN_CTRL_RUN                     0
+#define BM_AUDIOIN_CTRL_RUN                     0x1
+#define BF_AUDIOIN_CTRL_RUN(v)                  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOIN_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_AUDIOIN_STAT                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10))
+#define BP_AUDIOIN_STAT_ADC_PRESENT     31
+#define BM_AUDIOIN_STAT_ADC_PRESENT     0x80000000
+#define BF_AUDIOIN_STAT_ADC_PRESENT(v)  (((v) << 31) & 0x80000000)
+
+/**
+ * Register: HW_AUDIOIN_ADCSRR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCSRR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0))
+#define HW_AUDIOIN_ADCSRR_SET                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4))
+#define HW_AUDIOIN_ADCSRR_CLR                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8))
+#define HW_AUDIOIN_ADCSRR_TOG                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc))
+#define BP_AUDIOIN_ADCSRR_OSR                   31
+#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
+#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
+#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
+#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) << 31) & 0x80000000)
+#define BF_AUDIOIN_ADCSRR_OSR_V(v)              ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000)
+#define BP_AUDIOIN_ADCSRR_BASEMULT              28
+#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
+#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) << 28) & 0x70000000)
+#define BF_AUDIOIN_ADCSRR_BASEMULT_V(v)         ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000)
+#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
+#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) << 24) & 0x7000000)
+#define BP_AUDIOIN_ADCSRR_SRC_INT               16
+#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
+#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) << 16) & 0x1f0000)
+#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
+#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_AUDIOIN_ADCVOLUME
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCVOLUME                        (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0))
+#define HW_AUDIOIN_ADCVOLUME_SET                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4))
+#define HW_AUDIOIN_ADCVOLUME_CLR                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8))
+#define HW_AUDIOIN_ADCVOLUME_TOG                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc))
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     28
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     0x10000000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)  (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                 25
+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                 0x2000000
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)              (((v) << 25) & 0x2000000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT            16
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT            0xff0000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)         (((v) << 16) & 0xff0000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    12
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    0x1000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0xff
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)        (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOIN_ADCDEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCDEBUG                                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0))
+#define HW_AUDIOIN_ADCDEBUG_SET                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4))
+#define HW_AUDIOIN_ADCDEBUG_CLR                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8))
+#define HW_AUDIOIN_ADCDEBUG_TOG                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc))
+#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       31
+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       0x80000000
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                    (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    3
+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    0x8
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8)
+#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           2
+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           0x4
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)        (((v) << 2) & 0x4)
+#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                            1
+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                            0x2
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                         (((v) << 1) & 0x2)
+#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0
+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0x1
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOIN_ADCVOL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCVOL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0))
+#define HW_AUDIOIN_ADCVOL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4))
+#define HW_AUDIOIN_ADCVOL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8))
+#define HW_AUDIOIN_ADCVOL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc))
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT       28
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT       0x30000000
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)    (((v) << 28) & 0x30000000)
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT      24
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT      0x3000000
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)   (((v) << 24) & 0x3000000)
+#define BP_AUDIOIN_ADCVOL_MUTE              8
+#define BM_AUDIOIN_ADCVOL_MUTE              0x100
+#define BF_AUDIOIN_ADCVOL_MUTE(v)           (((v) << 8) & 0x100)
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT         4
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT         0xf0
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)      (((v) << 4) & 0xf0)
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT        0
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT        0xf
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_AUDIOIN_MICLINE
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_AUDIOIN_MICLINE                          (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0))
+#define HW_AUDIOIN_MICLINE_SET                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4))
+#define HW_AUDIOIN_MICLINE_CLR                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8))
+#define HW_AUDIOIN_MICLINE_TOG                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc))
+#define BP_AUDIOIN_MICLINE_ATTEN_LINE               30
+#define BM_AUDIOIN_MICLINE_ATTEN_LINE               0x40000000
+#define BF_AUDIOIN_MICLINE_ATTEN_LINE(v)            (((v) << 30) & 0x40000000)
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1             29
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1             0x20000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)          (((v) << 29) & 0x20000000)
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2             28
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2             0x10000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)          (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_MICLINE_MIC_SELECT               24
+#define BM_AUDIOIN_MICLINE_MIC_SELECT               0x1000000
+#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)            (((v) << 24) & 0x1000000)
+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR             20
+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR             0x300000
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off        0x0
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm      0x1
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm      0x2
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm      0x3
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)          (((v) << 20) & 0x300000)
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)        ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000)
+#define BP_AUDIOIN_MICLINE_MIC_BIAS                 16
+#define BM_AUDIOIN_MICLINE_MIC_BIAS                 0x70000
+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)              (((v) << 16) & 0x70000)
+#define BP_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP       8
+#define BM_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP       0x100
+#define BF_AUDIOIN_MICLINE_FORCE_MICAMP_PWRUP(v)    (((v) << 8) & 0x100)
+#define BP_AUDIOIN_MICLINE_MIC_GAIN                 0
+#define BM_AUDIOIN_MICLINE_MIC_GAIN                 0x3
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB            0x0
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB           0x1
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB           0x2
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB           0x3
+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)              (((v) << 0) & 0x3)
+#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v)            ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3)
+
+/**
+ * Register: HW_AUDIOIN_ANACLKCTRL
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ANACLKCTRL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0))
+#define HW_AUDIOIN_ANACLKCTRL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4))
+#define HW_AUDIOIN_ANACLKCTRL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8))
+#define HW_AUDIOIN_ANACLKCTRL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc))
+#define BP_AUDIOIN_ANACLKCTRL_CLKGATE           31
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE           0x80000000
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)        (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_ANACLKCTRL_DITHER_ENABLE     6
+#define BM_AUDIOIN_ANACLKCTRL_DITHER_ENABLE     0x40
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_ENABLE(v)  (((v) << 6) & 0x40)
+#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER       5
+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER       0x20
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)    (((v) << 5) & 0x20)
+#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     4
+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     0x10
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)  (((v) << 4) & 0x10)
+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV            0
+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV            0x7
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)         (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOIN_DATA
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_AUDIOIN_DATA         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80))
+#define BP_AUDIOIN_DATA_HIGH    16
+#define BM_AUDIOIN_DATA_HIGH    0xffff0000
+#define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000)
+#define BP_AUDIOIN_DATA_LOW     0
+#define BM_AUDIOIN_DATA_LOW     0xffff
+#define BF_AUDIOIN_DATA_LOW(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3600__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h
new file mode 100644
index 0000000000..20e639c6dd
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-audioout.h
@@ -0,0 +1,473 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__AUDIOOUT__H__
+#define __HEADERGEN__STMP3600__AUDIOOUT__H__
+
+#define REGS_AUDIOOUT_BASE (0x80048000)
+
+#define REGS_AUDIOOUT_VERSION "2.3.0"
+
+/**
+ * Register: HW_AUDIOOUT_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_CTRL                        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0))
+#define HW_AUDIOOUT_CTRL_SET                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4))
+#define HW_AUDIOOUT_CTRL_CLR                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8))
+#define HW_AUDIOOUT_CTRL_TOG                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc))
+#define BP_AUDIOOUT_CTRL_SFTRST                 31
+#define BM_AUDIOOUT_CTRL_SFTRST                 0x80000000
+#define BF_AUDIOOUT_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_CTRL_CLKGATE                30
+#define BM_AUDIOOUT_CTRL_CLKGATE                0x40000000
+#define BF_AUDIOOUT_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT          16
+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT          0x1f0000
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
+#define BP_AUDIOOUT_CTRL_LR_SWAP                14
+#define BM_AUDIOOUT_CTRL_LR_SWAP                0x4000
+#define BF_AUDIOOUT_CTRL_LR_SWAP(v)             (((v) << 14) & 0x4000)
+#define BP_AUDIOOUT_CTRL_EDGE_SYNC              13
+#define BM_AUDIOOUT_CTRL_EDGE_SYNC              0x2000
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)           (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_CTRL_INVERT_1BIT            12
+#define BM_AUDIOOUT_CTRL_INVERT_1BIT            0x1000
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)         (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT            8
+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT            0x300
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)         (((v) << 8) & 0x300)
+#define BP_AUDIOOUT_CTRL_WORD_LENGTH            6
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH            0x40
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)         (((v) << 6) & 0x40)
+#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        5
+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        0x20
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)     (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_CTRL_LOOPBACK               4
+#define BM_AUDIOOUT_CTRL_LOOPBACK               0x10
+#define BF_AUDIOOUT_CTRL_LOOPBACK(v)            (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     3
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x8
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)  (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      2
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x4
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)   (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      1
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x2
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_CTRL_RUN                    0
+#define BM_AUDIOOUT_CTRL_RUN                    0x1
+#define BF_AUDIOOUT_CTRL_RUN(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_AUDIOOUT_STAT                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10))
+#define BP_AUDIOOUT_STAT_DAC_PRESENT    31
+#define BM_AUDIOOUT_STAT_DAC_PRESENT    0x80000000
+#define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000)
+
+/**
+ * Register: HW_AUDIOOUT_DACSRR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACSRR                          (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0))
+#define HW_AUDIOOUT_DACSRR_SET                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4))
+#define HW_AUDIOOUT_DACSRR_CLR                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8))
+#define HW_AUDIOOUT_DACSRR_TOG                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc))
+#define BP_AUDIOOUT_DACSRR_OSR                      31
+#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
+#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
+#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
+#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) << 31) & 0x80000000)
+#define BF_AUDIOOUT_DACSRR_OSR_V(v)                 ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000)
+#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
+#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
+#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) << 28) & 0x70000000)
+#define BF_AUDIOOUT_DACSRR_BASEMULT_V(v)            ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000)
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) << 24) & 0x7000000)
+#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
+#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
+#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) << 16) & 0x1f0000)
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_AUDIOOUT_DACVOLUME
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACVOLUME                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0))
+#define HW_AUDIOOUT_DACVOLUME_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4))
+#define HW_AUDIOOUT_DACVOLUME_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8))
+#define HW_AUDIOOUT_DACVOLUME_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc))
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) << 16) & 0xff0000)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) << 8) & 0x100)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOOUT_DACDEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACDEBUG                                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0))
+#define HW_AUDIOOUT_DACDEBUG_SET                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4))
+#define HW_AUDIOOUT_DACDEBUG_CLR                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8))
+#define HW_AUDIOOUT_DACDEBUG_TOG                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc))
+#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  31
+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  0x80000000
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)               (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       5
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       0x20
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)    (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       4
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       0x10
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)    (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      3
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      0x8
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)   (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      2
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      0x4
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)   (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                       1
+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                       0x2
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0
+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0x1
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_HPVOL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_HPVOL               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0))
+#define HW_AUDIOOUT_HPVOL_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4))
+#define HW_AUDIOOUT_HPVOL_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8))
+#define HW_AUDIOOUT_HPVOL_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc))
+#define BP_AUDIOOUT_HPVOL_SELECT        24
+#define BM_AUDIOOUT_HPVOL_SELECT        0x3000000
+#define BF_AUDIOOUT_HPVOL_SELECT(v)     (((v) << 24) & 0x3000000)
+#define BP_AUDIOOUT_HPVOL_MUTE          16
+#define BM_AUDIOOUT_HPVOL_MUTE          0x10000
+#define BF_AUDIOOUT_HPVOL_MUTE(v)       (((v) << 16) & 0x10000)
+#define BP_AUDIOOUT_HPVOL_VOL_LEFT      8
+#define BM_AUDIOOUT_HPVOL_VOL_LEFT      0x1f00
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)   (((v) << 8) & 0x1f00)
+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT     0
+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT     0x1f
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)  (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_AUDIOOUT_SPKRVOL
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_SPKRVOL         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x0))
+#define HW_AUDIOOUT_SPKRVOL_SET     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x4))
+#define HW_AUDIOOUT_SPKRVOL_CLR     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0x8))
+#define HW_AUDIOOUT_SPKRVOL_TOG     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60 + 0xc))
+#define BP_AUDIOOUT_SPKRVOL_MUTE    16
+#define BM_AUDIOOUT_SPKRVOL_MUTE    0x10000
+#define BF_AUDIOOUT_SPKRVOL_MUTE(v) (((v) << 16) & 0x10000)
+#define BP_AUDIOOUT_SPKRVOL_VOL     0
+#define BM_AUDIOOUT_SPKRVOL_VOL     0xf
+#define BF_AUDIOOUT_SPKRVOL_VOL(v)  (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_AUDIOOUT_PWRDN
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_PWRDN               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0))
+#define HW_AUDIOOUT_PWRDN_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4))
+#define HW_AUDIOOUT_PWRDN_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8))
+#define HW_AUDIOOUT_PWRDN_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc))
+#define BP_AUDIOOUT_PWRDN_SPEAKER       24
+#define BM_AUDIOOUT_PWRDN_SPEAKER       0x1000000
+#define BF_AUDIOOUT_PWRDN_SPEAKER(v)    (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_PWRDN_SELFBIAS      20
+#define BM_AUDIOOUT_PWRDN_SELFBIAS      0x100000
+#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)   (((v) << 20) & 0x100000)
+#define BP_AUDIOOUT_PWRDN_RIGHT_ADC     16
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x10000
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)  (((v) << 16) & 0x10000)
+#define BP_AUDIOOUT_PWRDN_DAC           12
+#define BM_AUDIOOUT_PWRDN_DAC           0x1000
+#define BF_AUDIOOUT_PWRDN_DAC(v)        (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_PWRDN_ADC           8
+#define BM_AUDIOOUT_PWRDN_ADC           0x100
+#define BF_AUDIOOUT_PWRDN_ADC(v)        (((v) << 8) & 0x100)
+#define BP_AUDIOOUT_PWRDN_CAPLESS       4
+#define BM_AUDIOOUT_PWRDN_CAPLESS       0x10
+#define BF_AUDIOOUT_PWRDN_CAPLESS(v)    (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
+#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x1
+#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_REFCTRL
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_REFCTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0))
+#define HW_AUDIOOUT_REFCTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4))
+#define HW_AUDIOOUT_REFCTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8))
+#define HW_AUDIOOUT_REFCTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc))
+#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       24
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x1000000
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)    (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ             20
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ             0x700000
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)          (((v) << 20) & 0x700000)
+#define BP_AUDIOOUT_REFCTRL_LOW_PWR             19
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR             0x80000
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)          (((v) << 19) & 0x80000)
+#define BP_AUDIOOUT_REFCTRL_LW_REF              18
+#define BM_AUDIOOUT_REFCTRL_LW_REF              0x40000
+#define BF_AUDIOOUT_REFCTRL_LW_REF(v)           (((v) << 18) & 0x40000)
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL           16
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL           0x30000
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)        (((v) << 16) & 0x30000)
+#define BP_AUDIOOUT_REFCTRL_ADJ_ADC             13
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC             0x2000
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)          (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_REFCTRL_ADJ_VAG             12
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG             0x1000
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)          (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL          8
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL          0xf00
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)       (((v) << 8) & 0xf00)
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL             4
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL             0xf0
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)          (((v) << 4) & 0xf0)
+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ             0
+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ             0x7
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)          (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOOUT_ANACTRL
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_ANACTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0))
+#define HW_AUDIOOUT_ANACTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4))
+#define HW_AUDIOOUT_ANACTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8))
+#define HW_AUDIOOUT_ANACTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc))
+#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) << 20) & 0x300000)
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) << 17) & 0x60000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) << 12) & 0x7000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) << 8) & 0x700)
+#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_ANACTRL_EN_SPKR_ZCD         2
+#define BM_AUDIOOUT_ANACTRL_EN_SPKR_ZCD         0x4
+#define BF_AUDIOOUT_ANACTRL_EN_SPKR_ZCD(v)      (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_ANACTRL_ZCD_SELECTADC       1
+#define BM_AUDIOOUT_ANACTRL_ZCD_SELECTADC       0x2
+#define BF_AUDIOOUT_ANACTRL_ZCD_SELECTADC(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_ANACTRL_EN_ZCD              0
+#define BM_AUDIOOUT_ANACTRL_EN_ZCD              0x1
+#define BF_AUDIOOUT_ANACTRL_EN_ZCD(v)           (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_TEST
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_TEST                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0))
+#define HW_AUDIOOUT_TEST_SET                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4))
+#define HW_AUDIOOUT_TEST_CLR                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8))
+#define HW_AUDIOOUT_TEST_TOG                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc))
+#define BP_AUDIOOUT_TEST_HP_ANTIPOP         28
+#define BM_AUDIOOUT_TEST_HP_ANTIPOP         0x70000000
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)      (((v) << 28) & 0x70000000)
+#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP      26
+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP      0x4000000
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)   (((v) << 26) & 0x4000000)
+#define BP_AUDIOOUT_TEST_TM_SPEAKER         25
+#define BM_AUDIOOUT_TEST_TM_SPEAKER         0x2000000
+#define BF_AUDIOOUT_TEST_TM_SPEAKER(v)      (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_TEST_TM_HPCOMMON        24
+#define BM_AUDIOOUT_TEST_TM_HPCOMMON        0x1000000
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)     (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ          22
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ          0xc00000
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)       (((v) << 22) & 0xc00000)
+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ        20
+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ        0x300000
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)     (((v) << 20) & 0x300000)
+#define BP_AUDIOOUT_TEST_SPKR_I1_ADJ        18
+#define BM_AUDIOOUT_TEST_SPKR_I1_ADJ        0xc0000
+#define BF_AUDIOOUT_TEST_SPKR_I1_ADJ(v)     (((v) << 18) & 0xc0000)
+#define BP_AUDIOOUT_TEST_SPKR_IALL_ADJ      16
+#define BM_AUDIOOUT_TEST_SPKR_IALL_ADJ      0x30000
+#define BF_AUDIOOUT_TEST_SPKR_IALL_ADJ(v)   (((v) << 16) & 0x30000)
+#define BP_AUDIOOUT_TEST_VAG_CLASSA         13
+#define BM_AUDIOOUT_TEST_VAG_CLASSA         0x2000
+#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)      (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I       12
+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I       0x1000
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)    (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_TEST_HP_CHOPCLK         8
+#define BM_AUDIOOUT_TEST_HP_CHOPCLK         0x300
+#define BF_AUDIOOUT_TEST_HP_CHOPCLK(v)      (((v) << 8) & 0x300)
+#define BP_AUDIOOUT_TEST_DAC_CHOPCLK        4
+#define BM_AUDIOOUT_TEST_DAC_CHOPCLK        0x30
+#define BF_AUDIOOUT_TEST_DAC_CHOPCLK(v)     (((v) << 4) & 0x30)
+#define BP_AUDIOOUT_TEST_DAC_CLASSA         2
+#define BM_AUDIOOUT_TEST_DAC_CLASSA         0x4
+#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)      (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I       1
+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I       0x2
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ        0
+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ        0x1
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_BISTCTRL
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_BISTCTRL            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0))
+#define HW_AUDIOOUT_BISTCTRL_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4))
+#define HW_AUDIOOUT_BISTCTRL_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8))
+#define HW_AUDIOOUT_BISTCTRL_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc))
+#define BP_AUDIOOUT_BISTCTRL_FAIL       3
+#define BM_AUDIOOUT_BISTCTRL_FAIL       0x8
+#define BF_AUDIOOUT_BISTCTRL_FAIL(v)    (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_BISTCTRL_PASS       2
+#define BM_AUDIOOUT_BISTCTRL_PASS       0x4
+#define BF_AUDIOOUT_BISTCTRL_PASS(v)    (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_BISTCTRL_DONE       1
+#define BM_AUDIOOUT_BISTCTRL_DONE       0x2
+#define BF_AUDIOOUT_BISTCTRL_DONE(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_BISTCTRL_START      0
+#define BM_AUDIOOUT_BISTCTRL_START      0x1
+#define BF_AUDIOOUT_BISTCTRL_START(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_BISTSTAT0
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_AUDIOOUT_BISTSTAT0           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0))
+#define BP_AUDIOOUT_BISTSTAT0_DATA      0
+#define BM_AUDIOOUT_BISTSTAT0_DATA      0xffffff
+#define BF_AUDIOOUT_BISTSTAT0_DATA(v)   (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_AUDIOOUT_BISTSTAT1
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_AUDIOOUT_BISTSTAT1           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0))
+#define BP_AUDIOOUT_BISTSTAT1_STATE     24
+#define BM_AUDIOOUT_BISTSTAT1_STATE     0x1f000000
+#define BF_AUDIOOUT_BISTSTAT1_STATE(v)  (((v) << 24) & 0x1f000000)
+#define BP_AUDIOOUT_BISTSTAT1_ADDR      0
+#define BM_AUDIOOUT_BISTSTAT1_ADDR      0xff
+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOOUT_ANACLKCTRL
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_ANACLKCTRL                  (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0))
+#define HW_AUDIOOUT_ANACLKCTRL_SET              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4))
+#define HW_AUDIOOUT_ANACLKCTRL_CLR              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8))
+#define HW_AUDIOOUT_ANACLKCTRL_TOG              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc))
+#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE          31
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE          0x80000000
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    4
+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    0x10
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV           0
+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV           0x7
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)        (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOOUT_DATA
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DATA            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0))
+#define HW_AUDIOOUT_DATA_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4))
+#define HW_AUDIOOUT_DATA_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8))
+#define HW_AUDIOOUT_DATA_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc))
+#define BP_AUDIOOUT_DATA_HIGH       16
+#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
+#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) << 16) & 0xffff0000)
+#define BP_AUDIOOUT_DATA_LOW        0
+#define BM_AUDIOOUT_DATA_LOW        0xffff
+#define BF_AUDIOOUT_DATA_LOW(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3600__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h b/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h
new file mode 100644
index 0000000000..903cf09878
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-brazoiocsr.h
@@ -0,0 +1,30 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__BRAZOIOCSR__H__
+#define __HEADERGEN__STMP3600__BRAZOIOCSR__H__
+
+#define REGS_BRAZOIOCSR_BASE (0x80038000)
+
+#define REGS_BRAZOIOCSR_VERSION "2.3.0"
+
+#endif /* __HEADERGEN__STMP3600__BRAZOIOCSR__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h
new file mode 100644
index 0000000000..218298b69d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h
@@ -0,0 +1,344 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.4.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__CLKCTRL__H__
+#define __HEADERGEN__STMP3600__CLKCTRL__H__
+
+#define REGS_CLKCTRL_BASE (0x80040000)
+
+#define REGS_CLKCTRL_VERSION "2.4.0"
+
+/**
+ * Register: HW_CLKCTRL_PLLCTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_CLKCTRL_PLLCTRL0                                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0))
+#define HW_CLKCTRL_PLLCTRL0_SET                                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4))
+#define HW_CLKCTRL_PLLCTRL0_CLR                                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8))
+#define HW_CLKCTRL_PLLCTRL0_TOG                                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc))
+#define BP_CLKCTRL_PLLCTRL0_PLLVCOKSTART                        30
+#define BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART                        0x40000000
+#define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v)                     (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR                       29
+#define BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR                       0x20000000
+#define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v)                    (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_PLLCTRL0_PLLCPDBLIP                          28
+#define BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP                          0x10000000
+#define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v)                       (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_PLLCTRL0_PLLCPNSEL                           24
+#define BM_CLKCTRL_PLLCTRL0_PLLCPNSEL                           0x7000000
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__DEFAULT                  0x0
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_15                 0x2
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_075                0x3
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_05                 0x4
+#define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_04                 0x7
+#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(v)                        (((v) << 24) & 0x7000000)
+#define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(v)                      ((BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__##v << 24) & 0x7000000)
+#define BP_CLKCTRL_PLLCTRL0_PLLV2ISEL                           20
+#define BM_CLKCTRL_PLLCTRL0_PLLV2ISEL                           0x300000
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__NORMAL                   0x0
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWER                    0x1
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWEST                   0x2
+#define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__HIGHEST                  0x3
+#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(v)                        (((v) << 20) & 0x300000)
+#define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(v)                      ((BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__##v << 20) & 0x300000)
+#define BP_CLKCTRL_PLLCTRL0_FORCE_FREQ                          19
+#define BM_CLKCTRL_PLLCTRL0_FORCE_FREQ                          0x80000
+#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__FORCE_SAME_FREQ         0x1
+#define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__HONOR_SAME_FREQ_RULE    0x0
+#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(v)                       (((v) << 19) & 0x80000)
+#define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(v)                     ((BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__##v << 19) & 0x80000)
+#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS                         18
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS                         0x40000
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)                      (((v) << 18) & 0x40000)
+#define BP_CLKCTRL_PLLCTRL0_BYPASS                              17
+#define BM_CLKCTRL_PLLCTRL0_BYPASS                              0x20000
+#define BF_CLKCTRL_PLLCTRL0_BYPASS(v)                           (((v) << 17) & 0x20000)
+#define BP_CLKCTRL_PLLCTRL0_POWER                               16
+#define BM_CLKCTRL_PLLCTRL0_POWER                               0x10000
+#define BF_CLKCTRL_PLLCTRL0_POWER(v)                            (((v) << 16) & 0x10000)
+#define BP_CLKCTRL_PLLCTRL0_FREQ                                0
+#define BM_CLKCTRL_PLLCTRL0_FREQ                                0x1ff
+#define BF_CLKCTRL_PLLCTRL0_FREQ(v)                             (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_CLKCTRL_PLLCTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_CLKCTRL_PLLCTRL1                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x0))
+#define HW_CLKCTRL_PLLCTRL1_SET             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x4))
+#define HW_CLKCTRL_PLLCTRL1_CLR             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x8))
+#define HW_CLKCTRL_PLLCTRL1_TOG             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0xc))
+#define BP_CLKCTRL_PLLCTRL1_LOCK            31
+#define BM_CLKCTRL_PLLCTRL1_LOCK            0x80000000
+#define BF_CLKCTRL_PLLCTRL1_LOCK(v)         (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK      30
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK      0x40000000
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)   (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT      0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT      0xffff
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_CLKCTRL_CPU
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_CLKCTRL_CPU                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20))
+#define BP_CLKCTRL_CPU_WAIT_PLL_LOCK        30
+#define BM_CLKCTRL_CPU_WAIT_PLL_LOCK        0x40000000
+#define BF_CLKCTRL_CPU_WAIT_PLL_LOCK(v)     (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_CPU_BUSY                 29
+#define BM_CLKCTRL_CPU_BUSY                 0x20000000
+#define BF_CLKCTRL_CPU_BUSY(v)              (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_CPU_INTERRUPT_WAIT       12
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT       0x1000
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)    (((v) << 12) & 0x1000)
+#define BP_CLKCTRL_CPU_DIV                  0
+#define BM_CLKCTRL_CPU_DIV                  0x3ff
+#define BF_CLKCTRL_CPU_DIV(v)               (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_HBUS
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_CLKCTRL_HBUS                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30))
+#define BP_CLKCTRL_HBUS_WAIT_PLL_LOCK           30
+#define BM_CLKCTRL_HBUS_WAIT_PLL_LOCK           0x40000000
+#define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(v)        (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_HBUS_BUSY                    29
+#define BM_CLKCTRL_HBUS_BUSY                    0x20000000
+#define BF_CLKCTRL_HBUS_BUSY(v)                 (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_HBUS_EMI_BUSY_FAST           27
+#define BM_CLKCTRL_HBUS_EMI_BUSY_FAST           0x8000000
+#define BF_CLKCTRL_HBUS_EMI_BUSY_FAST(v)        (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_HBUS_APBHDMA_BUSY_FAST       26
+#define BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST       0x4000000
+#define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v)    (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_HBUS_APBXDMA_BUSY_FAST       25
+#define BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST       0x2000000
+#define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v)    (((v) << 25) & 0x2000000)
+#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_FAST        24
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST        0x1000000
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v)     (((v) << 24) & 0x1000000)
+#define BP_CLKCTRL_HBUS_TRAFFIC_FAST            23
+#define BM_CLKCTRL_HBUS_TRAFFIC_FAST            0x800000
+#define BF_CLKCTRL_HBUS_TRAFFIC_FAST(v)         (((v) << 23) & 0x800000)
+#define BP_CLKCTRL_HBUS_CPU_DATA_FAST           22
+#define BM_CLKCTRL_HBUS_CPU_DATA_FAST           0x400000
+#define BF_CLKCTRL_HBUS_CPU_DATA_FAST(v)        (((v) << 22) & 0x400000)
+#define BP_CLKCTRL_HBUS_CPU_INSTR_FAST          21
+#define BM_CLKCTRL_HBUS_CPU_INSTR_FAST          0x200000
+#define BF_CLKCTRL_HBUS_CPU_INSTR_FAST(v)       (((v) << 21) & 0x200000)
+#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE          20
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE          0x100000
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)       (((v) << 20) & 0x100000)
+#define BP_CLKCTRL_HBUS_SLOW_DIV                16
+#define BM_CLKCTRL_HBUS_SLOW_DIV                0x30000
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1           0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2           0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4           0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8           0x3
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)             (((v) << 16) & 0x30000)
+#define BF_CLKCTRL_HBUS_SLOW_DIV_V(v)           ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x30000)
+#define BP_CLKCTRL_HBUS_DIV                     0
+#define BM_CLKCTRL_HBUS_DIV                     0x1f
+#define BF_CLKCTRL_HBUS_DIV(v)                  (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_CLKCTRL_XBUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_CLKCTRL_XBUS         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40))
+#define BP_CLKCTRL_XBUS_BUSY    31
+#define BM_CLKCTRL_XBUS_BUSY    0x80000000
+#define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_XBUS_DIV     0
+#define BM_CLKCTRL_XBUS_DIV     0x3ff
+#define BF_CLKCTRL_XBUS_DIV(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_XTAL
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_CLKCTRL_XTAL                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50))
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE           31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE           0x80000000
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)        (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)     (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE         29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE         0x20000000
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)      (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE         28
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE         0x10000000
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)      (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      27
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x8000000
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)   (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x4000000
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)   (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_XTAL_EXRAM_CLK16K_GATE       25
+#define BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE       0x2000000
+#define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v)    (((v) << 25) & 0x2000000)
+#define BP_CLKCTRL_XTAL_LRADC_CLK2K_GATE        24
+#define BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE        0x1000000
+#define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v)     (((v) << 24) & 0x1000000)
+
+/**
+ * Register: HW_CLKCTRL_OCRAM
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_CLKCTRL_OCRAM            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60))
+#define BP_CLKCTRL_OCRAM_CLKGATE    31
+#define BM_CLKCTRL_OCRAM_CLKGATE    0x80000000
+#define BF_CLKCTRL_OCRAM_CLKGATE(v) (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_OCRAM_BUSY       30
+#define BM_CLKCTRL_OCRAM_BUSY       0x40000000
+#define BF_CLKCTRL_OCRAM_BUSY(v)    (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_OCRAM_DIV        0
+#define BM_CLKCTRL_OCRAM_DIV        0x3ff
+#define BF_CLKCTRL_OCRAM_DIV(v)     (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_UTMI
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_CLKCTRL_UTMI                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70))
+#define BP_CLKCTRL_UTMI_UTMI_CLK120M_GATE       31
+#define BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE       0x80000000
+#define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v)    (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_UTMI_UTMI_CLK30M_GATE        30
+#define BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE        0x40000000
+#define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v)     (((v) << 30) & 0x40000000)
+
+/**
+ * Register: HW_CLKCTRL_SSP
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_CLKCTRL_SSP                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80))
+#define BP_CLKCTRL_SSP_CLKGATE          31
+#define BM_CLKCTRL_SSP_CLKGATE          0x80000000
+#define BF_CLKCTRL_SSP_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_SSP_WAIT_PLL_LOCK    30
+#define BM_CLKCTRL_SSP_WAIT_PLL_LOCK    0x40000000
+#define BF_CLKCTRL_SSP_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_SSP_BUSY             29
+#define BM_CLKCTRL_SSP_BUSY             0x20000000
+#define BF_CLKCTRL_SSP_BUSY(v)          (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_SSP_DIV              0
+#define BM_CLKCTRL_SSP_DIV              0x1ff
+#define BF_CLKCTRL_SSP_DIV(v)           (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_CLKCTRL_GPMI
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_CLKCTRL_GPMI                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90))
+#define BP_CLKCTRL_GPMI_CLKGATE             31
+#define BM_CLKCTRL_GPMI_CLKGATE             0x80000000
+#define BF_CLKCTRL_GPMI_CLKGATE(v)          (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_GPMI_WAIT_PLL_LOCK       30
+#define BM_CLKCTRL_GPMI_WAIT_PLL_LOCK       0x40000000
+#define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(v)    (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_GPMI_BUSY                29
+#define BM_CLKCTRL_GPMI_BUSY                0x20000000
+#define BF_CLKCTRL_GPMI_BUSY(v)             (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_GPMI_DIV                 0
+#define BM_CLKCTRL_GPMI_DIV                 0x3ff
+#define BF_CLKCTRL_GPMI_DIV(v)              (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_SPDIF
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_CLKCTRL_SPDIF            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0))
+#define BP_CLKCTRL_SPDIF_CLKGATE    31
+#define BM_CLKCTRL_SPDIF_CLKGATE    0x80000000
+#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_SPDIF_BUSY       30
+#define BM_CLKCTRL_SPDIF_BUSY       0x40000000
+#define BF_CLKCTRL_SPDIF_BUSY(v)    (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_SPDIF_DIV        0
+#define BM_CLKCTRL_SPDIF_DIV        0x7
+#define BF_CLKCTRL_SPDIF_DIV(v)     (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_CLKCTRL_EMI
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_CLKCTRL_EMI                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0))
+#define BP_CLKCTRL_EMI_CLKGATE          31
+#define BM_CLKCTRL_EMI_CLKGATE          0x80000000
+#define BF_CLKCTRL_EMI_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_EMI_WAIT_PLL_LOCK    30
+#define BM_CLKCTRL_EMI_WAIT_PLL_LOCK    0x40000000
+#define BF_CLKCTRL_EMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_EMI_BUSY             29
+#define BM_CLKCTRL_EMI_BUSY             0x20000000
+#define BF_CLKCTRL_EMI_BUSY(v)          (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_EMI_DIV              0
+#define BM_CLKCTRL_EMI_DIV              0x7
+#define BF_CLKCTRL_EMI_DIV(v)           (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_CLKCTRL_IR
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_CLKCTRL_IR                   (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0))
+#define BP_CLKCTRL_IR_CLKGATE           31
+#define BM_CLKCTRL_IR_CLKGATE           0x80000000
+#define BF_CLKCTRL_IR_CLKGATE(v)        (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_IR_WAIT_PLL_LOCK     30
+#define BM_CLKCTRL_IR_WAIT_PLL_LOCK     0x40000000
+#define BF_CLKCTRL_IR_WAIT_PLL_LOCK(v)  (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_IR_AUTO_DIV          29
+#define BM_CLKCTRL_IR_AUTO_DIV          0x20000000
+#define BF_CLKCTRL_IR_AUTO_DIV(v)       (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_IR_IR_BUSY           28
+#define BM_CLKCTRL_IR_IR_BUSY           0x10000000
+#define BF_CLKCTRL_IR_IR_BUSY(v)        (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_IR_IROV_BUSY         27
+#define BM_CLKCTRL_IR_IROV_BUSY         0x8000000
+#define BF_CLKCTRL_IR_IROV_BUSY(v)      (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_IR_IROV_DIV          16
+#define BM_CLKCTRL_IR_IROV_DIV          0x1ff0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)       (((v) << 16) & 0x1ff0000)
+#define BP_CLKCTRL_IR_IR_DIV            0
+#define BM_CLKCTRL_IR_IR_DIV            0x3ff
+#define BF_CLKCTRL_IR_IR_DIV(v)         (((v) << 0) & 0x3ff)
+
+#endif /* __HEADERGEN__STMP3600__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h
new file mode 100644
index 0000000000..5d2fe44fb1
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-dacdma.h
@@ -0,0 +1,62 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__DACDMA__H__
+#define __HEADERGEN__STMP3600__DACDMA__H__
+
+#define REGS_DACDMA_BASE (0x8004c000)
+
+#define REGS_DACDMA_VERSION "2.3.0"
+
+/**
+ * Register: HW_DACDMA_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DACDMA_CTRL              (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x0))
+#define HW_DACDMA_CTRL_SET          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x4))
+#define HW_DACDMA_CTRL_CLR          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0x8))
+#define HW_DACDMA_CTRL_TOG          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x0 + 0xc))
+#define BP_DACDMA_CTRL_SFTRST       31
+#define BM_DACDMA_CTRL_SFTRST       0x80000000
+#define BF_DACDMA_CTRL_SFTRST(v)    (((v) << 31) & 0x80000000)
+#define BP_DACDMA_CTRL_CLKGATE      30
+#define BM_DACDMA_CTRL_CLKGATE      0x40000000
+#define BF_DACDMA_CTRL_CLKGATE(v)   (((v) << 30) & 0x40000000)
+#define BP_DACDMA_CTRL_RUN          0
+#define BM_DACDMA_CTRL_RUN          0x1
+#define BF_DACDMA_CTRL_RUN(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DACDMA_DATA
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_DACDMA_DATA          (*(volatile unsigned long *)(REGS_DACDMA_BASE + 0x80))
+#define BP_DACDMA_DATA_HIGH     16
+#define BM_DACDMA_DATA_HIGH     0xffff0000
+#define BF_DACDMA_DATA_HIGH(v)  (((v) << 16) & 0xffff0000)
+#define BP_DACDMA_DATA_LOW      0
+#define BM_DACDMA_DATA_LOW      0xffff
+#define BF_DACDMA_DATA_LOW(v)   (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3600__DACDMA__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h
new file mode 100644
index 0000000000..a7b45a7ca9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-digctl.h
@@ -0,0 +1,595 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__DIGCTL__H__
+#define __HEADERGEN__STMP3600__DIGCTL__H__
+
+#define REGS_DIGCTL_BASE (0x8001c000)
+
+#define REGS_DIGCTL_VERSION "2.3.0"
+
+/**
+ * Register: HW_DIGCTL_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DIGCTL_CTRL                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0))
+#define HW_DIGCTL_CTRL_SET                              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4))
+#define HW_DIGCTL_CTRL_CLR                              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8))
+#define HW_DIGCTL_CTRL_TOG                              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc))
+#define BP_DIGCTL_CTRL_MASTER_SELECT                    24
+#define BM_DIGCTL_CTRL_MASTER_SELECT                    0x1f000000
+#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I             0x1
+#define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D             0x2
+#define BV_DIGCTL_CTRL_MASTER_SELECT__USB               0x4
+#define BV_DIGCTL_CTRL_MASTER_SELECT__APBH              0x8
+#define BV_DIGCTL_CTRL_MASTER_SELECT__APBX              0x10
+#define BF_DIGCTL_CTRL_MASTER_SELECT(v)                 (((v) << 24) & 0x1f000000)
+#define BF_DIGCTL_CTRL_MASTER_SELECT_V(v)               ((BV_DIGCTL_CTRL_MASTER_SELECT__##v << 24) & 0x1f000000)
+#define BP_DIGCTL_CTRL_USB_TESTMODE                     20
+#define BM_DIGCTL_CTRL_USB_TESTMODE                     0x100000
+#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                  (((v) << 20) & 0x100000)
+#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                  19
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                  0x80000
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)               (((v) << 19) & 0x80000)
+#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                 18
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                 0x40000
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)              (((v) << 18) & 0x40000)
+#define BP_DIGCTL_CTRL_UTMI_TESTMODE                    17
+#define BM_DIGCTL_CTRL_UTMI_TESTMODE                    0x20000
+#define BF_DIGCTL_CTRL_UTMI_TESTMODE(v)                 (((v) << 17) & 0x20000)
+#define BP_DIGCTL_CTRL_UART_LOOPBACK                    16
+#define BM_DIGCTL_CTRL_UART_LOOPBACK                    0x10000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL            0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT            0x1
+#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                 (((v) << 16) & 0x10000)
+#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v)               ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000)
+#define BP_DIGCTL_CTRL_DEBUG_DISABLE                    3
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE                    0x8
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                 (((v) << 3) & 0x8)
+#define BP_DIGCTL_CTRL_USB_CLKGATE                      2
+#define BM_DIGCTL_CTRL_USB_CLKGATE                      0x4
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                 0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS             0x1
+#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                   (((v) << 2) & 0x4)
+#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v)                 ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4)
+#define BP_DIGCTL_CTRL_JTAG_SHIELD                      1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD                      0x2
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL              0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP          0x1
+#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                   (((v) << 1) & 0x2)
+#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v)                 ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2)
+#define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE             0
+#define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE             0x1
+#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE    0x0
+#define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE     0x1
+#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v)          (((v) << 0) & 0x1)
+#define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v)        ((BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##v << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_STATUS
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DIGCTL_STATUS                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10))
+#define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT       31
+#define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT       0x80000000
+#define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v)    (((v) << 31) & 0x80000000)
+#define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT    6
+#define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT    0x40
+#define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) << 6) & 0x40)
+#define BP_DIGCTL_STATUS_ROM_SHIELDED           5
+#define BM_DIGCTL_STATUS_ROM_SHIELDED           0x20
+#define BF_DIGCTL_STATUS_ROM_SHIELDED(v)        (((v) << 5) & 0x20)
+#define BP_DIGCTL_STATUS_JTAG_IN_USE            4
+#define BM_DIGCTL_STATUS_JTAG_IN_USE            0x10
+#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)         (((v) << 4) & 0x10)
+#define BP_DIGCTL_STATUS_PSWITCH                2
+#define BM_DIGCTL_STATUS_PSWITCH                0xc
+#define BF_DIGCTL_STATUS_PSWITCH(v)             (((v) << 2) & 0xc)
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE           1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE           0x2
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)        (((v) << 1) & 0x2)
+#define BP_DIGCTL_STATUS_WRITTEN                0
+#define BM_DIGCTL_STATUS_WRITTEN                0x1
+#define BF_DIGCTL_STATUS_WRITTEN(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_HCLKCOUNT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DIGCTL_HCLKCOUNT             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20))
+#define BP_DIGCTL_HCLKCOUNT_COUNT       0
+#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_RAMCTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMCTRL                           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0))
+#define HW_DIGCTL_RAMCTRL_SET                       (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4))
+#define HW_DIGCTL_RAMCTRL_CLR                       (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8))
+#define HW_DIGCTL_RAMCTRL_TOG                       (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc))
+#define BP_DIGCTL_RAMCTRL_TEST_MARGIN               28
+#define BM_DIGCTL_RAMCTRL_TEST_MARGIN               0x70000000
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL       0x0
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1       0x1
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2       0x2
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3       0x3
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4       0x4
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5       0x5
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6       0x6
+#define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7       0x7
+#define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v)            (((v) << 28) & 0x70000000)
+#define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(v)          ((BV_DIGCTL_RAMCTRL_TEST_MARGIN__##v << 28) & 0x70000000)
+#define BP_DIGCTL_RAMCTRL_PWDN_BANKS                24
+#define BM_DIGCTL_RAMCTRL_PWDN_BANKS                0xf000000
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3    0x8
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2    0x4
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1    0x2
+#define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0    0x1
+#define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v)             (((v) << 24) & 0xf000000)
+#define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(v)           ((BV_DIGCTL_RAMCTRL_PWDN_BANKS__##v << 24) & 0xf000000)
+#define BP_DIGCTL_RAMCTRL_TEMP_SENSOR               20
+#define BM_DIGCTL_RAMCTRL_TEMP_SENSOR               0x700000
+#define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v)            (((v) << 20) & 0x700000)
+#define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP            16
+#define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP            0x70000
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP  0x1
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A   0x2
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B   0x3
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C   0x4
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D   0x5
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E   0x6
+#define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F   0x7
+#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v)         (((v) << 16) & 0x70000)
+#define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v)       ((BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##v << 16) & 0x70000)
+#define BP_DIGCTL_RAMCTRL_SHIFT_COUNT               8
+#define BM_DIGCTL_RAMCTRL_SHIFT_COUNT               0x7f00
+#define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v)            (((v) << 8) & 0x7f00)
+#define BP_DIGCTL_RAMCTRL_FLIP_CLK                  7
+#define BM_DIGCTL_RAMCTRL_FLIP_CLK                  0x80
+#define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL          0x0
+#define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT          0x1
+#define BF_DIGCTL_RAMCTRL_FLIP_CLK(v)               (((v) << 7) & 0x80)
+#define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(v)             ((BV_DIGCTL_RAMCTRL_FLIP_CLK__##v << 7) & 0x80)
+#define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP            3
+#define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP            0x8
+#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL    0x0
+#define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1
+#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v)         (((v) << 3) & 0x8)
+#define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v)       ((BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##v << 3) & 0x8)
+#define BP_DIGCTL_RAMCTRL_REF_CLK_GATE              2
+#define BM_DIGCTL_RAMCTRL_REF_CLK_GATE              0x4
+#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL      0x0
+#define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF         0x1
+#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v)           (((v) << 2) & 0x4)
+#define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v)         ((BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##v << 2) & 0x4)
+#define BP_DIGCTL_RAMCTRL_REPAIR_STATUS             1
+#define BM_DIGCTL_RAMCTRL_REPAIR_STATUS             0x2
+#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE       0x0
+#define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY       0x1
+#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v)          (((v) << 1) & 0x2)
+#define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v)        ((BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##v << 1) & 0x2)
+#define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT           0
+#define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT           0x1
+#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE     0x0
+#define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND     0x1
+#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v)        (((v) << 0) & 0x1)
+#define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v)      ((BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##v << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_RAMREPAIR0
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMREPAIR0            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0))
+#define HW_DIGCTL_RAMREPAIR0_SET        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4))
+#define HW_DIGCTL_RAMREPAIR0_CLR        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8))
+#define HW_DIGCTL_RAMREPAIR0_TOG        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc))
+#define BP_DIGCTL_RAMREPAIR0_EFUSE3     24
+#define BM_DIGCTL_RAMREPAIR0_EFUSE3     0x7f000000
+#define BF_DIGCTL_RAMREPAIR0_EFUSE3(v)  (((v) << 24) & 0x7f000000)
+#define BP_DIGCTL_RAMREPAIR0_EFUSE2     16
+#define BM_DIGCTL_RAMREPAIR0_EFUSE2     0x7f0000
+#define BF_DIGCTL_RAMREPAIR0_EFUSE2(v)  (((v) << 16) & 0x7f0000)
+#define BP_DIGCTL_RAMREPAIR0_EFUSE1     8
+#define BM_DIGCTL_RAMREPAIR0_EFUSE1     0x7f00
+#define BF_DIGCTL_RAMREPAIR0_EFUSE1(v)  (((v) << 8) & 0x7f00)
+#define BP_DIGCTL_RAMREPAIR0_EFUSE0     0
+#define BM_DIGCTL_RAMREPAIR0_EFUSE0     0x7f
+#define BF_DIGCTL_RAMREPAIR0_EFUSE0(v)  (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_DIGCTL_RAMREPAIR1
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMREPAIR1            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0))
+#define HW_DIGCTL_RAMREPAIR1_SET        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4))
+#define HW_DIGCTL_RAMREPAIR1_CLR        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8))
+#define HW_DIGCTL_RAMREPAIR1_TOG        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc))
+#define BP_DIGCTL_RAMREPAIR1_EFUSE3     24
+#define BM_DIGCTL_RAMREPAIR1_EFUSE3     0x7f000000
+#define BF_DIGCTL_RAMREPAIR1_EFUSE3(v)  (((v) << 24) & 0x7f000000)
+#define BP_DIGCTL_RAMREPAIR1_EFUSE2     16
+#define BM_DIGCTL_RAMREPAIR1_EFUSE2     0x7f0000
+#define BF_DIGCTL_RAMREPAIR1_EFUSE2(v)  (((v) << 16) & 0x7f0000)
+#define BP_DIGCTL_RAMREPAIR1_EFUSE1     8
+#define BM_DIGCTL_RAMREPAIR1_EFUSE1     0x7f00
+#define BF_DIGCTL_RAMREPAIR1_EFUSE1(v)  (((v) << 8) & 0x7f00)
+#define BP_DIGCTL_RAMREPAIR1_EFUSE0     0
+#define BM_DIGCTL_RAMREPAIR1_EFUSE0     0x7f
+#define BF_DIGCTL_RAMREPAIR1_EFUSE0(v)  (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_DIGCTL_WRITEONCE
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DIGCTL_WRITEONCE         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60))
+#define BP_DIGCTL_WRITEONCE_BITS    0
+#define BM_DIGCTL_WRITEONCE_BITS    0xffffffff
+#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_AHBCYCLES
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_DIGCTL_AHBCYCLES             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x70))
+#define BP_DIGCTL_AHBCYCLES_COUNT       0
+#define BM_DIGCTL_AHBCYCLES_COUNT       0xffffffff
+#define BF_DIGCTL_AHBCYCLES_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_AHBSTALLED
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_DIGCTL_AHBSTALLED            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x80))
+#define BP_DIGCTL_AHBSTALLED_COUNT      0
+#define BM_DIGCTL_AHBSTALLED_COUNT      0xffffffff
+#define BF_DIGCTL_AHBSTALLED_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ENTROPY
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DIGCTL_ENTROPY           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90))
+#define BP_DIGCTL_ENTROPY_VALUE     0
+#define BM_DIGCTL_ENTROPY_VALUE     0xffffffff
+#define BF_DIGCTL_ENTROPY_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ROMSHIELD
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DIGCTL_ROMSHIELD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0))
+#define BP_DIGCTL_ROMSHIELD_WRITE_ONCE      0
+#define BM_DIGCTL_ROMSHIELD_WRITE_ONCE      0x1
+#define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_MICROSECONDS
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_DIGCTL_MICROSECONDS          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0))
+#define HW_DIGCTL_MICROSECONDS_SET      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4))
+#define HW_DIGCTL_MICROSECONDS_CLR      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8))
+#define HW_DIGCTL_MICROSECONDS_TOG      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc))
+#define BP_DIGCTL_MICROSECONDS_VALUE    0
+#define BM_DIGCTL_MICROSECONDS_VALUE    0xffffffff
+#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBGRD
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBGRD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0))
+#define BP_DIGCTL_DBGRD_COMPLEMENT      0
+#define BM_DIGCTL_DBGRD_COMPLEMENT      0xffffffff
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBG
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0))
+#define BP_DIGCTL_DBG_VALUE     0
+#define BM_DIGCTL_DBG_VALUE     0xffffffff
+#define BF_DIGCTL_DBG_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_BIST_CSR
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_DIGCTL_1TRAM_BIST_CSR            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x0))
+#define HW_DIGCTL_1TRAM_BIST_CSR_SET        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x4))
+#define HW_DIGCTL_1TRAM_BIST_CSR_CLR        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0x8))
+#define HW_DIGCTL_1TRAM_BIST_CSR_TOG        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0 + 0xc))
+#define BP_DIGCTL_1TRAM_BIST_CSR_FAIL       3
+#define BM_DIGCTL_1TRAM_BIST_CSR_FAIL       0x8
+#define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v)    (((v) << 3) & 0x8)
+#define BP_DIGCTL_1TRAM_BIST_CSR_PASS       2
+#define BM_DIGCTL_1TRAM_BIST_CSR_PASS       0x4
+#define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v)    (((v) << 2) & 0x4)
+#define BP_DIGCTL_1TRAM_BIST_CSR_DONE       1
+#define BM_DIGCTL_1TRAM_BIST_CSR_DONE       0x2
+#define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v)    (((v) << 1) & 0x2)
+#define BP_DIGCTL_1TRAM_BIST_CSR_START      0
+#define BM_DIGCTL_1TRAM_BIST_CSR_START      0x1
+#define BF_DIGCTL_1TRAM_BIST_CSR_START(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_BIST_REPAIR0
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_BIST_REPAIR0    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0))
+
+/**
+ * Register: HW_DIGCTL_1TRAM_BIST_REPAIR1
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_BIST_REPAIR1    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x100))
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS0
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS0                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110))
+#define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00      0
+#define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS1
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS1                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120))
+#define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01      0
+#define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS2
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS2                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130))
+#define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10      0
+#define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS3
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS3                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140))
+#define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11      0
+#define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS4
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS4                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150))
+#define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20      0
+#define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS5
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS5                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160))
+#define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21      0
+#define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS6
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS6                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170))
+#define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30      0
+#define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS7
+ * Address: 0x180
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS7                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180))
+#define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31      0
+#define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31      0xffffffff
+#define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS8
+ * Address: 0x190
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS8                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190))
+#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01      16
+#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01      0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v)   (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00      0
+#define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00      0xffff
+#define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS9
+ * Address: 0x1a0
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS9                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0))
+#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11      16
+#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11      0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v)   (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10      0
+#define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10      0xffff
+#define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS10
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS10                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0))
+#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21     16
+#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21     0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v)  (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20     0
+#define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20     0xffff
+#define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS11
+ * Address: 0x1c0
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS11                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0))
+#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31     16
+#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31     0xffff0000
+#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v)  (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30     0
+#define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30     0xffff
+#define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS12
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS12                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0))
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11    24
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11    0x1f000000
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000)
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10    16
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10    0x1f0000
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000)
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01    8
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01    0x1f00
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00)
+#define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00    0
+#define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00    0x1f
+#define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DIGCTL_1TRAM_STATUS13
+ * Address: 0x1e0
+ * SCT: no
+*/
+#define HW_DIGCTL_1TRAM_STATUS13                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0))
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31    24
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31    0x1f000000
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000)
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30    16
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30    0x1f0000
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000)
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21    8
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21    0x1f00
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00)
+#define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20    0
+#define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20    0x1f
+#define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH0
+ * Address: 0x290
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH0          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290))
+#define BP_DIGCTL_SCRATCH0_PTR      0
+#define BM_DIGCTL_SCRATCH0_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH0_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH1
+ * Address: 0x2a0
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH1          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0))
+#define BP_DIGCTL_SCRATCH1_PTR      0
+#define BM_DIGCTL_SCRATCH1_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH1_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ARMCACHE
+ * Address: 0x2b0
+ * SCT: no
+*/
+#define HW_DIGCTL_ARMCACHE              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0))
+#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  (((v) << 8) & 0x300)
+#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x30
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)   (((v) << 4) & 0x30)
+#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x3
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)   (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DIGCTL_SGTL
+ * Address: 0x300
+ * SCT: no
+*/
+#define HW_DIGCTL_SGTL              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300))
+#define BP_DIGCTL_SGTL_COPYRIGHT    0
+#define BM_DIGCTL_SGTL_COPYRIGHT    0xffffffff
+#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_CHIPID
+ * Address: 0x310
+ * SCT: no
+*/
+#define HW_DIGCTL_CHIPID                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310))
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_CHIPID_REVISION           0
+#define BM_DIGCTL_CHIPID_REVISION           0xff
+#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) << 0) & 0xff)
+
+#endif /* __HEADERGEN__STMP3600__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h
new file mode 100644
index 0000000000..2d2624a953
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-dri.h
@@ -0,0 +1,258 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__DRI__H__
+#define __HEADERGEN__STMP3600__DRI__H__
+
+#define REGS_DRI_BASE (0x80074000)
+
+#define REGS_DRI_VERSION "2.3.0"
+
+/**
+ * Register: HW_DRI_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DRI_CTRL                                     (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
+#define HW_DRI_CTRL_SET                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
+#define HW_DRI_CTRL_CLR                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
+#define HW_DRI_CTRL_TOG                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
+#define BP_DRI_CTRL_SFTRST                              31
+#define BM_DRI_CTRL_SFTRST                              0x80000000
+#define BV_DRI_CTRL_SFTRST__RUN                         0x0
+#define BV_DRI_CTRL_SFTRST__RESET                       0x1
+#define BF_DRI_CTRL_SFTRST(v)                           (((v) << 31) & 0x80000000)
+#define BF_DRI_CTRL_SFTRST_V(v)                         ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_DRI_CTRL_CLKGATE                             30
+#define BM_DRI_CTRL_CLKGATE                             0x40000000
+#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
+#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
+#define BF_DRI_CTRL_CLKGATE(v)                          (((v) << 30) & 0x40000000)
+#define BF_DRI_CTRL_CLKGATE_V(v)                        ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_DRI_CTRL_ENABLE_INPUTS                       29
+#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
+#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
+#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
+#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) << 29) & 0x20000000)
+#define BF_DRI_CTRL_ENABLE_INPUTS_V(v)                  ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
+#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
+#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) << 26) & 0x4000000)
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
+#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
+#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) << 25) & 0x2000000)
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
+#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
+#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
+#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) << 16) & 0x1f0000)
+#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
+#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
+#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) << 15) & 0x8000)
+#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v)                ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
+#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
+#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) << 11) & 0x800)
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)                ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) << 10) & 0x400)
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)         ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
+#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
+#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) << 9) & 0x200)
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v)               ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
+#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
+#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
+#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) << 3) & 0x8)
+#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v)                   ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) << 2) & 0x4)
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)            ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
+#define BP_DRI_CTRL_ATTENTION_IRQ                       1
+#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
+#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) << 1) & 0x2)
+#define BF_DRI_CTRL_ATTENTION_IRQ_V(v)                  ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
+#define BP_DRI_CTRL_RUN                                 0
+#define BM_DRI_CTRL_RUN                                 0x1
+#define BV_DRI_CTRL_RUN__HALT                           0x0
+#define BV_DRI_CTRL_RUN__RUN                            0x1
+#define BF_DRI_CTRL_RUN(v)                              (((v) << 0) & 0x1)
+#define BF_DRI_CTRL_RUN_V(v)                            ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
+
+/**
+ * Register: HW_DRI_TIMING
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DRI_TIMING                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
+#define BP_DRI_TIMING_PILOT_REP_RATE            16
+#define BM_DRI_TIMING_PILOT_REP_RATE            0xf0000
+#define BF_DRI_TIMING_PILOT_REP_RATE(v)         (((v) << 16) & 0xf0000)
+#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL    0
+#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL    0xff
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DRI_STAT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DRI_STAT                                         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
+#define BP_DRI_STAT_DRI_PRESENT                             31
+#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
+#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
+#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
+#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) << 31) & 0x80000000)
+#define BF_DRI_STAT_DRI_PRESENT_V(v)                        ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
+#define BP_DRI_STAT_PILOT_PHASE                             16
+#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
+#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) << 16) & 0xf0000)
+#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
+#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) << 3) & 0x8)
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)               ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
+#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
+#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) << 2) & 0x4)
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)        ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
+#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
+#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) << 1) & 0x2)
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)              ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
+
+/**
+ * Register: HW_DRI_DATA
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_DRI_DATA         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
+#define BP_DRI_DATA_DATA    0
+#define BM_DRI_DATA_DATA    0xffffffff
+#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DRI_DEBUG0
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_DRI_DEBUG0                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
+#define HW_DRI_DEBUG0_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
+#define HW_DRI_DEBUG0_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
+#define HW_DRI_DEBUG0_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
+#define BP_DRI_DEBUG0_DMAREQ                        31
+#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
+#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) << 31) & 0x80000000)
+#define BP_DRI_DEBUG0_DMACMDKICK                    30
+#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
+#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) << 30) & 0x40000000)
+#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
+#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) << 29) & 0x20000000)
+#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
+#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) << 28) & 0x10000000)
+#define BP_DRI_DEBUG0_TEST_MODE                     27
+#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
+#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) << 27) & 0x8000000)
+#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
+#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
+#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) << 26) & 0x4000000)
+#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v)           ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
+#define BP_DRI_DEBUG0_SPARE                         18
+#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
+#define BF_DRI_DEBUG0_SPARE(v)                      (((v) << 18) & 0x3fc0000)
+#define BP_DRI_DEBUG0_FRAME                         0
+#define BM_DRI_DEBUG0_FRAME                         0x3ffff
+#define BF_DRI_DEBUG0_FRAME(v)                      (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_DRI_DEBUG1
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_DRI_DEBUG1                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
+#define HW_DRI_DEBUG1_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
+#define HW_DRI_DEBUG1_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
+#define HW_DRI_DEBUG1_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
+#define BP_DRI_DEBUG1_INVERT_PILOT                  31
+#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
+#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
+#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
+#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) << 31) & 0x80000000)
+#define BF_DRI_DEBUG1_INVERT_PILOT_V(v)             ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
+#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
+#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) << 30) & 0x40000000)
+#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v)         ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
+#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
+#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) << 29) & 0x20000000)
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v)          ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
+#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
+#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) << 28) & 0x10000000)
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)         ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
+#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
+#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
+#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
+#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
+#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) << 27) & 0x8000000)
+#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v)            ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
+#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
+#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) << 0) & 0x3ffff)
+
+#endif /* __HEADERGEN__STMP3600__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h
new file mode 100644
index 0000000000..88a94f977b
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-emictrl.h
@@ -0,0 +1,30 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__EMICTRL__H__
+#define __HEADERGEN__STMP3600__EMICTRL__H__
+
+#define REGS_EMICTRL_BASE (0x80020000)
+
+#define REGS_EMICTRL_VERSION "2.3.0"
+
+#endif /* __HEADERGEN__STMP3600__EMICTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h
new file mode 100644
index 0000000000..bdf52c9308
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-gpmi.h
@@ -0,0 +1,372 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__GPMI__H__
+#define __HEADERGEN__STMP3600__GPMI__H__
+
+#define REGS_GPMI_BASE (0x8000c000)
+
+#define REGS_GPMI_VERSION "2.3.0"
+
+/**
+ * Register: HW_GPMI_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL0                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
+#define HW_GPMI_CTRL0_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
+#define HW_GPMI_CTRL0_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
+#define HW_GPMI_CTRL0_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
+#define BP_GPMI_CTRL0_SFTRST                            31
+#define BM_GPMI_CTRL0_SFTRST                            0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
+#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) << 31) & 0x80000000)
+#define BF_GPMI_CTRL0_SFTRST_V(v)                       ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
+#define BP_GPMI_CTRL0_CLKGATE                           30
+#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
+#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) << 30) & 0x40000000)
+#define BF_GPMI_CTRL0_CLKGATE_V(v)                      ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
+#define BP_GPMI_CTRL0_RUN                               29
+#define BM_GPMI_CTRL0_RUN                               0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
+#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
+#define BF_GPMI_CTRL0_RUN(v)                            (((v) << 29) & 0x20000000)
+#define BF_GPMI_CTRL0_RUN_V(v)                          ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
+#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
+#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
+#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) << 28) & 0x10000000)
+#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) << 27) & 0x8000000)
+#define BP_GPMI_CTRL0_UDMA                              26
+#define BM_GPMI_CTRL0_UDMA                              0x4000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
+#define BF_GPMI_CTRL0_UDMA(v)                           (((v) << 26) & 0x4000000)
+#define BF_GPMI_CTRL0_UDMA_V(v)                         ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
+#define BP_GPMI_CTRL0_COMMAND_MODE                      24
+#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) << 24) & 0x3000000)
+#define BF_GPMI_CTRL0_COMMAND_MODE_V(v)                 ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
+#define BP_GPMI_CTRL0_WORD_LENGTH                       23
+#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
+#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) << 23) & 0x800000)
+#define BF_GPMI_CTRL0_WORD_LENGTH_V(v)                  ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
+#define BP_GPMI_CTRL0_LOCK_CS                           22
+#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
+#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) << 22) & 0x400000)
+#define BF_GPMI_CTRL0_LOCK_CS_V(v)                      ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
+#define BP_GPMI_CTRL0_CS                                20
+#define BM_GPMI_CTRL0_CS                                0x300000
+#define BF_GPMI_CTRL0_CS(v)                             (((v) << 20) & 0x300000)
+#define BP_GPMI_CTRL0_ADDRESS                           17
+#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
+#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) << 17) & 0xe0000)
+#define BF_GPMI_CTRL0_ADDRESS_V(v)                      ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
+#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) << 16) & 0x10000)
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)            ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
+#define BP_GPMI_CTRL0_XFER_COUNT                        0
+#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
+#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_COMPARE
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_GPMI_COMPARE                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
+#define BP_GPMI_COMPARE_MASK            16
+#define BM_GPMI_COMPARE_MASK            0xffff0000
+#define BF_GPMI_COMPARE_MASK(v)         (((v) << 16) & 0xffff0000)
+#define BP_GPMI_COMPARE_REFERENCE       0
+#define BM_GPMI_COMPARE_REFERENCE       0xffff
+#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_CTRL1
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL1                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
+#define HW_GPMI_CTRL1_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
+#define HW_GPMI_CTRL1_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
+#define HW_GPMI_CTRL1_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
+#define BP_GPMI_CTRL1_DSAMPLE_TIME                      12
+#define BM_GPMI_CTRL1_DSAMPLE_TIME                      0x3000
+#define BF_GPMI_CTRL1_DSAMPLE_TIME(v)                   (((v) << 12) & 0x3000)
+#define BP_GPMI_CTRL1_DEV_IRQ                           10
+#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
+#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) << 10) & 0x400)
+#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) << 9) & 0x200)
+#define BP_GPMI_CTRL1_BURST_EN                          8
+#define BM_GPMI_CTRL1_BURST_EN                          0x100
+#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) << 8) & 0x100)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) << 7) & 0x80)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) << 6) & 0x40)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) << 5) & 0x20)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) << 4) & 0x10)
+#define BP_GPMI_CTRL1_DEV_RESET                         3
+#define BM_GPMI_CTRL1_DEV_RESET                         0x8
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
+#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) << 3) & 0x8)
+#define BF_GPMI_CTRL1_DEV_RESET_V(v)                    ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
+#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) << 2) & 0x4)
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)          ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
+#define BP_GPMI_CTRL1_CAMERA_MODE                       1
+#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
+#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) << 1) & 0x2)
+#define BP_GPMI_CTRL1_GPMI_MODE                         0
+#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
+#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) << 0) & 0x1)
+#define BF_GPMI_CTRL1_GPMI_MODE_V(v)                    ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
+
+/**
+ * Register: HW_GPMI_TIMING0
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_GPMI_TIMING0                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
+#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING0_DATA_HOLD           8
+#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING0_DATA_SETUP          0
+#define BM_GPMI_TIMING0_DATA_SETUP          0xff
+#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_GPMI_TIMING1
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_GPMI_TIMING1                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xffff0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)  (((v) << 16) & 0xffff0000)
+#define BP_GPMI_TIMING1_ATA_READY_TIMEOUT       0
+#define BM_GPMI_TIMING1_ATA_READY_TIMEOUT       0xffff
+#define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_TIMING2
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_GPMI_TIMING2                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
+#define BP_GPMI_TIMING2_UDMA_TRP        24
+#define BM_GPMI_TIMING2_UDMA_TRP        0xff000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v)     (((v) << 24) & 0xff000000)
+#define BP_GPMI_TIMING2_UDMA_ENV        16
+#define BM_GPMI_TIMING2_UDMA_ENV        0xff0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)     (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING2_UDMA_HOLD       8
+#define BM_GPMI_TIMING2_UDMA_HOLD       0xff00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING2_UDMA_SETUP      0
+#define BM_GPMI_TIMING2_UDMA_SETUP      0xff
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_GPMI_DATA
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_GPMI_DATA            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60))
+#define BP_GPMI_DATA_DATA       0
+#define BM_GPMI_DATA_DATA       0xffffffff
+#define BF_GPMI_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPMI_STAT
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_GPMI_STAT                        (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
+#define BP_GPMI_STAT_PRESENT                31
+#define BM_GPMI_STAT_PRESENT                0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
+#define BF_GPMI_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
+#define BF_GPMI_STAT_PRESENT_V(v)           ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_GPMI_STAT_RDY_TIMEOUT            8
+#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) << 8) & 0xf00)
+#define BP_GPMI_STAT_ATA_IRQ                7
+#define BM_GPMI_STAT_ATA_IRQ                0x80
+#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) << 7) & 0x80)
+#define BP_GPMI_STAT_FIFO_EMPTY             5
+#define BM_GPMI_STAT_FIFO_EMPTY             0x20
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
+#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) << 5) & 0x20)
+#define BF_GPMI_STAT_FIFO_EMPTY_V(v)        ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
+#define BP_GPMI_STAT_FIFO_FULL              4
+#define BM_GPMI_STAT_FIFO_FULL              0x10
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
+#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) << 4) & 0x10)
+#define BF_GPMI_STAT_FIFO_FULL_V(v)         ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
+#define BP_GPMI_STAT_DEV3_ERROR             3
+#define BM_GPMI_STAT_DEV3_ERROR             0x8
+#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) << 3) & 0x8)
+#define BP_GPMI_STAT_DEV2_ERROR             2
+#define BM_GPMI_STAT_DEV2_ERROR             0x4
+#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) << 2) & 0x4)
+#define BP_GPMI_STAT_DEV1_ERROR             1
+#define BM_GPMI_STAT_DEV1_ERROR             0x2
+#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) << 1) & 0x2)
+#define BP_GPMI_STAT_DEV0_ERROR             0
+#define BM_GPMI_STAT_DEV0_ERROR             0x1
+#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_GPMI_DEBUG
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_GPMI_DEBUG                           (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
+#define BP_GPMI_DEBUG_READY3                    31
+#define BM_GPMI_DEBUG_READY3                    0x80000000
+#define BF_GPMI_DEBUG_READY3(v)                 (((v) << 31) & 0x80000000)
+#define BP_GPMI_DEBUG_READY2                    30
+#define BM_GPMI_DEBUG_READY2                    0x40000000
+#define BF_GPMI_DEBUG_READY2(v)                 (((v) << 30) & 0x40000000)
+#define BP_GPMI_DEBUG_READY1                    29
+#define BM_GPMI_DEBUG_READY1                    0x20000000
+#define BF_GPMI_DEBUG_READY1(v)                 (((v) << 29) & 0x20000000)
+#define BP_GPMI_DEBUG_READY0                    28
+#define BM_GPMI_DEBUG_READY0                    0x10000000
+#define BF_GPMI_DEBUG_READY0(v)                 (((v) << 28) & 0x10000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) << 27) & 0x8000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) << 26) & 0x4000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) << 25) & 0x2000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) << 24) & 0x1000000)
+#define BP_GPMI_DEBUG_SENSE3                    23
+#define BM_GPMI_DEBUG_SENSE3                    0x800000
+#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) << 23) & 0x800000)
+#define BP_GPMI_DEBUG_SENSE2                    22
+#define BM_GPMI_DEBUG_SENSE2                    0x400000
+#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) << 22) & 0x400000)
+#define BP_GPMI_DEBUG_SENSE1                    21
+#define BM_GPMI_DEBUG_SENSE1                    0x200000
+#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) << 21) & 0x200000)
+#define BP_GPMI_DEBUG_SENSE0                    20
+#define BM_GPMI_DEBUG_SENSE0                    0x100000
+#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) << 20) & 0x100000)
+#define BP_GPMI_DEBUG_DMAREQ3                   19
+#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
+#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) << 19) & 0x80000)
+#define BP_GPMI_DEBUG_DMAREQ2                   18
+#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
+#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) << 18) & 0x40000)
+#define BP_GPMI_DEBUG_DMAREQ1                   17
+#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
+#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) << 17) & 0x20000)
+#define BP_GPMI_DEBUG_DMAREQ0                   16
+#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
+#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) << 16) & 0x10000)
+#define BP_GPMI_DEBUG_CMD_END                   12
+#define BM_GPMI_DEBUG_CMD_END                   0xf000
+#define BF_GPMI_DEBUG_CMD_END(v)                (((v) << 12) & 0xf000)
+#define BP_GPMI_DEBUG_UDMA_STATE                8
+#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) << 8) & 0xf00)
+#define BP_GPMI_DEBUG_BUSY                      7
+#define BM_GPMI_DEBUG_BUSY                      0x80
+#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
+#define BF_GPMI_DEBUG_BUSY(v)                   (((v) << 7) & 0x80)
+#define BF_GPMI_DEBUG_BUSY_V(v)                 ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
+#define BP_GPMI_DEBUG_PIN_STATE                 4
+#define BM_GPMI_DEBUG_PIN_STATE                 0x70
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
+#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) << 4) & 0x70)
+#define BF_GPMI_DEBUG_PIN_STATE_V(v)            ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
+#define BP_GPMI_DEBUG_MAIN_STATE                0
+#define BM_GPMI_DEBUG_MAIN_STATE                0xf
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
+#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) << 0) & 0xf)
+#define BF_GPMI_DEBUG_MAIN_STATE_V(v)           ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
+
+#endif /* __HEADERGEN__STMP3600__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h
new file mode 100644
index 0000000000..b6e5ead2ba
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-hwecc.h
@@ -0,0 +1,223 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__HWECC__H__
+#define __HEADERGEN__STMP3600__HWECC__H__
+
+#define REGS_HWECC_BASE (0x80008000)
+
+#define REGS_HWECC_VERSION "2.3.0"
+
+/**
+ * Register: HW_HWECC_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_HWECC_CTRL                   (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x0))
+#define HW_HWECC_CTRL_SET               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x4))
+#define HW_HWECC_CTRL_CLR               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0x8))
+#define HW_HWECC_CTRL_TOG               (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x0 + 0xc))
+#define BP_HWECC_CTRL_SFTRST            31
+#define BM_HWECC_CTRL_SFTRST            0x80000000
+#define BF_HWECC_CTRL_SFTRST(v)         (((v) << 31) & 0x80000000)
+#define BP_HWECC_CTRL_CLKGATE           30
+#define BM_HWECC_CTRL_CLKGATE           0x40000000
+#define BF_HWECC_CTRL_CLKGATE(v)        (((v) << 30) & 0x40000000)
+#define BP_HWECC_CTRL_NUM_SYMBOLS       16
+#define BM_HWECC_CTRL_NUM_SYMBOLS       0x1ff0000
+#define BF_HWECC_CTRL_NUM_SYMBOLS(v)    (((v) << 16) & 0x1ff0000)
+#define BP_HWECC_CTRL_DMAWAIT_COUNT     8
+#define BM_HWECC_CTRL_DMAWAIT_COUNT     0x1f00
+#define BF_HWECC_CTRL_DMAWAIT_COUNT(v)  (((v) << 8) & 0x1f00)
+#define BP_HWECC_CTRL_BYTE_ENABLE       6
+#define BM_HWECC_CTRL_BYTE_ENABLE       0x40
+#define BF_HWECC_CTRL_BYTE_ENABLE(v)    (((v) << 6) & 0x40)
+#define BP_HWECC_CTRL_ECC_SEL           5
+#define BM_HWECC_CTRL_ECC_SEL           0x20
+#define BF_HWECC_CTRL_ECC_SEL(v)        (((v) << 5) & 0x20)
+#define BP_HWECC_CTRL_ENC_SEL           4
+#define BM_HWECC_CTRL_ENC_SEL           0x10
+#define BF_HWECC_CTRL_ENC_SEL(v)        (((v) << 4) & 0x10)
+#define BP_HWECC_CTRL_UNCORR_IRQ        2
+#define BM_HWECC_CTRL_UNCORR_IRQ        0x4
+#define BF_HWECC_CTRL_UNCORR_IRQ(v)     (((v) << 2) & 0x4)
+#define BP_HWECC_CTRL_UNCORR_IRQ_EN     1
+#define BM_HWECC_CTRL_UNCORR_IRQ_EN     0x2
+#define BF_HWECC_CTRL_UNCORR_IRQ_EN(v)  (((v) << 1) & 0x2)
+#define BP_HWECC_CTRL_RUN               0
+#define BM_HWECC_CTRL_RUN               0x1
+#define BF_HWECC_CTRL_RUN(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_HWECC_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_HWECC_STAT                   (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x10))
+#define BP_HWECC_STAT_RSDEC_PRESENT     31
+#define BM_HWECC_STAT_RSDEC_PRESENT     0x80000000
+#define BF_HWECC_STAT_RSDEC_PRESENT(v)  (((v) << 31) & 0x80000000)
+#define BP_HWECC_STAT_RSENC_PRESENT     30
+#define BM_HWECC_STAT_RSENC_PRESENT     0x40000000
+#define BF_HWECC_STAT_RSENC_PRESENT(v)  (((v) << 30) & 0x40000000)
+#define BP_HWECC_STAT_SSDEC_PRESENT     29
+#define BM_HWECC_STAT_SSDEC_PRESENT     0x20000000
+#define BF_HWECC_STAT_SSDEC_PRESENT(v)  (((v) << 29) & 0x20000000)
+#define BP_HWECC_STAT_SSENC_PRESENT     28
+#define BM_HWECC_STAT_SSENC_PRESENT     0x10000000
+#define BF_HWECC_STAT_SSENC_PRESENT(v)  (((v) << 28) & 0x10000000)
+
+/**
+ * Register: HW_HWECC_DEBUG0
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG0                         (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x20))
+#define BP_HWECC_DEBUG0_DMA_PENDCMD             29
+#define BM_HWECC_DEBUG0_DMA_PENDCMD             0x20000000
+#define BF_HWECC_DEBUG0_DMA_PENDCMD(v)          (((v) << 29) & 0x20000000)
+#define BP_HWECC_DEBUG0_DMA_PREQ                28
+#define BM_HWECC_DEBUG0_DMA_PREQ                0x10000000
+#define BF_HWECC_DEBUG0_DMA_PREQ(v)             (((v) << 28) & 0x10000000)
+#define BP_HWECC_DEBUG0_SYMBOL_STATE            24
+#define BM_HWECC_DEBUG0_SYMBOL_STATE            0xf000000
+#define BF_HWECC_DEBUG0_SYMBOL_STATE(v)         (((v) << 24) & 0xf000000)
+#define BP_HWECC_DEBUG0_CTRL_STATE              16
+#define BM_HWECC_DEBUG0_CTRL_STATE              0x3f0000
+#define BF_HWECC_DEBUG0_CTRL_STATE(v)           (((v) << 16) & 0x3f0000)
+#define BP_HWECC_DEBUG0_ECC_EXCEPTION           12
+#define BM_HWECC_DEBUG0_ECC_EXCEPTION           0xf000
+#define BF_HWECC_DEBUG0_ECC_EXCEPTION(v)        (((v) << 12) & 0xf000)
+#define BP_HWECC_DEBUG0_NUM_BIT_ERRORS          4
+#define BM_HWECC_DEBUG0_NUM_BIT_ERRORS          0x3f0
+#define BF_HWECC_DEBUG0_NUM_BIT_ERRORS(v)       (((v) << 4) & 0x3f0)
+#define BP_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0
+#define BM_HWECC_DEBUG0_NUM_SYMBOL_ERRORS       0x7
+#define BF_HWECC_DEBUG0_NUM_SYMBOL_ERRORS(v)    (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_HWECC_DEBUG1
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG1                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x30))
+#define BP_HWECC_DEBUG1_SYNDROME2       18
+#define BM_HWECC_DEBUG1_SYNDROME2       0x7fc0000
+#define BF_HWECC_DEBUG1_SYNDROME2(v)    (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG1_SYNDROME1       9
+#define BM_HWECC_DEBUG1_SYNDROME1       0x3fe00
+#define BF_HWECC_DEBUG1_SYNDROME1(v)    (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG1_SYNDROME0       0
+#define BM_HWECC_DEBUG1_SYNDROME0       0x1ff
+#define BF_HWECC_DEBUG1_SYNDROME0(v)    (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG2
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG2                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x40))
+#define BP_HWECC_DEBUG2_SYNDROME5       18
+#define BM_HWECC_DEBUG2_SYNDROME5       0x7fc0000
+#define BF_HWECC_DEBUG2_SYNDROME5(v)    (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG2_SYNDROME4       9
+#define BM_HWECC_DEBUG2_SYNDROME4       0x3fe00
+#define BF_HWECC_DEBUG2_SYNDROME4(v)    (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG2_SYNDROME3       0
+#define BM_HWECC_DEBUG2_SYNDROME3       0x1ff
+#define BF_HWECC_DEBUG2_SYNDROME3(v)    (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG3
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG3                 (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x50))
+#define BP_HWECC_DEBUG3_OMEGA0          18
+#define BM_HWECC_DEBUG3_OMEGA0          0x7fc0000
+#define BF_HWECC_DEBUG3_OMEGA0(v)       (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG3_SYNDROME7       9
+#define BM_HWECC_DEBUG3_SYNDROME7       0x3fe00
+#define BF_HWECC_DEBUG3_SYNDROME7(v)    (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG3_SYNDROME6       0
+#define BM_HWECC_DEBUG3_SYNDROME6       0x1ff
+#define BF_HWECC_DEBUG3_SYNDROME6(v)    (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG4
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG4             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x60))
+#define BP_HWECC_DEBUG4_OMEGA3      18
+#define BM_HWECC_DEBUG4_OMEGA3      0x7fc0000
+#define BF_HWECC_DEBUG4_OMEGA3(v)   (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG4_OMEGA2      9
+#define BM_HWECC_DEBUG4_OMEGA2      0x3fe00
+#define BF_HWECC_DEBUG4_OMEGA2(v)   (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG4_OMEGA1      0
+#define BM_HWECC_DEBUG4_OMEGA1      0x1ff
+#define BF_HWECC_DEBUG4_OMEGA1(v)   (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG5
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG5             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x70))
+#define BP_HWECC_DEBUG5_LAMBDA2     18
+#define BM_HWECC_DEBUG5_LAMBDA2     0x7fc0000
+#define BF_HWECC_DEBUG5_LAMBDA2(v)  (((v) << 18) & 0x7fc0000)
+#define BP_HWECC_DEBUG5_LAMBDA1     9
+#define BM_HWECC_DEBUG5_LAMBDA1     0x3fe00
+#define BF_HWECC_DEBUG5_LAMBDA1(v)  (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG5_LAMBDA0     0
+#define BM_HWECC_DEBUG5_LAMBDA0     0x1ff
+#define BF_HWECC_DEBUG5_LAMBDA0(v)  (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DEBUG6
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_HWECC_DEBUG6             (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x80))
+#define BP_HWECC_DEBUG6_LAMBDA4     9
+#define BM_HWECC_DEBUG6_LAMBDA4     0x3fe00
+#define BF_HWECC_DEBUG6_LAMBDA4(v)  (((v) << 9) & 0x3fe00)
+#define BP_HWECC_DEBUG6_LAMBDA3     0
+#define BM_HWECC_DEBUG6_LAMBDA3     0x1ff
+#define BF_HWECC_DEBUG6_LAMBDA3(v)  (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_HWECC_DATA
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_HWECC_DATA           (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x0))
+#define HW_HWECC_DATA_SET       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x4))
+#define HW_HWECC_DATA_CLR       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0x8))
+#define HW_HWECC_DATA_TOG       (*(volatile unsigned long *)(REGS_HWECC_BASE + 0x90 + 0xc))
+#define BP_HWECC_DATA_DATA      0
+#define BM_HWECC_DATA_DATA      0xffffffff
+#define BF_HWECC_DATA_DATA(v)   (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3600__HWECC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h
new file mode 100644
index 0000000000..0b3317c231
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-i2c.h
@@ -0,0 +1,521 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__I2C__H__
+#define __HEADERGEN__STMP3600__I2C__H__
+
+#define REGS_I2C_BASE (0x80058000)
+
+#define REGS_I2C_VERSION "2.3.0"
+
+/**
+ * Register: HW_I2C_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_I2C_CTRL0                                (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0))
+#define HW_I2C_CTRL0_SET                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4))
+#define HW_I2C_CTRL0_CLR                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8))
+#define HW_I2C_CTRL0_TOG                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc))
+#define BP_I2C_CTRL0_SFTRST                         31
+#define BM_I2C_CTRL0_SFTRST                         0x80000000
+#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
+#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
+#define BF_I2C_CTRL0_SFTRST(v)                      (((v) << 31) & 0x80000000)
+#define BF_I2C_CTRL0_SFTRST_V(v)                    ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000)
+#define BP_I2C_CTRL0_CLKGATE                        30
+#define BM_I2C_CTRL0_CLKGATE                        0x40000000
+#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
+#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
+#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) << 30) & 0x40000000)
+#define BF_I2C_CTRL0_CLKGATE_V(v)                   ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000)
+#define BP_I2C_CTRL0_RUN                            29
+#define BM_I2C_CTRL0_RUN                            0x20000000
+#define BV_I2C_CTRL0_RUN__HALT                      0x0
+#define BV_I2C_CTRL0_RUN__RUN                       0x1
+#define BF_I2C_CTRL0_RUN(v)                         (((v) << 29) & 0x20000000)
+#define BF_I2C_CTRL0_RUN_V(v)                       ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000)
+#define BP_I2C_CTRL0_PRE_ACK                        27
+#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
+#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) << 27) & 0x8000000)
+#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
+#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
+#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
+#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
+#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) << 26) & 0x4000000)
+#define BF_I2C_CTRL0_ACKNOWLEDGE_V(v)               ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000)
+#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) << 25) & 0x2000000)
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)          ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000)
+#define BP_I2C_CTRL0_PIO_MODE                       24
+#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
+#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) << 24) & 0x1000000)
+#define BP_I2C_CTRL0_MULTI_MASTER                   23
+#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
+#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
+#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
+#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) << 23) & 0x800000)
+#define BF_I2C_CTRL0_MULTI_MASTER_V(v)              ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000)
+#define BP_I2C_CTRL0_CLOCK_HELD                     22
+#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
+#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
+#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
+#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) << 22) & 0x400000)
+#define BF_I2C_CTRL0_CLOCK_HELD_V(v)                ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000)
+#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
+#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
+#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
+#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
+#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) << 21) & 0x200000)
+#define BF_I2C_CTRL0_RETAIN_CLOCK_V(v)              ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000)
+#define BP_I2C_CTRL0_POST_SEND_STOP                 20
+#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
+#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
+#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
+#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) << 20) & 0x100000)
+#define BF_I2C_CTRL0_POST_SEND_STOP_V(v)            ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000)
+#define BP_I2C_CTRL0_PRE_SEND_START                 19
+#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
+#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
+#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
+#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) << 19) & 0x80000)
+#define BF_I2C_CTRL0_PRE_SEND_START_V(v)            ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000)
+#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
+#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) << 18) & 0x40000)
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)      ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000)
+#define BP_I2C_CTRL0_MASTER_MODE                    17
+#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
+#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
+#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
+#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) << 17) & 0x20000)
+#define BF_I2C_CTRL0_MASTER_MODE_V(v)               ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000)
+#define BP_I2C_CTRL0_DIRECTION                      16
+#define BM_I2C_CTRL0_DIRECTION                      0x10000
+#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
+#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
+#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) << 16) & 0x10000)
+#define BF_I2C_CTRL0_DIRECTION_V(v)                 ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000)
+#define BP_I2C_CTRL0_XFER_COUNT                     0
+#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
+#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_I2C_TIMING0
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_I2C_TIMING0                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0))
+#define HW_I2C_TIMING0_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4))
+#define HW_I2C_TIMING0_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8))
+#define HW_I2C_TIMING0_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc))
+#define BP_I2C_TIMING0_HIGH_COUNT       16
+#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
+#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING0_RCV_COUNT        0
+#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
+#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_TIMING1
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_I2C_TIMING1                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0))
+#define HW_I2C_TIMING1_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4))
+#define HW_I2C_TIMING1_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8))
+#define HW_I2C_TIMING1_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc))
+#define BP_I2C_TIMING1_LOW_COUNT        16
+#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
+#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING1_XMIT_COUNT       0
+#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
+#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_TIMING2
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_I2C_TIMING2                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0))
+#define HW_I2C_TIMING2_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4))
+#define HW_I2C_TIMING2_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8))
+#define HW_I2C_TIMING2_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc))
+#define BP_I2C_TIMING2_BUS_FREE         16
+#define BM_I2C_TIMING2_BUS_FREE         0x3ff0000
+#define BF_I2C_TIMING2_BUS_FREE(v)      (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING2_LEADIN_COUNT     0
+#define BM_I2C_TIMING2_LEADIN_COUNT     0x3ff
+#define BF_I2C_TIMING2_LEADIN_COUNT(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_CTRL1
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_I2C_CTRL1                                        (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0))
+#define HW_I2C_CTRL1_SET                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4))
+#define HW_I2C_CTRL1_CLR                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8))
+#define HW_I2C_CTRL1_TOG                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc))
+#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
+#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) << 24) & 0x1000000)
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                    ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000)
+#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
+#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) << 16) & 0xff0000)
+#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
+#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) << 15) & 0x8000)
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                   ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000)
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) << 14) & 0x4000)
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)          ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000)
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) << 13) & 0x2000)
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)               ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000)
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) << 12) & 0x1000)
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)         ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000)
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) << 11) & 0x800)
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800)
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) << 10) & 0x400)
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)                ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400)
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) << 9) & 0x200)
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200)
+#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
+#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) << 8) & 0x100)
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                      ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100)
+#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
+#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) << 7) & 0x80)
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v)                      ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80)
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) << 6) & 0x40)
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)             ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40)
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) << 5) & 0x20)
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                  ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20)
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) << 4) & 0x10)
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)            ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10)
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) << 3) & 0x8)
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                    ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8)
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) << 2) & 0x4)
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                   ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4)
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) << 1) & 0x2)
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                    ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2)
+#define BP_I2C_CTRL1_SLAVE_IRQ                              0
+#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
+#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) << 0) & 0x1)
+#define BF_I2C_CTRL1_SLAVE_IRQ_V(v)                         ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_STAT
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_I2C_STAT                                             (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50))
+#define BP_I2C_STAT_MASTER_PRESENT                              31
+#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
+#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
+#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
+#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) << 31) & 0x80000000)
+#define BF_I2C_STAT_MASTER_PRESENT_V(v)                         ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000)
+#define BP_I2C_STAT_SLAVE_PRESENT                               30
+#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
+#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
+#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
+#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) << 30) & 0x40000000)
+#define BF_I2C_STAT_SLAVE_PRESENT_V(v)                          ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000)
+#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
+#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
+#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) << 29) & 0x20000000)
+#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v)                        ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000)
+#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
+#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) << 16) & 0xff0000)
+#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
+#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) << 15) & 0x8000)
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                     ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000)
+#define BP_I2C_STAT_SLAVE_FOUND                                 14
+#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
+#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
+#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
+#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) << 14) & 0x4000)
+#define BF_I2C_STAT_SLAVE_FOUND_V(v)                            ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000)
+#define BP_I2C_STAT_SLAVE_SEARCHING                             13
+#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
+#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
+#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
+#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) << 13) & 0x2000)
+#define BF_I2C_STAT_SLAVE_SEARCHING_V(v)                        ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000)
+#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
+#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) << 12) & 0x1000)
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                   ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000)
+#define BP_I2C_STAT_BUS_BUSY                                    11
+#define BM_I2C_STAT_BUS_BUSY                                    0x800
+#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
+#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
+#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) << 11) & 0x800)
+#define BF_I2C_STAT_BUS_BUSY_V(v)                               ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800)
+#define BP_I2C_STAT_CLK_GEN_BUSY                                10
+#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
+#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
+#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
+#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) << 10) & 0x400)
+#define BF_I2C_STAT_CLK_GEN_BUSY_V(v)                           ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400)
+#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
+#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
+#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) << 9) & 0x200)
+#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v)                       ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200)
+#define BP_I2C_STAT_SLAVE_BUSY                                  8
+#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
+#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
+#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
+#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) << 8) & 0x100)
+#define BF_I2C_STAT_SLAVE_BUSY_V(v)                             ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100)
+#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
+#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) << 7) & 0x80)
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                   ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80)
+#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
+#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) << 6) & 0x40)
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)          ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40)
+#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
+#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) << 5) & 0x20)
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)               ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20)
+#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
+#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) << 4) & 0x10)
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)         ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10)
+#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
+#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) << 3) & 0x8)
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8)
+#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
+#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) << 2) & 0x4)
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)                ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
+#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
+#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) << 1) & 0x2)
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2)
+#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
+#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) << 0) & 0x1)
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                      ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_DATA
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_I2C_DATA         (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60))
+#define BP_I2C_DATA_DATA    0
+#define BM_I2C_DATA_DATA    0xffffffff
+#define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_I2C_DEBUG0
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_I2C_DEBUG0                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0))
+#define HW_I2C_DEBUG0_SET               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4))
+#define HW_I2C_DEBUG0_CLR               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8))
+#define HW_I2C_DEBUG0_TOG               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc))
+#define BP_I2C_DEBUG0_DMAREQ            31
+#define BM_I2C_DEBUG0_DMAREQ            0x80000000
+#define BF_I2C_DEBUG0_DMAREQ(v)         (((v) << 31) & 0x80000000)
+#define BP_I2C_DEBUG0_DMAENDCMD         30
+#define BM_I2C_DEBUG0_DMAENDCMD         0x40000000
+#define BF_I2C_DEBUG0_DMAENDCMD(v)      (((v) << 30) & 0x40000000)
+#define BP_I2C_DEBUG0_DMAKICK           29
+#define BM_I2C_DEBUG0_DMAKICK           0x20000000
+#define BF_I2C_DEBUG0_DMAKICK(v)        (((v) << 29) & 0x20000000)
+#define BP_I2C_DEBUG0_TBD               26
+#define BM_I2C_DEBUG0_TBD               0x1c000000
+#define BF_I2C_DEBUG0_TBD(v)            (((v) << 26) & 0x1c000000)
+#define BP_I2C_DEBUG0_DMA_STATE         16
+#define BM_I2C_DEBUG0_DMA_STATE         0x3ff0000
+#define BF_I2C_DEBUG0_DMA_STATE(v)      (((v) << 16) & 0x3ff0000)
+#define BP_I2C_DEBUG0_START_TOGGLE      15
+#define BM_I2C_DEBUG0_START_TOGGLE      0x8000
+#define BF_I2C_DEBUG0_START_TOGGLE(v)   (((v) << 15) & 0x8000)
+#define BP_I2C_DEBUG0_STOP_TOGGLE       14
+#define BM_I2C_DEBUG0_STOP_TOGGLE       0x4000
+#define BF_I2C_DEBUG0_STOP_TOGGLE(v)    (((v) << 14) & 0x4000)
+#define BP_I2C_DEBUG0_GRAB_TOGGLE       13
+#define BM_I2C_DEBUG0_GRAB_TOGGLE       0x2000
+#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)    (((v) << 13) & 0x2000)
+#define BP_I2C_DEBUG0_CHANGE_TOGGLE     12
+#define BM_I2C_DEBUG0_CHANGE_TOGGLE     0x1000
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)  (((v) << 12) & 0x1000)
+#define BP_I2C_DEBUG0_TESTMODE          11
+#define BM_I2C_DEBUG0_TESTMODE          0x800
+#define BF_I2C_DEBUG0_TESTMODE(v)       (((v) << 11) & 0x800)
+#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK    10
+#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK    0x400
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400)
+#define BP_I2C_DEBUG0_SLAVE_STATE       0
+#define BM_I2C_DEBUG0_SLAVE_STATE       0x3ff
+#define BF_I2C_DEBUG0_SLAVE_STATE(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_DEBUG1
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_I2C_DEBUG1                       (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0))
+#define HW_I2C_DEBUG1_SET                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4))
+#define HW_I2C_DEBUG1_CLR                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8))
+#define HW_I2C_DEBUG1_TOG                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc))
+#define BP_I2C_DEBUG1_I2C_CLK_IN            31
+#define BM_I2C_DEBUG1_I2C_CLK_IN            0x80000000
+#define BF_I2C_DEBUG1_I2C_CLK_IN(v)         (((v) << 31) & 0x80000000)
+#define BP_I2C_DEBUG1_I2C_DATA_IN           30
+#define BM_I2C_DEBUG1_I2C_DATA_IN           0x40000000
+#define BF_I2C_DEBUG1_I2C_DATA_IN(v)        (((v) << 30) & 0x40000000)
+#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES      24
+#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES      0xf000000
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)   (((v) << 24) & 0xf000000)
+#define BP_I2C_DEBUG1_CLK_GEN_STATE         16
+#define BM_I2C_DEBUG1_CLK_GEN_STATE         0x7f0000
+#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)      (((v) << 16) & 0x7f0000)
+#define BP_I2C_DEBUG1_LST_MODE              9
+#define BM_I2C_DEBUG1_LST_MODE              0x600
+#define BV_I2C_DEBUG1_LST_MODE__BCAST       0x0
+#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE    0x1
+#define BV_I2C_DEBUG1_LST_MODE__MY_READ     0x2
+#define BV_I2C_DEBUG1_LST_MODE__NOT_ME      0x3
+#define BF_I2C_DEBUG1_LST_MODE(v)           (((v) << 9) & 0x600)
+#define BF_I2C_DEBUG1_LST_MODE_V(v)         ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600)
+#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST      8
+#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST      0x100
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)   (((v) << 8) & 0x100)
+#define BP_I2C_DEBUG1_FORCE_CLK_ON          5
+#define BM_I2C_DEBUG1_FORCE_CLK_ON          0x20
+#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)       (((v) << 5) & 0x20)
+#define BP_I2C_DEBUG1_FORCE_CLK_IDLE        4
+#define BM_I2C_DEBUG1_FORCE_CLK_IDLE        0x10
+#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v)     (((v) << 4) & 0x10)
+#define BP_I2C_DEBUG1_FORCE_ARB_LOSS        3
+#define BM_I2C_DEBUG1_FORCE_ARB_LOSS        0x8
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)     (((v) << 3) & 0x8)
+#define BP_I2C_DEBUG1_FORCE_RCV_ACK         2
+#define BM_I2C_DEBUG1_FORCE_RCV_ACK         0x4
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)      (((v) << 2) & 0x4)
+#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE     1
+#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE     0x2
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)  (((v) << 1) & 0x2)
+#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE      0
+#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE      0x1
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)   (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3600__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h
new file mode 100644
index 0000000000..130ab2ca17
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-icoll.h
@@ -0,0 +1,348 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__ICOLL__H__
+#define __HEADERGEN__STMP3600__ICOLL__H__
+
+#define REGS_ICOLL_BASE (0x80000000)
+
+#define REGS_ICOLL_VERSION "2.3.0"
+
+/**
+ * Register: HW_ICOLL_VECTOR
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_ICOLL_VECTOR                 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0))
+#define HW_ICOLL_VECTOR_SET             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4))
+#define HW_ICOLL_VECTOR_CLR             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8))
+#define HW_ICOLL_VECTOR_TOG             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc))
+#define BP_ICOLL_VECTOR_IRQVECTOR       2
+#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
+#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) << 2) & 0xfffffffc)
+
+/**
+ * Register: HW_ICOLL_LEVELACK
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_ICOLL_LEVELACK                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10))
+#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
+#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
+#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) << 0) & 0xf)
+#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v)      ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf)
+
+/**
+ * Register: HW_ICOLL_CTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_ICOLL_CTRL                                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0))
+#define HW_ICOLL_CTRL_SET                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4))
+#define HW_ICOLL_CTRL_CLR                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8))
+#define HW_ICOLL_CTRL_TOG                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc))
+#define BP_ICOLL_CTRL_SFTRST                            31
+#define BM_ICOLL_CTRL_SFTRST                            0x80000000
+#define BV_ICOLL_CTRL_SFTRST__RUN                       0x0
+#define BV_ICOLL_CTRL_SFTRST__IN_RESET                  0x1
+#define BF_ICOLL_CTRL_SFTRST(v)                         (((v) << 31) & 0x80000000)
+#define BF_ICOLL_CTRL_SFTRST_V(v)                       ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_ICOLL_CTRL_CLKGATE                           30
+#define BM_ICOLL_CTRL_CLKGATE                           0x40000000
+#define BV_ICOLL_CTRL_CLKGATE__RUN                      0x0
+#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS                0x1
+#define BF_ICOLL_CTRL_CLKGATE(v)                        (((v) << 30) & 0x40000000)
+#define BF_ICOLL_CTRL_CLKGATE_V(v)                      ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_ICOLL_CTRL_ENABLE2FIQ35                      27
+#define BM_ICOLL_CTRL_ENABLE2FIQ35                      0x8000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ35(v)                   (((v) << 27) & 0x8000000)
+#define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 27) & 0x8000000)
+#define BP_ICOLL_CTRL_ENABLE2FIQ34                      26
+#define BM_ICOLL_CTRL_ENABLE2FIQ34                      0x4000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ34(v)                   (((v) << 26) & 0x4000000)
+#define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 26) & 0x4000000)
+#define BP_ICOLL_CTRL_ENABLE2FIQ33                      25
+#define BM_ICOLL_CTRL_ENABLE2FIQ33                      0x2000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ33(v)                   (((v) << 25) & 0x2000000)
+#define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 25) & 0x2000000)
+#define BP_ICOLL_CTRL_ENABLE2FIQ32                      24
+#define BM_ICOLL_CTRL_ENABLE2FIQ32                      0x1000000
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ32(v)                   (((v) << 24) & 0x1000000)
+#define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 24) & 0x1000000)
+#define BP_ICOLL_CTRL_BYPASS_FSM                        20
+#define BM_ICOLL_CTRL_BYPASS_FSM                        0x100000
+#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL                0x0
+#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS                0x1
+#define BF_ICOLL_CTRL_BYPASS_FSM(v)                     (((v) << 20) & 0x100000)
+#define BF_ICOLL_CTRL_BYPASS_FSM_V(v)                   ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000)
+#define BP_ICOLL_CTRL_NO_NESTING                        19
+#define BM_ICOLL_CTRL_NO_NESTING                        0x80000
+#define BV_ICOLL_CTRL_NO_NESTING__NORMAL                0x0
+#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST               0x1
+#define BF_ICOLL_CTRL_NO_NESTING(v)                     (((v) << 19) & 0x80000)
+#define BF_ICOLL_CTRL_NO_NESTING_V(v)                   ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000)
+#define BP_ICOLL_CTRL_ARM_RSE_MODE                      18
+#define BM_ICOLL_CTRL_ARM_RSE_MODE                      0x40000
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE          0x0
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT    0x1
+#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)                   (((v) << 18) & 0x40000)
+#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v)                 ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000)
+#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE                  17
+#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE                  0x20000
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)               (((v) << 17) & 0x20000)
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000)
+#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE                  16
+#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE                  0x10000
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)               (((v) << 16) & 0x10000)
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000)
+
+/**
+ * Register: HW_ICOLL_STAT
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_ICOLL_STAT                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30))
+#define BP_ICOLL_STAT_VECTOR_NUMBER     0
+#define BM_ICOLL_STAT_VECTOR_NUMBER     0x3f
+#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_ICOLL_VBASE
+ * Address: 0x160
+ * SCT: yes
+*/
+#define HW_ICOLL_VBASE                  (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0))
+#define HW_ICOLL_VBASE_SET              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4))
+#define HW_ICOLL_VBASE_CLR              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8))
+#define HW_ICOLL_VBASE_TOG              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc))
+#define BP_ICOLL_VBASE_TABLE_ADDRESS    2
+#define BM_ICOLL_VBASE_TABLE_ADDRESS    0xfffffffc
+#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc)
+
+/**
+ * Register: HW_ICOLL_DEBUG
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_ICOLL_DEBUG                              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170))
+#define BP_ICOLL_DEBUG_INSERVICE                    28
+#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
+#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) << 28) & 0xf0000000)
+#define BF_ICOLL_DEBUG_INSERVICE_V(v)               ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000)
+#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
+#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) << 24) & 0xf000000)
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)          ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000)
+#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
+#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) << 20) & 0xf00000)
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)       ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000)
+#define BP_ICOLL_DEBUG_FIQ                          17
+#define BM_ICOLL_DEBUG_FIQ                          0x20000
+#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) << 17) & 0x20000)
+#define BF_ICOLL_DEBUG_FIQ_V(v)                     ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000)
+#define BP_ICOLL_DEBUG_IRQ                          16
+#define BM_ICOLL_DEBUG_IRQ                          0x10000
+#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) << 16) & 0x10000)
+#define BF_ICOLL_DEBUG_IRQ_V(v)                     ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000)
+#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
+#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
+#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) << 0) & 0x3ff)
+#define BF_ICOLL_DEBUG_VECTOR_FSM_V(v)              ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff)
+
+/**
+ * Register: HW_ICOLL_DBGFLAG
+ * Address: 0x1a0
+ * SCT: yes
+*/
+#define HW_ICOLL_DBGFLAG            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0))
+#define HW_ICOLL_DBGFLAG_SET        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4))
+#define HW_ICOLL_DBGFLAG_CLR        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8))
+#define HW_ICOLL_DBGFLAG_TOG        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc))
+#define BP_ICOLL_DBGFLAG_FLAG       0
+#define BM_ICOLL_DBGFLAG_FLAG       0xffff
+#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_ICOLL_DBGREQUESTn
+ * Address: 0x1b0+n*0x10
+ * SCT: no
+*/
+#define HW_ICOLL_DBGREQUESTn(n)         (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10))
+#define BP_ICOLL_DBGREQUESTn_BITS       0
+#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
+#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_RAWn
+ * Address: 0x40+n*0x10
+ * SCT: no
+*/
+#define HW_ICOLL_RAWn(n)            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10))
+#define BP_ICOLL_RAWn_RAW_IRQS      0
+#define BM_ICOLL_RAWn_RAW_IRQS      0xffffffff
+#define BF_ICOLL_RAWn_RAW_IRQS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_DBGREADn
+ * Address: 0x180+n*0x10
+ * SCT: no
+*/
+#define HW_ICOLL_DBGREADn(n)        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180+(n)*0x10))
+#define BP_ICOLL_DBGREADn_VALUE     0
+#define BM_ICOLL_DBGREADn_VALUE     0xffffffff
+#define BF_ICOLL_DBGREADn_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_PRIORITYn
+ * Address: 0x60+n*0x10
+ * SCT: yes
+*/
+#define HW_ICOLL_PRIORITYn(n)                           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0))
+#define HW_ICOLL_PRIORITYn_SET(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4))
+#define HW_ICOLL_PRIORITYn_CLR(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8))
+#define HW_ICOLL_PRIORITYn_TOG(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc))
+#define BP_ICOLL_PRIORITYn_SOFTIRQ3                     27
+#define BM_ICOLL_PRIORITYn_SOFTIRQ3                     0x8000000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3(v)                  (((v) << 27) & 0x8000000)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000)
+#define BP_ICOLL_PRIORITYn_ENABLE3                      26
+#define BM_ICOLL_PRIORITYn_ENABLE3                      0x4000000
+#define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE3(v)                   (((v) << 26) & 0x4000000)
+#define BF_ICOLL_PRIORITYn_ENABLE3_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000)
+#define BP_ICOLL_PRIORITYn_PRIORITY3                    24
+#define BM_ICOLL_PRIORITYn_PRIORITY3                    0x3000000
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY3(v)                 (((v) << 24) & 0x3000000)
+#define BF_ICOLL_PRIORITYn_PRIORITY3_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ2                     19
+#define BM_ICOLL_PRIORITYn_SOFTIRQ2                     0x80000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2(v)                  (((v) << 19) & 0x80000)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000)
+#define BP_ICOLL_PRIORITYn_ENABLE2                      18
+#define BM_ICOLL_PRIORITYn_ENABLE2                      0x40000
+#define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE2(v)                   (((v) << 18) & 0x40000)
+#define BF_ICOLL_PRIORITYn_ENABLE2_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000)
+#define BP_ICOLL_PRIORITYn_PRIORITY2                    16
+#define BM_ICOLL_PRIORITYn_PRIORITY2                    0x30000
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY2(v)                 (((v) << 16) & 0x30000)
+#define BF_ICOLL_PRIORITYn_PRIORITY2_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ1                     11
+#define BM_ICOLL_PRIORITYn_SOFTIRQ1                     0x800
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1(v)                  (((v) << 11) & 0x800)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800)
+#define BP_ICOLL_PRIORITYn_ENABLE1                      10
+#define BM_ICOLL_PRIORITYn_ENABLE1                      0x400
+#define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE1(v)                   (((v) << 10) & 0x400)
+#define BF_ICOLL_PRIORITYn_ENABLE1_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400)
+#define BP_ICOLL_PRIORITYn_PRIORITY1                    8
+#define BM_ICOLL_PRIORITYn_PRIORITY1                    0x300
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY1(v)                 (((v) << 8) & 0x300)
+#define BF_ICOLL_PRIORITYn_PRIORITY1_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ0                     3
+#define BM_ICOLL_PRIORITYn_SOFTIRQ0                     0x8
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0(v)                  (((v) << 3) & 0x8)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8)
+#define BP_ICOLL_PRIORITYn_ENABLE0                      2
+#define BM_ICOLL_PRIORITYn_ENABLE0                      0x4
+#define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE0(v)                   (((v) << 2) & 0x4)
+#define BF_ICOLL_PRIORITYn_ENABLE0_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4)
+#define BP_ICOLL_PRIORITYn_PRIORITY0                    0
+#define BM_ICOLL_PRIORITYn_PRIORITY0                    0x3
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY0(v)                 (((v) << 0) & 0x3)
+#define BF_ICOLL_PRIORITYn_PRIORITY0_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3)
+
+#endif /* __HEADERGEN__STMP3600__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h
new file mode 100644
index 0000000000..56eeabaaa3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-ir.h
@@ -0,0 +1,477 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__IR__H__
+#define __HEADERGEN__STMP3600__IR__H__
+
+#define REGS_IR_BASE (0x80078000)
+
+#define REGS_IR_VERSION "2.3.0"
+
+/**
+ * Register: HW_IR_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_IR_CTRL                  (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0))
+#define HW_IR_CTRL_SET              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4))
+#define HW_IR_CTRL_CLR              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8))
+#define HW_IR_CTRL_TOG              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc))
+#define BP_IR_CTRL_SFTRST           31
+#define BM_IR_CTRL_SFTRST           0x80000000
+#define BV_IR_CTRL_SFTRST__RUN      0x0
+#define BV_IR_CTRL_SFTRST__RESET    0x1
+#define BF_IR_CTRL_SFTRST(v)        (((v) << 31) & 0x80000000)
+#define BF_IR_CTRL_SFTRST_V(v)      ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_IR_CTRL_CLKGATE          30
+#define BM_IR_CTRL_CLKGATE          0x40000000
+#define BF_IR_CTRL_CLKGATE(v)       (((v) << 30) & 0x40000000)
+#define BP_IR_CTRL_MTA              24
+#define BM_IR_CTRL_MTA              0x7000000
+#define BV_IR_CTRL_MTA__MTA_10MS    0x0
+#define BV_IR_CTRL_MTA__MTA_5MS     0x1
+#define BV_IR_CTRL_MTA__MTA_1MS     0x2
+#define BV_IR_CTRL_MTA__MTA_500US   0x3
+#define BV_IR_CTRL_MTA__MTA_100US   0x4
+#define BV_IR_CTRL_MTA__MTA_50US    0x5
+#define BV_IR_CTRL_MTA__MTA_10US    0x6
+#define BV_IR_CTRL_MTA__MTA_0       0x7
+#define BF_IR_CTRL_MTA(v)           (((v) << 24) & 0x7000000)
+#define BF_IR_CTRL_MTA_V(v)         ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000)
+#define BP_IR_CTRL_MODE             22
+#define BM_IR_CTRL_MODE             0xc00000
+#define BV_IR_CTRL_MODE__SIR        0x0
+#define BV_IR_CTRL_MODE__MIR        0x1
+#define BV_IR_CTRL_MODE__FIR        0x2
+#define BV_IR_CTRL_MODE__VFIR       0x3
+#define BF_IR_CTRL_MODE(v)          (((v) << 22) & 0xc00000)
+#define BF_IR_CTRL_MODE_V(v)        ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000)
+#define BP_IR_CTRL_SPEED            19
+#define BM_IR_CTRL_SPEED            0x380000
+#define BV_IR_CTRL_SPEED__SPD000    0x0
+#define BV_IR_CTRL_SPEED__SPD001    0x1
+#define BV_IR_CTRL_SPEED__SPD010    0x2
+#define BV_IR_CTRL_SPEED__SPD011    0x3
+#define BV_IR_CTRL_SPEED__SPD100    0x4
+#define BV_IR_CTRL_SPEED__SPD101    0x5
+#define BF_IR_CTRL_SPEED(v)         (((v) << 19) & 0x380000)
+#define BF_IR_CTRL_SPEED_V(v)       ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000)
+#define BP_IR_CTRL_TC_TIME_DIV      8
+#define BM_IR_CTRL_TC_TIME_DIV      0x3f00
+#define BF_IR_CTRL_TC_TIME_DIV(v)   (((v) << 8) & 0x3f00)
+#define BP_IR_CTRL_TC_TYPE          7
+#define BM_IR_CTRL_TC_TYPE          0x80
+#define BF_IR_CTRL_TC_TYPE(v)       (((v) << 7) & 0x80)
+#define BP_IR_CTRL_SIR_GAP          4
+#define BM_IR_CTRL_SIR_GAP          0x70
+#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
+#define BV_IR_CTRL_SIR_GAP__GAP_5K  0x1
+#define BV_IR_CTRL_SIR_GAP__GAP_1K  0x2
+#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
+#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
+#define BV_IR_CTRL_SIR_GAP__GAP_50  0x5
+#define BV_IR_CTRL_SIR_GAP__GAP_10  0x6
+#define BV_IR_CTRL_SIR_GAP__GAP_0   0x7
+#define BF_IR_CTRL_SIR_GAP(v)       (((v) << 4) & 0x70)
+#define BF_IR_CTRL_SIR_GAP_V(v)     ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70)
+#define BP_IR_CTRL_SIPEN            3
+#define BM_IR_CTRL_SIPEN            0x8
+#define BF_IR_CTRL_SIPEN(v)         (((v) << 3) & 0x8)
+#define BP_IR_CTRL_TCEN             2
+#define BM_IR_CTRL_TCEN             0x4
+#define BF_IR_CTRL_TCEN(v)          (((v) << 2) & 0x4)
+#define BP_IR_CTRL_TXEN             1
+#define BM_IR_CTRL_TXEN             0x2
+#define BF_IR_CTRL_TXEN(v)          (((v) << 1) & 0x2)
+#define BP_IR_CTRL_RXEN             0
+#define BM_IR_CTRL_RXEN             0x1
+#define BF_IR_CTRL_RXEN(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_TXDMA
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_IR_TXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0))
+#define HW_IR_TXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4))
+#define HW_IR_TXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8))
+#define HW_IR_TXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc))
+#define BP_IR_TXDMA_RUN             31
+#define BM_IR_TXDMA_RUN             0x80000000
+#define BF_IR_TXDMA_RUN(v)          (((v) << 31) & 0x80000000)
+#define BP_IR_TXDMA_EMPTY           29
+#define BM_IR_TXDMA_EMPTY           0x20000000
+#define BF_IR_TXDMA_EMPTY(v)        (((v) << 29) & 0x20000000)
+#define BP_IR_TXDMA_INT             28
+#define BM_IR_TXDMA_INT             0x10000000
+#define BF_IR_TXDMA_INT(v)          (((v) << 28) & 0x10000000)
+#define BP_IR_TXDMA_CHANGE          27
+#define BM_IR_TXDMA_CHANGE          0x8000000
+#define BF_IR_TXDMA_CHANGE(v)       (((v) << 27) & 0x8000000)
+#define BP_IR_TXDMA_NEW_MTA         24
+#define BM_IR_TXDMA_NEW_MTA         0x7000000
+#define BF_IR_TXDMA_NEW_MTA(v)      (((v) << 24) & 0x7000000)
+#define BP_IR_TXDMA_NEW_MODE        22
+#define BM_IR_TXDMA_NEW_MODE        0xc00000
+#define BF_IR_TXDMA_NEW_MODE(v)     (((v) << 22) & 0xc00000)
+#define BP_IR_TXDMA_NEW_SPEED       19
+#define BM_IR_TXDMA_NEW_SPEED       0x380000
+#define BF_IR_TXDMA_NEW_SPEED(v)    (((v) << 19) & 0x380000)
+#define BP_IR_TXDMA_BOF_TYPE        18
+#define BM_IR_TXDMA_BOF_TYPE        0x40000
+#define BF_IR_TXDMA_BOF_TYPE(v)     (((v) << 18) & 0x40000)
+#define BP_IR_TXDMA_XBOFS           12
+#define BM_IR_TXDMA_XBOFS           0x3f000
+#define BF_IR_TXDMA_XBOFS(v)        (((v) << 12) & 0x3f000)
+#define BP_IR_TXDMA_XFER_COUNT      0
+#define BM_IR_TXDMA_XFER_COUNT      0xfff
+#define BF_IR_TXDMA_XFER_COUNT(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_IR_RXDMA
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_IR_RXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0))
+#define HW_IR_RXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4))
+#define HW_IR_RXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8))
+#define HW_IR_RXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc))
+#define BP_IR_RXDMA_RUN             31
+#define BM_IR_RXDMA_RUN             0x80000000
+#define BF_IR_RXDMA_RUN(v)          (((v) << 31) & 0x80000000)
+#define BP_IR_RXDMA_XFER_COUNT      0
+#define BM_IR_RXDMA_XFER_COUNT      0x3ff
+#define BF_IR_RXDMA_XFER_COUNT(v)   (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_IR_DBGCTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_IR_DBGCTRL                   (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0))
+#define HW_IR_DBGCTRL_SET               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4))
+#define HW_IR_DBGCTRL_CLR               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8))
+#define HW_IR_DBGCTRL_TOG               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc))
+#define BP_IR_DBGCTRL_VFIRSWZ           12
+#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
+#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
+#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
+#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) << 12) & 0x1000)
+#define BF_IR_DBGCTRL_VFIRSWZ_V(v)      ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000)
+#define BP_IR_DBGCTRL_RXFRMOFF          11
+#define BM_IR_DBGCTRL_RXFRMOFF          0x800
+#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) << 11) & 0x800)
+#define BP_IR_DBGCTRL_RXCRCOFF          10
+#define BM_IR_DBGCTRL_RXCRCOFF          0x400
+#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) << 10) & 0x400)
+#define BP_IR_DBGCTRL_RXINVERT          9
+#define BM_IR_DBGCTRL_RXINVERT          0x200
+#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) << 9) & 0x200)
+#define BP_IR_DBGCTRL_TXFRMOFF          8
+#define BM_IR_DBGCTRL_TXFRMOFF          0x100
+#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) << 8) & 0x100)
+#define BP_IR_DBGCTRL_TXCRCOFF          7
+#define BM_IR_DBGCTRL_TXCRCOFF          0x80
+#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) << 7) & 0x80)
+#define BP_IR_DBGCTRL_TXINVERT          6
+#define BM_IR_DBGCTRL_TXINVERT          0x40
+#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) << 6) & 0x40)
+#define BP_IR_DBGCTRL_INTLOOPBACK       5
+#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
+#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) << 5) & 0x20)
+#define BP_IR_DBGCTRL_DUPLEX            4
+#define BM_IR_DBGCTRL_DUPLEX            0x10
+#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) << 4) & 0x10)
+#define BP_IR_DBGCTRL_MIO_RX            3
+#define BM_IR_DBGCTRL_MIO_RX            0x8
+#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) << 3) & 0x8)
+#define BP_IR_DBGCTRL_MIO_TX            2
+#define BM_IR_DBGCTRL_MIO_TX            0x4
+#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) << 2) & 0x4)
+#define BP_IR_DBGCTRL_MIO_SCLK          1
+#define BM_IR_DBGCTRL_MIO_SCLK          0x2
+#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) << 1) & 0x2)
+#define BP_IR_DBGCTRL_MIO_EN            0
+#define BM_IR_DBGCTRL_MIO_EN            0x1
+#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_INTR
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_IR_INTR                          (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0))
+#define HW_IR_INTR_SET                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4))
+#define HW_IR_INTR_CLR                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8))
+#define HW_IR_INTR_TOG                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc))
+#define BP_IR_INTR_RXABORT_IRQ_EN           22
+#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
+#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
+#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
+#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) << 22) & 0x400000)
+#define BF_IR_INTR_RXABORT_IRQ_EN_V(v)      ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000)
+#define BP_IR_INTR_SPEED_IRQ_EN             21
+#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
+#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
+#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
+#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) << 21) & 0x200000)
+#define BF_IR_INTR_SPEED_IRQ_EN_V(v)        ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000)
+#define BP_IR_INTR_RXOF_IRQ_EN              20
+#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
+#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) << 20) & 0x100000)
+#define BF_IR_INTR_RXOF_IRQ_EN_V(v)         ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000)
+#define BP_IR_INTR_TXUF_IRQ_EN              19
+#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
+#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) << 19) & 0x80000)
+#define BF_IR_INTR_TXUF_IRQ_EN_V(v)         ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000)
+#define BP_IR_INTR_TC_IRQ_EN                18
+#define BM_IR_INTR_TC_IRQ_EN                0x40000
+#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) << 18) & 0x40000)
+#define BF_IR_INTR_TC_IRQ_EN_V(v)           ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000)
+#define BP_IR_INTR_RX_IRQ_EN                17
+#define BM_IR_INTR_RX_IRQ_EN                0x20000
+#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) << 17) & 0x20000)
+#define BF_IR_INTR_RX_IRQ_EN_V(v)           ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000)
+#define BP_IR_INTR_TX_IRQ_EN                16
+#define BM_IR_INTR_TX_IRQ_EN                0x10000
+#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) << 16) & 0x10000)
+#define BF_IR_INTR_TX_IRQ_EN_V(v)           ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000)
+#define BP_IR_INTR_RXABORT_IRQ              6
+#define BM_IR_INTR_RXABORT_IRQ              0x40
+#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
+#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
+#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) << 6) & 0x40)
+#define BF_IR_INTR_RXABORT_IRQ_V(v)         ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40)
+#define BP_IR_INTR_SPEED_IRQ                5
+#define BM_IR_INTR_SPEED_IRQ                0x20
+#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
+#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
+#define BF_IR_INTR_SPEED_IRQ(v)             (((v) << 5) & 0x20)
+#define BF_IR_INTR_SPEED_IRQ_V(v)           ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20)
+#define BP_IR_INTR_RXOF_IRQ                 4
+#define BM_IR_INTR_RXOF_IRQ                 0x10
+#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_RXOF_IRQ(v)              (((v) << 4) & 0x10)
+#define BF_IR_INTR_RXOF_IRQ_V(v)            ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10)
+#define BP_IR_INTR_TXUF_IRQ                 3
+#define BM_IR_INTR_TXUF_IRQ                 0x8
+#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_TXUF_IRQ(v)              (((v) << 3) & 0x8)
+#define BF_IR_INTR_TXUF_IRQ_V(v)            ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8)
+#define BP_IR_INTR_TC_IRQ                   2
+#define BM_IR_INTR_TC_IRQ                   0x4
+#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TC_IRQ(v)                (((v) << 2) & 0x4)
+#define BF_IR_INTR_TC_IRQ_V(v)              ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4)
+#define BP_IR_INTR_RX_IRQ                   1
+#define BM_IR_INTR_RX_IRQ                   0x2
+#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_RX_IRQ(v)                (((v) << 1) & 0x2)
+#define BF_IR_INTR_RX_IRQ_V(v)              ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2)
+#define BP_IR_INTR_TX_IRQ                   0
+#define BM_IR_INTR_TX_IRQ                   0x1
+#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TX_IRQ(v)                (((v) << 0) & 0x1)
+#define BF_IR_INTR_TX_IRQ_V(v)              ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_IR_DATA
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_IR_DATA          (*(volatile unsigned long *)(REGS_IR_BASE + 0x50))
+#define BP_IR_DATA_DATA     0
+#define BM_IR_DATA_DATA     0xffffffff
+#define BF_IR_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_IR_STAT
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_IR_STAT                              (*(volatile unsigned long *)(REGS_IR_BASE + 0x60))
+#define BP_IR_STAT_PRESENT                      31
+#define BM_IR_STAT_PRESENT                      0x80000000
+#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
+#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
+#define BF_IR_STAT_PRESENT(v)                   (((v) << 31) & 0x80000000)
+#define BF_IR_STAT_PRESENT_V(v)                 ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_IR_STAT_MODE_ALLOWED                 29
+#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
+#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
+#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
+#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
+#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
+#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) << 29) & 0x60000000)
+#define BF_IR_STAT_MODE_ALLOWED_V(v)            ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000)
+#define BP_IR_STAT_ANY_IRQ                      28
+#define BM_IR_STAT_ANY_IRQ                      0x10000000
+#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
+#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
+#define BF_IR_STAT_ANY_IRQ(v)                   (((v) << 28) & 0x10000000)
+#define BF_IR_STAT_ANY_IRQ_V(v)                 ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000)
+#define BP_IR_STAT_RXABORT_SUMMARY              22
+#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
+#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
+#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
+#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) << 22) & 0x400000)
+#define BF_IR_STAT_RXABORT_SUMMARY_V(v)         ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000)
+#define BP_IR_STAT_SPEED_SUMMARY                21
+#define BM_IR_STAT_SPEED_SUMMARY                0x200000
+#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
+#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
+#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) << 21) & 0x200000)
+#define BF_IR_STAT_SPEED_SUMMARY_V(v)           ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000)
+#define BP_IR_STAT_RXOF_SUMMARY                 20
+#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
+#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) << 20) & 0x100000)
+#define BF_IR_STAT_RXOF_SUMMARY_V(v)            ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000)
+#define BP_IR_STAT_TXUF_SUMMARY                 19
+#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
+#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) << 19) & 0x80000)
+#define BF_IR_STAT_TXUF_SUMMARY_V(v)            ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000)
+#define BP_IR_STAT_TC_SUMMARY                   18
+#define BM_IR_STAT_TC_SUMMARY                   0x40000
+#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TC_SUMMARY(v)                (((v) << 18) & 0x40000)
+#define BF_IR_STAT_TC_SUMMARY_V(v)              ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000)
+#define BP_IR_STAT_RX_SUMMARY                   17
+#define BM_IR_STAT_RX_SUMMARY                   0x20000
+#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_RX_SUMMARY(v)                (((v) << 17) & 0x20000)
+#define BF_IR_STAT_RX_SUMMARY_V(v)              ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000)
+#define BP_IR_STAT_TX_SUMMARY                   16
+#define BM_IR_STAT_TX_SUMMARY                   0x10000
+#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TX_SUMMARY(v)                (((v) << 16) & 0x10000)
+#define BF_IR_STAT_TX_SUMMARY_V(v)              ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000)
+#define BP_IR_STAT_MEDIA_BUSY                   2
+#define BM_IR_STAT_MEDIA_BUSY                   0x4
+#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) << 2) & 0x4)
+#define BP_IR_STAT_RX_ACTIVE                    1
+#define BM_IR_STAT_RX_ACTIVE                    0x2
+#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) << 1) & 0x2)
+#define BP_IR_STAT_TX_ACTIVE                    0
+#define BM_IR_STAT_TX_ACTIVE                    0x1
+#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_TCCTRL
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_IR_TCCTRL                (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0))
+#define HW_IR_TCCTRL_SET            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4))
+#define HW_IR_TCCTRL_CLR            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8))
+#define HW_IR_TCCTRL_TOG            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc))
+#define BP_IR_TCCTRL_INIT           31
+#define BM_IR_TCCTRL_INIT           0x80000000
+#define BF_IR_TCCTRL_INIT(v)        (((v) << 31) & 0x80000000)
+#define BP_IR_TCCTRL_GO             30
+#define BM_IR_TCCTRL_GO             0x40000000
+#define BF_IR_TCCTRL_GO(v)          (((v) << 30) & 0x40000000)
+#define BP_IR_TCCTRL_BUSY           29
+#define BM_IR_TCCTRL_BUSY           0x20000000
+#define BF_IR_TCCTRL_BUSY(v)        (((v) << 29) & 0x20000000)
+#define BP_IR_TCCTRL_TEMIC          24
+#define BM_IR_TCCTRL_TEMIC          0x1000000
+#define BV_IR_TCCTRL_TEMIC__LOW     0x0
+#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
+#define BF_IR_TCCTRL_TEMIC(v)       (((v) << 24) & 0x1000000)
+#define BF_IR_TCCTRL_TEMIC_V(v)     ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000)
+#define BP_IR_TCCTRL_EXT_DATA       16
+#define BM_IR_TCCTRL_EXT_DATA       0xff0000
+#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) << 16) & 0xff0000)
+#define BP_IR_TCCTRL_DATA           8
+#define BM_IR_TCCTRL_DATA           0xff00
+#define BF_IR_TCCTRL_DATA(v)        (((v) << 8) & 0xff00)
+#define BP_IR_TCCTRL_ADDR           5
+#define BM_IR_TCCTRL_ADDR           0xe0
+#define BF_IR_TCCTRL_ADDR(v)        (((v) << 5) & 0xe0)
+#define BP_IR_TCCTRL_INDX           1
+#define BM_IR_TCCTRL_INDX           0x1e
+#define BF_IR_TCCTRL_INDX(v)        (((v) << 1) & 0x1e)
+#define BP_IR_TCCTRL_C              0
+#define BM_IR_TCCTRL_C              0x1
+#define BF_IR_TCCTRL_C(v)           (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_SI_READ
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_IR_SI_READ           (*(volatile unsigned long *)(REGS_IR_BASE + 0x80))
+#define BP_IR_SI_READ_ABORT     8
+#define BM_IR_SI_READ_ABORT     0x100
+#define BF_IR_SI_READ_ABORT(v)  (((v) << 8) & 0x100)
+#define BP_IR_SI_READ_DATA      0
+#define BM_IR_SI_READ_DATA      0xff
+#define BF_IR_SI_READ_DATA(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_IR_DEBUG
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_IR_DEBUG                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x90))
+#define BP_IR_DEBUG_TXDMAKICK       5
+#define BM_IR_DEBUG_TXDMAKICK       0x20
+#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) << 5) & 0x20)
+#define BP_IR_DEBUG_RXDMAKICK       4
+#define BM_IR_DEBUG_RXDMAKICK       0x10
+#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) << 4) & 0x10)
+#define BP_IR_DEBUG_TXDMAEND        3
+#define BM_IR_DEBUG_TXDMAEND        0x8
+#define BF_IR_DEBUG_TXDMAEND(v)     (((v) << 3) & 0x8)
+#define BP_IR_DEBUG_RXDMAEND        2
+#define BM_IR_DEBUG_RXDMAEND        0x4
+#define BF_IR_DEBUG_RXDMAEND(v)     (((v) << 2) & 0x4)
+#define BP_IR_DEBUG_TXDMAREQ        1
+#define BM_IR_DEBUG_TXDMAREQ        0x2
+#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) << 1) & 0x2)
+#define BP_IR_DEBUG_RXDMAREQ        0
+#define BM_IR_DEBUG_RXDMAREQ        0x1
+#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3600__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h
new file mode 100644
index 0000000000..24b17d5905
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-lcdif.h
@@ -0,0 +1,167 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__LCDIF__H__
+#define __HEADERGEN__STMP3600__LCDIF__H__
+
+#define REGS_LCDIF_BASE (0x80060000)
+
+#define REGS_LCDIF_VERSION "2.3.0"
+
+/**
+ * Register: HW_LCDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
+#define HW_LCDIF_CTRL_SET                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
+#define HW_LCDIF_CTRL_CLR                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
+#define HW_LCDIF_CTRL_TOG                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
+#define BP_LCDIF_CTRL_SFTRST                        31
+#define BM_LCDIF_CTRL_SFTRST                        0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                     (((v) << 31) & 0x80000000)
+#define BP_LCDIF_CTRL_CLKGATE                       30
+#define BM_LCDIF_CTRL_CLKGATE                       0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
+#define BP_LCDIF_CTRL_PRESENT                       29
+#define BM_LCDIF_CTRL_PRESENT                       0x20000000
+#define BF_LCDIF_CTRL_PRESENT(v)                    (((v) << 29) & 0x20000000)
+#define BP_LCDIF_CTRL_BUSY_ENABLE                   25
+#define BM_LCDIF_CTRL_BUSY_ENABLE                   0x2000000
+#define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_DISABLED    0x0
+#define BV_LCDIF_CTRL_BUSY_ENABLE__BUSY_ENABLED     0x1
+#define BF_LCDIF_CTRL_BUSY_ENABLE(v)                (((v) << 25) & 0x2000000)
+#define BF_LCDIF_CTRL_BUSY_ENABLE_V(v)              ((BV_LCDIF_CTRL_BUSY_ENABLE__##v << 25) & 0x2000000)
+#define BP_LCDIF_CTRL_FIFO_STATUS                   24
+#define BM_LCDIF_CTRL_FIFO_STATUS                   0x1000000
+#define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_FULL        0x0
+#define BV_LCDIF_CTRL_FIFO_STATUS__FIFO_OK          0x1
+#define BF_LCDIF_CTRL_FIFO_STATUS(v)                (((v) << 24) & 0x1000000)
+#define BF_LCDIF_CTRL_FIFO_STATUS_V(v)              ((BV_LCDIF_CTRL_FIFO_STATUS__##v << 24) & 0x1000000)
+#define BP_LCDIF_CTRL_DMA_REQ                       23
+#define BM_LCDIF_CTRL_DMA_REQ                       0x800000
+#define BF_LCDIF_CTRL_DMA_REQ(v)                    (((v) << 23) & 0x800000)
+#define BP_LCDIF_CTRL_DATA_SWIZZLE                  21
+#define BM_LCDIF_CTRL_DATA_SWIZZLE                  0x600000
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP         0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN   0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES  0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP        0x2
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP   0x3
+#define BF_LCDIF_CTRL_DATA_SWIZZLE(v)               (((v) << 21) & 0x600000)
+#define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v)             ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000)
+#define BP_LCDIF_CTRL_RESET                         20
+#define BM_LCDIF_CTRL_RESET                         0x100000
+#define BV_LCDIF_CTRL_RESET__LCDRESET_LOW           0x0
+#define BV_LCDIF_CTRL_RESET__LCDRESET_HIGH          0x1
+#define BF_LCDIF_CTRL_RESET(v)                      (((v) << 20) & 0x100000)
+#define BF_LCDIF_CTRL_RESET_V(v)                    ((BV_LCDIF_CTRL_RESET__##v << 20) & 0x100000)
+#define BP_LCDIF_CTRL_MODE86                        19
+#define BM_LCDIF_CTRL_MODE86                        0x80000
+#define BV_LCDIF_CTRL_MODE86__8080_MODE             0x0
+#define BV_LCDIF_CTRL_MODE86__6800_MODE             0x1
+#define BF_LCDIF_CTRL_MODE86(v)                     (((v) << 19) & 0x80000)
+#define BF_LCDIF_CTRL_MODE86_V(v)                   ((BV_LCDIF_CTRL_MODE86__##v << 19) & 0x80000)
+#define BP_LCDIF_CTRL_DATA_SELECT                   18
+#define BM_LCDIF_CTRL_DATA_SELECT                   0x40000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE         0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE        0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                (((v) << 18) & 0x40000)
+#define BF_LCDIF_CTRL_DATA_SELECT_V(v)              ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000)
+#define BP_LCDIF_CTRL_WORD_LENGTH                   17
+#define BM_LCDIF_CTRL_WORD_LENGTH                   0x20000
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT           0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT            0x1
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                (((v) << 17) & 0x20000)
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)              ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000)
+#define BP_LCDIF_CTRL_RUN                           16
+#define BM_LCDIF_CTRL_RUN                           0x10000
+#define BF_LCDIF_CTRL_RUN(v)                        (((v) << 16) & 0x10000)
+#define BP_LCDIF_CTRL_COUNT                         0
+#define BM_LCDIF_CTRL_COUNT                         0xffff
+#define BF_LCDIF_CTRL_COUNT(v)                      (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_TIMING
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10))
+#define BP_LCDIF_TIMING_CMD_HOLD        24
+#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
+#define BP_LCDIF_TIMING_CMD_SETUP       16
+#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_LCDIF_TIMING_DATA_HOLD       8
+#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_LCDIF_TIMING_DATA_SETUP      0
+#define BM_LCDIF_TIMING_DATA_SETUP      0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_DATA
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
+#define BP_LCDIF_DATA_DATA_THREE    24
+#define BM_LCDIF_DATA_DATA_THREE    0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
+#define BP_LCDIF_DATA_DATA_TWO      16
+#define BM_LCDIF_DATA_DATA_TWO      0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_DATA_DATA_ONE      8
+#define BM_LCDIF_DATA_DATA_ONE      0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
+#define BP_LCDIF_DATA_DATA_ZERO     0
+#define BM_LCDIF_DATA_DATA_ZERO     0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_DEBUG
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_LCDIF_DEBUG                      (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30))
+#define BP_LCDIF_DEBUG_BUSY                 27
+#define BM_LCDIF_DEBUG_BUSY                 0x8000000
+#define BF_LCDIF_DEBUG_BUSY(v)              (((v) << 27) & 0x8000000)
+#define BP_LCDIF_DEBUG_LAST_SUBWORD         26
+#define BM_LCDIF_DEBUG_LAST_SUBWORD         0x4000000
+#define BF_LCDIF_DEBUG_LAST_SUBWORD(v)      (((v) << 26) & 0x4000000)
+#define BP_LCDIF_DEBUG_SUBWORD_POSITION     24
+#define BM_LCDIF_DEBUG_SUBWORD_POSITION     0x3000000
+#define BF_LCDIF_DEBUG_SUBWORD_POSITION(v)  (((v) << 24) & 0x3000000)
+#define BP_LCDIF_DEBUG_EMPTY_WORD           23
+#define BM_LCDIF_DEBUG_EMPTY_WORD           0x800000
+#define BF_LCDIF_DEBUG_EMPTY_WORD(v)        (((v) << 23) & 0x800000)
+#define BP_LCDIF_DEBUG_STATE                16
+#define BM_LCDIF_DEBUG_STATE                0x7f0000
+#define BF_LCDIF_DEBUG_STATE(v)             (((v) << 16) & 0x7f0000)
+#define BP_LCDIF_DEBUG_DATA_COUNT           0
+#define BM_LCDIF_DEBUG_DATA_COUNT           0xffff
+#define BF_LCDIF_DEBUG_DATA_COUNT(v)        (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3600__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h
new file mode 100644
index 0000000000..c799635306
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-lradc.h
@@ -0,0 +1,572 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__LRADC__H__
+#define __HEADERGEN__STMP3600__LRADC__H__
+
+#define REGS_LRADC_BASE (0x80050000)
+
+#define REGS_LRADC_VERSION "2.3.0"
+
+/**
+ * Register: HW_LRADC_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL0                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0))
+#define HW_LRADC_CTRL0_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4))
+#define HW_LRADC_CTRL0_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8))
+#define HW_LRADC_CTRL0_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc))
+#define BP_LRADC_CTRL0_SFTRST                   31
+#define BM_LRADC_CTRL0_SFTRST                   0x80000000
+#define BF_LRADC_CTRL0_SFTRST(v)                (((v) << 31) & 0x80000000)
+#define BP_LRADC_CTRL0_CLKGATE                  30
+#define BM_LRADC_CTRL0_CLKGATE                  0x40000000
+#define BF_LRADC_CTRL0_CLKGATE(v)               (((v) << 30) & 0x40000000)
+#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF         21
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF         0x200000
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF    0x0
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON     0x1
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)      (((v) << 21) & 0x200000)
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)    ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000)
+#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE      20
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x100000
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON  0x1
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)   (((v) << 20) & 0x100000)
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000)
+#define BP_LRADC_CTRL0_YMINUS_ENABLE            19
+#define BM_LRADC_CTRL0_YMINUS_ENABLE            0x80000
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF       0x0
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON        0x1
+#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)         (((v) << 19) & 0x80000)
+#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000)
+#define BP_LRADC_CTRL0_XMINUS_ENABLE            18
+#define BM_LRADC_CTRL0_XMINUS_ENABLE            0x40000
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF       0x0
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON        0x1
+#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)         (((v) << 18) & 0x40000)
+#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000)
+#define BP_LRADC_CTRL0_YPLUS_ENABLE             17
+#define BM_LRADC_CTRL0_YPLUS_ENABLE             0x20000
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF        0x0
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON         0x1
+#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)          (((v) << 17) & 0x20000)
+#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000)
+#define BP_LRADC_CTRL0_XPLUS_ENABLE             16
+#define BM_LRADC_CTRL0_XPLUS_ENABLE             0x10000
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF        0x0
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON         0x1
+#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)          (((v) << 16) & 0x10000)
+#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000)
+#define BP_LRADC_CTRL0_SCHEDULE                 0
+#define BM_LRADC_CTRL0_SCHEDULE                 0xff
+#define BF_LRADC_CTRL0_SCHEDULE(v)              (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LRADC_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL1                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0))
+#define HW_LRADC_CTRL1_SET                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4))
+#define HW_LRADC_CTRL1_CLR                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8))
+#define HW_LRADC_CTRL1_TOG                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc))
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) << 24) & 0x1000000)
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)     ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000)
+#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
+#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
+#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) << 22) & 0x400000)
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000)
+#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) << 21) & 0x200000)
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000)
+#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
+#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) << 20) & 0x100000)
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000)
+#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
+#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) << 19) & 0x80000)
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000)
+#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
+#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) << 18) & 0x40000)
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000)
+#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
+#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) << 17) & 0x20000)
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000)
+#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) << 16) & 0x10000)
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000)
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) << 8) & 0x100)
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)        ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100)
+#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
+#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
+#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) << 7) & 0x80)
+#define BF_LRADC_CTRL1_LRADC7_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80)
+#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
+#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
+#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) << 6) & 0x40)
+#define BF_LRADC_CTRL1_LRADC6_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40)
+#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
+#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
+#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) << 5) & 0x20)
+#define BF_LRADC_CTRL1_LRADC5_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20)
+#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
+#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
+#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) << 4) & 0x10)
+#define BF_LRADC_CTRL1_LRADC4_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10)
+#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
+#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
+#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) << 3) & 0x8)
+#define BF_LRADC_CTRL1_LRADC3_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8)
+#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
+#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
+#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) << 2) & 0x4)
+#define BF_LRADC_CTRL1_LRADC2_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4)
+#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
+#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
+#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) << 1) & 0x2)
+#define BF_LRADC_CTRL1_LRADC1_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2)
+#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
+#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
+#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) << 0) & 0x1)
+#define BF_LRADC_CTRL1_LRADC0_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL2                                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0))
+#define HW_LRADC_CTRL2_SET                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4))
+#define HW_LRADC_CTRL2_CLR                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8))
+#define HW_LRADC_CTRL2_TOG                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc))
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) << 24) & 0xff000000)
+#define BP_LRADC_CTRL2_LRADC6SELECT                     20
+#define BM_LRADC_CTRL2_LRADC6SELECT                     0xf00000
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL0           0x0
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL1           0x1
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL2           0x2
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL3           0x3
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL4           0x4
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL5           0x5
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL6           0x6
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL7           0x7
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL8           0x8
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL9           0x9
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL10          0xa
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL11          0xb
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL12          0xc
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL13          0xd
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL14          0xe
+#define BV_LRADC_CTRL2_LRADC6SELECT__CHANNEL15          0xf
+#define BF_LRADC_CTRL2_LRADC6SELECT(v)                  (((v) << 20) & 0xf00000)
+#define BF_LRADC_CTRL2_LRADC6SELECT_V(v)                ((BV_LRADC_CTRL2_LRADC6SELECT__##v << 20) & 0xf00000)
+#define BP_LRADC_CTRL2_LRADC7SELECT                     16
+#define BM_LRADC_CTRL2_LRADC7SELECT                     0xf0000
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL0           0x0
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL1           0x1
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL2           0x2
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL3           0x3
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL4           0x4
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL5           0x5
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL6           0x6
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL7           0x7
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL8           0x8
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL9           0x9
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL10          0xa
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL11          0xb
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL12          0xc
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL13          0xd
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL14          0xe
+#define BV_LRADC_CTRL2_LRADC7SELECT__CHANNEL15          0xf
+#define BF_LRADC_CTRL2_LRADC7SELECT(v)                  (((v) << 16) & 0xf0000)
+#define BF_LRADC_CTRL2_LRADC7SELECT_V(v)                ((BV_LRADC_CTRL2_LRADC7SELECT__##v << 16) & 0xf0000)
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) << 9) & 0x200)
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200)
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) << 8) & 0x100)
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100)
+#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
+#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
+#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) << 4) & 0xf0)
+#define BF_LRADC_CTRL2_TEMP_ISRC1_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0)
+#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
+#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) << 0) & 0xf)
+#define BF_LRADC_CTRL2_TEMP_ISRC0_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf)
+
+/**
+ * Register: HW_LRADC_CTRL3
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL3                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0))
+#define HW_LRADC_CTRL3_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4))
+#define HW_LRADC_CTRL3_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8))
+#define HW_LRADC_CTRL3_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc))
+#define BP_LRADC_CTRL3_DISCARD                  24
+#define BM_LRADC_CTRL3_DISCARD                  0x3000000
+#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
+#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
+#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
+#define BF_LRADC_CTRL3_DISCARD(v)               (((v) << 24) & 0x3000000)
+#define BF_LRADC_CTRL3_DISCARD_V(v)             ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000)
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) << 22) & 0x400000)
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000)
+#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWUP       21
+#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWUP       0x200000
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__OFF  0x0
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__ON   0x1
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP(v)    (((v) << 21) & 0x200000)
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWUP_V(v)  ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWUP__##v << 21) & 0x200000)
+#define BP_LRADC_CTRL3_FORCE_PWD40UA_PWDN       20
+#define BM_LRADC_CTRL3_FORCE_PWD40UA_PWDN       0x100000
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__ON   0x0
+#define BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__OFF  0x1
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN(v)    (((v) << 20) & 0x100000)
+#define BF_LRADC_CTRL3_FORCE_PWD40UA_PWDN_V(v)  ((BV_LRADC_CTRL3_FORCE_PWD40UA_PWDN__##v << 20) & 0x100000)
+#define BP_LRADC_CTRL3_VDD_FILTER               16
+#define BM_LRADC_CTRL3_VDD_FILTER               0x30000
+#define BV_LRADC_CTRL3_VDD_FILTER__0OHMS        0x0
+#define BV_LRADC_CTRL3_VDD_FILTER__100OHMS      0x1
+#define BV_LRADC_CTRL3_VDD_FILTER__250OHMS      0x2
+#define BV_LRADC_CTRL3_VDD_FILTER__5000OHMS     0x3
+#define BF_LRADC_CTRL3_VDD_FILTER(v)            (((v) << 16) & 0x30000)
+#define BF_LRADC_CTRL3_VDD_FILTER_V(v)          ((BV_LRADC_CTRL3_VDD_FILTER__##v << 16) & 0x30000)
+#define BP_LRADC_CTRL3_ADD_CAP2INPUTS           12
+#define BM_LRADC_CTRL3_ADD_CAP2INPUTS           0x3000
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0PF      0x0
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__0_5PF    0x1
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__1_0PF    0x2
+#define BV_LRADC_CTRL3_ADD_CAP2INPUTS__2_5PF    0x3
+#define BF_LRADC_CTRL3_ADD_CAP2INPUTS(v)        (((v) << 12) & 0x3000)
+#define BF_LRADC_CTRL3_ADD_CAP2INPUTS_V(v)      ((BV_LRADC_CTRL3_ADD_CAP2INPUTS__##v << 12) & 0x3000)
+#define BP_LRADC_CTRL3_CYCLE_TIME               8
+#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
+#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
+#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
+#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
+#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
+#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) << 8) & 0x300)
+#define BF_LRADC_CTRL3_CYCLE_TIME_V(v)          ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300)
+#define BP_LRADC_CTRL3_HIGH_TIME                4
+#define BM_LRADC_CTRL3_HIGH_TIME                0x30
+#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
+#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
+#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
+#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
+#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) << 4) & 0x30)
+#define BF_LRADC_CTRL3_HIGH_TIME_V(v)           ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30)
+#define BP_LRADC_CTRL3_REMOVE_CFILT             3
+#define BM_LRADC_CTRL3_REMOVE_CFILT             0x8
+#define BV_LRADC_CTRL3_REMOVE_CFILT__OFF        0x0
+#define BV_LRADC_CTRL3_REMOVE_CFILT__ON         0x1
+#define BF_LRADC_CTRL3_REMOVE_CFILT(v)          (((v) << 3) & 0x8)
+#define BF_LRADC_CTRL3_REMOVE_CFILT_V(v)        ((BV_LRADC_CTRL3_REMOVE_CFILT__##v << 3) & 0x8)
+#define BP_LRADC_CTRL3_SHORT_RFILT              2
+#define BM_LRADC_CTRL3_SHORT_RFILT              0x4
+#define BV_LRADC_CTRL3_SHORT_RFILT__OFF         0x0
+#define BV_LRADC_CTRL3_SHORT_RFILT__ON          0x1
+#define BF_LRADC_CTRL3_SHORT_RFILT(v)           (((v) << 2) & 0x4)
+#define BF_LRADC_CTRL3_SHORT_RFILT_V(v)         ((BV_LRADC_CTRL3_SHORT_RFILT__##v << 2) & 0x4)
+#define BP_LRADC_CTRL3_DELAY_CLOCK              1
+#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
+#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
+#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
+#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) << 1) & 0x2)
+#define BF_LRADC_CTRL3_DELAY_CLOCK_V(v)         ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2)
+#define BP_LRADC_CTRL3_INVERT_CLOCK             0
+#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
+#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
+#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
+#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) << 0) & 0x1)
+#define BF_LRADC_CTRL3_INVERT_CLOCK_V(v)        ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_STATUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_LRADC_STATUS                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40))
+#define BP_LRADC_STATUS_TEMP1_PRESENT           26
+#define BM_LRADC_STATUS_TEMP1_PRESENT           0x4000000
+#define BF_LRADC_STATUS_TEMP1_PRESENT(v)        (((v) << 26) & 0x4000000)
+#define BP_LRADC_STATUS_TEMP0_PRESENT           25
+#define BM_LRADC_STATUS_TEMP0_PRESENT           0x2000000
+#define BF_LRADC_STATUS_TEMP0_PRESENT(v)        (((v) << 25) & 0x2000000)
+#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT     24
+#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT     0x1000000
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)  (((v) << 24) & 0x1000000)
+#define BP_LRADC_STATUS_CHANNEL7_PRESENT        23
+#define BM_LRADC_STATUS_CHANNEL7_PRESENT        0x800000
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)     (((v) << 23) & 0x800000)
+#define BP_LRADC_STATUS_CHANNEL6_PRESENT        22
+#define BM_LRADC_STATUS_CHANNEL6_PRESENT        0x400000
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)     (((v) << 22) & 0x400000)
+#define BP_LRADC_STATUS_CHANNEL5_PRESENT        21
+#define BM_LRADC_STATUS_CHANNEL5_PRESENT        0x200000
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)     (((v) << 21) & 0x200000)
+#define BP_LRADC_STATUS_CHANNEL4_PRESENT        20
+#define BM_LRADC_STATUS_CHANNEL4_PRESENT        0x100000
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)     (((v) << 20) & 0x100000)
+#define BP_LRADC_STATUS_CHANNEL3_PRESENT        19
+#define BM_LRADC_STATUS_CHANNEL3_PRESENT        0x80000
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)     (((v) << 19) & 0x80000)
+#define BP_LRADC_STATUS_CHANNEL2_PRESENT        18
+#define BM_LRADC_STATUS_CHANNEL2_PRESENT        0x40000
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)     (((v) << 18) & 0x40000)
+#define BP_LRADC_STATUS_CHANNEL1_PRESENT        17
+#define BM_LRADC_STATUS_CHANNEL1_PRESENT        0x20000
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)     (((v) << 17) & 0x20000)
+#define BP_LRADC_STATUS_CHANNEL0_PRESENT        16
+#define BM_LRADC_STATUS_CHANNEL0_PRESENT        0x10000
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)     (((v) << 16) & 0x10000)
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x1
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN  0x0
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT   0x1
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)     (((v) << 0) & 0x1)
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)   ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_DEBUG0
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_LRADC_DEBUG0             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110))
+#define BP_LRADC_DEBUG0_READONLY    16
+#define BM_LRADC_DEBUG0_READONLY    0xffff0000
+#define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000)
+#define BP_LRADC_DEBUG0_STATE       0
+#define BM_LRADC_DEBUG0_STATE       0xfff
+#define BF_LRADC_DEBUG0_STATE(v)    (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_LRADC_DEBUG1
+ * Address: 0x120
+ * SCT: yes
+*/
+#define HW_LRADC_DEBUG1                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0))
+#define HW_LRADC_DEBUG1_SET                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4))
+#define HW_LRADC_DEBUG1_CLR                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8))
+#define HW_LRADC_DEBUG1_TOG                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc))
+#define BP_LRADC_DEBUG1_REQUEST             16
+#define BM_LRADC_DEBUG1_REQUEST             0xff0000
+#define BF_LRADC_DEBUG1_REQUEST(v)          (((v) << 16) & 0xff0000)
+#define BP_LRADC_DEBUG1_TESTMODE_COUNT      8
+#define BM_LRADC_DEBUG1_TESTMODE_COUNT      0x1f00
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)   (((v) << 8) & 0x1f00)
+#define BP_LRADC_DEBUG1_TESTMODE6           2
+#define BM_LRADC_DEBUG1_TESTMODE6           0x4
+#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL   0x0
+#define BV_LRADC_DEBUG1_TESTMODE6__TEST     0x1
+#define BF_LRADC_DEBUG1_TESTMODE6(v)        (((v) << 2) & 0x4)
+#define BF_LRADC_DEBUG1_TESTMODE6_V(v)      ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4)
+#define BP_LRADC_DEBUG1_TESTMODE5           1
+#define BM_LRADC_DEBUG1_TESTMODE5           0x2
+#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL   0x0
+#define BV_LRADC_DEBUG1_TESTMODE5__TEST     0x1
+#define BF_LRADC_DEBUG1_TESTMODE5(v)        (((v) << 1) & 0x2)
+#define BF_LRADC_DEBUG1_TESTMODE5_V(v)      ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2)
+#define BP_LRADC_DEBUG1_TESTMODE            0
+#define BM_LRADC_DEBUG1_TESTMODE            0x1
+#define BV_LRADC_DEBUG1_TESTMODE__NORMAL    0x0
+#define BV_LRADC_DEBUG1_TESTMODE__TEST      0x1
+#define BF_LRADC_DEBUG1_TESTMODE(v)         (((v) << 0) & 0x1)
+#define BF_LRADC_DEBUG1_TESTMODE_V(v)       ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CONVERSION
+ * Address: 0x130
+ * SCT: yes
+*/
+#define HW_LRADC_CONVERSION                             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0))
+#define HW_LRADC_CONVERSION_SET                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4))
+#define HW_LRADC_CONVERSION_CLR                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8))
+#define HW_LRADC_CONVERSION_TOG                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc))
+#define BP_LRADC_CONVERSION_AUTOMATIC                   20
+#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
+#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
+#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
+#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) << 20) & 0x100000)
+#define BF_LRADC_CONVERSION_AUTOMATIC_V(v)              ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000)
+#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
+#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
+#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) << 16) & 0x30000)
+#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v)           ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000)
+#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
+#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LRADC_DELAYn
+ * Address: 0xd0+n*0x10
+ * SCT: yes
+*/
+#define HW_LRADC_DELAYn(n)                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0))
+#define HW_LRADC_DELAYn_SET(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4))
+#define HW_LRADC_DELAYn_CLR(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8))
+#define HW_LRADC_DELAYn_TOG(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc))
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS      24
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS      0xff000000
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)   (((v) << 24) & 0xff000000)
+#define BP_LRADC_DELAYn_KICK                20
+#define BM_LRADC_DELAYn_KICK                0x100000
+#define BF_LRADC_DELAYn_KICK(v)             (((v) << 20) & 0x100000)
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS      16
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS      0xf0000
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)   (((v) << 16) & 0xf0000)
+#define BP_LRADC_DELAYn_LOOP_COUNT          11
+#define BM_LRADC_DELAYn_LOOP_COUNT          0xf800
+#define BF_LRADC_DELAYn_LOOP_COUNT(v)       (((v) << 11) & 0xf800)
+#define BP_LRADC_DELAYn_DELAY               0
+#define BM_LRADC_DELAYn_DELAY               0x7ff
+#define BF_LRADC_DELAYn_DELAY(v)            (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_LRADC_CHn
+ * Address: 0x50+n*0x10
+ * SCT: yes
+*/
+#define HW_LRADC_CHn(n)             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0))
+#define HW_LRADC_CHn_SET(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4))
+#define HW_LRADC_CHn_CLR(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8))
+#define HW_LRADC_CHn_TOG(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc))
+#define BP_LRADC_CHn_TOGGLE         31
+#define BM_LRADC_CHn_TOGGLE         0x80000000
+#define BF_LRADC_CHn_TOGGLE(v)      (((v) << 31) & 0x80000000)
+#define BP_LRADC_CHn_ACCUMULATE     29
+#define BM_LRADC_CHn_ACCUMULATE     0x20000000
+#define BF_LRADC_CHn_ACCUMULATE(v)  (((v) << 29) & 0x20000000)
+#define BP_LRADC_CHn_NUM_SAMPLES    24
+#define BM_LRADC_CHn_NUM_SAMPLES    0x1f000000
+#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000)
+#define BP_LRADC_CHn_VALUE          0
+#define BM_LRADC_CHn_VALUE          0x3ffff
+#define BF_LRADC_CHn_VALUE(v)       (((v) << 0) & 0x3ffff)
+
+#endif /* __HEADERGEN__STMP3600__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h
new file mode 100644
index 0000000000..3ba723eab3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-memcpy.h
@@ -0,0 +1,105 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__MEMCPY__H__
+#define __HEADERGEN__STMP3600__MEMCPY__H__
+
+#define REGS_MEMCPY_BASE (0x80014000)
+
+#define REGS_MEMCPY_VERSION "2.3.0"
+
+/**
+ * Register: HW_MEMCPY_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_MEMCPY_CTRL                      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x0))
+#define HW_MEMCPY_CTRL_SET                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x4))
+#define HW_MEMCPY_CTRL_CLR                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x8))
+#define HW_MEMCPY_CTRL_TOG                  (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0xc))
+#define BP_MEMCPY_CTRL_SFTRST               31
+#define BM_MEMCPY_CTRL_SFTRST               0x80000000
+#define BV_MEMCPY_CTRL_SFTRST__RUN          0x0
+#define BV_MEMCPY_CTRL_SFTRST__RESET        0x1
+#define BF_MEMCPY_CTRL_SFTRST(v)            (((v) << 31) & 0x80000000)
+#define BF_MEMCPY_CTRL_SFTRST_V(v)          ((BV_MEMCPY_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_MEMCPY_CTRL_CLKGATE              30
+#define BM_MEMCPY_CTRL_CLKGATE              0x40000000
+#define BV_MEMCPY_CTRL_CLKGATE__RUN         0x0
+#define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS     0x1
+#define BF_MEMCPY_CTRL_CLKGATE(v)           (((v) << 30) & 0x40000000)
+#define BF_MEMCPY_CTRL_CLKGATE_V(v)         ((BV_MEMCPY_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_MEMCPY_CTRL_PRESENT              29
+#define BM_MEMCPY_CTRL_PRESENT              0x20000000
+#define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0
+#define BV_MEMCPY_CTRL_PRESENT__AVAILABLE   0x1
+#define BF_MEMCPY_CTRL_PRESENT(v)           (((v) << 29) & 0x20000000)
+#define BF_MEMCPY_CTRL_PRESENT_V(v)         ((BV_MEMCPY_CTRL_PRESENT__##v << 29) & 0x20000000)
+#define BP_MEMCPY_CTRL_BURST                16
+#define BM_MEMCPY_CTRL_BURST                0x10000
+#define BF_MEMCPY_CTRL_BURST(v)             (((v) << 16) & 0x10000)
+#define BP_MEMCPY_CTRL_XFER_SIZE            0
+#define BM_MEMCPY_CTRL_XFER_SIZE            0xffff
+#define BF_MEMCPY_CTRL_XFER_SIZE(v)         (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_MEMCPY_DATA
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_MEMCPY_DATA          (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x0))
+#define HW_MEMCPY_DATA_SET      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x4))
+#define HW_MEMCPY_DATA_CLR      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x8))
+#define HW_MEMCPY_DATA_TOG      (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0xc))
+#define BP_MEMCPY_DATA_DATA     0
+#define BM_MEMCPY_DATA_DATA     0xffffffff
+#define BF_MEMCPY_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_MEMCPY_DEBUG
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_MEMCPY_DEBUG                 (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x20))
+#define BP_MEMCPY_DEBUG_DST_END_CMD     30
+#define BM_MEMCPY_DEBUG_DST_END_CMD     0x40000000
+#define BF_MEMCPY_DEBUG_DST_END_CMD(v)  (((v) << 30) & 0x40000000)
+#define BP_MEMCPY_DEBUG_DST_KICK        29
+#define BM_MEMCPY_DEBUG_DST_KICK        0x20000000
+#define BF_MEMCPY_DEBUG_DST_KICK(v)     (((v) << 29) & 0x20000000)
+#define BP_MEMCPY_DEBUG_DST_DMA_REQ     28
+#define BM_MEMCPY_DEBUG_DST_DMA_REQ     0x10000000
+#define BF_MEMCPY_DEBUG_DST_DMA_REQ(v)  (((v) << 28) & 0x10000000)
+#define BP_MEMCPY_DEBUG_SRC_KICK        25
+#define BM_MEMCPY_DEBUG_SRC_KICK        0x2000000
+#define BF_MEMCPY_DEBUG_SRC_KICK(v)     (((v) << 25) & 0x2000000)
+#define BP_MEMCPY_DEBUG_SRC_DMA_REQ     24
+#define BM_MEMCPY_DEBUG_SRC_DMA_REQ     0x1000000
+#define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v)  (((v) << 24) & 0x1000000)
+#define BP_MEMCPY_DEBUG_WRITE_STATE     2
+#define BM_MEMCPY_DEBUG_WRITE_STATE     0xc
+#define BF_MEMCPY_DEBUG_WRITE_STATE(v)  (((v) << 2) & 0xc)
+#define BP_MEMCPY_DEBUG_READ_STATE      0
+#define BM_MEMCPY_DEBUG_READ_STATE      0x3
+#define BF_MEMCPY_DEBUG_READ_STATE(v)   (((v) << 0) & 0x3)
+
+#endif /* __HEADERGEN__STMP3600__MEMCPY__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h
new file mode 100644
index 0000000000..14b6069060
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-pinctrl.h
@@ -0,0 +1,213 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__PINCTRL__H__
+#define __HEADERGEN__STMP3600__PINCTRL__H__
+
+#define REGS_PINCTRL_BASE (0x80018000)
+
+#define REGS_PINCTRL_VERSION "2.3.0"
+
+/**
+ * Register: HW_PINCTRL_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_PINCTRL_CTRL             (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
+#define HW_PINCTRL_CTRL_SET         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
+#define HW_PINCTRL_CTRL_CLR         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
+#define HW_PINCTRL_CTRL_TOG         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
+#define BP_PINCTRL_CTRL_SFTRST      31
+#define BM_PINCTRL_CTRL_SFTRST      0x80000000
+#define BF_PINCTRL_CTRL_SFTRST(v)   (((v) << 31) & 0x80000000)
+#define BP_PINCTRL_CTRL_CLKGATE     30
+#define BM_PINCTRL_CTRL_CLKGATE     0x40000000
+#define BF_PINCTRL_CTRL_CLKGATE(v)  (((v) << 30) & 0x40000000)
+#define BP_PINCTRL_CTRL_PRESENT3    29
+#define BM_PINCTRL_CTRL_PRESENT3    0x20000000
+#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000)
+#define BP_PINCTRL_CTRL_PRESENT2    28
+#define BM_PINCTRL_CTRL_PRESENT2    0x10000000
+#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000)
+#define BP_PINCTRL_CTRL_PRESENT1    27
+#define BM_PINCTRL_CTRL_PRESENT1    0x8000000
+#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000)
+#define BP_PINCTRL_CTRL_PRESENT0    26
+#define BM_PINCTRL_CTRL_PRESENT0    0x4000000
+#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000)
+#define BP_PINCTRL_CTRL_IRQOUT3     3
+#define BM_PINCTRL_CTRL_IRQOUT3     0x8
+#define BF_PINCTRL_CTRL_IRQOUT3(v)  (((v) << 3) & 0x8)
+#define BP_PINCTRL_CTRL_IRQOUT2     2
+#define BM_PINCTRL_CTRL_IRQOUT2     0x4
+#define BF_PINCTRL_CTRL_IRQOUT2(v)  (((v) << 2) & 0x4)
+#define BP_PINCTRL_CTRL_IRQOUT1     1
+#define BM_PINCTRL_CTRL_IRQOUT1     0x2
+#define BF_PINCTRL_CTRL_IRQOUT1(v)  (((v) << 1) & 0x2)
+#define BP_PINCTRL_CTRL_IRQOUT0     0
+#define BM_PINCTRL_CTRL_IRQOUT0     0x1
+#define BF_PINCTRL_CTRL_IRQOUT0(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PINCTRL_MUXSELLn
+ * Address: 0x10+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_MUXSELLn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x0))
+#define HW_PINCTRL_MUXSELLn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x4))
+#define HW_PINCTRL_MUXSELLn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0x8))
+#define HW_PINCTRL_MUXSELLn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x10+(n)*0x100 + 0xc))
+#define BP_PINCTRL_MUXSELLn_BITS    0
+#define BM_PINCTRL_MUXSELLn_BITS    0xffffffff
+#define BF_PINCTRL_MUXSELLn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_MUXSELHn
+ * Address: 0x20+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_MUXSELHn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x0))
+#define HW_PINCTRL_MUXSELHn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x4))
+#define HW_PINCTRL_MUXSELHn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0x8))
+#define HW_PINCTRL_MUXSELHn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x20+(n)*0x100 + 0xc))
+#define BP_PINCTRL_MUXSELHn_BITS    0
+#define BM_PINCTRL_MUXSELHn_BITS    0xffffffff
+#define BF_PINCTRL_MUXSELHn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DRIVEn
+ * Address: 0x30+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_DRIVEn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x0))
+#define HW_PINCTRL_DRIVEn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x4))
+#define HW_PINCTRL_DRIVEn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0x8))
+#define HW_PINCTRL_DRIVEn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x30+(n)*0x100 + 0xc))
+#define BP_PINCTRL_DRIVEn_BITS      0
+#define BM_PINCTRL_DRIVEn_BITS      0xffffffff
+#define BF_PINCTRL_DRIVEn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DOUTn
+ * Address: 0x50+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_DOUTn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x0))
+#define HW_PINCTRL_DOUTn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x4))
+#define HW_PINCTRL_DOUTn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0x8))
+#define HW_PINCTRL_DOUTn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x50+(n)*0x100 + 0xc))
+#define BP_PINCTRL_DOUTn_BITS       0
+#define BM_PINCTRL_DOUTn_BITS       0xffffffff
+#define BF_PINCTRL_DOUTn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DINn
+ * Address: 0x60+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_DINn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x0))
+#define HW_PINCTRL_DINn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x4))
+#define HW_PINCTRL_DINn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0x8))
+#define HW_PINCTRL_DINn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x60+(n)*0x100 + 0xc))
+#define BP_PINCTRL_DINn_BITS    0
+#define BM_PINCTRL_DINn_BITS    0xffffffff
+#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DOEn
+ * Address: 0x70+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_DOEn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x0))
+#define HW_PINCTRL_DOEn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x4))
+#define HW_PINCTRL_DOEn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0x8))
+#define HW_PINCTRL_DOEn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x70+(n)*0x100 + 0xc))
+#define BP_PINCTRL_DOEn_BITS    0
+#define BM_PINCTRL_DOEn_BITS    0xffffffff
+#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_PIN2IRQn
+ * Address: 0x80+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_PIN2IRQn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x0))
+#define HW_PINCTRL_PIN2IRQn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x4))
+#define HW_PINCTRL_PIN2IRQn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0x8))
+#define HW_PINCTRL_PIN2IRQn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x80+(n)*0x100 + 0xc))
+#define BP_PINCTRL_PIN2IRQn_BITS    0
+#define BM_PINCTRL_PIN2IRQn_BITS    0xffffffff
+#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQENn
+ * Address: 0x90+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQENn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x0))
+#define HW_PINCTRL_IRQENn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x4))
+#define HW_PINCTRL_IRQENn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0x8))
+#define HW_PINCTRL_IRQENn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x90+(n)*0x100 + 0xc))
+#define BP_PINCTRL_IRQENn_BITS      0
+#define BM_PINCTRL_IRQENn_BITS      0xffffffff
+#define BF_PINCTRL_IRQENn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQLEVELn
+ * Address: 0xa0+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQLEVELn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x0))
+#define HW_PINCTRL_IRQLEVELn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x4))
+#define HW_PINCTRL_IRQLEVELn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0x8))
+#define HW_PINCTRL_IRQLEVELn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa0+(n)*0x100 + 0xc))
+#define BP_PINCTRL_IRQLEVELn_BITS       0
+#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
+#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQPOLn
+ * Address: 0xb0+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQPOLn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x0))
+#define HW_PINCTRL_IRQPOLn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x4))
+#define HW_PINCTRL_IRQPOLn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0x8))
+#define HW_PINCTRL_IRQPOLn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb0+(n)*0x100 + 0xc))
+#define BP_PINCTRL_IRQPOLn_BITS     0
+#define BM_PINCTRL_IRQPOLn_BITS     0xffffffff
+#define BF_PINCTRL_IRQPOLn_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQSTATn
+ * Address: 0xc0+n*0x100
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQSTATn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x0))
+#define HW_PINCTRL_IRQSTATn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x4))
+#define HW_PINCTRL_IRQSTATn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0x8))
+#define HW_PINCTRL_IRQSTATn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xc0+(n)*0x100 + 0xc))
+#define BP_PINCTRL_IRQSTATn_BITS    0
+#define BM_PINCTRL_IRQSTATn_BITS    0xffffffff
+#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3600__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-power.h b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h
new file mode 100644
index 0000000000..577a1c6415
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-power.h
@@ -0,0 +1,484 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__POWER__H__
+#define __HEADERGEN__STMP3600__POWER__H__
+
+#define REGS_POWER_BASE (0x80044000)
+
+#define REGS_POWER_VERSION "2.3.0"
+
+/**
+ * Register: HW_POWER_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_POWER_CTRL                               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0))
+#define HW_POWER_CTRL_SET                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4))
+#define HW_POWER_CTRL_CLR                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8))
+#define HW_POWER_CTRL_TOG                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc))
+#define BP_POWER_CTRL_CLKGATE                       30
+#define BM_POWER_CTRL_CLKGATE                       0x40000000
+#define BF_POWER_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
+#define BP_POWER_CTRL_BATT_BO_IRQ                   8
+#define BM_POWER_CTRL_BATT_BO_IRQ                   0x100
+#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) << 8) & 0x100)
+#define BP_POWER_CTRL_ENIRQBATT_BO                  7
+#define BM_POWER_CTRL_ENIRQBATT_BO                  0x80
+#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) << 7) & 0x80)
+#define BP_POWER_CTRL_VDDIO_BO_IRQ                  6
+#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x40
+#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) << 6) & 0x40)
+#define BP_POWER_CTRL_ENIRQVDDIO_BO                 5
+#define BM_POWER_CTRL_ENIRQVDDIO_BO                 0x20
+#define BF_POWER_CTRL_ENIRQVDDIO_BO(v)              (((v) << 5) & 0x20)
+#define BP_POWER_CTRL_VDDD_BO_IRQ                   4
+#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x10
+#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) << 4) & 0x10)
+#define BP_POWER_CTRL_ENIRQVDDD_BO                  3
+#define BM_POWER_CTRL_ENIRQVDDD_BO                  0x8
+#define BF_POWER_CTRL_ENIRQVDDD_BO(v)               (((v) << 3) & 0x8)
+#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) << 2) & 0x4)
+#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) << 1) & 0x2)
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_5VCTRL
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_POWER_5VCTRL                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0))
+#define HW_POWER_5VCTRL_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4))
+#define HW_POWER_5VCTRL_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8))
+#define HW_POWER_5VCTRL_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc))
+#define BP_POWER_5VCTRL_PWDN_5VBRNOUT           21
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT           0x200000
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)        (((v) << 21) & 0x200000)
+#define BP_POWER_5VCTRL_PWDN_IOBRNOUT           20
+#define BM_POWER_5VCTRL_PWDN_IOBRNOUT           0x100000
+#define BF_POWER_5VCTRL_PWDN_IOBRNOUT(v)        (((v) << 20) & 0x100000)
+#define BP_POWER_5VCTRL_DISABLE_ILIMIT          19
+#define BM_POWER_5VCTRL_DISABLE_ILIMIT          0x80000
+#define BF_POWER_5VCTRL_DISABLE_ILIMIT(v)       (((v) << 19) & 0x80000)
+#define BP_POWER_5VCTRL_DCDC_XFER               18
+#define BM_POWER_5VCTRL_DCDC_XFER               0x40000
+#define BF_POWER_5VCTRL_DCDC_XFER(v)            (((v) << 18) & 0x40000)
+#define BP_POWER_5VCTRL_EN_BATT_PULLDN          17
+#define BM_POWER_5VCTRL_EN_BATT_PULLDN          0x20000
+#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)       (((v) << 17) & 0x20000)
+#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT      16
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT      0x10000
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)   (((v) << 16) & 0x10000)
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH          8
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH          0x300
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)       (((v) << 8) & 0x300)
+#define BP_POWER_5VCTRL_USB_SUSPEND_I           7
+#define BM_POWER_5VCTRL_USB_SUSPEND_I           0x80
+#define BF_POWER_5VCTRL_USB_SUSPEND_I(v)        (((v) << 7) & 0x80)
+#define BP_POWER_5VCTRL_VBUSVALID_TO_B          6
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B          0x40
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)       (((v) << 6) & 0x40)
+#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO          5
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO          0x20
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)       (((v) << 5) & 0x20)
+#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS          4
+#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS          0x10
+#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)       (((v) << 4) & 0x10)
+#define BP_POWER_5VCTRL_EN_DCDC2                3
+#define BM_POWER_5VCTRL_EN_DCDC2                0x8
+#define BF_POWER_5VCTRL_EN_DCDC2(v)             (((v) << 3) & 0x8)
+#define BP_POWER_5VCTRL_PWD_VDDD_LINREG         2
+#define BM_POWER_5VCTRL_PWD_VDDD_LINREG         0x4
+#define BF_POWER_5VCTRL_PWD_VDDD_LINREG(v)      (((v) << 2) & 0x4)
+#define BP_POWER_5VCTRL_EN_DCDC1                1
+#define BM_POWER_5VCTRL_EN_DCDC1                0x2
+#define BF_POWER_5VCTRL_EN_DCDC1(v)             (((v) << 1) & 0x2)
+#define BP_POWER_5VCTRL_LINREG_OFFSET           0
+#define BM_POWER_5VCTRL_LINREG_OFFSET           0x1
+#define BF_POWER_5VCTRL_LINREG_OFFSET(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_MINPWR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_POWER_MINPWR                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0))
+#define HW_POWER_MINPWR_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4))
+#define HW_POWER_MINPWR_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8))
+#define HW_POWER_MINPWR_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc))
+#define BP_POWER_MINPWR_TEST_DISCHRG_VBUS       23
+#define BM_POWER_MINPWR_TEST_DISCHRG_VBUS       0x800000
+#define BF_POWER_MINPWR_TEST_DISCHRG_VBUS(v)    (((v) << 23) & 0x800000)
+#define BP_POWER_MINPWR_TEST_CHRG_VBUS          22
+#define BM_POWER_MINPWR_TEST_CHRG_VBUS          0x400000
+#define BF_POWER_MINPWR_TEST_CHRG_VBUS(v)       (((v) << 22) & 0x400000)
+#define BP_POWER_MINPWR_DC2_TST                 21
+#define BM_POWER_MINPWR_DC2_TST                 0x200000
+#define BF_POWER_MINPWR_DC2_TST(v)              (((v) << 21) & 0x200000)
+#define BP_POWER_MINPWR_DC1_TST                 20
+#define BM_POWER_MINPWR_DC1_TST                 0x100000
+#define BF_POWER_MINPWR_DC1_TST(v)              (((v) << 20) & 0x100000)
+#define BP_POWER_MINPWR_PERIPHERALSWOFF         19
+#define BM_POWER_MINPWR_PERIPHERALSWOFF         0x80000
+#define BF_POWER_MINPWR_PERIPHERALSWOFF(v)      (((v) << 19) & 0x80000)
+#define BP_POWER_MINPWR_TOGGLE_DIF              18
+#define BM_POWER_MINPWR_TOGGLE_DIF              0x40000
+#define BF_POWER_MINPWR_TOGGLE_DIF(v)           (((v) << 18) & 0x40000)
+#define BP_POWER_MINPWR_DISABLE_VDDIOSTEP       17
+#define BM_POWER_MINPWR_DISABLE_VDDIOSTEP       0x20000
+#define BF_POWER_MINPWR_DISABLE_VDDIOSTEP(v)    (((v) << 17) & 0x20000)
+#define BP_POWER_MINPWR_DISABLE_VDDSTEP         16
+#define BM_POWER_MINPWR_DISABLE_VDDSTEP         0x10000
+#define BF_POWER_MINPWR_DISABLE_VDDSTEP(v)      (((v) << 16) & 0x10000)
+#define BP_POWER_MINPWR_SEL_PLLDIV16CLK         9
+#define BM_POWER_MINPWR_SEL_PLLDIV16CLK         0x200
+#define BF_POWER_MINPWR_SEL_PLLDIV16CLK(v)      (((v) << 9) & 0x200)
+#define BP_POWER_MINPWR_PWD_VDDIOBO             8
+#define BM_POWER_MINPWR_PWD_VDDIOBO             0x100
+#define BF_POWER_MINPWR_PWD_VDDIOBO(v)          (((v) << 8) & 0x100)
+#define BP_POWER_MINPWR_LESSANA_I               7
+#define BM_POWER_MINPWR_LESSANA_I               0x80
+#define BF_POWER_MINPWR_LESSANA_I(v)            (((v) << 7) & 0x80)
+#define BP_POWER_MINPWR_DC1_HALFFETS            6
+#define BM_POWER_MINPWR_DC1_HALFFETS            0x40
+#define BF_POWER_MINPWR_DC1_HALFFETS(v)         (((v) << 6) & 0x40)
+#define BP_POWER_MINPWR_DC2_STOPCLK             5
+#define BM_POWER_MINPWR_DC2_STOPCLK             0x20
+#define BF_POWER_MINPWR_DC2_STOPCLK(v)          (((v) << 5) & 0x20)
+#define BP_POWER_MINPWR_DC1_STOPCLK             4
+#define BM_POWER_MINPWR_DC1_STOPCLK             0x10
+#define BF_POWER_MINPWR_DC1_STOPCLK(v)          (((v) << 4) & 0x10)
+#define BP_POWER_MINPWR_EN_DC2_PFM              3
+#define BM_POWER_MINPWR_EN_DC2_PFM              0x8
+#define BF_POWER_MINPWR_EN_DC2_PFM(v)           (((v) << 3) & 0x8)
+#define BP_POWER_MINPWR_EN_DC1_PFM              2
+#define BM_POWER_MINPWR_EN_DC1_PFM              0x4
+#define BF_POWER_MINPWR_EN_DC1_PFM(v)           (((v) << 2) & 0x4)
+#define BP_POWER_MINPWR_DC2_HALFCLK             1
+#define BM_POWER_MINPWR_DC2_HALFCLK             0x2
+#define BF_POWER_MINPWR_DC2_HALFCLK(v)          (((v) << 1) & 0x2)
+#define BP_POWER_MINPWR_DC1_HALFCLK             0
+#define BM_POWER_MINPWR_DC1_HALFCLK             0x1
+#define BF_POWER_MINPWR_DC1_HALFCLK(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_BATTCHRG
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_POWER_BATTCHRG                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0))
+#define HW_POWER_BATTCHRG_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4))
+#define HW_POWER_BATTCHRG_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8))
+#define HW_POWER_BATTCHRG_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc))
+#define BP_POWER_BATTCHRG_CHRG_STS_OFF      19
+#define BM_POWER_BATTCHRG_CHRG_STS_OFF      0x80000
+#define BF_POWER_BATTCHRG_CHRG_STS_OFF(v)   (((v) << 19) & 0x80000)
+#define BP_POWER_BATTCHRG_LIION_4P1         18
+#define BM_POWER_BATTCHRG_LIION_4P1         0x40000
+#define BF_POWER_BATTCHRG_LIION_4P1(v)      (((v) << 18) & 0x40000)
+#define BP_POWER_BATTCHRG_USE_EXTERN_R      17
+#define BM_POWER_BATTCHRG_USE_EXTERN_R      0x20000
+#define BF_POWER_BATTCHRG_USE_EXTERN_R(v)   (((v) << 17) & 0x20000)
+#define BP_POWER_BATTCHRG_PWD_BATTCHRG      16
+#define BM_POWER_BATTCHRG_PWD_BATTCHRG      0x10000
+#define BF_POWER_BATTCHRG_PWD_BATTCHRG(v)   (((v) << 16) & 0x10000)
+#define BP_POWER_BATTCHRG_STOP_ILIMIT       8
+#define BM_POWER_BATTCHRG_STOP_ILIMIT       0xf00
+#define BF_POWER_BATTCHRG_STOP_ILIMIT(v)    (((v) << 8) & 0xf00)
+#define BP_POWER_BATTCHRG_BATTCHRG_I        0
+#define BM_POWER_BATTCHRG_BATTCHRG_I        0x3f
+#define BF_POWER_BATTCHRG_BATTCHRG_I(v)     (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_POWER_VDDCTRL
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_POWER_VDDCTRL                (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40))
+#define BP_POWER_VDDCTRL_VDDIO_BO       24
+#define BM_POWER_VDDCTRL_VDDIO_BO       0x1f000000
+#define BF_POWER_VDDCTRL_VDDIO_BO(v)    (((v) << 24) & 0x1f000000)
+#define BP_POWER_VDDCTRL_VDDIO_TRG      16
+#define BM_POWER_VDDCTRL_VDDIO_TRG      0x1f0000
+#define BF_POWER_VDDCTRL_VDDIO_TRG(v)   (((v) << 16) & 0x1f0000)
+#define BP_POWER_VDDCTRL_VDDD_BO        8
+#define BM_POWER_VDDCTRL_VDDD_BO        0x1f00
+#define BF_POWER_VDDCTRL_VDDD_BO(v)     (((v) << 8) & 0x1f00)
+#define BP_POWER_VDDCTRL_VDDD_TRG       0
+#define BM_POWER_VDDCTRL_VDDD_TRG       0x1f
+#define BF_POWER_VDDCTRL_VDDD_TRG(v)    (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_DC1MULTOUT
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_POWER_DC1MULTOUT                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50))
+#define BP_POWER_DC1MULTOUT_FUNCV           16
+#define BM_POWER_DC1MULTOUT_FUNCV           0x1ff0000
+#define BF_POWER_DC1MULTOUT_FUNCV(v)        (((v) << 16) & 0x1ff0000)
+#define BP_POWER_DC1MULTOUT_EN_BATADJ       8
+#define BM_POWER_DC1MULTOUT_EN_BATADJ       0x100
+#define BF_POWER_DC1MULTOUT_EN_BATADJ(v)    (((v) << 8) & 0x100)
+#define BP_POWER_DC1MULTOUT_ADJTN           0
+#define BM_POWER_DC1MULTOUT_ADJTN           0xf
+#define BF_POWER_DC1MULTOUT_ADJTN(v)        (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_POWER_DC1LIMITS
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_POWER_DC1LIMITS                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60))
+#define BP_POWER_DC1LIMITS_EN_PFETOFF           24
+#define BM_POWER_DC1LIMITS_EN_PFETOFF           0x1000000
+#define BF_POWER_DC1LIMITS_EN_PFETOFF(v)        (((v) << 24) & 0x1000000)
+#define BP_POWER_DC1LIMITS_POSLIMIT_BOOST       16
+#define BM_POWER_DC1LIMITS_POSLIMIT_BOOST       0x7f0000
+#define BF_POWER_DC1LIMITS_POSLIMIT_BOOST(v)    (((v) << 16) & 0x7f0000)
+#define BP_POWER_DC1LIMITS_POSLIMIT_BUCK        8
+#define BM_POWER_DC1LIMITS_POSLIMIT_BUCK        0x7f00
+#define BF_POWER_DC1LIMITS_POSLIMIT_BUCK(v)     (((v) << 8) & 0x7f00)
+#define BP_POWER_DC1LIMITS_NEGLIMIT             0
+#define BM_POWER_DC1LIMITS_NEGLIMIT             0x7f
+#define BF_POWER_DC1LIMITS_NEGLIMIT(v)          (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_POWER_DC2LIMITS
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_POWER_DC2LIMITS                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70))
+#define BP_POWER_DC2LIMITS_EN_BOOST             24
+#define BM_POWER_DC2LIMITS_EN_BOOST             0x1000000
+#define BF_POWER_DC2LIMITS_EN_BOOST(v)          (((v) << 24) & 0x1000000)
+#define BP_POWER_DC2LIMITS_POSLIMIT_BOOST       16
+#define BM_POWER_DC2LIMITS_POSLIMIT_BOOST       0x7f0000
+#define BF_POWER_DC2LIMITS_POSLIMIT_BOOST(v)    (((v) << 16) & 0x7f0000)
+#define BP_POWER_DC2LIMITS_POSLIMIT_BUCK        8
+#define BM_POWER_DC2LIMITS_POSLIMIT_BUCK        0x7f00
+#define BF_POWER_DC2LIMITS_POSLIMIT_BUCK(v)     (((v) << 8) & 0x7f00)
+#define BP_POWER_DC2LIMITS_NEGLIMIT             0
+#define BM_POWER_DC2LIMITS_NEGLIMIT             0x7f
+#define BF_POWER_DC2LIMITS_NEGLIMIT(v)          (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_POWER_LOOPCTRL
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_POWER_LOOPCTRL                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x0))
+#define HW_POWER_LOOPCTRL_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x4))
+#define HW_POWER_LOOPCTRL_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0x8))
+#define HW_POWER_LOOPCTRL_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80 + 0xc))
+#define BP_POWER_LOOPCTRL_TRAN_NOHYST       30
+#define BM_POWER_LOOPCTRL_TRAN_NOHYST       0x40000000
+#define BF_POWER_LOOPCTRL_TRAN_NOHYST(v)    (((v) << 30) & 0x40000000)
+#define BP_POWER_LOOPCTRL_HYST_SIGN         29
+#define BM_POWER_LOOPCTRL_HYST_SIGN         0x20000000
+#define BF_POWER_LOOPCTRL_HYST_SIGN(v)      (((v) << 29) & 0x20000000)
+#define BP_POWER_LOOPCTRL_EN_CMP_HYST       28
+#define BM_POWER_LOOPCTRL_EN_CMP_HYST       0x10000000
+#define BF_POWER_LOOPCTRL_EN_CMP_HYST(v)    (((v) << 28) & 0x10000000)
+#define BP_POWER_LOOPCTRL_EN_DC2_RCSCALE    27
+#define BM_POWER_LOOPCTRL_EN_DC2_RCSCALE    0x8000000
+#define BF_POWER_LOOPCTRL_EN_DC2_RCSCALE(v) (((v) << 27) & 0x8000000)
+#define BP_POWER_LOOPCTRL_EN_DC1_RCSCALE    26
+#define BM_POWER_LOOPCTRL_EN_DC1_RCSCALE    0x4000000
+#define BF_POWER_LOOPCTRL_EN_DC1_RCSCALE(v) (((v) << 26) & 0x4000000)
+#define BP_POWER_LOOPCTRL_RC_SIGN           25
+#define BM_POWER_LOOPCTRL_RC_SIGN           0x2000000
+#define BF_POWER_LOOPCTRL_RC_SIGN(v)        (((v) << 25) & 0x2000000)
+#define BP_POWER_LOOPCTRL_EN_RCSCALE        24
+#define BM_POWER_LOOPCTRL_EN_RCSCALE        0x1000000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)     (((v) << 24) & 0x1000000)
+#define BP_POWER_LOOPCTRL_DC2_FF            20
+#define BM_POWER_LOOPCTRL_DC2_FF            0x700000
+#define BF_POWER_LOOPCTRL_DC2_FF(v)         (((v) << 20) & 0x700000)
+#define BP_POWER_LOOPCTRL_DC2_R             16
+#define BM_POWER_LOOPCTRL_DC2_R             0xf0000
+#define BF_POWER_LOOPCTRL_DC2_R(v)          (((v) << 16) & 0xf0000)
+#define BP_POWER_LOOPCTRL_DC2_C             12
+#define BM_POWER_LOOPCTRL_DC2_C             0x3000
+#define BF_POWER_LOOPCTRL_DC2_C(v)          (((v) << 12) & 0x3000)
+#define BP_POWER_LOOPCTRL_DC1_FF            8
+#define BM_POWER_LOOPCTRL_DC1_FF            0x700
+#define BF_POWER_LOOPCTRL_DC1_FF(v)         (((v) << 8) & 0x700)
+#define BP_POWER_LOOPCTRL_DC1_R             4
+#define BM_POWER_LOOPCTRL_DC1_R             0xf0
+#define BF_POWER_LOOPCTRL_DC1_R(v)          (((v) << 4) & 0xf0)
+#define BP_POWER_LOOPCTRL_DC1_C             0
+#define BM_POWER_LOOPCTRL_DC1_C             0x3
+#define BF_POWER_LOOPCTRL_DC1_C(v)          (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_POWER_STS
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_POWER_STS                        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90))
+#define BP_POWER_STS_BATT_CHRG_PRESENT      31
+#define BM_POWER_STS_BATT_CHRG_PRESENT      0x80000000
+#define BF_POWER_STS_BATT_CHRG_PRESENT(v)   (((v) << 31) & 0x80000000)
+#define BP_POWER_STS_MODE                   20
+#define BM_POWER_STS_MODE                   0x300000
+#define BF_POWER_STS_MODE(v)                (((v) << 20) & 0x300000)
+#define BP_POWER_STS_BATT_BO                16
+#define BM_POWER_STS_BATT_BO                0x10000
+#define BF_POWER_STS_BATT_BO(v)             (((v) << 16) & 0x10000)
+#define BP_POWER_STS_CHRGSTS                14
+#define BM_POWER_STS_CHRGSTS                0x4000
+#define BF_POWER_STS_CHRGSTS(v)             (((v) << 14) & 0x4000)
+#define BP_POWER_STS_DC2_OK                 13
+#define BM_POWER_STS_DC2_OK                 0x2000
+#define BF_POWER_STS_DC2_OK(v)              (((v) << 13) & 0x2000)
+#define BP_POWER_STS_DC1_OK                 12
+#define BM_POWER_STS_DC1_OK                 0x1000
+#define BF_POWER_STS_DC1_OK(v)              (((v) << 12) & 0x1000)
+#define BP_POWER_STS_VDDIO_BO               9
+#define BM_POWER_STS_VDDIO_BO               0x200
+#define BF_POWER_STS_VDDIO_BO(v)            (((v) << 9) & 0x200)
+#define BP_POWER_STS_VDDD_BO                8
+#define BM_POWER_STS_VDDD_BO                0x100
+#define BF_POWER_STS_VDDD_BO(v)             (((v) << 8) & 0x100)
+#define BP_POWER_STS_VDD5V_GT_VDDIO         4
+#define BM_POWER_STS_VDD5V_GT_VDDIO         0x10
+#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) << 4) & 0x10)
+#define BP_POWER_STS_AVALID                 3
+#define BM_POWER_STS_AVALID                 0x8
+#define BF_POWER_STS_AVALID(v)              (((v) << 3) & 0x8)
+#define BP_POWER_STS_BVALID                 2
+#define BM_POWER_STS_BVALID                 0x4
+#define BF_POWER_STS_BVALID(v)              (((v) << 2) & 0x4)
+#define BP_POWER_STS_VBUSVALID              1
+#define BM_POWER_STS_VBUSVALID              0x2
+#define BF_POWER_STS_VBUSVALID(v)           (((v) << 1) & 0x2)
+#define BP_POWER_STS_SESSEND                0
+#define BM_POWER_STS_SESSEND                0x1
+#define BF_POWER_STS_SESSEND(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_SPEEDTEMP
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_POWER_SPEEDTEMP                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0))
+#define HW_POWER_SPEEDTEMP_SET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4))
+#define HW_POWER_SPEEDTEMP_CLR              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8))
+#define HW_POWER_SPEEDTEMP_TOG              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc))
+#define BP_POWER_SPEEDTEMP_SPEED_STS1       24
+#define BM_POWER_SPEEDTEMP_SPEED_STS1       0xff000000
+#define BF_POWER_SPEEDTEMP_SPEED_STS1(v)    (((v) << 24) & 0xff000000)
+#define BP_POWER_SPEEDTEMP_SPEED_STS2       16
+#define BM_POWER_SPEEDTEMP_SPEED_STS2       0xff0000
+#define BF_POWER_SPEEDTEMP_SPEED_STS2(v)    (((v) << 16) & 0xff0000)
+#define BP_POWER_SPEEDTEMP_TEMP_STS         8
+#define BM_POWER_SPEEDTEMP_TEMP_STS         0xf00
+#define BF_POWER_SPEEDTEMP_TEMP_STS(v)      (((v) << 8) & 0xf00)
+#define BP_POWER_SPEEDTEMP_SPEED_CTRL       4
+#define BM_POWER_SPEEDTEMP_SPEED_CTRL       0x30
+#define BF_POWER_SPEEDTEMP_SPEED_CTRL(v)    (((v) << 4) & 0x30)
+#define BP_POWER_SPEEDTEMP_TEMP_CTRL        0
+#define BM_POWER_SPEEDTEMP_TEMP_CTRL        0xf
+#define BF_POWER_SPEEDTEMP_TEMP_CTRL(v)     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_POWER_BATTMONITOR
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_POWER_BATTMONITOR                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0))
+#define BP_POWER_BATTMONITOR_BATT_VAL           16
+#define BM_POWER_BATTMONITOR_BATT_VAL           0x3ff0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)        (((v) << 16) & 0x3ff0000)
+#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT    9
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT    0x200
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 9) & 0x200)
+#define BP_POWER_BATTMONITOR_BRWNOUT_PWD        8
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD        0x100
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)     (((v) << 8) & 0x100)
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL        0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL        0xf
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_POWER_RESET
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_POWER_RESET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0))
+#define HW_POWER_RESET_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4))
+#define HW_POWER_RESET_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8))
+#define HW_POWER_RESET_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc))
+#define BP_POWER_RESET_UNLOCK       16
+#define BM_POWER_RESET_UNLOCK       0xffff0000
+#define BV_POWER_RESET_UNLOCK__KEY  0x3e77
+#define BF_POWER_RESET_UNLOCK(v)    (((v) << 16) & 0xffff0000)
+#define BF_POWER_RESET_UNLOCK_V(v)  ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000)
+#define BP_POWER_RESET_PWD_OFF      4
+#define BM_POWER_RESET_PWD_OFF      0x10
+#define BF_POWER_RESET_PWD_OFF(v)   (((v) << 4) & 0x10)
+#define BP_POWER_RESET_POR          3
+#define BM_POWER_RESET_POR          0x8
+#define BF_POWER_RESET_POR(v)       (((v) << 3) & 0x8)
+#define BP_POWER_RESET_PWD          2
+#define BM_POWER_RESET_PWD          0x4
+#define BF_POWER_RESET_PWD(v)       (((v) << 2) & 0x4)
+#define BP_POWER_RESET_RST_DIG      1
+#define BM_POWER_RESET_RST_DIG      0x2
+#define BF_POWER_RESET_RST_DIG(v)   (((v) << 1) & 0x2)
+#define BP_POWER_RESET_RST_ALL      0
+#define BM_POWER_RESET_RST_ALL      0x1
+#define BF_POWER_RESET_RST_ALL(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_DEBUG
+ * Address: 0xd0
+ * SCT: yes
+*/
+#define HW_POWER_DEBUG                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x0))
+#define HW_POWER_DEBUG_SET                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x4))
+#define HW_POWER_DEBUG_CLR                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0x8))
+#define HW_POWER_DEBUG_TOG                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0 + 0xc))
+#define BP_POWER_DEBUG_ENCTRLVBUS           4
+#define BM_POWER_DEBUG_ENCTRLVBUS           0x10
+#define BF_POWER_DEBUG_ENCTRLVBUS(v)        (((v) << 4) & 0x10)
+#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK     3
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK     0x8
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)  (((v) << 3) & 0x8)
+#define BP_POWER_DEBUG_AVALIDPIOLOCK        2
+#define BM_POWER_DEBUG_AVALIDPIOLOCK        0x4
+#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)     (((v) << 2) & 0x4)
+#define BP_POWER_DEBUG_BVALIDPIOLOCK        1
+#define BM_POWER_DEBUG_BVALIDPIOLOCK        0x2
+#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)     (((v) << 1) & 0x2)
+#define BP_POWER_DEBUG_SESSENDPIOLOCK       0
+#define BM_POWER_DEBUG_SESSENDPIOLOCK       0x1
+#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)    (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3600__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h
new file mode 100644
index 0000000000..72d456fd10
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-pwm.h
@@ -0,0 +1,134 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__PWM__H__
+#define __HEADERGEN__STMP3600__PWM__H__
+
+#define REGS_PWM_BASE (0x80064000)
+
+#define REGS_PWM_VERSION "2.3.0"
+
+/**
+ * Register: HW_PWM_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_PWM_CTRL                 (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0))
+#define HW_PWM_CTRL_SET             (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4))
+#define HW_PWM_CTRL_CLR             (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8))
+#define HW_PWM_CTRL_TOG             (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc))
+#define BP_PWM_CTRL_SFTRST          31
+#define BM_PWM_CTRL_SFTRST          0x80000000
+#define BF_PWM_CTRL_SFTRST(v)       (((v) << 31) & 0x80000000)
+#define BP_PWM_CTRL_CLKGATE         30
+#define BM_PWM_CTRL_CLKGATE         0x40000000
+#define BF_PWM_CTRL_CLKGATE(v)      (((v) << 30) & 0x40000000)
+#define BP_PWM_CTRL_PWM4_PRESENT    29
+#define BM_PWM_CTRL_PWM4_PRESENT    0x20000000
+#define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000)
+#define BP_PWM_CTRL_PWM3_PRESENT    28
+#define BM_PWM_CTRL_PWM3_PRESENT    0x10000000
+#define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000)
+#define BP_PWM_CTRL_PWM2_PRESENT    27
+#define BM_PWM_CTRL_PWM2_PRESENT    0x8000000
+#define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000)
+#define BP_PWM_CTRL_PWM1_PRESENT    26
+#define BM_PWM_CTRL_PWM1_PRESENT    0x4000000
+#define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000)
+#define BP_PWM_CTRL_PWM0_PRESENT    25
+#define BM_PWM_CTRL_PWM0_PRESENT    0x2000000
+#define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000)
+#define BP_PWM_CTRL_PWM4_ENABLE     4
+#define BM_PWM_CTRL_PWM4_ENABLE     0x10
+#define BF_PWM_CTRL_PWM4_ENABLE(v)  (((v) << 4) & 0x10)
+#define BP_PWM_CTRL_PWM3_ENABLE     3
+#define BM_PWM_CTRL_PWM3_ENABLE     0x8
+#define BF_PWM_CTRL_PWM3_ENABLE(v)  (((v) << 3) & 0x8)
+#define BP_PWM_CTRL_PWM2_ENABLE     2
+#define BM_PWM_CTRL_PWM2_ENABLE     0x4
+#define BF_PWM_CTRL_PWM2_ENABLE(v)  (((v) << 2) & 0x4)
+#define BP_PWM_CTRL_PWM1_ENABLE     1
+#define BM_PWM_CTRL_PWM1_ENABLE     0x2
+#define BF_PWM_CTRL_PWM1_ENABLE(v)  (((v) << 1) & 0x2)
+#define BP_PWM_CTRL_PWM0_ENABLE     0
+#define BM_PWM_CTRL_PWM0_ENABLE     0x1
+#define BF_PWM_CTRL_PWM0_ENABLE(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PWM_ACTIVEn
+ * Address: 0x10+n*0x20
+ * SCT: yes
+*/
+#define HW_PWM_ACTIVEn(n)           (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0))
+#define HW_PWM_ACTIVEn_SET(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4))
+#define HW_PWM_ACTIVEn_CLR(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8))
+#define HW_PWM_ACTIVEn_TOG(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc))
+#define BP_PWM_ACTIVEn_INACTIVE     16
+#define BM_PWM_ACTIVEn_INACTIVE     0xffff0000
+#define BF_PWM_ACTIVEn_INACTIVE(v)  (((v) << 16) & 0xffff0000)
+#define BP_PWM_ACTIVEn_ACTIVE       0
+#define BM_PWM_ACTIVEn_ACTIVE       0xffff
+#define BF_PWM_ACTIVEn_ACTIVE(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_PWM_PERIODn
+ * Address: 0x20+n*0x20
+ * SCT: yes
+*/
+#define HW_PWM_PERIODn(n)                   (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0))
+#define HW_PWM_PERIODn_SET(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4))
+#define HW_PWM_PERIODn_CLR(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8))
+#define HW_PWM_PERIODn_TOG(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc))
+#define BP_PWM_PERIODn_MATT                 23
+#define BM_PWM_PERIODn_MATT                 0x800000
+#define BF_PWM_PERIODn_MATT(v)              (((v) << 23) & 0x800000)
+#define BP_PWM_PERIODn_CDIV                 20
+#define BM_PWM_PERIODn_CDIV                 0x700000
+#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
+#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
+#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
+#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
+#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
+#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
+#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
+#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
+#define BF_PWM_PERIODn_CDIV(v)              (((v) << 20) & 0x700000)
+#define BF_PWM_PERIODn_CDIV_V(v)            ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000)
+#define BP_PWM_PERIODn_INACTIVE_STATE       18
+#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
+#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
+#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
+#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) << 18) & 0xc0000)
+#define BF_PWM_PERIODn_INACTIVE_STATE_V(v)  ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000)
+#define BP_PWM_PERIODn_ACTIVE_STATE         16
+#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
+#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
+#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
+#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
+#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) << 16) & 0x30000)
+#define BF_PWM_PERIODn_ACTIVE_STATE_V(v)    ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000)
+#define BP_PWM_PERIODn_PERIOD               0
+#define BM_PWM_PERIODn_PERIOD               0xffff
+#define BF_PWM_PERIODn_PERIOD(v)            (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3600__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h
new file mode 100644
index 0000000000..8661e75706
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-rtc.h
@@ -0,0 +1,304 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__RTC__H__
+#define __HEADERGEN__STMP3600__RTC__H__
+
+#define REGS_RTC_BASE (0x8005c000)
+
+#define REGS_RTC_VERSION "2.3.0"
+
+/**
+ * Register: HW_RTC_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_RTC_CTRL                                 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0))
+#define HW_RTC_CTRL_SET                             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4))
+#define HW_RTC_CTRL_CLR                             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8))
+#define HW_RTC_CTRL_TOG                             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc))
+#define BP_RTC_CTRL_SFTRST                          31
+#define BM_RTC_CTRL_SFTRST                          0x80000000
+#define BF_RTC_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
+#define BP_RTC_CTRL_CLKGATE                         30
+#define BM_RTC_CTRL_CLKGATE                         0x40000000
+#define BF_RTC_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
+#define BP_RTC_CTRL_CLKDIV                          24
+#define BM_RTC_CTRL_CLKDIV                          0xf000000
+#define BF_RTC_CTRL_CLKDIV(v)                       (((v) << 24) & 0xf000000)
+#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG            6
+#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG            0x40
+#define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NORMAL    0x0
+#define BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__NO_COPY   0x1
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v)         (((v) << 6) & 0x40)
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG_V(v)       ((BV_RTC_CTRL_SUPPRESS_COPY2ANALOG__##v << 6) & 0x40)
+#define BP_RTC_CTRL_FORCE_UPDATE                    5
+#define BM_RTC_CTRL_FORCE_UPDATE                    0x20
+#define BV_RTC_CTRL_FORCE_UPDATE__NORMAL            0x0
+#define BV_RTC_CTRL_FORCE_UPDATE__FORCE_COPY        0x1
+#define BF_RTC_CTRL_FORCE_UPDATE(v)                 (((v) << 5) & 0x20)
+#define BF_RTC_CTRL_FORCE_UPDATE_V(v)               ((BV_RTC_CTRL_FORCE_UPDATE__##v << 5) & 0x20)
+#define BP_RTC_CTRL_WATCHDOGEN                      4
+#define BM_RTC_CTRL_WATCHDOGEN                      0x10
+#define BF_RTC_CTRL_WATCHDOGEN(v)                   (((v) << 4) & 0x10)
+#define BP_RTC_CTRL_ONEMSEC_IRQ                     3
+#define BM_RTC_CTRL_ONEMSEC_IRQ                     0x8
+#define BF_RTC_CTRL_ONEMSEC_IRQ(v)                  (((v) << 3) & 0x8)
+#define BP_RTC_CTRL_ALARM_IRQ                       2
+#define BM_RTC_CTRL_ALARM_IRQ                       0x4
+#define BF_RTC_CTRL_ALARM_IRQ(v)                    (((v) << 2) & 0x4)
+#define BP_RTC_CTRL_ONEMSEC_IRQ_EN                  1
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN                  0x2
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)               (((v) << 1) & 0x2)
+#define BP_RTC_CTRL_ALARM_IRQ_EN                    0
+#define BM_RTC_CTRL_ALARM_IRQ_EN                    0x1
+#define BF_RTC_CTRL_ALARM_IRQ_EN(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_RTC_STAT                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10))
+#define BP_RTC_STAT_RTC_PRESENT             31
+#define BM_RTC_STAT_RTC_PRESENT             0x80000000
+#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) << 31) & 0x80000000)
+#define BP_RTC_STAT_ALARM_PRESENT           30
+#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
+#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) << 30) & 0x40000000)
+#define BP_RTC_STAT_WATCHDOG_PRESENT        29
+#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
+#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) << 29) & 0x20000000)
+#define BP_RTC_STAT_XTAL32768_PRESENT       28
+#define BM_RTC_STAT_XTAL32768_PRESENT       0x10000000
+#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) << 28) & 0x10000000)
+#define BP_RTC_STAT_STALE_REGS              16
+#define BM_RTC_STAT_STALE_REGS              0x3f0000
+#define BF_RTC_STAT_STALE_REGS(v)           (((v) << 16) & 0x3f0000)
+#define BP_RTC_STAT_NEW_REGS                8
+#define BM_RTC_STAT_NEW_REGS                0x3f00
+#define BF_RTC_STAT_NEW_REGS(v)             (((v) << 8) & 0x3f00)
+#define BP_RTC_STAT_FUSE_UNLOCK             1
+#define BM_RTC_STAT_FUSE_UNLOCK             0x2
+#define BF_RTC_STAT_FUSE_UNLOCK(v)          (((v) << 1) & 0x2)
+#define BP_RTC_STAT_FUSE_DONE               0
+#define BM_RTC_STAT_FUSE_DONE               0x1
+#define BF_RTC_STAT_FUSE_DONE(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_MILLISECONDS
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_RTC_MILLISECONDS             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0))
+#define HW_RTC_MILLISECONDS_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4))
+#define HW_RTC_MILLISECONDS_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8))
+#define HW_RTC_MILLISECONDS_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc))
+#define BP_RTC_MILLISECONDS_COUNT       0
+#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
+#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_SECONDS
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_RTC_SECONDS          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0))
+#define HW_RTC_SECONDS_SET      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4))
+#define HW_RTC_SECONDS_CLR      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8))
+#define HW_RTC_SECONDS_TOG      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc))
+#define BP_RTC_SECONDS_COUNT    0
+#define BM_RTC_SECONDS_COUNT    0xffffffff
+#define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_ALARM
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_RTC_ALARM            (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0))
+#define HW_RTC_ALARM_SET        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4))
+#define HW_RTC_ALARM_CLR        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8))
+#define HW_RTC_ALARM_TOG        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc))
+#define BP_RTC_ALARM_VALUE      0
+#define BM_RTC_ALARM_VALUE      0xffffffff
+#define BF_RTC_ALARM_VALUE(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_WATCHDOG
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_RTC_WATCHDOG             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0))
+#define HW_RTC_WATCHDOG_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4))
+#define HW_RTC_WATCHDOG_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8))
+#define HW_RTC_WATCHDOG_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc))
+#define BP_RTC_WATCHDOG_COUNT       0
+#define BM_RTC_WATCHDOG_COUNT       0xffffffff
+#define BF_RTC_WATCHDOG_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT0
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT0                                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0))
+#define HW_RTC_PERSISTENT0_SET                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4))
+#define HW_RTC_PERSISTENT0_CLR                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8))
+#define HW_RTC_PERSISTENT0_TOG                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc))
+#define BP_RTC_PERSISTENT0_GENERAL                          16
+#define BM_RTC_PERSISTENT0_GENERAL                          0xffff0000
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_BOOT              0x8000
+#define BV_RTC_PERSISTENT0_GENERAL__ENUMERATE_500MA_TWICE   0x4000
+#define BV_RTC_PERSISTENT0_GENERAL__USB_BOOT_PLAYER_MODE    0x2000
+#define BV_RTC_PERSISTENT0_GENERAL__SKIP_CHECKDISK          0x1000
+#define BV_RTC_PERSISTENT0_GENERAL__USB_LOW_POWER_MODE      0x800
+#define BV_RTC_PERSISTENT0_GENERAL__OTG_HNP_BIT             0x400
+#define BV_RTC_PERSISTENT0_GENERAL__OTG_ATL_ROLE_BIT        0x200
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_HI             0x100
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_CS_LO             0x80
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_3             0x40
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_2             0x20
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_1             0x10
+#define BV_RTC_PERSISTENT0_GENERAL__SDRAM_NDX_0             0x8
+#define BV_RTC_PERSISTENT0_GENERAL__ETM_ENABLE              0x4
+#define BF_RTC_PERSISTENT0_GENERAL(v)                       (((v) << 16) & 0xffff0000)
+#define BF_RTC_PERSISTENT0_GENERAL_V(v)                     ((BV_RTC_PERSISTENT0_GENERAL__##v << 16) & 0xffff0000)
+#define BP_RTC_PERSISTENT0_DCDC_CTRL                        6
+#define BM_RTC_PERSISTENT0_DCDC_CTRL                        0xffc0
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SD_PRESENT            0x200
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__LOWBAT_3P0            0x100
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SELFBIAS_PWRUP        0x80
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__AUTO_RESTART          0x40
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DETECT_LOWBAT         0x20
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS1            0x10
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DROP_BIAS2            0x8
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE                 0x4
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__DISABLE_XTALSTOP      0x2
+#define BV_RTC_PERSISTENT0_DCDC_CTRL__SPARE2                0x1
+#define BF_RTC_PERSISTENT0_DCDC_CTRL(v)                     (((v) << 6) & 0xffc0)
+#define BF_RTC_PERSISTENT0_DCDC_CTRL_V(v)                   ((BV_RTC_PERSISTENT0_DCDC_CTRL__##v << 6) & 0xffc0)
+#define BP_RTC_PERSISTENT0_XTAL32_PDOWN                     5
+#define BM_RTC_PERSISTENT0_XTAL32_PDOWN                     0x20
+#define BF_RTC_PERSISTENT0_XTAL32_PDOWN(v)                  (((v) << 5) & 0x20)
+#define BP_RTC_PERSISTENT0_XTAL24_PDOWN                     4
+#define BM_RTC_PERSISTENT0_XTAL24_PDOWN                     0x10
+#define BF_RTC_PERSISTENT0_XTAL24_PDOWN(v)                  (((v) << 4) & 0x10)
+#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN                    3
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN                    0x8
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)                 (((v) << 3) & 0x8)
+#define BP_RTC_PERSISTENT0_ALARM_EN                         2
+#define BM_RTC_PERSISTENT0_ALARM_EN                         0x4
+#define BF_RTC_PERSISTENT0_ALARM_EN(v)                      (((v) << 2) & 0x4)
+#define BP_RTC_PERSISTENT0_ALARM_WAKE                       1
+#define BM_RTC_PERSISTENT0_ALARM_WAKE                       0x2
+#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)                    (((v) << 1) & 0x2)
+#define BP_RTC_PERSISTENT0_CLOCKSOURCE                      0
+#define BM_RTC_PERSISTENT0_CLOCKSOURCE                      0x1
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)                   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_PERSISTENT1
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT1              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0))
+#define HW_RTC_PERSISTENT1_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4))
+#define HW_RTC_PERSISTENT1_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8))
+#define HW_RTC_PERSISTENT1_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc))
+#define BP_RTC_PERSISTENT1_GENERAL      0
+#define BM_RTC_PERSISTENT1_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT1_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT2
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT2                      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0))
+#define HW_RTC_PERSISTENT2_SET                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4))
+#define HW_RTC_PERSISTENT2_CLR                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8))
+#define HW_RTC_PERSISTENT2_TOG                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc))
+#define BP_RTC_PERSISTENT2_SRAM_LO              0
+#define BM_RTC_PERSISTENT2_SRAM_LO              0xffffffff
+#define BV_RTC_PERSISTENT2_SRAM_LO__WARM_BOOT   0x80000000
+#define BF_RTC_PERSISTENT2_SRAM_LO(v)           (((v) << 0) & 0xffffffff)
+#define BF_RTC_PERSISTENT2_SRAM_LO_V(v)         ((BV_RTC_PERSISTENT2_SRAM_LO__##v << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT3
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT3              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0))
+#define HW_RTC_PERSISTENT3_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4))
+#define HW_RTC_PERSISTENT3_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8))
+#define HW_RTC_PERSISTENT3_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc))
+#define BP_RTC_PERSISTENT3_SRAM_HI      0
+#define BM_RTC_PERSISTENT3_SRAM_HI      0xffffffff
+#define BF_RTC_PERSISTENT3_SRAM_HI(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_DEBUG
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_RTC_DEBUG                        (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0))
+#define HW_RTC_DEBUG_SET                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4))
+#define HW_RTC_DEBUG_CLR                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8))
+#define HW_RTC_DEBUG_TOG                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc))
+#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK    1
+#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK    0x2
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2)
+#define BP_RTC_DEBUG_WATCHDOG_RESET         0
+#define BM_RTC_DEBUG_WATCHDOG_RESET         0x1
+#define BF_RTC_DEBUG_WATCHDOG_RESET(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_UNLOCK
+ * Address: 0x200
+ * SCT: yes
+*/
+#define HW_RTC_UNLOCK           (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x0))
+#define HW_RTC_UNLOCK_SET       (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x4))
+#define HW_RTC_UNLOCK_CLR       (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0x8))
+#define HW_RTC_UNLOCK_TOG       (*(volatile unsigned long *)(REGS_RTC_BASE + 0x200 + 0xc))
+#define BP_RTC_UNLOCK_KEY       0
+#define BM_RTC_UNLOCK_KEY       0xffffffff
+#define BV_RTC_UNLOCK_KEY__VAL  0xc6a83957
+#define BF_RTC_UNLOCK_KEY(v)    (((v) << 0) & 0xffffffff)
+#define BF_RTC_UNLOCK_KEY_V(v)  ((BV_RTC_UNLOCK_KEY__##v << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_LASERFUSEn
+ * Address: 0x300+n*0x10
+ * SCT: yes
+*/
+#define HW_RTC_LASERFUSEn(n)        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x0))
+#define HW_RTC_LASERFUSEn_SET(n)    (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x4))
+#define HW_RTC_LASERFUSEn_CLR(n)    (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0x8))
+#define HW_RTC_LASERFUSEn_TOG(n)    (*(volatile unsigned long *)(REGS_RTC_BASE + 0x300+(n)*0x10 + 0xc))
+#define BP_RTC_LASERFUSEn_BITS      0
+#define BM_RTC_LASERFUSEn_BITS      0xffffffff
+#define BF_RTC_LASERFUSEn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3600__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h
new file mode 100644
index 0000000000..32e88b37cd
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-spdif.h
@@ -0,0 +1,165 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__SPDIF__H__
+#define __HEADERGEN__STMP3600__SPDIF__H__
+
+#define REGS_SPDIF_BASE (0x80054000)
+
+#define REGS_SPDIF_VERSION "2.3.0"
+
+/**
+ * Register: HW_SPDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SPDIF_CTRL                       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0))
+#define HW_SPDIF_CTRL_SET                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4))
+#define HW_SPDIF_CTRL_CLR                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8))
+#define HW_SPDIF_CTRL_TOG                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc))
+#define BP_SPDIF_CTRL_SFTRST                31
+#define BM_SPDIF_CTRL_SFTRST                0x80000000
+#define BF_SPDIF_CTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
+#define BP_SPDIF_CTRL_CLKGATE               30
+#define BM_SPDIF_CTRL_CLKGATE               0x40000000
+#define BF_SPDIF_CTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
+#define BP_SPDIF_CTRL_DMAWAIT_COUNT         16
+#define BM_SPDIF_CTRL_DMAWAIT_COUNT         0x1f0000
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)      (((v) << 16) & 0x1f0000)
+#define BP_SPDIF_CTRL_WAIT_END_XFER         5
+#define BM_SPDIF_CTRL_WAIT_END_XFER         0x20
+#define BF_SPDIF_CTRL_WAIT_END_XFER(v)      (((v) << 5) & 0x20)
+#define BP_SPDIF_CTRL_WORD_LENGTH           4
+#define BM_SPDIF_CTRL_WORD_LENGTH           0x10
+#define BF_SPDIF_CTRL_WORD_LENGTH(v)        (((v) << 4) & 0x10)
+#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    3
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    0x8
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
+#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     2
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     0x4
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)  (((v) << 2) & 0x4)
+#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     1
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     0x2
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)  (((v) << 1) & 0x2)
+#define BP_SPDIF_CTRL_RUN                   0
+#define BM_SPDIF_CTRL_RUN                   0x1
+#define BF_SPDIF_CTRL_RUN(v)                (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_SPDIF_STAT               (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10))
+#define BP_SPDIF_STAT_PRESENT       31
+#define BM_SPDIF_STAT_PRESENT       0x80000000
+#define BF_SPDIF_STAT_PRESENT(v)    (((v) << 31) & 0x80000000)
+#define BP_SPDIF_STAT_END_XFER      0
+#define BM_SPDIF_STAT_END_XFER      0x1
+#define BF_SPDIF_STAT_END_XFER(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_FRAMECTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_SPDIF_FRAMECTRL              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0))
+#define HW_SPDIF_FRAMECTRL_SET          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4))
+#define HW_SPDIF_FRAMECTRL_CLR          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8))
+#define HW_SPDIF_FRAMECTRL_TOG          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc))
+#define BP_SPDIF_FRAMECTRL_V_CONFIG     17
+#define BM_SPDIF_FRAMECTRL_V_CONFIG     0x20000
+#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)  (((v) << 17) & 0x20000)
+#define BP_SPDIF_FRAMECTRL_AUTO_MUTE    16
+#define BM_SPDIF_FRAMECTRL_AUTO_MUTE    0x10000
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
+#define BP_SPDIF_FRAMECTRL_USER_DATA    14
+#define BM_SPDIF_FRAMECTRL_USER_DATA    0x4000
+#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
+#define BP_SPDIF_FRAMECTRL_V            13
+#define BM_SPDIF_FRAMECTRL_V            0x2000
+#define BF_SPDIF_FRAMECTRL_V(v)         (((v) << 13) & 0x2000)
+#define BP_SPDIF_FRAMECTRL_L            12
+#define BM_SPDIF_FRAMECTRL_L            0x1000
+#define BF_SPDIF_FRAMECTRL_L(v)         (((v) << 12) & 0x1000)
+#define BP_SPDIF_FRAMECTRL_CC           4
+#define BM_SPDIF_FRAMECTRL_CC           0x7f0
+#define BF_SPDIF_FRAMECTRL_CC(v)        (((v) << 4) & 0x7f0)
+#define BP_SPDIF_FRAMECTRL_PRE          3
+#define BM_SPDIF_FRAMECTRL_PRE          0x8
+#define BF_SPDIF_FRAMECTRL_PRE(v)       (((v) << 3) & 0x8)
+#define BP_SPDIF_FRAMECTRL_COPY         2
+#define BM_SPDIF_FRAMECTRL_COPY         0x4
+#define BF_SPDIF_FRAMECTRL_COPY(v)      (((v) << 2) & 0x4)
+#define BP_SPDIF_FRAMECTRL_AUDIO        1
+#define BM_SPDIF_FRAMECTRL_AUDIO        0x2
+#define BF_SPDIF_FRAMECTRL_AUDIO(v)     (((v) << 1) & 0x2)
+#define BP_SPDIF_FRAMECTRL_PRO          0
+#define BM_SPDIF_FRAMECTRL_PRO          0x1
+#define BF_SPDIF_FRAMECTRL_PRO(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_SRR
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_SPDIF_SRR                (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0))
+#define HW_SPDIF_SRR_SET            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4))
+#define HW_SPDIF_SRR_CLR            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8))
+#define HW_SPDIF_SRR_TOG            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc))
+#define BP_SPDIF_SRR_BASEMULT       28
+#define BM_SPDIF_SRR_BASEMULT       0x70000000
+#define BF_SPDIF_SRR_BASEMULT(v)    (((v) << 28) & 0x70000000)
+#define BP_SPDIF_SRR_RATE           0
+#define BM_SPDIF_SRR_RATE           0xfffff
+#define BF_SPDIF_SRR_RATE(v)        (((v) << 0) & 0xfffff)
+
+/**
+ * Register: HW_SPDIF_DEBUG
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_SPDIF_DEBUG                  (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40))
+#define BP_SPDIF_DEBUG_DMA_PREQ         1
+#define BM_SPDIF_DEBUG_DMA_PREQ         0x2
+#define BF_SPDIF_DEBUG_DMA_PREQ(v)      (((v) << 1) & 0x2)
+#define BP_SPDIF_DEBUG_FIFO_STATUS      0
+#define BM_SPDIF_DEBUG_FIFO_STATUS      0x1
+#define BF_SPDIF_DEBUG_FIFO_STATUS(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_DATA
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_SPDIF_DATA           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0))
+#define HW_SPDIF_DATA_SET       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4))
+#define HW_SPDIF_DATA_CLR       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8))
+#define HW_SPDIF_DATA_TOG       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc))
+#define BP_SPDIF_DATA_HIGH      16
+#define BM_SPDIF_DATA_HIGH      0xffff0000
+#define BF_SPDIF_DATA_HIGH(v)   (((v) << 16) & 0xffff0000)
+#define BP_SPDIF_DATA_LOW       0
+#define BM_SPDIF_DATA_LOW       0xffff
+#define BF_SPDIF_DATA_LOW(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3600__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h
new file mode 100644
index 0000000000..2c589f5256
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-ssp.h
@@ -0,0 +1,541 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__SSP__H__
+#define __HEADERGEN__STMP3600__SSP__H__
+
+#define REGS_SSP_BASE (0x80010000)
+
+#define REGS_SSP_VERSION "2.3.0"
+
+/**
+ * Register: HW_SSP_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SSP_CTRL0                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x0))
+#define HW_SSP_CTRL0_SET                    (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x4))
+#define HW_SSP_CTRL0_CLR                    (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0x8))
+#define HW_SSP_CTRL0_TOG                    (*(volatile unsigned long *)(REGS_SSP_BASE + 0x0 + 0xc))
+#define BP_SSP_CTRL0_SFTRST                 31
+#define BM_SSP_CTRL0_SFTRST                 0x80000000
+#define BF_SSP_CTRL0_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_SSP_CTRL0_CLKGATE                30
+#define BM_SSP_CTRL0_CLKGATE                0x40000000
+#define BF_SSP_CTRL0_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_SSP_CTRL0_RUN                    29
+#define BM_SSP_CTRL0_RUN                    0x20000000
+#define BF_SSP_CTRL0_RUN(v)                 (((v) << 29) & 0x20000000)
+#define BP_SSP_CTRL0_HALF_DUPLEX            28
+#define BM_SSP_CTRL0_HALF_DUPLEX            0x10000000
+#define BF_SSP_CTRL0_HALF_DUPLEX(v)         (((v) << 28) & 0x10000000)
+#define BP_SSP_CTRL0_LOCK_CS                27
+#define BM_SSP_CTRL0_LOCK_CS                0x8000000
+#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) << 27) & 0x8000000)
+#define BP_SSP_CTRL0_IGNORE_CRC             26
+#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
+#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) << 26) & 0x4000000)
+#define BP_SSP_CTRL0_READ                   25
+#define BM_SSP_CTRL0_READ                   0x2000000
+#define BF_SSP_CTRL0_READ(v)                (((v) << 25) & 0x2000000)
+#define BP_SSP_CTRL0_DATA_XFER              24
+#define BM_SSP_CTRL0_DATA_XFER              0x1000000
+#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) << 24) & 0x1000000)
+#define BP_SSP_CTRL0_SDIO_IRQ               23
+#define BM_SSP_CTRL0_SDIO_IRQ               0x800000
+#define BF_SSP_CTRL0_SDIO_IRQ(v)            (((v) << 23) & 0x800000)
+#define BP_SSP_CTRL0_BUS_WIDTH              22
+#define BM_SSP_CTRL0_BUS_WIDTH              0x400000
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
+#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) << 22) & 0x400000)
+#define BF_SSP_CTRL0_BUS_WIDTH_V(v)         ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0x400000)
+#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) << 21) & 0x200000)
+#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
+#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
+#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) << 20) & 0x100000)
+#define BP_SSP_CTRL0_LONG_RESP              19
+#define BM_SSP_CTRL0_LONG_RESP              0x80000
+#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) << 19) & 0x80000)
+#define BP_SSP_CTRL0_CHECK_RESP             18
+#define BM_SSP_CTRL0_CHECK_RESP             0x40000
+#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) << 18) & 0x40000)
+#define BP_SSP_CTRL0_GET_RESP               17
+#define BM_SSP_CTRL0_GET_RESP               0x20000
+#define BF_SSP_CTRL0_GET_RESP(v)            (((v) << 17) & 0x20000)
+#define BP_SSP_CTRL0_ENABLE                 16
+#define BM_SSP_CTRL0_ENABLE                 0x10000
+#define BF_SSP_CTRL0_ENABLE(v)              (((v) << 16) & 0x10000)
+#define BP_SSP_CTRL0_XFER_COUNT             0
+#define BM_SSP_CTRL0_XFER_COUNT             0xffff
+#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_SSP_CMD0
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SSP_CMD0                                 (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x0))
+#define HW_SSP_CMD0_SET                             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x4))
+#define HW_SSP_CMD0_CLR                             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0x8))
+#define HW_SSP_CMD0_TOG                             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x10 + 0xc))
+#define BP_SSP_CMD0_CMD                             0
+#define BM_SSP_CMD0_CMD                             0xff
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
+#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
+#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
+#define BF_SSP_CMD0_CMD(v)                          (((v) << 0) & 0xff)
+#define BF_SSP_CMD0_CMD_V(v)                        ((BV_SSP_CMD0_CMD__##v << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_CMD1
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_SSP_CMD1             (*(volatile unsigned long *)(REGS_SSP_BASE + 0x20))
+#define BP_SSP_CMD1_CMD_ARG     0
+#define BM_SSP_CMD1_CMD_ARG     0xffffffff
+#define BF_SSP_CMD1_CMD_ARG(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_COMPREF
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_SSP_COMPREF              (*(volatile unsigned long *)(REGS_SSP_BASE + 0x30))
+#define BP_SSP_COMPREF_REFERENCE    0
+#define BM_SSP_COMPREF_REFERENCE    0xffffffff
+#define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_COMPMASK
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_SSP_COMPMASK         (*(volatile unsigned long *)(REGS_SSP_BASE + 0x40))
+#define BP_SSP_COMPMASK_MASK    0
+#define BM_SSP_COMPMASK_MASK    0xffffffff
+#define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_TIMING
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_SSP_TIMING                   (*(volatile unsigned long *)(REGS_SSP_BASE + 0x50))
+#define BP_SSP_TIMING_TIMEOUT           16
+#define BM_SSP_TIMING_TIMEOUT           0xffff0000
+#define BF_SSP_TIMING_TIMEOUT(v)        (((v) << 16) & 0xffff0000)
+#define BP_SSP_TIMING_CLOCK_DIVIDE      8
+#define BM_SSP_TIMING_CLOCK_DIVIDE      0xff00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v)   (((v) << 8) & 0xff00)
+#define BP_SSP_TIMING_CLOCK_RATE        0
+#define BM_SSP_TIMING_CLOCK_RATE        0xff
+#define BF_SSP_TIMING_CLOCK_RATE(v)     (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_CTRL1
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_SSP_CTRL1                            (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x0))
+#define HW_SSP_CTRL1_SET                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x4))
+#define HW_SSP_CTRL1_CLR                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0x8))
+#define HW_SSP_CTRL1_TOG                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x60 + 0xc))
+#define BP_SSP_CTRL1_SDIO_IRQ                   31
+#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
+#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) << 31) & 0x80000000)
+#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
+#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
+#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) << 30) & 0x40000000)
+#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
+#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) << 29) & 0x20000000)
+#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) << 28) & 0x10000000)
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) << 27) & 0x8000000)
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) << 26) & 0x4000000)
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) << 25) & 0x2000000)
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) << 24) & 0x1000000)
+#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
+#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) << 23) & 0x800000)
+#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) << 22) & 0x400000)
+#define BP_SSP_CTRL1_XMIT_IRQ                   21
+#define BM_SSP_CTRL1_XMIT_IRQ                   0x200000
+#define BF_SSP_CTRL1_XMIT_IRQ(v)                (((v) << 21) & 0x200000)
+#define BP_SSP_CTRL1_XMIT_IRQ_EN                20
+#define BM_SSP_CTRL1_XMIT_IRQ_EN                0x100000
+#define BF_SSP_CTRL1_XMIT_IRQ_EN(v)             (((v) << 20) & 0x100000)
+#define BP_SSP_CTRL1_RECV_IRQ                   19
+#define BM_SSP_CTRL1_RECV_IRQ                   0x80000
+#define BF_SSP_CTRL1_RECV_IRQ(v)                (((v) << 19) & 0x80000)
+#define BP_SSP_CTRL1_RECV_IRQ_EN                18
+#define BM_SSP_CTRL1_RECV_IRQ_EN                0x40000
+#define BF_SSP_CTRL1_RECV_IRQ_EN(v)             (((v) << 18) & 0x40000)
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) << 17) & 0x20000)
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) << 16) & 0x10000)
+#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ            15
+#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ            0x8000
+#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ(v)         (((v) << 15) & 0x8000)
+#define BP_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         14
+#define BM_SSP_CTRL1_RECV_OVRFLW_IRQ_EN         0x4000
+#define BF_SSP_CTRL1_RECV_OVRFLW_IRQ_EN(v)      (((v) << 14) & 0x4000)
+#define BP_SSP_CTRL1_DMA_ENABLE                 13
+#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
+#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) << 13) & 0x2000)
+#define BP_SSP_CTRL1_LOOPBACK                   12
+#define BM_SSP_CTRL1_LOOPBACK                   0x1000
+#define BF_SSP_CTRL1_LOOPBACK(v)                (((v) << 12) & 0x1000)
+#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) << 11) & 0x800)
+#define BP_SSP_CTRL1_PHASE                      10
+#define BM_SSP_CTRL1_PHASE                      0x400
+#define BF_SSP_CTRL1_PHASE(v)                   (((v) << 10) & 0x400)
+#define BP_SSP_CTRL1_POLARITY                   9
+#define BM_SSP_CTRL1_POLARITY                   0x200
+#define BF_SSP_CTRL1_POLARITY(v)                (((v) << 9) & 0x200)
+#define BP_SSP_CTRL1_SLAVE_MODE                 8
+#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
+#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) << 8) & 0x100)
+#define BP_SSP_CTRL1_WORD_LENGTH                4
+#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
+#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) << 4) & 0xf0)
+#define BF_SSP_CTRL1_WORD_LENGTH_V(v)           ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0)
+#define BP_SSP_CTRL1_SSP_MODE                   0
+#define BM_SSP_CTRL1_SSP_MODE                   0xf
+#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
+#define BV_SSP_CTRL1_SSP_MODE__MICROWIRE        0x2
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
+#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) << 0) & 0xf)
+#define BF_SSP_CTRL1_SSP_MODE_V(v)              ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf)
+
+/**
+ * Register: HW_SSP_DATA
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_SSP_DATA         (*(volatile unsigned long *)(REGS_SSP_BASE + 0x70))
+#define BP_SSP_DATA_DATA    0
+#define BM_SSP_DATA_DATA    0xffffffff
+#define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP0
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_SSP_SDRESP0          (*(volatile unsigned long *)(REGS_SSP_BASE + 0x80))
+#define BP_SSP_SDRESP0_RESP0    0
+#define BM_SSP_SDRESP0_RESP0    0xffffffff
+#define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP1
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_SSP_SDRESP1          (*(volatile unsigned long *)(REGS_SSP_BASE + 0x90))
+#define BP_SSP_SDRESP1_RESP1    0
+#define BM_SSP_SDRESP1_RESP1    0xffffffff
+#define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP2
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_SSP_SDRESP2          (*(volatile unsigned long *)(REGS_SSP_BASE + 0xa0))
+#define BP_SSP_SDRESP2_RESP2    0
+#define BM_SSP_SDRESP2_RESP2    0xffffffff
+#define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP3
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_SSP_SDRESP3          (*(volatile unsigned long *)(REGS_SSP_BASE + 0xb0))
+#define BP_SSP_SDRESP3_RESP3    0
+#define BM_SSP_SDRESP3_RESP3    0xffffffff
+#define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_STATUS
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_SSP_STATUS                       (*(volatile unsigned long *)(REGS_SSP_BASE + 0xc0))
+#define BP_SSP_STATUS_PRESENT               31
+#define BM_SSP_STATUS_PRESENT               0x80000000
+#define BF_SSP_STATUS_PRESENT(v)            (((v) << 31) & 0x80000000)
+#define BP_SSP_STATUS_MS_PRESENT            30
+#define BM_SSP_STATUS_MS_PRESENT            0x40000000
+#define BF_SSP_STATUS_MS_PRESENT(v)         (((v) << 30) & 0x40000000)
+#define BP_SSP_STATUS_SD_PRESENT            29
+#define BM_SSP_STATUS_SD_PRESENT            0x20000000
+#define BF_SSP_STATUS_SD_PRESENT(v)         (((v) << 29) & 0x20000000)
+#define BP_SSP_STATUS_CARD_DETECT           28
+#define BM_SSP_STATUS_CARD_DETECT           0x10000000
+#define BF_SSP_STATUS_CARD_DETECT(v)        (((v) << 28) & 0x10000000)
+#define BP_SSP_STATUS_RECV_COUNT            24
+#define BM_SSP_STATUS_RECV_COUNT            0xf000000
+#define BF_SSP_STATUS_RECV_COUNT(v)         (((v) << 24) & 0xf000000)
+#define BP_SSP_STATUS_XMIT_COUNT            20
+#define BM_SSP_STATUS_XMIT_COUNT            0xf00000
+#define BF_SSP_STATUS_XMIT_COUNT(v)         (((v) << 20) & 0xf00000)
+#define BP_SSP_STATUS_DMAREQ                19
+#define BM_SSP_STATUS_DMAREQ                0x80000
+#define BF_SSP_STATUS_DMAREQ(v)             (((v) << 19) & 0x80000)
+#define BP_SSP_STATUS_DMAEND                18
+#define BM_SSP_STATUS_DMAEND                0x40000
+#define BF_SSP_STATUS_DMAEND(v)             (((v) << 18) & 0x40000)
+#define BP_SSP_STATUS_SDIO_IRQ              17
+#define BM_SSP_STATUS_SDIO_IRQ              0x20000
+#define BF_SSP_STATUS_SDIO_IRQ(v)           (((v) << 17) & 0x20000)
+#define BP_SSP_STATUS_RESP_CRC_ERR          16
+#define BM_SSP_STATUS_RESP_CRC_ERR          0x10000
+#define BF_SSP_STATUS_RESP_CRC_ERR(v)       (((v) << 16) & 0x10000)
+#define BP_SSP_STATUS_RESP_ERR              15
+#define BM_SSP_STATUS_RESP_ERR              0x8000
+#define BF_SSP_STATUS_RESP_ERR(v)           (((v) << 15) & 0x8000)
+#define BP_SSP_STATUS_RESP_TIMEOUT          14
+#define BM_SSP_STATUS_RESP_TIMEOUT          0x4000
+#define BF_SSP_STATUS_RESP_TIMEOUT(v)       (((v) << 14) & 0x4000)
+#define BP_SSP_STATUS_DATA_CRC_ERR          13
+#define BM_SSP_STATUS_DATA_CRC_ERR          0x2000
+#define BF_SSP_STATUS_DATA_CRC_ERR(v)       (((v) << 13) & 0x2000)
+#define BP_SSP_STATUS_TIMEOUT               12
+#define BM_SSP_STATUS_TIMEOUT               0x1000
+#define BF_SSP_STATUS_TIMEOUT(v)            (((v) << 12) & 0x1000)
+#define BP_SSP_STATUS_RECV_TIMEOUT_STAT     11
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT     0x800
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)  (((v) << 11) & 0x800)
+#define BP_SSP_STATUS_RECV_DATA_STAT        10
+#define BM_SSP_STATUS_RECV_DATA_STAT        0x400
+#define BF_SSP_STATUS_RECV_DATA_STAT(v)     (((v) << 10) & 0x400)
+#define BP_SSP_STATUS_RECV_OVRFLW           9
+#define BM_SSP_STATUS_RECV_OVRFLW           0x200
+#define BF_SSP_STATUS_RECV_OVRFLW(v)        (((v) << 9) & 0x200)
+#define BP_SSP_STATUS_RECV_FULL             8
+#define BM_SSP_STATUS_RECV_FULL             0x100
+#define BF_SSP_STATUS_RECV_FULL(v)          (((v) << 8) & 0x100)
+#define BP_SSP_STATUS_RECV_NOT_EMPTY        7
+#define BM_SSP_STATUS_RECV_NOT_EMPTY        0x80
+#define BF_SSP_STATUS_RECV_NOT_EMPTY(v)     (((v) << 7) & 0x80)
+#define BP_SSP_STATUS_XMIT_NOT_FULL         6
+#define BM_SSP_STATUS_XMIT_NOT_FULL         0x40
+#define BF_SSP_STATUS_XMIT_NOT_FULL(v)      (((v) << 6) & 0x40)
+#define BP_SSP_STATUS_XMIT_EMPTY            5
+#define BM_SSP_STATUS_XMIT_EMPTY            0x20
+#define BF_SSP_STATUS_XMIT_EMPTY(v)         (((v) << 5) & 0x20)
+#define BP_SSP_STATUS_XMIT_UNDRFLW          4
+#define BM_SSP_STATUS_XMIT_UNDRFLW          0x10
+#define BF_SSP_STATUS_XMIT_UNDRFLW(v)       (((v) << 4) & 0x10)
+#define BP_SSP_STATUS_CMD_BUSY              3
+#define BM_SSP_STATUS_CMD_BUSY              0x8
+#define BF_SSP_STATUS_CMD_BUSY(v)           (((v) << 3) & 0x8)
+#define BP_SSP_STATUS_DATA_BUSY             2
+#define BM_SSP_STATUS_DATA_BUSY             0x4
+#define BF_SSP_STATUS_DATA_BUSY(v)          (((v) << 2) & 0x4)
+#define BP_SSP_STATUS_DATA_XFER             1
+#define BM_SSP_STATUS_DATA_XFER             0x2
+#define BF_SSP_STATUS_DATA_XFER(v)          (((v) << 1) & 0x2)
+#define BP_SSP_STATUS_BUSY                  0
+#define BM_SSP_STATUS_BUSY                  0x1
+#define BF_SSP_STATUS_BUSY(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SSP_DEBUG
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_SSP_DEBUG                        (*(volatile unsigned long *)(REGS_SSP_BASE + 0x100))
+#define BP_SSP_DEBUG_DATACRC_ERR            28
+#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) << 28) & 0xf0000000)
+#define BP_SSP_DEBUG_DATA_STALL             27
+#define BM_SSP_DEBUG_DATA_STALL             0x8000000
+#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) << 27) & 0x8000000)
+#define BP_SSP_DEBUG_DAT_SM                 24
+#define BM_SSP_DEBUG_DAT_SM                 0x7000000
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_START      0x1
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
+#define BV_SSP_DEBUG_DAT_SM__DSM_RXDLY      0x6
+#define BF_SSP_DEBUG_DAT_SM(v)              (((v) << 24) & 0x7000000)
+#define BF_SSP_DEBUG_DAT_SM_V(v)            ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000)
+#define BP_SSP_DEBUG_MSTK_SM                20
+#define BM_SSP_DEBUG_MSTK_SM                0xf00000
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xb
+#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) << 20) & 0xf00000)
+#define BF_SSP_DEBUG_MSTK_SM_V(v)           ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000)
+#define BP_SSP_DEBUG_CMD_OE                 19
+#define BM_SSP_DEBUG_CMD_OE                 0x80000
+#define BF_SSP_DEBUG_CMD_OE(v)              (((v) << 19) & 0x80000)
+#define BP_SSP_DEBUG_CMD_SM                 16
+#define BM_SSP_DEBUG_CMD_SM                 0x70000
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
+#define BF_SSP_DEBUG_CMD_SM(v)              (((v) << 16) & 0x70000)
+#define BF_SSP_DEBUG_CMD_SM_V(v)            ((BV_SSP_DEBUG_CMD_SM__##v << 16) & 0x70000)
+#define BP_SSP_DEBUG_CLK_OE                 15
+#define BM_SSP_DEBUG_CLK_OE                 0x8000
+#define BF_SSP_DEBUG_CLK_OE(v)              (((v) << 15) & 0x8000)
+#define BP_SSP_DEBUG_MMC_SM                 12
+#define BM_SSP_DEBUG_MMC_SM                 0x7000
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
+#define BF_SSP_DEBUG_MMC_SM(v)              (((v) << 12) & 0x7000)
+#define BF_SSP_DEBUG_MMC_SM_V(v)            ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0x7000)
+#define BP_SSP_DEBUG_DAT0_OE                11
+#define BM_SSP_DEBUG_DAT0_OE                0x800
+#define BF_SSP_DEBUG_DAT0_OE(v)             (((v) << 11) & 0x800)
+#define BP_SSP_DEBUG_DAT321_OE              10
+#define BM_SSP_DEBUG_DAT321_OE              0x400
+#define BF_SSP_DEBUG_DAT321_OE(v)           (((v) << 10) & 0x400)
+#define BP_SSP_DEBUG_SSP_CMD                9
+#define BM_SSP_DEBUG_SSP_CMD                0x200
+#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) << 9) & 0x200)
+#define BP_SSP_DEBUG_SSP_RESP               8
+#define BM_SSP_DEBUG_SSP_RESP               0x100
+#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) << 8) & 0x100)
+#define BP_SSP_DEBUG_SSP_TXD                4
+#define BM_SSP_DEBUG_SSP_TXD                0xf0
+#define BF_SSP_DEBUG_SSP_TXD(v)             (((v) << 4) & 0xf0)
+#define BP_SSP_DEBUG_SSP_RXD                0
+#define BM_SSP_DEBUG_SSP_RXD                0xf
+#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) << 0) & 0xf)
+
+#endif /* __HEADERGEN__STMP3600__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h
new file mode 100644
index 0000000000..a726662ac8
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-timrot.h
@@ -0,0 +1,267 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__TIMROT__H__
+#define __HEADERGEN__STMP3600__TIMROT__H__
+
+#define REGS_TIMROT_BASE (0x80068000)
+
+#define REGS_TIMROT_VERSION "2.3.0"
+
+/**
+ * Register: HW_TIMROT_ROTCTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_TIMROT_ROTCTRL                       (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0))
+#define HW_TIMROT_ROTCTRL_SET                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4))
+#define HW_TIMROT_ROTCTRL_CLR                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8))
+#define HW_TIMROT_ROTCTRL_TOG                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc))
+#define BP_TIMROT_ROTCTRL_SFTRST                31
+#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
+#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
+#define BP_TIMROT_ROTCTRL_CLKGATE               30
+#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
+#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
+#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) << 29) & 0x20000000)
+#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) << 28) & 0x10000000)
+#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) << 27) & 0x8000000)
+#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) << 26) & 0x4000000)
+#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) << 25) & 0x2000000)
+#define BP_TIMROT_ROTCTRL_STATE                 22
+#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
+#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) << 22) & 0x1c00000)
+#define BP_TIMROT_ROTCTRL_DIVIDER               16
+#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) << 16) & 0x3f0000)
+#define BP_TIMROT_ROTCTRL_RELATIVE              12
+#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
+#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) << 12) & 0x1000)
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) << 10) & 0xc00)
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v)       ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00)
+#define BP_TIMROT_ROTCTRL_POLARITY_B            9
+#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
+#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) << 9) & 0x200)
+#define BP_TIMROT_ROTCTRL_POLARITY_A            8
+#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
+#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) << 8) & 0x100)
+#define BP_TIMROT_ROTCTRL_SELECT_B              4
+#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) << 4) & 0x70)
+#define BF_TIMROT_ROTCTRL_SELECT_B_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70)
+#define BP_TIMROT_ROTCTRL_SELECT_A              0
+#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) << 0) & 0x7)
+#define BF_TIMROT_ROTCTRL_SELECT_A_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7)
+
+/**
+ * Register: HW_TIMROT_ROTCOUNT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_TIMROT_ROTCOUNT              (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10))
+#define BP_TIMROT_ROTCOUNT_UPDOWN       0
+#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_TIMCTRL3
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_TIMROT_TIMCTRL3                          (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0))
+#define HW_TIMROT_TIMCTRL3_SET                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4))
+#define HW_TIMROT_TIMCTRL3_CLR                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8))
+#define HW_TIMROT_TIMCTRL3_TOG                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc))
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) << 16) & 0xf0000)
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)         ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000)
+#define BP_TIMROT_TIMCTRL3_IRQ                      15
+#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
+#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) << 15) & 0x8000)
+#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
+#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
+#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) << 14) & 0x4000)
+#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) << 10) & 0x400)
+#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) << 9) & 0x200)
+#define BP_TIMROT_TIMCTRL3_POLARITY                 8
+#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
+#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) << 8) & 0x100)
+#define BP_TIMROT_TIMCTRL3_UPDATE                   7
+#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
+#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) << 7) & 0x80)
+#define BP_TIMROT_TIMCTRL3_RELOAD                   6
+#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
+#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) << 6) & 0x40)
+#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) << 4) & 0x30)
+#define BF_TIMROT_TIMCTRL3_PRESCALE_V(v)            ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30)
+#define BP_TIMROT_TIMCTRL3_SELECT                   0
+#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
+#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) << 0) & 0xf)
+#define BF_TIMROT_TIMCTRL3_SELECT_V(v)              ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_TIMROT_TIMCOUNT3
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_TIMROT_TIMCOUNT3                         (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90))
+#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
+#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_TIMCOUNTn
+ * Address: 0x30+n*0x20
+ * SCT: no
+*/
+#define HW_TIMROT_TIMCOUNTn(n)                  (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20))
+#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
+#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_TIMCTRLn
+ * Address: 0x20+n*0x20
+ * SCT: yes
+*/
+#define HW_TIMROT_TIMCTRLn(n)                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0))
+#define HW_TIMROT_TIMCTRLn_SET(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4))
+#define HW_TIMROT_TIMCTRLn_CLR(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8))
+#define HW_TIMROT_TIMCTRLn_TOG(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc))
+#define BP_TIMROT_TIMCTRLn_IRQ                  15
+#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
+#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) << 15) & 0x8000)
+#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
+#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
+#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) << 14) & 0x4000)
+#define BP_TIMROT_TIMCTRLn_POLARITY             8
+#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
+#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) << 8) & 0x100)
+#define BP_TIMROT_TIMCTRLn_UPDATE               7
+#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
+#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) << 7) & 0x80)
+#define BP_TIMROT_TIMCTRLn_RELOAD               6
+#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
+#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) << 6) & 0x40)
+#define BP_TIMROT_TIMCTRLn_PRESCALE             4
+#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) << 4) & 0x30)
+#define BF_TIMROT_TIMCTRLn_PRESCALE_V(v)        ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30)
+#define BP_TIMROT_TIMCTRLn_SELECT               0
+#define BM_TIMROT_TIMCTRLn_SELECT               0xf
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
+#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) << 0) & 0xf)
+#define BF_TIMROT_TIMCTRLn_SELECT_V(v)          ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf)
+
+#endif /* __HEADERGEN__STMP3600__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h
new file mode 100644
index 0000000000..62442f3ef3
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-uartapp.h
@@ -0,0 +1,371 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__UARTAPP__H__
+#define __HEADERGEN__STMP3600__UARTAPP__H__
+
+#define REGS_UARTAPP_BASE (0x8006c000)
+
+#define REGS_UARTAPP_VERSION "2.3.0"
+
+/**
+ * Register: HW_UARTAPP_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL0                (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x0))
+#define HW_UARTAPP_CTRL0_SET            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x4))
+#define HW_UARTAPP_CTRL0_CLR            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0x8))
+#define HW_UARTAPP_CTRL0_TOG            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x0 + 0xc))
+#define BP_UARTAPP_CTRL0_SFTRST         31
+#define BM_UARTAPP_CTRL0_SFTRST         0x80000000
+#define BF_UARTAPP_CTRL0_SFTRST(v)      (((v) << 31) & 0x80000000)
+#define BP_UARTAPP_CTRL0_CLKGATE        30
+#define BM_UARTAPP_CTRL0_CLKGATE        0x40000000
+#define BF_UARTAPP_CTRL0_CLKGATE(v)     (((v) << 30) & 0x40000000)
+#define BP_UARTAPP_CTRL0_RUN            28
+#define BM_UARTAPP_CTRL0_RUN            0x10000000
+#define BF_UARTAPP_CTRL0_RUN(v)         (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL0_RX_SOURCE      25
+#define BM_UARTAPP_CTRL0_RX_SOURCE      0x2000000
+#define BF_UARTAPP_CTRL0_RX_SOURCE(v)   (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_CTRL0_RXTO_ENABLE    24
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x1000000
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
+#define BM_UARTAPP_CTRL0_RXTIMEOUT      0xff0000
+#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)   (((v) << 16) & 0xff0000)
+#define BP_UARTAPP_CTRL0_XFER_COUNT     0
+#define BM_UARTAPP_CTRL0_XFER_COUNT     0xffff
+#define BF_UARTAPP_CTRL0_XFER_COUNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL1                (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x0))
+#define HW_UARTAPP_CTRL1_SET            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x4))
+#define HW_UARTAPP_CTRL1_CLR            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0x8))
+#define HW_UARTAPP_CTRL1_TOG            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x10 + 0xc))
+#define BP_UARTAPP_CTRL1_RUN            28
+#define BM_UARTAPP_CTRL1_RUN            0x10000000
+#define BF_UARTAPP_CTRL1_RUN(v)         (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL1_XFER_COUNT     0
+#define BM_UARTAPP_CTRL1_XFER_COUNT     0xffff
+#define BF_UARTAPP_CTRL1_XFER_COUNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL2                            (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x0))
+#define HW_UARTAPP_CTRL2_SET                        (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x4))
+#define HW_UARTAPP_CTRL2_CLR                        (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0x8))
+#define HW_UARTAPP_CTRL2_TOG                        (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x20 + 0xc))
+#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
+#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
+#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) << 31) & 0x80000000)
+#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
+#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
+#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) << 30) & 0x40000000)
+#define BP_UARTAPP_CTRL2_INVERT_TX                  29
+#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
+#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_CTRL2_INVERT_RX                  28
+#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
+#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL2_DMAONERR                   26
+#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
+#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_CTRL2_TXDMAE                     25
+#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
+#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_CTRL2_RXDMAE                     24
+#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
+#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
+#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
+#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) << 20) & 0x700000)
+#define BF_UARTAPP_CTRL2_RXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000)
+#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
+#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
+#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) << 16) & 0x70000)
+#define BF_UARTAPP_CTRL2_TXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000)
+#define BP_UARTAPP_CTRL2_CTSEN                      15
+#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
+#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) << 15) & 0x8000)
+#define BP_UARTAPP_CTRL2_RTSEN                      14
+#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
+#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) << 14) & 0x4000)
+#define BP_UARTAPP_CTRL2_OUT2                       13
+#define BM_UARTAPP_CTRL2_OUT2                       0x2000
+#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) << 13) & 0x2000)
+#define BP_UARTAPP_CTRL2_OUT1                       12
+#define BM_UARTAPP_CTRL2_OUT1                       0x1000
+#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) << 12) & 0x1000)
+#define BP_UARTAPP_CTRL2_RTS                        11
+#define BM_UARTAPP_CTRL2_RTS                        0x800
+#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) << 11) & 0x800)
+#define BP_UARTAPP_CTRL2_DTR                        10
+#define BM_UARTAPP_CTRL2_DTR                        0x400
+#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) << 10) & 0x400)
+#define BP_UARTAPP_CTRL2_RXE                        9
+#define BM_UARTAPP_CTRL2_RXE                        0x200
+#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) << 9) & 0x200)
+#define BP_UARTAPP_CTRL2_TXE                        8
+#define BM_UARTAPP_CTRL2_TXE                        0x100
+#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) << 8) & 0x100)
+#define BP_UARTAPP_CTRL2_LBE                        7
+#define BM_UARTAPP_CTRL2_LBE                        0x80
+#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) << 7) & 0x80)
+#define BP_UARTAPP_CTRL2_SIRLP                      2
+#define BM_UARTAPP_CTRL2_SIRLP                      0x4
+#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) << 2) & 0x4)
+#define BP_UARTAPP_CTRL2_SIREN                      1
+#define BM_UARTAPP_CTRL2_SIREN                      0x2
+#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) << 1) & 0x2)
+#define BP_UARTAPP_CTRL2_UARTEN                     0
+#define BM_UARTAPP_CTRL2_UARTEN                     0x1
+#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_LINECTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_UARTAPP_LINECTRL                 (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x0))
+#define HW_UARTAPP_LINECTRL_SET             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x4))
+#define HW_UARTAPP_LINECTRL_CLR             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0x8))
+#define HW_UARTAPP_LINECTRL_TOG             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x30 + 0xc))
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT     16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT     0xffff0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC    8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC    0x3f00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00)
+#define BP_UARTAPP_LINECTRL_SPS             7
+#define BM_UARTAPP_LINECTRL_SPS             0x80
+#define BF_UARTAPP_LINECTRL_SPS(v)          (((v) << 7) & 0x80)
+#define BP_UARTAPP_LINECTRL_WLEN            5
+#define BM_UARTAPP_LINECTRL_WLEN            0x60
+#define BF_UARTAPP_LINECTRL_WLEN(v)         (((v) << 5) & 0x60)
+#define BP_UARTAPP_LINECTRL_FEN             4
+#define BM_UARTAPP_LINECTRL_FEN             0x10
+#define BF_UARTAPP_LINECTRL_FEN(v)          (((v) << 4) & 0x10)
+#define BP_UARTAPP_LINECTRL_STP2            3
+#define BM_UARTAPP_LINECTRL_STP2            0x8
+#define BF_UARTAPP_LINECTRL_STP2(v)         (((v) << 3) & 0x8)
+#define BP_UARTAPP_LINECTRL_EPS             2
+#define BM_UARTAPP_LINECTRL_EPS             0x4
+#define BF_UARTAPP_LINECTRL_EPS(v)          (((v) << 2) & 0x4)
+#define BP_UARTAPP_LINECTRL_PEN             1
+#define BM_UARTAPP_LINECTRL_PEN             0x2
+#define BF_UARTAPP_LINECTRL_PEN(v)          (((v) << 1) & 0x2)
+#define BP_UARTAPP_LINECTRL_BRK             0
+#define BM_UARTAPP_LINECTRL_BRK             0x1
+#define BF_UARTAPP_LINECTRL_BRK(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_INTR
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_UARTAPP_INTR             (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x0))
+#define HW_UARTAPP_INTR_SET         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x4))
+#define HW_UARTAPP_INTR_CLR         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0x8))
+#define HW_UARTAPP_INTR_TOG         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x40 + 0xc))
+#define BP_UARTAPP_INTR_OEIEN       26
+#define BM_UARTAPP_INTR_OEIEN       0x4000000
+#define BF_UARTAPP_INTR_OEIEN(v)    (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_INTR_BEIEN       25
+#define BM_UARTAPP_INTR_BEIEN       0x2000000
+#define BF_UARTAPP_INTR_BEIEN(v)    (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_INTR_PEIEN       24
+#define BM_UARTAPP_INTR_PEIEN       0x1000000
+#define BF_UARTAPP_INTR_PEIEN(v)    (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_INTR_FEIEN       23
+#define BM_UARTAPP_INTR_FEIEN       0x800000
+#define BF_UARTAPP_INTR_FEIEN(v)    (((v) << 23) & 0x800000)
+#define BP_UARTAPP_INTR_RTIEN       22
+#define BM_UARTAPP_INTR_RTIEN       0x400000
+#define BF_UARTAPP_INTR_RTIEN(v)    (((v) << 22) & 0x400000)
+#define BP_UARTAPP_INTR_TXIEN       21
+#define BM_UARTAPP_INTR_TXIEN       0x200000
+#define BF_UARTAPP_INTR_TXIEN(v)    (((v) << 21) & 0x200000)
+#define BP_UARTAPP_INTR_RXIEN       20
+#define BM_UARTAPP_INTR_RXIEN       0x100000
+#define BF_UARTAPP_INTR_RXIEN(v)    (((v) << 20) & 0x100000)
+#define BP_UARTAPP_INTR_DSRMIEN     19
+#define BM_UARTAPP_INTR_DSRMIEN     0x80000
+#define BF_UARTAPP_INTR_DSRMIEN(v)  (((v) << 19) & 0x80000)
+#define BP_UARTAPP_INTR_DCDMIEN     18
+#define BM_UARTAPP_INTR_DCDMIEN     0x40000
+#define BF_UARTAPP_INTR_DCDMIEN(v)  (((v) << 18) & 0x40000)
+#define BP_UARTAPP_INTR_CTSMIEN     17
+#define BM_UARTAPP_INTR_CTSMIEN     0x20000
+#define BF_UARTAPP_INTR_CTSMIEN(v)  (((v) << 17) & 0x20000)
+#define BP_UARTAPP_INTR_RIMIEN      16
+#define BM_UARTAPP_INTR_RIMIEN      0x10000
+#define BF_UARTAPP_INTR_RIMIEN(v)   (((v) << 16) & 0x10000)
+#define BP_UARTAPP_INTR_OEIS        10
+#define BM_UARTAPP_INTR_OEIS        0x400
+#define BF_UARTAPP_INTR_OEIS(v)     (((v) << 10) & 0x400)
+#define BP_UARTAPP_INTR_BEIS        9
+#define BM_UARTAPP_INTR_BEIS        0x200
+#define BF_UARTAPP_INTR_BEIS(v)     (((v) << 9) & 0x200)
+#define BP_UARTAPP_INTR_PEIS        8
+#define BM_UARTAPP_INTR_PEIS        0x100
+#define BF_UARTAPP_INTR_PEIS(v)     (((v) << 8) & 0x100)
+#define BP_UARTAPP_INTR_FEIS        7
+#define BM_UARTAPP_INTR_FEIS        0x80
+#define BF_UARTAPP_INTR_FEIS(v)     (((v) << 7) & 0x80)
+#define BP_UARTAPP_INTR_RTIS        6
+#define BM_UARTAPP_INTR_RTIS        0x40
+#define BF_UARTAPP_INTR_RTIS(v)     (((v) << 6) & 0x40)
+#define BP_UARTAPP_INTR_TXIS        5
+#define BM_UARTAPP_INTR_TXIS        0x20
+#define BF_UARTAPP_INTR_TXIS(v)     (((v) << 5) & 0x20)
+#define BP_UARTAPP_INTR_RXIS        4
+#define BM_UARTAPP_INTR_RXIS        0x10
+#define BF_UARTAPP_INTR_RXIS(v)     (((v) << 4) & 0x10)
+#define BP_UARTAPP_INTR_DSRMIS      3
+#define BM_UARTAPP_INTR_DSRMIS      0x8
+#define BF_UARTAPP_INTR_DSRMIS(v)   (((v) << 3) & 0x8)
+#define BP_UARTAPP_INTR_DCDMIS      2
+#define BM_UARTAPP_INTR_DCDMIS      0x4
+#define BF_UARTAPP_INTR_DCDMIS(v)   (((v) << 2) & 0x4)
+#define BP_UARTAPP_INTR_CTSMIS      1
+#define BM_UARTAPP_INTR_CTSMIS      0x2
+#define BF_UARTAPP_INTR_CTSMIS(v)   (((v) << 1) & 0x2)
+#define BP_UARTAPP_INTR_RIMIS       0
+#define BM_UARTAPP_INTR_RIMIS       0x1
+#define BF_UARTAPP_INTR_RIMIS(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_DATA
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_UARTAPP_DATA         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x50))
+#define BP_UARTAPP_DATA_DATA    0
+#define BM_UARTAPP_DATA_DATA    0xffffffff
+#define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_UARTAPP_STAT
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_UARTAPP_STAT                         (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x60))
+#define BP_UARTAPP_STAT_PRESENT                 31
+#define BM_UARTAPP_STAT_PRESENT                 0x80000000
+#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_PRESENT(v)              (((v) << 31) & 0x80000000)
+#define BF_UARTAPP_STAT_PRESENT_V(v)            ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_UARTAPP_STAT_HISPEED                 30
+#define BM_UARTAPP_STAT_HISPEED                 0x40000000
+#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_HISPEED(v)              (((v) << 30) & 0x40000000)
+#define BF_UARTAPP_STAT_HISPEED_V(v)            ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000)
+#define BP_UARTAPP_STAT_BUSY                    29
+#define BM_UARTAPP_STAT_BUSY                    0x20000000
+#define BF_UARTAPP_STAT_BUSY(v)                 (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_STAT_CTS                     28
+#define BM_UARTAPP_STAT_CTS                     0x10000000
+#define BF_UARTAPP_STAT_CTS(v)                  (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_STAT_TXFE                    27
+#define BM_UARTAPP_STAT_TXFE                    0x8000000
+#define BF_UARTAPP_STAT_TXFE(v)                 (((v) << 27) & 0x8000000)
+#define BP_UARTAPP_STAT_RXFF                    26
+#define BM_UARTAPP_STAT_RXFF                    0x4000000
+#define BF_UARTAPP_STAT_RXFF(v)                 (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_STAT_TXFF                    25
+#define BM_UARTAPP_STAT_TXFF                    0x2000000
+#define BF_UARTAPP_STAT_TXFF(v)                 (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_STAT_RXFE                    24
+#define BM_UARTAPP_STAT_RXFE                    0x1000000
+#define BF_UARTAPP_STAT_RXFE(v)                 (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
+#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
+#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) << 20) & 0xf00000)
+#define BP_UARTAPP_STAT_OERR                    19
+#define BM_UARTAPP_STAT_OERR                    0x80000
+#define BF_UARTAPP_STAT_OERR(v)                 (((v) << 19) & 0x80000)
+#define BP_UARTAPP_STAT_BERR                    18
+#define BM_UARTAPP_STAT_BERR                    0x40000
+#define BF_UARTAPP_STAT_BERR(v)                 (((v) << 18) & 0x40000)
+#define BP_UARTAPP_STAT_PERR                    17
+#define BM_UARTAPP_STAT_PERR                    0x20000
+#define BF_UARTAPP_STAT_PERR(v)                 (((v) << 17) & 0x20000)
+#define BP_UARTAPP_STAT_FERR                    16
+#define BM_UARTAPP_STAT_FERR                    0x10000
+#define BF_UARTAPP_STAT_FERR(v)                 (((v) << 16) & 0x10000)
+#define BP_UARTAPP_STAT_RXCOUNT                 0
+#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
+#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_DEBUG
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_UARTAPP_DEBUG                (*(volatile unsigned long *)(REGS_UARTAPP_BASE + 0x70))
+#define BP_UARTAPP_DEBUG_TXDMARUN       5
+#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
+#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) << 5) & 0x20)
+#define BP_UARTAPP_DEBUG_RXDMARUN       4
+#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
+#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) << 4) & 0x10)
+#define BP_UARTAPP_DEBUG_TXCMDEND       3
+#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
+#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) << 3) & 0x8)
+#define BP_UARTAPP_DEBUG_RXCMDEND       2
+#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
+#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) << 2) & 0x4)
+#define BP_UARTAPP_DEBUG_TXDMARQ        1
+#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
+#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) << 1) & 0x2)
+#define BP_UARTAPP_DEBUG_RXDMARQ        0
+#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
+#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3600__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h
new file mode 100644
index 0000000000..9750330d9d
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-uartdbg.h
@@ -0,0 +1,491 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__UARTDBG__H__
+#define __HEADERGEN__STMP3600__UARTDBG__H__
+
+#define REGS_UARTDBG_BASE (0x80070000)
+
+#define REGS_UARTDBG_VERSION "2.3.0"
+
+/**
+ * Register: HW_UARTDBG_DR
+ * Address: 0
+ * SCT: no
+*/
+#define HW_UARTDBG_DR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0))
+#define BP_UARTDBG_DR_UNAVAILABLE       16
+#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_DR_RESERVED          12
+#define BM_UARTDBG_DR_RESERVED          0xf000
+#define BF_UARTDBG_DR_RESERVED(v)       (((v) << 12) & 0xf000)
+#define BP_UARTDBG_DR_OE                11
+#define BM_UARTDBG_DR_OE                0x800
+#define BF_UARTDBG_DR_OE(v)             (((v) << 11) & 0x800)
+#define BP_UARTDBG_DR_BE                10
+#define BM_UARTDBG_DR_BE                0x400
+#define BF_UARTDBG_DR_BE(v)             (((v) << 10) & 0x400)
+#define BP_UARTDBG_DR_PE                9
+#define BM_UARTDBG_DR_PE                0x200
+#define BF_UARTDBG_DR_PE(v)             (((v) << 9) & 0x200)
+#define BP_UARTDBG_DR_FE                8
+#define BM_UARTDBG_DR_FE                0x100
+#define BF_UARTDBG_DR_FE(v)             (((v) << 8) & 0x100)
+#define BP_UARTDBG_DR_DATA              0
+#define BM_UARTDBG_DR_DATA              0xff
+#define BF_UARTDBG_DR_DATA(v)           (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_UARTDBG_RSR_ECR
+ * Address: 0x4
+ * SCT: no
+*/
+#define HW_UARTDBG_RSR_ECR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4))
+#define BP_UARTDBG_RSR_ECR_UNAVAILABLE      8
+#define BM_UARTDBG_RSR_ECR_UNAVAILABLE      0xffffff00
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)   (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_RSR_ECR_EC               4
+#define BM_UARTDBG_RSR_ECR_EC               0xf0
+#define BF_UARTDBG_RSR_ECR_EC(v)            (((v) << 4) & 0xf0)
+#define BP_UARTDBG_RSR_ECR_OE               3
+#define BM_UARTDBG_RSR_ECR_OE               0x8
+#define BF_UARTDBG_RSR_ECR_OE(v)            (((v) << 3) & 0x8)
+#define BP_UARTDBG_RSR_ECR_BE               2
+#define BM_UARTDBG_RSR_ECR_BE               0x4
+#define BF_UARTDBG_RSR_ECR_BE(v)            (((v) << 2) & 0x4)
+#define BP_UARTDBG_RSR_ECR_PE               1
+#define BM_UARTDBG_RSR_ECR_PE               0x2
+#define BF_UARTDBG_RSR_ECR_PE(v)            (((v) << 1) & 0x2)
+#define BP_UARTDBG_RSR_ECR_FE               0
+#define BM_UARTDBG_RSR_ECR_FE               0x1
+#define BF_UARTDBG_RSR_ECR_FE(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_FR
+ * Address: 0x18
+ * SCT: no
+*/
+#define HW_UARTDBG_FR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18))
+#define BP_UARTDBG_FR_UNAVAILABLE       16
+#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_FR_RESERVED          9
+#define BM_UARTDBG_FR_RESERVED          0xfe00
+#define BF_UARTDBG_FR_RESERVED(v)       (((v) << 9) & 0xfe00)
+#define BP_UARTDBG_FR_RI                8
+#define BM_UARTDBG_FR_RI                0x100
+#define BF_UARTDBG_FR_RI(v)             (((v) << 8) & 0x100)
+#define BP_UARTDBG_FR_TXFE              7
+#define BM_UARTDBG_FR_TXFE              0x80
+#define BF_UARTDBG_FR_TXFE(v)           (((v) << 7) & 0x80)
+#define BP_UARTDBG_FR_RXFF              6
+#define BM_UARTDBG_FR_RXFF              0x40
+#define BF_UARTDBG_FR_RXFF(v)           (((v) << 6) & 0x40)
+#define BP_UARTDBG_FR_TXFF              5
+#define BM_UARTDBG_FR_TXFF              0x20
+#define BF_UARTDBG_FR_TXFF(v)           (((v) << 5) & 0x20)
+#define BP_UARTDBG_FR_RXFE              4
+#define BM_UARTDBG_FR_RXFE              0x10
+#define BF_UARTDBG_FR_RXFE(v)           (((v) << 4) & 0x10)
+#define BP_UARTDBG_FR_BUSY              3
+#define BM_UARTDBG_FR_BUSY              0x8
+#define BF_UARTDBG_FR_BUSY(v)           (((v) << 3) & 0x8)
+#define BP_UARTDBG_FR_DCD               2
+#define BM_UARTDBG_FR_DCD               0x4
+#define BF_UARTDBG_FR_DCD(v)            (((v) << 2) & 0x4)
+#define BP_UARTDBG_FR_DSR               1
+#define BM_UARTDBG_FR_DSR               0x2
+#define BF_UARTDBG_FR_DSR(v)            (((v) << 1) & 0x2)
+#define BP_UARTDBG_FR_CTS               0
+#define BM_UARTDBG_FR_CTS               0x1
+#define BF_UARTDBG_FR_CTS(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_ILPR
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_UARTDBG_ILPR                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20))
+#define BP_UARTDBG_ILPR_UNAVAILABLE     8
+#define BM_UARTDBG_ILPR_UNAVAILABLE     0xffffff00
+#define BF_UARTDBG_ILPR_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_ILPR_ILPDVSR         0
+#define BM_UARTDBG_ILPR_ILPDVSR         0xff
+#define BF_UARTDBG_ILPR_ILPDVSR(v)      (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_UARTDBG_IBRD
+ * Address: 0x24
+ * SCT: no
+*/
+#define HW_UARTDBG_IBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24))
+#define BP_UARTDBG_IBRD_UNAVAILABLE     16
+#define BM_UARTDBG_IBRD_UNAVAILABLE     0xffff0000
+#define BF_UARTDBG_IBRD_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IBRD_BAUD_DIVINT     0
+#define BM_UARTDBG_IBRD_BAUD_DIVINT     0xffff
+#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTDBG_FBRD
+ * Address: 0x28
+ * SCT: no
+*/
+#define HW_UARTDBG_FBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28))
+#define BP_UARTDBG_FBRD_UNAVAILABLE     8
+#define BM_UARTDBG_FBRD_UNAVAILABLE     0xffffff00
+#define BF_UARTDBG_FBRD_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_FBRD_RESERVED        6
+#define BM_UARTDBG_FBRD_RESERVED        0xc0
+#define BF_UARTDBG_FBRD_RESERVED(v)     (((v) << 6) & 0xc0)
+#define BP_UARTDBG_FBRD_BAUD_DIVFRAC    0
+#define BM_UARTDBG_FBRD_BAUD_DIVFRAC    0x3f
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_UARTDBG_LCR_H
+ * Address: 0x2c
+ * SCT: no
+*/
+#define HW_UARTDBG_LCR_H                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c))
+#define BP_UARTDBG_LCR_H_UNAVAILABLE    16
+#define BM_UARTDBG_LCR_H_UNAVAILABLE    0xffff0000
+#define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_LCR_H_RESERVED       8
+#define BM_UARTDBG_LCR_H_RESERVED       0xff00
+#define BF_UARTDBG_LCR_H_RESERVED(v)    (((v) << 8) & 0xff00)
+#define BP_UARTDBG_LCR_H_SPS            7
+#define BM_UARTDBG_LCR_H_SPS            0x80
+#define BF_UARTDBG_LCR_H_SPS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_LCR_H_WLEN           5
+#define BM_UARTDBG_LCR_H_WLEN           0x60
+#define BF_UARTDBG_LCR_H_WLEN(v)        (((v) << 5) & 0x60)
+#define BP_UARTDBG_LCR_H_FEN            4
+#define BM_UARTDBG_LCR_H_FEN            0x10
+#define BF_UARTDBG_LCR_H_FEN(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_LCR_H_STP2           3
+#define BM_UARTDBG_LCR_H_STP2           0x8
+#define BF_UARTDBG_LCR_H_STP2(v)        (((v) << 3) & 0x8)
+#define BP_UARTDBG_LCR_H_EPS            2
+#define BM_UARTDBG_LCR_H_EPS            0x4
+#define BF_UARTDBG_LCR_H_EPS(v)         (((v) << 2) & 0x4)
+#define BP_UARTDBG_LCR_H_PEN            1
+#define BM_UARTDBG_LCR_H_PEN            0x2
+#define BF_UARTDBG_LCR_H_PEN(v)         (((v) << 1) & 0x2)
+#define BP_UARTDBG_LCR_H_BRK            0
+#define BM_UARTDBG_LCR_H_BRK            0x1
+#define BF_UARTDBG_LCR_H_BRK(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_CR
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_UARTDBG_CR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30))
+#define BP_UARTDBG_CR_UNAVAILABLE       16
+#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_CR_CTSEN             15
+#define BM_UARTDBG_CR_CTSEN             0x8000
+#define BF_UARTDBG_CR_CTSEN(v)          (((v) << 15) & 0x8000)
+#define BP_UARTDBG_CR_RTSEN             14
+#define BM_UARTDBG_CR_RTSEN             0x4000
+#define BF_UARTDBG_CR_RTSEN(v)          (((v) << 14) & 0x4000)
+#define BP_UARTDBG_CR_OUT2              13
+#define BM_UARTDBG_CR_OUT2              0x2000
+#define BF_UARTDBG_CR_OUT2(v)           (((v) << 13) & 0x2000)
+#define BP_UARTDBG_CR_OUT1              12
+#define BM_UARTDBG_CR_OUT1              0x1000
+#define BF_UARTDBG_CR_OUT1(v)           (((v) << 12) & 0x1000)
+#define BP_UARTDBG_CR_RTS               11
+#define BM_UARTDBG_CR_RTS               0x800
+#define BF_UARTDBG_CR_RTS(v)            (((v) << 11) & 0x800)
+#define BP_UARTDBG_CR_DTR               10
+#define BM_UARTDBG_CR_DTR               0x400
+#define BF_UARTDBG_CR_DTR(v)            (((v) << 10) & 0x400)
+#define BP_UARTDBG_CR_RXE               9
+#define BM_UARTDBG_CR_RXE               0x200
+#define BF_UARTDBG_CR_RXE(v)            (((v) << 9) & 0x200)
+#define BP_UARTDBG_CR_TXE               8
+#define BM_UARTDBG_CR_TXE               0x100
+#define BF_UARTDBG_CR_TXE(v)            (((v) << 8) & 0x100)
+#define BP_UARTDBG_CR_LBE               7
+#define BM_UARTDBG_CR_LBE               0x80
+#define BF_UARTDBG_CR_LBE(v)            (((v) << 7) & 0x80)
+#define BP_UARTDBG_CR_RESERVED          3
+#define BM_UARTDBG_CR_RESERVED          0x78
+#define BF_UARTDBG_CR_RESERVED(v)       (((v) << 3) & 0x78)
+#define BP_UARTDBG_CR_SIRLP             2
+#define BM_UARTDBG_CR_SIRLP             0x4
+#define BF_UARTDBG_CR_SIRLP(v)          (((v) << 2) & 0x4)
+#define BP_UARTDBG_CR_SIREN             1
+#define BM_UARTDBG_CR_SIREN             0x2
+#define BF_UARTDBG_CR_SIREN(v)          (((v) << 1) & 0x2)
+#define BP_UARTDBG_CR_UARTEN            0
+#define BM_UARTDBG_CR_UARTEN            0x1
+#define BF_UARTDBG_CR_UARTEN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_IFLS
+ * Address: 0x34
+ * SCT: no
+*/
+#define HW_UARTDBG_IFLS                             (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34))
+#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
+#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
+#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IFLS_RESERVED                    6
+#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
+#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) << 6) & 0xffc0)
+#define BP_UARTDBG_IFLS_RXIFLSEL                    3
+#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
+#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) << 3) & 0x38)
+#define BF_UARTDBG_IFLS_RXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38)
+#define BP_UARTDBG_IFLS_TXIFLSEL                    0
+#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
+#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) << 0) & 0x7)
+#define BF_UARTDBG_IFLS_TXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7)
+
+/**
+ * Register: HW_UARTDBG_IMSC
+ * Address: 0x38
+ * SCT: no
+*/
+#define HW_UARTDBG_IMSC                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38))
+#define BP_UARTDBG_IMSC_UNAVAILABLE     16
+#define BM_UARTDBG_IMSC_UNAVAILABLE     0xffff0000
+#define BF_UARTDBG_IMSC_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IMSC_RESERVED        11
+#define BM_UARTDBG_IMSC_RESERVED        0xf800
+#define BF_UARTDBG_IMSC_RESERVED(v)     (((v) << 11) & 0xf800)
+#define BP_UARTDBG_IMSC_OEIM            10
+#define BM_UARTDBG_IMSC_OEIM            0x400
+#define BF_UARTDBG_IMSC_OEIM(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_IMSC_BEIM            9
+#define BM_UARTDBG_IMSC_BEIM            0x200
+#define BF_UARTDBG_IMSC_BEIM(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_IMSC_PEIM            8
+#define BM_UARTDBG_IMSC_PEIM            0x100
+#define BF_UARTDBG_IMSC_PEIM(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_IMSC_FEIM            7
+#define BM_UARTDBG_IMSC_FEIM            0x80
+#define BF_UARTDBG_IMSC_FEIM(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_IMSC_RTIM            6
+#define BM_UARTDBG_IMSC_RTIM            0x40
+#define BF_UARTDBG_IMSC_RTIM(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_IMSC_TXIM            5
+#define BM_UARTDBG_IMSC_TXIM            0x20
+#define BF_UARTDBG_IMSC_TXIM(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_IMSC_RXIM            4
+#define BM_UARTDBG_IMSC_RXIM            0x10
+#define BF_UARTDBG_IMSC_RXIM(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_IMSC_DSRMIM          3
+#define BM_UARTDBG_IMSC_DSRMIM          0x8
+#define BF_UARTDBG_IMSC_DSRMIM(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_IMSC_DCDMIM          2
+#define BM_UARTDBG_IMSC_DCDMIM          0x4
+#define BF_UARTDBG_IMSC_DCDMIM(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_IMSC_CTSMIM          1
+#define BM_UARTDBG_IMSC_CTSMIM          0x2
+#define BF_UARTDBG_IMSC_CTSMIM(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_IMSC_RIMIM           0
+#define BM_UARTDBG_IMSC_RIMIM           0x1
+#define BF_UARTDBG_IMSC_RIMIM(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_RIS
+ * Address: 0x3c
+ * SCT: no
+*/
+#define HW_UARTDBG_RIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c))
+#define BP_UARTDBG_RIS_UNAVAILABLE      16
+#define BM_UARTDBG_RIS_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_RIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_RIS_RESERVED         11
+#define BM_UARTDBG_RIS_RESERVED         0xf800
+#define BF_UARTDBG_RIS_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_RIS_OERIS            10
+#define BM_UARTDBG_RIS_OERIS            0x400
+#define BF_UARTDBG_RIS_OERIS(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_RIS_BERIS            9
+#define BM_UARTDBG_RIS_BERIS            0x200
+#define BF_UARTDBG_RIS_BERIS(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_RIS_PERIS            8
+#define BM_UARTDBG_RIS_PERIS            0x100
+#define BF_UARTDBG_RIS_PERIS(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_RIS_FERIS            7
+#define BM_UARTDBG_RIS_FERIS            0x80
+#define BF_UARTDBG_RIS_FERIS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_RIS_RTRIS            6
+#define BM_UARTDBG_RIS_RTRIS            0x40
+#define BF_UARTDBG_RIS_RTRIS(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_RIS_TXRIS            5
+#define BM_UARTDBG_RIS_TXRIS            0x20
+#define BF_UARTDBG_RIS_TXRIS(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_RIS_RXRIS            4
+#define BM_UARTDBG_RIS_RXRIS            0x10
+#define BF_UARTDBG_RIS_RXRIS(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_RIS_DSRRMIS          3
+#define BM_UARTDBG_RIS_DSRRMIS          0x8
+#define BF_UARTDBG_RIS_DSRRMIS(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_RIS_DCDRMIS          2
+#define BM_UARTDBG_RIS_DCDRMIS          0x4
+#define BF_UARTDBG_RIS_DCDRMIS(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_RIS_CTSRMIS          1
+#define BM_UARTDBG_RIS_CTSRMIS          0x2
+#define BF_UARTDBG_RIS_CTSRMIS(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_RIS_RIRMIS           0
+#define BM_UARTDBG_RIS_RIRMIS           0x1
+#define BF_UARTDBG_RIS_RIRMIS(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_MIS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_UARTDBG_MIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40))
+#define BP_UARTDBG_MIS_UNAVAILABLE      16
+#define BM_UARTDBG_MIS_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_MIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_MIS_RESERVED         11
+#define BM_UARTDBG_MIS_RESERVED         0xf800
+#define BF_UARTDBG_MIS_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_MIS_OEMIS            10
+#define BM_UARTDBG_MIS_OEMIS            0x400
+#define BF_UARTDBG_MIS_OEMIS(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_MIS_BEMIS            9
+#define BM_UARTDBG_MIS_BEMIS            0x200
+#define BF_UARTDBG_MIS_BEMIS(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_MIS_PEMIS            8
+#define BM_UARTDBG_MIS_PEMIS            0x100
+#define BF_UARTDBG_MIS_PEMIS(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_MIS_FEMIS            7
+#define BM_UARTDBG_MIS_FEMIS            0x80
+#define BF_UARTDBG_MIS_FEMIS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_MIS_RTMIS            6
+#define BM_UARTDBG_MIS_RTMIS            0x40
+#define BF_UARTDBG_MIS_RTMIS(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_MIS_TXMIS            5
+#define BM_UARTDBG_MIS_TXMIS            0x20
+#define BF_UARTDBG_MIS_TXMIS(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_MIS_RXMIS            4
+#define BM_UARTDBG_MIS_RXMIS            0x10
+#define BF_UARTDBG_MIS_RXMIS(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_MIS_DSRMMIS          3
+#define BM_UARTDBG_MIS_DSRMMIS          0x8
+#define BF_UARTDBG_MIS_DSRMMIS(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_MIS_DCDMMIS          2
+#define BM_UARTDBG_MIS_DCDMMIS          0x4
+#define BF_UARTDBG_MIS_DCDMMIS(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_MIS_CTSMMIS          1
+#define BM_UARTDBG_MIS_CTSMMIS          0x2
+#define BF_UARTDBG_MIS_CTSMMIS(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_MIS_RIMMIS           0
+#define BM_UARTDBG_MIS_RIMMIS           0x1
+#define BF_UARTDBG_MIS_RIMMIS(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_ICR
+ * Address: 0x44
+ * SCT: no
+*/
+#define HW_UARTDBG_ICR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44))
+#define BP_UARTDBG_ICR_UNAVAILABLE      16
+#define BM_UARTDBG_ICR_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_ICR_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_ICR_RESERVED         11
+#define BM_UARTDBG_ICR_RESERVED         0xf800
+#define BF_UARTDBG_ICR_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_ICR_OEIC             10
+#define BM_UARTDBG_ICR_OEIC             0x400
+#define BF_UARTDBG_ICR_OEIC(v)          (((v) << 10) & 0x400)
+#define BP_UARTDBG_ICR_BEIC             9
+#define BM_UARTDBG_ICR_BEIC             0x200
+#define BF_UARTDBG_ICR_BEIC(v)          (((v) << 9) & 0x200)
+#define BP_UARTDBG_ICR_PEIC             8
+#define BM_UARTDBG_ICR_PEIC             0x100
+#define BF_UARTDBG_ICR_PEIC(v)          (((v) << 8) & 0x100)
+#define BP_UARTDBG_ICR_FEIC             7
+#define BM_UARTDBG_ICR_FEIC             0x80
+#define BF_UARTDBG_ICR_FEIC(v)          (((v) << 7) & 0x80)
+#define BP_UARTDBG_ICR_RTIC             6
+#define BM_UARTDBG_ICR_RTIC             0x40
+#define BF_UARTDBG_ICR_RTIC(v)          (((v) << 6) & 0x40)
+#define BP_UARTDBG_ICR_TXIC             5
+#define BM_UARTDBG_ICR_TXIC             0x20
+#define BF_UARTDBG_ICR_TXIC(v)          (((v) << 5) & 0x20)
+#define BP_UARTDBG_ICR_RXIC             4
+#define BM_UARTDBG_ICR_RXIC             0x10
+#define BF_UARTDBG_ICR_RXIC(v)          (((v) << 4) & 0x10)
+#define BP_UARTDBG_ICR_DSRMIC           3
+#define BM_UARTDBG_ICR_DSRMIC           0x8
+#define BF_UARTDBG_ICR_DSRMIC(v)        (((v) << 3) & 0x8)
+#define BP_UARTDBG_ICR_DCDMIC           2
+#define BM_UARTDBG_ICR_DCDMIC           0x4
+#define BF_UARTDBG_ICR_DCDMIC(v)        (((v) << 2) & 0x4)
+#define BP_UARTDBG_ICR_CTSMIC           1
+#define BM_UARTDBG_ICR_CTSMIC           0x2
+#define BF_UARTDBG_ICR_CTSMIC(v)        (((v) << 1) & 0x2)
+#define BP_UARTDBG_ICR_RIMIC            0
+#define BM_UARTDBG_ICR_RIMIC            0x1
+#define BF_UARTDBG_ICR_RIMIC(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_DMACR
+ * Address: 0x48
+ * SCT: no
+*/
+#define HW_UARTDBG_DMACR                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48))
+#define BP_UARTDBG_DMACR_UNAVAILABLE    16
+#define BM_UARTDBG_DMACR_UNAVAILABLE    0xffff0000
+#define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_DMACR_RESERVED       3
+#define BM_UARTDBG_DMACR_RESERVED       0xfff8
+#define BF_UARTDBG_DMACR_RESERVED(v)    (((v) << 3) & 0xfff8)
+#define BP_UARTDBG_DMACR_DMAONERR       2
+#define BM_UARTDBG_DMACR_DMAONERR       0x4
+#define BF_UARTDBG_DMACR_DMAONERR(v)    (((v) << 2) & 0x4)
+#define BP_UARTDBG_DMACR_TXDMAE         1
+#define BM_UARTDBG_DMACR_TXDMAE         0x2
+#define BF_UARTDBG_DMACR_TXDMAE(v)      (((v) << 1) & 0x2)
+#define BP_UARTDBG_DMACR_RXDMAE         0
+#define BM_UARTDBG_DMACR_RXDMAE         0x1
+#define BF_UARTDBG_DMACR_RXDMAE(v)      (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3600__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h
new file mode 100644
index 0000000000..f255a3bc6c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3600/regs-usbphy.h
@@ -0,0 +1,405 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3600:2.3.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3600__USBPHY__H__
+#define __HEADERGEN__STMP3600__USBPHY__H__
+
+#define REGS_USBPHY_BASE (0x8007c000)
+
+#define REGS_USBPHY_VERSION "2.3.0"
+
+/**
+ * Register: HW_USBPHY_PWD
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_USBPHY_PWD               (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0))
+#define HW_USBPHY_PWD_SET           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4))
+#define HW_USBPHY_PWD_CLR           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8))
+#define HW_USBPHY_PWD_TOG           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc))
+#define BP_USBPHY_PWD_RXPWDRX       20
+#define BM_USBPHY_PWD_RXPWDRX       0x100000
+#define BF_USBPHY_PWD_RXPWDRX(v)    (((v) << 20) & 0x100000)
+#define BP_USBPHY_PWD_RXPWDDIFF     19
+#define BM_USBPHY_PWD_RXPWDDIFF     0x80000
+#define BF_USBPHY_PWD_RXPWDDIFF(v)  (((v) << 19) & 0x80000)
+#define BP_USBPHY_PWD_RXPWD1PT1     18
+#define BM_USBPHY_PWD_RXPWD1PT1     0x40000
+#define BF_USBPHY_PWD_RXPWD1PT1(v)  (((v) << 18) & 0x40000)
+#define BP_USBPHY_PWD_RXPWDENV      17
+#define BM_USBPHY_PWD_RXPWDENV      0x20000
+#define BF_USBPHY_PWD_RXPWDENV(v)   (((v) << 17) & 0x20000)
+#define BP_USBPHY_PWD_TXPWDCOMP     14
+#define BM_USBPHY_PWD_TXPWDCOMP     0x4000
+#define BF_USBPHY_PWD_TXPWDCOMP(v)  (((v) << 14) & 0x4000)
+#define BP_USBPHY_PWD_TXPWDVBG      13
+#define BM_USBPHY_PWD_TXPWDVBG      0x2000
+#define BF_USBPHY_PWD_TXPWDVBG(v)   (((v) << 13) & 0x2000)
+#define BP_USBPHY_PWD_TXPWDV2I      12
+#define BM_USBPHY_PWD_TXPWDV2I      0x1000
+#define BF_USBPHY_PWD_TXPWDV2I(v)   (((v) << 12) & 0x1000)
+#define BP_USBPHY_PWD_TXPWDIBIAS    11
+#define BM_USBPHY_PWD_TXPWDIBIAS    0x800
+#define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800)
+#define BP_USBPHY_PWD_TXPWDFS       10
+#define BM_USBPHY_PWD_TXPWDFS       0x400
+#define BF_USBPHY_PWD_TXPWDFS(v)    (((v) << 10) & 0x400)
+
+/**
+ * Register: HW_USBPHY_TX
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_USBPHY_TX                    (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0))
+#define HW_USBPHY_TX_SET                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4))
+#define HW_USBPHY_TX_CLR                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8))
+#define HW_USBPHY_TX_TOG                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc))
+#define BP_USBPHY_TX_TXCMPOUT_STATUS    23
+#define BM_USBPHY_TX_TXCMPOUT_STATUS    0x800000
+#define BF_USBPHY_TX_TXCMPOUT_STATUS(v) (((v) << 23) & 0x800000)
+#define BP_USBPHY_TX_TXENCAL45DP        21
+#define BM_USBPHY_TX_TXENCAL45DP        0x200000
+#define BF_USBPHY_TX_TXENCAL45DP(v)     (((v) << 21) & 0x200000)
+#define BP_USBPHY_TX_TXCAL45DP          16
+#define BM_USBPHY_TX_TXCAL45DP          0x1f0000
+#define BF_USBPHY_TX_TXCAL45DP(v)       (((v) << 16) & 0x1f0000)
+#define BP_USBPHY_TX_TXENCAL45DN        13
+#define BM_USBPHY_TX_TXENCAL45DN        0x2000
+#define BF_USBPHY_TX_TXENCAL45DN(v)     (((v) << 13) & 0x2000)
+#define BP_USBPHY_TX_TXCAL45DN          8
+#define BM_USBPHY_TX_TXCAL45DN          0x1f00
+#define BF_USBPHY_TX_TXCAL45DN(v)       (((v) << 8) & 0x1f00)
+#define BP_USBPHY_TX_TXCALIBRATE        7
+#define BM_USBPHY_TX_TXCALIBRATE        0x80
+#define BF_USBPHY_TX_TXCALIBRATE(v)     (((v) << 7) & 0x80)
+
+/**
+ * Register: HW_USBPHY_RX
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_USBPHY_RX                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0))
+#define HW_USBPHY_RX_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4))
+#define HW_USBPHY_RX_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8))
+#define HW_USBPHY_RX_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc))
+#define BP_USBPHY_RX_RXDBYPASS      22
+#define BM_USBPHY_RX_RXDBYPASS      0x400000
+#define BF_USBPHY_RX_RXDBYPASS(v)   (((v) << 22) & 0x400000)
+#define BP_USBPHY_RX_DISCONADJ      4
+#define BM_USBPHY_RX_DISCONADJ      0x30
+#define BF_USBPHY_RX_DISCONADJ(v)   (((v) << 4) & 0x30)
+#define BP_USBPHY_RX_ENVADJ         0
+#define BM_USBPHY_RX_ENVADJ         0x3
+#define BF_USBPHY_RX_ENVADJ(v)      (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_USBPHY_CTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_USBPHY_CTRL                          (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0))
+#define HW_USBPHY_CTRL_SET                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4))
+#define HW_USBPHY_CTRL_CLR                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8))
+#define HW_USBPHY_CTRL_TOG                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc))
+#define BP_USBPHY_CTRL_SFTRST                   31
+#define BM_USBPHY_CTRL_SFTRST                   0x80000000
+#define BF_USBPHY_CTRL_SFTRST(v)                (((v) << 31) & 0x80000000)
+#define BP_USBPHY_CTRL_CLKGATE                  30
+#define BM_USBPHY_CTRL_CLKGATE                  0x40000000
+#define BF_USBPHY_CTRL_CLKGATE(v)               (((v) << 30) & 0x40000000)
+#define BP_USBPHY_CTRL_UTMI_SUSPENDM            29
+#define BM_USBPHY_CTRL_UTMI_SUSPENDM            0x20000000
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)         (((v) << 29) & 0x20000000)
+#define BP_USBPHY_CTRL_RESUME_IRQ               10
+#define BM_USBPHY_CTRL_RESUME_IRQ               0x400
+#define BF_USBPHY_CTRL_RESUME_IRQ(v)            (((v) << 10) & 0x400)
+#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT        9
+#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT        0x200
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)     (((v) << 9) & 0x200)
+#define BP_USBPHY_CTRL_ENOTGIDDETECT            7
+#define BM_USBPHY_CTRL_ENOTGIDDETECT            0x80
+#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)         (((v) << 7) & 0x80)
+#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT        4
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x10
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)     (((v) << 4) & 0x10)
+#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     3
+#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     0x8
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)  (((v) << 3) & 0x8)
+#define BP_USBPHY_CTRL_ENIRQHOSTDISCON          2
+#define BM_USBPHY_CTRL_ENIRQHOSTDISCON          0x4
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)       (((v) << 2) & 0x4)
+#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT       1
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x2
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)    (((v) << 1) & 0x2)
+#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT        0
+#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT        0x1
+#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBPHY_STATUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_USBPHY_STATUS                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40))
+#define BP_USBPHY_STATUS_RESUME_STATUS              10
+#define BM_USBPHY_STATUS_RESUME_STATUS              0x400
+#define BF_USBPHY_STATUS_RESUME_STATUS(v)           (((v) << 10) & 0x400)
+#define BP_USBPHY_STATUS_OTGID_STATUS               8
+#define BM_USBPHY_STATUS_OTGID_STATUS               0x100
+#define BF_USBPHY_STATUS_OTGID_STATUS(v)            (((v) << 8) & 0x100)
+#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS           6
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS           0x40
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)        (((v) << 6) & 0x40)
+#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    3
+#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    0x8
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8)
+
+/**
+ * Register: HW_USBPHY_DEBUG
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_USBPHY_DEBUG                         (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0))
+#define HW_USBPHY_DEBUG_SET                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4))
+#define HW_USBPHY_DEBUG_CLR                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8))
+#define HW_USBPHY_DEBUG_TOG                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc))
+#define BP_USBPHY_DEBUG_CLKGATE                 30
+#define BM_USBPHY_DEBUG_CLKGATE                 0x40000000
+#define BF_USBPHY_DEBUG_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH      25
+#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH      0x1e000000
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)   (((v) << 25) & 0x1e000000)
+#define BP_USBPHY_DEBUG_ENSQUELCHRESET          24
+#define BM_USBPHY_DEBUG_ENSQUELCHRESET          0x1000000
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)       (((v) << 24) & 0x1000000)
+#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT       16
+#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT       0x1f0000
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)    (((v) << 16) & 0x1f0000)
+#define BP_USBPHY_DEBUG_ENTX2RXCOUNT            12
+#define BM_USBPHY_DEBUG_ENTX2RXCOUNT            0x1000
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)         (((v) << 12) & 0x1000)
+#define BP_USBPHY_DEBUG_TX2RXCOUNT              8
+#define BM_USBPHY_DEBUG_TX2RXCOUNT              0xf00
+#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)           (((v) << 8) & 0xf00)
+#define BP_USBPHY_DEBUG_ENHSTPULLDOWN           4
+#define BM_USBPHY_DEBUG_ENHSTPULLDOWN           0x30
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)        (((v) << 4) & 0x30)
+#define BP_USBPHY_DEBUG_HSTPULLDOWN             2
+#define BM_USBPHY_DEBUG_HSTPULLDOWN             0xc
+#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)          (((v) << 2) & 0xc)
+#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    1
+#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    0x2
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2)
+#define BP_USBPHY_DEBUG_OTGIDPIOLOCK            0
+#define BM_USBPHY_DEBUG_OTGIDPIOLOCK            0x1
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBPHY_DEBUG0_STATUS
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG0_STATUS                             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60))
+#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               26
+#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               0xfc000000
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)            (((v) << 26) & 0xfc000000)
+#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     16
+#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     0x3ff0000
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)  (((v) << 16) & 0x3ff0000)
+#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0
+#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0xffff
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBPHY_DEBUG1_STATUS
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG1_STATUS                 (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70))
+#define BP_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA    16
+#define BM_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA    0xffff0000
+#define BF_USBPHY_DEBUG1_STATUS_UTMI_TX_DATA(v) (((v) << 16) & 0xffff0000)
+#define BP_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA    0
+#define BM_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA    0xffff
+#define BF_USBPHY_DEBUG1_STATUS_UTMI_RX_DATA(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBPHY_DEBUG2_STATUS
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG2_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80))
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH       22
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH       0x400000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALIDH(v)    (((v) << 22) & 0x400000)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXVALID        21
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXVALID        0x200000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXVALID(v)     (((v) << 21) & 0x200000)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT     20
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT     0x100000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TERMSELECT(v)  (((v) << 20) & 0x100000)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT     18
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT     0xc0000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_XCVRSELECT(v)  (((v) << 18) & 0xc0000)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_OPMODE         16
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_OPMODE         0x30000
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_OPMODE(v)      (((v) << 16) & 0x30000)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE      6
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE      0xc0
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_LINESTATE(v)   (((v) << 6) & 0xc0)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM       5
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM       0x20
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_SUSPENDM(v)    (((v) << 5) & 0x20)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH       4
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH       0x10
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALIDH(v)    (((v) << 4) & 0x10)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXVALID        3
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXVALID        0x8
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXVALID(v)     (((v) << 3) & 0x8)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE       2
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE       0x4
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXACTIVE(v)    (((v) << 2) & 0x4)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_RXERROR        1
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_RXERROR        0x2
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_RXERROR(v)     (((v) << 1) & 0x2)
+#define BP_USBPHY_DEBUG2_STATUS_UTMI_TXREADY        0
+#define BM_USBPHY_DEBUG2_STATUS_UTMI_TXREADY        0x1
+#define BF_USBPHY_DEBUG2_STATUS_UTMI_TXREADY(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBPHY_DEBUG3_STATUS
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG3_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x90))
+#define BP_USBPHY_DEBUG3_STATUS_B_CNT_FSM           28
+#define BM_USBPHY_DEBUG3_STATUS_B_CNT_FSM           0x70000000
+#define BF_USBPHY_DEBUG3_STATUS_B_CNT_FSM(v)        (((v) << 28) & 0x70000000)
+#define BP_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM       23
+#define BM_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM       0x3800000
+#define BF_USBPHY_DEBUG3_STATUS_SQ_UNLOCK_FSM(v)    (((v) << 23) & 0x3800000)
+#define BP_USBPHY_DEBUG3_STATUS_BIT_CNT             12
+#define BM_USBPHY_DEBUG3_STATUS_BIT_CNT             0x3ff000
+#define BF_USBPHY_DEBUG3_STATUS_BIT_CNT(v)          (((v) << 12) & 0x3ff000)
+#define BP_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM      8
+#define BM_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM      0xf00
+#define BF_USBPHY_DEBUG3_STATUS_MAIN_HS_RX_FSM(v)   (((v) << 8) & 0xf00)
+#define BP_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT     0
+#define BM_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT     0xff
+#define BF_USBPHY_DEBUG3_STATUS_UNSTUFF_BIT_CNT(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBPHY_DEBUG4_STATUS
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG4_STATUS             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xa0))
+#define BP_USBPHY_DEBUG4_STATUS_BYTE_FSM    16
+#define BM_USBPHY_DEBUG4_STATUS_BYTE_FSM    0x1fff0000
+#define BF_USBPHY_DEBUG4_STATUS_BYTE_FSM(v) (((v) << 16) & 0x1fff0000)
+#define BP_USBPHY_DEBUG4_STATUS_SND_FSM     0
+#define BM_USBPHY_DEBUG4_STATUS_SND_FSM     0x3fff
+#define BF_USBPHY_DEBUG4_STATUS_SND_FSM(v)  (((v) << 0) & 0x3fff)
+
+/**
+ * Register: HW_USBPHY_DEBUG5_STATUS
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG5_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xb0))
+#define BP_USBPHY_DEBUG5_STATUS_MAIN_FSM            24
+#define BM_USBPHY_DEBUG5_STATUS_MAIN_FSM            0xf000000
+#define BF_USBPHY_DEBUG5_STATUS_MAIN_FSM(v)         (((v) << 24) & 0xf000000)
+#define BP_USBPHY_DEBUG5_STATUS_SYNC_FSM            16
+#define BM_USBPHY_DEBUG5_STATUS_SYNC_FSM            0x3f0000
+#define BF_USBPHY_DEBUG5_STATUS_SYNC_FSM(v)         (((v) << 16) & 0x3f0000)
+#define BP_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM       12
+#define BM_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM       0x7000
+#define BF_USBPHY_DEBUG5_STATUS_PRECHARGE_FSM(v)    (((v) << 12) & 0x7000)
+#define BP_USBPHY_DEBUG5_STATUS_SHIFT_FSM           8
+#define BM_USBPHY_DEBUG5_STATUS_SHIFT_FSM           0x700
+#define BF_USBPHY_DEBUG5_STATUS_SHIFT_FSM(v)        (((v) << 8) & 0x700)
+#define BP_USBPHY_DEBUG5_STATUS_SOF_FSM             0
+#define BM_USBPHY_DEBUG5_STATUS_SOF_FSM             0x1f
+#define BF_USBPHY_DEBUG5_STATUS_SOF_FSM(v)          (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBPHY_DEBUG6_STATUS
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG6_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xc0))
+#define BP_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM       8
+#define BM_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM       0x700
+#define BF_USBPHY_DEBUG6_STATUS_FIRST_EOP_FSM(v)    (((v) << 8) & 0x700)
+#define BP_USBPHY_DEBUG6_STATUS_EOP_FSM             0
+#define BM_USBPHY_DEBUG6_STATUS_EOP_FSM             0xff
+#define BF_USBPHY_DEBUG6_STATUS_EOP_FSM(v)          (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBPHY_DEBUG7_STATUS
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG7_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xd0))
+#define BP_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM      28
+#define BM_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM      0x30000000
+#define BF_USBPHY_DEBUG7_STATUS_FIRST_DATA_FSM(v)   (((v) << 28) & 0x30000000)
+#define BP_USBPHY_DEBUG7_STATUS_BIT_CNT             24
+#define BM_USBPHY_DEBUG7_STATUS_BIT_CNT             0xf000000
+#define BF_USBPHY_DEBUG7_STATUS_BIT_CNT(v)          (((v) << 24) & 0xf000000)
+#define BP_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT         20
+#define BM_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT         0x700000
+#define BF_USBPHY_DEBUG7_STATUS_UNSTUFF_CNT(v)      (((v) << 20) & 0x700000)
+#define BP_USBPHY_DEBUG7_STATUS_LD_FSM              16
+#define BM_USBPHY_DEBUG7_STATUS_LD_FSM              0x30000
+#define BF_USBPHY_DEBUG7_STATUS_LD_FSM(v)           (((v) << 16) & 0x30000)
+#define BP_USBPHY_DEBUG7_STATUS_FIFO_FSM            8
+#define BM_USBPHY_DEBUG7_STATUS_FIFO_FSM            0x3f00
+#define BF_USBPHY_DEBUG7_STATUS_FIFO_FSM(v)         (((v) << 8) & 0x3f00)
+#define BP_USBPHY_DEBUG7_STATUS_MAIN_FSM            4
+#define BM_USBPHY_DEBUG7_STATUS_MAIN_FSM            0xf0
+#define BF_USBPHY_DEBUG7_STATUS_MAIN_FSM(v)         (((v) << 4) & 0xf0)
+#define BP_USBPHY_DEBUG7_STATUS_EOP_FSM             0
+#define BM_USBPHY_DEBUG7_STATUS_EOP_FSM             0xf
+#define BF_USBPHY_DEBUG7_STATUS_EOP_FSM(v)          (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_USBPHY_DEBUG8_STATUS
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG8_STATUS                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0xe0))
+#define BP_USBPHY_DEBUG8_STATUS_RX_SIE_FSM          28
+#define BM_USBPHY_DEBUG8_STATUS_RX_SIE_FSM          0xf0000000
+#define BF_USBPHY_DEBUG8_STATUS_RX_SIE_FSM(v)       (((v) << 28) & 0xf0000000)
+#define BP_USBPHY_DEBUG8_STATUS_TX_SIE_FSM          24
+#define BM_USBPHY_DEBUG8_STATUS_TX_SIE_FSM          0xf000000
+#define BF_USBPHY_DEBUG8_STATUS_TX_SIE_FSM(v)       (((v) << 24) & 0xf000000)
+#define BP_USBPHY_DEBUG8_STATUS_SHIFT_FSM           8
+#define BM_USBPHY_DEBUG8_STATUS_SHIFT_FSM           0x300
+#define BF_USBPHY_DEBUG8_STATUS_SHIFT_FSM(v)        (((v) << 8) & 0x300)
+#define BP_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM      0
+#define BM_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM      0x7f
+#define BF_USBPHY_DEBUG8_STATUS_FS_TX_MAIN_FSM(v)   (((v) << 0) & 0x7f)
+
+#endif /* __HEADERGEN__STMP3600__USBPHY__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h
new file mode 100644
index 0000000000..fe654841af
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h
@@ -0,0 +1,301 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__APBH__H__
+#define __HEADERGEN__STMP3700__APBH__H__
+
+#define REGS_APBH_BASE (0x80004000)
+
+#define REGS_APBH_VERSION "3.2.0"
+
+/**
+ * Register: HW_APBH_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_APBH_CTRL0                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0))
+#define HW_APBH_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4))
+#define HW_APBH_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8))
+#define HW_APBH_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc))
+#define BP_APBH_CTRL0_SFTRST                    31
+#define BM_APBH_CTRL0_SFTRST                    0x80000000
+#define BF_APBH_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
+#define BP_APBH_CTRL0_CLKGATE                   30
+#define BM_APBH_CTRL0_CLKGATE                   0x40000000
+#define BF_APBH_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
+#define BP_APBH_CTRL0_RESET_CHANNEL             16
+#define BM_APBH_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1       0x1
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2       0x2
+#define BV_APBH_CTRL0_RESET_CHANNEL__LCDIF      0x4
+#define BV_APBH_CTRL0_RESET_CHANNEL__ATA        0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0      0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1      0x20
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2      0x40
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3      0x80
+#define BF_APBH_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
+#define BF_APBH_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL           8
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL           0xff00
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1     0x1
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2     0x2
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF    0x4
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA      0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0    0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1    0x20
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2    0x40
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3    0x80
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)        (((v) << 8) & 0xff00)
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v)      ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00)
+#define BP_APBH_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBH_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1      0x1
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2      0x2
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__LCDIF     0x4
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA       0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0     0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1     0x20
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2     0x30
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3     0x40
+#define BF_APBH_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
+#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_APBH_CTRL1                       (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0))
+#define HW_APBH_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4))
+#define HW_APBH_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8))
+#define HW_APBH_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc))
+#define BP_APBH_CTRL1_CH_AHB_ERROR_IRQ      16
+#define BM_APBH_CTRL1_CH_AHB_ERROR_IRQ      0xff0000
+#define BF_APBH_CTRL1_CH_AHB_ERROR_IRQ(v)   (((v) << 16) & 0xff0000)
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    8
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff00
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00)
+#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ       0
+#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ       0xff
+#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_DEVSEL
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_APBH_DEVSEL          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20))
+#define BP_APBH_DEVSEL_CH7      28
+#define BM_APBH_DEVSEL_CH7      0xf0000000
+#define BF_APBH_DEVSEL_CH7(v)   (((v) << 28) & 0xf0000000)
+#define BP_APBH_DEVSEL_CH6      24
+#define BM_APBH_DEVSEL_CH6      0xf000000
+#define BF_APBH_DEVSEL_CH6(v)   (((v) << 24) & 0xf000000)
+#define BP_APBH_DEVSEL_CH5      20
+#define BM_APBH_DEVSEL_CH5      0xf00000
+#define BF_APBH_DEVSEL_CH5(v)   (((v) << 20) & 0xf00000)
+#define BP_APBH_DEVSEL_CH4      16
+#define BM_APBH_DEVSEL_CH4      0xf0000
+#define BF_APBH_DEVSEL_CH4(v)   (((v) << 16) & 0xf0000)
+#define BP_APBH_DEVSEL_CH3      12
+#define BM_APBH_DEVSEL_CH3      0xf000
+#define BF_APBH_DEVSEL_CH3(v)   (((v) << 12) & 0xf000)
+#define BP_APBH_DEVSEL_CH2      8
+#define BM_APBH_DEVSEL_CH2      0xf00
+#define BF_APBH_DEVSEL_CH2(v)   (((v) << 8) & 0xf00)
+#define BP_APBH_DEVSEL_CH1      4
+#define BM_APBH_DEVSEL_CH1      0xf0
+#define BF_APBH_DEVSEL_CH1(v)   (((v) << 4) & 0xf0)
+#define BP_APBH_DEVSEL_CH0      0
+#define BM_APBH_DEVSEL_CH0      0xf
+#define BF_APBH_DEVSEL_CH0(v)   (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_APBH_CHn_CURCMDAR
+ * Address: 0x40+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70))
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_NXTCMDAR
+ * Address: 0x50+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70))
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_CMD
+ * Address: 0x60+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70))
+#define BP_APBH_CHn_CMD_XFER_COUNT              16
+#define BM_APBH_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
+#define BP_APBH_CHn_CMD_CMDWORDS                12
+#define BM_APBH_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBH_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
+#define BP_APBH_CHn_CMD_HALTONTERMINATE         8
+#define BM_APBH_CHn_CMD_HALTONTERMINATE         0x100
+#define BF_APBH_CHn_CMD_HALTONTERMINATE(v)      (((v) << 8) & 0x100)
+#define BP_APBH_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
+#define BP_APBH_CHn_CMD_SEMAPHORE               6
+#define BM_APBH_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBH_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
+#define BP_APBH_CHn_CMD_NANDWAIT4READY          5
+#define BM_APBH_CHn_CMD_NANDWAIT4READY          0x20
+#define BF_APBH_CHn_CMD_NANDWAIT4READY(v)       (((v) << 5) & 0x20)
+#define BP_APBH_CHn_CMD_NANDLOCK                4
+#define BM_APBH_CHn_CMD_NANDLOCK                0x10
+#define BF_APBH_CHn_CMD_NANDLOCK(v)             (((v) << 4) & 0x10)
+#define BP_APBH_CHn_CMD_IRQONCMPLT              3
+#define BM_APBH_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBH_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
+#define BP_APBH_CHn_CMD_CHAIN                   2
+#define BM_APBH_CHn_CMD_CHAIN                   0x4
+#define BF_APBH_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
+#define BP_APBH_CHn_CMD_COMMAND                 0
+#define BM_APBH_CHn_CMD_COMMAND                 0x3
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE      0x3
+#define BF_APBH_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
+#define BF_APBH_CHn_CMD_COMMAND_V(v)            ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3)
+
+/**
+ * Register: HW_APBH_CHn_BAR
+ * Address: 0x70+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70))
+#define BP_APBH_CHn_BAR_ADDRESS     0
+#define BM_APBH_CHn_BAR_ADDRESS     0xffffffff
+#define BF_APBH_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBH_CHn_SEMA
+ * Address: 0x80+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70))
+#define BP_APBH_CHn_SEMA_PHORE              16
+#define BM_APBH_CHn_SEMA_PHORE              0xff0000
+#define BF_APBH_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA     0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA     0xff
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBH_CHn_DEBUG1
+ * Address: 0x90+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70))
+#define BP_APBH_CHn_DEBUG1_REQ                          31
+#define BM_APBH_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBH_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
+#define BP_APBH_CHn_DEBUG1_BURST                        30
+#define BM_APBH_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBH_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
+#define BP_APBH_CHn_DEBUG1_KICK                         29
+#define BM_APBH_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBH_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
+#define BP_APBH_CHn_DEBUG1_END                          28
+#define BM_APBH_CHn_DEBUG1_END                          0x10000000
+#define BF_APBH_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
+#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
+#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
+#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
+
+/**
+ * Register: HW_APBH_CHn_DEBUG2
+ * Address: 0xa0+n*0x70
+ * SCT: no
+*/
+#define HW_APBH_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBH_BASE + 0xa0+(n)*0x70))
+#define BP_APBH_CHn_DEBUG2_APB_BYTES    16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES    0xffff0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES    0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES    0xffff
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBH_VERSION
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_APBH_VERSION             (*(volatile unsigned long *)(REGS_APBH_BASE + 0x3f0))
+#define BP_APBH_VERSION_MAJOR       24
+#define BM_APBH_VERSION_MAJOR       0xff000000
+#define BF_APBH_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_APBH_VERSION_MINOR       16
+#define BM_APBH_VERSION_MINOR       0xff0000
+#define BF_APBH_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_APBH_VERSION_STEP        0
+#define BM_APBH_VERSION_STEP        0xffff
+#define BF_APBH_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__APBH__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h
new file mode 100644
index 0000000000..5f93e5de3c
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h
@@ -0,0 +1,294 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__APBX__H__
+#define __HEADERGEN__STMP3700__APBX__H__
+
+#define REGS_APBX_BASE (0x80024000)
+
+#define REGS_APBX_VERSION "3.2.0"
+
+/**
+ * Register: HW_APBX_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_APBX_CTRL0                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0))
+#define HW_APBX_CTRL0_SET                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4))
+#define HW_APBX_CTRL0_CLR                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8))
+#define HW_APBX_CTRL0_TOG                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc))
+#define BP_APBX_CTRL0_SFTRST                    31
+#define BM_APBX_CTRL0_SFTRST                    0x80000000
+#define BF_APBX_CTRL0_SFTRST(v)                 (((v) << 31) & 0x80000000)
+#define BP_APBX_CTRL0_CLKGATE                   30
+#define BM_APBX_CTRL0_CLKGATE                   0x40000000
+#define BF_APBX_CTRL0_CLKGATE(v)                (((v) << 30) & 0x40000000)
+#define BP_APBX_CTRL0_RESET_CHANNEL             16
+#define BM_APBX_CTRL0_RESET_CHANNEL             0xff0000
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN    0x1
+#define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT   0x2
+#define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX   0x4
+#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF2      0x4
+#define BV_APBX_CTRL0_RESET_CHANNEL__I2C        0x8
+#define BV_APBX_CTRL0_RESET_CHANNEL__SAIF1      0x10
+#define BV_APBX_CTRL0_RESET_CHANNEL__DRI        0x20
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX    0x40
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX    0x40
+#define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX    0x80
+#define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX    0x80
+#define BF_APBX_CTRL0_RESET_CHANNEL(v)          (((v) << 16) & 0xff0000)
+#define BF_APBX_CTRL0_RESET_CHANNEL_V(v)        ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000)
+#define BP_APBX_CTRL0_FREEZE_CHANNEL            0
+#define BM_APBX_CTRL0_FREEZE_CHANNEL            0xff
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN   0x1
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT  0x2
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX  0x4
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF2     0x4
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C       0x8
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF1     0x10
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI       0x20
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX   0x40
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX   0x40
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX   0x80
+#define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX   0x80
+#define BF_APBX_CTRL0_FREEZE_CHANNEL(v)         (((v) << 0) & 0xff)
+#define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v)       ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff)
+
+/**
+ * Register: HW_APBX_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_APBX_CTRL1                       (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0))
+#define HW_APBX_CTRL1_SET                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4))
+#define HW_APBX_CTRL1_CLR                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8))
+#define HW_APBX_CTRL1_TOG                   (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc))
+#define BP_APBX_CTRL1_CH_AHB_ERROR_IRQ      16
+#define BM_APBX_CTRL1_CH_AHB_ERROR_IRQ      0xff0000
+#define BF_APBX_CTRL1_CH_AHB_ERROR_IRQ(v)   (((v) << 16) & 0xff0000)
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    8
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN    0xff00
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00)
+#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ       0
+#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ       0xff
+#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBX_DEVSEL
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_APBX_DEVSEL                  (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20))
+#define BP_APBX_DEVSEL_CH7              28
+#define BM_APBX_DEVSEL_CH7              0xf0000000
+#define BV_APBX_DEVSEL_CH7__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH7__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH7(v)           (((v) << 28) & 0xf0000000)
+#define BF_APBX_DEVSEL_CH7_V(v)         ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000)
+#define BP_APBX_DEVSEL_CH6              24
+#define BM_APBX_DEVSEL_CH6              0xf000000
+#define BV_APBX_DEVSEL_CH6__USE_UART    0x0
+#define BV_APBX_DEVSEL_CH6__USE_IRDA    0x1
+#define BF_APBX_DEVSEL_CH6(v)           (((v) << 24) & 0xf000000)
+#define BF_APBX_DEVSEL_CH6_V(v)         ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000)
+#define BP_APBX_DEVSEL_CH5              20
+#define BM_APBX_DEVSEL_CH5              0xf00000
+#define BF_APBX_DEVSEL_CH5(v)           (((v) << 20) & 0xf00000)
+#define BP_APBX_DEVSEL_CH4              16
+#define BM_APBX_DEVSEL_CH4              0xf0000
+#define BF_APBX_DEVSEL_CH4(v)           (((v) << 16) & 0xf0000)
+#define BP_APBX_DEVSEL_CH3              12
+#define BM_APBX_DEVSEL_CH3              0xf000
+#define BF_APBX_DEVSEL_CH3(v)           (((v) << 12) & 0xf000)
+#define BP_APBX_DEVSEL_CH2              8
+#define BM_APBX_DEVSEL_CH2              0xf00
+#define BV_APBX_DEVSEL_CH2__USE_SPDIF   0x0
+#define BV_APBX_DEVSEL_CH2__USE_SAIF2   0x1
+#define BF_APBX_DEVSEL_CH2(v)           (((v) << 8) & 0xf00)
+#define BF_APBX_DEVSEL_CH2_V(v)         ((BV_APBX_DEVSEL_CH2__##v << 8) & 0xf00)
+#define BP_APBX_DEVSEL_CH1              4
+#define BM_APBX_DEVSEL_CH1              0xf0
+#define BF_APBX_DEVSEL_CH1(v)           (((v) << 4) & 0xf0)
+#define BP_APBX_DEVSEL_CH0              0
+#define BM_APBX_DEVSEL_CH0              0xf
+#define BF_APBX_DEVSEL_CH0(v)           (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_APBX_CHn_CURCMDAR
+ * Address: 0x40+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_CURCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70))
+#define BP_APBX_CHn_CURCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_CURCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_NXTCMDAR
+ * Address: 0x50+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_NXTCMDAR(n)             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70))
+#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR       0
+#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR       0xffffffff
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_CMD
+ * Address: 0x60+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_CMD(n)                      (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70))
+#define BP_APBX_CHn_CMD_XFER_COUNT              16
+#define BM_APBX_CHn_CMD_XFER_COUNT              0xffff0000
+#define BF_APBX_CHn_CMD_XFER_COUNT(v)           (((v) << 16) & 0xffff0000)
+#define BP_APBX_CHn_CMD_CMDWORDS                12
+#define BM_APBX_CHn_CMD_CMDWORDS                0xf000
+#define BF_APBX_CHn_CMD_CMDWORDS(v)             (((v) << 12) & 0xf000)
+#define BP_APBX_CHn_CMD_WAIT4ENDCMD             7
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD             0x80
+#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v)          (((v) << 7) & 0x80)
+#define BP_APBX_CHn_CMD_SEMAPHORE               6
+#define BM_APBX_CHn_CMD_SEMAPHORE               0x40
+#define BF_APBX_CHn_CMD_SEMAPHORE(v)            (((v) << 6) & 0x40)
+#define BP_APBX_CHn_CMD_IRQONCMPLT              3
+#define BM_APBX_CHn_CMD_IRQONCMPLT              0x8
+#define BF_APBX_CHn_CMD_IRQONCMPLT(v)           (((v) << 3) & 0x8)
+#define BP_APBX_CHn_CMD_CHAIN                   2
+#define BM_APBX_CHn_CMD_CHAIN                   0x4
+#define BF_APBX_CHn_CMD_CHAIN(v)                (((v) << 2) & 0x4)
+#define BP_APBX_CHn_CMD_COMMAND                 0
+#define BM_APBX_CHn_CMD_COMMAND                 0x3
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER    0x0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE      0x1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ       0x2
+#define BF_APBX_CHn_CMD_COMMAND(v)              (((v) << 0) & 0x3)
+#define BF_APBX_CHn_CMD_COMMAND_V(v)            ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3)
+
+/**
+ * Register: HW_APBX_CHn_BAR
+ * Address: 0x70+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_BAR(n)          (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70))
+#define BP_APBX_CHn_BAR_ADDRESS     0
+#define BM_APBX_CHn_BAR_ADDRESS     0xffffffff
+#define BF_APBX_CHn_BAR_ADDRESS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_APBX_CHn_SEMA
+ * Address: 0x80+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_SEMA(n)                 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70))
+#define BP_APBX_CHn_SEMA_PHORE              16
+#define BM_APBX_CHn_SEMA_PHORE              0xff0000
+#define BF_APBX_CHn_SEMA_PHORE(v)           (((v) << 16) & 0xff0000)
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA     0
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA     0xff
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_APBX_CHn_DEBUG1
+ * Address: 0x90+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_DEBUG1(n)                           (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70))
+#define BP_APBX_CHn_DEBUG1_REQ                          31
+#define BM_APBX_CHn_DEBUG1_REQ                          0x80000000
+#define BF_APBX_CHn_DEBUG1_REQ(v)                       (((v) << 31) & 0x80000000)
+#define BP_APBX_CHn_DEBUG1_BURST                        30
+#define BM_APBX_CHn_DEBUG1_BURST                        0x40000000
+#define BF_APBX_CHn_DEBUG1_BURST(v)                     (((v) << 30) & 0x40000000)
+#define BP_APBX_CHn_DEBUG1_KICK                         29
+#define BM_APBX_CHn_DEBUG1_KICK                         0x20000000
+#define BF_APBX_CHn_DEBUG1_KICK(v)                      (((v) << 29) & 0x20000000)
+#define BP_APBX_CHn_DEBUG1_END                          28
+#define BM_APBX_CHn_DEBUG1_END                          0x10000000
+#define BF_APBX_CHn_DEBUG1_END(v)                       (((v) << 28) & 0x10000000)
+#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             24
+#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID             0x1000000
+#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v)          (((v) << 24) & 0x1000000)
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                23
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY                0x800000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v)             (((v) << 23) & 0x800000)
+#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL                 22
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL                 0x400000
+#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v)              (((v) << 22) & 0x400000)
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                21
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY                0x200000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v)             (((v) << 21) & 0x200000)
+#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL                 20
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL                 0x100000
+#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v)              (((v) << 20) & 0x100000)
+#define BP_APBX_CHn_DEBUG1_STATEMACHINE                 0
+#define BM_APBX_CHn_DEBUG1_STATEMACHINE                 0x1f
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE           0x0
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1       0x1
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3       0x2
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2       0x3
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE    0x4
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT       0x5
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4       0x6
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ        0x7
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH     0x8
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT      0x9
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE          0xc
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ       0xd
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN    0xe
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE  0xf
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END       0x15
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT     0x1c
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT     0x1e
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)              (((v) << 0) & 0x1f)
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v)            ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f)
+
+/**
+ * Register: HW_APBX_CHn_DEBUG2
+ * Address: 0xa0+n*0x70
+ * SCT: no
+*/
+#define HW_APBX_CHn_DEBUG2(n)           (*(volatile unsigned long *)(REGS_APBX_BASE + 0xa0+(n)*0x70))
+#define BP_APBX_CHn_DEBUG2_APB_BYTES    16
+#define BM_APBX_CHn_DEBUG2_APB_BYTES    0xffff0000
+#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000)
+#define BP_APBX_CHn_DEBUG2_AHB_BYTES    0
+#define BM_APBX_CHn_DEBUG2_AHB_BYTES    0xffff
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_APBX_VERSION
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_APBX_VERSION             (*(volatile unsigned long *)(REGS_APBX_BASE + 0x3f0))
+#define BP_APBX_VERSION_MAJOR       24
+#define BM_APBX_VERSION_MAJOR       0xff000000
+#define BF_APBX_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_APBX_VERSION_MINOR       16
+#define BM_APBX_VERSION_MINOR       0xff0000
+#define BF_APBX_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_APBX_VERSION_STEP        0
+#define BM_APBX_VERSION_STEP        0xffff
+#define BF_APBX_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__APBX__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h
new file mode 100644
index 0000000000..8bb4cb3e71
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h
@@ -0,0 +1,284 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.4.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__AUDIOIN__H__
+#define __HEADERGEN__STMP3700__AUDIOIN__H__
+
+#define REGS_AUDIOIN_BASE (0x8004c000)
+
+#define REGS_AUDIOIN_VERSION "3.4.0"
+
+/**
+ * Register: HW_AUDIOIN_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_AUDIOIN_CTRL                         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0))
+#define HW_AUDIOIN_CTRL_SET                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4))
+#define HW_AUDIOIN_CTRL_CLR                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8))
+#define HW_AUDIOIN_CTRL_TOG                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc))
+#define BP_AUDIOIN_CTRL_SFTRST                  31
+#define BM_AUDIOIN_CTRL_SFTRST                  0x80000000
+#define BF_AUDIOIN_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_CTRL_CLKGATE                 30
+#define BM_AUDIOIN_CTRL_CLKGATE                 0x40000000
+#define BF_AUDIOIN_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT           16
+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT           0x1f0000
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v)        (((v) << 16) & 0x1f0000)
+#define BP_AUDIOIN_CTRL_LR_SWAP                 10
+#define BM_AUDIOIN_CTRL_LR_SWAP                 0x400
+#define BF_AUDIOIN_CTRL_LR_SWAP(v)              (((v) << 10) & 0x400)
+#define BP_AUDIOIN_CTRL_EDGE_SYNC               9
+#define BM_AUDIOIN_CTRL_EDGE_SYNC               0x200
+#define BF_AUDIOIN_CTRL_EDGE_SYNC(v)            (((v) << 9) & 0x200)
+#define BP_AUDIOIN_CTRL_INVERT_1BIT             8
+#define BM_AUDIOIN_CTRL_INVERT_1BIT             0x100
+#define BF_AUDIOIN_CTRL_INVERT_1BIT(v)          (((v) << 8) & 0x100)
+#define BP_AUDIOIN_CTRL_OFFSET_ENABLE           7
+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE           0x80
+#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v)        (((v) << 7) & 0x80)
+#define BP_AUDIOIN_CTRL_HPF_ENABLE              6
+#define BM_AUDIOIN_CTRL_HPF_ENABLE              0x40
+#define BF_AUDIOIN_CTRL_HPF_ENABLE(v)           (((v) << 6) & 0x40)
+#define BP_AUDIOIN_CTRL_WORD_LENGTH             5
+#define BM_AUDIOIN_CTRL_WORD_LENGTH             0x20
+#define BF_AUDIOIN_CTRL_WORD_LENGTH(v)          (((v) << 5) & 0x20)
+#define BP_AUDIOIN_CTRL_LOOPBACK                4
+#define BM_AUDIOIN_CTRL_LOOPBACK                0x10
+#define BF_AUDIOIN_CTRL_LOOPBACK(v)             (((v) << 4) & 0x10)
+#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      3
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ      0x8
+#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v)   (((v) << 3) & 0x8)
+#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       2
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ       0x4
+#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v)    (((v) << 2) & 0x4)
+#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       1
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN       0x2
+#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOIN_CTRL_RUN                     0
+#define BM_AUDIOIN_CTRL_RUN                     0x1
+#define BF_AUDIOIN_CTRL_RUN(v)                  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOIN_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_AUDIOIN_STAT                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10))
+#define BP_AUDIOIN_STAT_ADC_PRESENT     31
+#define BM_AUDIOIN_STAT_ADC_PRESENT     0x80000000
+#define BF_AUDIOIN_STAT_ADC_PRESENT(v)  (((v) << 31) & 0x80000000)
+
+/**
+ * Register: HW_AUDIOIN_ADCSRR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCSRR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0))
+#define HW_AUDIOIN_ADCSRR_SET                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4))
+#define HW_AUDIOIN_ADCSRR_CLR                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8))
+#define HW_AUDIOIN_ADCSRR_TOG                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc))
+#define BP_AUDIOIN_ADCSRR_OSR                   31
+#define BM_AUDIOIN_ADCSRR_OSR                   0x80000000
+#define BV_AUDIOIN_ADCSRR_OSR__OSR6             0x0
+#define BV_AUDIOIN_ADCSRR_OSR__OSR12            0x1
+#define BF_AUDIOIN_ADCSRR_OSR(v)                (((v) << 31) & 0x80000000)
+#define BF_AUDIOIN_ADCSRR_OSR_V(v)              ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000)
+#define BP_AUDIOIN_ADCSRR_BASEMULT              28
+#define BM_AUDIOIN_ADCSRR_BASEMULT              0x70000000
+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE   0x4
+#define BF_AUDIOIN_ADCSRR_BASEMULT(v)           (((v) << 28) & 0x70000000)
+#define BF_AUDIOIN_ADCSRR_BASEMULT_V(v)         ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000)
+#define BP_AUDIOIN_ADCSRR_SRC_HOLD              24
+#define BM_AUDIOIN_ADCSRR_SRC_HOLD              0x7000000
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v)           (((v) << 24) & 0x7000000)
+#define BP_AUDIOIN_ADCSRR_SRC_INT               16
+#define BM_AUDIOIN_ADCSRR_SRC_INT               0x1f0000
+#define BF_AUDIOIN_ADCSRR_SRC_INT(v)            (((v) << 16) & 0x1f0000)
+#define BP_AUDIOIN_ADCSRR_SRC_FRAC              0
+#define BM_AUDIOIN_ADCSRR_SRC_FRAC              0x1fff
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v)           (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_AUDIOIN_ADCVOLUME
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCVOLUME                        (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0))
+#define HW_AUDIOIN_ADCVOLUME_SET                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4))
+#define HW_AUDIOIN_ADCVOLUME_CLR                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8))
+#define HW_AUDIOIN_ADCVOLUME_TOG                    (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc))
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     28
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT     0x10000000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v)  (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_ADCVOLUME_EN_ZCD                 25
+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD                 0x2000000
+#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v)              (((v) << 25) & 0x2000000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT            16
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT            0xff0000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v)         (((v) << 16) & 0xff0000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    12
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT    0x1000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT           0xff
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v)        (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOIN_ADCDEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCDEBUG                                     (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0))
+#define HW_AUDIOIN_ADCDEBUG_SET                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4))
+#define HW_AUDIOIN_ADCDEBUG_CLR                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8))
+#define HW_AUDIOIN_ADCDEBUG_TOG                                 (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc))
+#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       31
+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA                       0x80000000
+#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v)                    (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    3
+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS    0x8
+#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8)
+#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           2
+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE           0x4
+#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v)        (((v) << 2) & 0x4)
+#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ                            1
+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ                            0x2
+#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v)                         (((v) << 1) & 0x2)
+#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0
+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS                         0x1
+#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v)                      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOIN_ADCVOL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ADCVOL                           (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0))
+#define HW_AUDIOIN_ADCVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4))
+#define HW_AUDIOIN_ADCVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8))
+#define HW_AUDIOIN_ADCVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc))
+#define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     28
+#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING     0x10000000
+#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD                25
+#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD                0x2000000
+#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v)             (((v) << 25) & 0x2000000)
+#define BP_AUDIOIN_ADCVOL_MUTE                      24
+#define BM_AUDIOIN_ADCVOL_MUTE                      0x1000000
+#define BF_AUDIOIN_ADCVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT               12
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT               0x3000
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v)            (((v) << 12) & 0x3000)
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT                 8
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT                 0xf00
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v)              (((v) << 8) & 0xf00)
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT              4
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT              0x30
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v)           (((v) << 4) & 0x30)
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT                0
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT                0xf
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v)             (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_AUDIOIN_MICLINE
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_AUDIOIN_MICLINE                      (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0))
+#define HW_AUDIOIN_MICLINE_SET                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4))
+#define HW_AUDIOIN_MICLINE_CLR                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8))
+#define HW_AUDIOIN_MICLINE_TOG                  (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc))
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1         29
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1         0x20000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v)      (((v) << 29) & 0x20000000)
+#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2         28
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2         0x10000000
+#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v)      (((v) << 28) & 0x10000000)
+#define BP_AUDIOIN_MICLINE_MIC_SELECT           24
+#define BM_AUDIOIN_MICLINE_MIC_SELECT           0x1000000
+#define BF_AUDIOIN_MICLINE_MIC_SELECT(v)        (((v) << 24) & 0x1000000)
+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR         20
+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR         0x300000
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off    0x0
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm  0x1
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm  0x2
+#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm  0x3
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v)      (((v) << 20) & 0x300000)
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v)    ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000)
+#define BP_AUDIOIN_MICLINE_MIC_BIAS             16
+#define BM_AUDIOIN_MICLINE_MIC_BIAS             0x70000
+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v)          (((v) << 16) & 0x70000)
+#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK          4
+#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK          0x30
+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v)       (((v) << 4) & 0x30)
+#define BP_AUDIOIN_MICLINE_MIC_GAIN             0
+#define BM_AUDIOIN_MICLINE_MIC_GAIN             0x3
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB        0x0
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB       0x1
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB       0x2
+#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB       0x3
+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v)          (((v) << 0) & 0x3)
+#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v)        ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3)
+
+/**
+ * Register: HW_AUDIOIN_ANACLKCTRL
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_AUDIOIN_ANACLKCTRL                   (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0))
+#define HW_AUDIOIN_ANACLKCTRL_SET               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4))
+#define HW_AUDIOIN_ANACLKCTRL_CLR               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8))
+#define HW_AUDIOIN_ANACLKCTRL_TOG               (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc))
+#define BP_AUDIOIN_ANACLKCTRL_CLKGATE           31
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE           0x80000000
+#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v)        (((v) << 31) & 0x80000000)
+#define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF        6
+#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF        0x40
+#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v)     (((v) << 6) & 0x40)
+#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER       5
+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER       0x20
+#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v)    (((v) << 5) & 0x20)
+#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     4
+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK     0x10
+#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v)  (((v) << 4) & 0x10)
+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV            0
+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV            0x7
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v)         (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOIN_DATA
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_AUDIOIN_DATA         (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80))
+#define BP_AUDIOIN_DATA_HIGH    16
+#define BM_AUDIOIN_DATA_HIGH    0xffff0000
+#define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000)
+#define BP_AUDIOIN_DATA_LOW     0
+#define BM_AUDIOIN_DATA_LOW     0xffff
+#define BF_AUDIOIN_DATA_LOW(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__AUDIOIN__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h
new file mode 100644
index 0000000000..c45ea1e0d0
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h
@@ -0,0 +1,511 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__AUDIOOUT__H__
+#define __HEADERGEN__STMP3700__AUDIOOUT__H__
+
+#define REGS_AUDIOOUT_BASE (0x80048000)
+
+#define REGS_AUDIOOUT_VERSION "3.2.0"
+
+/**
+ * Register: HW_AUDIOOUT_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_CTRL                        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0))
+#define HW_AUDIOOUT_CTRL_SET                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4))
+#define HW_AUDIOOUT_CTRL_CLR                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8))
+#define HW_AUDIOOUT_CTRL_TOG                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc))
+#define BP_AUDIOOUT_CTRL_SFTRST                 31
+#define BM_AUDIOOUT_CTRL_SFTRST                 0x80000000
+#define BF_AUDIOOUT_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_CTRL_CLKGATE                30
+#define BM_AUDIOOUT_CTRL_CLKGATE                0x40000000
+#define BF_AUDIOOUT_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT          16
+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT          0x1f0000
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
+#define BP_AUDIOOUT_CTRL_LR_SWAP                14
+#define BM_AUDIOOUT_CTRL_LR_SWAP                0x4000
+#define BF_AUDIOOUT_CTRL_LR_SWAP(v)             (((v) << 14) & 0x4000)
+#define BP_AUDIOOUT_CTRL_EDGE_SYNC              13
+#define BM_AUDIOOUT_CTRL_EDGE_SYNC              0x2000
+#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v)           (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_CTRL_INVERT_1BIT            12
+#define BM_AUDIOOUT_CTRL_INVERT_1BIT            0x1000
+#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v)         (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT            8
+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT            0x300
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v)         (((v) << 8) & 0x300)
+#define BP_AUDIOOUT_CTRL_WORD_LENGTH            6
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH            0x40
+#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v)         (((v) << 6) & 0x40)
+#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        5
+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE        0x20
+#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v)     (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_CTRL_LOOPBACK               4
+#define BM_AUDIOOUT_CTRL_LOOPBACK               0x10
+#define BF_AUDIOOUT_CTRL_LOOPBACK(v)            (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     3
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ     0x8
+#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v)  (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      2
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ      0x4
+#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v)   (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      1
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN      0x2
+#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_CTRL_RUN                    0
+#define BM_AUDIOOUT_CTRL_RUN                    0x1
+#define BF_AUDIOOUT_CTRL_RUN(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_AUDIOOUT_STAT                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10))
+#define BP_AUDIOOUT_STAT_DAC_PRESENT    31
+#define BM_AUDIOOUT_STAT_DAC_PRESENT    0x80000000
+#define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000)
+
+/**
+ * Register: HW_AUDIOOUT_DACSRR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACSRR                          (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0))
+#define HW_AUDIOOUT_DACSRR_SET                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4))
+#define HW_AUDIOOUT_DACSRR_CLR                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8))
+#define HW_AUDIOOUT_DACSRR_TOG                      (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc))
+#define BP_AUDIOOUT_DACSRR_OSR                      31
+#define BM_AUDIOOUT_DACSRR_OSR                      0x80000000
+#define BV_AUDIOOUT_DACSRR_OSR__OSR6                0x0
+#define BV_AUDIOOUT_DACSRR_OSR__OSR12               0x1
+#define BF_AUDIOOUT_DACSRR_OSR(v)                   (((v) << 31) & 0x80000000)
+#define BF_AUDIOOUT_DACSRR_OSR_V(v)                 ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000)
+#define BP_AUDIOOUT_DACSRR_BASEMULT                 28
+#define BM_AUDIOOUT_DACSRR_BASEMULT                 0x70000000
+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE    0x1
+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE    0x2
+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE      0x4
+#define BF_AUDIOOUT_DACSRR_BASEMULT(v)              (((v) << 28) & 0x70000000)
+#define BF_AUDIOOUT_DACSRR_BASEMULT_V(v)            ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000)
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD                 24
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD                 0x7000000
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v)              (((v) << 24) & 0x7000000)
+#define BP_AUDIOOUT_DACSRR_SRC_INT                  16
+#define BM_AUDIOOUT_DACSRR_SRC_INT                  0x1f0000
+#define BF_AUDIOOUT_DACSRR_SRC_INT(v)               (((v) << 16) & 0x1f0000)
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC                 0
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC                 0x1fff
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v)              (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_AUDIOOUT_DACVOLUME
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACVOLUME                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0))
+#define HW_AUDIOOUT_DACVOLUME_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4))
+#define HW_AUDIOOUT_DACVOLUME_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8))
+#define HW_AUDIOOUT_DACVOLUME_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc))
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        28
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT        0x10000000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v)     (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_DACVOLUME_EN_ZCD                    25
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD                    0x2000000
+#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v)                 (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT                 24
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT                 0x1000000
+#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v)              (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT               16
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT               0xff0000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v)            (((v) << 16) & 0xff0000)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       12
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT       0x1000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v)    (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT                8
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT                0x100
+#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v)             (((v) << 8) & 0x100)
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT              0xff
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v)           (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOOUT_DACDEBUG
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DACDEBUG                                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0))
+#define HW_AUDIOOUT_DACDEBUG_SET                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4))
+#define HW_AUDIOOUT_DACDEBUG_CLR                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8))
+#define HW_AUDIOOUT_DACDEBUG_TOG                            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc))
+#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  31
+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA                  0x80000000
+#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v)               (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_DACDEBUG_RAM_SS                         8
+#define BM_AUDIOOUT_DACDEBUG_RAM_SS                         0xf00
+#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v)                      (((v) << 8) & 0xf00)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       5
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS       0x20
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v)    (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       4
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS       0x10
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v)    (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      3
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE      0x8
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v)   (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      2
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE      0x4
+#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v)   (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ                       1
+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ                       0x2
+#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v)                    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0
+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS                    0x1
+#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_HPVOL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_HPVOL                           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0))
+#define HW_AUDIOOUT_HPVOL_SET                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4))
+#define HW_AUDIOOUT_HPVOL_CLR                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8))
+#define HW_AUDIOOUT_HPVOL_TOG                       (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc))
+#define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     28
+#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING     0x10000000
+#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v)  (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD               25
+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD               0x2000000
+#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v)            (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_HPVOL_MUTE                      24
+#define BM_AUDIOOUT_HPVOL_MUTE                      0x1000000
+#define BF_AUDIOOUT_HPVOL_MUTE(v)                   (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_HPVOL_SELECT                    16
+#define BM_AUDIOOUT_HPVOL_SELECT                    0x10000
+#define BF_AUDIOOUT_HPVOL_SELECT(v)                 (((v) << 16) & 0x10000)
+#define BP_AUDIOOUT_HPVOL_VOL_LEFT                  8
+#define BM_AUDIOOUT_HPVOL_VOL_LEFT                  0x7f00
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v)               (((v) << 8) & 0x7f00)
+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT                 0
+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT                 0x7f
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v)              (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_AUDIOOUT_RESERVED
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_AUDIOOUT_RESERVED    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60))
+
+/**
+ * Register: HW_AUDIOOUT_PWRDN
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_PWRDN               (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0))
+#define HW_AUDIOOUT_PWRDN_SET           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4))
+#define HW_AUDIOOUT_PWRDN_CLR           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8))
+#define HW_AUDIOOUT_PWRDN_TOG           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc))
+#define BP_AUDIOOUT_PWRDN_LINEOUT       24
+#define BM_AUDIOOUT_PWRDN_LINEOUT       0x1000000
+#define BF_AUDIOOUT_PWRDN_LINEOUT(v)    (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_PWRDN_SELFBIAS      20
+#define BM_AUDIOOUT_PWRDN_SELFBIAS      0x100000
+#define BF_AUDIOOUT_PWRDN_SELFBIAS(v)   (((v) << 20) & 0x100000)
+#define BP_AUDIOOUT_PWRDN_RIGHT_ADC     16
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC     0x10000
+#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v)  (((v) << 16) & 0x10000)
+#define BP_AUDIOOUT_PWRDN_DAC           12
+#define BM_AUDIOOUT_PWRDN_DAC           0x1000
+#define BF_AUDIOOUT_PWRDN_DAC(v)        (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_PWRDN_ADC           8
+#define BM_AUDIOOUT_PWRDN_ADC           0x100
+#define BF_AUDIOOUT_PWRDN_ADC(v)        (((v) << 8) & 0x100)
+#define BP_AUDIOOUT_PWRDN_CAPLESS       4
+#define BM_AUDIOOUT_PWRDN_CAPLESS       0x10
+#define BF_AUDIOOUT_PWRDN_CAPLESS(v)    (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_PWRDN_HEADPHONE     0
+#define BM_AUDIOOUT_PWRDN_HEADPHONE     0x1
+#define BF_AUDIOOUT_PWRDN_HEADPHONE(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_REFCTRL
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_REFCTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0))
+#define HW_AUDIOOUT_REFCTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4))
+#define HW_AUDIOOUT_REFCTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8))
+#define HW_AUDIOOUT_REFCTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc))
+#define BP_AUDIOOUT_REFCTRL_FASTSETTLING        26
+#define BM_AUDIOOUT_REFCTRL_FASTSETTLING        0x4000000
+#define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v)     (((v) << 26) & 0x4000000)
+#define BP_AUDIOOUT_REFCTRL_RAISE_REF           25
+#define BM_AUDIOOUT_REFCTRL_RAISE_REF           0x2000000
+#define BF_AUDIOOUT_REFCTRL_RAISE_REF(v)        (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       24
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS       0x1000000
+#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v)    (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ             20
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ             0x700000
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v)          (((v) << 20) & 0x700000)
+#define BP_AUDIOOUT_REFCTRL_LOW_PWR             19
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR             0x80000
+#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v)          (((v) << 19) & 0x80000)
+#define BP_AUDIOOUT_REFCTRL_LW_REF              18
+#define BM_AUDIOOUT_REFCTRL_LW_REF              0x40000
+#define BF_AUDIOOUT_REFCTRL_LW_REF(v)           (((v) << 18) & 0x40000)
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL           16
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL           0x30000
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v)        (((v) << 16) & 0x30000)
+#define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     14
+#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD     0x4000
+#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v)  (((v) << 14) & 0x4000)
+#define BP_AUDIOOUT_REFCTRL_ADJ_ADC             13
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC             0x2000
+#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v)          (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_REFCTRL_ADJ_VAG             12
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG             0x1000
+#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v)          (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL          8
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL          0xf00
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v)       (((v) << 8) & 0xf00)
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL             4
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL             0xf0
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v)          (((v) << 4) & 0xf0)
+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ             0
+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ             0x7
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v)          (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOOUT_ANACTRL
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_ANACTRL                     (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0))
+#define HW_AUDIOOUT_ANACTRL_SET                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4))
+#define HW_AUDIOOUT_ANACTRL_CLR                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8))
+#define HW_AUDIOOUT_ANACTRL_TOG                 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc))
+#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS        28
+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS        0x10000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v)     (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS        24
+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS        0x1000000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v)     (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM        20
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM        0x300000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v)     (((v) << 20) & 0x300000)
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR        17
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR        0x60000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v)     (((v) << 17) & 0x60000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL       12
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL       0x7000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v)    (((v) << 12) & 0x7000)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR       8
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR       0x700
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v)    (((v) << 8) & 0x700)
+#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND         5
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND         0x20
+#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v)      (((v) << 5) & 0x20)
+#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB          4
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB          0x10
+#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v)       (((v) << 4) & 0x10)
+
+/**
+ * Register: HW_AUDIOOUT_TEST
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_TEST                    (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0))
+#define HW_AUDIOOUT_TEST_SET                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4))
+#define HW_AUDIOOUT_TEST_CLR                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8))
+#define HW_AUDIOOUT_TEST_TOG                (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc))
+#define BP_AUDIOOUT_TEST_HP_ANTIPOP         28
+#define BM_AUDIOOUT_TEST_HP_ANTIPOP         0x70000000
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v)      (((v) << 28) & 0x70000000)
+#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP      26
+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP      0x4000000
+#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v)   (((v) << 26) & 0x4000000)
+#define BP_AUDIOOUT_TEST_TM_LINEOUT         25
+#define BM_AUDIOOUT_TEST_TM_LINEOUT         0x2000000
+#define BF_AUDIOOUT_TEST_TM_LINEOUT(v)      (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_TEST_TM_HPCOMMON        24
+#define BM_AUDIOOUT_TEST_TM_HPCOMMON        0x1000000
+#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v)     (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ          22
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ          0xc00000
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v)       (((v) << 22) & 0xc00000)
+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ        20
+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ        0x300000
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v)     (((v) << 20) & 0x300000)
+#define BP_AUDIOOUT_TEST_VAG_CLASSA         13
+#define BM_AUDIOOUT_TEST_VAG_CLASSA         0x2000
+#define BF_AUDIOOUT_TEST_VAG_CLASSA(v)      (((v) << 13) & 0x2000)
+#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I       12
+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I       0x1000
+#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v)    (((v) << 12) & 0x1000)
+#define BP_AUDIOOUT_TEST_DAC_CLASSA         2
+#define BM_AUDIOOUT_TEST_DAC_CLASSA         0x4
+#define BF_AUDIOOUT_TEST_DAC_CLASSA(v)      (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I       1
+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I       0x2
+#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ        0
+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ        0x1
+#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_BISTCTRL
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_BISTCTRL            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0))
+#define HW_AUDIOOUT_BISTCTRL_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4))
+#define HW_AUDIOOUT_BISTCTRL_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8))
+#define HW_AUDIOOUT_BISTCTRL_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc))
+#define BP_AUDIOOUT_BISTCTRL_FAIL       3
+#define BM_AUDIOOUT_BISTCTRL_FAIL       0x8
+#define BF_AUDIOOUT_BISTCTRL_FAIL(v)    (((v) << 3) & 0x8)
+#define BP_AUDIOOUT_BISTCTRL_PASS       2
+#define BM_AUDIOOUT_BISTCTRL_PASS       0x4
+#define BF_AUDIOOUT_BISTCTRL_PASS(v)    (((v) << 2) & 0x4)
+#define BP_AUDIOOUT_BISTCTRL_DONE       1
+#define BM_AUDIOOUT_BISTCTRL_DONE       0x2
+#define BF_AUDIOOUT_BISTCTRL_DONE(v)    (((v) << 1) & 0x2)
+#define BP_AUDIOOUT_BISTCTRL_START      0
+#define BM_AUDIOOUT_BISTCTRL_START      0x1
+#define BF_AUDIOOUT_BISTCTRL_START(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_AUDIOOUT_BISTSTAT0
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_AUDIOOUT_BISTSTAT0           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0))
+#define BP_AUDIOOUT_BISTSTAT0_DATA      0
+#define BM_AUDIOOUT_BISTSTAT0_DATA      0xffffff
+#define BF_AUDIOOUT_BISTSTAT0_DATA(v)   (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_AUDIOOUT_BISTSTAT1
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_AUDIOOUT_BISTSTAT1           (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0))
+#define BP_AUDIOOUT_BISTSTAT1_STATE     24
+#define BM_AUDIOOUT_BISTSTAT1_STATE     0x1f000000
+#define BF_AUDIOOUT_BISTSTAT1_STATE(v)  (((v) << 24) & 0x1f000000)
+#define BP_AUDIOOUT_BISTSTAT1_ADDR      0
+#define BM_AUDIOOUT_BISTSTAT1_ADDR      0xff
+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_AUDIOOUT_ANACLKCTRL
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_ANACLKCTRL                  (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0))
+#define HW_AUDIOOUT_ANACLKCTRL_SET              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4))
+#define HW_AUDIOOUT_ANACLKCTRL_CLR              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8))
+#define HW_AUDIOOUT_ANACLKCTRL_TOG              (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc))
+#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE          31
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE          0x80000000
+#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    4
+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK    0x10
+#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10)
+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV           0
+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV           0x7
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v)        (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_AUDIOOUT_DATA
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_DATA            (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0))
+#define HW_AUDIOOUT_DATA_SET        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4))
+#define HW_AUDIOOUT_DATA_CLR        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8))
+#define HW_AUDIOOUT_DATA_TOG        (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc))
+#define BP_AUDIOOUT_DATA_HIGH       16
+#define BM_AUDIOOUT_DATA_HIGH       0xffff0000
+#define BF_AUDIOOUT_DATA_HIGH(v)    (((v) << 16) & 0xffff0000)
+#define BP_AUDIOOUT_DATA_LOW        0
+#define BM_AUDIOOUT_DATA_LOW        0xffff
+#define BF_AUDIOOUT_DATA_LOW(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_AUDIOOUT_LINEOUTCTRL
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_AUDIOOUT_LINEOUTCTRL                             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x0))
+#define HW_AUDIOOUT_LINEOUTCTRL_SET                         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x4))
+#define HW_AUDIOOUT_LINEOUTCTRL_CLR                         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x8))
+#define HW_AUDIOOUT_LINEOUTCTRL_TOG                         (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0xc))
+#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING       28
+#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING       0x10000000
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING(v)    (((v) << 28) & 0x10000000)
+#define BP_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD              25
+#define BM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD              0x2000000
+#define BF_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD(v)           (((v) << 25) & 0x2000000)
+#define BP_AUDIOOUT_LINEOUTCTRL_MUTE                        24
+#define BM_AUDIOOUT_LINEOUTCTRL_MUTE                        0x1000000
+#define BF_AUDIOOUT_LINEOUTCTRL_MUTE(v)                     (((v) << 24) & 0x1000000)
+#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL                    20
+#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL                    0xf00000
+#define BF_AUDIOOUT_LINEOUTCTRL_VAG_CTRL(v)                 (((v) << 20) & 0xf00000)
+#define BP_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT                 16
+#define BM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT                 0xf0000
+#define BF_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT(v)              (((v) << 16) & 0xf0000)
+#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP                  13
+#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP                  0xe000
+#define BF_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP(v)               (((v) << 13) & 0xe000)
+#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT                 8
+#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT                 0x1f00
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT(v)              (((v) << 8) & 0x1f00)
+#define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT                0
+#define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT                0x1f
+#define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT(v)             (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_AUDIOOUT_VERSION
+ * Address: 0x200
+ * SCT: no
+*/
+#define HW_AUDIOOUT_VERSION             (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x200))
+#define BP_AUDIOOUT_VERSION_MAJOR       24
+#define BM_AUDIOOUT_VERSION_MAJOR       0xff000000
+#define BF_AUDIOOUT_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_AUDIOOUT_VERSION_MINOR       16
+#define BM_AUDIOOUT_VERSION_MINOR       0xff0000
+#define BF_AUDIOOUT_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_AUDIOOUT_VERSION_STEP        0
+#define BM_AUDIOOUT_VERSION_STEP        0xffff
+#define BF_AUDIOOUT_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__AUDIOOUT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h
new file mode 100644
index 0000000000..0449161d11
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h
@@ -0,0 +1,459 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__CLKCTRL__H__
+#define __HEADERGEN__STMP3700__CLKCTRL__H__
+
+#define REGS_CLKCTRL_BASE (0x80040000)
+
+#define REGS_CLKCTRL_VERSION "3.2.0"
+
+/**
+ * Register: HW_CLKCTRL_PLLCTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_CLKCTRL_PLLCTRL0                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0))
+#define HW_CLKCTRL_PLLCTRL0_SET                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4))
+#define HW_CLKCTRL_PLLCTRL0_CLR                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8))
+#define HW_CLKCTRL_PLLCTRL0_TOG                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc))
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL             28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL             0x30000000
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2    0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05   0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)          (((v) << 28) & 0x30000000)
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000)
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL              24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL              0x3000000
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT     0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2     0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05    0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED   0x3
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)           (((v) << 24) & 0x3000000)
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v)         ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000)
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL             20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL             0x300000
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT    0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER      0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST     0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED  0x3
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)          (((v) << 20) & 0x300000)
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v)        ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000)
+#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS         18
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS         0x40000
+#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v)      (((v) << 18) & 0x40000)
+#define BP_CLKCTRL_PLLCTRL0_POWER               16
+#define BM_CLKCTRL_PLLCTRL0_POWER               0x10000
+#define BF_CLKCTRL_PLLCTRL0_POWER(v)            (((v) << 16) & 0x10000)
+
+/**
+ * Register: HW_CLKCTRL_PLLCTRL1
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_CLKCTRL_PLLCTRL1                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10))
+#define BP_CLKCTRL_PLLCTRL1_LOCK            31
+#define BM_CLKCTRL_PLLCTRL1_LOCK            0x80000000
+#define BF_CLKCTRL_PLLCTRL1_LOCK(v)         (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK      30
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK      0x40000000
+#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v)   (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT      0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT      0xffff
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_CLKCTRL_CPU
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_CLKCTRL_CPU                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0))
+#define HW_CLKCTRL_CPU_SET                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4))
+#define HW_CLKCTRL_CPU_CLR                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8))
+#define HW_CLKCTRL_CPU_TOG                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc))
+#define BP_CLKCTRL_CPU_BUSY_REF_XTAL        29
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL        0x20000000
+#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_CPU_BUSY_REF_CPU         28
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU         0x10000000
+#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v)      (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     26
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN     0x4000000
+#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v)  (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_CPU_DIV_XTAL             16
+#define BM_CLKCTRL_CPU_DIV_XTAL             0x3ff0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)          (((v) << 16) & 0x3ff0000)
+#define BP_CLKCTRL_CPU_INTERRUPT_WAIT       12
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT       0x1000
+#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v)    (((v) << 12) & 0x1000)
+#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN      10
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN      0x400
+#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v)   (((v) << 10) & 0x400)
+#define BP_CLKCTRL_CPU_DIV_CPU              0
+#define BM_CLKCTRL_CPU_DIV_CPU              0x3ff
+#define BF_CLKCTRL_CPU_DIV_CPU(v)           (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_HBUS
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_CLKCTRL_HBUS                             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0))
+#define HW_CLKCTRL_HBUS_SET                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4))
+#define HW_CLKCTRL_HBUS_CLR                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8))
+#define HW_CLKCTRL_HBUS_TOG                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc))
+#define BP_CLKCTRL_HBUS_BUSY                        29
+#define BM_CLKCTRL_HBUS_BUSY                        0x20000000
+#define BF_CLKCTRL_HBUS_BUSY(v)                     (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           26
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE           0x4000000
+#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v)        (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           25
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE           0x2000000
+#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v)        (((v) << 25) & 0x2000000)
+#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       24
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE       0x1000000
+#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v)    (((v) << 24) & 0x1000000)
+#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           23
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE           0x800000
+#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v)        (((v) << 23) & 0x800000)
+#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          22
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE          0x400000
+#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v)       (((v) << 22) & 0x400000)
+#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         21
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE         0x200000
+#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v)      (((v) << 21) & 0x200000)
+#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE              20
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE              0x100000
+#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v)           (((v) << 20) & 0x100000)
+#define BP_CLKCTRL_HBUS_SLOW_DIV                    16
+#define BM_CLKCTRL_HBUS_SLOW_DIV                    0x70000
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1               0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2               0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4               0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8               0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16              0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32              0x5
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)                 (((v) << 16) & 0x70000)
+#define BF_CLKCTRL_HBUS_SLOW_DIV_V(v)               ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000)
+#define BP_CLKCTRL_HBUS_DIV_FRAC_EN                 5
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN                 0x20
+#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v)              (((v) << 5) & 0x20)
+#define BP_CLKCTRL_HBUS_DIV                         0
+#define BM_CLKCTRL_HBUS_DIV                         0x1f
+#define BF_CLKCTRL_HBUS_DIV(v)                      (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_CLKCTRL_XBUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_CLKCTRL_XBUS                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40))
+#define BP_CLKCTRL_XBUS_BUSY            31
+#define BM_CLKCTRL_XBUS_BUSY            0x80000000
+#define BF_CLKCTRL_XBUS_BUSY(v)         (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_XBUS_DIV_FRAC_EN     10
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x400
+#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
+#define BP_CLKCTRL_XBUS_DIV             0
+#define BM_CLKCTRL_XBUS_DIV             0x3ff
+#define BF_CLKCTRL_XBUS_DIV(v)          (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_XTAL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_CLKCTRL_XTAL                         (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0))
+#define HW_CLKCTRL_XTAL_SET                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4))
+#define HW_CLKCTRL_XTAL_CLR                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8))
+#define HW_CLKCTRL_XTAL_TOG                     (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc))
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE           31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE           0x80000000
+#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v)        (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
+#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v)     (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE         29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE         0x20000000
+#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v)      (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE         28
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE         0x10000000
+#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v)      (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      27
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x8000000
+#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v)   (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x4000000
+#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v)   (((v) << 26) & 0x4000000)
+#define BP_CLKCTRL_XTAL_DIV_UART                0
+#define BM_CLKCTRL_XTAL_DIV_UART                0x3
+#define BF_CLKCTRL_XTAL_DIV_UART(v)             (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_CLKCTRL_PIX
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_CLKCTRL_PIX                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60))
+#define BP_CLKCTRL_PIX_CLKGATE          31
+#define BM_CLKCTRL_PIX_CLKGATE          0x80000000
+#define BF_CLKCTRL_PIX_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_PIX_BUSY             29
+#define BM_CLKCTRL_PIX_BUSY             0x20000000
+#define BF_CLKCTRL_PIX_BUSY(v)          (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_PIX_DIV_FRAC_EN      15
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x8000
+#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v)   (((v) << 15) & 0x8000)
+#define BP_CLKCTRL_PIX_DIV              0
+#define BM_CLKCTRL_PIX_DIV              0x7fff
+#define BF_CLKCTRL_PIX_DIV(v)           (((v) << 0) & 0x7fff)
+
+/**
+ * Register: HW_CLKCTRL_SSP
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_CLKCTRL_SSP                  (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70))
+#define BP_CLKCTRL_SSP_CLKGATE          31
+#define BM_CLKCTRL_SSP_CLKGATE          0x80000000
+#define BF_CLKCTRL_SSP_CLKGATE(v)       (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_SSP_BUSY             29
+#define BM_CLKCTRL_SSP_BUSY             0x20000000
+#define BF_CLKCTRL_SSP_BUSY(v)          (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_SSP_DIV_FRAC_EN      9
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x200
+#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v)   (((v) << 9) & 0x200)
+#define BP_CLKCTRL_SSP_DIV              0
+#define BM_CLKCTRL_SSP_DIV              0x1ff
+#define BF_CLKCTRL_SSP_DIV(v)           (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_CLKCTRL_GPMI
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_CLKCTRL_GPMI                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80))
+#define BP_CLKCTRL_GPMI_CLKGATE         31
+#define BM_CLKCTRL_GPMI_CLKGATE         0x80000000
+#define BF_CLKCTRL_GPMI_CLKGATE(v)      (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_GPMI_BUSY            29
+#define BM_CLKCTRL_GPMI_BUSY            0x20000000
+#define BF_CLKCTRL_GPMI_BUSY(v)         (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_GPMI_DIV_FRAC_EN     10
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x400
+#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v)  (((v) << 10) & 0x400)
+#define BP_CLKCTRL_GPMI_DIV             0
+#define BM_CLKCTRL_GPMI_DIV             0x3ff
+#define BF_CLKCTRL_GPMI_DIV(v)          (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_SPDIF
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_CLKCTRL_SPDIF            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90))
+#define BP_CLKCTRL_SPDIF_CLKGATE    31
+#define BM_CLKCTRL_SPDIF_CLKGATE    0x80000000
+#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000)
+
+/**
+ * Register: HW_CLKCTRL_EMI
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_CLKCTRL_EMI                      (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0))
+#define BP_CLKCTRL_EMI_CLKGATE              31
+#define BM_CLKCTRL_EMI_CLKGATE              0x80000000
+#define BF_CLKCTRL_EMI_CLKGATE(v)           (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_EMI_BUSY_REF_XTAL        29
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL        0x20000000
+#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v)     (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_EMI_BUSY_REF_EMI         28
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI         0x10000000
+#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v)      (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC      17
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC      0x20000
+#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v)   (((v) << 17) & 0x20000)
+#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE    16
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE    0x10000
+#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000)
+#define BP_CLKCTRL_EMI_DIV_XTAL             8
+#define BM_CLKCTRL_EMI_DIV_XTAL             0xf00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)          (((v) << 8) & 0xf00)
+#define BP_CLKCTRL_EMI_DIV_EMI              0
+#define BM_CLKCTRL_EMI_DIV_EMI              0x3f
+#define BF_CLKCTRL_EMI_DIV_EMI(v)           (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_CLKCTRL_IR
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_CLKCTRL_IR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0))
+#define BP_CLKCTRL_IR_CLKGATE       31
+#define BM_CLKCTRL_IR_CLKGATE       0x80000000
+#define BF_CLKCTRL_IR_CLKGATE(v)    (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_IR_AUTO_DIV      29
+#define BM_CLKCTRL_IR_AUTO_DIV      0x20000000
+#define BF_CLKCTRL_IR_AUTO_DIV(v)   (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_IR_IR_BUSY       28
+#define BM_CLKCTRL_IR_IR_BUSY       0x10000000
+#define BF_CLKCTRL_IR_IR_BUSY(v)    (((v) << 28) & 0x10000000)
+#define BP_CLKCTRL_IR_IROV_BUSY     27
+#define BM_CLKCTRL_IR_IROV_BUSY     0x8000000
+#define BF_CLKCTRL_IR_IROV_BUSY(v)  (((v) << 27) & 0x8000000)
+#define BP_CLKCTRL_IR_IROV_DIV      16
+#define BM_CLKCTRL_IR_IROV_DIV      0x1ff0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)   (((v) << 16) & 0x1ff0000)
+#define BP_CLKCTRL_IR_IR_DIV        0
+#define BM_CLKCTRL_IR_IR_DIV        0x3ff
+#define BF_CLKCTRL_IR_IR_DIV(v)     (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_CLKCTRL_SAIF
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_CLKCTRL_SAIF                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0))
+#define BP_CLKCTRL_SAIF_CLKGATE         31
+#define BM_CLKCTRL_SAIF_CLKGATE         0x80000000
+#define BF_CLKCTRL_SAIF_CLKGATE(v)      (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_SAIF_BUSY            29
+#define BM_CLKCTRL_SAIF_BUSY            0x20000000
+#define BF_CLKCTRL_SAIF_BUSY(v)         (((v) << 29) & 0x20000000)
+#define BP_CLKCTRL_SAIF_DIV_FRAC_EN     16
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x10000
+#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v)  (((v) << 16) & 0x10000)
+#define BP_CLKCTRL_SAIF_DIV             0
+#define BM_CLKCTRL_SAIF_DIV             0xffff
+#define BF_CLKCTRL_SAIF_DIV(v)          (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_CLKCTRL_FRAC
+ * Address: 0xd0
+ * SCT: yes
+*/
+#define HW_CLKCTRL_FRAC                 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x0))
+#define HW_CLKCTRL_FRAC_SET             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x4))
+#define HW_CLKCTRL_FRAC_CLR             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x8))
+#define HW_CLKCTRL_FRAC_TOG             (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0xc))
+#define BP_CLKCTRL_FRAC_CLKGATEIO       31
+#define BM_CLKCTRL_FRAC_CLKGATEIO       0x80000000
+#define BF_CLKCTRL_FRAC_CLKGATEIO(v)    (((v) << 31) & 0x80000000)
+#define BP_CLKCTRL_FRAC_IO_STABLE       30
+#define BM_CLKCTRL_FRAC_IO_STABLE       0x40000000
+#define BF_CLKCTRL_FRAC_IO_STABLE(v)    (((v) << 30) & 0x40000000)
+#define BP_CLKCTRL_FRAC_IOFRAC          24
+#define BM_CLKCTRL_FRAC_IOFRAC          0x3f000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v)       (((v) << 24) & 0x3f000000)
+#define BP_CLKCTRL_FRAC_CLKGATEPIX      23
+#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x800000
+#define BF_CLKCTRL_FRAC_CLKGATEPIX(v)   (((v) << 23) & 0x800000)
+#define BP_CLKCTRL_FRAC_PIX_STABLE      22
+#define BM_CLKCTRL_FRAC_PIX_STABLE      0x400000
+#define BF_CLKCTRL_FRAC_PIX_STABLE(v)   (((v) << 22) & 0x400000)
+#define BP_CLKCTRL_FRAC_PIXFRAC         16
+#define BM_CLKCTRL_FRAC_PIXFRAC         0x3f0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v)      (((v) << 16) & 0x3f0000)
+#define BP_CLKCTRL_FRAC_CLKGATEEMI      15
+#define BM_CLKCTRL_FRAC_CLKGATEEMI      0x8000
+#define BF_CLKCTRL_FRAC_CLKGATEEMI(v)   (((v) << 15) & 0x8000)
+#define BP_CLKCTRL_FRAC_EMI_STABLE      14
+#define BM_CLKCTRL_FRAC_EMI_STABLE      0x4000
+#define BF_CLKCTRL_FRAC_EMI_STABLE(v)   (((v) << 14) & 0x4000)
+#define BP_CLKCTRL_FRAC_EMIFRAC         8
+#define BM_CLKCTRL_FRAC_EMIFRAC         0x3f00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v)      (((v) << 8) & 0x3f00)
+#define BP_CLKCTRL_FRAC_CLKGATECPU      7
+#define BM_CLKCTRL_FRAC_CLKGATECPU      0x80
+#define BF_CLKCTRL_FRAC_CLKGATECPU(v)   (((v) << 7) & 0x80)
+#define BP_CLKCTRL_FRAC_CPU_STABLE      6
+#define BM_CLKCTRL_FRAC_CPU_STABLE      0x40
+#define BF_CLKCTRL_FRAC_CPU_STABLE(v)   (((v) << 6) & 0x40)
+#define BP_CLKCTRL_FRAC_CPUFRAC         0
+#define BM_CLKCTRL_FRAC_CPUFRAC         0x3f
+#define BF_CLKCTRL_FRAC_CPUFRAC(v)      (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_CLKCTRL_CLKSEQ
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_CLKCTRL_CLKSEQ                   (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x0))
+#define HW_CLKCTRL_CLKSEQ_SET               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x4))
+#define HW_CLKCTRL_CLKSEQ_CLR               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x8))
+#define HW_CLKCTRL_CLKSEQ_TOG               (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0xc))
+#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU        7
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU        0x80
+#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v)     (((v) << 7) & 0x80)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI        6
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI        0x40
+#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v)     (((v) << 6) & 0x40)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP        5
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP        0x20
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v)     (((v) << 5) & 0x20)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI       4
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI       0x10
+#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v)    (((v) << 4) & 0x10)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_IR         3
+#define BM_CLKCTRL_CLKSEQ_BYPASS_IR         0x8
+#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v)      (((v) << 3) & 0x8)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX        1
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX        0x2
+#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v)     (((v) << 1) & 0x2)
+#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF       0
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF       0x1
+#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_CLKCTRL_RESET
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_CLKCTRL_RESET            (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0))
+#define BP_CLKCTRL_RESET_CHIP       1
+#define BM_CLKCTRL_RESET_CHIP       0x2
+#define BF_CLKCTRL_RESET_CHIP(v)    (((v) << 1) & 0x2)
+#define BP_CLKCTRL_RESET_DIG        0
+#define BM_CLKCTRL_RESET_DIG        0x1
+#define BF_CLKCTRL_RESET_DIG(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_CLKCTRL_VERSION
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_CLKCTRL_VERSION          (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100))
+#define BP_CLKCTRL_VERSION_MAJOR    24
+#define BM_CLKCTRL_VERSION_MAJOR    0xff000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_CLKCTRL_VERSION_MINOR    16
+#define BM_CLKCTRL_VERSION_MINOR    0xff0000
+#define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_CLKCTRL_VERSION_STEP     0
+#define BM_CLKCTRL_VERSION_STEP     0xffff
+#define BF_CLKCTRL_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__CLKCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h
new file mode 100644
index 0000000000..f0b6273439
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h
@@ -0,0 +1,707 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__DCP__H__
+#define __HEADERGEN__STMP3700__DCP__H__
+
+#define REGS_DCP_BASE (0x80028000)
+
+#define REGS_DCP_VERSION "3.2.0"
+
+/**
+ * Register: HW_DCP_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DCP_CTRL                                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0))
+#define HW_DCP_CTRL_SET                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4))
+#define HW_DCP_CTRL_CLR                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8))
+#define HW_DCP_CTRL_TOG                             (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc))
+#define BP_DCP_CTRL_SFTRST                          31
+#define BM_DCP_CTRL_SFTRST                          0x80000000
+#define BF_DCP_CTRL_SFTRST(v)                       (((v) << 31) & 0x80000000)
+#define BP_DCP_CTRL_CLKGATE                         30
+#define BM_DCP_CTRL_CLKGATE                         0x40000000
+#define BF_DCP_CTRL_CLKGATE(v)                      (((v) << 30) & 0x40000000)
+#define BP_DCP_CTRL_PRESENT_CRYPTO                  29
+#define BM_DCP_CTRL_PRESENT_CRYPTO                  0x20000000
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Present         0x1
+#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent          0x0
+#define BF_DCP_CTRL_PRESENT_CRYPTO(v)               (((v) << 29) & 0x20000000)
+#define BF_DCP_CTRL_PRESENT_CRYPTO_V(v)             ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000)
+#define BP_DCP_CTRL_PRESENT_CSC                     28
+#define BM_DCP_CTRL_PRESENT_CSC                     0x10000000
+#define BV_DCP_CTRL_PRESENT_CSC__Present            0x1
+#define BV_DCP_CTRL_PRESENT_CSC__Absent             0x0
+#define BF_DCP_CTRL_PRESENT_CSC(v)                  (((v) << 28) & 0x10000000)
+#define BF_DCP_CTRL_PRESENT_CSC_V(v)                ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000)
+#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES          23
+#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES          0x800000
+#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v)       (((v) << 23) & 0x800000)
+#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING          22
+#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING          0x400000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v)       (((v) << 22) & 0x400000)
+#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        21
+#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING        0x200000
+#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v)     (((v) << 21) & 0x200000)
+#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE            8
+#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE            0x100
+#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v)         (((v) << 8) & 0x100)
+#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0
+#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE        0xff
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0   0x1
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1   0x2
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2   0x4
+#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3   0x8
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v)     (((v) << 0) & 0xff)
+#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v)   ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_DCP_STAT                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0))
+#define HW_DCP_STAT_SET                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4))
+#define HW_DCP_STAT_CLR                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8))
+#define HW_DCP_STAT_TOG                 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc))
+#define BP_DCP_STAT_OTP_KEY_READY       28
+#define BM_DCP_STAT_OTP_KEY_READY       0x10000000
+#define BF_DCP_STAT_OTP_KEY_READY(v)    (((v) << 28) & 0x10000000)
+#define BP_DCP_STAT_CUR_CHANNEL         24
+#define BM_DCP_STAT_CUR_CHANNEL         0xf000000
+#define BV_DCP_STAT_CUR_CHANNEL__None   0x0
+#define BV_DCP_STAT_CUR_CHANNEL__CH0    0x1
+#define BV_DCP_STAT_CUR_CHANNEL__CH1    0x2
+#define BV_DCP_STAT_CUR_CHANNEL__CH2    0x3
+#define BV_DCP_STAT_CUR_CHANNEL__CH3    0x4
+#define BV_DCP_STAT_CUR_CHANNEL__CSC    0x8
+#define BF_DCP_STAT_CUR_CHANNEL(v)      (((v) << 24) & 0xf000000)
+#define BF_DCP_STAT_CUR_CHANNEL_V(v)    ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000)
+#define BP_DCP_STAT_READY_CHANNELS      16
+#define BM_DCP_STAT_READY_CHANNELS      0xff0000
+#define BV_DCP_STAT_READY_CHANNELS__CH0 0x1
+#define BV_DCP_STAT_READY_CHANNELS__CH1 0x2
+#define BV_DCP_STAT_READY_CHANNELS__CH2 0x4
+#define BV_DCP_STAT_READY_CHANNELS__CH3 0x8
+#define BF_DCP_STAT_READY_CHANNELS(v)   (((v) << 16) & 0xff0000)
+#define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000)
+#define BP_DCP_STAT_CSCIRQ              8
+#define BM_DCP_STAT_CSCIRQ              0x100
+#define BF_DCP_STAT_CSCIRQ(v)           (((v) << 8) & 0x100)
+#define BP_DCP_STAT_IRQ                 0
+#define BM_DCP_STAT_IRQ                 0xf
+#define BF_DCP_STAT_IRQ(v)              (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DCP_CHANNELCTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_DCP_CHANNELCTRL                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0))
+#define HW_DCP_CHANNELCTRL_SET                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4))
+#define HW_DCP_CHANNELCTRL_CLR                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8))
+#define HW_DCP_CHANNELCTRL_TOG                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc))
+#define BP_DCP_CHANNELCTRL_CSC_PRIORITY                 17
+#define BM_DCP_CHANNELCTRL_CSC_PRIORITY                 0x60000
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH           0x3
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED            0x2
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW            0x1
+#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND     0x0
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v)              (((v) << 17) & 0x60000)
+#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v)            ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000)
+#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED               16
+#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED               0x10000
+#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v)            (((v) << 16) & 0x10000)
+#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        8
+#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL        0xff00
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0   0x1
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1   0x2
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2   0x4
+#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3   0x8
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v)     (((v) << 8) & 0xff00)
+#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v)   ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00)
+#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL               0
+#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL               0xff
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0          0x1
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1          0x2
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2          0x4
+#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3          0x8
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v)            (((v) << 0) & 0xff)
+#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v)          ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CAPABILITY0
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_DCP_CAPABILITY0                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30))
+#define BP_DCP_CAPABILITY0_NUM_CHANNELS     8
+#define BM_DCP_CAPABILITY0_NUM_CHANNELS     0xf00
+#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v)  (((v) << 8) & 0xf00)
+#define BP_DCP_CAPABILITY0_NUM_KEYS         0
+#define BM_DCP_CAPABILITY0_NUM_KEYS         0xff
+#define BF_DCP_CAPABILITY0_NUM_KEYS(v)      (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CAPABILITY1
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_DCP_CAPABILITY1                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40))
+#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS              16
+#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS              0xffff0000
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1        0x1
+#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32       0x2
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v)           (((v) << 16) & 0xffff0000)
+#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v)         ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000)
+#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0
+#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS            0xffff
+#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128    0x1
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v)         (((v) << 0) & 0xffff)
+#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v)       ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff)
+
+/**
+ * Register: HW_DCP_CONTEXT
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_DCP_CONTEXT          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50))
+#define BP_DCP_CONTEXT_ADDR     0
+#define BM_DCP_CONTEXT_ADDR     0xffffffff
+#define BF_DCP_CONTEXT_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_KEY
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DCP_KEY              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60))
+#define BP_DCP_KEY_INDEX        4
+#define BM_DCP_KEY_INDEX        0x30
+#define BF_DCP_KEY_INDEX(v)     (((v) << 4) & 0x30)
+#define BP_DCP_KEY_SUBWORD      0
+#define BM_DCP_KEY_SUBWORD      0x3
+#define BF_DCP_KEY_SUBWORD(v)   (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DCP_KEYDATA
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_DCP_KEYDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70))
+#define BP_DCP_KEYDATA_DATA     0
+#define BM_DCP_KEYDATA_DATA     0xffffffff
+#define BF_DCP_KEYDATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET0
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_DCP_PACKET0          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80))
+#define BP_DCP_PACKET0_ADDR     0
+#define BM_DCP_PACKET0_ADDR     0xffffffff
+#define BF_DCP_PACKET0_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET1
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DCP_PACKET1                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90))
+#define BP_DCP_PACKET1_TAG                      24
+#define BM_DCP_PACKET1_TAG                      0xff000000
+#define BF_DCP_PACKET1_TAG(v)                   (((v) << 24) & 0xff000000)
+#define BP_DCP_PACKET1_OUTPUT_WORDSWAP          23
+#define BM_DCP_PACKET1_OUTPUT_WORDSWAP          0x800000
+#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v)       (((v) << 23) & 0x800000)
+#define BP_DCP_PACKET1_OUTPUT_BYTESWAP          22
+#define BM_DCP_PACKET1_OUTPUT_BYTESWAP          0x400000
+#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v)       (((v) << 22) & 0x400000)
+#define BP_DCP_PACKET1_INPUT_WORDSWAP           21
+#define BM_DCP_PACKET1_INPUT_WORDSWAP           0x200000
+#define BF_DCP_PACKET1_INPUT_WORDSWAP(v)        (((v) << 21) & 0x200000)
+#define BP_DCP_PACKET1_INPUT_BYTESWAP           20
+#define BM_DCP_PACKET1_INPUT_BYTESWAP           0x100000
+#define BF_DCP_PACKET1_INPUT_BYTESWAP(v)        (((v) << 20) & 0x100000)
+#define BP_DCP_PACKET1_KEY_WORDSWAP             19
+#define BM_DCP_PACKET1_KEY_WORDSWAP             0x80000
+#define BF_DCP_PACKET1_KEY_WORDSWAP(v)          (((v) << 19) & 0x80000)
+#define BP_DCP_PACKET1_KEY_BYTESWAP             18
+#define BM_DCP_PACKET1_KEY_BYTESWAP             0x40000
+#define BF_DCP_PACKET1_KEY_BYTESWAP(v)          (((v) << 18) & 0x40000)
+#define BP_DCP_PACKET1_TEST_SEMA_IRQ            17
+#define BM_DCP_PACKET1_TEST_SEMA_IRQ            0x20000
+#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v)         (((v) << 17) & 0x20000)
+#define BP_DCP_PACKET1_CONSTANT_FILL            16
+#define BM_DCP_PACKET1_CONSTANT_FILL            0x10000
+#define BF_DCP_PACKET1_CONSTANT_FILL(v)         (((v) << 16) & 0x10000)
+#define BP_DCP_PACKET1_HASH_OUTPUT              15
+#define BM_DCP_PACKET1_HASH_OUTPUT              0x8000
+#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT       0x0
+#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT      0x1
+#define BF_DCP_PACKET1_HASH_OUTPUT(v)           (((v) << 15) & 0x8000)
+#define BF_DCP_PACKET1_HASH_OUTPUT_V(v)         ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000)
+#define BP_DCP_PACKET1_CHECK_HASH               14
+#define BM_DCP_PACKET1_CHECK_HASH               0x4000
+#define BF_DCP_PACKET1_CHECK_HASH(v)            (((v) << 14) & 0x4000)
+#define BP_DCP_PACKET1_HASH_TERM                13
+#define BM_DCP_PACKET1_HASH_TERM                0x2000
+#define BF_DCP_PACKET1_HASH_TERM(v)             (((v) << 13) & 0x2000)
+#define BP_DCP_PACKET1_HASH_INIT                12
+#define BM_DCP_PACKET1_HASH_INIT                0x1000
+#define BF_DCP_PACKET1_HASH_INIT(v)             (((v) << 12) & 0x1000)
+#define BP_DCP_PACKET1_PAYLOAD_KEY              11
+#define BM_DCP_PACKET1_PAYLOAD_KEY              0x800
+#define BF_DCP_PACKET1_PAYLOAD_KEY(v)           (((v) << 11) & 0x800)
+#define BP_DCP_PACKET1_OTP_KEY                  10
+#define BM_DCP_PACKET1_OTP_KEY                  0x400
+#define BF_DCP_PACKET1_OTP_KEY(v)               (((v) << 10) & 0x400)
+#define BP_DCP_PACKET1_CIPHER_INIT              9
+#define BM_DCP_PACKET1_CIPHER_INIT              0x200
+#define BF_DCP_PACKET1_CIPHER_INIT(v)           (((v) << 9) & 0x200)
+#define BP_DCP_PACKET1_CIPHER_ENCRYPT           8
+#define BM_DCP_PACKET1_CIPHER_ENCRYPT           0x100
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT  0x1
+#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT  0x0
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v)        (((v) << 8) & 0x100)
+#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v)      ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100)
+#define BP_DCP_PACKET1_ENABLE_BLIT              7
+#define BM_DCP_PACKET1_ENABLE_BLIT              0x80
+#define BF_DCP_PACKET1_ENABLE_BLIT(v)           (((v) << 7) & 0x80)
+#define BP_DCP_PACKET1_ENABLE_HASH              6
+#define BM_DCP_PACKET1_ENABLE_HASH              0x40
+#define BF_DCP_PACKET1_ENABLE_HASH(v)           (((v) << 6) & 0x40)
+#define BP_DCP_PACKET1_ENABLE_CIPHER            5
+#define BM_DCP_PACKET1_ENABLE_CIPHER            0x20
+#define BF_DCP_PACKET1_ENABLE_CIPHER(v)         (((v) << 5) & 0x20)
+#define BP_DCP_PACKET1_ENABLE_MEMCOPY           4
+#define BM_DCP_PACKET1_ENABLE_MEMCOPY           0x10
+#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v)        (((v) << 4) & 0x10)
+#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS         3
+#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS         0x8
+#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v)      (((v) << 3) & 0x8)
+#define BP_DCP_PACKET1_CHAIN                    2
+#define BM_DCP_PACKET1_CHAIN                    0x4
+#define BF_DCP_PACKET1_CHAIN(v)                 (((v) << 2) & 0x4)
+#define BP_DCP_PACKET1_DECR_SEMAPHORE           1
+#define BM_DCP_PACKET1_DECR_SEMAPHORE           0x2
+#define BF_DCP_PACKET1_DECR_SEMAPHORE(v)        (((v) << 1) & 0x2)
+#define BP_DCP_PACKET1_INTERRUPT                0
+#define BM_DCP_PACKET1_INTERRUPT                0x1
+#define BF_DCP_PACKET1_INTERRUPT(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_PACKET2
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DCP_PACKET2                          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0))
+#define BP_DCP_PACKET2_CIPHER_CFG               24
+#define BM_DCP_PACKET2_CIPHER_CFG               0xff000000
+#define BF_DCP_PACKET2_CIPHER_CFG(v)            (((v) << 24) & 0xff000000)
+#define BP_DCP_PACKET2_HASH_SELECT              16
+#define BM_DCP_PACKET2_HASH_SELECT              0xf0000
+#define BV_DCP_PACKET2_HASH_SELECT__SHA1        0x0
+#define BV_DCP_PACKET2_HASH_SELECT__CRC32       0x1
+#define BF_DCP_PACKET2_HASH_SELECT(v)           (((v) << 16) & 0xf0000)
+#define BF_DCP_PACKET2_HASH_SELECT_V(v)         ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000)
+#define BP_DCP_PACKET2_KEY_SELECT               8
+#define BM_DCP_PACKET2_KEY_SELECT               0xff00
+#define BF_DCP_PACKET2_KEY_SELECT(v)            (((v) << 8) & 0xff00)
+#define BP_DCP_PACKET2_CIPHER_MODE              4
+#define BM_DCP_PACKET2_CIPHER_MODE              0xf0
+#define BV_DCP_PACKET2_CIPHER_MODE__ECB         0x0
+#define BV_DCP_PACKET2_CIPHER_MODE__CCB         0x1
+#define BF_DCP_PACKET2_CIPHER_MODE(v)           (((v) << 4) & 0xf0)
+#define BF_DCP_PACKET2_CIPHER_MODE_V(v)         ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0)
+#define BP_DCP_PACKET2_CIPHER_SELECT            0
+#define BM_DCP_PACKET2_CIPHER_SELECT            0xf
+#define BV_DCP_PACKET2_CIPHER_SELECT__AES128    0x0
+#define BF_DCP_PACKET2_CIPHER_SELECT(v)         (((v) << 0) & 0xf)
+#define BF_DCP_PACKET2_CIPHER_SELECT_V(v)       ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_DCP_PACKET3
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_DCP_PACKET3          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0))
+#define BP_DCP_PACKET3_ADDR     0
+#define BM_DCP_PACKET3_ADDR     0xffffffff
+#define BF_DCP_PACKET3_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET4
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_DCP_PACKET4          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0))
+#define BP_DCP_PACKET4_ADDR     0
+#define BM_DCP_PACKET4_ADDR     0xffffffff
+#define BF_DCP_PACKET4_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET5
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_DCP_PACKET5          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0))
+#define BP_DCP_PACKET5_COUNT    0
+#define BM_DCP_PACKET5_COUNT    0xffffffff
+#define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_PACKET6
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_DCP_PACKET6          (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0))
+#define BP_DCP_PACKET6_ADDR     0
+#define BM_DCP_PACKET6_ADDR     0xffffffff
+#define BF_DCP_PACKET6_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CHnCMDPTR
+ * Address: 0x100+n*0x40
+ * SCT: no
+*/
+#define HW_DCP_CHnCMDPTR(n)         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40))
+#define BP_DCP_CHnCMDPTR_ADDR       0
+#define BM_DCP_CHnCMDPTR_ADDR       0xffffffff
+#define BF_DCP_CHnCMDPTR_ADDR(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CHnSEMA
+ * Address: 0x110+n*0x40
+ * SCT: no
+*/
+#define HW_DCP_CHnSEMA(n)           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40))
+#define BP_DCP_CHnSEMA_VALUE        16
+#define BM_DCP_CHnSEMA_VALUE        0xff0000
+#define BF_DCP_CHnSEMA_VALUE(v)     (((v) << 16) & 0xff0000)
+#define BP_DCP_CHnSEMA_INCREMENT    0
+#define BM_DCP_CHnSEMA_INCREMENT    0xff
+#define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CHnSTAT
+ * Address: 0x120+n*0x40
+ * SCT: yes
+*/
+#define HW_DCP_CHnSTAT(n)                           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0))
+#define HW_DCP_CHnSTAT_SET(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4))
+#define HW_DCP_CHnSTAT_CLR(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8))
+#define HW_DCP_CHnSTAT_TOG(n)                       (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc))
+#define BP_DCP_CHnSTAT_TAG                          24
+#define BM_DCP_CHnSTAT_TAG                          0xff000000
+#define BF_DCP_CHnSTAT_TAG(v)                       (((v) << 24) & 0xff000000)
+#define BP_DCP_CHnSTAT_ERROR_CODE                   16
+#define BM_DCP_CHnSTAT_ERROR_CODE                   0xff0000
+#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0  0x1
+#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN         0x2
+#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR    0x3
+#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR    0x4
+#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE     0x5
+#define BF_DCP_CHnSTAT_ERROR_CODE(v)                (((v) << 16) & 0xff0000)
+#define BF_DCP_CHnSTAT_ERROR_CODE_V(v)              ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000)
+#define BP_DCP_CHnSTAT_ERROR_DST                    5
+#define BM_DCP_CHnSTAT_ERROR_DST                    0x20
+#define BF_DCP_CHnSTAT_ERROR_DST(v)                 (((v) << 5) & 0x20)
+#define BP_DCP_CHnSTAT_ERROR_SRC                    4
+#define BM_DCP_CHnSTAT_ERROR_SRC                    0x10
+#define BF_DCP_CHnSTAT_ERROR_SRC(v)                 (((v) << 4) & 0x10)
+#define BP_DCP_CHnSTAT_ERROR_PACKET                 3
+#define BM_DCP_CHnSTAT_ERROR_PACKET                 0x8
+#define BF_DCP_CHnSTAT_ERROR_PACKET(v)              (((v) << 3) & 0x8)
+#define BP_DCP_CHnSTAT_ERROR_SETUP                  2
+#define BM_DCP_CHnSTAT_ERROR_SETUP                  0x4
+#define BF_DCP_CHnSTAT_ERROR_SETUP(v)               (((v) << 2) & 0x4)
+#define BP_DCP_CHnSTAT_HASH_MISMATCH                1
+#define BM_DCP_CHnSTAT_HASH_MISMATCH                0x2
+#define BF_DCP_CHnSTAT_HASH_MISMATCH(v)             (((v) << 1) & 0x2)
+
+/**
+ * Register: HW_DCP_CHnOPTS
+ * Address: 0x130+n*0x40
+ * SCT: yes
+*/
+#define HW_DCP_CHnOPTS(n)                   (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0))
+#define HW_DCP_CHnOPTS_SET(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4))
+#define HW_DCP_CHnOPTS_CLR(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8))
+#define HW_DCP_CHnOPTS_TOG(n)               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc))
+#define BP_DCP_CHnOPTS_RECOVERY_TIMER       0
+#define BM_DCP_CHnOPTS_RECOVERY_TIMER       0xffff
+#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DCP_CSCCTRL0
+ * Address: 0x300
+ * SCT: yes
+*/
+#define HW_DCP_CSCCTRL0                         (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0))
+#define HW_DCP_CSCCTRL0_SET                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4))
+#define HW_DCP_CSCCTRL0_CLR                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8))
+#define HW_DCP_CSCCTRL0_TOG                     (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc))
+#define BP_DCP_CSCCTRL0_UPSAMPLE                14
+#define BM_DCP_CSCCTRL0_UPSAMPLE                0x4000
+#define BF_DCP_CSCCTRL0_UPSAMPLE(v)             (((v) << 14) & 0x4000)
+#define BP_DCP_CSCCTRL0_SCALE                   13
+#define BM_DCP_CSCCTRL0_SCALE                   0x2000
+#define BF_DCP_CSCCTRL0_SCALE(v)                (((v) << 13) & 0x2000)
+#define BP_DCP_CSCCTRL0_ROTATE                  12
+#define BM_DCP_CSCCTRL0_ROTATE                  0x1000
+#define BF_DCP_CSCCTRL0_ROTATE(v)               (((v) << 12) & 0x1000)
+#define BP_DCP_CSCCTRL0_SUBSAMPLE               11
+#define BM_DCP_CSCCTRL0_SUBSAMPLE               0x800
+#define BF_DCP_CSCCTRL0_SUBSAMPLE(v)            (((v) << 11) & 0x800)
+#define BP_DCP_CSCCTRL0_DELTA                   10
+#define BM_DCP_CSCCTRL0_DELTA                   0x400
+#define BF_DCP_CSCCTRL0_DELTA(v)                (((v) << 10) & 0x400)
+#define BP_DCP_CSCCTRL0_RGB_FORMAT              8
+#define BM_DCP_CSCCTRL0_RGB_FORMAT              0x300
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565   0x0
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24       0x2
+#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I     0x3
+#define BF_DCP_CSCCTRL0_RGB_FORMAT(v)           (((v) << 8) & 0x300)
+#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300)
+#define BP_DCP_CSCCTRL0_YUV_FORMAT              4
+#define BM_DCP_CSCCTRL0_YUV_FORMAT              0xf0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420      0x0
+#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422      0x2
+#define BF_DCP_CSCCTRL0_YUV_FORMAT(v)           (((v) << 4) & 0xf0)
+#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v)         ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0)
+#define BP_DCP_CSCCTRL0_ENABLE                  0
+#define BM_DCP_CSCCTRL0_ENABLE                  0x1
+#define BF_DCP_CSCCTRL0_ENABLE(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_CSCSTAT
+ * Address: 0x310
+ * SCT: yes
+*/
+#define HW_DCP_CSCSTAT                                  (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0))
+#define HW_DCP_CSCSTAT_SET                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4))
+#define HW_DCP_CSCSTAT_CLR                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8))
+#define HW_DCP_CSCSTAT_TOG                              (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc))
+#define BP_DCP_CSCSTAT_ERROR_CODE                       16
+#define BM_DCP_CSCSTAT_ERROR_CODE                       0xff0000
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1
+#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3
+#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4
+#define BF_DCP_CSCSTAT_ERROR_CODE(v)                    (((v) << 16) & 0xff0000)
+#define BF_DCP_CSCSTAT_ERROR_CODE_V(v)                  ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000)
+#define BP_DCP_CSCSTAT_ERROR_DST                        5
+#define BM_DCP_CSCSTAT_ERROR_DST                        0x20
+#define BF_DCP_CSCSTAT_ERROR_DST(v)                     (((v) << 5) & 0x20)
+#define BP_DCP_CSCSTAT_ERROR_SRC                        4
+#define BM_DCP_CSCSTAT_ERROR_SRC                        0x10
+#define BF_DCP_CSCSTAT_ERROR_SRC(v)                     (((v) << 4) & 0x10)
+#define BP_DCP_CSCSTAT_ERROR_SETUP                      2
+#define BM_DCP_CSCSTAT_ERROR_SETUP                      0x4
+#define BF_DCP_CSCSTAT_ERROR_SETUP(v)                   (((v) << 2) & 0x4)
+#define BP_DCP_CSCSTAT_COMPLETE                         0
+#define BM_DCP_CSCSTAT_COMPLETE                         0x1
+#define BF_DCP_CSCSTAT_COMPLETE(v)                      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DCP_CSCOUTBUFPARAM
+ * Address: 0x320
+ * SCT: no
+*/
+#define HW_DCP_CSCOUTBUFPARAM               (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320))
+#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE    12
+#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE    0xfff000
+#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000)
+#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE     0
+#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE     0xfff
+#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_CSCINBUFPARAM
+ * Address: 0x330
+ * SCT: no
+*/
+#define HW_DCP_CSCINBUFPARAM                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330))
+#define BP_DCP_CSCINBUFPARAM_LINE_SIZE      0
+#define BM_DCP_CSCINBUFPARAM_LINE_SIZE      0xfff
+#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_CSCRGB
+ * Address: 0x340
+ * SCT: no
+*/
+#define HW_DCP_CSCRGB           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340))
+#define BP_DCP_CSCRGB_ADDR      0
+#define BM_DCP_CSCRGB_ADDR      0xffffffff
+#define BF_DCP_CSCRGB_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCLUMA
+ * Address: 0x350
+ * SCT: no
+*/
+#define HW_DCP_CSCLUMA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350))
+#define BP_DCP_CSCLUMA_ADDR     0
+#define BM_DCP_CSCLUMA_ADDR     0xffffffff
+#define BF_DCP_CSCLUMA_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCCHROMAU
+ * Address: 0x360
+ * SCT: no
+*/
+#define HW_DCP_CSCCHROMAU           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360))
+#define BP_DCP_CSCCHROMAU_ADDR      0
+#define BM_DCP_CSCCHROMAU_ADDR      0xffffffff
+#define BF_DCP_CSCCHROMAU_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCCHROMAV
+ * Address: 0x370
+ * SCT: no
+*/
+#define HW_DCP_CSCCHROMAV           (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370))
+#define BP_DCP_CSCCHROMAV_ADDR      0
+#define BM_DCP_CSCCHROMAV_ADDR      0xffffffff
+#define BF_DCP_CSCCHROMAV_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_CSCCOEFF0
+ * Address: 0x380
+ * SCT: no
+*/
+#define HW_DCP_CSCCOEFF0                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380))
+#define BP_DCP_CSCCOEFF0_C0             16
+#define BM_DCP_CSCCOEFF0_C0             0x3ff0000
+#define BF_DCP_CSCCOEFF0_C0(v)          (((v) << 16) & 0x3ff0000)
+#define BP_DCP_CSCCOEFF0_UV_OFFSET      8
+#define BM_DCP_CSCCOEFF0_UV_OFFSET      0xff00
+#define BF_DCP_CSCCOEFF0_UV_OFFSET(v)   (((v) << 8) & 0xff00)
+#define BP_DCP_CSCCOEFF0_Y_OFFSET       0
+#define BM_DCP_CSCCOEFF0_Y_OFFSET       0xff
+#define BF_DCP_CSCCOEFF0_Y_OFFSET(v)    (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_CSCCOEFF1
+ * Address: 0x390
+ * SCT: no
+*/
+#define HW_DCP_CSCCOEFF1        (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390))
+#define BP_DCP_CSCCOEFF1_C1     16
+#define BM_DCP_CSCCOEFF1_C1     0x3ff0000
+#define BF_DCP_CSCCOEFF1_C1(v)  (((v) << 16) & 0x3ff0000)
+#define BP_DCP_CSCCOEFF1_C4     0
+#define BM_DCP_CSCCOEFF1_C4     0x3ff
+#define BF_DCP_CSCCOEFF1_C4(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_DCP_CSCCOEFF2
+ * Address: 0x3a0
+ * SCT: no
+*/
+#define HW_DCP_CSCCOEFF2        (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0))
+#define BP_DCP_CSCCOEFF2_C2     16
+#define BM_DCP_CSCCOEFF2_C2     0x3ff0000
+#define BF_DCP_CSCCOEFF2_C2(v)  (((v) << 16) & 0x3ff0000)
+#define BP_DCP_CSCCOEFF2_C3     0
+#define BM_DCP_CSCCOEFF2_C3     0x3ff
+#define BF_DCP_CSCCOEFF2_C3(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_DCP_CSCXSCALE
+ * Address: 0x3e0
+ * SCT: no
+*/
+#define HW_DCP_CSCXSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0))
+#define BP_DCP_CSCXSCALE_INT        24
+#define BM_DCP_CSCXSCALE_INT        0x3000000
+#define BF_DCP_CSCXSCALE_INT(v)     (((v) << 24) & 0x3000000)
+#define BP_DCP_CSCXSCALE_FRAC       12
+#define BM_DCP_CSCXSCALE_FRAC       0xfff000
+#define BF_DCP_CSCXSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
+#define BP_DCP_CSCXSCALE_WIDTH      0
+#define BM_DCP_CSCXSCALE_WIDTH      0xfff
+#define BF_DCP_CSCXSCALE_WIDTH(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_CSCYSCALE
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_DCP_CSCYSCALE            (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0))
+#define BP_DCP_CSCYSCALE_INT        24
+#define BM_DCP_CSCYSCALE_INT        0x3000000
+#define BF_DCP_CSCYSCALE_INT(v)     (((v) << 24) & 0x3000000)
+#define BP_DCP_CSCYSCALE_FRAC       12
+#define BM_DCP_CSCYSCALE_FRAC       0xfff000
+#define BF_DCP_CSCYSCALE_FRAC(v)    (((v) << 12) & 0xfff000)
+#define BP_DCP_CSCYSCALE_HEIGHT     0
+#define BM_DCP_CSCYSCALE_HEIGHT     0xfff
+#define BF_DCP_CSCYSCALE_HEIGHT(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DCP_DBGSELECT
+ * Address: 0x400
+ * SCT: no
+*/
+#define HW_DCP_DBGSELECT                (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400))
+#define BP_DCP_DBGSELECT_INDEX          0
+#define BM_DCP_DBGSELECT_INDEX          0xff
+#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12
+#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13
+#define BF_DCP_DBGSELECT_INDEX(v)       (((v) << 0) & 0xff)
+#define BF_DCP_DBGSELECT_INDEX_V(v)     ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff)
+
+/**
+ * Register: HW_DCP_DBGDATA
+ * Address: 0x410
+ * SCT: no
+*/
+#define HW_DCP_DBGDATA          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410))
+#define BP_DCP_DBGDATA_DATA     0
+#define BM_DCP_DBGDATA_DATA     0xffffffff
+#define BF_DCP_DBGDATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DCP_VERSION
+ * Address: 0x420
+ * SCT: no
+*/
+#define HW_DCP_VERSION          (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420))
+#define BP_DCP_VERSION_MAJOR    24
+#define BM_DCP_VERSION_MAJOR    0xff000000
+#define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_DCP_VERSION_MINOR    16
+#define BM_DCP_VERSION_MINOR    0xff0000
+#define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_DCP_VERSION_STEP     0
+#define BM_DCP_VERSION_STEP     0xffff
+#define BF_DCP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__DCP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h
new file mode 100644
index 0000000000..69d4e7128f
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h
@@ -0,0 +1,759 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__DIGCTL__H__
+#define __HEADERGEN__STMP3700__DIGCTL__H__
+
+#define REGS_DIGCTL_BASE (0x8001c000)
+
+#define REGS_DIGCTL_VERSION "3.2.0"
+
+/**
+ * Register: HW_DIGCTL_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DIGCTL_CTRL                                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0))
+#define HW_DIGCTL_CTRL_SET                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4))
+#define HW_DIGCTL_CTRL_CLR                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8))
+#define HW_DIGCTL_CTRL_TOG                                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc))
+#define BP_DIGCTL_CTRL_TRAP_IRQ                             29
+#define BM_DIGCTL_CTRL_TRAP_IRQ                             0x20000000
+#define BF_DIGCTL_CTRL_TRAP_IRQ(v)                          (((v) << 29) & 0x20000000)
+#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN                       23
+#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN                       0x800000
+#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v)                    (((v) << 23) & 0x800000)
+#define BP_DIGCTL_CTRL_DCP_BIST_START                       22
+#define BM_DIGCTL_CTRL_DCP_BIST_START                       0x400000
+#define BF_DIGCTL_CTRL_DCP_BIST_START(v)                    (((v) << 22) & 0x400000)
+#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN                       21
+#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN                       0x200000
+#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v)                    (((v) << 21) & 0x200000)
+#define BP_DIGCTL_CTRL_USB_TESTMODE                         20
+#define BM_DIGCTL_CTRL_USB_TESTMODE                         0x100000
+#define BF_DIGCTL_CTRL_USB_TESTMODE(v)                      (((v) << 20) & 0x100000)
+#define BP_DIGCTL_CTRL_ANALOG_TESTMODE                      19
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE                      0x80000
+#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v)                   (((v) << 19) & 0x80000)
+#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE                     18
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE                     0x40000
+#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v)                  (((v) << 18) & 0x40000)
+#define BP_DIGCTL_CTRL_ARM_BIST_START                       17
+#define BM_DIGCTL_CTRL_ARM_BIST_START                       0x20000
+#define BF_DIGCTL_CTRL_ARM_BIST_START(v)                    (((v) << 17) & 0x20000)
+#define BP_DIGCTL_CTRL_UART_LOOPBACK                        16
+#define BM_DIGCTL_CTRL_UART_LOOPBACK                        0x10000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_UART_LOOPBACK(v)                     (((v) << 16) & 0x10000)
+#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000)
+#define BP_DIGCTL_CTRL_SAIF_LOOPBACK                        15
+#define BM_DIGCTL_CTRL_SAIF_LOOPBACK                        0x8000
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL                0x0
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT                0x1
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v)                     (((v) << 15) & 0x8000)
+#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v)                   ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000)
+#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      13
+#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL                      0x6000
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT         0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT          0x1
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN           0x3
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v)                   (((v) << 13) & 0x6000)
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000)
+#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL                      12
+#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL                      0x1000
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST           0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST           0x1
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v)                   (((v) << 12) & 0x1000)
+#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v)                 ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000)
+#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  11
+#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL                  0x800
+#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v)               (((v) << 11) & 0x800)
+#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG                      6
+#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG                      0x40
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG            0x0
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG         0x1
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v)                   (((v) << 6) & 0x40)
+#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v)                 ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40)
+#define BP_DIGCTL_CTRL_TRAP_IN_RANGE                        5
+#define BM_DIGCTL_CTRL_TRAP_IN_RANGE                        0x20
+#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v)                     (((v) << 5) & 0x20)
+#define BP_DIGCTL_CTRL_TRAP_ENABLE                          4
+#define BM_DIGCTL_CTRL_TRAP_ENABLE                          0x10
+#define BF_DIGCTL_CTRL_TRAP_ENABLE(v)                       (((v) << 4) & 0x10)
+#define BP_DIGCTL_CTRL_DEBUG_DISABLE                        3
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE                        0x8
+#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v)                     (((v) << 3) & 0x8)
+#define BP_DIGCTL_CTRL_USB_CLKGATE                          2
+#define BM_DIGCTL_CTRL_USB_CLKGATE                          0x4
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN                     0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS                 0x1
+#define BF_DIGCTL_CTRL_USB_CLKGATE(v)                       (((v) << 2) & 0x4)
+#define BF_DIGCTL_CTRL_USB_CLKGATE_V(v)                     ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4)
+#define BP_DIGCTL_CTRL_JTAG_SHIELD                          1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD                          0x2
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL                  0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP              0x1
+#define BF_DIGCTL_CTRL_JTAG_SHIELD(v)                       (((v) << 1) & 0x2)
+#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v)                     ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2)
+#define BP_DIGCTL_CTRL_LATCH_ENTROPY                        0
+#define BM_DIGCTL_CTRL_LATCH_ENTROPY                        0x1
+#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v)                     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_STATUS
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DIGCTL_STATUS                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10))
+#define BP_DIGCTL_STATUS_USB_HS_PRESENT         31
+#define BM_DIGCTL_STATUS_USB_HS_PRESENT         0x80000000
+#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v)      (((v) << 31) & 0x80000000)
+#define BP_DIGCTL_STATUS_USB_OTG_PRESENT        30
+#define BM_DIGCTL_STATUS_USB_OTG_PRESENT        0x40000000
+#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v)     (((v) << 30) & 0x40000000)
+#define BP_DIGCTL_STATUS_USB_HOST_PRESENT       29
+#define BM_DIGCTL_STATUS_USB_HOST_PRESENT       0x20000000
+#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v)    (((v) << 29) & 0x20000000)
+#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT     28
+#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT     0x10000000
+#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v)  (((v) << 28) & 0x10000000)
+#define BP_DIGCTL_STATUS_DCP_BIST_FAIL          10
+#define BM_DIGCTL_STATUS_DCP_BIST_FAIL          0x400
+#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v)       (((v) << 10) & 0x400)
+#define BP_DIGCTL_STATUS_DCP_BIST_PASS          9
+#define BM_DIGCTL_STATUS_DCP_BIST_PASS          0x200
+#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v)       (((v) << 9) & 0x200)
+#define BP_DIGCTL_STATUS_DCP_BIST_DONE          8
+#define BM_DIGCTL_STATUS_DCP_BIST_DONE          0x100
+#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v)       (((v) << 8) & 0x100)
+#define BP_DIGCTL_STATUS_JTAG_IN_USE            4
+#define BM_DIGCTL_STATUS_JTAG_IN_USE            0x10
+#define BF_DIGCTL_STATUS_JTAG_IN_USE(v)         (((v) << 4) & 0x10)
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE           1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE           0xe
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v)        (((v) << 1) & 0xe)
+#define BP_DIGCTL_STATUS_WRITTEN                0
+#define BM_DIGCTL_STATUS_WRITTEN                0x1
+#define BF_DIGCTL_STATUS_WRITTEN(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_HCLKCOUNT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DIGCTL_HCLKCOUNT             (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20))
+#define BP_DIGCTL_HCLKCOUNT_COUNT       0
+#define BM_DIGCTL_HCLKCOUNT_COUNT       0xffffffff
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_RAMCTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMCTRL                   (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0))
+#define HW_DIGCTL_RAMCTRL_SET               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4))
+#define HW_DIGCTL_RAMCTRL_CLR               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8))
+#define HW_DIGCTL_RAMCTRL_TOG               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc))
+#define BP_DIGCTL_RAMCTRL_SPEED_SELECT      8
+#define BM_DIGCTL_RAMCTRL_SPEED_SELECT      0xf00
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v)   (((v) << 8) & 0xf00)
+#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0
+#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN     0x1
+#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_RAMREPAIR
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_DIGCTL_RAMREPAIR         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0))
+#define HW_DIGCTL_RAMREPAIR_SET     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4))
+#define HW_DIGCTL_RAMREPAIR_CLR     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8))
+#define HW_DIGCTL_RAMREPAIR_TOG     (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc))
+#define BP_DIGCTL_RAMREPAIR_ADDR    0
+#define BM_DIGCTL_RAMREPAIR_ADDR    0xffff
+#define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_ROMCTRL
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_DIGCTL_ROMCTRL               (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0))
+#define HW_DIGCTL_ROMCTRL_SET           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4))
+#define HW_DIGCTL_ROMCTRL_CLR           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8))
+#define HW_DIGCTL_ROMCTRL_TOG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc))
+#define BP_DIGCTL_ROMCTRL_RD_MARGIN     0
+#define BM_DIGCTL_ROMCTRL_RD_MARGIN     0xf
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v)  (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_WRITEONCE
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DIGCTL_WRITEONCE         (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60))
+#define BP_DIGCTL_WRITEONCE_BITS    0
+#define BM_DIGCTL_WRITEONCE_BITS    0xffffffff
+#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ENTROPY
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DIGCTL_ENTROPY           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90))
+#define BP_DIGCTL_ENTROPY_VALUE     0
+#define BM_DIGCTL_ENTROPY_VALUE     0xffffffff
+#define BF_DIGCTL_ENTROPY_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ENTROPY_LATCHED
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DIGCTL_ENTROPY_LATCHED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0))
+#define BP_DIGCTL_ENTROPY_LATCHED_VALUE     0
+#define BM_DIGCTL_ENTROPY_LATCHED_VALUE     0xffffffff
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SJTAGDBG
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_DIGCTL_SJTAGDBG                      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0))
+#define HW_DIGCTL_SJTAGDBG_SET                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4))
+#define HW_DIGCTL_SJTAGDBG_CLR                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8))
+#define HW_DIGCTL_SJTAGDBG_TOG                  (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc))
+#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE          16
+#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE          0x7ff0000
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v)       (((v) << 16) & 0x7ff0000)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO            10
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO            0x400
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v)         (((v) << 10) & 0x400)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI            9
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI            0x200
+#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v)         (((v) << 9) & 0x200)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE           8
+#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE           0x100
+#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v)        (((v) << 8) & 0x100)
+#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       4
+#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE       0xf0
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v)    (((v) << 4) & 0xf0)
+#define BP_DIGCTL_SJTAGDBG_ACTIVE               3
+#define BM_DIGCTL_SJTAGDBG_ACTIVE               0x8
+#define BF_DIGCTL_SJTAGDBG_ACTIVE(v)            (((v) << 3) & 0x8)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      2
+#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE      0x4
+#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v)   (((v) << 2) & 0x4)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     1
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA     0x2
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v)  (((v) << 1) & 0x2)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE       0x1
+#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_MICROSECONDS
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_DIGCTL_MICROSECONDS          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0))
+#define HW_DIGCTL_MICROSECONDS_SET      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4))
+#define HW_DIGCTL_MICROSECONDS_CLR      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8))
+#define HW_DIGCTL_MICROSECONDS_TOG      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc))
+#define BP_DIGCTL_MICROSECONDS_VALUE    0
+#define BM_DIGCTL_MICROSECONDS_VALUE    0xffffffff
+#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBGRD
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBGRD                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0))
+#define BP_DIGCTL_DBGRD_COMPLEMENT      0
+#define BM_DIGCTL_DBGRD_COMPLEMENT      0xffffffff
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DBG
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_DIGCTL_DBG           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0))
+#define BP_DIGCTL_DBG_VALUE     0
+#define BM_DIGCTL_DBG_VALUE     0xffffffff
+#define BF_DIGCTL_DBG_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_BIST_CSR
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_DIGCTL_OCRAM_BIST_CSR                        (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0))
+#define HW_DIGCTL_OCRAM_BIST_CSR_SET                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4))
+#define HW_DIGCTL_OCRAM_BIST_CSR_CLR                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8))
+#define HW_DIGCTL_OCRAM_BIST_CSR_TOG                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc))
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       9
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE       0x200
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v)    (((v) << 9) & 0x200)
+#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             8
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN             0x100
+#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v)          (((v) << 8) & 0x100)
+#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL                   3
+#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL                   0x8
+#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v)                (((v) << 3) & 0x8)
+#define BP_DIGCTL_OCRAM_BIST_CSR_PASS                   2
+#define BM_DIGCTL_OCRAM_BIST_CSR_PASS                   0x4
+#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v)                (((v) << 2) & 0x4)
+#define BP_DIGCTL_OCRAM_BIST_CSR_DONE                   1
+#define BM_DIGCTL_OCRAM_BIST_CSR_DONE                   0x2
+#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v)                (((v) << 1) & 0x2)
+#define BP_DIGCTL_OCRAM_BIST_CSR_START                  0
+#define BM_DIGCTL_OCRAM_BIST_CSR_START                  0x1
+#define BF_DIGCTL_OCRAM_BIST_CSR_START(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS0
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS0                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110))
+#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00      0
+#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS1
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS1                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120))
+#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01      0
+#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS2
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS2                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130))
+#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10      0
+#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS3
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS3                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140))
+#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11      0
+#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS4
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS4                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150))
+#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20      0
+#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS5
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS5                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160))
+#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21      0
+#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS6
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS6                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170))
+#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30      0
+#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS7
+ * Address: 0x180
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS7                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180))
+#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31      0
+#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31      0xffffffff
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS8
+ * Address: 0x190
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS8                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190))
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01      16
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01      0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v)   (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00      0
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00      0xffff
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS9
+ * Address: 0x1a0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS9                 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0))
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11      16
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11      0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v)   (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10      0
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10      0xffff
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS10
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS10                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0))
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21     16
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21     0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v)  (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20     0
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20     0xffff
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS11
+ * Address: 0x1c0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS11                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0))
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31     16
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31     0xffff0000
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v)  (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30     0
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30     0xffff
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS12
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS12                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0))
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11    24
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11    0x1f000000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10    16
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10    0x1f0000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01    8
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01    0x1f00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00    0x1f
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DIGCTL_OCRAM_STATUS13
+ * Address: 0x1e0
+ * SCT: no
+*/
+#define HW_DIGCTL_OCRAM_STATUS13                (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0))
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31    24
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31    0x1f000000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30    16
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30    0x1f0000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21    8
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21    0x1f00
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20    0x1f
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH0
+ * Address: 0x290
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH0          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290))
+#define BP_DIGCTL_SCRATCH0_PTR      0
+#define BM_DIGCTL_SCRATCH0_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH0_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SCRATCH1
+ * Address: 0x2a0
+ * SCT: no
+*/
+#define HW_DIGCTL_SCRATCH1          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0))
+#define BP_DIGCTL_SCRATCH1_PTR      0
+#define BM_DIGCTL_SCRATCH1_PTR      0xffffffff
+#define BF_DIGCTL_SCRATCH1_PTR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_ARMCACHE
+ * Address: 0x2b0
+ * SCT: no
+*/
+#define HW_DIGCTL_ARMCACHE              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0))
+#define BP_DIGCTL_ARMCACHE_CACHE_SS     8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS     0x300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v)  (((v) << 8) & 0x300)
+#define BP_DIGCTL_ARMCACHE_DTAG_SS      4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS      0x30
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v)   (((v) << 4) & 0x30)
+#define BP_DIGCTL_ARMCACHE_ITAG_SS      0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS      0x3
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v)   (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW
+ * Address: 0x2c0
+ * SCT: no
+*/
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0))
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR      0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH
+ * Address: 0x2d0
+ * SCT: no
+*/
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0))
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR     0xffffffff
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_SGTL
+ * Address: 0x300
+ * SCT: no
+*/
+#define HW_DIGCTL_SGTL              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300))
+#define BP_DIGCTL_SGTL_COPYRIGHT    0
+#define BM_DIGCTL_SGTL_COPYRIGHT    0xffffffff
+#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_CHIPID
+ * Address: 0x310
+ * SCT: no
+*/
+#define HW_DIGCTL_CHIPID                    (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310))
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE       16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE       0xffff0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v)    (((v) << 16) & 0xffff0000)
+#define BP_DIGCTL_CHIPID_REVISION           0
+#define BM_DIGCTL_CHIPID_REVISION           0xff
+#define BF_DIGCTL_CHIPID_REVISION(v)        (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DIGCTL_AHB_STATS_SELECT
+ * Address: 0x330
+ * SCT: no
+*/
+#define HW_DIGCTL_AHB_STATS_SELECT                          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330))
+#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         24
+#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT         0xf000000
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX   0x2
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB    0x4
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v)      (((v) << 24) & 0xf000000)
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000)
+#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         16
+#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT         0xf0000
+#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v)      (((v) << 16) & 0xf0000)
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000)
+#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         8
+#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT         0xf00
+#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I  0x1
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v)      (((v) << 8) & 0xf00)
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00)
+#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0
+#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT         0xf
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8   0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v)      (((v) << 0) & 0xf)
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v)    ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES
+ * Address: 0x340
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340))
+#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_DATA_STALLED
+ * Address: 0x350
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350))
+#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES
+ * Address: 0x360
+ * SCT: no
+*/
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360))
+#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES
+ * Address: 0x370
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370))
+#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_DATA_STALLED
+ * Address: 0x380
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380))
+#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES
+ * Address: 0x390
+ * SCT: no
+*/
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390))
+#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES
+ * Address: 0x3a0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0))
+#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_DATA_STALLED
+ * Address: 0x3b0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0))
+#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES
+ * Address: 0x3c0
+ * SCT: no
+*/
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0))
+#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES
+ * Address: 0x3d0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES          (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0))
+#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0
+#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT    0xffffffff
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_DATA_STALLED
+ * Address: 0x3e0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_DATA_STALLED           (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0))
+#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0
+#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT     0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES
+ * Address: 0x3f0
+ * SCT: no
+*/
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES            (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0))
+#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0
+#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT      0xffffffff
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DIGCTL_MPTEn_LOC
+ * Address: 0x400+n*0x10
+ * SCT: no
+*/
+#define HW_DIGCTL_MPTEn_LOC(n)      (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10))
+#define BP_DIGCTL_MPTEn_LOC_LOC     0
+#define BM_DIGCTL_MPTEn_LOC_LOC     0xfff
+#define BF_DIGCTL_MPTEn_LOC_LOC(v)  (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DIGCTL_EMICLK_DELAY
+ * Address: 0x480
+ * SCT: no
+*/
+#define HW_DIGCTL_EMICLK_DELAY              (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x480))
+#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS     0
+#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS     0x1f
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v)  (((v) << 0) & 0x1f)
+
+#endif /* __HEADERGEN__STMP3700__DIGCTL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h
new file mode 100644
index 0000000000..7ec44c41ee
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h
@@ -0,0 +1,671 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__DRAM__H__
+#define __HEADERGEN__STMP3700__DRAM__H__
+
+#define REGS_DRAM_BASE (0x800e0000)
+
+#define REGS_DRAM_VERSION "3.2.0"
+
+/**
+ * Register: HW_DRAM_CTL00
+ * Address: 0
+ * SCT: no
+*/
+#define HW_DRAM_CTL00                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0))
+#define BP_DRAM_CTL00_AHB0_W_PRIORITY       24
+#define BM_DRAM_CTL00_AHB0_W_PRIORITY       0x1000000
+#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL00_AHB0_R_PRIORITY       16
+#define BM_DRAM_CTL00_AHB0_R_PRIORITY       0x10000
+#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v)    (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG    8
+#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG    0x100
+#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100)
+#define BP_DRAM_CTL00_ADDR_CMP_EN           0
+#define BM_DRAM_CTL00_ADDR_CMP_EN           0x1
+#define BF_DRAM_CTL00_ADDR_CMP_EN(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL01
+ * Address: 0x4
+ * SCT: no
+*/
+#define HW_DRAM_CTL01                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4))
+#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG    24
+#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG    0x1000000
+#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL01_AHB1_W_PRIORITY       16
+#define BM_DRAM_CTL01_AHB1_W_PRIORITY       0x10000
+#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v)    (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL01_AHB1_R_PRIORITY       8
+#define BM_DRAM_CTL01_AHB1_R_PRIORITY       0x100
+#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v)    (((v) << 8) & 0x100)
+#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0
+#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG    0x1
+#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL02
+ * Address: 0x8
+ * SCT: no
+*/
+#define HW_DRAM_CTL02                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8))
+#define BP_DRAM_CTL02_AHB3_R_PRIORITY       24
+#define BM_DRAM_CTL02_AHB3_R_PRIORITY       0x1000000
+#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG    16
+#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG    0x10000
+#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL02_AHB2_W_PRIORITY       8
+#define BM_DRAM_CTL02_AHB2_W_PRIORITY       0x100
+#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v)    (((v) << 8) & 0x100)
+#define BP_DRAM_CTL02_AHB2_R_PRIORITY       0
+#define BM_DRAM_CTL02_AHB2_R_PRIORITY       0x1
+#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL03
+ * Address: 0xc
+ * SCT: no
+*/
+#define HW_DRAM_CTL03                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc))
+#define BP_DRAM_CTL03_AUTO_REFRESH_MODE     24
+#define BM_DRAM_CTL03_AUTO_REFRESH_MODE     0x1000000
+#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v)  (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL03_AREFRESH              16
+#define BM_DRAM_CTL03_AREFRESH              0x10000
+#define BF_DRAM_CTL03_AREFRESH(v)           (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL03_AP                    8
+#define BM_DRAM_CTL03_AP                    0x100
+#define BF_DRAM_CTL03_AP(v)                 (((v) << 8) & 0x100)
+#define BP_DRAM_CTL03_AHB3_W_PRIORITY       0
+#define BM_DRAM_CTL03_AHB3_W_PRIORITY       0x1
+#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL04
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DRAM_CTL04                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10))
+#define BP_DRAM_CTL04_DLL_BYPASS_MODE       24
+#define BM_DRAM_CTL04_DLL_BYPASS_MODE       0x1000000
+#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL04_DLLLOCKREG            16
+#define BM_DRAM_CTL04_DLLLOCKREG            0x10000
+#define BF_DRAM_CTL04_DLLLOCKREG(v)         (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL04_CONCURRENTAP          8
+#define BM_DRAM_CTL04_CONCURRENTAP          0x100
+#define BF_DRAM_CTL04_CONCURRENTAP(v)       (((v) << 8) & 0x100)
+#define BP_DRAM_CTL04_BANK_SPLIT_EN         0
+#define BM_DRAM_CTL04_BANK_SPLIT_EN         0x1
+#define BF_DRAM_CTL04_BANK_SPLIT_EN(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL05
+ * Address: 0x14
+ * SCT: no
+*/
+#define HW_DRAM_CTL05                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14))
+#define BP_DRAM_CTL05_INTRPTREADA           24
+#define BM_DRAM_CTL05_INTRPTREADA           0x1000000
+#define BF_DRAM_CTL05_INTRPTREADA(v)        (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL05_INTRPTAPBURST         16
+#define BM_DRAM_CTL05_INTRPTAPBURST         0x10000
+#define BF_DRAM_CTL05_INTRPTAPBURST(v)      (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL05_FAST_WRITE            8
+#define BM_DRAM_CTL05_FAST_WRITE            0x100
+#define BF_DRAM_CTL05_FAST_WRITE(v)         (((v) << 8) & 0x100)
+#define BP_DRAM_CTL05_EN_LOWPOWER_MODE      0
+#define BM_DRAM_CTL05_EN_LOWPOWER_MODE      0x1
+#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL06
+ * Address: 0x18
+ * SCT: no
+*/
+#define HW_DRAM_CTL06                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18))
+#define BP_DRAM_CTL06_POWER_DOWN        24
+#define BM_DRAM_CTL06_POWER_DOWN        0x1000000
+#define BF_DRAM_CTL06_POWER_DOWN(v)     (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL06_PLACEMENT_EN      16
+#define BM_DRAM_CTL06_PLACEMENT_EN      0x10000
+#define BF_DRAM_CTL06_PLACEMENT_EN(v)   (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL06_NO_CMD_INIT       8
+#define BM_DRAM_CTL06_NO_CMD_INIT       0x100
+#define BF_DRAM_CTL06_NO_CMD_INIT(v)    (((v) << 8) & 0x100)
+#define BP_DRAM_CTL06_INTRPTWRITEA      0
+#define BM_DRAM_CTL06_INTRPTWRITEA      0x1
+#define BF_DRAM_CTL06_INTRPTWRITEA(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL07
+ * Address: 0x1c
+ * SCT: no
+*/
+#define HW_DRAM_CTL07                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c))
+#define BP_DRAM_CTL07_RW_SAME_EN            24
+#define BM_DRAM_CTL07_RW_SAME_EN            0x1000000
+#define BF_DRAM_CTL07_RW_SAME_EN(v)         (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL07_REG_DIMM_ENABLE       16
+#define BM_DRAM_CTL07_REG_DIMM_ENABLE       0x10000
+#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v)    (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL07_RD2RD_TURN            8
+#define BM_DRAM_CTL07_RD2RD_TURN            0x100
+#define BF_DRAM_CTL07_RD2RD_TURN(v)         (((v) << 8) & 0x100)
+#define BP_DRAM_CTL07_PRIORITY_EN           0
+#define BM_DRAM_CTL07_PRIORITY_EN           0x1
+#define BF_DRAM_CTL07_PRIORITY_EN(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL08
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DRAM_CTL08                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20))
+#define BP_DRAM_CTL08_TRAS_LOCKOUT      24
+#define BM_DRAM_CTL08_TRAS_LOCKOUT      0x1000000
+#define BF_DRAM_CTL08_TRAS_LOCKOUT(v)   (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL08_START             16
+#define BM_DRAM_CTL08_START             0x10000
+#define BF_DRAM_CTL08_START(v)          (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL08_SREFRESH          8
+#define BM_DRAM_CTL08_SREFRESH          0x100
+#define BF_DRAM_CTL08_SREFRESH(v)       (((v) << 8) & 0x100)
+#define BP_DRAM_CTL08_SDR_MODE          0
+#define BM_DRAM_CTL08_SDR_MODE          0x1
+#define BF_DRAM_CTL08_SDR_MODE(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL09
+ * Address: 0x24
+ * SCT: no
+*/
+#define HW_DRAM_CTL09                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24))
+#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE         24
+#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE         0x3000000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v)      (((v) << 24) & 0x3000000)
+#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    16
+#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID    0x30000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000)
+#define BP_DRAM_CTL09_WRITE_MODEREG             8
+#define BM_DRAM_CTL09_WRITE_MODEREG             0x100
+#define BF_DRAM_CTL09_WRITE_MODEREG(v)          (((v) << 8) & 0x100)
+#define BP_DRAM_CTL09_WRITEINTERP               0
+#define BM_DRAM_CTL09_WRITEINTERP               0x1
+#define BF_DRAM_CTL09_WRITEINTERP(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL10
+ * Address: 0x28
+ * SCT: no
+*/
+#define HW_DRAM_CTL10               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28))
+#define BP_DRAM_CTL10_AGE_COUNT     24
+#define BM_DRAM_CTL10_AGE_COUNT     0x7000000
+#define BF_DRAM_CTL10_AGE_COUNT(v)  (((v) << 24) & 0x7000000)
+#define BP_DRAM_CTL10_ADDR_PINS     16
+#define BM_DRAM_CTL10_ADDR_PINS     0x70000
+#define BF_DRAM_CTL10_ADDR_PINS(v)  (((v) << 16) & 0x70000)
+#define BP_DRAM_CTL10_TEMRS         8
+#define BM_DRAM_CTL10_TEMRS         0x300
+#define BF_DRAM_CTL10_TEMRS(v)      (((v) << 8) & 0x300)
+#define BP_DRAM_CTL10_Q_FULLNESS    0
+#define BM_DRAM_CTL10_Q_FULLNESS    0x3
+#define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_DRAM_CTL11
+ * Address: 0x2c
+ * SCT: no
+*/
+#define HW_DRAM_CTL11                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c))
+#define BP_DRAM_CTL11_MAX_CS_REG            24
+#define BM_DRAM_CTL11_MAX_CS_REG            0x7000000
+#define BF_DRAM_CTL11_MAX_CS_REG(v)         (((v) << 24) & 0x7000000)
+#define BP_DRAM_CTL11_COMMAND_AGE_COUNT     16
+#define BM_DRAM_CTL11_COMMAND_AGE_COUNT     0x70000
+#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v)  (((v) << 16) & 0x70000)
+#define BP_DRAM_CTL11_COLUMN_SIZE           8
+#define BM_DRAM_CTL11_COLUMN_SIZE           0x700
+#define BF_DRAM_CTL11_COLUMN_SIZE(v)        (((v) << 8) & 0x700)
+#define BP_DRAM_CTL11_CASLAT                0
+#define BM_DRAM_CTL11_CASLAT                0x7
+#define BF_DRAM_CTL11_CASLAT(v)             (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_DRAM_CTL12
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_DRAM_CTL12               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30))
+#define BP_DRAM_CTL12_TWR_INT       24
+#define BM_DRAM_CTL12_TWR_INT       0x7000000
+#define BF_DRAM_CTL12_TWR_INT(v)    (((v) << 24) & 0x7000000)
+#define BP_DRAM_CTL12_TRRD          16
+#define BM_DRAM_CTL12_TRRD          0x70000
+#define BF_DRAM_CTL12_TRRD(v)       (((v) << 16) & 0x70000)
+#define BP_DRAM_CTL12_TCKE          0
+#define BM_DRAM_CTL12_TCKE          0x7
+#define BF_DRAM_CTL12_TCKE(v)       (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_DRAM_CTL13
+ * Address: 0x34
+ * SCT: no
+*/
+#define HW_DRAM_CTL13                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34))
+#define BP_DRAM_CTL13_CASLAT_LIN_GATE       24
+#define BM_DRAM_CTL13_CASLAT_LIN_GATE       0xf000000
+#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v)    (((v) << 24) & 0xf000000)
+#define BP_DRAM_CTL13_CASLAT_LIN            16
+#define BM_DRAM_CTL13_CASLAT_LIN            0xf0000
+#define BF_DRAM_CTL13_CASLAT_LIN(v)         (((v) << 16) & 0xf0000)
+#define BP_DRAM_CTL13_APREBIT               8
+#define BM_DRAM_CTL13_APREBIT               0xf00
+#define BF_DRAM_CTL13_APREBIT(v)            (((v) << 8) & 0xf00)
+#define BP_DRAM_CTL13_TWTR                  0
+#define BM_DRAM_CTL13_TWTR                  0x7
+#define BF_DRAM_CTL13_TWTR(v)               (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_DRAM_CTL14
+ * Address: 0x38
+ * SCT: no
+*/
+#define HW_DRAM_CTL14                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38))
+#define BP_DRAM_CTL14_MAX_COL_REG                   24
+#define BM_DRAM_CTL14_MAX_COL_REG                   0xf000000
+#define BF_DRAM_CTL14_MAX_COL_REG(v)                (((v) << 24) & 0xf000000)
+#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       16
+#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE       0xf0000
+#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v)    (((v) << 16) & 0xf0000)
+#define BP_DRAM_CTL14_INITAREF                      8
+#define BM_DRAM_CTL14_INITAREF                      0xf00
+#define BF_DRAM_CTL14_INITAREF(v)                   (((v) << 8) & 0xf00)
+#define BP_DRAM_CTL14_CS_MAP                        0
+#define BM_DRAM_CTL14_CS_MAP                        0xf
+#define BF_DRAM_CTL14_CS_MAP(v)                     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DRAM_CTL15
+ * Address: 0x3c
+ * SCT: no
+*/
+#define HW_DRAM_CTL15                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c))
+#define BP_DRAM_CTL15_TRP               24
+#define BM_DRAM_CTL15_TRP               0xf000000
+#define BF_DRAM_CTL15_TRP(v)            (((v) << 24) & 0xf000000)
+#define BP_DRAM_CTL15_TDAL              16
+#define BM_DRAM_CTL15_TDAL              0xf0000
+#define BF_DRAM_CTL15_TDAL(v)           (((v) << 16) & 0xf0000)
+#define BP_DRAM_CTL15_PORT_BUSY         8
+#define BM_DRAM_CTL15_PORT_BUSY         0xf00
+#define BF_DRAM_CTL15_PORT_BUSY(v)      (((v) << 8) & 0xf00)
+#define BP_DRAM_CTL15_MAX_ROW_REG       0
+#define BM_DRAM_CTL15_MAX_ROW_REG       0xf
+#define BF_DRAM_CTL15_MAX_ROW_REG(v)    (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DRAM_CTL16
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_DRAM_CTL16                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40))
+#define BP_DRAM_CTL16_TMRD                      24
+#define BM_DRAM_CTL16_TMRD                      0x1f000000
+#define BF_DRAM_CTL16_TMRD(v)                   (((v) << 24) & 0x1f000000)
+#define BP_DRAM_CTL16_LOWPOWER_CONTROL          16
+#define BM_DRAM_CTL16_LOWPOWER_CONTROL          0x1f0000
+#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v)       (((v) << 16) & 0x1f0000)
+#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      8
+#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE      0x1f00
+#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v)   (((v) << 8) & 0x1f00)
+#define BP_DRAM_CTL16_INT_ACK                   0
+#define BM_DRAM_CTL16_INT_ACK                   0xf
+#define BF_DRAM_CTL16_INT_ACK(v)                (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_DRAM_CTL17
+ * Address: 0x44
+ * SCT: no
+*/
+#define HW_DRAM_CTL17                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44))
+#define BP_DRAM_CTL17_DLL_START_POINT       24
+#define BM_DRAM_CTL17_DLL_START_POINT       0xff000000
+#define BF_DRAM_CTL17_DLL_START_POINT(v)    (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL17_DLL_LOCK              16
+#define BM_DRAM_CTL17_DLL_LOCK              0xff0000
+#define BF_DRAM_CTL17_DLL_LOCK(v)           (((v) << 16) & 0xff0000)
+#define BP_DRAM_CTL17_DLL_INCREMENT         8
+#define BM_DRAM_CTL17_DLL_INCREMENT         0xff00
+#define BF_DRAM_CTL17_DLL_INCREMENT(v)      (((v) << 8) & 0xff00)
+#define BP_DRAM_CTL17_TRC                   0
+#define BM_DRAM_CTL17_TRC                   0x1f
+#define BF_DRAM_CTL17_TRC(v)                (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DRAM_CTL18
+ * Address: 0x48
+ * SCT: no
+*/
+#define HW_DRAM_CTL18                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48))
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_1       24
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_1       0x7f000000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v)    (((v) << 24) & 0x7f000000)
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_0       16
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_0       0x7f0000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v)    (((v) << 16) & 0x7f0000)
+#define BP_DRAM_CTL18_INT_STATUS            8
+#define BM_DRAM_CTL18_INT_STATUS            0x1f00
+#define BF_DRAM_CTL18_INT_STATUS(v)         (((v) << 8) & 0x1f00)
+#define BP_DRAM_CTL18_INT_MASK              0
+#define BM_DRAM_CTL18_INT_MASK              0x1f
+#define BF_DRAM_CTL18_INT_MASK(v)           (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_DRAM_CTL19
+ * Address: 0x4c
+ * SCT: no
+*/
+#define HW_DRAM_CTL19                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c))
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      24
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS      0xff000000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v)   (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT             16
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT             0x7f0000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v)          (((v) << 16) & 0x7f0000)
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    8
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1    0xff00
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00)
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0    0xff
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DRAM_CTL20
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_DRAM_CTL20                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50))
+#define BP_DRAM_CTL20_TRCD_INT                  24
+#define BM_DRAM_CTL20_TRCD_INT                  0xff000000
+#define BF_DRAM_CTL20_TRCD_INT(v)               (((v) << 24) & 0xff000000)
+#define BP_DRAM_CTL20_TRAS_MIN                  16
+#define BM_DRAM_CTL20_TRAS_MIN                  0xff0000
+#define BF_DRAM_CTL20_TRAS_MIN(v)               (((v) << 16) & 0xff0000)
+#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       8
+#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS       0xff00
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v)    (((v) << 8) & 0xff00)
+#define BP_DRAM_CTL20_WR_DQS_SHIFT              0
+#define BM_DRAM_CTL20_WR_DQS_SHIFT              0x7f
+#define BF_DRAM_CTL20_WR_DQS_SHIFT(v)           (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_DRAM_CTL21
+ * Address: 0x54
+ * SCT: no
+*/
+#define HW_DRAM_CTL21                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54))
+#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH       8
+#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH       0x3ff00
+#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v)    (((v) << 8) & 0x3ff00)
+#define BP_DRAM_CTL21_TRFC                      0
+#define BM_DRAM_CTL21_TRFC                      0xff
+#define BF_DRAM_CTL21_TRFC(v)                   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DRAM_CTL22
+ * Address: 0x58
+ * SCT: no
+*/
+#define HW_DRAM_CTL22               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58))
+#define BP_DRAM_CTL22_AHB0_WRCNT    16
+#define BM_DRAM_CTL22_AHB0_WRCNT    0x7ff0000
+#define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL22_AHB0_RDCNT    0
+#define BM_DRAM_CTL22_AHB0_RDCNT    0x7ff
+#define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL23
+ * Address: 0x5c
+ * SCT: no
+*/
+#define HW_DRAM_CTL23               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c))
+#define BP_DRAM_CTL23_AHB1_WRCNT    16
+#define BM_DRAM_CTL23_AHB1_WRCNT    0x7ff0000
+#define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL23_AHB1_RDCNT    0
+#define BM_DRAM_CTL23_AHB1_RDCNT    0x7ff
+#define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL24
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DRAM_CTL24               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60))
+#define BP_DRAM_CTL24_AHB2_WRCNT    16
+#define BM_DRAM_CTL24_AHB2_WRCNT    0x7ff0000
+#define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL24_AHB2_RDCNT    0
+#define BM_DRAM_CTL24_AHB2_RDCNT    0x7ff
+#define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL25
+ * Address: 0x64
+ * SCT: no
+*/
+#define HW_DRAM_CTL25               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64))
+#define BP_DRAM_CTL25_AHB3_WRCNT    16
+#define BM_DRAM_CTL25_AHB3_WRCNT    0x7ff0000
+#define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000)
+#define BP_DRAM_CTL25_AHB3_RDCNT    0
+#define BM_DRAM_CTL25_AHB3_RDCNT    0x7ff
+#define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_DRAM_CTL26
+ * Address: 0x68
+ * SCT: no
+*/
+#define HW_DRAM_CTL26           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68))
+#define BP_DRAM_CTL26_TREF      0
+#define BM_DRAM_CTL26_TREF      0xfff
+#define BF_DRAM_CTL26_TREF(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_DRAM_CTL27
+ * Address: 0x6c
+ * SCT: no
+*/
+#define HW_DRAM_CTL27   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c))
+
+/**
+ * Register: HW_DRAM_CTL28
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_DRAM_CTL28   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70))
+
+/**
+ * Register: HW_DRAM_CTL29
+ * Address: 0x74
+ * SCT: no
+*/
+#define HW_DRAM_CTL29                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74))
+#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     16
+#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT     0xffff0000
+#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v)  (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0
+#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT     0xffff
+#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL30
+ * Address: 0x78
+ * SCT: no
+*/
+#define HW_DRAM_CTL30                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78))
+#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         16
+#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD         0xffff0000
+#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v)      (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0
+#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT       0xffff
+#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL31
+ * Address: 0x7c
+ * SCT: no
+*/
+#define HW_DRAM_CTL31                               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c))
+#define BP_DRAM_CTL31_TDLL                          16
+#define BM_DRAM_CTL31_TDLL                          0xffff0000
+#define BF_DRAM_CTL31_TDLL(v)                       (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0
+#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT     0xffff
+#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL32
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_DRAM_CTL32               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80))
+#define BP_DRAM_CTL32_TXSNR         16
+#define BM_DRAM_CTL32_TXSNR         0xffff0000
+#define BF_DRAM_CTL32_TXSNR(v)      (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL32_TRAS_MAX      0
+#define BM_DRAM_CTL32_TRAS_MAX      0xffff
+#define BF_DRAM_CTL32_TRAS_MAX(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL33
+ * Address: 0x84
+ * SCT: no
+*/
+#define HW_DRAM_CTL33               (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84))
+#define BP_DRAM_CTL33_VERSION       16
+#define BM_DRAM_CTL33_VERSION       0xffff0000
+#define BF_DRAM_CTL33_VERSION(v)    (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL33_TXSR          0
+#define BM_DRAM_CTL33_TXSR          0xffff
+#define BF_DRAM_CTL33_TXSR(v)       (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_DRAM_CTL34
+ * Address: 0x88
+ * SCT: no
+*/
+#define HW_DRAM_CTL34           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88))
+#define BP_DRAM_CTL34_TINIT     0
+#define BM_DRAM_CTL34_TINIT     0xffffff
+#define BF_DRAM_CTL34_TINIT(v)  (((v) << 0) & 0xffffff)
+
+/**
+ * Register: HW_DRAM_CTL35
+ * Address: 0x8c
+ * SCT: no
+*/
+#define HW_DRAM_CTL35                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c))
+#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR     0
+#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR     0x7fffffff
+#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v)  (((v) << 0) & 0x7fffffff)
+
+/**
+ * Register: HW_DRAM_CTL36
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_DRAM_CTL36                           (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90))
+#define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT       24
+#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT       0x1000000
+#define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v)    (((v) << 24) & 0x1000000)
+#define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH     16
+#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH     0x10000
+#define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v)  (((v) << 16) & 0x10000)
+#define BP_DRAM_CTL36_BUS_SHARE_ENABLE          8
+#define BM_DRAM_CTL36_BUS_SHARE_ENABLE          0x100
+#define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v)       (((v) << 8) & 0x100)
+#define BP_DRAM_CTL36_ACTIVE_AGING              0
+#define BM_DRAM_CTL36_ACTIVE_AGING              0x1
+#define BF_DRAM_CTL36_ACTIVE_AGING(v)           (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL37
+ * Address: 0x94
+ * SCT: no
+*/
+#define HW_DRAM_CTL37                       (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94))
+#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT     8
+#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT     0x3ff00
+#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v)  (((v) << 8) & 0x3ff00)
+#define BP_DRAM_CTL37_TREF_ENABLE           0
+#define BM_DRAM_CTL37_TREF_ENABLE           0x1
+#define BF_DRAM_CTL37_TREF_ENABLE(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_DRAM_CTL38
+ * Address: 0x98
+ * SCT: no
+*/
+#define HW_DRAM_CTL38                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98))
+#define BP_DRAM_CTL38_EMRS2_DATA_0      16
+#define BM_DRAM_CTL38_EMRS2_DATA_0      0x1fff0000
+#define BF_DRAM_CTL38_EMRS2_DATA_0(v)   (((v) << 16) & 0x1fff0000)
+#define BP_DRAM_CTL38_EMRS1_DATA        0
+#define BM_DRAM_CTL38_EMRS1_DATA        0x1fff
+#define BF_DRAM_CTL38_EMRS1_DATA(v)     (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DRAM_CTL39
+ * Address: 0x9c
+ * SCT: no
+*/
+#define HW_DRAM_CTL39                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c))
+#define BP_DRAM_CTL39_EMRS2_DATA_2      16
+#define BM_DRAM_CTL39_EMRS2_DATA_2      0x1fff0000
+#define BF_DRAM_CTL39_EMRS2_DATA_2(v)   (((v) << 16) & 0x1fff0000)
+#define BP_DRAM_CTL39_EMRS2_DATA_1      0
+#define BM_DRAM_CTL39_EMRS2_DATA_1      0x1fff
+#define BF_DRAM_CTL39_EMRS2_DATA_1(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_DRAM_CTL40
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_DRAM_CTL40                   (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0))
+#define BP_DRAM_CTL40_TPDEX             16
+#define BM_DRAM_CTL40_TPDEX             0xffff0000
+#define BF_DRAM_CTL40_TPDEX(v)          (((v) << 16) & 0xffff0000)
+#define BP_DRAM_CTL40_EMRS2_DATA_3      0
+#define BM_DRAM_CTL40_EMRS2_DATA_3      0x1fff
+#define BF_DRAM_CTL40_EMRS2_DATA_3(v)   (((v) << 0) & 0x1fff)
+
+#endif /* __HEADERGEN__STMP3700__DRAM__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h
new file mode 100644
index 0000000000..a3ae0f52d1
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h
@@ -0,0 +1,274 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__DRI__H__
+#define __HEADERGEN__STMP3700__DRI__H__
+
+#define REGS_DRI_BASE (0x80074000)
+
+#define REGS_DRI_VERSION "3.2.0"
+
+/**
+ * Register: HW_DRI_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_DRI_CTRL                                     (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
+#define HW_DRI_CTRL_SET                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
+#define HW_DRI_CTRL_CLR                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
+#define HW_DRI_CTRL_TOG                                 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
+#define BP_DRI_CTRL_SFTRST                              31
+#define BM_DRI_CTRL_SFTRST                              0x80000000
+#define BV_DRI_CTRL_SFTRST__RUN                         0x0
+#define BV_DRI_CTRL_SFTRST__RESET                       0x1
+#define BF_DRI_CTRL_SFTRST(v)                           (((v) << 31) & 0x80000000)
+#define BF_DRI_CTRL_SFTRST_V(v)                         ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_DRI_CTRL_CLKGATE                             30
+#define BM_DRI_CTRL_CLKGATE                             0x40000000
+#define BV_DRI_CTRL_CLKGATE__RUN                        0x0
+#define BV_DRI_CTRL_CLKGATE__NO_CLKS                    0x1
+#define BF_DRI_CTRL_CLKGATE(v)                          (((v) << 30) & 0x40000000)
+#define BF_DRI_CTRL_CLKGATE_V(v)                        ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_DRI_CTRL_ENABLE_INPUTS                       29
+#define BM_DRI_CTRL_ENABLE_INPUTS                       0x20000000
+#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN       0x0
+#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN       0x1
+#define BF_DRI_CTRL_ENABLE_INPUTS(v)                    (((v) << 29) & 0x20000000)
+#define BF_DRI_CTRL_ENABLE_INPUTS_V(v)                  ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
+#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR                 26
+#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR                 0x4000000
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v)              (((v) << 26) & 0x4000000)
+#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
+#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR                 25
+#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR                 0x2000000
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE         0x0
+#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP           0x1
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v)              (((v) << 25) & 0x2000000)
+#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v)            ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
+#define BP_DRI_CTRL_DMA_DELAY_COUNT                     16
+#define BM_DRI_CTRL_DMA_DELAY_COUNT                     0x1f0000
+#define BF_DRI_CTRL_DMA_DELAY_COUNT(v)                  (((v) << 16) & 0x1f0000)
+#define BP_DRI_CTRL_REACQUIRE_PHASE                     15
+#define BM_DRI_CTRL_REACQUIRE_PHASE                     0x8000
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL             0x0
+#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE          0x1
+#define BF_DRI_CTRL_REACQUIRE_PHASE(v)                  (((v) << 15) & 0x8000)
+#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v)                ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
+#define BP_DRI_CTRL_OVERFLOW_IRQ_EN                     11
+#define BM_DRI_CTRL_OVERFLOW_IRQ_EN                     0x800
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED           0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED            0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v)                  (((v) << 11) & 0x800)
+#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v)                ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              10
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN              0x400
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED    0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED     0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v)           (((v) << 10) & 0x400)
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v)         ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
+#define BP_DRI_CTRL_ATTENTION_IRQ_EN                    9
+#define BM_DRI_CTRL_ATTENTION_IRQ_EN                    0x200
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED          0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED           0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v)                 (((v) << 9) & 0x200)
+#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v)               ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
+#define BP_DRI_CTRL_OVERFLOW_IRQ                        3
+#define BM_DRI_CTRL_OVERFLOW_IRQ                        0x8
+#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST               0x1
+#define BF_DRI_CTRL_OVERFLOW_IRQ(v)                     (((v) << 3) & 0x8)
+#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v)                   ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
+#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 2
+#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ                 0x4
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST     0x0
+#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST        0x1
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v)              (((v) << 2) & 0x4)
+#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v)            ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
+#define BP_DRI_CTRL_ATTENTION_IRQ                       1
+#define BM_DRI_CTRL_ATTENTION_IRQ                       0x2
+#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST           0x0
+#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST              0x1
+#define BF_DRI_CTRL_ATTENTION_IRQ(v)                    (((v) << 1) & 0x2)
+#define BF_DRI_CTRL_ATTENTION_IRQ_V(v)                  ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
+#define BP_DRI_CTRL_RUN                                 0
+#define BM_DRI_CTRL_RUN                                 0x1
+#define BV_DRI_CTRL_RUN__HALT                           0x0
+#define BV_DRI_CTRL_RUN__RUN                            0x1
+#define BF_DRI_CTRL_RUN(v)                              (((v) << 0) & 0x1)
+#define BF_DRI_CTRL_RUN_V(v)                            ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
+
+/**
+ * Register: HW_DRI_TIMING
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_DRI_TIMING                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
+#define BP_DRI_TIMING_PILOT_REP_RATE            16
+#define BM_DRI_TIMING_PILOT_REP_RATE            0xf0000
+#define BF_DRI_TIMING_PILOT_REP_RATE(v)         (((v) << 16) & 0xf0000)
+#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL    0
+#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL    0xff
+#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_DRI_STAT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_DRI_STAT                                         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
+#define BP_DRI_STAT_DRI_PRESENT                             31
+#define BM_DRI_STAT_DRI_PRESENT                             0x80000000
+#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE                0x0
+#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE                  0x1
+#define BF_DRI_STAT_DRI_PRESENT(v)                          (((v) << 31) & 0x80000000)
+#define BF_DRI_STAT_DRI_PRESENT_V(v)                        ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
+#define BP_DRI_STAT_PILOT_PHASE                             16
+#define BM_DRI_STAT_PILOT_PHASE                             0xf0000
+#define BF_DRI_STAT_PILOT_PHASE(v)                          (((v) << 16) & 0xf0000)
+#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    3
+#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY                    0x8
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST           0x1
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v)                 (((v) << 3) & 0x8)
+#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v)               ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
+#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             2
+#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY             0x4
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST    0x1
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v)          (((v) << 2) & 0x4)
+#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v)        ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
+#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY                   1
+#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY                   0x2
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST       0x0
+#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST          0x1
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v)                (((v) << 1) & 0x2)
+#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v)              ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
+
+/**
+ * Register: HW_DRI_DATA
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_DRI_DATA         (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
+#define BP_DRI_DATA_DATA    0
+#define BM_DRI_DATA_DATA    0xffffffff
+#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_DRI_DEBUG0
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_DRI_DEBUG0                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
+#define HW_DRI_DEBUG0_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
+#define HW_DRI_DEBUG0_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
+#define HW_DRI_DEBUG0_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
+#define BP_DRI_DEBUG0_DMAREQ                        31
+#define BM_DRI_DEBUG0_DMAREQ                        0x80000000
+#define BF_DRI_DEBUG0_DMAREQ(v)                     (((v) << 31) & 0x80000000)
+#define BP_DRI_DEBUG0_DMACMDKICK                    30
+#define BM_DRI_DEBUG0_DMACMDKICK                    0x40000000
+#define BF_DRI_DEBUG0_DMACMDKICK(v)                 (((v) << 30) & 0x40000000)
+#define BP_DRI_DEBUG0_DRI_CLK_INPUT                 29
+#define BM_DRI_DEBUG0_DRI_CLK_INPUT                 0x20000000
+#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v)              (((v) << 29) & 0x20000000)
+#define BP_DRI_DEBUG0_DRI_DATA_INPUT                28
+#define BM_DRI_DEBUG0_DRI_DATA_INPUT                0x10000000
+#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v)             (((v) << 28) & 0x10000000)
+#define BP_DRI_DEBUG0_TEST_MODE                     27
+#define BM_DRI_DEBUG0_TEST_MODE                     0x8000000
+#define BF_DRI_DEBUG0_TEST_MODE(v)                  (((v) << 27) & 0x8000000)
+#define BP_DRI_DEBUG0_PILOT_REP_RATE                26
+#define BM_DRI_DEBUG0_PILOT_REP_RATE                0x4000000
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ     0x0
+#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ    0x1
+#define BF_DRI_DEBUG0_PILOT_REP_RATE(v)             (((v) << 26) & 0x4000000)
+#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v)           ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
+#define BP_DRI_DEBUG0_SPARE                         18
+#define BM_DRI_DEBUG0_SPARE                         0x3fc0000
+#define BF_DRI_DEBUG0_SPARE(v)                      (((v) << 18) & 0x3fc0000)
+#define BP_DRI_DEBUG0_FRAME                         0
+#define BM_DRI_DEBUG0_FRAME                         0x3ffff
+#define BF_DRI_DEBUG0_FRAME(v)                      (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_DRI_DEBUG1
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_DRI_DEBUG1                               (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
+#define HW_DRI_DEBUG1_SET                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
+#define HW_DRI_DEBUG1_CLR                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
+#define HW_DRI_DEBUG1_TOG                           (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
+#define BP_DRI_DEBUG1_INVERT_PILOT                  31
+#define BM_DRI_DEBUG1_INVERT_PILOT                  0x80000000
+#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL          0x0
+#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED        0x1
+#define BF_DRI_DEBUG1_INVERT_PILOT(v)               (((v) << 31) & 0x80000000)
+#define BF_DRI_DEBUG1_INVERT_PILOT_V(v)             ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
+#define BP_DRI_DEBUG1_INVERT_ATTENTION              30
+#define BM_DRI_DEBUG1_INVERT_ATTENTION              0x40000000
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_ATTENTION(v)           (((v) << 30) & 0x40000000)
+#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v)         ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
+#define BP_DRI_DEBUG1_INVERT_DRI_DATA               29
+#define BM_DRI_DEBUG1_INVERT_DRI_DATA               0x20000000
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL       0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED     0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v)            (((v) << 29) & 0x20000000)
+#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v)          ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
+#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK              28
+#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK              0x10000000
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL      0x0
+#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED    0x1
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v)           (((v) << 28) & 0x10000000)
+#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v)         ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
+#define BP_DRI_DEBUG1_REVERSE_FRAME                 27
+#define BM_DRI_DEBUG1_REVERSE_FRAME                 0x8000000
+#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL         0x0
+#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED       0x1
+#define BF_DRI_DEBUG1_REVERSE_FRAME(v)              (((v) << 27) & 0x8000000)
+#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v)            ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
+#define BP_DRI_DEBUG1_SWIZZLED_FRAME                0
+#define BM_DRI_DEBUG1_SWIZZLED_FRAME                0x3ffff
+#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v)             (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_DRI_VERSION
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_DRI_VERSION          (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60))
+#define BP_DRI_VERSION_MAJOR    24
+#define BM_DRI_VERSION_MAJOR    0xff000000
+#define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_DRI_VERSION_MINOR    16
+#define BM_DRI_VERSION_MINOR    0xff0000
+#define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_DRI_VERSION_STEP     0
+#define BM_DRI_VERSION_STEP     0xffff
+#define BF_DRI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__DRI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h
new file mode 100644
index 0000000000..e84274169e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h
@@ -0,0 +1,387 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__ECC8__H__
+#define __HEADERGEN__STMP3700__ECC8__H__
+
+#define REGS_ECC8_BASE (0x80008000)
+
+#define REGS_ECC8_VERSION "3.2.0"
+
+/**
+ * Register: HW_ECC8_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_ECC8_CTRL                        (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x0))
+#define HW_ECC8_CTRL_SET                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x4))
+#define HW_ECC8_CTRL_CLR                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x8))
+#define HW_ECC8_CTRL_TOG                    (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0xc))
+#define BP_ECC8_CTRL_SFTRST                 31
+#define BM_ECC8_CTRL_SFTRST                 0x80000000
+#define BV_ECC8_CTRL_SFTRST__RUN            0x0
+#define BV_ECC8_CTRL_SFTRST__RESET          0x1
+#define BF_ECC8_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BF_ECC8_CTRL_SFTRST_V(v)            ((BV_ECC8_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_ECC8_CTRL_CLKGATE                30
+#define BM_ECC8_CTRL_CLKGATE                0x40000000
+#define BV_ECC8_CTRL_CLKGATE__RUN           0x0
+#define BV_ECC8_CTRL_CLKGATE__NO_CLKS       0x1
+#define BF_ECC8_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BF_ECC8_CTRL_CLKGATE_V(v)           ((BV_ECC8_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_ECC8_CTRL_AHBM_SFTRST            29
+#define BM_ECC8_CTRL_AHBM_SFTRST            0x20000000
+#define BV_ECC8_CTRL_AHBM_SFTRST__RUN       0x0
+#define BV_ECC8_CTRL_AHBM_SFTRST__RESET     0x1
+#define BF_ECC8_CTRL_AHBM_SFTRST(v)         (((v) << 29) & 0x20000000)
+#define BF_ECC8_CTRL_AHBM_SFTRST_V(v)       ((BV_ECC8_CTRL_AHBM_SFTRST__##v << 29) & 0x20000000)
+#define BP_ECC8_CTRL_THROTTLE               24
+#define BM_ECC8_CTRL_THROTTLE               0xf000000
+#define BF_ECC8_CTRL_THROTTLE(v)            (((v) << 24) & 0xf000000)
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN     10
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN     0x400
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v)  (((v) << 10) & 0x400)
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     9
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN     0x200
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v)  (((v) << 9) & 0x200)
+#define BP_ECC8_CTRL_COMPLETE_IRQ_EN        8
+#define BM_ECC8_CTRL_COMPLETE_IRQ_EN        0x100
+#define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v)     (((v) << 8) & 0x100)
+#define BP_ECC8_CTRL_BM_ERROR_IRQ           3
+#define BM_ECC8_CTRL_BM_ERROR_IRQ           0x8
+#define BF_ECC8_CTRL_BM_ERROR_IRQ(v)        (((v) << 3) & 0x8)
+#define BP_ECC8_CTRL_DEBUG_STALL_IRQ        2
+#define BM_ECC8_CTRL_DEBUG_STALL_IRQ        0x4
+#define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v)     (((v) << 2) & 0x4)
+#define BP_ECC8_CTRL_DEBUG_WRITE_IRQ        1
+#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ        0x2
+#define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v)     (((v) << 1) & 0x2)
+#define BP_ECC8_CTRL_COMPLETE_IRQ           0
+#define BM_ECC8_CTRL_COMPLETE_IRQ           0x1
+#define BF_ECC8_CTRL_COMPLETE_IRQ(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_ECC8_STATUS0
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_ECC8_STATUS0                                 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x10))
+#define BP_ECC8_STATUS0_HANDLE                          16
+#define BM_ECC8_STATUS0_HANDLE                          0xffff0000
+#define BF_ECC8_STATUS0_HANDLE(v)                       (((v) << 16) & 0xffff0000)
+#define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT              15
+#define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT              0x8000
+#define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v)           (((v) << 15) & 0x8000)
+#define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT              14
+#define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT              0x4000
+#define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v)           (((v) << 14) & 0x4000)
+#define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT              13
+#define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT              0x2000
+#define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v)           (((v) << 13) & 0x2000)
+#define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT              12
+#define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT              0x1000
+#define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v)           (((v) << 12) & 0x1000)
+#define BP_ECC8_STATUS0_STATUS_AUX                      8
+#define BM_ECC8_STATUS0_STATUS_AUX                      0xf00
+#define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS           0x0
+#define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE     0x1
+#define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE     0x2
+#define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE   0x3
+#define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE    0x4
+#define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED         0xc
+#define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE       0xe
+#define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES            0xf
+#define BF_ECC8_STATUS0_STATUS_AUX(v)                   (((v) << 8) & 0xf00)
+#define BF_ECC8_STATUS0_STATUS_AUX_V(v)                 ((BV_ECC8_STATUS0_STATUS_AUX__##v << 8) & 0xf00)
+#define BP_ECC8_STATUS0_ALLONES                         4
+#define BM_ECC8_STATUS0_ALLONES                         0x10
+#define BF_ECC8_STATUS0_ALLONES(v)                      (((v) << 4) & 0x10)
+#define BP_ECC8_STATUS0_CORRECTED                       3
+#define BM_ECC8_STATUS0_CORRECTED                       0x8
+#define BF_ECC8_STATUS0_CORRECTED(v)                    (((v) << 3) & 0x8)
+#define BP_ECC8_STATUS0_UNCORRECTABLE                   2
+#define BM_ECC8_STATUS0_UNCORRECTABLE                   0x4
+#define BF_ECC8_STATUS0_UNCORRECTABLE(v)                (((v) << 2) & 0x4)
+#define BP_ECC8_STATUS0_COMPLETED_CE                    0
+#define BM_ECC8_STATUS0_COMPLETED_CE                    0x3
+#define BF_ECC8_STATUS0_COMPLETED_CE(v)                 (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_ECC8_STATUS1
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_ECC8_STATUS1                                     (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x20))
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD7                     28
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD7                     0xf0000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v)                  (((v) << 28) & 0xf0000000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD7__##v << 28) & 0xf0000000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD6                     24
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD6                     0xf000000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v)                  (((v) << 24) & 0xf000000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD6__##v << 24) & 0xf000000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD5                     20
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD5                     0xf00000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v)                  (((v) << 20) & 0xf00000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD5__##v << 20) & 0xf00000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD4                     16
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD4                     0xf0000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v)                  (((v) << 16) & 0xf0000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD4__##v << 16) & 0xf0000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD3                     12
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD3                     0xf000
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v)                  (((v) << 12) & 0xf000)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD3__##v << 12) & 0xf000)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD2                     8
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD2                     0xf00
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v)                  (((v) << 8) & 0xf00)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD2__##v << 8) & 0xf00)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD1                     4
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD1                     0xf0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v)                  (((v) << 4) & 0xf0)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD1__##v << 4) & 0xf0)
+#define BP_ECC8_STATUS1_STATUS_PAYLOAD0                     0
+#define BM_ECC8_STATUS1_STATUS_PAYLOAD0                     0xf
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS          0x0
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE    0x1
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE    0x2
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE  0x3
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE   0x4
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE   0x5
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE    0x6
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE  0x7
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE  0x8
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED        0xc
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE      0xe
+#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES           0xf
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v)                  (((v) << 0) & 0xf)
+#define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(v)                ((BV_ECC8_STATUS1_STATUS_PAYLOAD0__##v << 0) & 0xf)
+
+/**
+ * Register: HW_ECC8_DEBUG0
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_ECC8_DEBUG0                                      (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x0))
+#define HW_ECC8_DEBUG0_SET                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x4))
+#define HW_ECC8_DEBUG0_CLR                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x8))
+#define HW_ECC8_DEBUG0_TOG                                  (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0xc))
+#define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            16
+#define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL            0x1ff0000
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL    0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v)         (((v) << 16) & 0x1ff0000)
+#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v)       ((BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 15
+#define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND                 0x8000
+#define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v)              (((v) << 15) & 0x8000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               14
+#define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG               0x4000
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA         0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX          0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v)            (((v) << 14) & 0x4000)
+#define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v)          ((BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K                     13
+#define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K                     0x2000
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k                 0x1
+#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k                 0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v)                  (((v) << 13) & 0x2000)
+#define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v)                ((BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000)
+#define BP_ECC8_DEBUG0_KES_DEBUG_KICK                       12
+#define BM_ECC8_DEBUG0_KES_DEBUG_KICK                       0x1000
+#define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v)                    (((v) << 12) & 0x1000)
+#define BP_ECC8_DEBUG0_KES_STANDALONE                       11
+#define BM_ECC8_DEBUG0_KES_STANDALONE                       0x800
+#define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL               0x0
+#define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE            0x1
+#define BF_ECC8_DEBUG0_KES_STANDALONE(v)                    (((v) << 11) & 0x800)
+#define BF_ECC8_DEBUG0_KES_STANDALONE_V(v)                  ((BV_ECC8_DEBUG0_KES_STANDALONE__##v << 11) & 0x800)
+#define BP_ECC8_DEBUG0_KES_DEBUG_STEP                       10
+#define BM_ECC8_DEBUG0_KES_DEBUG_STEP                       0x400
+#define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v)                    (((v) << 10) & 0x400)
+#define BP_ECC8_DEBUG0_KES_DEBUG_STALL                      9
+#define BM_ECC8_DEBUG0_KES_DEBUG_STALL                      0x200
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL              0x0
+#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT                0x1
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v)                   (((v) << 9) & 0x200)
+#define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(v)                 ((BV_ECC8_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200)
+#define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   8
+#define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS                   0x100
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL           0x0
+#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE        0x1
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v)                (((v) << 8) & 0x100)
+#define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v)              ((BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100)
+#define BP_ECC8_DEBUG0_DEBUG_REG_SELECT                     0
+#define BM_ECC8_DEBUG0_DEBUG_REG_SELECT                     0x3f
+#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v)                  (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_ECC8_DBGKESREAD
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_ECC8_DBGKESREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x40))
+#define BP_ECC8_DBGKESREAD_VALUES       0
+#define BM_ECC8_DBGKESREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGKESREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_DBGCSFEREAD
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_ECC8_DBGCSFEREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x50))
+#define BP_ECC8_DBGCSFEREAD_VALUES      0
+#define BM_ECC8_DBGCSFEREAD_VALUES      0xffffffff
+#define BF_ECC8_DBGCSFEREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_DBGSYNDGENREAD
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_ECC8_DBGSYNDGENREAD              (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x60))
+#define BP_ECC8_DBGSYNDGENREAD_VALUES       0
+#define BM_ECC8_DBGSYNDGENREAD_VALUES       0xffffffff
+#define BF_ECC8_DBGSYNDGENREAD_VALUES(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_DBGAHBMREAD
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_ECC8_DBGAHBMREAD             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x70))
+#define BP_ECC8_DBGAHBMREAD_VALUES      0
+#define BM_ECC8_DBGAHBMREAD_VALUES      0xffffffff
+#define BF_ECC8_DBGAHBMREAD_VALUES(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_BLOCKNAME
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_ECC8_BLOCKNAME           (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x80))
+#define BP_ECC8_BLOCKNAME_NAME      0
+#define BM_ECC8_BLOCKNAME_NAME      0xffffffff
+#define BF_ECC8_BLOCKNAME_NAME(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ECC8_VERSION
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_ECC8_VERSION             (*(volatile unsigned long *)(REGS_ECC8_BASE + 0xa0))
+#define BP_ECC8_VERSION_MAJOR       24
+#define BM_ECC8_VERSION_MAJOR       0xff000000
+#define BF_ECC8_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_ECC8_VERSION_MINOR       16
+#define BM_ECC8_VERSION_MINOR       0xff0000
+#define BF_ECC8_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_ECC8_VERSION_STEP        0
+#define BM_ECC8_VERSION_STEP        0xffff
+#define BF_ECC8_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__ECC8__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h
new file mode 100644
index 0000000000..b81fb35313
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h
@@ -0,0 +1,196 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__EMI__H__
+#define __HEADERGEN__STMP3700__EMI__H__
+
+#define REGS_EMI_BASE (0x80020000)
+
+#define REGS_EMI_VERSION "3.2.0"
+
+/**
+ * Register: HW_EMI_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_EMI_CTRL                     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0))
+#define HW_EMI_CTRL_SET                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4))
+#define HW_EMI_CTRL_CLR                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8))
+#define HW_EMI_CTRL_TOG                 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc))
+#define BP_EMI_CTRL_SFTRST              31
+#define BM_EMI_CTRL_SFTRST              0x80000000
+#define BF_EMI_CTRL_SFTRST(v)           (((v) << 31) & 0x80000000)
+#define BP_EMI_CTRL_CLKGATE             30
+#define BM_EMI_CTRL_CLKGATE             0x40000000
+#define BF_EMI_CTRL_CLKGATE(v)          (((v) << 30) & 0x40000000)
+#define BP_EMI_CTRL_MEM_WIDTH           6
+#define BM_EMI_CTRL_MEM_WIDTH           0x40
+#define BF_EMI_CTRL_MEM_WIDTH(v)        (((v) << 6) & 0x40)
+#define BP_EMI_CTRL_WRITE_PROTECT       5
+#define BM_EMI_CTRL_WRITE_PROTECT       0x20
+#define BF_EMI_CTRL_WRITE_PROTECT(v)    (((v) << 5) & 0x20)
+#define BP_EMI_CTRL_RESET_OUT           4
+#define BM_EMI_CTRL_RESET_OUT           0x10
+#define BF_EMI_CTRL_RESET_OUT(v)        (((v) << 4) & 0x10)
+#define BP_EMI_CTRL_CE_SELECT           0
+#define BM_EMI_CTRL_CE_SELECT           0xf
+#define BV_EMI_CTRL_CE_SELECT__NONE     0x0
+#define BV_EMI_CTRL_CE_SELECT__CE0      0x1
+#define BV_EMI_CTRL_CE_SELECT__CE1      0x2
+#define BV_EMI_CTRL_CE_SELECT__CE2      0x4
+#define BV_EMI_CTRL_CE_SELECT__CE3      0x8
+#define BF_EMI_CTRL_CE_SELECT(v)        (((v) << 0) & 0xf)
+#define BF_EMI_CTRL_CE_SELECT_V(v)      ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_EMI_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_EMI_STAT                         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10))
+#define BP_EMI_STAT_DRAM_PRESENT            31
+#define BM_EMI_STAT_DRAM_PRESENT            0x80000000
+#define BF_EMI_STAT_DRAM_PRESENT(v)         (((v) << 31) & 0x80000000)
+#define BP_EMI_STAT_NOR_PRESENT             30
+#define BM_EMI_STAT_NOR_PRESENT             0x40000000
+#define BF_EMI_STAT_NOR_PRESENT(v)          (((v) << 30) & 0x40000000)
+#define BP_EMI_STAT_LARGE_DRAM_ENABLED      29
+#define BM_EMI_STAT_LARGE_DRAM_ENABLED      0x20000000
+#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)   (((v) << 29) & 0x20000000)
+#define BP_EMI_STAT_DRAM_HALTED             1
+#define BM_EMI_STAT_DRAM_HALTED             0x2
+#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
+#define BV_EMI_STAT_DRAM_HALTED__HALTED     0x1
+#define BF_EMI_STAT_DRAM_HALTED(v)          (((v) << 1) & 0x2)
+#define BF_EMI_STAT_DRAM_HALTED_V(v)        ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2)
+#define BP_EMI_STAT_NOR_BUSY                0
+#define BM_EMI_STAT_NOR_BUSY                0x1
+#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY      0x0
+#define BV_EMI_STAT_NOR_BUSY__BUSY          0x1
+#define BF_EMI_STAT_NOR_BUSY(v)             (((v) << 0) & 0x1)
+#define BF_EMI_STAT_NOR_BUSY_V(v)           ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1)
+
+/**
+ * Register: HW_EMI_TIME
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_EMI_TIME         (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0))
+#define HW_EMI_TIME_SET     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4))
+#define HW_EMI_TIME_CLR     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8))
+#define HW_EMI_TIME_TOG     (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc))
+#define BP_EMI_TIME_THZ     24
+#define BM_EMI_TIME_THZ     0xf000000
+#define BF_EMI_TIME_THZ(v)  (((v) << 24) & 0xf000000)
+#define BP_EMI_TIME_TDH     16
+#define BM_EMI_TIME_TDH     0xf0000
+#define BF_EMI_TIME_TDH(v)  (((v) << 16) & 0xf0000)
+#define BP_EMI_TIME_TDS     8
+#define BM_EMI_TIME_TDS     0x1f00
+#define BF_EMI_TIME_TDS(v)  (((v) << 8) & 0x1f00)
+#define BP_EMI_TIME_TAS     0
+#define BM_EMI_TIME_TAS     0xf
+#define BF_EMI_TIME_TAS(v)  (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_CSR
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_EMI_DDR_TEST_MODE_CSR            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0))
+#define HW_EMI_DDR_TEST_MODE_CSR_SET        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4))
+#define HW_EMI_DDR_TEST_MODE_CSR_CLR        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8))
+#define HW_EMI_DDR_TEST_MODE_CSR_TOG        (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc))
+#define BP_EMI_DDR_TEST_MODE_CSR_DONE       1
+#define BM_EMI_DDR_TEST_MODE_CSR_DONE       0x2
+#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v)    (((v) << 1) & 0x2)
+#define BP_EMI_DDR_TEST_MODE_CSR_START      0
+#define BM_EMI_DDR_TEST_MODE_CSR_START      0x1
+#define BF_EMI_DDR_TEST_MODE_CSR_START(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_EMI_DEBUG
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_EMI_DEBUG                (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80))
+#define BP_EMI_DEBUG_NOR_STATE      0
+#define BM_EMI_DEBUG_NOR_STATE      0xf
+#define BF_EMI_DEBUG_NOR_STATE(v)   (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS0
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS0            (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90))
+#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0
+#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0      0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS1
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS1            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0))
+#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0
+#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1      0x1fff
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)   (((v) << 0) & 0x1fff)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS2
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS2            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0))
+#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0      0
+#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0      0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_EMI_DDR_TEST_MODE_STATUS3
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_EMI_DDR_TEST_MODE_STATUS3            (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0))
+#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1      0
+#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1      0xffffffff
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_EMI_VERSION
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_EMI_VERSION          (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0))
+#define BP_EMI_VERSION_MAJOR    24
+#define BM_EMI_VERSION_MAJOR    0xff000000
+#define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_EMI_VERSION_MINOR    16
+#define BM_EMI_VERSION_MINOR    0xff0000
+#define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_EMI_VERSION_STEP     0
+#define BM_EMI_VERSION_STEP     0xffff
+#define BF_EMI_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__EMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h
new file mode 100644
index 0000000000..a872606da4
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h
@@ -0,0 +1,355 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__GPIOMON__H__
+#define __HEADERGEN__STMP3700__GPIOMON__H__
+
+#define REGS_GPIOMON_BASE (0x8003c300)
+
+#define REGS_GPIOMON_VERSION "3.2.0"
+
+/**
+ * Register: HW_GPIOMON_BANK0_DATAIN
+ * Address: 0
+ * SCT: no
+*/
+#define HW_GPIOMON_BANK0_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x0))
+#define BP_GPIOMON_BANK0_DATAIN_DATA    0
+#define BM_GPIOMON_BANK0_DATAIN_DATA    0xffffffff
+#define BF_GPIOMON_BANK0_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK1_DATAIN
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_GPIOMON_BANK1_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x10))
+#define BP_GPIOMON_BANK1_DATAIN_DATA    0
+#define BM_GPIOMON_BANK1_DATAIN_DATA    0xffffffff
+#define BF_GPIOMON_BANK1_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK2_DATAIN
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_GPIOMON_BANK2_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x20))
+#define BP_GPIOMON_BANK2_DATAIN_DATA    0
+#define BM_GPIOMON_BANK2_DATAIN_DATA    0xffffffff
+#define BF_GPIOMON_BANK2_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK3_DATAIN
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_GPIOMON_BANK3_DATAIN         (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x30))
+#define BP_GPIOMON_BANK3_DATAIN_DATA    0
+#define BM_GPIOMON_BANK3_DATAIN_DATA    0xffffffff
+#define BF_GPIOMON_BANK3_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK0_DATAOUT
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK0_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x0))
+#define HW_GPIOMON_BANK0_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x4))
+#define HW_GPIOMON_BANK0_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x8))
+#define HW_GPIOMON_BANK0_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0xc))
+#define BP_GPIOMON_BANK0_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK0_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK0_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK1_DATAOUT
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK1_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x0))
+#define HW_GPIOMON_BANK1_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x4))
+#define HW_GPIOMON_BANK1_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x8))
+#define HW_GPIOMON_BANK1_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0xc))
+#define BP_GPIOMON_BANK1_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK1_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK1_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK2_DATAOUT
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK2_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x0))
+#define HW_GPIOMON_BANK2_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x4))
+#define HW_GPIOMON_BANK2_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x8))
+#define HW_GPIOMON_BANK2_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0xc))
+#define BP_GPIOMON_BANK2_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK2_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK2_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK3_DATAOUT
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK3_DATAOUT            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x0))
+#define HW_GPIOMON_BANK3_DATAOUT_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x4))
+#define HW_GPIOMON_BANK3_DATAOUT_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x8))
+#define HW_GPIOMON_BANK3_DATAOUT_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0xc))
+#define BP_GPIOMON_BANK3_DATAOUT_DATA       0
+#define BM_GPIOMON_BANK3_DATAOUT_DATA       0xffffffff
+#define BF_GPIOMON_BANK3_DATAOUT_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK0_DATAOEN
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK0_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x0))
+#define HW_GPIOMON_BANK0_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x4))
+#define HW_GPIOMON_BANK0_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x8))
+#define HW_GPIOMON_BANK0_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0xc))
+#define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES     0
+#define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES     0xffffffff
+#define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK1_DATAOEN
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK1_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x0))
+#define HW_GPIOMON_BANK1_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x4))
+#define HW_GPIOMON_BANK1_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x8))
+#define HW_GPIOMON_BANK1_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0xc))
+#define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES     0
+#define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES     0xffffffff
+#define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK2_DATAOEN
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK2_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x0))
+#define HW_GPIOMON_BANK2_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x4))
+#define HW_GPIOMON_BANK2_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x8))
+#define HW_GPIOMON_BANK2_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0xc))
+#define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES     0
+#define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES     0xffffffff
+#define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_BANK3_DATAOEN
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_GPIOMON_BANK3_DATAOEN                    (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x0))
+#define HW_GPIOMON_BANK3_DATAOEN_SET                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x4))
+#define HW_GPIOMON_BANK3_DATAOEN_CLR                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x8))
+#define HW_GPIOMON_BANK3_DATAOEN_TOG                (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0xc))
+#define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES     0
+#define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES     0xffffffff
+#define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_CTRL
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_GPIOMON_CTRL                     (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x0))
+#define HW_GPIOMON_CTRL_SET                 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x4))
+#define HW_GPIOMON_CTRL_CLR                 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x8))
+#define HW_GPIOMON_CTRL_TOG                 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0xc))
+#define BP_GPIOMON_CTRL_RSRVD               4
+#define BM_GPIOMON_CTRL_RSRVD               0xfffffff0
+#define BF_GPIOMON_CTRL_RSRVD(v)            (((v) << 4) & 0xfffffff0)
+#define BP_GPIOMON_CTRL_PINMUX_ALT_RESET    3
+#define BM_GPIOMON_CTRL_PINMUX_ALT_RESET    0x8
+#define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v) (((v) << 3) & 0x8)
+#define BP_GPIOMON_CTRL_OEN_8MA             2
+#define BM_GPIOMON_CTRL_OEN_8MA             0x4
+#define BF_GPIOMON_CTRL_OEN_8MA(v)          (((v) << 2) & 0x4)
+#define BP_GPIOMON_CTRL_OEN_4MA             1
+#define BM_GPIOMON_CTRL_OEN_4MA             0x2
+#define BF_GPIOMON_CTRL_OEN_4MA(v)          (((v) << 1) & 0x2)
+#define BP_GPIOMON_CTRL_OEN_NAND            0
+#define BM_GPIOMON_CTRL_OEN_NAND            0x1
+#define BF_GPIOMON_CTRL_OEN_NAND(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_GPIOMON_ALT1_PINMUX_BANK0
+ * Address: 0xd0
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT1_PINMUX_BANK0            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x0))
+#define HW_GPIOMON_ALT1_PINMUX_BANK0_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x4))
+#define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x8))
+#define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0xc))
+#define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX      0
+#define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX      0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT1_PINMUX_BANK1
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT1_PINMUX_BANK1            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x0))
+#define HW_GPIOMON_ALT1_PINMUX_BANK1_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x4))
+#define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x8))
+#define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0xc))
+#define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX      0
+#define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX      0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT1_PINMUX_BANK2
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT1_PINMUX_BANK2            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x0))
+#define HW_GPIOMON_ALT1_PINMUX_BANK2_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x4))
+#define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x8))
+#define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0xc))
+#define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX      0
+#define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX      0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT1_PINMUX_BANK3
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT1_PINMUX_BANK3            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x0))
+#define HW_GPIOMON_ALT1_PINMUX_BANK3_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x4))
+#define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x8))
+#define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0xc))
+#define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX      0
+#define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX      0xffffffff
+#define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT2_PINMUX_BANK0
+ * Address: 0x110
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT2_PINMUX_BANK0            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x0))
+#define HW_GPIOMON_ALT2_PINMUX_BANK0_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x4))
+#define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x8))
+#define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0xc))
+#define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX      0
+#define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX      0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT2_PINMUX_BANK1
+ * Address: 0x120
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT2_PINMUX_BANK1            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x0))
+#define HW_GPIOMON_ALT2_PINMUX_BANK1_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x4))
+#define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x8))
+#define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0xc))
+#define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX      0
+#define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX      0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT2_PINMUX_BANK2
+ * Address: 0x130
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT2_PINMUX_BANK2            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x0))
+#define HW_GPIOMON_ALT2_PINMUX_BANK2_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x4))
+#define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x8))
+#define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0xc))
+#define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX      0
+#define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX      0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT2_PINMUX_BANK3
+ * Address: 0x140
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT2_PINMUX_BANK3            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x0))
+#define HW_GPIOMON_ALT2_PINMUX_BANK3_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x4))
+#define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x8))
+#define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0xc))
+#define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX      0
+#define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX      0xffffffff
+#define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT3_PINMUX_BANK0
+ * Address: 0x150
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT3_PINMUX_BANK0            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x0))
+#define HW_GPIOMON_ALT3_PINMUX_BANK0_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x4))
+#define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x8))
+#define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0xc))
+#define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX      0
+#define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX      0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT3_PINMUX_BANK1
+ * Address: 0x160
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT3_PINMUX_BANK1            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x0))
+#define HW_GPIOMON_ALT3_PINMUX_BANK1_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x4))
+#define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x8))
+#define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0xc))
+#define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX      0
+#define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX      0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT3_PINMUX_BANK2
+ * Address: 0x170
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT3_PINMUX_BANK2            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x0))
+#define HW_GPIOMON_ALT3_PINMUX_BANK2_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x4))
+#define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x8))
+#define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0xc))
+#define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX      0
+#define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX      0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPIOMON_ALT3_PINMUX_BANK3
+ * Address: 0x180
+ * SCT: yes
+*/
+#define HW_GPIOMON_ALT3_PINMUX_BANK3            (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x0))
+#define HW_GPIOMON_ALT3_PINMUX_BANK3_SET        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x4))
+#define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x8))
+#define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG        (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0xc))
+#define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX      0
+#define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX      0xffffffff
+#define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v)   (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3700__GPIOMON__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h
new file mode 100644
index 0000000000..d8dcb3b5cf
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h
@@ -0,0 +1,461 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__GPMI__H__
+#define __HEADERGEN__STMP3700__GPMI__H__
+
+#define REGS_GPMI_BASE (0x8000c000)
+
+#define REGS_GPMI_VERSION "3.2.0"
+
+/**
+ * Register: HW_GPMI_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL0                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
+#define HW_GPMI_CTRL0_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
+#define HW_GPMI_CTRL0_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
+#define HW_GPMI_CTRL0_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
+#define BP_GPMI_CTRL0_SFTRST                            31
+#define BM_GPMI_CTRL0_SFTRST                            0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN                       0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET                     0x1
+#define BF_GPMI_CTRL0_SFTRST(v)                         (((v) << 31) & 0x80000000)
+#define BF_GPMI_CTRL0_SFTRST_V(v)                       ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
+#define BP_GPMI_CTRL0_CLKGATE                           30
+#define BM_GPMI_CTRL0_CLKGATE                           0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN                      0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS                  0x1
+#define BF_GPMI_CTRL0_CLKGATE(v)                        (((v) << 30) & 0x40000000)
+#define BF_GPMI_CTRL0_CLKGATE_V(v)                      ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
+#define BP_GPMI_CTRL0_RUN                               29
+#define BM_GPMI_CTRL0_RUN                               0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE                         0x0
+#define BV_GPMI_CTRL0_RUN__BUSY                         0x1
+#define BF_GPMI_CTRL0_RUN(v)                            (((v) << 29) & 0x20000000)
+#define BF_GPMI_CTRL0_RUN_V(v)                          ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
+#define BP_GPMI_CTRL0_DEV_IRQ_EN                        28
+#define BM_GPMI_CTRL0_DEV_IRQ_EN                        0x10000000
+#define BF_GPMI_CTRL0_DEV_IRQ_EN(v)                     (((v) << 28) & 0x10000000)
+#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN                    27
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN                    0x8000000
+#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v)                 (((v) << 27) & 0x8000000)
+#define BP_GPMI_CTRL0_UDMA                              26
+#define BM_GPMI_CTRL0_UDMA                              0x4000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED                    0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED                     0x1
+#define BF_GPMI_CTRL0_UDMA(v)                           (((v) << 26) & 0x4000000)
+#define BF_GPMI_CTRL0_UDMA_V(v)                         ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
+#define BP_GPMI_CTRL0_COMMAND_MODE                      24
+#define BM_GPMI_CTRL0_COMMAND_MODE                      0x3000000
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE               0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ                0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE    0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY      0x3
+#define BF_GPMI_CTRL0_COMMAND_MODE(v)                   (((v) << 24) & 0x3000000)
+#define BF_GPMI_CTRL0_COMMAND_MODE_V(v)                 ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
+#define BP_GPMI_CTRL0_WORD_LENGTH                       23
+#define BM_GPMI_CTRL0_WORD_LENGTH                       0x800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT               0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT                0x1
+#define BF_GPMI_CTRL0_WORD_LENGTH(v)                    (((v) << 23) & 0x800000)
+#define BF_GPMI_CTRL0_WORD_LENGTH_V(v)                  ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
+#define BP_GPMI_CTRL0_LOCK_CS                           22
+#define BM_GPMI_CTRL0_LOCK_CS                           0x400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED                 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED                  0x1
+#define BF_GPMI_CTRL0_LOCK_CS(v)                        (((v) << 22) & 0x400000)
+#define BF_GPMI_CTRL0_LOCK_CS_V(v)                      ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
+#define BP_GPMI_CTRL0_CS                                20
+#define BM_GPMI_CTRL0_CS                                0x300000
+#define BF_GPMI_CTRL0_CS(v)                             (((v) << 20) & 0x300000)
+#define BP_GPMI_CTRL0_ADDRESS                           17
+#define BM_GPMI_CTRL0_ADDRESS                           0xe0000
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA                0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE                 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE                 0x2
+#define BF_GPMI_CTRL0_ADDRESS(v)                        (((v) << 17) & 0xe0000)
+#define BF_GPMI_CTRL0_ADDRESS_V(v)                      ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
+#define BP_GPMI_CTRL0_ADDRESS_INCREMENT                 16
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT                 0x10000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED       0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED        0x1
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v)              (((v) << 16) & 0x10000)
+#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v)            ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
+#define BP_GPMI_CTRL0_XFER_COUNT                        0
+#define BM_GPMI_CTRL0_XFER_COUNT                        0xffff
+#define BF_GPMI_CTRL0_XFER_COUNT(v)                     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_COMPARE
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_GPMI_COMPARE                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
+#define BP_GPMI_COMPARE_MASK            16
+#define BM_GPMI_COMPARE_MASK            0xffff0000
+#define BF_GPMI_COMPARE_MASK(v)         (((v) << 16) & 0xffff0000)
+#define BP_GPMI_COMPARE_REFERENCE       0
+#define BM_GPMI_COMPARE_REFERENCE       0xffff
+#define BF_GPMI_COMPARE_REFERENCE(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_ECCCTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_GPMI_ECCCTRL                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
+#define HW_GPMI_ECCCTRL_SET                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
+#define HW_GPMI_ECCCTRL_CLR                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
+#define HW_GPMI_ECCCTRL_TOG                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
+#define BP_GPMI_ECCCTRL_HANDLE                  16
+#define BM_GPMI_ECCCTRL_HANDLE                  0xffff0000
+#define BF_GPMI_ECCCTRL_HANDLE(v)               (((v) << 16) & 0xffff0000)
+#define BP_GPMI_ECCCTRL_ECC_CMD                 13
+#define BM_GPMI_ECCCTRL_ECC_CMD                 0x6000
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT   0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT   0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT   0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT   0x3
+#define BF_GPMI_ECCCTRL_ECC_CMD(v)              (((v) << 13) & 0x6000)
+#define BF_GPMI_ECCCTRL_ECC_CMD_V(v)            ((BV_GPMI_ECCCTRL_ECC_CMD__##v << 13) & 0x6000)
+#define BP_GPMI_ECCCTRL_ENABLE_ECC              12
+#define BM_GPMI_ECCCTRL_ENABLE_ECC              0x1000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE      0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE     0x0
+#define BF_GPMI_ECCCTRL_ENABLE_ECC(v)           (((v) << 12) & 0x1000)
+#define BF_GPMI_ECCCTRL_ENABLE_ECC_V(v)         ((BV_GPMI_ECCCTRL_ENABLE_ECC__##v << 12) & 0x1000)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK             0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK             0x1ff
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY  0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7    0x80
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6    0x40
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5    0x20
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4    0x10
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3    0x8
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2    0x4
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1    0x2
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0    0x1
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v)          (((v) << 0) & 0x1ff)
+#define BF_GPMI_ECCCTRL_BUFFER_MASK_V(v)        ((BV_GPMI_ECCCTRL_BUFFER_MASK__##v << 0) & 0x1ff)
+
+/**
+ * Register: HW_GPMI_ECCCOUNT
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_GPMI_ECCCOUNT            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
+#define BP_GPMI_ECCCOUNT_COUNT      0
+#define BM_GPMI_ECCCOUNT_COUNT      0xffff
+#define BF_GPMI_ECCCOUNT_COUNT(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_GPMI_PAYLOAD
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_GPMI_PAYLOAD             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
+#define BP_GPMI_PAYLOAD_ADDRESS     2
+#define BM_GPMI_PAYLOAD_ADDRESS     0xfffffffc
+#define BF_GPMI_PAYLOAD_ADDRESS(v)  (((v) << 2) & 0xfffffffc)
+
+/**
+ * Register: HW_GPMI_AUXILIARY
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_GPMI_AUXILIARY               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
+#define BP_GPMI_AUXILIARY_ADDRESS       2
+#define BM_GPMI_AUXILIARY_ADDRESS       0xfffffffc
+#define BF_GPMI_AUXILIARY_ADDRESS(v)    (((v) << 2) & 0xfffffffc)
+
+/**
+ * Register: HW_GPMI_CTRL1
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_GPMI_CTRL1                                   (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x0))
+#define HW_GPMI_CTRL1_SET                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x4))
+#define HW_GPMI_CTRL1_CLR                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x8))
+#define HW_GPMI_CTRL1_TOG                               (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0xc))
+#define BP_GPMI_CTRL1_DSAMPLE_TIME                      12
+#define BM_GPMI_CTRL1_DSAMPLE_TIME                      0x7000
+#define BF_GPMI_CTRL1_DSAMPLE_TIME(v)                   (((v) << 12) & 0x7000)
+#define BP_GPMI_CTRL1_DMA2ECC_MODE                      11
+#define BM_GPMI_CTRL1_DMA2ECC_MODE                      0x800
+#define BF_GPMI_CTRL1_DMA2ECC_MODE(v)                   (((v) << 11) & 0x800)
+#define BP_GPMI_CTRL1_DEV_IRQ                           10
+#define BM_GPMI_CTRL1_DEV_IRQ                           0x400
+#define BF_GPMI_CTRL1_DEV_IRQ(v)                        (((v) << 10) & 0x400)
+#define BP_GPMI_CTRL1_TIMEOUT_IRQ                       9
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ                       0x200
+#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v)                    (((v) << 9) & 0x200)
+#define BP_GPMI_CTRL1_BURST_EN                          8
+#define BM_GPMI_CTRL1_BURST_EN                          0x100
+#define BF_GPMI_CTRL1_BURST_EN(v)                       (((v) << 8) & 0x100)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             7
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3             0x80
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v)          (((v) << 7) & 0x80)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             6
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2             0x40
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v)          (((v) << 6) & 0x40)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             5
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1             0x20
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v)          (((v) << 5) & 0x20)
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0             0x10
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v)          (((v) << 4) & 0x10)
+#define BP_GPMI_CTRL1_DEV_RESET                         3
+#define BM_GPMI_CTRL1_DEV_RESET                         0x8
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED                0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED               0x1
+#define BF_GPMI_CTRL1_DEV_RESET(v)                      (((v) << 3) & 0x8)
+#define BF_GPMI_CTRL1_DEV_RESET_V(v)                    ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
+#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY               2
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY               0x4
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW    0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH   0x1
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v)            (((v) << 2) & 0x4)
+#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v)          ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
+#define BP_GPMI_CTRL1_CAMERA_MODE                       1
+#define BM_GPMI_CTRL1_CAMERA_MODE                       0x2
+#define BF_GPMI_CTRL1_CAMERA_MODE(v)                    (((v) << 1) & 0x2)
+#define BP_GPMI_CTRL1_GPMI_MODE                         0
+#define BM_GPMI_CTRL1_GPMI_MODE                         0x1
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND                   0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA                    0x1
+#define BF_GPMI_CTRL1_GPMI_MODE(v)                      (((v) << 0) & 0x1)
+#define BF_GPMI_CTRL1_GPMI_MODE_V(v)                    ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
+
+/**
+ * Register: HW_GPMI_TIMING0
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_GPMI_TIMING0                     (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
+#define BP_GPMI_TIMING0_ADDRESS_SETUP       16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP       0xff0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING0_DATA_HOLD           8
+#define BM_GPMI_TIMING0_DATA_HOLD           0xff00
+#define BF_GPMI_TIMING0_DATA_HOLD(v)        (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING0_DATA_SETUP          0
+#define BM_GPMI_TIMING0_DATA_SETUP          0xff
+#define BF_GPMI_TIMING0_DATA_SETUP(v)       (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_GPMI_TIMING1
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_GPMI_TIMING1                         (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT     0xffff0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v)  (((v) << 16) & 0xffff0000)
+
+/**
+ * Register: HW_GPMI_TIMING2
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_GPMI_TIMING2                 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x90))
+#define BP_GPMI_TIMING2_UDMA_TRP        24
+#define BM_GPMI_TIMING2_UDMA_TRP        0xff000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v)     (((v) << 24) & 0xff000000)
+#define BP_GPMI_TIMING2_UDMA_ENV        16
+#define BM_GPMI_TIMING2_UDMA_ENV        0xff0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v)     (((v) << 16) & 0xff0000)
+#define BP_GPMI_TIMING2_UDMA_HOLD       8
+#define BM_GPMI_TIMING2_UDMA_HOLD       0xff00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_GPMI_TIMING2_UDMA_SETUP      0
+#define BM_GPMI_TIMING2_UDMA_SETUP      0xff
+#define BF_GPMI_TIMING2_UDMA_SETUP(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_GPMI_DATA
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_GPMI_DATA            (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xa0))
+#define BP_GPMI_DATA_DATA       0
+#define BM_GPMI_DATA_DATA       0xffffffff
+#define BF_GPMI_DATA_DATA(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_GPMI_STAT
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_GPMI_STAT                        (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xb0))
+#define BP_GPMI_STAT_PRESENT                31
+#define BM_GPMI_STAT_PRESENT                0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE   0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE     0x1
+#define BF_GPMI_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
+#define BF_GPMI_STAT_PRESENT_V(v)           ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_GPMI_STAT_RDY_TIMEOUT            8
+#define BM_GPMI_STAT_RDY_TIMEOUT            0xf00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v)         (((v) << 8) & 0xf00)
+#define BP_GPMI_STAT_ATA_IRQ                7
+#define BM_GPMI_STAT_ATA_IRQ                0x80
+#define BF_GPMI_STAT_ATA_IRQ(v)             (((v) << 7) & 0x80)
+#define BP_GPMI_STAT_INVALID_BUFFER_MASK    6
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK    0x40
+#define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & 0x40)
+#define BP_GPMI_STAT_FIFO_EMPTY             5
+#define BM_GPMI_STAT_FIFO_EMPTY             0x20
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY  0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY      0x1
+#define BF_GPMI_STAT_FIFO_EMPTY(v)          (((v) << 5) & 0x20)
+#define BF_GPMI_STAT_FIFO_EMPTY_V(v)        ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
+#define BP_GPMI_STAT_FIFO_FULL              4
+#define BM_GPMI_STAT_FIFO_FULL              0x10
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL    0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL        0x1
+#define BF_GPMI_STAT_FIFO_FULL(v)           (((v) << 4) & 0x10)
+#define BF_GPMI_STAT_FIFO_FULL_V(v)         ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
+#define BP_GPMI_STAT_DEV3_ERROR             3
+#define BM_GPMI_STAT_DEV3_ERROR             0x8
+#define BF_GPMI_STAT_DEV3_ERROR(v)          (((v) << 3) & 0x8)
+#define BP_GPMI_STAT_DEV2_ERROR             2
+#define BM_GPMI_STAT_DEV2_ERROR             0x4
+#define BF_GPMI_STAT_DEV2_ERROR(v)          (((v) << 2) & 0x4)
+#define BP_GPMI_STAT_DEV1_ERROR             1
+#define BM_GPMI_STAT_DEV1_ERROR             0x2
+#define BF_GPMI_STAT_DEV1_ERROR(v)          (((v) << 1) & 0x2)
+#define BP_GPMI_STAT_DEV0_ERROR             0
+#define BM_GPMI_STAT_DEV0_ERROR             0x1
+#define BF_GPMI_STAT_DEV0_ERROR(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_GPMI_DEBUG
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_GPMI_DEBUG                           (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xc0))
+#define BP_GPMI_DEBUG_READY3                    31
+#define BM_GPMI_DEBUG_READY3                    0x80000000
+#define BF_GPMI_DEBUG_READY3(v)                 (((v) << 31) & 0x80000000)
+#define BP_GPMI_DEBUG_READY2                    30
+#define BM_GPMI_DEBUG_READY2                    0x40000000
+#define BF_GPMI_DEBUG_READY2(v)                 (((v) << 30) & 0x40000000)
+#define BP_GPMI_DEBUG_READY1                    29
+#define BM_GPMI_DEBUG_READY1                    0x20000000
+#define BF_GPMI_DEBUG_READY1(v)                 (((v) << 29) & 0x20000000)
+#define BP_GPMI_DEBUG_READY0                    28
+#define BM_GPMI_DEBUG_READY0                    0x10000000
+#define BF_GPMI_DEBUG_READY0(v)                 (((v) << 28) & 0x10000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3       27
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3       0x8000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v)    (((v) << 27) & 0x8000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2       26
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2       0x4000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v)    (((v) << 26) & 0x4000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1       25
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1       0x2000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v)    (((v) << 25) & 0x2000000)
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0       24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0       0x1000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v)    (((v) << 24) & 0x1000000)
+#define BP_GPMI_DEBUG_SENSE3                    23
+#define BM_GPMI_DEBUG_SENSE3                    0x800000
+#define BF_GPMI_DEBUG_SENSE3(v)                 (((v) << 23) & 0x800000)
+#define BP_GPMI_DEBUG_SENSE2                    22
+#define BM_GPMI_DEBUG_SENSE2                    0x400000
+#define BF_GPMI_DEBUG_SENSE2(v)                 (((v) << 22) & 0x400000)
+#define BP_GPMI_DEBUG_SENSE1                    21
+#define BM_GPMI_DEBUG_SENSE1                    0x200000
+#define BF_GPMI_DEBUG_SENSE1(v)                 (((v) << 21) & 0x200000)
+#define BP_GPMI_DEBUG_SENSE0                    20
+#define BM_GPMI_DEBUG_SENSE0                    0x100000
+#define BF_GPMI_DEBUG_SENSE0(v)                 (((v) << 20) & 0x100000)
+#define BP_GPMI_DEBUG_DMAREQ3                   19
+#define BM_GPMI_DEBUG_DMAREQ3                   0x80000
+#define BF_GPMI_DEBUG_DMAREQ3(v)                (((v) << 19) & 0x80000)
+#define BP_GPMI_DEBUG_DMAREQ2                   18
+#define BM_GPMI_DEBUG_DMAREQ2                   0x40000
+#define BF_GPMI_DEBUG_DMAREQ2(v)                (((v) << 18) & 0x40000)
+#define BP_GPMI_DEBUG_DMAREQ1                   17
+#define BM_GPMI_DEBUG_DMAREQ1                   0x20000
+#define BF_GPMI_DEBUG_DMAREQ1(v)                (((v) << 17) & 0x20000)
+#define BP_GPMI_DEBUG_DMAREQ0                   16
+#define BM_GPMI_DEBUG_DMAREQ0                   0x10000
+#define BF_GPMI_DEBUG_DMAREQ0(v)                (((v) << 16) & 0x10000)
+#define BP_GPMI_DEBUG_CMD_END                   12
+#define BM_GPMI_DEBUG_CMD_END                   0xf000
+#define BF_GPMI_DEBUG_CMD_END(v)                (((v) << 12) & 0xf000)
+#define BP_GPMI_DEBUG_UDMA_STATE                8
+#define BM_GPMI_DEBUG_UDMA_STATE                0xf00
+#define BF_GPMI_DEBUG_UDMA_STATE(v)             (((v) << 8) & 0xf00)
+#define BP_GPMI_DEBUG_BUSY                      7
+#define BM_GPMI_DEBUG_BUSY                      0x80
+#define BV_GPMI_DEBUG_BUSY__DISABLED            0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED             0x1
+#define BF_GPMI_DEBUG_BUSY(v)                   (((v) << 7) & 0x80)
+#define BF_GPMI_DEBUG_BUSY_V(v)                 ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
+#define BP_GPMI_DEBUG_PIN_STATE                 4
+#define BM_GPMI_DEBUG_PIN_STATE                 0x70
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE       0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT     0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR       0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL      0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE     0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY     0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD      0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE       0x7
+#define BF_GPMI_DEBUG_PIN_STATE(v)              (((v) << 4) & 0x70)
+#define BF_GPMI_DEBUG_PIN_STATE_V(v)            ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
+#define BP_GPMI_DEBUG_MAIN_STATE                0
+#define BM_GPMI_DEBUG_MAIN_STATE                0xf
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE      0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT    0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE    0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR    0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ    0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK    0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF    0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO    0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR    0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP     0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE      0xa
+#define BF_GPMI_DEBUG_MAIN_STATE(v)             (((v) << 0) & 0xf)
+#define BF_GPMI_DEBUG_MAIN_STATE_V(v)           ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
+
+/**
+ * Register: HW_GPMI_VERSION
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_GPMI_VERSION             (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xd0))
+#define BP_GPMI_VERSION_MAJOR       24
+#define BM_GPMI_VERSION_MAJOR       0xff000000
+#define BF_GPMI_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_GPMI_VERSION_MINOR       16
+#define BM_GPMI_VERSION_MINOR       0xff0000
+#define BF_GPMI_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_GPMI_VERSION_STEP        0
+#define BM_GPMI_VERSION_STEP        0xffff
+#define BF_GPMI_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__GPMI__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h
new file mode 100644
index 0000000000..ea34d27db2
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h
@@ -0,0 +1,537 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__I2C__H__
+#define __HEADERGEN__STMP3700__I2C__H__
+
+#define REGS_I2C_BASE (0x80058000)
+
+#define REGS_I2C_VERSION "3.2.0"
+
+/**
+ * Register: HW_I2C_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_I2C_CTRL0                                (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0))
+#define HW_I2C_CTRL0_SET                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4))
+#define HW_I2C_CTRL0_CLR                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8))
+#define HW_I2C_CTRL0_TOG                            (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc))
+#define BP_I2C_CTRL0_SFTRST                         31
+#define BM_I2C_CTRL0_SFTRST                         0x80000000
+#define BV_I2C_CTRL0_SFTRST__RUN                    0x0
+#define BV_I2C_CTRL0_SFTRST__RESET                  0x1
+#define BF_I2C_CTRL0_SFTRST(v)                      (((v) << 31) & 0x80000000)
+#define BF_I2C_CTRL0_SFTRST_V(v)                    ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000)
+#define BP_I2C_CTRL0_CLKGATE                        30
+#define BM_I2C_CTRL0_CLKGATE                        0x40000000
+#define BV_I2C_CTRL0_CLKGATE__RUN                   0x0
+#define BV_I2C_CTRL0_CLKGATE__NO_CLKS               0x1
+#define BF_I2C_CTRL0_CLKGATE(v)                     (((v) << 30) & 0x40000000)
+#define BF_I2C_CTRL0_CLKGATE_V(v)                   ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000)
+#define BP_I2C_CTRL0_RUN                            29
+#define BM_I2C_CTRL0_RUN                            0x20000000
+#define BV_I2C_CTRL0_RUN__HALT                      0x0
+#define BV_I2C_CTRL0_RUN__RUN                       0x1
+#define BF_I2C_CTRL0_RUN(v)                         (((v) << 29) & 0x20000000)
+#define BF_I2C_CTRL0_RUN_V(v)                       ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000)
+#define BP_I2C_CTRL0_PRE_ACK                        27
+#define BM_I2C_CTRL0_PRE_ACK                        0x8000000
+#define BF_I2C_CTRL0_PRE_ACK(v)                     (((v) << 27) & 0x8000000)
+#define BP_I2C_CTRL0_ACKNOWLEDGE                    26
+#define BM_I2C_CTRL0_ACKNOWLEDGE                    0x4000000
+#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK              0x0
+#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK               0x1
+#define BF_I2C_CTRL0_ACKNOWLEDGE(v)                 (((v) << 26) & 0x4000000)
+#define BF_I2C_CTRL0_ACKNOWLEDGE_V(v)               ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000)
+#define BP_I2C_CTRL0_SEND_NAK_ON_LAST               25
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST               0x2000000
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT       0x0
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT       0x1
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v)            (((v) << 25) & 0x2000000)
+#define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v)          ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000)
+#define BP_I2C_CTRL0_PIO_MODE                       24
+#define BM_I2C_CTRL0_PIO_MODE                       0x1000000
+#define BF_I2C_CTRL0_PIO_MODE(v)                    (((v) << 24) & 0x1000000)
+#define BP_I2C_CTRL0_MULTI_MASTER                   23
+#define BM_I2C_CTRL0_MULTI_MASTER                   0x800000
+#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE           0x0
+#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE         0x1
+#define BF_I2C_CTRL0_MULTI_MASTER(v)                (((v) << 23) & 0x800000)
+#define BF_I2C_CTRL0_MULTI_MASTER_V(v)              ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000)
+#define BP_I2C_CTRL0_CLOCK_HELD                     22
+#define BM_I2C_CTRL0_CLOCK_HELD                     0x400000
+#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE            0x0
+#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW           0x1
+#define BF_I2C_CTRL0_CLOCK_HELD(v)                  (((v) << 22) & 0x400000)
+#define BF_I2C_CTRL0_CLOCK_HELD_V(v)                ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000)
+#define BP_I2C_CTRL0_RETAIN_CLOCK                   21
+#define BM_I2C_CTRL0_RETAIN_CLOCK                   0x200000
+#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE          0x0
+#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW         0x1
+#define BF_I2C_CTRL0_RETAIN_CLOCK(v)                (((v) << 21) & 0x200000)
+#define BF_I2C_CTRL0_RETAIN_CLOCK_V(v)              ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000)
+#define BP_I2C_CTRL0_POST_SEND_STOP                 20
+#define BM_I2C_CTRL0_POST_SEND_STOP                 0x100000
+#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP        0x0
+#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP      0x1
+#define BF_I2C_CTRL0_POST_SEND_STOP(v)              (((v) << 20) & 0x100000)
+#define BF_I2C_CTRL0_POST_SEND_STOP_V(v)            ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000)
+#define BP_I2C_CTRL0_PRE_SEND_START                 19
+#define BM_I2C_CTRL0_PRE_SEND_START                 0x80000
+#define BV_I2C_CTRL0_PRE_SEND_START__NO_START       0x0
+#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START     0x1
+#define BF_I2C_CTRL0_PRE_SEND_START(v)              (((v) << 19) & 0x80000)
+#define BF_I2C_CTRL0_PRE_SEND_START_V(v)            ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000)
+#define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           18
+#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE           0x40000
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED  0x1
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v)        (((v) << 18) & 0x40000)
+#define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v)      ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000)
+#define BP_I2C_CTRL0_MASTER_MODE                    17
+#define BM_I2C_CTRL0_MASTER_MODE                    0x20000
+#define BV_I2C_CTRL0_MASTER_MODE__SLAVE             0x0
+#define BV_I2C_CTRL0_MASTER_MODE__MASTER            0x1
+#define BF_I2C_CTRL0_MASTER_MODE(v)                 (((v) << 17) & 0x20000)
+#define BF_I2C_CTRL0_MASTER_MODE_V(v)               ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000)
+#define BP_I2C_CTRL0_DIRECTION                      16
+#define BM_I2C_CTRL0_DIRECTION                      0x10000
+#define BV_I2C_CTRL0_DIRECTION__RECEIVE             0x0
+#define BV_I2C_CTRL0_DIRECTION__TRANSMIT            0x1
+#define BF_I2C_CTRL0_DIRECTION(v)                   (((v) << 16) & 0x10000)
+#define BF_I2C_CTRL0_DIRECTION_V(v)                 ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000)
+#define BP_I2C_CTRL0_XFER_COUNT                     0
+#define BM_I2C_CTRL0_XFER_COUNT                     0xffff
+#define BF_I2C_CTRL0_XFER_COUNT(v)                  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_I2C_TIMING0
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_I2C_TIMING0                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0))
+#define HW_I2C_TIMING0_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4))
+#define HW_I2C_TIMING0_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8))
+#define HW_I2C_TIMING0_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc))
+#define BP_I2C_TIMING0_HIGH_COUNT       16
+#define BM_I2C_TIMING0_HIGH_COUNT       0x3ff0000
+#define BF_I2C_TIMING0_HIGH_COUNT(v)    (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING0_RCV_COUNT        0
+#define BM_I2C_TIMING0_RCV_COUNT        0x3ff
+#define BF_I2C_TIMING0_RCV_COUNT(v)     (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_TIMING1
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_I2C_TIMING1                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0))
+#define HW_I2C_TIMING1_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4))
+#define HW_I2C_TIMING1_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8))
+#define HW_I2C_TIMING1_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc))
+#define BP_I2C_TIMING1_LOW_COUNT        16
+#define BM_I2C_TIMING1_LOW_COUNT        0x3ff0000
+#define BF_I2C_TIMING1_LOW_COUNT(v)     (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING1_XMIT_COUNT       0
+#define BM_I2C_TIMING1_XMIT_COUNT       0x3ff
+#define BF_I2C_TIMING1_XMIT_COUNT(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_TIMING2
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_I2C_TIMING2                  (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0))
+#define HW_I2C_TIMING2_SET              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4))
+#define HW_I2C_TIMING2_CLR              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8))
+#define HW_I2C_TIMING2_TOG              (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc))
+#define BP_I2C_TIMING2_BUS_FREE         16
+#define BM_I2C_TIMING2_BUS_FREE         0x3ff0000
+#define BF_I2C_TIMING2_BUS_FREE(v)      (((v) << 16) & 0x3ff0000)
+#define BP_I2C_TIMING2_LEADIN_COUNT     0
+#define BM_I2C_TIMING2_LEADIN_COUNT     0x3ff
+#define BF_I2C_TIMING2_LEADIN_COUNT(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_CTRL1
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_I2C_CTRL1                                        (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0))
+#define HW_I2C_CTRL1_SET                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4))
+#define HW_I2C_CTRL1_CLR                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8))
+#define HW_I2C_CTRL1_TOG                                    (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc))
+#define BP_I2C_CTRL1_BCAST_SLAVE_EN                         24
+#define BM_I2C_CTRL1_BCAST_SLAVE_EN                         0x1000000
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST               0x0
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST            0x1
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN(v)                      (((v) << 24) & 0x1000000)
+#define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v)                    ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000)
+#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     16
+#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE                     0xff0000
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v)                  (((v) << 16) & 0xff0000)
+#define BP_I2C_CTRL1_BUS_FREE_IRQ_EN                        15
+#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN                        0x8000
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED              0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED               0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v)                     (((v) << 15) & 0x8000)
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v)                   ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000)
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               14
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN               0x4000
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED     0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED      0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v)            (((v) << 14) & 0x4000)
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v)          ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000)
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    13
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN                    0x2000
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED          0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED           0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v)                 (((v) << 13) & 0x2000)
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v)               ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000)
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              12
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN              0x1000
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED    0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED     0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v)           (((v) << 12) & 0x1000)
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v)         ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000)
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN                      11
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN                      0x800
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v)                   (((v) << 11) & 0x800)
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800)
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     10
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN                     0x400
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED           0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED            0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v)                  (((v) << 10) & 0x400)
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v)                ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400)
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      9
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN                      0x200
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED            0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED             0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v)                   (((v) << 9) & 0x200)
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v)                 ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200)
+#define BP_I2C_CTRL1_SLAVE_IRQ_EN                           8
+#define BM_I2C_CTRL1_SLAVE_IRQ_EN                           0x100
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED                 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED                  0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN(v)                        (((v) << 8) & 0x100)
+#define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v)                      ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100)
+#define BP_I2C_CTRL1_BUS_FREE_IRQ                           7
+#define BM_I2C_CTRL1_BUS_FREE_IRQ                           0x80
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST               0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST                  0x1
+#define BF_I2C_CTRL1_BUS_FREE_IRQ(v)                        (((v) << 7) & 0x80)
+#define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v)                      ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80)
+#define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  6
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ                  0x40
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST      0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST         0x1
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v)               (((v) << 6) & 0x40)
+#define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v)             ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40)
+#define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       5
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ                       0x20
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST           0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST              0x1
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v)                    (((v) << 5) & 0x20)
+#define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v)                  ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20)
+#define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 4
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ                 0x10
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST     0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST        0x1
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v)              (((v) << 4) & 0x10)
+#define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v)            ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10)
+#define BP_I2C_CTRL1_EARLY_TERM_IRQ                         3
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ                         0x8
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ(v)                      (((v) << 3) & 0x8)
+#define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v)                    ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8)
+#define BP_I2C_CTRL1_MASTER_LOSS_IRQ                        2
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ                        0x4
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST            0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST               0x1
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v)                     (((v) << 2) & 0x4)
+#define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v)                   ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4)
+#define BP_I2C_CTRL1_SLAVE_STOP_IRQ                         1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ                         0x2
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST             0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST                0x1
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v)                      (((v) << 1) & 0x2)
+#define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v)                    ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2)
+#define BP_I2C_CTRL1_SLAVE_IRQ                              0
+#define BM_I2C_CTRL1_SLAVE_IRQ                              0x1
+#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST                  0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST                     0x1
+#define BF_I2C_CTRL1_SLAVE_IRQ(v)                           (((v) << 0) & 0x1)
+#define BF_I2C_CTRL1_SLAVE_IRQ_V(v)                         ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_STAT
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_I2C_STAT                                             (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50))
+#define BP_I2C_STAT_MASTER_PRESENT                              31
+#define BM_I2C_STAT_MASTER_PRESENT                              0x80000000
+#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE                 0x0
+#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE                   0x1
+#define BF_I2C_STAT_MASTER_PRESENT(v)                           (((v) << 31) & 0x80000000)
+#define BF_I2C_STAT_MASTER_PRESENT_V(v)                         ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000)
+#define BP_I2C_STAT_SLAVE_PRESENT                               30
+#define BM_I2C_STAT_SLAVE_PRESENT                               0x40000000
+#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE                  0x0
+#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE                    0x1
+#define BF_I2C_STAT_SLAVE_PRESENT(v)                            (((v) << 30) & 0x40000000)
+#define BF_I2C_STAT_SLAVE_PRESENT_V(v)                          ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000)
+#define BP_I2C_STAT_ANY_ENABLED_IRQ                             29
+#define BM_I2C_STAT_ANY_ENABLED_IRQ                             0x20000000
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS                0x0
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST       0x1
+#define BF_I2C_STAT_ANY_ENABLED_IRQ(v)                          (((v) << 29) & 0x20000000)
+#define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v)                        ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000)
+#define BP_I2C_STAT_RCVD_SLAVE_ADDR                             16
+#define BM_I2C_STAT_RCVD_SLAVE_ADDR                             0xff0000
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v)                          (((v) << 16) & 0xff0000)
+#define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          15
+#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO                          0x8000
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED        0x0
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO                0x1
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v)                       (((v) << 15) & 0x8000)
+#define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v)                     ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000)
+#define BP_I2C_STAT_SLAVE_FOUND                                 14
+#define BM_I2C_STAT_SLAVE_FOUND                                 0x4000
+#define BV_I2C_STAT_SLAVE_FOUND__IDLE                           0x0
+#define BV_I2C_STAT_SLAVE_FOUND__WAITING                        0x1
+#define BF_I2C_STAT_SLAVE_FOUND(v)                              (((v) << 14) & 0x4000)
+#define BF_I2C_STAT_SLAVE_FOUND_V(v)                            ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000)
+#define BP_I2C_STAT_SLAVE_SEARCHING                             13
+#define BM_I2C_STAT_SLAVE_SEARCHING                             0x2000
+#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE                       0x0
+#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE                     0x1
+#define BF_I2C_STAT_SLAVE_SEARCHING(v)                          (((v) << 13) & 0x2000)
+#define BF_I2C_STAT_SLAVE_SEARCHING_V(v)                        ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000)
+#define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT                        12
+#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT                        0x1000
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE              0x0
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING               0x1
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v)                     (((v) << 12) & 0x1000)
+#define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v)                   ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000)
+#define BP_I2C_STAT_BUS_BUSY                                    11
+#define BM_I2C_STAT_BUS_BUSY                                    0x800
+#define BV_I2C_STAT_BUS_BUSY__IDLE                              0x0
+#define BV_I2C_STAT_BUS_BUSY__BUSY                              0x1
+#define BF_I2C_STAT_BUS_BUSY(v)                                 (((v) << 11) & 0x800)
+#define BF_I2C_STAT_BUS_BUSY_V(v)                               ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800)
+#define BP_I2C_STAT_CLK_GEN_BUSY                                10
+#define BM_I2C_STAT_CLK_GEN_BUSY                                0x400
+#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE                          0x0
+#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY                          0x1
+#define BF_I2C_STAT_CLK_GEN_BUSY(v)                             (((v) << 10) & 0x400)
+#define BF_I2C_STAT_CLK_GEN_BUSY_V(v)                           ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400)
+#define BP_I2C_STAT_DATA_ENGINE_BUSY                            9
+#define BM_I2C_STAT_DATA_ENGINE_BUSY                            0x200
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE                      0x0
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY                      0x1
+#define BF_I2C_STAT_DATA_ENGINE_BUSY(v)                         (((v) << 9) & 0x200)
+#define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v)                       ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200)
+#define BP_I2C_STAT_SLAVE_BUSY                                  8
+#define BM_I2C_STAT_SLAVE_BUSY                                  0x100
+#define BV_I2C_STAT_SLAVE_BUSY__IDLE                            0x0
+#define BV_I2C_STAT_SLAVE_BUSY__BUSY                            0x1
+#define BF_I2C_STAT_SLAVE_BUSY(v)                               (((v) << 8) & 0x100)
+#define BF_I2C_STAT_SLAVE_BUSY_V(v)                             ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100)
+#define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        7
+#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY                        0x80
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST            0x0
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST               0x1
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v)                     (((v) << 7) & 0x80)
+#define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v)                   ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80)
+#define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               6
+#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY               0x40
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST   0x0
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST      0x1
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v)            (((v) << 6) & 0x40)
+#define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v)          ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40)
+#define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    5
+#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY                    0x20
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST        0x0
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST           0x1
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v)                 (((v) << 5) & 0x20)
+#define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v)               ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20)
+#define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              4
+#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY              0x10
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST  0x0
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST     0x1
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v)           (((v) << 4) & 0x10)
+#define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v)         ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10)
+#define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      3
+#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY                      0x8
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v)                   (((v) << 3) & 0x8)
+#define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8)
+#define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     2
+#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY                     0x4
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST         0x0
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST            0x1
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v)                  (((v) << 2) & 0x4)
+#define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v)                ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
+#define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      1
+#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY                      0x2
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST          0x0
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST             0x1
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v)                   (((v) << 1) & 0x2)
+#define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v)                 ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2)
+#define BP_I2C_STAT_SLAVE_IRQ_SUMMARY                           0
+#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY                           0x1
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST               0x0
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST                  0x1
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v)                        (((v) << 0) & 0x1)
+#define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v)                      ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_DATA
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_I2C_DATA         (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60))
+#define BP_I2C_DATA_DATA    0
+#define BM_I2C_DATA_DATA    0xffffffff
+#define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_I2C_DEBUG0
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_I2C_DEBUG0                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0))
+#define HW_I2C_DEBUG0_SET               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4))
+#define HW_I2C_DEBUG0_CLR               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8))
+#define HW_I2C_DEBUG0_TOG               (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc))
+#define BP_I2C_DEBUG0_DMAREQ            31
+#define BM_I2C_DEBUG0_DMAREQ            0x80000000
+#define BF_I2C_DEBUG0_DMAREQ(v)         (((v) << 31) & 0x80000000)
+#define BP_I2C_DEBUG0_DMAENDCMD         30
+#define BM_I2C_DEBUG0_DMAENDCMD         0x40000000
+#define BF_I2C_DEBUG0_DMAENDCMD(v)      (((v) << 30) & 0x40000000)
+#define BP_I2C_DEBUG0_DMAKICK           29
+#define BM_I2C_DEBUG0_DMAKICK           0x20000000
+#define BF_I2C_DEBUG0_DMAKICK(v)        (((v) << 29) & 0x20000000)
+#define BP_I2C_DEBUG0_TBD               26
+#define BM_I2C_DEBUG0_TBD               0x1c000000
+#define BF_I2C_DEBUG0_TBD(v)            (((v) << 26) & 0x1c000000)
+#define BP_I2C_DEBUG0_DMA_STATE         16
+#define BM_I2C_DEBUG0_DMA_STATE         0x3ff0000
+#define BF_I2C_DEBUG0_DMA_STATE(v)      (((v) << 16) & 0x3ff0000)
+#define BP_I2C_DEBUG0_START_TOGGLE      15
+#define BM_I2C_DEBUG0_START_TOGGLE      0x8000
+#define BF_I2C_DEBUG0_START_TOGGLE(v)   (((v) << 15) & 0x8000)
+#define BP_I2C_DEBUG0_STOP_TOGGLE       14
+#define BM_I2C_DEBUG0_STOP_TOGGLE       0x4000
+#define BF_I2C_DEBUG0_STOP_TOGGLE(v)    (((v) << 14) & 0x4000)
+#define BP_I2C_DEBUG0_GRAB_TOGGLE       13
+#define BM_I2C_DEBUG0_GRAB_TOGGLE       0x2000
+#define BF_I2C_DEBUG0_GRAB_TOGGLE(v)    (((v) << 13) & 0x2000)
+#define BP_I2C_DEBUG0_CHANGE_TOGGLE     12
+#define BM_I2C_DEBUG0_CHANGE_TOGGLE     0x1000
+#define BF_I2C_DEBUG0_CHANGE_TOGGLE(v)  (((v) << 12) & 0x1000)
+#define BP_I2C_DEBUG0_TESTMODE          11
+#define BM_I2C_DEBUG0_TESTMODE          0x800
+#define BF_I2C_DEBUG0_TESTMODE(v)       (((v) << 11) & 0x800)
+#define BP_I2C_DEBUG0_SLAVE_HOLD_CLK    10
+#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK    0x400
+#define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400)
+#define BP_I2C_DEBUG0_SLAVE_STATE       0
+#define BM_I2C_DEBUG0_SLAVE_STATE       0x3ff
+#define BF_I2C_DEBUG0_SLAVE_STATE(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_I2C_DEBUG1
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_I2C_DEBUG1                       (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0))
+#define HW_I2C_DEBUG1_SET                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4))
+#define HW_I2C_DEBUG1_CLR                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8))
+#define HW_I2C_DEBUG1_TOG                   (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc))
+#define BP_I2C_DEBUG1_I2C_CLK_IN            31
+#define BM_I2C_DEBUG1_I2C_CLK_IN            0x80000000
+#define BF_I2C_DEBUG1_I2C_CLK_IN(v)         (((v) << 31) & 0x80000000)
+#define BP_I2C_DEBUG1_I2C_DATA_IN           30
+#define BM_I2C_DEBUG1_I2C_DATA_IN           0x40000000
+#define BF_I2C_DEBUG1_I2C_DATA_IN(v)        (((v) << 30) & 0x40000000)
+#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES      24
+#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES      0xf000000
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v)   (((v) << 24) & 0xf000000)
+#define BP_I2C_DEBUG1_CLK_GEN_STATE         16
+#define BM_I2C_DEBUG1_CLK_GEN_STATE         0x7f0000
+#define BF_I2C_DEBUG1_CLK_GEN_STATE(v)      (((v) << 16) & 0x7f0000)
+#define BP_I2C_DEBUG1_LST_MODE              9
+#define BM_I2C_DEBUG1_LST_MODE              0x600
+#define BV_I2C_DEBUG1_LST_MODE__BCAST       0x0
+#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE    0x1
+#define BV_I2C_DEBUG1_LST_MODE__MY_READ     0x2
+#define BV_I2C_DEBUG1_LST_MODE__NOT_ME      0x3
+#define BF_I2C_DEBUG1_LST_MODE(v)           (((v) << 9) & 0x600)
+#define BF_I2C_DEBUG1_LST_MODE_V(v)         ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600)
+#define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST      8
+#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST      0x100
+#define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v)   (((v) << 8) & 0x100)
+#define BP_I2C_DEBUG1_FORCE_CLK_ON          5
+#define BM_I2C_DEBUG1_FORCE_CLK_ON          0x20
+#define BF_I2C_DEBUG1_FORCE_CLK_ON(v)       (((v) << 5) & 0x20)
+#define BP_I2C_DEBUG1_FORCE_CLK_IDLE        4
+#define BM_I2C_DEBUG1_FORCE_CLK_IDLE        0x10
+#define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v)     (((v) << 4) & 0x10)
+#define BP_I2C_DEBUG1_FORCE_ARB_LOSS        3
+#define BM_I2C_DEBUG1_FORCE_ARB_LOSS        0x8
+#define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v)     (((v) << 3) & 0x8)
+#define BP_I2C_DEBUG1_FORCE_RCV_ACK         2
+#define BM_I2C_DEBUG1_FORCE_RCV_ACK         0x4
+#define BF_I2C_DEBUG1_FORCE_RCV_ACK(v)      (((v) << 2) & 0x4)
+#define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE     1
+#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE     0x2
+#define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v)  (((v) << 1) & 0x2)
+#define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE      0
+#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE      0x1
+#define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_I2C_VERSION
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_I2C_VERSION          (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90))
+#define BP_I2C_VERSION_MAJOR    24
+#define BM_I2C_VERSION_MAJOR    0xff000000
+#define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_I2C_VERSION_MINOR    16
+#define BM_I2C_VERSION_MINOR    0xff0000
+#define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_I2C_VERSION_STEP     0
+#define BM_I2C_VERSION_STEP     0xffff
+#define BF_I2C_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__I2C__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h
new file mode 100644
index 0000000000..a4b7d51519
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h
@@ -0,0 +1,410 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__ICOLL__H__
+#define __HEADERGEN__STMP3700__ICOLL__H__
+
+#define REGS_ICOLL_BASE (0x80000000)
+
+#define REGS_ICOLL_VERSION "3.2.0"
+
+/**
+ * Register: HW_ICOLL_VECTOR
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_ICOLL_VECTOR                 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0))
+#define HW_ICOLL_VECTOR_SET             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4))
+#define HW_ICOLL_VECTOR_CLR             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8))
+#define HW_ICOLL_VECTOR_TOG             (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc))
+#define BP_ICOLL_VECTOR_IRQVECTOR       2
+#define BM_ICOLL_VECTOR_IRQVECTOR       0xfffffffc
+#define BF_ICOLL_VECTOR_IRQVECTOR(v)    (((v) << 2) & 0xfffffffc)
+
+/**
+ * Register: HW_ICOLL_LEVELACK
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_ICOLL_LEVELACK                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10))
+#define BP_ICOLL_LEVELACK_IRQLEVELACK           0
+#define BM_ICOLL_LEVELACK_IRQLEVELACK           0xf
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1   0x2
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2   0x4
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3   0x8
+#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)        (((v) << 0) & 0xf)
+#define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v)      ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf)
+
+/**
+ * Register: HW_ICOLL_CTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_ICOLL_CTRL                                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0))
+#define HW_ICOLL_CTRL_SET                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4))
+#define HW_ICOLL_CTRL_CLR                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8))
+#define HW_ICOLL_CTRL_TOG                               (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc))
+#define BP_ICOLL_CTRL_SFTRST                            31
+#define BM_ICOLL_CTRL_SFTRST                            0x80000000
+#define BV_ICOLL_CTRL_SFTRST__RUN                       0x0
+#define BV_ICOLL_CTRL_SFTRST__IN_RESET                  0x1
+#define BF_ICOLL_CTRL_SFTRST(v)                         (((v) << 31) & 0x80000000)
+#define BF_ICOLL_CTRL_SFTRST_V(v)                       ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_ICOLL_CTRL_CLKGATE                           30
+#define BM_ICOLL_CTRL_CLKGATE                           0x40000000
+#define BV_ICOLL_CTRL_CLKGATE__RUN                      0x0
+#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS                0x1
+#define BF_ICOLL_CTRL_CLKGATE(v)                        (((v) << 30) & 0x40000000)
+#define BF_ICOLL_CTRL_CLKGATE_V(v)                      ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000)
+#define BP_ICOLL_CTRL_VECTOR_PITCH                      21
+#define BM_ICOLL_CTRL_VECTOR_PITCH                      0xe00000
+#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4         0x0
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4                 0x1
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8                 0x2
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12                0x3
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16                0x4
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20                0x5
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24                0x6
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28                0x7
+#define BF_ICOLL_CTRL_VECTOR_PITCH(v)                   (((v) << 21) & 0xe00000)
+#define BF_ICOLL_CTRL_VECTOR_PITCH_V(v)                 ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000)
+#define BP_ICOLL_CTRL_BYPASS_FSM                        20
+#define BM_ICOLL_CTRL_BYPASS_FSM                        0x100000
+#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL                0x0
+#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS                0x1
+#define BF_ICOLL_CTRL_BYPASS_FSM(v)                     (((v) << 20) & 0x100000)
+#define BF_ICOLL_CTRL_BYPASS_FSM_V(v)                   ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000)
+#define BP_ICOLL_CTRL_NO_NESTING                        19
+#define BM_ICOLL_CTRL_NO_NESTING                        0x80000
+#define BV_ICOLL_CTRL_NO_NESTING__NORMAL                0x0
+#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST               0x1
+#define BF_ICOLL_CTRL_NO_NESTING(v)                     (((v) << 19) & 0x80000)
+#define BF_ICOLL_CTRL_NO_NESTING_V(v)                   ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000)
+#define BP_ICOLL_CTRL_ARM_RSE_MODE                      18
+#define BM_ICOLL_CTRL_ARM_RSE_MODE                      0x40000
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE          0x0
+#define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT    0x1
+#define BF_ICOLL_CTRL_ARM_RSE_MODE(v)                   (((v) << 18) & 0x40000)
+#define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v)                 ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000)
+#define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE                  17
+#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE                  0x20000
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v)               (((v) << 17) & 0x20000)
+#define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000)
+#define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE                  16
+#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE                  0x10000
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE         0x0
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE          0x1
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v)               (((v) << 16) & 0x10000)
+#define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v)             ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000)
+#define BP_ICOLL_CTRL_ENABLE2FIQ35                      7
+#define BM_ICOLL_CTRL_ENABLE2FIQ35                      0x80
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ35(v)                   (((v) << 7) & 0x80)
+#define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 7) & 0x80)
+#define BP_ICOLL_CTRL_ENABLE2FIQ34                      6
+#define BM_ICOLL_CTRL_ENABLE2FIQ34                      0x40
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ34(v)                   (((v) << 6) & 0x40)
+#define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 6) & 0x40)
+#define BP_ICOLL_CTRL_ENABLE2FIQ33                      5
+#define BM_ICOLL_CTRL_ENABLE2FIQ33                      0x20
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ33(v)                   (((v) << 5) & 0x20)
+#define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 5) & 0x20)
+#define BP_ICOLL_CTRL_ENABLE2FIQ32                      4
+#define BM_ICOLL_CTRL_ENABLE2FIQ32                      0x10
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE             0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE              0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ32(v)                   (((v) << 4) & 0x10)
+#define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v)                 ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 4) & 0x10)
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T3                     3
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T3                     0x8
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T3__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T3__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T3(v)                  (((v) << 3) & 0x8)
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T3_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T3__##v << 3) & 0x8)
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T2                     2
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T2                     0x4
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T2__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T2__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T2(v)                  (((v) << 2) & 0x4)
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T2_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T2__##v << 2) & 0x4)
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T1                     1
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T1                     0x2
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T1__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T1__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T1(v)                  (((v) << 1) & 0x2)
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T1_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T1__##v << 1) & 0x2)
+#define BP_ICOLL_CTRL_ENABLE2FIQ_T0                     0
+#define BM_ICOLL_CTRL_ENABLE2FIQ_T0                     0x1
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T0__DISABLE            0x0
+#define BV_ICOLL_CTRL_ENABLE2FIQ_T0__ENABLE             0x1
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T0(v)                  (((v) << 0) & 0x1)
+#define BF_ICOLL_CTRL_ENABLE2FIQ_T0_V(v)                ((BV_ICOLL_CTRL_ENABLE2FIQ_T0__##v << 0) & 0x1)
+
+/**
+ * Register: HW_ICOLL_STAT
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_ICOLL_STAT                   (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30))
+#define BP_ICOLL_STAT_VECTOR_NUMBER     0
+#define BM_ICOLL_STAT_VECTOR_NUMBER     0x3f
+#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_ICOLL_RAWn
+ * Address: 0x40+n*0x10
+ * SCT: no
+*/
+#define HW_ICOLL_RAWn(n)            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10))
+#define BP_ICOLL_RAWn_RAW_IRQS      0
+#define BM_ICOLL_RAWn_RAW_IRQS      0xffffffff
+#define BF_ICOLL_RAWn_RAW_IRQS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_PRIORITYn
+ * Address: 0x60+n*0x10
+ * SCT: yes
+*/
+#define HW_ICOLL_PRIORITYn(n)                           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0))
+#define HW_ICOLL_PRIORITYn_SET(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4))
+#define HW_ICOLL_PRIORITYn_CLR(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8))
+#define HW_ICOLL_PRIORITYn_TOG(n)                       (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc))
+#define BP_ICOLL_PRIORITYn_SOFTIRQ3                     27
+#define BM_ICOLL_PRIORITYn_SOFTIRQ3                     0x8000000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3(v)                  (((v) << 27) & 0x8000000)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000)
+#define BP_ICOLL_PRIORITYn_ENABLE3                      26
+#define BM_ICOLL_PRIORITYn_ENABLE3                      0x4000000
+#define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE3(v)                   (((v) << 26) & 0x4000000)
+#define BF_ICOLL_PRIORITYn_ENABLE3_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000)
+#define BP_ICOLL_PRIORITYn_PRIORITY3                    24
+#define BM_ICOLL_PRIORITYn_PRIORITY3                    0x3000000
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY3(v)                 (((v) << 24) & 0x3000000)
+#define BF_ICOLL_PRIORITYn_PRIORITY3_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ2                     19
+#define BM_ICOLL_PRIORITYn_SOFTIRQ2                     0x80000
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2(v)                  (((v) << 19) & 0x80000)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000)
+#define BP_ICOLL_PRIORITYn_ENABLE2                      18
+#define BM_ICOLL_PRIORITYn_ENABLE2                      0x40000
+#define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE2(v)                   (((v) << 18) & 0x40000)
+#define BF_ICOLL_PRIORITYn_ENABLE2_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000)
+#define BP_ICOLL_PRIORITYn_PRIORITY2                    16
+#define BM_ICOLL_PRIORITYn_PRIORITY2                    0x30000
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY2(v)                 (((v) << 16) & 0x30000)
+#define BF_ICOLL_PRIORITYn_PRIORITY2_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ1                     11
+#define BM_ICOLL_PRIORITYn_SOFTIRQ1                     0x800
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1(v)                  (((v) << 11) & 0x800)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800)
+#define BP_ICOLL_PRIORITYn_ENABLE1                      10
+#define BM_ICOLL_PRIORITYn_ENABLE1                      0x400
+#define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE1(v)                   (((v) << 10) & 0x400)
+#define BF_ICOLL_PRIORITYn_ENABLE1_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400)
+#define BP_ICOLL_PRIORITYn_PRIORITY1                    8
+#define BM_ICOLL_PRIORITYn_PRIORITY1                    0x300
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY1(v)                 (((v) << 8) & 0x300)
+#define BF_ICOLL_PRIORITYn_PRIORITY1_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300)
+#define BP_ICOLL_PRIORITYn_SOFTIRQ0                     3
+#define BM_ICOLL_PRIORITYn_SOFTIRQ0                     0x8
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT       0x0
+#define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT    0x1
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0(v)                  (((v) << 3) & 0x8)
+#define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v)                ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8)
+#define BP_ICOLL_PRIORITYn_ENABLE0                      2
+#define BM_ICOLL_PRIORITYn_ENABLE0                      0x4
+#define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE             0x0
+#define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE              0x1
+#define BF_ICOLL_PRIORITYn_ENABLE0(v)                   (((v) << 2) & 0x4)
+#define BF_ICOLL_PRIORITYn_ENABLE0_V(v)                 ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4)
+#define BP_ICOLL_PRIORITYn_PRIORITY0                    0
+#define BM_ICOLL_PRIORITYn_PRIORITY0                    0x3
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0            0x0
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1            0x1
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2            0x2
+#define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3            0x3
+#define BF_ICOLL_PRIORITYn_PRIORITY0(v)                 (((v) << 0) & 0x3)
+#define BF_ICOLL_PRIORITYn_PRIORITY0_V(v)               ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3)
+
+/**
+ * Register: HW_ICOLL_VBASE
+ * Address: 0x160
+ * SCT: yes
+*/
+#define HW_ICOLL_VBASE                  (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0))
+#define HW_ICOLL_VBASE_SET              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4))
+#define HW_ICOLL_VBASE_CLR              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8))
+#define HW_ICOLL_VBASE_TOG              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc))
+#define BP_ICOLL_VBASE_TABLE_ADDRESS    2
+#define BM_ICOLL_VBASE_TABLE_ADDRESS    0xfffffffc
+#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc)
+
+/**
+ * Register: HW_ICOLL_DEBUG
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_ICOLL_DEBUG                              (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170))
+#define BP_ICOLL_DEBUG_INSERVICE                    28
+#define BM_ICOLL_DEBUG_INSERVICE                    0xf0000000
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0            0x1
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1            0x2
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2            0x4
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3            0x8
+#define BF_ICOLL_DEBUG_INSERVICE(v)                 (((v) << 28) & 0xf0000000)
+#define BF_ICOLL_DEBUG_INSERVICE_V(v)               ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000)
+#define BP_ICOLL_DEBUG_LEVEL_REQUESTS               24
+#define BM_ICOLL_DEBUG_LEVEL_REQUESTS               0xf000000
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0       0x1
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1       0x2
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2       0x4
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3       0x8
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)            (((v) << 24) & 0xf000000)
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v)          ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000)
+#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL            20
+#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL            0xf00000
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0    0x1
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1    0x2
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2    0x4
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3    0x8
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)         (((v) << 20) & 0xf00000)
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v)       ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000)
+#define BP_ICOLL_DEBUG_FIQ                          17
+#define BM_ICOLL_DEBUG_FIQ                          0x20000
+#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_FIQ(v)                       (((v) << 17) & 0x20000)
+#define BF_ICOLL_DEBUG_FIQ_V(v)                     ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000)
+#define BP_ICOLL_DEBUG_IRQ                          16
+#define BM_ICOLL_DEBUG_IRQ                          0x10000
+#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED        0x0
+#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED           0x1
+#define BF_ICOLL_DEBUG_IRQ(v)                       (((v) << 16) & 0x10000)
+#define BF_ICOLL_DEBUG_IRQ_V(v)                     ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000)
+#define BP_ICOLL_DEBUG_VECTOR_FSM                   0
+#define BM_ICOLL_DEBUG_VECTOR_FSM                   0x3ff
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x0
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x1
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x2
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x4
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x8
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x10
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
+#define BF_ICOLL_DEBUG_VECTOR_FSM(v)                (((v) << 0) & 0x3ff)
+#define BF_ICOLL_DEBUG_VECTOR_FSM_V(v)              ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff)
+
+/**
+ * Register: HW_ICOLL_DBGREAD0
+ * Address: 0x180
+ * SCT: no
+*/
+#define HW_ICOLL_DBGREAD0           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180))
+#define BP_ICOLL_DBGREAD0_VALUE     0
+#define BM_ICOLL_DBGREAD0_VALUE     0xffffffff
+#define BF_ICOLL_DBGREAD0_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_DBGREAD1
+ * Address: 0x190
+ * SCT: no
+*/
+#define HW_ICOLL_DBGREAD1           (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x190))
+#define BP_ICOLL_DBGREAD1_VALUE     0
+#define BM_ICOLL_DBGREAD1_VALUE     0xffffffff
+#define BF_ICOLL_DBGREAD1_VALUE(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_DBGFLAG
+ * Address: 0x1a0
+ * SCT: yes
+*/
+#define HW_ICOLL_DBGFLAG            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0))
+#define HW_ICOLL_DBGFLAG_SET        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4))
+#define HW_ICOLL_DBGFLAG_CLR        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8))
+#define HW_ICOLL_DBGFLAG_TOG        (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc))
+#define BP_ICOLL_DBGFLAG_FLAG       0
+#define BM_ICOLL_DBGFLAG_FLAG       0xffff
+#define BF_ICOLL_DBGFLAG_FLAG(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_ICOLL_DBGREQUESTn
+ * Address: 0x1b0+n*0x10
+ * SCT: no
+*/
+#define HW_ICOLL_DBGREQUESTn(n)         (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10))
+#define BP_ICOLL_DBGREQUESTn_BITS       0
+#define BM_ICOLL_DBGREQUESTn_BITS       0xffffffff
+#define BF_ICOLL_DBGREQUESTn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_ICOLL_VERSION
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_ICOLL_VERSION            (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1d0))
+#define BP_ICOLL_VERSION_MAJOR      24
+#define BM_ICOLL_VERSION_MAJOR      0xff000000
+#define BF_ICOLL_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_ICOLL_VERSION_MINOR      16
+#define BM_ICOLL_VERSION_MINOR      0xff0000
+#define BF_ICOLL_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_ICOLL_VERSION_STEP       0
+#define BM_ICOLL_VERSION_STEP       0xffff
+#define BF_ICOLL_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__ICOLL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h
new file mode 100644
index 0000000000..d7c14dcecf
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h
@@ -0,0 +1,493 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__IR__H__
+#define __HEADERGEN__STMP3700__IR__H__
+
+#define REGS_IR_BASE (0x80078000)
+
+#define REGS_IR_VERSION "3.2.0"
+
+/**
+ * Register: HW_IR_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_IR_CTRL                  (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0))
+#define HW_IR_CTRL_SET              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4))
+#define HW_IR_CTRL_CLR              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8))
+#define HW_IR_CTRL_TOG              (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc))
+#define BP_IR_CTRL_SFTRST           31
+#define BM_IR_CTRL_SFTRST           0x80000000
+#define BV_IR_CTRL_SFTRST__RUN      0x0
+#define BV_IR_CTRL_SFTRST__RESET    0x1
+#define BF_IR_CTRL_SFTRST(v)        (((v) << 31) & 0x80000000)
+#define BF_IR_CTRL_SFTRST_V(v)      ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000)
+#define BP_IR_CTRL_CLKGATE          30
+#define BM_IR_CTRL_CLKGATE          0x40000000
+#define BF_IR_CTRL_CLKGATE(v)       (((v) << 30) & 0x40000000)
+#define BP_IR_CTRL_MTA              24
+#define BM_IR_CTRL_MTA              0x7000000
+#define BV_IR_CTRL_MTA__MTA_10MS    0x0
+#define BV_IR_CTRL_MTA__MTA_5MS     0x1
+#define BV_IR_CTRL_MTA__MTA_1MS     0x2
+#define BV_IR_CTRL_MTA__MTA_500US   0x3
+#define BV_IR_CTRL_MTA__MTA_100US   0x4
+#define BV_IR_CTRL_MTA__MTA_50US    0x5
+#define BV_IR_CTRL_MTA__MTA_10US    0x6
+#define BV_IR_CTRL_MTA__MTA_0       0x7
+#define BF_IR_CTRL_MTA(v)           (((v) << 24) & 0x7000000)
+#define BF_IR_CTRL_MTA_V(v)         ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000)
+#define BP_IR_CTRL_MODE             22
+#define BM_IR_CTRL_MODE             0xc00000
+#define BV_IR_CTRL_MODE__SIR        0x0
+#define BV_IR_CTRL_MODE__MIR        0x1
+#define BV_IR_CTRL_MODE__FIR        0x2
+#define BV_IR_CTRL_MODE__VFIR       0x3
+#define BF_IR_CTRL_MODE(v)          (((v) << 22) & 0xc00000)
+#define BF_IR_CTRL_MODE_V(v)        ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000)
+#define BP_IR_CTRL_SPEED            19
+#define BM_IR_CTRL_SPEED            0x380000
+#define BV_IR_CTRL_SPEED__SPD000    0x0
+#define BV_IR_CTRL_SPEED__SPD001    0x1
+#define BV_IR_CTRL_SPEED__SPD010    0x2
+#define BV_IR_CTRL_SPEED__SPD011    0x3
+#define BV_IR_CTRL_SPEED__SPD100    0x4
+#define BV_IR_CTRL_SPEED__SPD101    0x5
+#define BF_IR_CTRL_SPEED(v)         (((v) << 19) & 0x380000)
+#define BF_IR_CTRL_SPEED_V(v)       ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000)
+#define BP_IR_CTRL_TC_TIME_DIV      8
+#define BM_IR_CTRL_TC_TIME_DIV      0x3f00
+#define BF_IR_CTRL_TC_TIME_DIV(v)   (((v) << 8) & 0x3f00)
+#define BP_IR_CTRL_TC_TYPE          7
+#define BM_IR_CTRL_TC_TYPE          0x80
+#define BF_IR_CTRL_TC_TYPE(v)       (((v) << 7) & 0x80)
+#define BP_IR_CTRL_SIR_GAP          4
+#define BM_IR_CTRL_SIR_GAP          0x70
+#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0
+#define BV_IR_CTRL_SIR_GAP__GAP_5K  0x1
+#define BV_IR_CTRL_SIR_GAP__GAP_1K  0x2
+#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3
+#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4
+#define BV_IR_CTRL_SIR_GAP__GAP_50  0x5
+#define BV_IR_CTRL_SIR_GAP__GAP_10  0x6
+#define BV_IR_CTRL_SIR_GAP__GAP_0   0x7
+#define BF_IR_CTRL_SIR_GAP(v)       (((v) << 4) & 0x70)
+#define BF_IR_CTRL_SIR_GAP_V(v)     ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70)
+#define BP_IR_CTRL_SIPEN            3
+#define BM_IR_CTRL_SIPEN            0x8
+#define BF_IR_CTRL_SIPEN(v)         (((v) << 3) & 0x8)
+#define BP_IR_CTRL_TCEN             2
+#define BM_IR_CTRL_TCEN             0x4
+#define BF_IR_CTRL_TCEN(v)          (((v) << 2) & 0x4)
+#define BP_IR_CTRL_TXEN             1
+#define BM_IR_CTRL_TXEN             0x2
+#define BF_IR_CTRL_TXEN(v)          (((v) << 1) & 0x2)
+#define BP_IR_CTRL_RXEN             0
+#define BM_IR_CTRL_RXEN             0x1
+#define BF_IR_CTRL_RXEN(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_TXDMA
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_IR_TXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0))
+#define HW_IR_TXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4))
+#define HW_IR_TXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8))
+#define HW_IR_TXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc))
+#define BP_IR_TXDMA_RUN             31
+#define BM_IR_TXDMA_RUN             0x80000000
+#define BF_IR_TXDMA_RUN(v)          (((v) << 31) & 0x80000000)
+#define BP_IR_TXDMA_EMPTY           29
+#define BM_IR_TXDMA_EMPTY           0x20000000
+#define BF_IR_TXDMA_EMPTY(v)        (((v) << 29) & 0x20000000)
+#define BP_IR_TXDMA_INT             28
+#define BM_IR_TXDMA_INT             0x10000000
+#define BF_IR_TXDMA_INT(v)          (((v) << 28) & 0x10000000)
+#define BP_IR_TXDMA_CHANGE          27
+#define BM_IR_TXDMA_CHANGE          0x8000000
+#define BF_IR_TXDMA_CHANGE(v)       (((v) << 27) & 0x8000000)
+#define BP_IR_TXDMA_NEW_MTA         24
+#define BM_IR_TXDMA_NEW_MTA         0x7000000
+#define BF_IR_TXDMA_NEW_MTA(v)      (((v) << 24) & 0x7000000)
+#define BP_IR_TXDMA_NEW_MODE        22
+#define BM_IR_TXDMA_NEW_MODE        0xc00000
+#define BF_IR_TXDMA_NEW_MODE(v)     (((v) << 22) & 0xc00000)
+#define BP_IR_TXDMA_NEW_SPEED       19
+#define BM_IR_TXDMA_NEW_SPEED       0x380000
+#define BF_IR_TXDMA_NEW_SPEED(v)    (((v) << 19) & 0x380000)
+#define BP_IR_TXDMA_BOF_TYPE        18
+#define BM_IR_TXDMA_BOF_TYPE        0x40000
+#define BF_IR_TXDMA_BOF_TYPE(v)     (((v) << 18) & 0x40000)
+#define BP_IR_TXDMA_XBOFS           12
+#define BM_IR_TXDMA_XBOFS           0x3f000
+#define BF_IR_TXDMA_XBOFS(v)        (((v) << 12) & 0x3f000)
+#define BP_IR_TXDMA_XFER_COUNT      0
+#define BM_IR_TXDMA_XFER_COUNT      0xfff
+#define BF_IR_TXDMA_XFER_COUNT(v)   (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_IR_RXDMA
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_IR_RXDMA                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0))
+#define HW_IR_RXDMA_SET             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4))
+#define HW_IR_RXDMA_CLR             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8))
+#define HW_IR_RXDMA_TOG             (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc))
+#define BP_IR_RXDMA_RUN             31
+#define BM_IR_RXDMA_RUN             0x80000000
+#define BF_IR_RXDMA_RUN(v)          (((v) << 31) & 0x80000000)
+#define BP_IR_RXDMA_XFER_COUNT      0
+#define BM_IR_RXDMA_XFER_COUNT      0x3ff
+#define BF_IR_RXDMA_XFER_COUNT(v)   (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_IR_DBGCTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_IR_DBGCTRL                   (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0))
+#define HW_IR_DBGCTRL_SET               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4))
+#define HW_IR_DBGCTRL_CLR               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8))
+#define HW_IR_DBGCTRL_TOG               (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc))
+#define BP_IR_DBGCTRL_VFIRSWZ           12
+#define BM_IR_DBGCTRL_VFIRSWZ           0x1000
+#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL   0x0
+#define BV_IR_DBGCTRL_VFIRSWZ__SWAP     0x1
+#define BF_IR_DBGCTRL_VFIRSWZ(v)        (((v) << 12) & 0x1000)
+#define BF_IR_DBGCTRL_VFIRSWZ_V(v)      ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000)
+#define BP_IR_DBGCTRL_RXFRMOFF          11
+#define BM_IR_DBGCTRL_RXFRMOFF          0x800
+#define BF_IR_DBGCTRL_RXFRMOFF(v)       (((v) << 11) & 0x800)
+#define BP_IR_DBGCTRL_RXCRCOFF          10
+#define BM_IR_DBGCTRL_RXCRCOFF          0x400
+#define BF_IR_DBGCTRL_RXCRCOFF(v)       (((v) << 10) & 0x400)
+#define BP_IR_DBGCTRL_RXINVERT          9
+#define BM_IR_DBGCTRL_RXINVERT          0x200
+#define BF_IR_DBGCTRL_RXINVERT(v)       (((v) << 9) & 0x200)
+#define BP_IR_DBGCTRL_TXFRMOFF          8
+#define BM_IR_DBGCTRL_TXFRMOFF          0x100
+#define BF_IR_DBGCTRL_TXFRMOFF(v)       (((v) << 8) & 0x100)
+#define BP_IR_DBGCTRL_TXCRCOFF          7
+#define BM_IR_DBGCTRL_TXCRCOFF          0x80
+#define BF_IR_DBGCTRL_TXCRCOFF(v)       (((v) << 7) & 0x80)
+#define BP_IR_DBGCTRL_TXINVERT          6
+#define BM_IR_DBGCTRL_TXINVERT          0x40
+#define BF_IR_DBGCTRL_TXINVERT(v)       (((v) << 6) & 0x40)
+#define BP_IR_DBGCTRL_INTLOOPBACK       5
+#define BM_IR_DBGCTRL_INTLOOPBACK       0x20
+#define BF_IR_DBGCTRL_INTLOOPBACK(v)    (((v) << 5) & 0x20)
+#define BP_IR_DBGCTRL_DUPLEX            4
+#define BM_IR_DBGCTRL_DUPLEX            0x10
+#define BF_IR_DBGCTRL_DUPLEX(v)         (((v) << 4) & 0x10)
+#define BP_IR_DBGCTRL_MIO_RX            3
+#define BM_IR_DBGCTRL_MIO_RX            0x8
+#define BF_IR_DBGCTRL_MIO_RX(v)         (((v) << 3) & 0x8)
+#define BP_IR_DBGCTRL_MIO_TX            2
+#define BM_IR_DBGCTRL_MIO_TX            0x4
+#define BF_IR_DBGCTRL_MIO_TX(v)         (((v) << 2) & 0x4)
+#define BP_IR_DBGCTRL_MIO_SCLK          1
+#define BM_IR_DBGCTRL_MIO_SCLK          0x2
+#define BF_IR_DBGCTRL_MIO_SCLK(v)       (((v) << 1) & 0x2)
+#define BP_IR_DBGCTRL_MIO_EN            0
+#define BM_IR_DBGCTRL_MIO_EN            0x1
+#define BF_IR_DBGCTRL_MIO_EN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_INTR
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_IR_INTR                          (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0))
+#define HW_IR_INTR_SET                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4))
+#define HW_IR_INTR_CLR                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8))
+#define HW_IR_INTR_TOG                      (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc))
+#define BP_IR_INTR_RXABORT_IRQ_EN           22
+#define BM_IR_INTR_RXABORT_IRQ_EN           0x400000
+#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0
+#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED  0x1
+#define BF_IR_INTR_RXABORT_IRQ_EN(v)        (((v) << 22) & 0x400000)
+#define BF_IR_INTR_RXABORT_IRQ_EN_V(v)      ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000)
+#define BP_IR_INTR_SPEED_IRQ_EN             21
+#define BM_IR_INTR_SPEED_IRQ_EN             0x200000
+#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED   0x0
+#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED    0x1
+#define BF_IR_INTR_SPEED_IRQ_EN(v)          (((v) << 21) & 0x200000)
+#define BF_IR_INTR_SPEED_IRQ_EN_V(v)        ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000)
+#define BP_IR_INTR_RXOF_IRQ_EN              20
+#define BM_IR_INTR_RXOF_IRQ_EN              0x100000
+#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_RXOF_IRQ_EN(v)           (((v) << 20) & 0x100000)
+#define BF_IR_INTR_RXOF_IRQ_EN_V(v)         ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000)
+#define BP_IR_INTR_TXUF_IRQ_EN              19
+#define BM_IR_INTR_TXUF_IRQ_EN              0x80000
+#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED    0x0
+#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED     0x1
+#define BF_IR_INTR_TXUF_IRQ_EN(v)           (((v) << 19) & 0x80000)
+#define BF_IR_INTR_TXUF_IRQ_EN_V(v)         ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000)
+#define BP_IR_INTR_TC_IRQ_EN                18
+#define BM_IR_INTR_TC_IRQ_EN                0x40000
+#define BV_IR_INTR_TC_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TC_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TC_IRQ_EN(v)             (((v) << 18) & 0x40000)
+#define BF_IR_INTR_TC_IRQ_EN_V(v)           ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000)
+#define BP_IR_INTR_RX_IRQ_EN                17
+#define BM_IR_INTR_RX_IRQ_EN                0x20000
+#define BV_IR_INTR_RX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_RX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_RX_IRQ_EN(v)             (((v) << 17) & 0x20000)
+#define BF_IR_INTR_RX_IRQ_EN_V(v)           ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000)
+#define BP_IR_INTR_TX_IRQ_EN                16
+#define BM_IR_INTR_TX_IRQ_EN                0x10000
+#define BV_IR_INTR_TX_IRQ_EN__DISABLED      0x0
+#define BV_IR_INTR_TX_IRQ_EN__ENABLED       0x1
+#define BF_IR_INTR_TX_IRQ_EN(v)             (((v) << 16) & 0x10000)
+#define BF_IR_INTR_TX_IRQ_EN_V(v)           ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000)
+#define BP_IR_INTR_RXABORT_IRQ              6
+#define BM_IR_INTR_RXABORT_IRQ              0x40
+#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST  0x0
+#define BV_IR_INTR_RXABORT_IRQ__REQUEST     0x1
+#define BF_IR_INTR_RXABORT_IRQ(v)           (((v) << 6) & 0x40)
+#define BF_IR_INTR_RXABORT_IRQ_V(v)         ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40)
+#define BP_IR_INTR_SPEED_IRQ                5
+#define BM_IR_INTR_SPEED_IRQ                0x20
+#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST    0x0
+#define BV_IR_INTR_SPEED_IRQ__REQUEST       0x1
+#define BF_IR_INTR_SPEED_IRQ(v)             (((v) << 5) & 0x20)
+#define BF_IR_INTR_SPEED_IRQ_V(v)           ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20)
+#define BP_IR_INTR_RXOF_IRQ                 4
+#define BM_IR_INTR_RXOF_IRQ                 0x10
+#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_RXOF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_RXOF_IRQ(v)              (((v) << 4) & 0x10)
+#define BF_IR_INTR_RXOF_IRQ_V(v)            ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10)
+#define BP_IR_INTR_TXUF_IRQ                 3
+#define BM_IR_INTR_TXUF_IRQ                 0x8
+#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST     0x0
+#define BV_IR_INTR_TXUF_IRQ__REQUEST        0x1
+#define BF_IR_INTR_TXUF_IRQ(v)              (((v) << 3) & 0x8)
+#define BF_IR_INTR_TXUF_IRQ_V(v)            ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8)
+#define BP_IR_INTR_TC_IRQ                   2
+#define BM_IR_INTR_TC_IRQ                   0x4
+#define BV_IR_INTR_TC_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TC_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TC_IRQ(v)                (((v) << 2) & 0x4)
+#define BF_IR_INTR_TC_IRQ_V(v)              ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4)
+#define BP_IR_INTR_RX_IRQ                   1
+#define BM_IR_INTR_RX_IRQ                   0x2
+#define BV_IR_INTR_RX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_RX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_RX_IRQ(v)                (((v) << 1) & 0x2)
+#define BF_IR_INTR_RX_IRQ_V(v)              ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2)
+#define BP_IR_INTR_TX_IRQ                   0
+#define BM_IR_INTR_TX_IRQ                   0x1
+#define BV_IR_INTR_TX_IRQ__NO_REQUEST       0x0
+#define BV_IR_INTR_TX_IRQ__REQUEST          0x1
+#define BF_IR_INTR_TX_IRQ(v)                (((v) << 0) & 0x1)
+#define BF_IR_INTR_TX_IRQ_V(v)              ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_IR_DATA
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_IR_DATA          (*(volatile unsigned long *)(REGS_IR_BASE + 0x50))
+#define BP_IR_DATA_DATA     0
+#define BM_IR_DATA_DATA     0xffffffff
+#define BF_IR_DATA_DATA(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_IR_STAT
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_IR_STAT                              (*(volatile unsigned long *)(REGS_IR_BASE + 0x60))
+#define BP_IR_STAT_PRESENT                      31
+#define BM_IR_STAT_PRESENT                      0x80000000
+#define BV_IR_STAT_PRESENT__UNAVAILABLE         0x0
+#define BV_IR_STAT_PRESENT__AVAILABLE           0x1
+#define BF_IR_STAT_PRESENT(v)                   (((v) << 31) & 0x80000000)
+#define BF_IR_STAT_PRESENT_V(v)                 ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_IR_STAT_MODE_ALLOWED                 29
+#define BM_IR_STAT_MODE_ALLOWED                 0x60000000
+#define BV_IR_STAT_MODE_ALLOWED__VFIR           0x0
+#define BV_IR_STAT_MODE_ALLOWED__FIR            0x1
+#define BV_IR_STAT_MODE_ALLOWED__MIR            0x2
+#define BV_IR_STAT_MODE_ALLOWED__SIR            0x3
+#define BF_IR_STAT_MODE_ALLOWED(v)              (((v) << 29) & 0x60000000)
+#define BF_IR_STAT_MODE_ALLOWED_V(v)            ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000)
+#define BP_IR_STAT_ANY_IRQ                      28
+#define BM_IR_STAT_ANY_IRQ                      0x10000000
+#define BV_IR_STAT_ANY_IRQ__NO_REQUEST          0x0
+#define BV_IR_STAT_ANY_IRQ__REQUEST             0x1
+#define BF_IR_STAT_ANY_IRQ(v)                   (((v) << 28) & 0x10000000)
+#define BF_IR_STAT_ANY_IRQ_V(v)                 ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000)
+#define BP_IR_STAT_RXABORT_SUMMARY              22
+#define BM_IR_STAT_RXABORT_SUMMARY              0x400000
+#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST  0x0
+#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST     0x1
+#define BF_IR_STAT_RXABORT_SUMMARY(v)           (((v) << 22) & 0x400000)
+#define BF_IR_STAT_RXABORT_SUMMARY_V(v)         ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000)
+#define BP_IR_STAT_SPEED_SUMMARY                21
+#define BM_IR_STAT_SPEED_SUMMARY                0x200000
+#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST    0x0
+#define BV_IR_STAT_SPEED_SUMMARY__REQUEST       0x1
+#define BF_IR_STAT_SPEED_SUMMARY(v)             (((v) << 21) & 0x200000)
+#define BF_IR_STAT_SPEED_SUMMARY_V(v)           ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000)
+#define BP_IR_STAT_RXOF_SUMMARY                 20
+#define BM_IR_STAT_RXOF_SUMMARY                 0x100000
+#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_RXOF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_RXOF_SUMMARY(v)              (((v) << 20) & 0x100000)
+#define BF_IR_STAT_RXOF_SUMMARY_V(v)            ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000)
+#define BP_IR_STAT_TXUF_SUMMARY                 19
+#define BM_IR_STAT_TXUF_SUMMARY                 0x80000
+#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST     0x0
+#define BV_IR_STAT_TXUF_SUMMARY__REQUEST        0x1
+#define BF_IR_STAT_TXUF_SUMMARY(v)              (((v) << 19) & 0x80000)
+#define BF_IR_STAT_TXUF_SUMMARY_V(v)            ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000)
+#define BP_IR_STAT_TC_SUMMARY                   18
+#define BM_IR_STAT_TC_SUMMARY                   0x40000
+#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TC_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TC_SUMMARY(v)                (((v) << 18) & 0x40000)
+#define BF_IR_STAT_TC_SUMMARY_V(v)              ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000)
+#define BP_IR_STAT_RX_SUMMARY                   17
+#define BM_IR_STAT_RX_SUMMARY                   0x20000
+#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_RX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_RX_SUMMARY(v)                (((v) << 17) & 0x20000)
+#define BF_IR_STAT_RX_SUMMARY_V(v)              ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000)
+#define BP_IR_STAT_TX_SUMMARY                   16
+#define BM_IR_STAT_TX_SUMMARY                   0x10000
+#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST       0x0
+#define BV_IR_STAT_TX_SUMMARY__REQUEST          0x1
+#define BF_IR_STAT_TX_SUMMARY(v)                (((v) << 16) & 0x10000)
+#define BF_IR_STAT_TX_SUMMARY_V(v)              ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000)
+#define BP_IR_STAT_MEDIA_BUSY                   2
+#define BM_IR_STAT_MEDIA_BUSY                   0x4
+#define BF_IR_STAT_MEDIA_BUSY(v)                (((v) << 2) & 0x4)
+#define BP_IR_STAT_RX_ACTIVE                    1
+#define BM_IR_STAT_RX_ACTIVE                    0x2
+#define BF_IR_STAT_RX_ACTIVE(v)                 (((v) << 1) & 0x2)
+#define BP_IR_STAT_TX_ACTIVE                    0
+#define BM_IR_STAT_TX_ACTIVE                    0x1
+#define BF_IR_STAT_TX_ACTIVE(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_TCCTRL
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_IR_TCCTRL                (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0))
+#define HW_IR_TCCTRL_SET            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4))
+#define HW_IR_TCCTRL_CLR            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8))
+#define HW_IR_TCCTRL_TOG            (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc))
+#define BP_IR_TCCTRL_INIT           31
+#define BM_IR_TCCTRL_INIT           0x80000000
+#define BF_IR_TCCTRL_INIT(v)        (((v) << 31) & 0x80000000)
+#define BP_IR_TCCTRL_GO             30
+#define BM_IR_TCCTRL_GO             0x40000000
+#define BF_IR_TCCTRL_GO(v)          (((v) << 30) & 0x40000000)
+#define BP_IR_TCCTRL_BUSY           29
+#define BM_IR_TCCTRL_BUSY           0x20000000
+#define BF_IR_TCCTRL_BUSY(v)        (((v) << 29) & 0x20000000)
+#define BP_IR_TCCTRL_TEMIC          24
+#define BM_IR_TCCTRL_TEMIC          0x1000000
+#define BV_IR_TCCTRL_TEMIC__LOW     0x0
+#define BV_IR_TCCTRL_TEMIC__HIGH    0x1
+#define BF_IR_TCCTRL_TEMIC(v)       (((v) << 24) & 0x1000000)
+#define BF_IR_TCCTRL_TEMIC_V(v)     ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000)
+#define BP_IR_TCCTRL_EXT_DATA       16
+#define BM_IR_TCCTRL_EXT_DATA       0xff0000
+#define BF_IR_TCCTRL_EXT_DATA(v)    (((v) << 16) & 0xff0000)
+#define BP_IR_TCCTRL_DATA           8
+#define BM_IR_TCCTRL_DATA           0xff00
+#define BF_IR_TCCTRL_DATA(v)        (((v) << 8) & 0xff00)
+#define BP_IR_TCCTRL_ADDR           5
+#define BM_IR_TCCTRL_ADDR           0xe0
+#define BF_IR_TCCTRL_ADDR(v)        (((v) << 5) & 0xe0)
+#define BP_IR_TCCTRL_INDX           1
+#define BM_IR_TCCTRL_INDX           0x1e
+#define BF_IR_TCCTRL_INDX(v)        (((v) << 1) & 0x1e)
+#define BP_IR_TCCTRL_C              0
+#define BM_IR_TCCTRL_C              0x1
+#define BF_IR_TCCTRL_C(v)           (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_SI_READ
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_IR_SI_READ           (*(volatile unsigned long *)(REGS_IR_BASE + 0x80))
+#define BP_IR_SI_READ_ABORT     8
+#define BM_IR_SI_READ_ABORT     0x100
+#define BF_IR_SI_READ_ABORT(v)  (((v) << 8) & 0x100)
+#define BP_IR_SI_READ_DATA      0
+#define BM_IR_SI_READ_DATA      0xff
+#define BF_IR_SI_READ_DATA(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_IR_DEBUG
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_IR_DEBUG                 (*(volatile unsigned long *)(REGS_IR_BASE + 0x90))
+#define BP_IR_DEBUG_TXDMAKICK       5
+#define BM_IR_DEBUG_TXDMAKICK       0x20
+#define BF_IR_DEBUG_TXDMAKICK(v)    (((v) << 5) & 0x20)
+#define BP_IR_DEBUG_RXDMAKICK       4
+#define BM_IR_DEBUG_RXDMAKICK       0x10
+#define BF_IR_DEBUG_RXDMAKICK(v)    (((v) << 4) & 0x10)
+#define BP_IR_DEBUG_TXDMAEND        3
+#define BM_IR_DEBUG_TXDMAEND        0x8
+#define BF_IR_DEBUG_TXDMAEND(v)     (((v) << 3) & 0x8)
+#define BP_IR_DEBUG_RXDMAEND        2
+#define BM_IR_DEBUG_RXDMAEND        0x4
+#define BF_IR_DEBUG_RXDMAEND(v)     (((v) << 2) & 0x4)
+#define BP_IR_DEBUG_TXDMAREQ        1
+#define BM_IR_DEBUG_TXDMAREQ        0x2
+#define BF_IR_DEBUG_TXDMAREQ(v)     (((v) << 1) & 0x2)
+#define BP_IR_DEBUG_RXDMAREQ        0
+#define BM_IR_DEBUG_RXDMAREQ        0x1
+#define BF_IR_DEBUG_RXDMAREQ(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_IR_VERSION
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_IR_VERSION           (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0))
+#define BP_IR_VERSION_MAJOR     24
+#define BM_IR_VERSION_MAJOR     0xff000000
+#define BF_IR_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
+#define BP_IR_VERSION_MINOR     16
+#define BM_IR_VERSION_MINOR     0xff0000
+#define BF_IR_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
+#define BP_IR_VERSION_STEP      0
+#define BM_IR_VERSION_STEP      0xffff
+#define BF_IR_VERSION_STEP(v)   (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__IR__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h
new file mode 100644
index 0000000000..c528c81fee
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h
@@ -0,0 +1,451 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__LCDIF__H__
+#define __HEADERGEN__STMP3700__LCDIF__H__
+
+#define REGS_LCDIF_BASE (0x80030000)
+
+#define REGS_LCDIF_VERSION "3.2.0"
+
+/**
+ * Register: HW_LCDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL                                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
+#define HW_LCDIF_CTRL_SET                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
+#define HW_LCDIF_CTRL_CLR                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
+#define HW_LCDIF_CTRL_TOG                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
+#define BP_LCDIF_CTRL_SFTRST                                31
+#define BM_LCDIF_CTRL_SFTRST                                0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                             (((v) << 31) & 0x80000000)
+#define BP_LCDIF_CTRL_CLKGATE                               30
+#define BM_LCDIF_CTRL_CLKGATE                               0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                            (((v) << 30) & 0x40000000)
+#define BP_LCDIF_CTRL_READ_WRITEB                           29
+#define BM_LCDIF_CTRL_READ_WRITEB                           0x20000000
+#define BF_LCDIF_CTRL_READ_WRITEB(v)                        (((v) << 29) & 0x20000000)
+#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   28
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   0x10000000
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                (((v) << 28) & 0x10000000)
+#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                        27
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                        0x8000000
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT     0x0
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT    0x1
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                     (((v) << 27) & 0x8000000)
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                   ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 27) & 0x8000000)
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                        25
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                        0x6000000
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                     (((v) << 25) & 0x6000000)
+#define BP_LCDIF_CTRL_DVI_MODE                              24
+#define BM_LCDIF_CTRL_DVI_MODE                              0x1000000
+#define BF_LCDIF_CTRL_DVI_MODE(v)                           (((v) << 24) & 0x1000000)
+#define BP_LCDIF_CTRL_BYPASS_COUNT                          23
+#define BM_LCDIF_CTRL_BYPASS_COUNT                          0x800000
+#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                       (((v) << 23) & 0x800000)
+#define BP_LCDIF_CTRL_DATA_SWIZZLE                          21
+#define BM_LCDIF_CTRL_DATA_SWIZZLE                          0x600000
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP                 0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN           0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP         0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES          0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP                0x2
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP           0x3
+#define BF_LCDIF_CTRL_DATA_SWIZZLE(v)                       (((v) << 21) & 0x600000)
+#define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v)                     ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000)
+#define BP_LCDIF_CTRL_VSYNC_MODE                            20
+#define BM_LCDIF_CTRL_VSYNC_MODE                            0x100000
+#define BF_LCDIF_CTRL_VSYNC_MODE(v)                         (((v) << 20) & 0x100000)
+#define BP_LCDIF_CTRL_DOTCLK_MODE                           19
+#define BM_LCDIF_CTRL_DOTCLK_MODE                           0x80000
+#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                        (((v) << 19) & 0x80000)
+#define BP_LCDIF_CTRL_DATA_SELECT                           18
+#define BM_LCDIF_CTRL_DATA_SELECT                           0x40000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                 0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                        (((v) << 18) & 0x40000)
+#define BF_LCDIF_CTRL_DATA_SELECT_V(v)                      ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000)
+#define BP_LCDIF_CTRL_WORD_LENGTH                           17
+#define BM_LCDIF_CTRL_WORD_LENGTH                           0x20000
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                   0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                    0x1
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                        (((v) << 17) & 0x20000)
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)                      ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000)
+#define BP_LCDIF_CTRL_RUN                                   16
+#define BM_LCDIF_CTRL_RUN                                   0x10000
+#define BF_LCDIF_CTRL_RUN(v)                                (((v) << 16) & 0x10000)
+#define BP_LCDIF_CTRL_COUNT                                 0
+#define BM_LCDIF_CTRL_COUNT                                 0xffff
+#define BF_LCDIF_CTRL_COUNT(v)                              (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL1                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0))
+#define HW_LCDIF_CTRL1_SET                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4))
+#define HW_LCDIF_CTRL1_CLR                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8))
+#define HW_LCDIF_CTRL1_TOG                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc))
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT              16
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT              0xf0000
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)           (((v) << 16) & 0xf0000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                  15
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                  0x8000
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)               (((v) << 15) & 0x8000)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                 14
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                 0x4000
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)              (((v) << 14) & 0x4000)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN            13
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN            0x2000
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)         (((v) << 13) & 0x2000)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                12
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                0x1000
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)             (((v) << 12) & 0x1000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                     11
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                     0x800
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST         0x0
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST            0x1
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                  (((v) << 11) & 0x800)
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                    10
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                    0x400
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST        0x0
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST           0x1
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                 (((v) << 10) & 0x400)
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)               ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ               9
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ               0x200
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST   0x0
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST      0x1
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)            (((v) << 9) & 0x200)
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)          ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                   8
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                   0x100
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST       0x0
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST          0x1
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                (((v) << 8) & 0x100)
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)              ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100)
+#define BP_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS    5
+#define BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS    0xe0
+#define BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(v) (((v) << 5) & 0xe0)
+#define BP_LCDIF_CTRL1_FIRST_READ_DUMMY                 4
+#define BM_LCDIF_CTRL1_FIRST_READ_DUMMY                 0x10
+#define BF_LCDIF_CTRL1_FIRST_READ_DUMMY(v)              (((v) << 4) & 0x10)
+#define BP_LCDIF_CTRL1_LCD_CS_CTRL                      3
+#define BM_LCDIF_CTRL1_LCD_CS_CTRL                      0x8
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                   (((v) << 3) & 0x8)
+#define BP_LCDIF_CTRL1_BUSY_ENABLE                      2
+#define BM_LCDIF_CTRL1_BUSY_ENABLE                      0x4
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED       0x0
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED        0x1
+#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                   (((v) << 2) & 0x4)
+#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v)                 ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4)
+#define BP_LCDIF_CTRL1_MODE86                           1
+#define BM_LCDIF_CTRL1_MODE86                           0x2
+#define BV_LCDIF_CTRL1_MODE86__8080_MODE                0x0
+#define BV_LCDIF_CTRL1_MODE86__6800_MODE                0x1
+#define BF_LCDIF_CTRL1_MODE86(v)                        (((v) << 1) & 0x2)
+#define BF_LCDIF_CTRL1_MODE86_V(v)                      ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2)
+#define BP_LCDIF_CTRL1_RESET                            0
+#define BM_LCDIF_CTRL1_RESET                            0x1
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW              0x0
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH             0x1
+#define BF_LCDIF_CTRL1_RESET(v)                         (((v) << 0) & 0x1)
+#define BF_LCDIF_CTRL1_RESET_V(v)                       ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LCDIF_TIMING
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
+#define BP_LCDIF_TIMING_CMD_HOLD        24
+#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
+#define BP_LCDIF_TIMING_CMD_SETUP       16
+#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_LCDIF_TIMING_DATA_HOLD       8
+#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_LCDIF_TIMING_DATA_SETUP      0
+#define BM_LCDIF_TIMING_DATA_SETUP      0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL0
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_LCDIF_VDCTRL0                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x0))
+#define HW_LCDIF_VDCTRL0_SET                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x4))
+#define HW_LCDIF_VDCTRL0_CLR                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x8))
+#define HW_LCDIF_VDCTRL0_TOG                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0xc))
+#define BP_LCDIF_VDCTRL0_VSYNC_OEB                  29
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB                  0x20000000
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT    0x0
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT     0x1
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)               (((v) << 29) & 0x20000000)
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v)             ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT             28
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT             0x10000000
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)          (((v) << 28) & 0x10000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_POL                  27
+#define BM_LCDIF_VDCTRL0_VSYNC_POL                  0x8000000
+#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)               (((v) << 27) & 0x8000000)
+#define BP_LCDIF_VDCTRL0_HSYNC_POL                  26
+#define BM_LCDIF_VDCTRL0_HSYNC_POL                  0x4000000
+#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)               (((v) << 26) & 0x4000000)
+#define BP_LCDIF_VDCTRL0_DOTCLK_POL                 25
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL                 0x2000000
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)              (((v) << 25) & 0x2000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_POL                 24
+#define BM_LCDIF_VDCTRL0_ENABLE_POL                 0x1000000
+#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)              (((v) << 24) & 0x1000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          21
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          0x200000
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)       (((v) << 21) & 0x200000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     20
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     0x100000
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)  (((v) << 20) & 0x100000)
+#define BP_LCDIF_VDCTRL0_INTERLACE                  19
+#define BM_LCDIF_VDCTRL0_INTERLACE                  0x80000
+#define BF_LCDIF_VDCTRL0_INTERLACE(v)               (((v) << 19) & 0x80000)
+#define BP_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT    0
+#define BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT    0x3ff
+#define BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(v) (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL1
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL1                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40))
+#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      20
+#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      0xfff00000
+#define BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(v)   (((v) << 20) & 0xfff00000)
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD           0
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD           0xfffff
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)        (((v) << 0) & 0xfffff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL2
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL2                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50))
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          23
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          0xff800000
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)       (((v) << 23) & 0xff800000)
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD               11
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD               0x7ff800
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)            (((v) << 11) & 0x7ff800)
+#define BP_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT    0
+#define BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT    0x7ff
+#define BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL3
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL3                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60))
+#define BP_LCDIF_VDCTRL3_SYNC_SIGNALS_ON        24
+#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON        0x1000000
+#define BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(v)     (((v) << 24) & 0x1000000)
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    12
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0xfff000
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 12) & 0xfff000)
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0x1ff
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)   (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL0
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL0                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70))
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT      20
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT      0x7ff00000
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)   (((v) << 20) & 0x7ff00000)
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT    10
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT    0xffc00
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT       0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT       0x3ff
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL1
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL1                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80))
+#define BP_LCDIF_DVICTRL1_F1_START_LINE     20
+#define BM_LCDIF_DVICTRL1_F1_START_LINE     0x3ff00000
+#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)  (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL1_F1_END_LINE       10
+#define BM_LCDIF_DVICTRL1_F1_END_LINE       0xffc00
+#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL1_F2_START_LINE     0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE     0x3ff
+#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL2
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL2                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90))
+#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
+#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
+#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL3
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL3                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0))
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DATA
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0))
+#define BP_LCDIF_DATA_DATA_THREE    24
+#define BM_LCDIF_DATA_DATA_THREE    0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
+#define BP_LCDIF_DATA_DATA_TWO      16
+#define BM_LCDIF_DATA_DATA_TWO      0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_DATA_DATA_ONE      8
+#define BM_LCDIF_DATA_DATA_ONE      0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
+#define BP_LCDIF_DATA_DATA_ZERO     0
+#define BM_LCDIF_DATA_DATA_ZERO     0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_STAT
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_LCDIF_STAT                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0))
+#define BP_LCDIF_STAT_PRESENT               31
+#define BM_LCDIF_STAT_PRESENT               0x80000000
+#define BF_LCDIF_STAT_PRESENT(v)            (((v) << 31) & 0x80000000)
+#define BP_LCDIF_STAT_DMA_REQ               30
+#define BM_LCDIF_STAT_DMA_REQ               0x40000000
+#define BF_LCDIF_STAT_DMA_REQ(v)            (((v) << 30) & 0x40000000)
+#define BP_LCDIF_STAT_RXFIFO_FULL           29
+#define BM_LCDIF_STAT_RXFIFO_FULL           0x20000000
+#define BF_LCDIF_STAT_RXFIFO_FULL(v)        (((v) << 29) & 0x20000000)
+#define BP_LCDIF_STAT_RXFIFO_EMPTY          28
+#define BM_LCDIF_STAT_RXFIFO_EMPTY          0x10000000
+#define BF_LCDIF_STAT_RXFIFO_EMPTY(v)       (((v) << 28) & 0x10000000)
+#define BP_LCDIF_STAT_TXFIFO_FULL           27
+#define BM_LCDIF_STAT_TXFIFO_FULL           0x8000000
+#define BF_LCDIF_STAT_TXFIFO_FULL(v)        (((v) << 27) & 0x8000000)
+#define BP_LCDIF_STAT_TXFIFO_EMPTY          26
+#define BM_LCDIF_STAT_TXFIFO_EMPTY          0x4000000
+#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)       (((v) << 26) & 0x4000000)
+#define BP_LCDIF_STAT_BUSY                  25
+#define BM_LCDIF_STAT_BUSY                  0x2000000
+#define BF_LCDIF_STAT_BUSY(v)               (((v) << 25) & 0x2000000)
+#define BP_LCDIF_STAT_DVI_CURRENT_FIELD     24
+#define BM_LCDIF_STAT_DVI_CURRENT_FIELD     0x1000000
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)  (((v) << 24) & 0x1000000)
+
+/**
+ * Register: HW_LCDIF_VERSION
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_LCDIF_VERSION            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0))
+#define BP_LCDIF_VERSION_MAJOR      24
+#define BM_LCDIF_VERSION_MAJOR      0xff000000
+#define BF_LCDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_VERSION_MINOR      16
+#define BM_LCDIF_VERSION_MINOR      0xff0000
+#define BF_LCDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_VERSION_STEP       0
+#define BM_LCDIF_VERSION_STEP       0xffff
+#define BF_LCDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_DEBUG0
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_LCDIF_DEBUG0                             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0))
+#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED      31
+#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED      0x80000000
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)   (((v) << 31) & 0x80000000)
+#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     30
+#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     0x40000000
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)  (((v) << 30) & 0x40000000)
+#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         29
+#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         0x20000000
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)      (((v) << 29) & 0x20000000)
+#define BP_LCDIF_DEBUG0_DMACMDKICK                  28
+#define BM_LCDIF_DEBUG0_DMACMDKICK                  0x10000000
+#define BF_LCDIF_DEBUG0_DMACMDKICK(v)               (((v) << 28) & 0x10000000)
+#define BP_LCDIF_DEBUG0_ENABLE                      27
+#define BM_LCDIF_DEBUG0_ENABLE                      0x8000000
+#define BF_LCDIF_DEBUG0_ENABLE(v)                   (((v) << 27) & 0x8000000)
+#define BP_LCDIF_DEBUG0_HSYNC                       26
+#define BM_LCDIF_DEBUG0_HSYNC                       0x4000000
+#define BF_LCDIF_DEBUG0_HSYNC(v)                    (((v) << 26) & 0x4000000)
+#define BP_LCDIF_DEBUG0_VSYNC                       25
+#define BM_LCDIF_DEBUG0_VSYNC                       0x2000000
+#define BF_LCDIF_DEBUG0_VSYNC(v)                    (((v) << 25) & 0x2000000)
+#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                24
+#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                0x1000000
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)             (((v) << 24) & 0x1000000)
+#define BP_LCDIF_DEBUG0_EMPTY_WORD                  23
+#define BM_LCDIF_DEBUG0_EMPTY_WORD                  0x800000
+#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)               (((v) << 23) & 0x800000)
+#define BP_LCDIF_DEBUG0_CUR_STATE                   16
+#define BM_LCDIF_DEBUG0_CUR_STATE                   0x7f0000
+#define BF_LCDIF_DEBUG0_CUR_STATE(v)                (((v) << 16) & 0x7f0000)
+#define BP_LCDIF_DEBUG0_DATA_COUNT                  0
+#define BM_LCDIF_DEBUG0_DATA_COUNT                  0xffff
+#define BF_LCDIF_DEBUG0_DATA_COUNT(v)               (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__LCDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h
new file mode 100644
index 0000000000..ad0beecbae
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h
@@ -0,0 +1,708 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__LRADC__H__
+#define __HEADERGEN__STMP3700__LRADC__H__
+
+#define REGS_LRADC_BASE (0x80050000)
+
+#define REGS_LRADC_VERSION "3.2.0"
+
+/**
+ * Register: HW_LRADC_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL0                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0))
+#define HW_LRADC_CTRL0_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4))
+#define HW_LRADC_CTRL0_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8))
+#define HW_LRADC_CTRL0_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc))
+#define BP_LRADC_CTRL0_SFTRST                   31
+#define BM_LRADC_CTRL0_SFTRST                   0x80000000
+#define BF_LRADC_CTRL0_SFTRST(v)                (((v) << 31) & 0x80000000)
+#define BP_LRADC_CTRL0_CLKGATE                  30
+#define BM_LRADC_CTRL0_CLKGATE                  0x40000000
+#define BF_LRADC_CTRL0_CLKGATE(v)               (((v) << 30) & 0x40000000)
+#define BP_LRADC_CTRL0_ONCHIP_GROUNDREF         21
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF         0x200000
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF    0x0
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON     0x1
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v)      (((v) << 21) & 0x200000)
+#define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v)    ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000)
+#define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE      20
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE      0x100000
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON  0x1
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v)   (((v) << 20) & 0x100000)
+#define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000)
+#define BP_LRADC_CTRL0_YMINUS_ENABLE            19
+#define BM_LRADC_CTRL0_YMINUS_ENABLE            0x80000
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF       0x0
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON        0x1
+#define BF_LRADC_CTRL0_YMINUS_ENABLE(v)         (((v) << 19) & 0x80000)
+#define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000)
+#define BP_LRADC_CTRL0_XMINUS_ENABLE            18
+#define BM_LRADC_CTRL0_XMINUS_ENABLE            0x40000
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF       0x0
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON        0x1
+#define BF_LRADC_CTRL0_XMINUS_ENABLE(v)         (((v) << 18) & 0x40000)
+#define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v)       ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000)
+#define BP_LRADC_CTRL0_YPLUS_ENABLE             17
+#define BM_LRADC_CTRL0_YPLUS_ENABLE             0x20000
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF        0x0
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON         0x1
+#define BF_LRADC_CTRL0_YPLUS_ENABLE(v)          (((v) << 17) & 0x20000)
+#define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000)
+#define BP_LRADC_CTRL0_XPLUS_ENABLE             16
+#define BM_LRADC_CTRL0_XPLUS_ENABLE             0x10000
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF        0x0
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON         0x1
+#define BF_LRADC_CTRL0_XPLUS_ENABLE(v)          (((v) << 16) & 0x10000)
+#define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v)        ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000)
+#define BP_LRADC_CTRL0_SCHEDULE                 0
+#define BM_LRADC_CTRL0_SCHEDULE                 0xff
+#define BF_LRADC_CTRL0_SCHEDULE(v)              (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LRADC_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL1                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0))
+#define HW_LRADC_CTRL1_SET                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4))
+#define HW_LRADC_CTRL1_CLR                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8))
+#define HW_LRADC_CTRL1_TOG                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc))
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          24
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN          0x1000000
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE  0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v)       (((v) << 24) & 0x1000000)
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v)     ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000)
+#define BP_LRADC_CTRL1_LRADC7_IRQ_EN                23
+#define BM_LRADC_CTRL1_LRADC7_IRQ_EN                0x800000
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v)             (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL1_LRADC6_IRQ_EN                22
+#define BM_LRADC_CTRL1_LRADC6_IRQ_EN                0x400000
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v)             (((v) << 22) & 0x400000)
+#define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000)
+#define BP_LRADC_CTRL1_LRADC5_IRQ_EN                21
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN                0x200000
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v)             (((v) << 21) & 0x200000)
+#define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000)
+#define BP_LRADC_CTRL1_LRADC4_IRQ_EN                20
+#define BM_LRADC_CTRL1_LRADC4_IRQ_EN                0x100000
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v)             (((v) << 20) & 0x100000)
+#define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000)
+#define BP_LRADC_CTRL1_LRADC3_IRQ_EN                19
+#define BM_LRADC_CTRL1_LRADC3_IRQ_EN                0x80000
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v)             (((v) << 19) & 0x80000)
+#define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000)
+#define BP_LRADC_CTRL1_LRADC2_IRQ_EN                18
+#define BM_LRADC_CTRL1_LRADC2_IRQ_EN                0x40000
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v)             (((v) << 18) & 0x40000)
+#define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000)
+#define BP_LRADC_CTRL1_LRADC1_IRQ_EN                17
+#define BM_LRADC_CTRL1_LRADC1_IRQ_EN                0x20000
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v)             (((v) << 17) & 0x20000)
+#define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000)
+#define BP_LRADC_CTRL1_LRADC0_IRQ_EN                16
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN                0x10000
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE       0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE        0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v)             (((v) << 16) & 0x10000)
+#define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v)           ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000)
+#define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ             8
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ             0x100
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR      0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING    0x1
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v)          (((v) << 8) & 0x100)
+#define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v)        ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100)
+#define BP_LRADC_CTRL1_LRADC7_IRQ                   7
+#define BM_LRADC_CTRL1_LRADC7_IRQ                   0x80
+#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC7_IRQ(v)                (((v) << 7) & 0x80)
+#define BF_LRADC_CTRL1_LRADC7_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80)
+#define BP_LRADC_CTRL1_LRADC6_IRQ                   6
+#define BM_LRADC_CTRL1_LRADC6_IRQ                   0x40
+#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC6_IRQ(v)                (((v) << 6) & 0x40)
+#define BF_LRADC_CTRL1_LRADC6_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40)
+#define BP_LRADC_CTRL1_LRADC5_IRQ                   5
+#define BM_LRADC_CTRL1_LRADC5_IRQ                   0x20
+#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC5_IRQ(v)                (((v) << 5) & 0x20)
+#define BF_LRADC_CTRL1_LRADC5_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20)
+#define BP_LRADC_CTRL1_LRADC4_IRQ                   4
+#define BM_LRADC_CTRL1_LRADC4_IRQ                   0x10
+#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC4_IRQ(v)                (((v) << 4) & 0x10)
+#define BF_LRADC_CTRL1_LRADC4_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10)
+#define BP_LRADC_CTRL1_LRADC3_IRQ                   3
+#define BM_LRADC_CTRL1_LRADC3_IRQ                   0x8
+#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC3_IRQ(v)                (((v) << 3) & 0x8)
+#define BF_LRADC_CTRL1_LRADC3_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8)
+#define BP_LRADC_CTRL1_LRADC2_IRQ                   2
+#define BM_LRADC_CTRL1_LRADC2_IRQ                   0x4
+#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC2_IRQ(v)                (((v) << 2) & 0x4)
+#define BF_LRADC_CTRL1_LRADC2_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4)
+#define BP_LRADC_CTRL1_LRADC1_IRQ                   1
+#define BM_LRADC_CTRL1_LRADC1_IRQ                   0x2
+#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC1_IRQ(v)                (((v) << 1) & 0x2)
+#define BF_LRADC_CTRL1_LRADC1_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2)
+#define BP_LRADC_CTRL1_LRADC0_IRQ                   0
+#define BM_LRADC_CTRL1_LRADC0_IRQ                   0x1
+#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR            0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING          0x1
+#define BF_LRADC_CTRL1_LRADC0_IRQ(v)                (((v) << 0) & 0x1)
+#define BF_LRADC_CTRL1_LRADC0_IRQ_V(v)              ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL2                                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0))
+#define HW_LRADC_CTRL2_SET                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4))
+#define HW_LRADC_CTRL2_CLR                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8))
+#define HW_LRADC_CTRL2_TOG                              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc))
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO                    24
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO                    0xff000000
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v)                 (((v) << 24) & 0xff000000)
+#define BP_LRADC_CTRL2_BL_AMP_BYPASS                    23
+#define BM_LRADC_CTRL2_BL_AMP_BYPASS                    0x800000
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE           0x0
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE            0x1
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS(v)                 (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v)               ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL2_BL_ENABLE                        22
+#define BM_LRADC_CTRL2_BL_ENABLE                        0x400000
+#define BF_LRADC_CTRL2_BL_ENABLE(v)                     (((v) << 22) & 0x400000)
+#define BP_LRADC_CTRL2_BL_MUX_SELECT                    21
+#define BM_LRADC_CTRL2_BL_MUX_SELECT                    0x200000
+#define BF_LRADC_CTRL2_BL_MUX_SELECT(v)                 (((v) << 21) & 0x200000)
+#define BP_LRADC_CTRL2_BL_BRIGHTNESS                    16
+#define BM_LRADC_CTRL2_BL_BRIGHTNESS                    0x1f0000
+#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v)                 (((v) << 16) & 0x1f0000)
+#define BP_LRADC_CTRL2_TEMPSENSE_PWD                    15
+#define BM_LRADC_CTRL2_TEMPSENSE_PWD                    0x8000
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE           0x0
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE            0x1
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD(v)                 (((v) << 15) & 0x8000)
+#define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v)               ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000)
+#define BP_LRADC_CTRL2_EXT_EN1                          13
+#define BM_LRADC_CTRL2_EXT_EN1                          0x2000
+#define BV_LRADC_CTRL2_EXT_EN1__DISABLE                 0x0
+#define BV_LRADC_CTRL2_EXT_EN1__ENABLE                  0x1
+#define BF_LRADC_CTRL2_EXT_EN1(v)                       (((v) << 13) & 0x2000)
+#define BF_LRADC_CTRL2_EXT_EN1_V(v)                     ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000)
+#define BP_LRADC_CTRL2_EXT_EN0                          12
+#define BM_LRADC_CTRL2_EXT_EN0                          0x1000
+#define BF_LRADC_CTRL2_EXT_EN0(v)                       (((v) << 12) & 0x1000)
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             9
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1             0x200
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v)          (((v) << 9) & 0x200)
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200)
+#define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             8
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0             0x100
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE    0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE     0x1
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v)          (((v) << 8) & 0x100)
+#define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v)        ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100)
+#define BP_LRADC_CTRL2_TEMP_ISRC1                       4
+#define BM_LRADC_CTRL2_TEMP_ISRC1                       0xf0
+#define BV_LRADC_CTRL2_TEMP_ISRC1__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC1__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC1__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC1__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC1__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC1__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC1__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC1__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC1__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC1__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC1__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC1__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC1__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC1__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC1__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC1(v)                    (((v) << 4) & 0xf0)
+#define BF_LRADC_CTRL2_TEMP_ISRC1_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0)
+#define BP_LRADC_CTRL2_TEMP_ISRC0                       0
+#define BM_LRADC_CTRL2_TEMP_ISRC0                       0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__300                  0xf
+#define BV_LRADC_CTRL2_TEMP_ISRC0__280                  0xe
+#define BV_LRADC_CTRL2_TEMP_ISRC0__260                  0xd
+#define BV_LRADC_CTRL2_TEMP_ISRC0__240                  0xc
+#define BV_LRADC_CTRL2_TEMP_ISRC0__220                  0xb
+#define BV_LRADC_CTRL2_TEMP_ISRC0__200                  0xa
+#define BV_LRADC_CTRL2_TEMP_ISRC0__180                  0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC0__160                  0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC0__140                  0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC0__120                  0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC0__100                  0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC0__80                   0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC0__60                   0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC0__40                   0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC0__20                   0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO                 0x0
+#define BF_LRADC_CTRL2_TEMP_ISRC0(v)                    (((v) << 0) & 0xf)
+#define BF_LRADC_CTRL2_TEMP_ISRC0_V(v)                  ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf)
+
+/**
+ * Register: HW_LRADC_CTRL3
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL3                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0))
+#define HW_LRADC_CTRL3_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4))
+#define HW_LRADC_CTRL3_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8))
+#define HW_LRADC_CTRL3_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc))
+#define BP_LRADC_CTRL3_DISCARD                  24
+#define BM_LRADC_CTRL3_DISCARD                  0x3000000
+#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE        0x1
+#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES       0x2
+#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES       0x3
+#define BF_LRADC_CTRL3_DISCARD(v)               (((v) << 24) & 0x3000000)
+#define BF_LRADC_CTRL3_DISCARD_V(v)             ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000)
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP        23
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP        0x800000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF   0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON    0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v)     (((v) << 23) & 0x800000)
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000)
+#define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN        22
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN        0x400000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON    0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF   0x1
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v)     (((v) << 22) & 0x400000)
+#define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v)   ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000)
+#define BP_LRADC_CTRL3_CYCLE_TIME               8
+#define BM_LRADC_CTRL3_CYCLE_TIME               0x300
+#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ         0x0
+#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ         0x1
+#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ         0x2
+#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ         0x3
+#define BF_LRADC_CTRL3_CYCLE_TIME(v)            (((v) << 8) & 0x300)
+#define BF_LRADC_CTRL3_CYCLE_TIME_V(v)          ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300)
+#define BP_LRADC_CTRL3_HIGH_TIME                4
+#define BM_LRADC_CTRL3_HIGH_TIME                0x30
+#define BV_LRADC_CTRL3_HIGH_TIME__42NS          0x0
+#define BV_LRADC_CTRL3_HIGH_TIME__83NS          0x1
+#define BV_LRADC_CTRL3_HIGH_TIME__125NS         0x2
+#define BV_LRADC_CTRL3_HIGH_TIME__250NS         0x3
+#define BF_LRADC_CTRL3_HIGH_TIME(v)             (((v) << 4) & 0x30)
+#define BF_LRADC_CTRL3_HIGH_TIME_V(v)           ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30)
+#define BP_LRADC_CTRL3_DELAY_CLOCK              1
+#define BM_LRADC_CTRL3_DELAY_CLOCK              0x2
+#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL      0x0
+#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED     0x1
+#define BF_LRADC_CTRL3_DELAY_CLOCK(v)           (((v) << 1) & 0x2)
+#define BF_LRADC_CTRL3_DELAY_CLOCK_V(v)         ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2)
+#define BP_LRADC_CTRL3_INVERT_CLOCK             0
+#define BM_LRADC_CTRL3_INVERT_CLOCK             0x1
+#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL     0x0
+#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT     0x1
+#define BF_LRADC_CTRL3_INVERT_CLOCK(v)          (((v) << 0) & 0x1)
+#define BF_LRADC_CTRL3_INVERT_CLOCK_V(v)        ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_STATUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_LRADC_STATUS                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40))
+#define BP_LRADC_STATUS_TEMP1_PRESENT           26
+#define BM_LRADC_STATUS_TEMP1_PRESENT           0x4000000
+#define BF_LRADC_STATUS_TEMP1_PRESENT(v)        (((v) << 26) & 0x4000000)
+#define BP_LRADC_STATUS_TEMP0_PRESENT           25
+#define BM_LRADC_STATUS_TEMP0_PRESENT           0x2000000
+#define BF_LRADC_STATUS_TEMP0_PRESENT(v)        (((v) << 25) & 0x2000000)
+#define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT     24
+#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT     0x1000000
+#define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v)  (((v) << 24) & 0x1000000)
+#define BP_LRADC_STATUS_CHANNEL7_PRESENT        23
+#define BM_LRADC_STATUS_CHANNEL7_PRESENT        0x800000
+#define BF_LRADC_STATUS_CHANNEL7_PRESENT(v)     (((v) << 23) & 0x800000)
+#define BP_LRADC_STATUS_CHANNEL6_PRESENT        22
+#define BM_LRADC_STATUS_CHANNEL6_PRESENT        0x400000
+#define BF_LRADC_STATUS_CHANNEL6_PRESENT(v)     (((v) << 22) & 0x400000)
+#define BP_LRADC_STATUS_CHANNEL5_PRESENT        21
+#define BM_LRADC_STATUS_CHANNEL5_PRESENT        0x200000
+#define BF_LRADC_STATUS_CHANNEL5_PRESENT(v)     (((v) << 21) & 0x200000)
+#define BP_LRADC_STATUS_CHANNEL4_PRESENT        20
+#define BM_LRADC_STATUS_CHANNEL4_PRESENT        0x100000
+#define BF_LRADC_STATUS_CHANNEL4_PRESENT(v)     (((v) << 20) & 0x100000)
+#define BP_LRADC_STATUS_CHANNEL3_PRESENT        19
+#define BM_LRADC_STATUS_CHANNEL3_PRESENT        0x80000
+#define BF_LRADC_STATUS_CHANNEL3_PRESENT(v)     (((v) << 19) & 0x80000)
+#define BP_LRADC_STATUS_CHANNEL2_PRESENT        18
+#define BM_LRADC_STATUS_CHANNEL2_PRESENT        0x40000
+#define BF_LRADC_STATUS_CHANNEL2_PRESENT(v)     (((v) << 18) & 0x40000)
+#define BP_LRADC_STATUS_CHANNEL1_PRESENT        17
+#define BM_LRADC_STATUS_CHANNEL1_PRESENT        0x20000
+#define BF_LRADC_STATUS_CHANNEL1_PRESENT(v)     (((v) << 17) & 0x20000)
+#define BP_LRADC_STATUS_CHANNEL0_PRESENT        16
+#define BM_LRADC_STATUS_CHANNEL0_PRESENT        0x10000
+#define BF_LRADC_STATUS_CHANNEL0_PRESENT(v)     (((v) << 16) & 0x10000)
+#define BP_LRADC_STATUS_TOUCH_DETECT_RAW        0
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW        0x1
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN  0x0
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT   0x1
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v)     (((v) << 0) & 0x1)
+#define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v)   ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CHn
+ * Address: 0x50+n*0x10
+ * SCT: yes
+*/
+#define HW_LRADC_CHn(n)             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0))
+#define HW_LRADC_CHn_SET(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4))
+#define HW_LRADC_CHn_CLR(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8))
+#define HW_LRADC_CHn_TOG(n)         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc))
+#define BP_LRADC_CHn_TOGGLE         31
+#define BM_LRADC_CHn_TOGGLE         0x80000000
+#define BF_LRADC_CHn_TOGGLE(v)      (((v) << 31) & 0x80000000)
+#define BP_LRADC_CHn_ACCUMULATE     29
+#define BM_LRADC_CHn_ACCUMULATE     0x20000000
+#define BF_LRADC_CHn_ACCUMULATE(v)  (((v) << 29) & 0x20000000)
+#define BP_LRADC_CHn_NUM_SAMPLES    24
+#define BM_LRADC_CHn_NUM_SAMPLES    0x1f000000
+#define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000)
+#define BP_LRADC_CHn_VALUE          0
+#define BM_LRADC_CHn_VALUE          0x3ffff
+#define BF_LRADC_CHn_VALUE(v)       (((v) << 0) & 0x3ffff)
+
+/**
+ * Register: HW_LRADC_DELAYn
+ * Address: 0xd0+n*0x10
+ * SCT: yes
+*/
+#define HW_LRADC_DELAYn(n)                  (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0))
+#define HW_LRADC_DELAYn_SET(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4))
+#define HW_LRADC_DELAYn_CLR(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8))
+#define HW_LRADC_DELAYn_TOG(n)              (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc))
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS      24
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS      0xff000000
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v)   (((v) << 24) & 0xff000000)
+#define BP_LRADC_DELAYn_KICK                20
+#define BM_LRADC_DELAYn_KICK                0x100000
+#define BF_LRADC_DELAYn_KICK(v)             (((v) << 20) & 0x100000)
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS      16
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS      0xf0000
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v)   (((v) << 16) & 0xf0000)
+#define BP_LRADC_DELAYn_LOOP_COUNT          11
+#define BM_LRADC_DELAYn_LOOP_COUNT          0xf800
+#define BF_LRADC_DELAYn_LOOP_COUNT(v)       (((v) << 11) & 0xf800)
+#define BP_LRADC_DELAYn_DELAY               0
+#define BM_LRADC_DELAYn_DELAY               0x7ff
+#define BF_LRADC_DELAYn_DELAY(v)            (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_LRADC_DEBUG0
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_LRADC_DEBUG0             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110))
+#define BP_LRADC_DEBUG0_READONLY    16
+#define BM_LRADC_DEBUG0_READONLY    0xffff0000
+#define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000)
+#define BP_LRADC_DEBUG0_STATE       0
+#define BM_LRADC_DEBUG0_STATE       0xfff
+#define BF_LRADC_DEBUG0_STATE(v)    (((v) << 0) & 0xfff)
+
+/**
+ * Register: HW_LRADC_DEBUG1
+ * Address: 0x120
+ * SCT: yes
+*/
+#define HW_LRADC_DEBUG1                     (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0))
+#define HW_LRADC_DEBUG1_SET                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4))
+#define HW_LRADC_DEBUG1_CLR                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8))
+#define HW_LRADC_DEBUG1_TOG                 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc))
+#define BP_LRADC_DEBUG1_REQUEST             16
+#define BM_LRADC_DEBUG1_REQUEST             0xff0000
+#define BF_LRADC_DEBUG1_REQUEST(v)          (((v) << 16) & 0xff0000)
+#define BP_LRADC_DEBUG1_TESTMODE_COUNT      8
+#define BM_LRADC_DEBUG1_TESTMODE_COUNT      0x1f00
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v)   (((v) << 8) & 0x1f00)
+#define BP_LRADC_DEBUG1_TESTMODE6           2
+#define BM_LRADC_DEBUG1_TESTMODE6           0x4
+#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL   0x0
+#define BV_LRADC_DEBUG1_TESTMODE6__TEST     0x1
+#define BF_LRADC_DEBUG1_TESTMODE6(v)        (((v) << 2) & 0x4)
+#define BF_LRADC_DEBUG1_TESTMODE6_V(v)      ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4)
+#define BP_LRADC_DEBUG1_TESTMODE5           1
+#define BM_LRADC_DEBUG1_TESTMODE5           0x2
+#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL   0x0
+#define BV_LRADC_DEBUG1_TESTMODE5__TEST     0x1
+#define BF_LRADC_DEBUG1_TESTMODE5(v)        (((v) << 1) & 0x2)
+#define BF_LRADC_DEBUG1_TESTMODE5_V(v)      ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2)
+#define BP_LRADC_DEBUG1_TESTMODE            0
+#define BM_LRADC_DEBUG1_TESTMODE            0x1
+#define BV_LRADC_DEBUG1_TESTMODE__NORMAL    0x0
+#define BV_LRADC_DEBUG1_TESTMODE__TEST      0x1
+#define BF_LRADC_DEBUG1_TESTMODE(v)         (((v) << 0) & 0x1)
+#define BF_LRADC_DEBUG1_TESTMODE_V(v)       ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LRADC_CONVERSION
+ * Address: 0x130
+ * SCT: yes
+*/
+#define HW_LRADC_CONVERSION                             (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0))
+#define HW_LRADC_CONVERSION_SET                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4))
+#define HW_LRADC_CONVERSION_CLR                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8))
+#define HW_LRADC_CONVERSION_TOG                         (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc))
+#define BP_LRADC_CONVERSION_AUTOMATIC                   20
+#define BM_LRADC_CONVERSION_AUTOMATIC                   0x100000
+#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE          0x0
+#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE           0x1
+#define BF_LRADC_CONVERSION_AUTOMATIC(v)                (((v) << 20) & 0x100000)
+#define BF_LRADC_CONVERSION_AUTOMATIC_V(v)              ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000)
+#define BP_LRADC_CONVERSION_SCALE_FACTOR                16
+#define BM_LRADC_CONVERSION_SCALE_FACTOR                0x30000
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH          0x0
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH     0x1
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION        0x2
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION    0x3
+#define BF_LRADC_CONVERSION_SCALE_FACTOR(v)             (((v) << 16) & 0x30000)
+#define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v)           ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000)
+#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0
+#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE         0x3ff
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LRADC_CTRL4
+ * Address: 0x140
+ * SCT: yes
+*/
+#define HW_LRADC_CTRL4                          (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0))
+#define HW_LRADC_CTRL4_SET                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4))
+#define HW_LRADC_CTRL4_CLR                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8))
+#define HW_LRADC_CTRL4_TOG                      (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc))
+#define BP_LRADC_CTRL4_LRADC7SELECT             28
+#define BM_LRADC_CTRL4_LRADC7SELECT             0xf0000000
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC7SELECT(v)          (((v) << 28) & 0xf0000000)
+#define BF_LRADC_CTRL4_LRADC7SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000)
+#define BP_LRADC_CTRL4_LRADC6SELECT             24
+#define BM_LRADC_CTRL4_LRADC6SELECT             0xf000000
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC6SELECT(v)          (((v) << 24) & 0xf000000)
+#define BF_LRADC_CTRL4_LRADC6SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000)
+#define BP_LRADC_CTRL4_LRADC5SELECT             20
+#define BM_LRADC_CTRL4_LRADC5SELECT             0xf00000
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC5SELECT(v)          (((v) << 20) & 0xf00000)
+#define BF_LRADC_CTRL4_LRADC5SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000)
+#define BP_LRADC_CTRL4_LRADC4SELECT             16
+#define BM_LRADC_CTRL4_LRADC4SELECT             0xf0000
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC4SELECT(v)          (((v) << 16) & 0xf0000)
+#define BF_LRADC_CTRL4_LRADC4SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000)
+#define BP_LRADC_CTRL4_LRADC3SELECT             12
+#define BM_LRADC_CTRL4_LRADC3SELECT             0xf000
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC3SELECT(v)          (((v) << 12) & 0xf000)
+#define BF_LRADC_CTRL4_LRADC3SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000)
+#define BP_LRADC_CTRL4_LRADC2SELECT             8
+#define BM_LRADC_CTRL4_LRADC2SELECT             0xf00
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC2SELECT(v)          (((v) << 8) & 0xf00)
+#define BF_LRADC_CTRL4_LRADC2SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00)
+#define BP_LRADC_CTRL4_LRADC1SELECT             4
+#define BM_LRADC_CTRL4_LRADC1SELECT             0xf0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC1SELECT(v)          (((v) << 4) & 0xf0)
+#define BF_LRADC_CTRL4_LRADC1SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0)
+#define BP_LRADC_CTRL4_LRADC0SELECT             0
+#define BM_LRADC_CTRL4_LRADC0SELECT             0xf
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0   0x0
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1   0x1
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2   0x2
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3   0x3
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4   0x4
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5   0x5
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6   0x6
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7   0x7
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8   0x8
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9   0x9
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10  0xa
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11  0xb
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12  0xc
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13  0xd
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14  0xe
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15  0xf
+#define BF_LRADC_CTRL4_LRADC0SELECT(v)          (((v) << 0) & 0xf)
+#define BF_LRADC_CTRL4_LRADC0SELECT_V(v)        ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_LRADC_VERSION
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_LRADC_VERSION            (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150))
+#define BP_LRADC_VERSION_MAJOR      24
+#define BM_LRADC_VERSION_MAJOR      0xff000000
+#define BF_LRADC_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_LRADC_VERSION_MINOR      16
+#define BM_LRADC_VERSION_MINOR      0xff0000
+#define BF_LRADC_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_LRADC_VERSION_STEP       0
+#define BM_LRADC_VERSION_STEP       0xffff
+#define BF_LRADC_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__LRADC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h
new file mode 100644
index 0000000000..082952fc95
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h
@@ -0,0 +1,254 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__OCOTP__H__
+#define __HEADERGEN__STMP3700__OCOTP__H__
+
+#define REGS_OCOTP_BASE (0x8002c000)
+
+#define REGS_OCOTP_VERSION "3.2.0"
+
+/**
+ * Register: HW_OCOTP_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_OCOTP_CTRL                   (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x0))
+#define HW_OCOTP_CTRL_SET               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x4))
+#define HW_OCOTP_CTRL_CLR               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x8))
+#define HW_OCOTP_CTRL_TOG               (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0xc))
+#define BP_OCOTP_CTRL_WR_UNLOCK         16
+#define BM_OCOTP_CTRL_WR_UNLOCK         0xffff0000
+#define BV_OCOTP_CTRL_WR_UNLOCK__KEY    0x3e77
+#define BF_OCOTP_CTRL_WR_UNLOCK(v)      (((v) << 16) & 0xffff0000)
+#define BF_OCOTP_CTRL_WR_UNLOCK_V(v)    ((BV_OCOTP_CTRL_WR_UNLOCK__##v << 16) & 0xffff0000)
+#define BP_OCOTP_CTRL_RELOAD_SHADOWS    13
+#define BM_OCOTP_CTRL_RELOAD_SHADOWS    0x2000
+#define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) (((v) << 13) & 0x2000)
+#define BP_OCOTP_CTRL_RD_BANK_OPEN      12
+#define BM_OCOTP_CTRL_RD_BANK_OPEN      0x1000
+#define BF_OCOTP_CTRL_RD_BANK_OPEN(v)   (((v) << 12) & 0x1000)
+#define BP_OCOTP_CTRL_ERROR             9
+#define BM_OCOTP_CTRL_ERROR             0x200
+#define BF_OCOTP_CTRL_ERROR(v)          (((v) << 9) & 0x200)
+#define BP_OCOTP_CTRL_BUSY              8
+#define BM_OCOTP_CTRL_BUSY              0x100
+#define BF_OCOTP_CTRL_BUSY(v)           (((v) << 8) & 0x100)
+#define BP_OCOTP_CTRL_ADDR              0
+#define BM_OCOTP_CTRL_ADDR              0x1f
+#define BF_OCOTP_CTRL_ADDR(v)           (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_OCOTP_DATA
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_OCOTP_DATA           (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x10))
+#define BP_OCOTP_DATA_DATA      0
+#define BM_OCOTP_DATA_DATA      0xffffffff
+#define BF_OCOTP_DATA_DATA(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_CUSTn
+ * Address: 0x20+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_CUSTn(n)       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x20+(n)*0x10))
+#define BP_OCOTP_CUSTn_BITS     0
+#define BM_OCOTP_CUSTn_BITS     0xffffffff
+#define BF_OCOTP_CUSTn_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_CRYPTOn
+ * Address: 0x60+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_CRYPTOn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x60+(n)*0x10))
+#define BP_OCOTP_CRYPTOn_BITS       0
+#define BM_OCOTP_CRYPTOn_BITS       0xffffffff
+#define BF_OCOTP_CRYPTOn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_HWCAPn
+ * Address: 0xa0+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_HWCAPn(n)      (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0xa0+(n)*0x10))
+#define BP_OCOTP_HWCAPn_BITS    0
+#define BM_OCOTP_HWCAPn_BITS    0xffffffff
+#define BF_OCOTP_HWCAPn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_SWCAP
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_OCOTP_SWCAP          (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x100))
+#define BP_OCOTP_SWCAP_BITS     0
+#define BM_OCOTP_SWCAP_BITS     0xffffffff
+#define BF_OCOTP_SWCAP_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_CUSTCAP
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_OCOTP_CUSTCAP            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x110))
+#define BP_OCOTP_CUSTCAP_BITS       0
+#define BM_OCOTP_CUSTCAP_BITS       0xffffffff
+#define BF_OCOTP_CUSTCAP_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_LOCK
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_OCOTP_LOCK                       (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x120))
+#define BP_OCOTP_LOCK_ROM7                  31
+#define BM_OCOTP_LOCK_ROM7                  0x80000000
+#define BF_OCOTP_LOCK_ROM7(v)               (((v) << 31) & 0x80000000)
+#define BP_OCOTP_LOCK_ROM6                  30
+#define BM_OCOTP_LOCK_ROM6                  0x40000000
+#define BF_OCOTP_LOCK_ROM6(v)               (((v) << 30) & 0x40000000)
+#define BP_OCOTP_LOCK_ROM5                  29
+#define BM_OCOTP_LOCK_ROM5                  0x20000000
+#define BF_OCOTP_LOCK_ROM5(v)               (((v) << 29) & 0x20000000)
+#define BP_OCOTP_LOCK_ROM4                  28
+#define BM_OCOTP_LOCK_ROM4                  0x10000000
+#define BF_OCOTP_LOCK_ROM4(v)               (((v) << 28) & 0x10000000)
+#define BP_OCOTP_LOCK_ROM3                  27
+#define BM_OCOTP_LOCK_ROM3                  0x8000000
+#define BF_OCOTP_LOCK_ROM3(v)               (((v) << 27) & 0x8000000)
+#define BP_OCOTP_LOCK_ROM2                  26
+#define BM_OCOTP_LOCK_ROM2                  0x4000000
+#define BF_OCOTP_LOCK_ROM2(v)               (((v) << 26) & 0x4000000)
+#define BP_OCOTP_LOCK_ROM1                  25
+#define BM_OCOTP_LOCK_ROM1                  0x2000000
+#define BF_OCOTP_LOCK_ROM1(v)               (((v) << 25) & 0x2000000)
+#define BP_OCOTP_LOCK_ROM0                  24
+#define BM_OCOTP_LOCK_ROM0                  0x1000000
+#define BF_OCOTP_LOCK_ROM0(v)               (((v) << 24) & 0x1000000)
+#define BP_OCOTP_LOCK_HWSW_SHADOW_ALT       23
+#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT       0x800000
+#define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v)    (((v) << 23) & 0x800000)
+#define BP_OCOTP_LOCK_CRYPTODCP_ALT         22
+#define BM_OCOTP_LOCK_CRYPTODCP_ALT         0x400000
+#define BF_OCOTP_LOCK_CRYPTODCP_ALT(v)      (((v) << 22) & 0x400000)
+#define BP_OCOTP_LOCK_CRYPTOKEY_ALT         21
+#define BM_OCOTP_LOCK_CRYPTOKEY_ALT         0x200000
+#define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v)      (((v) << 21) & 0x200000)
+#define BP_OCOTP_LOCK_PIN                   20
+#define BM_OCOTP_LOCK_PIN                   0x100000
+#define BF_OCOTP_LOCK_PIN(v)                (((v) << 20) & 0x100000)
+#define BP_OCOTP_LOCK_OPS                   19
+#define BM_OCOTP_LOCK_OPS                   0x80000
+#define BF_OCOTP_LOCK_OPS(v)                (((v) << 19) & 0x80000)
+#define BP_OCOTP_LOCK_UN2                   18
+#define BM_OCOTP_LOCK_UN2                   0x40000
+#define BF_OCOTP_LOCK_UN2(v)                (((v) << 18) & 0x40000)
+#define BP_OCOTP_LOCK_UN1                   17
+#define BM_OCOTP_LOCK_UN1                   0x20000
+#define BF_OCOTP_LOCK_UN1(v)                (((v) << 17) & 0x20000)
+#define BP_OCOTP_LOCK_UN0                   16
+#define BM_OCOTP_LOCK_UN0                   0x10000
+#define BF_OCOTP_LOCK_UN0(v)                (((v) << 16) & 0x10000)
+#define BP_OCOTP_LOCK_UNALLOCATED           10
+#define BM_OCOTP_LOCK_UNALLOCATED           0xfc00
+#define BF_OCOTP_LOCK_UNALLOCATED(v)        (((v) << 10) & 0xfc00)
+#define BP_OCOTP_LOCK_CUSTCAP               9
+#define BM_OCOTP_LOCK_CUSTCAP               0x200
+#define BF_OCOTP_LOCK_CUSTCAP(v)            (((v) << 9) & 0x200)
+#define BP_OCOTP_LOCK_HWSW                  8
+#define BM_OCOTP_LOCK_HWSW                  0x100
+#define BF_OCOTP_LOCK_HWSW(v)               (((v) << 8) & 0x100)
+#define BP_OCOTP_LOCK_CUSTCAP_SHADOW        7
+#define BM_OCOTP_LOCK_CUSTCAP_SHADOW        0x80
+#define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v)     (((v) << 7) & 0x80)
+#define BP_OCOTP_LOCK_HWSW_SHADOW           6
+#define BM_OCOTP_LOCK_HWSW_SHADOW           0x40
+#define BF_OCOTP_LOCK_HWSW_SHADOW(v)        (((v) << 6) & 0x40)
+#define BP_OCOTP_LOCK_CRYPTODCP             5
+#define BM_OCOTP_LOCK_CRYPTODCP             0x20
+#define BF_OCOTP_LOCK_CRYPTODCP(v)          (((v) << 5) & 0x20)
+#define BP_OCOTP_LOCK_CRYPTOKEY             4
+#define BM_OCOTP_LOCK_CRYPTOKEY             0x10
+#define BF_OCOTP_LOCK_CRYPTOKEY(v)          (((v) << 4) & 0x10)
+#define BP_OCOTP_LOCK_CUST3                 3
+#define BM_OCOTP_LOCK_CUST3                 0x8
+#define BF_OCOTP_LOCK_CUST3(v)              (((v) << 3) & 0x8)
+#define BP_OCOTP_LOCK_CUST2                 2
+#define BM_OCOTP_LOCK_CUST2                 0x4
+#define BF_OCOTP_LOCK_CUST2(v)              (((v) << 2) & 0x4)
+#define BP_OCOTP_LOCK_CUST1                 1
+#define BM_OCOTP_LOCK_CUST1                 0x2
+#define BF_OCOTP_LOCK_CUST1(v)              (((v) << 1) & 0x2)
+#define BP_OCOTP_LOCK_CUST0                 0
+#define BM_OCOTP_LOCK_CUST0                 0x1
+#define BF_OCOTP_LOCK_CUST0(v)              (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_OCOTP_OPSn
+ * Address: 0x130+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_OPSn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x130+(n)*0x10))
+#define BP_OCOTP_OPSn_BITS      0
+#define BM_OCOTP_OPSn_BITS      0xffffffff
+#define BF_OCOTP_OPSn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_UNn
+ * Address: 0x170+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_UNn(n)         (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x170+(n)*0x10))
+#define BP_OCOTP_UNn_BITS       0
+#define BM_OCOTP_UNn_BITS       0xffffffff
+#define BF_OCOTP_UNn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_ROMn
+ * Address: 0x1a0+n*0x10
+ * SCT: no
+*/
+#define HW_OCOTP_ROMn(n)        (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x1a0+(n)*0x10))
+#define BP_OCOTP_ROMn_BITS      0
+#define BM_OCOTP_ROMn_BITS      0xffffffff
+#define BF_OCOTP_ROMn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_OCOTP_VERSION
+ * Address: 0x220
+ * SCT: no
+*/
+#define HW_OCOTP_VERSION            (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x220))
+#define BP_OCOTP_VERSION_MAJOR      24
+#define BM_OCOTP_VERSION_MAJOR      0xff000000
+#define BF_OCOTP_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_OCOTP_VERSION_MINOR      16
+#define BM_OCOTP_VERSION_MINOR      0xff0000
+#define BF_OCOTP_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_OCOTP_VERSION_STEP       0
+#define BM_OCOTP_VERSION_STEP       0xffff
+#define BF_OCOTP_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__OCOTP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
new file mode 100644
index 0000000000..bddc2dcfa9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h
@@ -0,0 +1,213 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__PINCTRL__H__
+#define __HEADERGEN__STMP3700__PINCTRL__H__
+
+#define REGS_PINCTRL_BASE (0x80018000)
+
+#define REGS_PINCTRL_VERSION "3.2.0"
+
+/**
+ * Register: HW_PINCTRL_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_PINCTRL_CTRL             (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0))
+#define HW_PINCTRL_CTRL_SET         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4))
+#define HW_PINCTRL_CTRL_CLR         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8))
+#define HW_PINCTRL_CTRL_TOG         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc))
+#define BP_PINCTRL_CTRL_SFTRST      31
+#define BM_PINCTRL_CTRL_SFTRST      0x80000000
+#define BF_PINCTRL_CTRL_SFTRST(v)   (((v) << 31) & 0x80000000)
+#define BP_PINCTRL_CTRL_CLKGATE     30
+#define BM_PINCTRL_CTRL_CLKGATE     0x40000000
+#define BF_PINCTRL_CTRL_CLKGATE(v)  (((v) << 30) & 0x40000000)
+#define BP_PINCTRL_CTRL_PRESENT3    29
+#define BM_PINCTRL_CTRL_PRESENT3    0x20000000
+#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000)
+#define BP_PINCTRL_CTRL_PRESENT2    28
+#define BM_PINCTRL_CTRL_PRESENT2    0x10000000
+#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000)
+#define BP_PINCTRL_CTRL_PRESENT1    27
+#define BM_PINCTRL_CTRL_PRESENT1    0x8000000
+#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000)
+#define BP_PINCTRL_CTRL_PRESENT0    26
+#define BM_PINCTRL_CTRL_PRESENT0    0x4000000
+#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000)
+#define BP_PINCTRL_CTRL_IRQOUT3     3
+#define BM_PINCTRL_CTRL_IRQOUT3     0x8
+#define BF_PINCTRL_CTRL_IRQOUT3(v)  (((v) << 3) & 0x8)
+#define BP_PINCTRL_CTRL_IRQOUT2     2
+#define BM_PINCTRL_CTRL_IRQOUT2     0x4
+#define BF_PINCTRL_CTRL_IRQOUT2(v)  (((v) << 2) & 0x4)
+#define BP_PINCTRL_CTRL_IRQOUT1     1
+#define BM_PINCTRL_CTRL_IRQOUT1     0x2
+#define BF_PINCTRL_CTRL_IRQOUT1(v)  (((v) << 1) & 0x2)
+#define BP_PINCTRL_CTRL_IRQOUT0     0
+#define BM_PINCTRL_CTRL_IRQOUT0     0x1
+#define BF_PINCTRL_CTRL_IRQOUT0(v)  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PINCTRL_MUXSELn
+ * Address: 0x100+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_MUXSELn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0))
+#define HW_PINCTRL_MUXSELn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4))
+#define HW_PINCTRL_MUXSELn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8))
+#define HW_PINCTRL_MUXSELn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc))
+#define BP_PINCTRL_MUXSELn_BITS     0
+#define BM_PINCTRL_MUXSELn_BITS     0xffffffff
+#define BF_PINCTRL_MUXSELn_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DRIVEn
+ * Address: 0x200+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DRIVEn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DRIVEn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DRIVEn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DRIVEn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DRIVEn_BITS      0
+#define BM_PINCTRL_DRIVEn_BITS      0xffffffff
+#define BF_PINCTRL_DRIVEn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_PULLn
+ * Address: 0x300+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_PULLn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x0))
+#define HW_PINCTRL_PULLn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x4))
+#define HW_PINCTRL_PULLn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x8))
+#define HW_PINCTRL_PULLn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0xc))
+#define BP_PINCTRL_PULLn_BITS       0
+#define BM_PINCTRL_PULLn_BITS       0xffffffff
+#define BF_PINCTRL_PULLn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DOUTn
+ * Address: 0x400+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DOUTn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DOUTn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DOUTn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DOUTn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DOUTn_BITS       0
+#define BM_PINCTRL_DOUTn_BITS       0xffffffff
+#define BF_PINCTRL_DOUTn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DINn
+ * Address: 0x500+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DINn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DINn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DINn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DINn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DINn_BITS    0
+#define BM_PINCTRL_DINn_BITS    0xffffffff
+#define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_DOEn
+ * Address: 0x600+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_DOEn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0))
+#define HW_PINCTRL_DOEn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4))
+#define HW_PINCTRL_DOEn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8))
+#define HW_PINCTRL_DOEn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc))
+#define BP_PINCTRL_DOEn_BITS    0
+#define BM_PINCTRL_DOEn_BITS    0xffffffff
+#define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_PIN2IRQn
+ * Address: 0x700+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_PIN2IRQn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0))
+#define HW_PINCTRL_PIN2IRQn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4))
+#define HW_PINCTRL_PIN2IRQn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8))
+#define HW_PINCTRL_PIN2IRQn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc))
+#define BP_PINCTRL_PIN2IRQn_BITS    0
+#define BM_PINCTRL_PIN2IRQn_BITS    0xffffffff
+#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQENn
+ * Address: 0x800+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQENn(n)        (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQENn_SET(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQENn_CLR(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQENn_TOG(n)    (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQENn_BITS      0
+#define BM_PINCTRL_IRQENn_BITS      0xffffffff
+#define BF_PINCTRL_IRQENn_BITS(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQLEVELn
+ * Address: 0x900+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQLEVELn(n)         (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQLEVELn_SET(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQLEVELn_CLR(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQLEVELn_TOG(n)     (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQLEVELn_BITS       0
+#define BM_PINCTRL_IRQLEVELn_BITS       0xffffffff
+#define BF_PINCTRL_IRQLEVELn_BITS(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQPOLn
+ * Address: 0xa00+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQPOLn(n)       (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQPOLn_SET(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQPOLn_CLR(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQPOLn_TOG(n)   (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQPOLn_BITS     0
+#define BM_PINCTRL_IRQPOLn_BITS     0xffffffff
+#define BF_PINCTRL_IRQPOLn_BITS(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_PINCTRL_IRQSTATn
+ * Address: 0xb00+n*0x10
+ * SCT: yes
+*/
+#define HW_PINCTRL_IRQSTATn(n)      (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0))
+#define HW_PINCTRL_IRQSTATn_SET(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4))
+#define HW_PINCTRL_IRQSTATn_CLR(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8))
+#define HW_PINCTRL_IRQSTATn_TOG(n)  (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc))
+#define BP_PINCTRL_IRQSTATn_BITS    0
+#define BM_PINCTRL_IRQSTATn_BITS    0xffffffff
+#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff)
+
+#endif /* __HEADERGEN__STMP3700__PINCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-power.h b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h
new file mode 100644
index 0000000000..85116c79cb
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h
@@ -0,0 +1,581 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__POWER__H__
+#define __HEADERGEN__STMP3700__POWER__H__
+
+#define REGS_POWER_BASE (0x80044000)
+
+#define REGS_POWER_VERSION "3.2.0"
+
+/**
+ * Register: HW_POWER_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_POWER_CTRL                               (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0))
+#define HW_POWER_CTRL_SET                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4))
+#define HW_POWER_CTRL_CLR                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8))
+#define HW_POWER_CTRL_TOG                           (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc))
+#define BP_POWER_CTRL_CLKGATE                       30
+#define BM_POWER_CTRL_CLKGATE                       0x40000000
+#define BF_POWER_CTRL_CLKGATE(v)                    (((v) << 30) & 0x40000000)
+#define BP_POWER_CTRL_PSWITCH_IRQ                   22
+#define BM_POWER_CTRL_PSWITCH_IRQ                   0x400000
+#define BF_POWER_CTRL_PSWITCH_IRQ(v)                (((v) << 22) & 0x400000)
+#define BP_POWER_CTRL_PSWITCH_IRQ_SRC               21
+#define BM_POWER_CTRL_PSWITCH_IRQ_SRC               0x200000
+#define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v)            (((v) << 21) & 0x200000)
+#define BP_POWER_CTRL_POLARITY_PSWITCH              20
+#define BM_POWER_CTRL_POLARITY_PSWITCH              0x100000
+#define BF_POWER_CTRL_POLARITY_PSWITCH(v)           (((v) << 20) & 0x100000)
+#define BP_POWER_CTRL_ENIRQ_PSWITCH                 19
+#define BM_POWER_CTRL_ENIRQ_PSWITCH                 0x80000
+#define BF_POWER_CTRL_ENIRQ_PSWITCH(v)              (((v) << 19) & 0x80000)
+#define BP_POWER_CTRL_POLARITY_LINREG_OK            18
+#define BM_POWER_CTRL_POLARITY_LINREG_OK            0x40000
+#define BF_POWER_CTRL_POLARITY_LINREG_OK(v)         (((v) << 18) & 0x40000)
+#define BP_POWER_CTRL_LINREG_OK_IRQ                 17
+#define BM_POWER_CTRL_LINREG_OK_IRQ                 0x20000
+#define BF_POWER_CTRL_LINREG_OK_IRQ(v)              (((v) << 17) & 0x20000)
+#define BP_POWER_CTRL_ENIRQ_LINREG_OK               16
+#define BM_POWER_CTRL_ENIRQ_LINREG_OK               0x10000
+#define BF_POWER_CTRL_ENIRQ_LINREG_OK(v)            (((v) << 16) & 0x10000)
+#define BP_POWER_CTRL_DC_OK_IRQ                     15
+#define BM_POWER_CTRL_DC_OK_IRQ                     0x8000
+#define BF_POWER_CTRL_DC_OK_IRQ(v)                  (((v) << 15) & 0x8000)
+#define BP_POWER_CTRL_ENIRQ_DC_OK                   14
+#define BM_POWER_CTRL_ENIRQ_DC_OK                   0x4000
+#define BF_POWER_CTRL_ENIRQ_DC_OK(v)                (((v) << 14) & 0x4000)
+#define BP_POWER_CTRL_BATT_BO_IRQ                   13
+#define BM_POWER_CTRL_BATT_BO_IRQ                   0x2000
+#define BF_POWER_CTRL_BATT_BO_IRQ(v)                (((v) << 13) & 0x2000)
+#define BP_POWER_CTRL_ENIRQBATT_BO                  12
+#define BM_POWER_CTRL_ENIRQBATT_BO                  0x1000
+#define BF_POWER_CTRL_ENIRQBATT_BO(v)               (((v) << 12) & 0x1000)
+#define BP_POWER_CTRL_VDDIO_BO_IRQ                  11
+#define BM_POWER_CTRL_VDDIO_BO_IRQ                  0x800
+#define BF_POWER_CTRL_VDDIO_BO_IRQ(v)               (((v) << 11) & 0x800)
+#define BP_POWER_CTRL_ENIRQ_VDDIO_BO                10
+#define BM_POWER_CTRL_ENIRQ_VDDIO_BO                0x400
+#define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v)             (((v) << 10) & 0x400)
+#define BP_POWER_CTRL_VDDA_BO_IRQ                   9
+#define BM_POWER_CTRL_VDDA_BO_IRQ                   0x200
+#define BF_POWER_CTRL_VDDA_BO_IRQ(v)                (((v) << 9) & 0x200)
+#define BP_POWER_CTRL_ENIRQ_VDDA_BO                 8
+#define BM_POWER_CTRL_ENIRQ_VDDA_BO                 0x100
+#define BF_POWER_CTRL_ENIRQ_VDDA_BO(v)              (((v) << 8) & 0x100)
+#define BP_POWER_CTRL_VDDD_BO_IRQ                   7
+#define BM_POWER_CTRL_VDDD_BO_IRQ                   0x80
+#define BF_POWER_CTRL_VDDD_BO_IRQ(v)                (((v) << 7) & 0x80)
+#define BP_POWER_CTRL_ENIRQ_VDDD_BO                 6
+#define BM_POWER_CTRL_ENIRQ_VDDD_BO                 0x40
+#define BF_POWER_CTRL_ENIRQ_VDDD_BO(v)              (((v) << 6) & 0x40)
+#define BP_POWER_CTRL_POLARITY_VBUSVALID            5
+#define BM_POWER_CTRL_POLARITY_VBUSVALID            0x20
+#define BF_POWER_CTRL_POLARITY_VBUSVALID(v)         (((v) << 5) & 0x20)
+#define BP_POWER_CTRL_VBUSVALID_IRQ                 4
+#define BM_POWER_CTRL_VBUSVALID_IRQ                 0x10
+#define BF_POWER_CTRL_VBUSVALID_IRQ(v)              (((v) << 4) & 0x10)
+#define BP_POWER_CTRL_ENIRQ_VBUS_VALID              3
+#define BM_POWER_CTRL_ENIRQ_VBUS_VALID              0x8
+#define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v)           (((v) << 3) & 0x8)
+#define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       2
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO       0x4
+#define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v)    (((v) << 2) & 0x4)
+#define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            1
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ            0x2
+#define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v)         (((v) << 1) & 0x2)
+#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO          0x1
+#define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_5VCTRL
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_POWER_5VCTRL                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0))
+#define HW_POWER_5VCTRL_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4))
+#define HW_POWER_5VCTRL_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8))
+#define HW_POWER_5VCTRL_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc))
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH          10
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH          0xc00
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v)       (((v) << 10) & 0xc00)
+#define BP_POWER_5VCTRL_PWDN_5VBRNOUT           8
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT           0x100
+#define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v)        (((v) << 8) & 0x100)
+#define BP_POWER_5VCTRL_ENABLE_ILIMIT           7
+#define BM_POWER_5VCTRL_ENABLE_ILIMIT           0x80
+#define BF_POWER_5VCTRL_ENABLE_ILIMIT(v)        (((v) << 7) & 0x80)
+#define BP_POWER_5VCTRL_DCDC_XFER               6
+#define BM_POWER_5VCTRL_DCDC_XFER               0x40
+#define BF_POWER_5VCTRL_DCDC_XFER(v)            (((v) << 6) & 0x40)
+#define BP_POWER_5VCTRL_EN_BATT_PULLDN          5
+#define BM_POWER_5VCTRL_EN_BATT_PULLDN          0x20
+#define BF_POWER_5VCTRL_EN_BATT_PULLDN(v)       (((v) << 5) & 0x20)
+#define BP_POWER_5VCTRL_VBUSVALID_5VDETECT      4
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT      0x10
+#define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v)   (((v) << 4) & 0x10)
+#define BP_POWER_5VCTRL_VBUSVALID_TO_B          3
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B          0x8
+#define BF_POWER_5VCTRL_VBUSVALID_TO_B(v)       (((v) << 3) & 0x8)
+#define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO          2
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO          0x4
+#define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v)       (((v) << 2) & 0x4)
+#define BP_POWER_5VCTRL_OTG_PWRUP_CMPS          1
+#define BM_POWER_5VCTRL_OTG_PWRUP_CMPS          0x2
+#define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v)       (((v) << 1) & 0x2)
+#define BP_POWER_5VCTRL_ENABLE_DCDC             0
+#define BM_POWER_5VCTRL_ENABLE_DCDC             0x1
+#define BF_POWER_5VCTRL_ENABLE_DCDC(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_MINPWR
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_POWER_MINPWR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0))
+#define HW_POWER_MINPWR_SET                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4))
+#define HW_POWER_MINPWR_CLR                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8))
+#define HW_POWER_MINPWR_TOG                 (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc))
+#define BP_POWER_MINPWR_PWD_BO              11
+#define BM_POWER_MINPWR_PWD_BO              0x800
+#define BF_POWER_MINPWR_PWD_BO(v)           (((v) << 11) & 0x800)
+#define BP_POWER_MINPWR_USB_I_SUSPEND       10
+#define BM_POWER_MINPWR_USB_I_SUSPEND       0x400
+#define BF_POWER_MINPWR_USB_I_SUSPEND(v)    (((v) << 10) & 0x400)
+#define BP_POWER_MINPWR_ENABLE_OSC          9
+#define BM_POWER_MINPWR_ENABLE_OSC          0x200
+#define BF_POWER_MINPWR_ENABLE_OSC(v)       (((v) << 9) & 0x200)
+#define BP_POWER_MINPWR_SELECT_OSC          8
+#define BM_POWER_MINPWR_SELECT_OSC          0x100
+#define BF_POWER_MINPWR_SELECT_OSC(v)       (((v) << 8) & 0x100)
+#define BP_POWER_MINPWR_VBG_OFF             7
+#define BM_POWER_MINPWR_VBG_OFF             0x80
+#define BF_POWER_MINPWR_VBG_OFF(v)          (((v) << 7) & 0x80)
+#define BP_POWER_MINPWR_DOUBLE_FETS         6
+#define BM_POWER_MINPWR_DOUBLE_FETS         0x40
+#define BF_POWER_MINPWR_DOUBLE_FETS(v)      (((v) << 6) & 0x40)
+#define BP_POWER_MINPWR_HALF_FETS           5
+#define BM_POWER_MINPWR_HALF_FETS           0x20
+#define BF_POWER_MINPWR_HALF_FETS(v)        (((v) << 5) & 0x20)
+#define BP_POWER_MINPWR_LESSANA_I           4
+#define BM_POWER_MINPWR_LESSANA_I           0x10
+#define BF_POWER_MINPWR_LESSANA_I(v)        (((v) << 4) & 0x10)
+#define BP_POWER_MINPWR_PWD_XTAL24          3
+#define BM_POWER_MINPWR_PWD_XTAL24          0x8
+#define BF_POWER_MINPWR_PWD_XTAL24(v)       (((v) << 3) & 0x8)
+#define BP_POWER_MINPWR_DC_STOPCLK          2
+#define BM_POWER_MINPWR_DC_STOPCLK          0x4
+#define BF_POWER_MINPWR_DC_STOPCLK(v)       (((v) << 2) & 0x4)
+#define BP_POWER_MINPWR_EN_DC_PFM           1
+#define BM_POWER_MINPWR_EN_DC_PFM           0x2
+#define BF_POWER_MINPWR_EN_DC_PFM(v)        (((v) << 1) & 0x2)
+#define BP_POWER_MINPWR_DC_HALFCLK          0
+#define BM_POWER_MINPWR_DC_HALFCLK          0x1
+#define BF_POWER_MINPWR_DC_HALFCLK(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_CHARGE
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_POWER_CHARGE                         (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0))
+#define HW_POWER_CHARGE_SET                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4))
+#define HW_POWER_CHARGE_CLR                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8))
+#define HW_POWER_CHARGE_TOG                     (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc))
+#define BP_POWER_CHARGE_ENABLE_FAULT_DETECT     20
+#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT     0x100000
+#define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v)  (((v) << 20) & 0x100000)
+#define BP_POWER_CHARGE_CHRG_STS_OFF            19
+#define BM_POWER_CHARGE_CHRG_STS_OFF            0x80000
+#define BF_POWER_CHARGE_CHRG_STS_OFF(v)         (((v) << 19) & 0x80000)
+#define BP_POWER_CHARGE_USE_EXTERN_R            17
+#define BM_POWER_CHARGE_USE_EXTERN_R            0x20000
+#define BF_POWER_CHARGE_USE_EXTERN_R(v)         (((v) << 17) & 0x20000)
+#define BP_POWER_CHARGE_PWD_BATTCHRG            16
+#define BM_POWER_CHARGE_PWD_BATTCHRG            0x10000
+#define BF_POWER_CHARGE_PWD_BATTCHRG(v)         (((v) << 16) & 0x10000)
+#define BP_POWER_CHARGE_STOP_ILIMIT             8
+#define BM_POWER_CHARGE_STOP_ILIMIT             0xf00
+#define BF_POWER_CHARGE_STOP_ILIMIT(v)          (((v) << 8) & 0xf00)
+#define BP_POWER_CHARGE_BATTCHRG_I              0
+#define BM_POWER_CHARGE_BATTCHRG_I              0x3f
+#define BF_POWER_CHARGE_BATTCHRG_I(v)           (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_POWER_VDDDCTRL
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_POWER_VDDDCTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40))
+#define BP_POWER_VDDDCTRL_ADJTN                 28
+#define BM_POWER_VDDDCTRL_ADJTN                 0xf0000000
+#define BF_POWER_VDDDCTRL_ADJTN(v)              (((v) << 28) & 0xf0000000)
+#define BP_POWER_VDDDCTRL_ALKALINE_CHARGE       24
+#define BM_POWER_VDDDCTRL_ALKALINE_CHARGE       0x1000000
+#define BF_POWER_VDDDCTRL_ALKALINE_CHARGE(v)    (((v) << 24) & 0x1000000)
+#define BP_POWER_VDDDCTRL_DISABLE_STEPPING      23
+#define BM_POWER_VDDDCTRL_DISABLE_STEPPING      0x800000
+#define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v)   (((v) << 23) & 0x800000)
+#define BP_POWER_VDDDCTRL_LINREG_FROM_BATT      22
+#define BM_POWER_VDDDCTRL_LINREG_FROM_BATT      0x400000
+#define BF_POWER_VDDDCTRL_LINREG_FROM_BATT(v)   (((v) << 22) & 0x400000)
+#define BP_POWER_VDDDCTRL_ENABLE_LINREG         21
+#define BM_POWER_VDDDCTRL_ENABLE_LINREG         0x200000
+#define BF_POWER_VDDDCTRL_ENABLE_LINREG(v)      (((v) << 21) & 0x200000)
+#define BP_POWER_VDDDCTRL_DISABLE_FET           20
+#define BM_POWER_VDDDCTRL_DISABLE_FET           0x100000
+#define BF_POWER_VDDDCTRL_DISABLE_FET(v)        (((v) << 20) & 0x100000)
+#define BP_POWER_VDDDCTRL_LINREG_OFFSET         16
+#define BM_POWER_VDDDCTRL_LINREG_OFFSET         0x30000
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v)      (((v) << 16) & 0x30000)
+#define BP_POWER_VDDDCTRL_BO_OFFSET             8
+#define BM_POWER_VDDDCTRL_BO_OFFSET             0x700
+#define BF_POWER_VDDDCTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
+#define BP_POWER_VDDDCTRL_TRG                   0
+#define BM_POWER_VDDDCTRL_TRG                   0x1f
+#define BF_POWER_VDDDCTRL_TRG(v)                (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_VDDACTRL
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_POWER_VDDACTRL                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50))
+#define BP_POWER_VDDACTRL_DISABLE_STEPPING      18
+#define BM_POWER_VDDACTRL_DISABLE_STEPPING      0x40000
+#define BF_POWER_VDDACTRL_DISABLE_STEPPING(v)   (((v) << 18) & 0x40000)
+#define BP_POWER_VDDACTRL_ENABLE_LINREG         17
+#define BM_POWER_VDDACTRL_ENABLE_LINREG         0x20000
+#define BF_POWER_VDDACTRL_ENABLE_LINREG(v)      (((v) << 17) & 0x20000)
+#define BP_POWER_VDDACTRL_DISABLE_FET           16
+#define BM_POWER_VDDACTRL_DISABLE_FET           0x10000
+#define BF_POWER_VDDACTRL_DISABLE_FET(v)        (((v) << 16) & 0x10000)
+#define BP_POWER_VDDACTRL_LINREG_OFFSET         12
+#define BM_POWER_VDDACTRL_LINREG_OFFSET         0x3000
+#define BF_POWER_VDDACTRL_LINREG_OFFSET(v)      (((v) << 12) & 0x3000)
+#define BP_POWER_VDDACTRL_BO_OFFSET             8
+#define BM_POWER_VDDACTRL_BO_OFFSET             0x700
+#define BF_POWER_VDDACTRL_BO_OFFSET(v)          (((v) << 8) & 0x700)
+#define BP_POWER_VDDACTRL_TRG                   0
+#define BM_POWER_VDDACTRL_TRG                   0x1f
+#define BF_POWER_VDDACTRL_TRG(v)                (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_VDDIOCTRL
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_POWER_VDDIOCTRL                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60))
+#define BP_POWER_VDDIOCTRL_ADJTN                16
+#define BM_POWER_VDDIOCTRL_ADJTN                0xf0000
+#define BF_POWER_VDDIOCTRL_ADJTN(v)             (((v) << 16) & 0xf0000)
+#define BP_POWER_VDDIOCTRL_DISABLE_STEPPING     15
+#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING     0x8000
+#define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v)  (((v) << 15) & 0x8000)
+#define BP_POWER_VDDIOCTRL_DISABLE_FET          14
+#define BM_POWER_VDDIOCTRL_DISABLE_FET          0x4000
+#define BF_POWER_VDDIOCTRL_DISABLE_FET(v)       (((v) << 14) & 0x4000)
+#define BP_POWER_VDDIOCTRL_LINREG_OFFSET        12
+#define BM_POWER_VDDIOCTRL_LINREG_OFFSET        0x3000
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v)     (((v) << 12) & 0x3000)
+#define BP_POWER_VDDIOCTRL_BO_OFFSET            8
+#define BM_POWER_VDDIOCTRL_BO_OFFSET            0x700
+#define BF_POWER_VDDIOCTRL_BO_OFFSET(v)         (((v) << 8) & 0x700)
+#define BP_POWER_VDDIOCTRL_TRG                  0
+#define BM_POWER_VDDIOCTRL_TRG                  0x1f
+#define BF_POWER_VDDIOCTRL_TRG(v)               (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_POWER_DCFUNCV
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_POWER_DCFUNCV            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70))
+#define BP_POWER_DCFUNCV_VDDD       16
+#define BM_POWER_DCFUNCV_VDDD       0x3ff0000
+#define BF_POWER_DCFUNCV_VDDD(v)    (((v) << 16) & 0x3ff0000)
+#define BP_POWER_DCFUNCV_VDDIO      0
+#define BM_POWER_DCFUNCV_VDDIO      0x3ff
+#define BF_POWER_DCFUNCV_VDDIO(v)   (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_POWER_MISC
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_POWER_MISC                       (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80))
+#define BP_POWER_MISC_FREQSEL               4
+#define BM_POWER_MISC_FREQSEL               0x30
+#define BF_POWER_MISC_FREQSEL(v)            (((v) << 4) & 0x30)
+#define BP_POWER_MISC_DELAY_TIMING          3
+#define BM_POWER_MISC_DELAY_TIMING          0x8
+#define BF_POWER_MISC_DELAY_TIMING(v)       (((v) << 3) & 0x8)
+#define BP_POWER_MISC_TEST                  2
+#define BM_POWER_MISC_TEST                  0x4
+#define BF_POWER_MISC_TEST(v)               (((v) << 2) & 0x4)
+#define BP_POWER_MISC_SEL_PLLCLK            1
+#define BM_POWER_MISC_SEL_PLLCLK            0x2
+#define BF_POWER_MISC_SEL_PLLCLK(v)         (((v) << 1) & 0x2)
+#define BP_POWER_MISC_PERIPHERALSWOFF       0
+#define BM_POWER_MISC_PERIPHERALSWOFF       0x1
+#define BF_POWER_MISC_PERIPHERALSWOFF(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_DCLIMITS
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_POWER_DCLIMITS                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90))
+#define BP_POWER_DCLIMITS_POSLIMIT_BOOST    16
+#define BM_POWER_DCLIMITS_POSLIMIT_BOOST    0x7f0000
+#define BF_POWER_DCLIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000)
+#define BP_POWER_DCLIMITS_POSLIMIT_BUCK     8
+#define BM_POWER_DCLIMITS_POSLIMIT_BUCK     0x7f00
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v)  (((v) << 8) & 0x7f00)
+#define BP_POWER_DCLIMITS_NEGLIMIT          0
+#define BM_POWER_DCLIMITS_NEGLIMIT          0x7f
+#define BF_POWER_DCLIMITS_NEGLIMIT(v)       (((v) << 0) & 0x7f)
+
+/**
+ * Register: HW_POWER_LOOPCTRL
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_POWER_LOOPCTRL                   (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0))
+#define HW_POWER_LOOPCTRL_SET               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4))
+#define HW_POWER_LOOPCTRL_CLR               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8))
+#define HW_POWER_LOOPCTRL_TOG               (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc))
+#define BP_POWER_LOOPCTRL_TOGGLE_DIF        20
+#define BM_POWER_LOOPCTRL_TOGGLE_DIF        0x100000
+#define BF_POWER_LOOPCTRL_TOGGLE_DIF(v)     (((v) << 20) & 0x100000)
+#define BP_POWER_LOOPCTRL_HYST_SIGN         19
+#define BM_POWER_LOOPCTRL_HYST_SIGN         0x80000
+#define BF_POWER_LOOPCTRL_HYST_SIGN(v)      (((v) << 19) & 0x80000)
+#define BP_POWER_LOOPCTRL_EN_CM_HYST        18
+#define BM_POWER_LOOPCTRL_EN_CM_HYST        0x40000
+#define BF_POWER_LOOPCTRL_EN_CM_HYST(v)     (((v) << 18) & 0x40000)
+#define BP_POWER_LOOPCTRL_EN_DF_HYST        17
+#define BM_POWER_LOOPCTRL_EN_DF_HYST        0x20000
+#define BF_POWER_LOOPCTRL_EN_DF_HYST(v)     (((v) << 17) & 0x20000)
+#define BP_POWER_LOOPCTRL_CM_HYST_THRESH    16
+#define BM_POWER_LOOPCTRL_CM_HYST_THRESH    0x10000
+#define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000)
+#define BP_POWER_LOOPCTRL_DF_HYST_THRESH    15
+#define BM_POWER_LOOPCTRL_DF_HYST_THRESH    0x8000
+#define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000)
+#define BP_POWER_LOOPCTRL_RCSCALE_THRESH    14
+#define BM_POWER_LOOPCTRL_RCSCALE_THRESH    0x4000
+#define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000)
+#define BP_POWER_LOOPCTRL_EN_RCSCALE        12
+#define BM_POWER_LOOPCTRL_EN_RCSCALE        0x3000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v)     (((v) << 12) & 0x3000)
+#define BP_POWER_LOOPCTRL_DC_FF             8
+#define BM_POWER_LOOPCTRL_DC_FF             0x700
+#define BF_POWER_LOOPCTRL_DC_FF(v)          (((v) << 8) & 0x700)
+#define BP_POWER_LOOPCTRL_DC_R              4
+#define BM_POWER_LOOPCTRL_DC_R              0xf0
+#define BF_POWER_LOOPCTRL_DC_R(v)           (((v) << 4) & 0xf0)
+#define BP_POWER_LOOPCTRL_DC_C              0
+#define BM_POWER_LOOPCTRL_DC_C              0x3
+#define BF_POWER_LOOPCTRL_DC_C(v)           (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_POWER_STS
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_POWER_STS                        (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0))
+#define BP_POWER_STS_BATT_CHRG_PRESENT      31
+#define BM_POWER_STS_BATT_CHRG_PRESENT      0x80000000
+#define BF_POWER_STS_BATT_CHRG_PRESENT(v)   (((v) << 31) & 0x80000000)
+#define BP_POWER_STS_PSWITCH                18
+#define BM_POWER_STS_PSWITCH                0xc0000
+#define BF_POWER_STS_PSWITCH(v)             (((v) << 18) & 0xc0000)
+#define BP_POWER_STS_AVALID_STATUS          17
+#define BM_POWER_STS_AVALID_STATUS          0x20000
+#define BF_POWER_STS_AVALID_STATUS(v)       (((v) << 17) & 0x20000)
+#define BP_POWER_STS_BVALID_STATUS          16
+#define BM_POWER_STS_BVALID_STATUS          0x10000
+#define BF_POWER_STS_BVALID_STATUS(v)       (((v) << 16) & 0x10000)
+#define BP_POWER_STS_VBUSVALID_STATUS       15
+#define BM_POWER_STS_VBUSVALID_STATUS       0x8000
+#define BF_POWER_STS_VBUSVALID_STATUS(v)    (((v) << 15) & 0x8000)
+#define BP_POWER_STS_SESSEND_STATUS         14
+#define BM_POWER_STS_SESSEND_STATUS         0x4000
+#define BF_POWER_STS_SESSEND_STATUS(v)      (((v) << 14) & 0x4000)
+#define BP_POWER_STS_MODE                   13
+#define BM_POWER_STS_MODE                   0x2000
+#define BF_POWER_STS_MODE(v)                (((v) << 13) & 0x2000)
+#define BP_POWER_STS_BATT_BO                12
+#define BM_POWER_STS_BATT_BO                0x1000
+#define BF_POWER_STS_BATT_BO(v)             (((v) << 12) & 0x1000)
+#define BP_POWER_STS_VDD5V_FAULT            11
+#define BM_POWER_STS_VDD5V_FAULT            0x800
+#define BF_POWER_STS_VDD5V_FAULT(v)         (((v) << 11) & 0x800)
+#define BP_POWER_STS_CHRGSTS                10
+#define BM_POWER_STS_CHRGSTS                0x400
+#define BF_POWER_STS_CHRGSTS(v)             (((v) << 10) & 0x400)
+#define BP_POWER_STS_LINREG_OK              9
+#define BM_POWER_STS_LINREG_OK              0x200
+#define BF_POWER_STS_LINREG_OK(v)           (((v) << 9) & 0x200)
+#define BP_POWER_STS_DC_OK                  8
+#define BM_POWER_STS_DC_OK                  0x100
+#define BF_POWER_STS_DC_OK(v)               (((v) << 8) & 0x100)
+#define BP_POWER_STS_VDDIO_BO               7
+#define BM_POWER_STS_VDDIO_BO               0x80
+#define BF_POWER_STS_VDDIO_BO(v)            (((v) << 7) & 0x80)
+#define BP_POWER_STS_VDDA_BO                6
+#define BM_POWER_STS_VDDA_BO                0x40
+#define BF_POWER_STS_VDDA_BO(v)             (((v) << 6) & 0x40)
+#define BP_POWER_STS_VDDD_BO                5
+#define BM_POWER_STS_VDDD_BO                0x20
+#define BF_POWER_STS_VDDD_BO(v)             (((v) << 5) & 0x20)
+#define BP_POWER_STS_VDD5V_GT_VDDIO         4
+#define BM_POWER_STS_VDD5V_GT_VDDIO         0x10
+#define BF_POWER_STS_VDD5V_GT_VDDIO(v)      (((v) << 4) & 0x10)
+#define BP_POWER_STS_AVALID                 3
+#define BM_POWER_STS_AVALID                 0x8
+#define BF_POWER_STS_AVALID(v)              (((v) << 3) & 0x8)
+#define BP_POWER_STS_BVALID                 2
+#define BM_POWER_STS_BVALID                 0x4
+#define BF_POWER_STS_BVALID(v)              (((v) << 2) & 0x4)
+#define BP_POWER_STS_VBUSVALID              1
+#define BM_POWER_STS_VBUSVALID              0x2
+#define BF_POWER_STS_VBUSVALID(v)           (((v) << 1) & 0x2)
+#define BP_POWER_STS_SESSEND                0
+#define BM_POWER_STS_SESSEND                0x1
+#define BF_POWER_STS_SESSEND(v)             (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_SPEED
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_POWER_SPEED              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0))
+#define HW_POWER_SPEED_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4))
+#define HW_POWER_SPEED_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8))
+#define HW_POWER_SPEED_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc))
+#define BP_POWER_SPEED_STATUS       16
+#define BM_POWER_SPEED_STATUS       0xff0000
+#define BF_POWER_SPEED_STATUS(v)    (((v) << 16) & 0xff0000)
+#define BP_POWER_SPEED_CTRL         0
+#define BM_POWER_SPEED_CTRL         0x3
+#define BF_POWER_SPEED_CTRL(v)      (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_POWER_BATTMONITOR
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_POWER_BATTMONITOR                    (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0))
+#define BP_POWER_BATTMONITOR_BATT_VAL           16
+#define BM_POWER_BATTMONITOR_BATT_VAL           0x3ff0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v)        (((v) << 16) & 0x3ff0000)
+#define BP_POWER_BATTMONITOR_EN_BATADJ          6
+#define BM_POWER_BATTMONITOR_EN_BATADJ          0x40
+#define BF_POWER_BATTMONITOR_EN_BATADJ(v)       (((v) << 6) & 0x40)
+#define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT    5
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT    0x20
+#define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 5) & 0x20)
+#define BP_POWER_BATTMONITOR_BRWNOUT_PWD        4
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD        0x10
+#define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v)     (((v) << 4) & 0x10)
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL        0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL        0xf
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v)     (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_POWER_RESET
+ * Address: 0xe0
+ * SCT: yes
+*/
+#define HW_POWER_RESET              (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x0))
+#define HW_POWER_RESET_SET          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x4))
+#define HW_POWER_RESET_CLR          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x8))
+#define HW_POWER_RESET_TOG          (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0xc))
+#define BP_POWER_RESET_UNLOCK       16
+#define BM_POWER_RESET_UNLOCK       0xffff0000
+#define BV_POWER_RESET_UNLOCK__KEY  0x3e77
+#define BF_POWER_RESET_UNLOCK(v)    (((v) << 16) & 0xffff0000)
+#define BF_POWER_RESET_UNLOCK_V(v)  ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000)
+#define BP_POWER_RESET_PWD_OFF      1
+#define BM_POWER_RESET_PWD_OFF      0x2
+#define BF_POWER_RESET_PWD_OFF(v)   (((v) << 1) & 0x2)
+#define BP_POWER_RESET_PWD          0
+#define BM_POWER_RESET_PWD          0x1
+#define BF_POWER_RESET_PWD(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_DEBUG
+ * Address: 0xf0
+ * SCT: yes
+*/
+#define HW_POWER_DEBUG                      (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x0))
+#define HW_POWER_DEBUG_SET                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x4))
+#define HW_POWER_DEBUG_CLR                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x8))
+#define HW_POWER_DEBUG_TOG                  (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0xc))
+#define BP_POWER_DEBUG_VBUSVALIDPIOLOCK     3
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK     0x8
+#define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v)  (((v) << 3) & 0x8)
+#define BP_POWER_DEBUG_AVALIDPIOLOCK        2
+#define BM_POWER_DEBUG_AVALIDPIOLOCK        0x4
+#define BF_POWER_DEBUG_AVALIDPIOLOCK(v)     (((v) << 2) & 0x4)
+#define BP_POWER_DEBUG_BVALIDPIOLOCK        1
+#define BM_POWER_DEBUG_BVALIDPIOLOCK        0x2
+#define BF_POWER_DEBUG_BVALIDPIOLOCK(v)     (((v) << 1) & 0x2)
+#define BP_POWER_DEBUG_SESSENDPIOLOCK       0
+#define BM_POWER_DEBUG_SESSENDPIOLOCK       0x1
+#define BF_POWER_DEBUG_SESSENDPIOLOCK(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_POWER_SPECIAL
+ * Address: 0x100
+ * SCT: yes
+*/
+#define HW_POWER_SPECIAL            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0))
+#define HW_POWER_SPECIAL_SET        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4))
+#define HW_POWER_SPECIAL_CLR        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8))
+#define HW_POWER_SPECIAL_TOG        (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc))
+#define BP_POWER_SPECIAL_TEST       0
+#define BM_POWER_SPECIAL_TEST       0xffffffff
+#define BF_POWER_SPECIAL_TEST(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_POWER_VERSION
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_POWER_VERSION            (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110))
+#define BP_POWER_VERSION_MAJOR      24
+#define BM_POWER_VERSION_MAJOR      0xff000000
+#define BF_POWER_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_POWER_VERSION_MINOR      16
+#define BM_POWER_VERSION_MINOR      0xff0000
+#define BF_POWER_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_POWER_VERSION_STEP       0
+#define BM_POWER_VERSION_STEP       0xffff
+#define BF_POWER_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__POWER__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h
new file mode 100644
index 0000000000..4d7b385d10
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h
@@ -0,0 +1,153 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__PWM__H__
+#define __HEADERGEN__STMP3700__PWM__H__
+
+#define REGS_PWM_BASE (0x80064000)
+
+#define REGS_PWM_VERSION "3.2.0"
+
+/**
+ * Register: HW_PWM_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_PWM_CTRL                         (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0))
+#define HW_PWM_CTRL_SET                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4))
+#define HW_PWM_CTRL_CLR                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8))
+#define HW_PWM_CTRL_TOG                     (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc))
+#define BP_PWM_CTRL_SFTRST                  31
+#define BM_PWM_CTRL_SFTRST                  0x80000000
+#define BF_PWM_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BP_PWM_CTRL_CLKGATE                 30
+#define BM_PWM_CTRL_CLKGATE                 0x40000000
+#define BF_PWM_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_PWM_CTRL_PWM4_PRESENT            29
+#define BM_PWM_CTRL_PWM4_PRESENT            0x20000000
+#define BF_PWM_CTRL_PWM4_PRESENT(v)         (((v) << 29) & 0x20000000)
+#define BP_PWM_CTRL_PWM3_PRESENT            28
+#define BM_PWM_CTRL_PWM3_PRESENT            0x10000000
+#define BF_PWM_CTRL_PWM3_PRESENT(v)         (((v) << 28) & 0x10000000)
+#define BP_PWM_CTRL_PWM2_PRESENT            27
+#define BM_PWM_CTRL_PWM2_PRESENT            0x8000000
+#define BF_PWM_CTRL_PWM2_PRESENT(v)         (((v) << 27) & 0x8000000)
+#define BP_PWM_CTRL_PWM1_PRESENT            26
+#define BM_PWM_CTRL_PWM1_PRESENT            0x4000000
+#define BF_PWM_CTRL_PWM1_PRESENT(v)         (((v) << 26) & 0x4000000)
+#define BP_PWM_CTRL_PWM0_PRESENT            25
+#define BM_PWM_CTRL_PWM0_PRESENT            0x2000000
+#define BF_PWM_CTRL_PWM0_PRESENT(v)         (((v) << 25) & 0x2000000)
+#define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    5
+#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE    0x20
+#define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v) (((v) << 5) & 0x20)
+#define BP_PWM_CTRL_PWM4_ENABLE             4
+#define BM_PWM_CTRL_PWM4_ENABLE             0x10
+#define BF_PWM_CTRL_PWM4_ENABLE(v)          (((v) << 4) & 0x10)
+#define BP_PWM_CTRL_PWM3_ENABLE             3
+#define BM_PWM_CTRL_PWM3_ENABLE             0x8
+#define BF_PWM_CTRL_PWM3_ENABLE(v)          (((v) << 3) & 0x8)
+#define BP_PWM_CTRL_PWM2_ENABLE             2
+#define BM_PWM_CTRL_PWM2_ENABLE             0x4
+#define BF_PWM_CTRL_PWM2_ENABLE(v)          (((v) << 2) & 0x4)
+#define BP_PWM_CTRL_PWM1_ENABLE             1
+#define BM_PWM_CTRL_PWM1_ENABLE             0x2
+#define BF_PWM_CTRL_PWM1_ENABLE(v)          (((v) << 1) & 0x2)
+#define BP_PWM_CTRL_PWM0_ENABLE             0
+#define BM_PWM_CTRL_PWM0_ENABLE             0x1
+#define BF_PWM_CTRL_PWM0_ENABLE(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_PWM_ACTIVEn
+ * Address: 0x10+n*0x20
+ * SCT: yes
+*/
+#define HW_PWM_ACTIVEn(n)           (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0))
+#define HW_PWM_ACTIVEn_SET(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4))
+#define HW_PWM_ACTIVEn_CLR(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8))
+#define HW_PWM_ACTIVEn_TOG(n)       (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc))
+#define BP_PWM_ACTIVEn_INACTIVE     16
+#define BM_PWM_ACTIVEn_INACTIVE     0xffff0000
+#define BF_PWM_ACTIVEn_INACTIVE(v)  (((v) << 16) & 0xffff0000)
+#define BP_PWM_ACTIVEn_ACTIVE       0
+#define BM_PWM_ACTIVEn_ACTIVE       0xffff
+#define BF_PWM_ACTIVEn_ACTIVE(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_PWM_PERIODn
+ * Address: 0x20+n*0x20
+ * SCT: yes
+*/
+#define HW_PWM_PERIODn(n)                   (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0))
+#define HW_PWM_PERIODn_SET(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4))
+#define HW_PWM_PERIODn_CLR(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8))
+#define HW_PWM_PERIODn_TOG(n)               (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc))
+#define BP_PWM_PERIODn_MATT                 23
+#define BM_PWM_PERIODn_MATT                 0x800000
+#define BF_PWM_PERIODn_MATT(v)              (((v) << 23) & 0x800000)
+#define BP_PWM_PERIODn_CDIV                 20
+#define BM_PWM_PERIODn_CDIV                 0x700000
+#define BV_PWM_PERIODn_CDIV__DIV_1          0x0
+#define BV_PWM_PERIODn_CDIV__DIV_2          0x1
+#define BV_PWM_PERIODn_CDIV__DIV_4          0x2
+#define BV_PWM_PERIODn_CDIV__DIV_8          0x3
+#define BV_PWM_PERIODn_CDIV__DIV_16         0x4
+#define BV_PWM_PERIODn_CDIV__DIV_64         0x5
+#define BV_PWM_PERIODn_CDIV__DIV_256        0x6
+#define BV_PWM_PERIODn_CDIV__DIV_1024       0x7
+#define BF_PWM_PERIODn_CDIV(v)              (((v) << 20) & 0x700000)
+#define BF_PWM_PERIODn_CDIV_V(v)            ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000)
+#define BP_PWM_PERIODn_INACTIVE_STATE       18
+#define BM_PWM_PERIODn_INACTIVE_STATE       0xc0000
+#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_INACTIVE_STATE__0    0x2
+#define BV_PWM_PERIODn_INACTIVE_STATE__1    0x3
+#define BF_PWM_PERIODn_INACTIVE_STATE(v)    (((v) << 18) & 0xc0000)
+#define BF_PWM_PERIODn_INACTIVE_STATE_V(v)  ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000)
+#define BP_PWM_PERIODn_ACTIVE_STATE         16
+#define BM_PWM_PERIODn_ACTIVE_STATE         0x30000
+#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z   0x0
+#define BV_PWM_PERIODn_ACTIVE_STATE__0      0x2
+#define BV_PWM_PERIODn_ACTIVE_STATE__1      0x3
+#define BF_PWM_PERIODn_ACTIVE_STATE(v)      (((v) << 16) & 0x30000)
+#define BF_PWM_PERIODn_ACTIVE_STATE_V(v)    ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000)
+#define BP_PWM_PERIODn_PERIOD               0
+#define BM_PWM_PERIODn_PERIOD               0xffff
+#define BF_PWM_PERIODn_PERIOD(v)            (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_PWM_VERSION
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_PWM_VERSION          (*(volatile unsigned long *)(REGS_PWM_BASE + 0xb0))
+#define BP_PWM_VERSION_MAJOR    24
+#define BM_PWM_VERSION_MAJOR    0xff000000
+#define BF_PWM_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_PWM_VERSION_MINOR    16
+#define BM_PWM_VERSION_MINOR    0xff0000
+#define BF_PWM_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_PWM_VERSION_STEP     0
+#define BM_PWM_VERSION_STEP     0xffff
+#define BF_PWM_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__PWM__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h
new file mode 100644
index 0000000000..ed2bf3270e
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h
@@ -0,0 +1,312 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__RTC__H__
+#define __HEADERGEN__STMP3700__RTC__H__
+
+#define REGS_RTC_BASE (0x8005c000)
+
+#define REGS_RTC_VERSION "3.2.0"
+
+/**
+ * Register: HW_RTC_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_RTC_CTRL                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0))
+#define HW_RTC_CTRL_SET                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4))
+#define HW_RTC_CTRL_CLR                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8))
+#define HW_RTC_CTRL_TOG                     (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc))
+#define BP_RTC_CTRL_SFTRST                  31
+#define BM_RTC_CTRL_SFTRST                  0x80000000
+#define BF_RTC_CTRL_SFTRST(v)               (((v) << 31) & 0x80000000)
+#define BP_RTC_CTRL_CLKGATE                 30
+#define BM_RTC_CTRL_CLKGATE                 0x40000000
+#define BF_RTC_CTRL_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG    6
+#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG    0x40
+#define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40)
+#define BP_RTC_CTRL_FORCE_UPDATE            5
+#define BM_RTC_CTRL_FORCE_UPDATE            0x20
+#define BF_RTC_CTRL_FORCE_UPDATE(v)         (((v) << 5) & 0x20)
+#define BP_RTC_CTRL_WATCHDOGEN              4
+#define BM_RTC_CTRL_WATCHDOGEN              0x10
+#define BF_RTC_CTRL_WATCHDOGEN(v)           (((v) << 4) & 0x10)
+#define BP_RTC_CTRL_ONEMSEC_IRQ             3
+#define BM_RTC_CTRL_ONEMSEC_IRQ             0x8
+#define BF_RTC_CTRL_ONEMSEC_IRQ(v)          (((v) << 3) & 0x8)
+#define BP_RTC_CTRL_ALARM_IRQ               2
+#define BM_RTC_CTRL_ALARM_IRQ               0x4
+#define BF_RTC_CTRL_ALARM_IRQ(v)            (((v) << 2) & 0x4)
+#define BP_RTC_CTRL_ONEMSEC_IRQ_EN          1
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN          0x2
+#define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v)       (((v) << 1) & 0x2)
+#define BP_RTC_CTRL_ALARM_IRQ_EN            0
+#define BM_RTC_CTRL_ALARM_IRQ_EN            0x1
+#define BF_RTC_CTRL_ALARM_IRQ_EN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_RTC_STAT                         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10))
+#define BP_RTC_STAT_RTC_PRESENT             31
+#define BM_RTC_STAT_RTC_PRESENT             0x80000000
+#define BF_RTC_STAT_RTC_PRESENT(v)          (((v) << 31) & 0x80000000)
+#define BP_RTC_STAT_ALARM_PRESENT           30
+#define BM_RTC_STAT_ALARM_PRESENT           0x40000000
+#define BF_RTC_STAT_ALARM_PRESENT(v)        (((v) << 30) & 0x40000000)
+#define BP_RTC_STAT_WATCHDOG_PRESENT        29
+#define BM_RTC_STAT_WATCHDOG_PRESENT        0x20000000
+#define BF_RTC_STAT_WATCHDOG_PRESENT(v)     (((v) << 29) & 0x20000000)
+#define BP_RTC_STAT_XTAL32000_PRESENT       28
+#define BM_RTC_STAT_XTAL32000_PRESENT       0x10000000
+#define BF_RTC_STAT_XTAL32000_PRESENT(v)    (((v) << 28) & 0x10000000)
+#define BP_RTC_STAT_XTAL32768_PRESENT       27
+#define BM_RTC_STAT_XTAL32768_PRESENT       0x8000000
+#define BF_RTC_STAT_XTAL32768_PRESENT(v)    (((v) << 27) & 0x8000000)
+#define BP_RTC_STAT_STALE_REGS              16
+#define BM_RTC_STAT_STALE_REGS              0xff0000
+#define BF_RTC_STAT_STALE_REGS(v)           (((v) << 16) & 0xff0000)
+#define BP_RTC_STAT_NEW_REGS                8
+#define BM_RTC_STAT_NEW_REGS                0xff00
+#define BF_RTC_STAT_NEW_REGS(v)             (((v) << 8) & 0xff00)
+
+/**
+ * Register: HW_RTC_MILLISECONDS
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_RTC_MILLISECONDS             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0))
+#define HW_RTC_MILLISECONDS_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4))
+#define HW_RTC_MILLISECONDS_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8))
+#define HW_RTC_MILLISECONDS_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc))
+#define BP_RTC_MILLISECONDS_COUNT       0
+#define BM_RTC_MILLISECONDS_COUNT       0xffffffff
+#define BF_RTC_MILLISECONDS_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_SECONDS
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_RTC_SECONDS          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0))
+#define HW_RTC_SECONDS_SET      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4))
+#define HW_RTC_SECONDS_CLR      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8))
+#define HW_RTC_SECONDS_TOG      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc))
+#define BP_RTC_SECONDS_COUNT    0
+#define BM_RTC_SECONDS_COUNT    0xffffffff
+#define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_ALARM
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_RTC_ALARM            (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0))
+#define HW_RTC_ALARM_SET        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4))
+#define HW_RTC_ALARM_CLR        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8))
+#define HW_RTC_ALARM_TOG        (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc))
+#define BP_RTC_ALARM_VALUE      0
+#define BM_RTC_ALARM_VALUE      0xffffffff
+#define BF_RTC_ALARM_VALUE(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_WATCHDOG
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_RTC_WATCHDOG             (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0))
+#define HW_RTC_WATCHDOG_SET         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4))
+#define HW_RTC_WATCHDOG_CLR         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8))
+#define HW_RTC_WATCHDOG_TOG         (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc))
+#define BP_RTC_WATCHDOG_COUNT       0
+#define BM_RTC_WATCHDOG_COUNT       0xffffffff
+#define BF_RTC_WATCHDOG_COUNT(v)    (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT0
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT0                      (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0))
+#define HW_RTC_PERSISTENT0_SET                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4))
+#define HW_RTC_PERSISTENT0_CLR                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8))
+#define HW_RTC_PERSISTENT0_TOG                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc))
+#define BP_RTC_PERSISTENT0_SPARE_ANALOG         18
+#define BM_RTC_PERSISTENT0_SPARE_ANALOG         0xfffc0000
+#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v)      (((v) << 18) & 0xfffc0000)
+#define BP_RTC_PERSISTENT0_AUTO_RESTART         17
+#define BM_RTC_PERSISTENT0_AUTO_RESTART         0x20000
+#define BF_RTC_PERSISTENT0_AUTO_RESTART(v)      (((v) << 17) & 0x20000)
+#define BP_RTC_PERSISTENT0_DISABLE_PSWITCH      16
+#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH      0x10000
+#define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v)   (((v) << 16) & 0x10000)
+#define BP_RTC_PERSISTENT0_LOWERBIAS            14
+#define BM_RTC_PERSISTENT0_LOWERBIAS            0xc000
+#define BF_RTC_PERSISTENT0_LOWERBIAS(v)         (((v) << 14) & 0xc000)
+#define BP_RTC_PERSISTENT0_DISABLE_XTALOK       13
+#define BM_RTC_PERSISTENT0_DISABLE_XTALOK       0x2000
+#define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v)    (((v) << 13) & 0x2000)
+#define BP_RTC_PERSISTENT0_MSEC_RES             8
+#define BM_RTC_PERSISTENT0_MSEC_RES             0x1f00
+#define BF_RTC_PERSISTENT0_MSEC_RES(v)          (((v) << 8) & 0x1f00)
+#define BP_RTC_PERSISTENT0_ALARM_WAKE           7
+#define BM_RTC_PERSISTENT0_ALARM_WAKE           0x80
+#define BF_RTC_PERSISTENT0_ALARM_WAKE(v)        (((v) << 7) & 0x80)
+#define BP_RTC_PERSISTENT0_XTAL32_FREQ          6
+#define BM_RTC_PERSISTENT0_XTAL32_FREQ          0x40
+#define BF_RTC_PERSISTENT0_XTAL32_FREQ(v)       (((v) << 6) & 0x40)
+#define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      5
+#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP      0x20
+#define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v)   (((v) << 5) & 0x20)
+#define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      4
+#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP      0x10
+#define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v)   (((v) << 4) & 0x10)
+#define BP_RTC_PERSISTENT0_LCK_SECS             3
+#define BM_RTC_PERSISTENT0_LCK_SECS             0x8
+#define BF_RTC_PERSISTENT0_LCK_SECS(v)          (((v) << 3) & 0x8)
+#define BP_RTC_PERSISTENT0_ALARM_EN             2
+#define BM_RTC_PERSISTENT0_ALARM_EN             0x4
+#define BF_RTC_PERSISTENT0_ALARM_EN(v)          (((v) << 2) & 0x4)
+#define BP_RTC_PERSISTENT0_ALARM_WAKE_EN        1
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN        0x2
+#define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v)     (((v) << 1) & 0x2)
+#define BP_RTC_PERSISTENT0_CLOCKSOURCE          0
+#define BM_RTC_PERSISTENT0_CLOCKSOURCE          0x1
+#define BF_RTC_PERSISTENT0_CLOCKSOURCE(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_PERSISTENT1
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT1                                  (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0))
+#define HW_RTC_PERSISTENT1_SET                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4))
+#define HW_RTC_PERSISTENT1_CLR                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8))
+#define HW_RTC_PERSISTENT1_TOG                              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc))
+#define BP_RTC_PERSISTENT1_GENERAL                          0
+#define BM_RTC_PERSISTENT1_GENERAL                          0xffffffff
+#define BV_RTC_PERSISTENT1_GENERAL__SPARE3                  0x4000
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_BOOT              0x2000
+#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE   0x1000
+#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE    0x800
+#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK          0x400
+#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE      0x200
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT             0x100
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT        0x80
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_HI             0x40
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_LO             0x20
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_3             0x10
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_2             0x8
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_1             0x4
+#define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_0             0x2
+#define BV_RTC_PERSISTENT1_GENERAL__ETM_ENABLE              0x1
+#define BF_RTC_PERSISTENT1_GENERAL(v)                       (((v) << 0) & 0xffffffff)
+#define BF_RTC_PERSISTENT1_GENERAL_V(v)                     ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT2
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT2              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0))
+#define HW_RTC_PERSISTENT2_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4))
+#define HW_RTC_PERSISTENT2_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8))
+#define HW_RTC_PERSISTENT2_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc))
+#define BP_RTC_PERSISTENT2_GENERAL      0
+#define BM_RTC_PERSISTENT2_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT2_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT3
+ * Address: 0x90
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT3              (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0))
+#define HW_RTC_PERSISTENT3_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4))
+#define HW_RTC_PERSISTENT3_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8))
+#define HW_RTC_PERSISTENT3_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc))
+#define BP_RTC_PERSISTENT3_GENERAL      0
+#define BM_RTC_PERSISTENT3_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT3_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT4
+ * Address: 0xa0
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT4              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0))
+#define HW_RTC_PERSISTENT4_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4))
+#define HW_RTC_PERSISTENT4_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8))
+#define HW_RTC_PERSISTENT4_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc))
+#define BP_RTC_PERSISTENT4_GENERAL      0
+#define BM_RTC_PERSISTENT4_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT4_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_PERSISTENT5
+ * Address: 0xb0
+ * SCT: yes
+*/
+#define HW_RTC_PERSISTENT5              (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0))
+#define HW_RTC_PERSISTENT5_SET          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4))
+#define HW_RTC_PERSISTENT5_CLR          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8))
+#define HW_RTC_PERSISTENT5_TOG          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc))
+#define BP_RTC_PERSISTENT5_GENERAL      0
+#define BM_RTC_PERSISTENT5_GENERAL      0xffffffff
+#define BF_RTC_PERSISTENT5_GENERAL(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_RTC_DEBUG
+ * Address: 0xc0
+ * SCT: yes
+*/
+#define HW_RTC_DEBUG                        (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0))
+#define HW_RTC_DEBUG_SET                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4))
+#define HW_RTC_DEBUG_CLR                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8))
+#define HW_RTC_DEBUG_TOG                    (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc))
+#define BP_RTC_DEBUG_WATCHDOG_RESET_MASK    1
+#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK    0x2
+#define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2)
+#define BP_RTC_DEBUG_WATCHDOG_RESET         0
+#define BM_RTC_DEBUG_WATCHDOG_RESET         0x1
+#define BF_RTC_DEBUG_WATCHDOG_RESET(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_RTC_VERSION
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_RTC_VERSION          (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0))
+#define BP_RTC_VERSION_MAJOR    24
+#define BM_RTC_VERSION_MAJOR    0xff000000
+#define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_RTC_VERSION_MINOR    16
+#define BM_RTC_VERSION_MINOR    0xff0000
+#define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_RTC_VERSION_STEP     0
+#define BM_RTC_VERSION_STEP     0xffff
+#define BF_RTC_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__RTC__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h
new file mode 100644
index 0000000000..01faeabc62
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h
@@ -0,0 +1,154 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__SAIF__H__
+#define __HEADERGEN__STMP3700__SAIF__H__
+
+#define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000)
+
+#define REGS_SAIF_VERSION "3.2.0"
+
+/**
+ * Register: HW_SAIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SAIF_CTRL(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0))
+#define HW_SAIF_CTRL_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4))
+#define HW_SAIF_CTRL_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8))
+#define HW_SAIF_CTRL_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc))
+#define BP_SAIF_CTRL_SFTRST                 31
+#define BM_SAIF_CTRL_SFTRST                 0x80000000
+#define BF_SAIF_CTRL_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_SAIF_CTRL_CLKGATE                30
+#define BM_SAIF_CTRL_CLKGATE                0x40000000
+#define BF_SAIF_CTRL_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_SAIF_CTRL_BITCLK_MULT_RATE       27
+#define BM_SAIF_CTRL_BITCLK_MULT_RATE       0x38000000
+#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v)    (((v) << 27) & 0x38000000)
+#define BP_SAIF_CTRL_BITCLK_BASE_RATE       26
+#define BM_SAIF_CTRL_BITCLK_BASE_RATE       0x4000000
+#define BF_SAIF_CTRL_BITCLK_BASE_RATE(v)    (((v) << 26) & 0x4000000)
+#define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN      25
+#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN      0x2000000
+#define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v)   (((v) << 25) & 0x2000000)
+#define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    24
+#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN    0x1000000
+#define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000)
+#define BP_SAIF_CTRL_DMAWAIT_COUNT          16
+#define BM_SAIF_CTRL_DMAWAIT_COUNT          0x1f0000
+#define BF_SAIF_CTRL_DMAWAIT_COUNT(v)       (((v) << 16) & 0x1f0000)
+#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT     14
+#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT     0xc000
+#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v)  (((v) << 14) & 0xc000)
+#define BP_SAIF_CTRL_BIT_ORDER              12
+#define BM_SAIF_CTRL_BIT_ORDER              0x1000
+#define BF_SAIF_CTRL_BIT_ORDER(v)           (((v) << 12) & 0x1000)
+#define BP_SAIF_CTRL_DELAY                  11
+#define BM_SAIF_CTRL_DELAY                  0x800
+#define BF_SAIF_CTRL_DELAY(v)               (((v) << 11) & 0x800)
+#define BP_SAIF_CTRL_JUSTIFY                10
+#define BM_SAIF_CTRL_JUSTIFY                0x400
+#define BF_SAIF_CTRL_JUSTIFY(v)             (((v) << 10) & 0x400)
+#define BP_SAIF_CTRL_LRCLK_POLARITY         9
+#define BM_SAIF_CTRL_LRCLK_POLARITY         0x200
+#define BF_SAIF_CTRL_LRCLK_POLARITY(v)      (((v) << 9) & 0x200)
+#define BP_SAIF_CTRL_BITCLK_EDGE            8
+#define BM_SAIF_CTRL_BITCLK_EDGE            0x100
+#define BF_SAIF_CTRL_BITCLK_EDGE(v)         (((v) << 8) & 0x100)
+#define BP_SAIF_CTRL_WORD_LENGTH            4
+#define BM_SAIF_CTRL_WORD_LENGTH            0xf0
+#define BF_SAIF_CTRL_WORD_LENGTH(v)         (((v) << 4) & 0xf0)
+#define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE    3
+#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE    0x8
+#define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8)
+#define BP_SAIF_CTRL_SLAVE_MODE             2
+#define BM_SAIF_CTRL_SLAVE_MODE             0x4
+#define BF_SAIF_CTRL_SLAVE_MODE(v)          (((v) << 2) & 0x4)
+#define BP_SAIF_CTRL_READ_MODE              1
+#define BM_SAIF_CTRL_READ_MODE              0x2
+#define BF_SAIF_CTRL_READ_MODE(v)           (((v) << 1) & 0x2)
+#define BP_SAIF_CTRL_RUN                    0
+#define BM_SAIF_CTRL_RUN                    0x1
+#define BF_SAIF_CTRL_RUN(v)                 (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SAIF_STAT
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SAIF_STAT(d)                     (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0))
+#define HW_SAIF_STAT_SET(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4))
+#define HW_SAIF_STAT_CLR(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8))
+#define HW_SAIF_STAT_TOG(d)                 (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc))
+#define BP_SAIF_STAT_PRESENT                31
+#define BM_SAIF_STAT_PRESENT                0x80000000
+#define BF_SAIF_STAT_PRESENT(v)             (((v) << 31) & 0x80000000)
+#define BP_SAIF_STAT_DMA_PREQ               16
+#define BM_SAIF_STAT_DMA_PREQ               0x10000
+#define BF_SAIF_STAT_DMA_PREQ(v)            (((v) << 16) & 0x10000)
+#define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ     6
+#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ     0x40
+#define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v)  (((v) << 6) & 0x40)
+#define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ      5
+#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ      0x20
+#define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v)   (((v) << 5) & 0x20)
+#define BP_SAIF_STAT_FIFO_SERVICE_IRQ       4
+#define BM_SAIF_STAT_FIFO_SERVICE_IRQ       0x10
+#define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v)    (((v) << 4) & 0x10)
+#define BP_SAIF_STAT_BUSY                   0
+#define BM_SAIF_STAT_BUSY                   0x1
+#define BF_SAIF_STAT_BUSY(v)                (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SAIF_DATA
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_SAIF_DATA(d)             (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0))
+#define HW_SAIF_DATA_SET(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4))
+#define HW_SAIF_DATA_CLR(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8))
+#define HW_SAIF_DATA_TOG(d)         (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc))
+#define BP_SAIF_DATA_PCM_RIGHT      16
+#define BM_SAIF_DATA_PCM_RIGHT      0xffff0000
+#define BF_SAIF_DATA_PCM_RIGHT(v)   (((v) << 16) & 0xffff0000)
+#define BP_SAIF_DATA_PCM_LEFT       0
+#define BM_SAIF_DATA_PCM_LEFT       0xffff
+#define BF_SAIF_DATA_PCM_LEFT(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_SAIF_VERSION
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_SAIF_VERSION(d)          (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30))
+#define BP_SAIF_VERSION_MAJOR       24
+#define BM_SAIF_VERSION_MAJOR       0xff000000
+#define BF_SAIF_VERSION_MAJOR(v)    (((v) << 24) & 0xff000000)
+#define BP_SAIF_VERSION_MINOR       16
+#define BM_SAIF_VERSION_MINOR       0xff0000
+#define BF_SAIF_VERSION_MINOR(v)    (((v) << 16) & 0xff0000)
+#define BP_SAIF_VERSION_STEP        0
+#define BM_SAIF_VERSION_STEP        0xffff
+#define BF_SAIF_VERSION_STEP(v)     (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__SAIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h
new file mode 100644
index 0000000000..4d58761ba9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h
@@ -0,0 +1,181 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__SPDIF__H__
+#define __HEADERGEN__STMP3700__SPDIF__H__
+
+#define REGS_SPDIF_BASE (0x80054000)
+
+#define REGS_SPDIF_VERSION "3.2.0"
+
+/**
+ * Register: HW_SPDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SPDIF_CTRL                       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0))
+#define HW_SPDIF_CTRL_SET                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4))
+#define HW_SPDIF_CTRL_CLR                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8))
+#define HW_SPDIF_CTRL_TOG                   (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc))
+#define BP_SPDIF_CTRL_SFTRST                31
+#define BM_SPDIF_CTRL_SFTRST                0x80000000
+#define BF_SPDIF_CTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
+#define BP_SPDIF_CTRL_CLKGATE               30
+#define BM_SPDIF_CTRL_CLKGATE               0x40000000
+#define BF_SPDIF_CTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
+#define BP_SPDIF_CTRL_DMAWAIT_COUNT         16
+#define BM_SPDIF_CTRL_DMAWAIT_COUNT         0x1f0000
+#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v)      (((v) << 16) & 0x1f0000)
+#define BP_SPDIF_CTRL_WAIT_END_XFER         5
+#define BM_SPDIF_CTRL_WAIT_END_XFER         0x20
+#define BF_SPDIF_CTRL_WAIT_END_XFER(v)      (((v) << 5) & 0x20)
+#define BP_SPDIF_CTRL_WORD_LENGTH           4
+#define BM_SPDIF_CTRL_WORD_LENGTH           0x10
+#define BF_SPDIF_CTRL_WORD_LENGTH(v)        (((v) << 4) & 0x10)
+#define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    3
+#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ    0x8
+#define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8)
+#define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     2
+#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ     0x4
+#define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v)  (((v) << 2) & 0x4)
+#define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     1
+#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN     0x2
+#define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v)  (((v) << 1) & 0x2)
+#define BP_SPDIF_CTRL_RUN                   0
+#define BM_SPDIF_CTRL_RUN                   0x1
+#define BF_SPDIF_CTRL_RUN(v)                (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_STAT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_SPDIF_STAT               (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10))
+#define BP_SPDIF_STAT_PRESENT       31
+#define BM_SPDIF_STAT_PRESENT       0x80000000
+#define BF_SPDIF_STAT_PRESENT(v)    (((v) << 31) & 0x80000000)
+#define BP_SPDIF_STAT_END_XFER      0
+#define BM_SPDIF_STAT_END_XFER      0x1
+#define BF_SPDIF_STAT_END_XFER(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_FRAMECTRL
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_SPDIF_FRAMECTRL              (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0))
+#define HW_SPDIF_FRAMECTRL_SET          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4))
+#define HW_SPDIF_FRAMECTRL_CLR          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8))
+#define HW_SPDIF_FRAMECTRL_TOG          (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc))
+#define BP_SPDIF_FRAMECTRL_V_CONFIG     17
+#define BM_SPDIF_FRAMECTRL_V_CONFIG     0x20000
+#define BF_SPDIF_FRAMECTRL_V_CONFIG(v)  (((v) << 17) & 0x20000)
+#define BP_SPDIF_FRAMECTRL_AUTO_MUTE    16
+#define BM_SPDIF_FRAMECTRL_AUTO_MUTE    0x10000
+#define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000)
+#define BP_SPDIF_FRAMECTRL_USER_DATA    14
+#define BM_SPDIF_FRAMECTRL_USER_DATA    0x4000
+#define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000)
+#define BP_SPDIF_FRAMECTRL_V            13
+#define BM_SPDIF_FRAMECTRL_V            0x2000
+#define BF_SPDIF_FRAMECTRL_V(v)         (((v) << 13) & 0x2000)
+#define BP_SPDIF_FRAMECTRL_L            12
+#define BM_SPDIF_FRAMECTRL_L            0x1000
+#define BF_SPDIF_FRAMECTRL_L(v)         (((v) << 12) & 0x1000)
+#define BP_SPDIF_FRAMECTRL_CC           4
+#define BM_SPDIF_FRAMECTRL_CC           0x7f0
+#define BF_SPDIF_FRAMECTRL_CC(v)        (((v) << 4) & 0x7f0)
+#define BP_SPDIF_FRAMECTRL_PRE          3
+#define BM_SPDIF_FRAMECTRL_PRE          0x8
+#define BF_SPDIF_FRAMECTRL_PRE(v)       (((v) << 3) & 0x8)
+#define BP_SPDIF_FRAMECTRL_COPY         2
+#define BM_SPDIF_FRAMECTRL_COPY         0x4
+#define BF_SPDIF_FRAMECTRL_COPY(v)      (((v) << 2) & 0x4)
+#define BP_SPDIF_FRAMECTRL_AUDIO        1
+#define BM_SPDIF_FRAMECTRL_AUDIO        0x2
+#define BF_SPDIF_FRAMECTRL_AUDIO(v)     (((v) << 1) & 0x2)
+#define BP_SPDIF_FRAMECTRL_PRO          0
+#define BM_SPDIF_FRAMECTRL_PRO          0x1
+#define BF_SPDIF_FRAMECTRL_PRO(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_SRR
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_SPDIF_SRR                (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0))
+#define HW_SPDIF_SRR_SET            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4))
+#define HW_SPDIF_SRR_CLR            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8))
+#define HW_SPDIF_SRR_TOG            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc))
+#define BP_SPDIF_SRR_BASEMULT       28
+#define BM_SPDIF_SRR_BASEMULT       0x70000000
+#define BF_SPDIF_SRR_BASEMULT(v)    (((v) << 28) & 0x70000000)
+#define BP_SPDIF_SRR_RATE           0
+#define BM_SPDIF_SRR_RATE           0xfffff
+#define BF_SPDIF_SRR_RATE(v)        (((v) << 0) & 0xfffff)
+
+/**
+ * Register: HW_SPDIF_DEBUG
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_SPDIF_DEBUG                  (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40))
+#define BP_SPDIF_DEBUG_DMA_PREQ         1
+#define BM_SPDIF_DEBUG_DMA_PREQ         0x2
+#define BF_SPDIF_DEBUG_DMA_PREQ(v)      (((v) << 1) & 0x2)
+#define BP_SPDIF_DEBUG_FIFO_STATUS      0
+#define BM_SPDIF_DEBUG_FIFO_STATUS      0x1
+#define BF_SPDIF_DEBUG_FIFO_STATUS(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SPDIF_DATA
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_SPDIF_DATA           (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0))
+#define HW_SPDIF_DATA_SET       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4))
+#define HW_SPDIF_DATA_CLR       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8))
+#define HW_SPDIF_DATA_TOG       (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc))
+#define BP_SPDIF_DATA_HIGH      16
+#define BM_SPDIF_DATA_HIGH      0xffff0000
+#define BF_SPDIF_DATA_HIGH(v)   (((v) << 16) & 0xffff0000)
+#define BP_SPDIF_DATA_LOW       0
+#define BM_SPDIF_DATA_LOW       0xffff
+#define BF_SPDIF_DATA_LOW(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_SPDIF_VERSION
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_SPDIF_VERSION            (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60))
+#define BP_SPDIF_VERSION_MAJOR      24
+#define BM_SPDIF_VERSION_MAJOR      0xff000000
+#define BF_SPDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_SPDIF_VERSION_MINOR      16
+#define BM_SPDIF_VERSION_MINOR      0xff0000
+#define BF_SPDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_SPDIF_VERSION_STEP       0
+#define BM_SPDIF_VERSION_STEP       0xffff
+#define BF_SPDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__SPDIF__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h
new file mode 100644
index 0000000000..463cf26cf7
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h
@@ -0,0 +1,558 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__SSP__H__
+#define __HEADERGEN__STMP3700__SSP__H__
+
+#define REGS_SSP_BASE(i) ((i) == 1 ? 0x80010000 : 0x80034000)
+
+#define REGS_SSP_VERSION "3.2.0"
+
+/**
+ * Register: HW_SSP_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_SSP_CTRL0(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x0))
+#define HW_SSP_CTRL0_SET(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x4))
+#define HW_SSP_CTRL0_CLR(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x8))
+#define HW_SSP_CTRL0_TOG(d)                 (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0xc))
+#define BP_SSP_CTRL0_SFTRST                 31
+#define BM_SSP_CTRL0_SFTRST                 0x80000000
+#define BF_SSP_CTRL0_SFTRST(v)              (((v) << 31) & 0x80000000)
+#define BP_SSP_CTRL0_CLKGATE                30
+#define BM_SSP_CTRL0_CLKGATE                0x40000000
+#define BF_SSP_CTRL0_CLKGATE(v)             (((v) << 30) & 0x40000000)
+#define BP_SSP_CTRL0_RUN                    29
+#define BM_SSP_CTRL0_RUN                    0x20000000
+#define BF_SSP_CTRL0_RUN(v)                 (((v) << 29) & 0x20000000)
+#define BP_SSP_CTRL0_SDIO_IRQ_CHECK         28
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK         0x10000000
+#define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v)      (((v) << 28) & 0x10000000)
+#define BP_SSP_CTRL0_LOCK_CS                27
+#define BM_SSP_CTRL0_LOCK_CS                0x8000000
+#define BF_SSP_CTRL0_LOCK_CS(v)             (((v) << 27) & 0x8000000)
+#define BP_SSP_CTRL0_IGNORE_CRC             26
+#define BM_SSP_CTRL0_IGNORE_CRC             0x4000000
+#define BF_SSP_CTRL0_IGNORE_CRC(v)          (((v) << 26) & 0x4000000)
+#define BP_SSP_CTRL0_READ                   25
+#define BM_SSP_CTRL0_READ                   0x2000000
+#define BF_SSP_CTRL0_READ(v)                (((v) << 25) & 0x2000000)
+#define BP_SSP_CTRL0_DATA_XFER              24
+#define BM_SSP_CTRL0_DATA_XFER              0x1000000
+#define BF_SSP_CTRL0_DATA_XFER(v)           (((v) << 24) & 0x1000000)
+#define BP_SSP_CTRL0_BUS_WIDTH              22
+#define BM_SSP_CTRL0_BUS_WIDTH              0xc00000
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT     0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT    0x1
+#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT   0x2
+#define BF_SSP_CTRL0_BUS_WIDTH(v)           (((v) << 22) & 0xc00000)
+#define BF_SSP_CTRL0_BUS_WIDTH_V(v)         ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0xc00000)
+#define BP_SSP_CTRL0_WAIT_FOR_IRQ           21
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ           0x200000
+#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v)        (((v) << 21) & 0x200000)
+#define BP_SSP_CTRL0_WAIT_FOR_CMD           20
+#define BM_SSP_CTRL0_WAIT_FOR_CMD           0x100000
+#define BF_SSP_CTRL0_WAIT_FOR_CMD(v)        (((v) << 20) & 0x100000)
+#define BP_SSP_CTRL0_LONG_RESP              19
+#define BM_SSP_CTRL0_LONG_RESP              0x80000
+#define BF_SSP_CTRL0_LONG_RESP(v)           (((v) << 19) & 0x80000)
+#define BP_SSP_CTRL0_CHECK_RESP             18
+#define BM_SSP_CTRL0_CHECK_RESP             0x40000
+#define BF_SSP_CTRL0_CHECK_RESP(v)          (((v) << 18) & 0x40000)
+#define BP_SSP_CTRL0_GET_RESP               17
+#define BM_SSP_CTRL0_GET_RESP               0x20000
+#define BF_SSP_CTRL0_GET_RESP(v)            (((v) << 17) & 0x20000)
+#define BP_SSP_CTRL0_ENABLE                 16
+#define BM_SSP_CTRL0_ENABLE                 0x10000
+#define BF_SSP_CTRL0_ENABLE(v)              (((v) << 16) & 0x10000)
+#define BP_SSP_CTRL0_XFER_COUNT             0
+#define BM_SSP_CTRL0_XFER_COUNT             0xffff
+#define BF_SSP_CTRL0_XFER_COUNT(v)          (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_SSP_CMD0
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_SSP_CMD0(d)                              (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x0))
+#define HW_SSP_CMD0_SET(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x4))
+#define HW_SSP_CMD0_CLR(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x8))
+#define HW_SSP_CMD0_TOG(d)                          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0xc))
+#define BP_SSP_CMD0_APPEND_8CYC                     20
+#define BM_SSP_CMD0_APPEND_8CYC                     0x100000
+#define BF_SSP_CMD0_APPEND_8CYC(v)                  (((v) << 20) & 0x100000)
+#define BP_SSP_CMD0_BLOCK_SIZE                      16
+#define BM_SSP_CMD0_BLOCK_SIZE                      0xf0000
+#define BF_SSP_CMD0_BLOCK_SIZE(v)                   (((v) << 16) & 0xf0000)
+#define BP_SSP_CMD0_BLOCK_COUNT                     8
+#define BM_SSP_CMD0_BLOCK_COUNT                     0xff00
+#define BF_SSP_CMD0_BLOCK_COUNT(v)                  (((v) << 8) & 0xff00)
+#define BP_SSP_CMD0_CMD                             0
+#define BM_SSP_CMD0_CMD                             0xff
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE          0x0
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND           0x1
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID           0x2
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR                0x4
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5             0x5
+#define BV_SSP_CMD0_CMD__MMC_SWITCH                 0x6
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD   0x7
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD           0x8
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD               0x9
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID               0xa
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP    0xb
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION      0xc
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS            0xd
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R              0xe
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE      0xf
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN           0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK      0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK    0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W              0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP   0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT        0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK            0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK   0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID            0x1a
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD            0x1b
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT         0x1c
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT         0x1d
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT        0x1e
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START      0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END        0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE                  0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO                0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE           0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK            0x2a
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD                0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD                0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE           0x0
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID            0x2
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR      0x3
+#define BV_SSP_CMD0_CMD__SD_SET_DSR                 0x4
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND         0x5
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD    0x7
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD                0x9
+#define BV_SSP_CMD0_CMD__SD_SEND_CID                0xa
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION       0xc
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS             0xd
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE       0xf
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN            0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK       0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK     0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK             0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK    0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD             0x1b
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT          0x1c
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT          0x1d
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT         0x1e
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START      0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END        0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START       0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END         0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE                   0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK             0x2a
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT            0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED          0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD                 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD                 0x38
+#define BF_SSP_CMD0_CMD(v)                          (((v) << 0) & 0xff)
+#define BF_SSP_CMD0_CMD_V(v)                        ((BV_SSP_CMD0_CMD__##v << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_CMD1
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_SSP_CMD1(d)          (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x20))
+#define BP_SSP_CMD1_CMD_ARG     0
+#define BM_SSP_CMD1_CMD_ARG     0xffffffff
+#define BF_SSP_CMD1_CMD_ARG(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_COMPREF
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_SSP_COMPREF(d)           (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x30))
+#define BP_SSP_COMPREF_REFERENCE    0
+#define BM_SSP_COMPREF_REFERENCE    0xffffffff
+#define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_COMPMASK
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_SSP_COMPMASK(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x40))
+#define BP_SSP_COMPMASK_MASK    0
+#define BM_SSP_COMPMASK_MASK    0xffffffff
+#define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_TIMING
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_SSP_TIMING(d)                (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x50))
+#define BP_SSP_TIMING_TIMEOUT           16
+#define BM_SSP_TIMING_TIMEOUT           0xffff0000
+#define BF_SSP_TIMING_TIMEOUT(v)        (((v) << 16) & 0xffff0000)
+#define BP_SSP_TIMING_CLOCK_DIVIDE      8
+#define BM_SSP_TIMING_CLOCK_DIVIDE      0xff00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v)   (((v) << 8) & 0xff00)
+#define BP_SSP_TIMING_CLOCK_RATE        0
+#define BM_SSP_TIMING_CLOCK_RATE        0xff
+#define BF_SSP_TIMING_CLOCK_RATE(v)     (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_CTRL1
+ * Address: 0x60
+ * SCT: yes
+*/
+#define HW_SSP_CTRL1(d)                         (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x0))
+#define HW_SSP_CTRL1_SET(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x4))
+#define HW_SSP_CTRL1_CLR(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x8))
+#define HW_SSP_CTRL1_TOG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0xc))
+#define BP_SSP_CTRL1_SDIO_IRQ                   31
+#define BM_SSP_CTRL1_SDIO_IRQ                   0x80000000
+#define BF_SSP_CTRL1_SDIO_IRQ(v)                (((v) << 31) & 0x80000000)
+#define BP_SSP_CTRL1_SDIO_IRQ_EN                30
+#define BM_SSP_CTRL1_SDIO_IRQ_EN                0x40000000
+#define BF_SSP_CTRL1_SDIO_IRQ_EN(v)             (((v) << 30) & 0x40000000)
+#define BP_SSP_CTRL1_RESP_ERR_IRQ               29
+#define BM_SSP_CTRL1_RESP_ERR_IRQ               0x20000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ(v)            (((v) << 29) & 0x20000000)
+#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN            28
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN            0x10000000
+#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v)         (((v) << 28) & 0x10000000)
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ           27
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ           0x8000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v)        (((v) << 27) & 0x8000000)
+#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        26
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN        0x4000000
+#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v)     (((v) << 26) & 0x4000000)
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ           25
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ           0x2000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v)        (((v) << 25) & 0x2000000)
+#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        24
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN        0x1000000
+#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v)     (((v) << 24) & 0x1000000)
+#define BP_SSP_CTRL1_DATA_CRC_IRQ               23
+#define BM_SSP_CTRL1_DATA_CRC_IRQ               0x800000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ(v)            (((v) << 23) & 0x800000)
+#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN            22
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN            0x400000
+#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v)         (((v) << 22) & 0x400000)
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ          21
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ          0x200000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v)       (((v) << 21) & 0x200000)
+#define BP_SSP_CTRL1_FIFO_UNDERRUN_EN           20
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN           0x100000
+#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v)        (((v) << 20) & 0x100000)
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ          19
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ          0x80000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v)       (((v) << 19) & 0x80000)
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       18
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN       0x40000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v)    (((v) << 18) & 0x40000)
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ           17
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ           0x20000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v)        (((v) << 17) & 0x20000)
+#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        16
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN        0x10000
+#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v)     (((v) << 16) & 0x10000)
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ           15
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ           0x8000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v)        (((v) << 15) & 0x8000)
+#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        14
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN        0x4000
+#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v)     (((v) << 14) & 0x4000)
+#define BP_SSP_CTRL1_DMA_ENABLE                 13
+#define BM_SSP_CTRL1_DMA_ENABLE                 0x2000
+#define BF_SSP_CTRL1_DMA_ENABLE(v)              (((v) << 13) & 0x2000)
+#define BP_SSP_CTRL1_CEATA_CCS_ERR_EN           12
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN           0x1000
+#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v)        (((v) << 12) & 0x1000)
+#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE          11
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE          0x800
+#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v)       (((v) << 11) & 0x800)
+#define BP_SSP_CTRL1_PHASE                      10
+#define BM_SSP_CTRL1_PHASE                      0x400
+#define BF_SSP_CTRL1_PHASE(v)                   (((v) << 10) & 0x400)
+#define BP_SSP_CTRL1_POLARITY                   9
+#define BM_SSP_CTRL1_POLARITY                   0x200
+#define BF_SSP_CTRL1_POLARITY(v)                (((v) << 9) & 0x200)
+#define BP_SSP_CTRL1_SLAVE_MODE                 8
+#define BM_SSP_CTRL1_SLAVE_MODE                 0x100
+#define BF_SSP_CTRL1_SLAVE_MODE(v)              (((v) << 8) & 0x100)
+#define BP_SSP_CTRL1_WORD_LENGTH                4
+#define BM_SSP_CTRL1_WORD_LENGTH                0xf0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0     0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1     0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2     0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS     0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS    0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS  0xf
+#define BF_SSP_CTRL1_WORD_LENGTH(v)             (((v) << 4) & 0xf0)
+#define BF_SSP_CTRL1_WORD_LENGTH_V(v)           ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0)
+#define BP_SSP_CTRL1_SSP_MODE                   0
+#define BM_SSP_CTRL1_SSP_MODE                   0xf
+#define BV_SSP_CTRL1_SSP_MODE__SPI              0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI              0x1
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC           0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS               0x4
+#define BV_SSP_CTRL1_SSP_MODE__CE_ATA           0x7
+#define BF_SSP_CTRL1_SSP_MODE(v)                (((v) << 0) & 0xf)
+#define BF_SSP_CTRL1_SSP_MODE_V(v)              ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf)
+
+/**
+ * Register: HW_SSP_DATA
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_SSP_DATA(d)      (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x70))
+#define BP_SSP_DATA_DATA    0
+#define BM_SSP_DATA_DATA    0xffffffff
+#define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP0
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_SSP_SDRESP0(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x80))
+#define BP_SSP_SDRESP0_RESP0    0
+#define BM_SSP_SDRESP0_RESP0    0xffffffff
+#define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP1
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_SSP_SDRESP1(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x90))
+#define BP_SSP_SDRESP1_RESP1    0
+#define BM_SSP_SDRESP1_RESP1    0xffffffff
+#define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP2
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_SSP_SDRESP2(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xa0))
+#define BP_SSP_SDRESP2_RESP2    0
+#define BM_SSP_SDRESP2_RESP2    0xffffffff
+#define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_SDRESP3
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_SSP_SDRESP3(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xb0))
+#define BP_SSP_SDRESP3_RESP3    0
+#define BM_SSP_SDRESP3_RESP3    0xffffffff
+#define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_SSP_STATUS
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_SSP_STATUS(d)                    (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xc0))
+#define BP_SSP_STATUS_PRESENT               31
+#define BM_SSP_STATUS_PRESENT               0x80000000
+#define BF_SSP_STATUS_PRESENT(v)            (((v) << 31) & 0x80000000)
+#define BP_SSP_STATUS_MS_PRESENT            30
+#define BM_SSP_STATUS_MS_PRESENT            0x40000000
+#define BF_SSP_STATUS_MS_PRESENT(v)         (((v) << 30) & 0x40000000)
+#define BP_SSP_STATUS_SD_PRESENT            29
+#define BM_SSP_STATUS_SD_PRESENT            0x20000000
+#define BF_SSP_STATUS_SD_PRESENT(v)         (((v) << 29) & 0x20000000)
+#define BP_SSP_STATUS_CARD_DETECT           28
+#define BM_SSP_STATUS_CARD_DETECT           0x10000000
+#define BF_SSP_STATUS_CARD_DETECT(v)        (((v) << 28) & 0x10000000)
+#define BP_SSP_STATUS_DMASENSE              21
+#define BM_SSP_STATUS_DMASENSE              0x200000
+#define BF_SSP_STATUS_DMASENSE(v)           (((v) << 21) & 0x200000)
+#define BP_SSP_STATUS_DMATERM               20
+#define BM_SSP_STATUS_DMATERM               0x100000
+#define BF_SSP_STATUS_DMATERM(v)            (((v) << 20) & 0x100000)
+#define BP_SSP_STATUS_DMAREQ                19
+#define BM_SSP_STATUS_DMAREQ                0x80000
+#define BF_SSP_STATUS_DMAREQ(v)             (((v) << 19) & 0x80000)
+#define BP_SSP_STATUS_DMAEND                18
+#define BM_SSP_STATUS_DMAEND                0x40000
+#define BF_SSP_STATUS_DMAEND(v)             (((v) << 18) & 0x40000)
+#define BP_SSP_STATUS_SDIO_IRQ              17
+#define BM_SSP_STATUS_SDIO_IRQ              0x20000
+#define BF_SSP_STATUS_SDIO_IRQ(v)           (((v) << 17) & 0x20000)
+#define BP_SSP_STATUS_RESP_CRC_ERR          16
+#define BM_SSP_STATUS_RESP_CRC_ERR          0x10000
+#define BF_SSP_STATUS_RESP_CRC_ERR(v)       (((v) << 16) & 0x10000)
+#define BP_SSP_STATUS_RESP_ERR              15
+#define BM_SSP_STATUS_RESP_ERR              0x8000
+#define BF_SSP_STATUS_RESP_ERR(v)           (((v) << 15) & 0x8000)
+#define BP_SSP_STATUS_RESP_TIMEOUT          14
+#define BM_SSP_STATUS_RESP_TIMEOUT          0x4000
+#define BF_SSP_STATUS_RESP_TIMEOUT(v)       (((v) << 14) & 0x4000)
+#define BP_SSP_STATUS_DATA_CRC_ERR          13
+#define BM_SSP_STATUS_DATA_CRC_ERR          0x2000
+#define BF_SSP_STATUS_DATA_CRC_ERR(v)       (((v) << 13) & 0x2000)
+#define BP_SSP_STATUS_TIMEOUT               12
+#define BM_SSP_STATUS_TIMEOUT               0x1000
+#define BF_SSP_STATUS_TIMEOUT(v)            (((v) << 12) & 0x1000)
+#define BP_SSP_STATUS_RECV_TIMEOUT_STAT     11
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT     0x800
+#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v)  (((v) << 11) & 0x800)
+#define BP_SSP_STATUS_CEATA_CCS_ERR         10
+#define BM_SSP_STATUS_CEATA_CCS_ERR         0x400
+#define BF_SSP_STATUS_CEATA_CCS_ERR(v)      (((v) << 10) & 0x400)
+#define BP_SSP_STATUS_FIFO_OVRFLW           9
+#define BM_SSP_STATUS_FIFO_OVRFLW           0x200
+#define BF_SSP_STATUS_FIFO_OVRFLW(v)        (((v) << 9) & 0x200)
+#define BP_SSP_STATUS_FIFO_FULL             8
+#define BM_SSP_STATUS_FIFO_FULL             0x100
+#define BF_SSP_STATUS_FIFO_FULL(v)          (((v) << 8) & 0x100)
+#define BP_SSP_STATUS_FIFO_EMPTY            5
+#define BM_SSP_STATUS_FIFO_EMPTY            0x20
+#define BF_SSP_STATUS_FIFO_EMPTY(v)         (((v) << 5) & 0x20)
+#define BP_SSP_STATUS_FIFO_UNDRFLW          4
+#define BM_SSP_STATUS_FIFO_UNDRFLW          0x10
+#define BF_SSP_STATUS_FIFO_UNDRFLW(v)       (((v) << 4) & 0x10)
+#define BP_SSP_STATUS_CMD_BUSY              3
+#define BM_SSP_STATUS_CMD_BUSY              0x8
+#define BF_SSP_STATUS_CMD_BUSY(v)           (((v) << 3) & 0x8)
+#define BP_SSP_STATUS_DATA_BUSY             2
+#define BM_SSP_STATUS_DATA_BUSY             0x4
+#define BF_SSP_STATUS_DATA_BUSY(v)          (((v) << 2) & 0x4)
+#define BP_SSP_STATUS_BUSY                  0
+#define BM_SSP_STATUS_BUSY                  0x1
+#define BF_SSP_STATUS_BUSY(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_SSP_DEBUG
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_SSP_DEBUG(d)                     (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x100))
+#define BP_SSP_DEBUG_DATACRC_ERR            28
+#define BM_SSP_DEBUG_DATACRC_ERR            0xf0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v)         (((v) << 28) & 0xf0000000)
+#define BP_SSP_DEBUG_DATA_STALL             27
+#define BM_SSP_DEBUG_DATA_STALL             0x8000000
+#define BF_SSP_DEBUG_DATA_STALL(v)          (((v) << 27) & 0x8000000)
+#define BP_SSP_DEBUG_DAT_SM                 24
+#define BM_SSP_DEBUG_DAT_SM                 0x7000000
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE       0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD       0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1       0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2       0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END        0x5
+#define BF_SSP_DEBUG_DAT_SM(v)              (((v) << 24) & 0x7000000)
+#define BF_SSP_DEBUG_DAT_SM_V(v)            ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000)
+#define BP_SSP_DEBUG_MSTK_SM                20
+#define BM_SSP_DEBUG_MSTK_SM                0xf00000
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE     0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON     0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1      0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC      0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2      0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK    0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3      0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW       0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1     0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2     0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0      0xa
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1     0xb
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W    0xc
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R    0xd
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE     0xe
+#define BF_SSP_DEBUG_MSTK_SM(v)             (((v) << 20) & 0xf00000)
+#define BF_SSP_DEBUG_MSTK_SM_V(v)           ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000)
+#define BP_SSP_DEBUG_CMD_OE                 19
+#define BM_SSP_DEBUG_CMD_OE                 0x80000
+#define BF_SSP_DEBUG_CMD_OE(v)              (((v) << 19) & 0x80000)
+#define BP_SSP_DEBUG_DMA_SM                 16
+#define BM_SSP_DEBUG_DMA_SM                 0x70000
+#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE       0x0
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ     0x1
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK     0x2
+#define BV_SSP_DEBUG_DMA_SM__DMA_STALL      0x3
+#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY       0x4
+#define BV_SSP_DEBUG_DMA_SM__DMA_DONE       0x5
+#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT      0x6
+#define BF_SSP_DEBUG_DMA_SM(v)              (((v) << 16) & 0x70000)
+#define BF_SSP_DEBUG_DMA_SM_V(v)            ((BV_SSP_DEBUG_DMA_SM__##v << 16) & 0x70000)
+#define BP_SSP_DEBUG_MMC_SM                 12
+#define BM_SSP_DEBUG_MMC_SM                 0xf000
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE       0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD        0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC        0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP       0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX       0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX         0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK       0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX         0x7
+#define BV_SSP_DEBUG_MMC_SM__MMC_CCS        0x8
+#define BV_SSP_DEBUG_MMC_SM__MMC_PUP        0x9
+#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT       0xa
+#define BF_SSP_DEBUG_MMC_SM(v)              (((v) << 12) & 0xf000)
+#define BF_SSP_DEBUG_MMC_SM_V(v)            ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0xf000)
+#define BP_SSP_DEBUG_CMD_SM                 10
+#define BM_SSP_DEBUG_CMD_SM                 0xc00
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE       0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX      0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG        0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC        0x3
+#define BF_SSP_DEBUG_CMD_SM(v)              (((v) << 10) & 0xc00)
+#define BF_SSP_DEBUG_CMD_SM_V(v)            ((BV_SSP_DEBUG_CMD_SM__##v << 10) & 0xc00)
+#define BP_SSP_DEBUG_SSP_CMD                9
+#define BM_SSP_DEBUG_SSP_CMD                0x200
+#define BF_SSP_DEBUG_SSP_CMD(v)             (((v) << 9) & 0x200)
+#define BP_SSP_DEBUG_SSP_RESP               8
+#define BM_SSP_DEBUG_SSP_RESP               0x100
+#define BF_SSP_DEBUG_SSP_RESP(v)            (((v) << 8) & 0x100)
+#define BP_SSP_DEBUG_SSP_RXD                0
+#define BM_SSP_DEBUG_SSP_RXD                0xff
+#define BF_SSP_DEBUG_SSP_RXD(v)             (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_SSP_VERSION
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_SSP_VERSION(d)       (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x110))
+#define BP_SSP_VERSION_MAJOR    24
+#define BM_SSP_VERSION_MAJOR    0xff000000
+#define BF_SSP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_SSP_VERSION_MINOR    16
+#define BM_SSP_VERSION_MINOR    0xff0000
+#define BF_SSP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_SSP_VERSION_STEP     0
+#define BM_SSP_VERSION_STEP     0xffff
+#define BF_SSP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__SSP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h
new file mode 100644
index 0000000000..a741fc6856
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h
@@ -0,0 +1,283 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__TIMROT__H__
+#define __HEADERGEN__STMP3700__TIMROT__H__
+
+#define REGS_TIMROT_BASE (0x80068000)
+
+#define REGS_TIMROT_VERSION "3.2.0"
+
+/**
+ * Register: HW_TIMROT_ROTCTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_TIMROT_ROTCTRL                       (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0))
+#define HW_TIMROT_ROTCTRL_SET                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4))
+#define HW_TIMROT_ROTCTRL_CLR                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8))
+#define HW_TIMROT_ROTCTRL_TOG                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc))
+#define BP_TIMROT_ROTCTRL_SFTRST                31
+#define BM_TIMROT_ROTCTRL_SFTRST                0x80000000
+#define BF_TIMROT_ROTCTRL_SFTRST(v)             (((v) << 31) & 0x80000000)
+#define BP_TIMROT_ROTCTRL_CLKGATE               30
+#define BM_TIMROT_ROTCTRL_CLKGATE               0x40000000
+#define BF_TIMROT_ROTCTRL_CLKGATE(v)            (((v) << 30) & 0x40000000)
+#define BP_TIMROT_ROTCTRL_ROTARY_PRESENT        29
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT        0x20000000
+#define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v)     (((v) << 29) & 0x20000000)
+#define BP_TIMROT_ROTCTRL_TIM3_PRESENT          28
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT          0x10000000
+#define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v)       (((v) << 28) & 0x10000000)
+#define BP_TIMROT_ROTCTRL_TIM2_PRESENT          27
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT          0x8000000
+#define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v)       (((v) << 27) & 0x8000000)
+#define BP_TIMROT_ROTCTRL_TIM1_PRESENT          26
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT          0x4000000
+#define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v)       (((v) << 26) & 0x4000000)
+#define BP_TIMROT_ROTCTRL_TIM0_PRESENT          25
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT          0x2000000
+#define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v)       (((v) << 25) & 0x2000000)
+#define BP_TIMROT_ROTCTRL_STATE                 22
+#define BM_TIMROT_ROTCTRL_STATE                 0x1c00000
+#define BF_TIMROT_ROTCTRL_STATE(v)              (((v) << 22) & 0x1c00000)
+#define BP_TIMROT_ROTCTRL_DIVIDER               16
+#define BM_TIMROT_ROTCTRL_DIVIDER               0x3f0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v)            (((v) << 16) & 0x3f0000)
+#define BP_TIMROT_ROTCTRL_RELATIVE              12
+#define BM_TIMROT_ROTCTRL_RELATIVE              0x1000
+#define BF_TIMROT_ROTCTRL_RELATIVE(v)           (((v) << 12) & 0x1000)
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE            10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE            0xc00
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X        0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X        0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X        0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X        0x3
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v)         (((v) << 10) & 0xc00)
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v)       ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00)
+#define BP_TIMROT_ROTCTRL_POLARITY_B            9
+#define BM_TIMROT_ROTCTRL_POLARITY_B            0x200
+#define BF_TIMROT_ROTCTRL_POLARITY_B(v)         (((v) << 9) & 0x200)
+#define BP_TIMROT_ROTCTRL_POLARITY_A            8
+#define BM_TIMROT_ROTCTRL_POLARITY_A            0x100
+#define BF_TIMROT_ROTCTRL_POLARITY_A(v)         (((v) << 8) & 0x100)
+#define BP_TIMROT_ROTCTRL_SELECT_B              4
+#define BM_TIMROT_ROTCTRL_SELECT_B              0x70
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_B(v)           (((v) << 4) & 0x70)
+#define BF_TIMROT_ROTCTRL_SELECT_B_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70)
+#define BP_TIMROT_ROTCTRL_SELECT_A              0
+#define BM_TIMROT_ROTCTRL_SELECT_A              0x7
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK  0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0        0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1        0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2        0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3        0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4        0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA     0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB     0x7
+#define BF_TIMROT_ROTCTRL_SELECT_A(v)           (((v) << 0) & 0x7)
+#define BF_TIMROT_ROTCTRL_SELECT_A_V(v)         ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7)
+
+/**
+ * Register: HW_TIMROT_ROTCOUNT
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_TIMROT_ROTCOUNT              (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10))
+#define BP_TIMROT_ROTCOUNT_UPDOWN       0
+#define BM_TIMROT_ROTCOUNT_UPDOWN       0xffff
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_TIMCTRLn
+ * Address: 0x20+n*0x20
+ * SCT: yes
+*/
+#define HW_TIMROT_TIMCTRLn(n)                   (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0))
+#define HW_TIMROT_TIMCTRLn_SET(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4))
+#define HW_TIMROT_TIMCTRLn_CLR(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8))
+#define HW_TIMROT_TIMCTRLn_TOG(n)               (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc))
+#define BP_TIMROT_TIMCTRLn_IRQ                  15
+#define BM_TIMROT_TIMCTRLn_IRQ                  0x8000
+#define BF_TIMROT_TIMCTRLn_IRQ(v)               (((v) << 15) & 0x8000)
+#define BP_TIMROT_TIMCTRLn_IRQ_EN               14
+#define BM_TIMROT_TIMCTRLn_IRQ_EN               0x4000
+#define BF_TIMROT_TIMCTRLn_IRQ_EN(v)            (((v) << 14) & 0x4000)
+#define BP_TIMROT_TIMCTRLn_POLARITY             8
+#define BM_TIMROT_TIMCTRLn_POLARITY             0x100
+#define BF_TIMROT_TIMCTRLn_POLARITY(v)          (((v) << 8) & 0x100)
+#define BP_TIMROT_TIMCTRLn_UPDATE               7
+#define BM_TIMROT_TIMCTRLn_UPDATE               0x80
+#define BF_TIMROT_TIMCTRLn_UPDATE(v)            (((v) << 7) & 0x80)
+#define BP_TIMROT_TIMCTRLn_RELOAD               6
+#define BM_TIMROT_TIMCTRLn_RELOAD               0x40
+#define BF_TIMROT_TIMCTRLn_RELOAD(v)            (((v) << 6) & 0x40)
+#define BP_TIMROT_TIMCTRLn_PRESCALE             4
+#define BM_TIMROT_TIMCTRLn_PRESCALE             0x30
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1   0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2   0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4   0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8   0x3
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v)          (((v) << 4) & 0x30)
+#define BF_TIMROT_TIMCTRLn_PRESCALE_V(v)        ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30)
+#define BP_TIMROT_TIMCTRLn_SELECT               0
+#define BM_TIMROT_TIMCTRLn_SELECT               0xf
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK   0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0         0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1         0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2         0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3         0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4         0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA      0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB      0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL   0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL    0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL    0xa
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL    0xb
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS  0xc
+#define BF_TIMROT_TIMCTRLn_SELECT(v)            (((v) << 0) & 0xf)
+#define BF_TIMROT_TIMCTRLn_SELECT_V(v)          ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_TIMROT_TIMCOUNTn
+ * Address: 0x30+n*0x20
+ * SCT: no
+*/
+#define HW_TIMROT_TIMCOUNTn(n)                  (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20))
+#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT         0
+#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT         0xffff
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v)      (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_TIMCTRL3
+ * Address: 0x80
+ * SCT: yes
+*/
+#define HW_TIMROT_TIMCTRL3                          (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0))
+#define HW_TIMROT_TIMCTRL3_SET                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4))
+#define HW_TIMROT_TIMCTRL3_CLR                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8))
+#define HW_TIMROT_TIMCTRL3_TOG                      (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc))
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL              16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL              0xf0000
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK  0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0        0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1        0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2        0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3        0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4        0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA     0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB     0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL  0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL   0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL   0xa
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL   0xb
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v)           (((v) << 16) & 0xf0000)
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v)         ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000)
+#define BP_TIMROT_TIMCTRL3_IRQ                      15
+#define BM_TIMROT_TIMCTRL3_IRQ                      0x8000
+#define BF_TIMROT_TIMCTRL3_IRQ(v)                   (((v) << 15) & 0x8000)
+#define BP_TIMROT_TIMCTRL3_IRQ_EN                   14
+#define BM_TIMROT_TIMCTRL3_IRQ_EN                   0x4000
+#define BF_TIMROT_TIMCTRL3_IRQ_EN(v)                (((v) << 14) & 0x4000)
+#define BP_TIMROT_TIMCTRL3_DUTY_VALID               10
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID               0x400
+#define BF_TIMROT_TIMCTRL3_DUTY_VALID(v)            (((v) << 10) & 0x400)
+#define BP_TIMROT_TIMCTRL3_DUTY_CYCLE               9
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE               0x200
+#define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v)            (((v) << 9) & 0x200)
+#define BP_TIMROT_TIMCTRL3_POLARITY                 8
+#define BM_TIMROT_TIMCTRL3_POLARITY                 0x100
+#define BF_TIMROT_TIMCTRL3_POLARITY(v)              (((v) << 8) & 0x100)
+#define BP_TIMROT_TIMCTRL3_UPDATE                   7
+#define BM_TIMROT_TIMCTRL3_UPDATE                   0x80
+#define BF_TIMROT_TIMCTRL3_UPDATE(v)                (((v) << 7) & 0x80)
+#define BP_TIMROT_TIMCTRL3_RELOAD                   6
+#define BM_TIMROT_TIMCTRL3_RELOAD                   0x40
+#define BF_TIMROT_TIMCTRL3_RELOAD(v)                (((v) << 6) & 0x40)
+#define BP_TIMROT_TIMCTRL3_PRESCALE                 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE                 0x30
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1       0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2       0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4       0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8       0x3
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v)              (((v) << 4) & 0x30)
+#define BF_TIMROT_TIMCTRL3_PRESCALE_V(v)            ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30)
+#define BP_TIMROT_TIMCTRL3_SELECT                   0
+#define BM_TIMROT_TIMCTRL3_SELECT                   0xf
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK       0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0             0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1             0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2             0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3             0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4             0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA          0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB          0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL       0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL        0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL        0xa
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL        0xb
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS      0xc
+#define BF_TIMROT_TIMCTRL3_SELECT(v)                (((v) << 0) & 0xf)
+#define BF_TIMROT_TIMCTRL3_SELECT_V(v)              ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf)
+
+/**
+ * Register: HW_TIMROT_TIMCOUNT3
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_TIMROT_TIMCOUNT3                         (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90))
+#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       16
+#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT       0xffff0000
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v)    (((v) << 16) & 0xffff0000)
+#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0
+#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT        0xffff
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_TIMROT_VERSION
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_TIMROT_VERSION           (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0xa0))
+#define BP_TIMROT_VERSION_MAJOR     24
+#define BM_TIMROT_VERSION_MAJOR     0xff000000
+#define BF_TIMROT_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
+#define BP_TIMROT_VERSION_MINOR     16
+#define BM_TIMROT_VERSION_MINOR     0xff0000
+#define BF_TIMROT_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
+#define BP_TIMROT_VERSION_STEP      0
+#define BM_TIMROT_VERSION_STEP      0xffff
+#define BF_TIMROT_VERSION_STEP(v)   (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__TIMROT__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h
new file mode 100644
index 0000000000..a346fc1246
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h
@@ -0,0 +1,427 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__UARTAPP__H__
+#define __HEADERGEN__STMP3700__UARTAPP__H__
+
+#define REGS_UARTAPP_BASE(i) ((i) == 1 ? 0x8006c000 : 0x8006e000)
+
+#define REGS_UARTAPP_VERSION "3.2.0"
+
+/**
+ * Register: HW_UARTAPP_CTRL0
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL0(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x0))
+#define HW_UARTAPP_CTRL0_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x4))
+#define HW_UARTAPP_CTRL0_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x8))
+#define HW_UARTAPP_CTRL0_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0xc))
+#define BP_UARTAPP_CTRL0_SFTRST         31
+#define BM_UARTAPP_CTRL0_SFTRST         0x80000000
+#define BF_UARTAPP_CTRL0_SFTRST(v)      (((v) << 31) & 0x80000000)
+#define BP_UARTAPP_CTRL0_CLKGATE        30
+#define BM_UARTAPP_CTRL0_CLKGATE        0x40000000
+#define BF_UARTAPP_CTRL0_CLKGATE(v)     (((v) << 30) & 0x40000000)
+#define BP_UARTAPP_CTRL0_RUN            29
+#define BM_UARTAPP_CTRL0_RUN            0x20000000
+#define BF_UARTAPP_CTRL0_RUN(v)         (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_CTRL0_RX_SOURCE      28
+#define BM_UARTAPP_CTRL0_RX_SOURCE      0x10000000
+#define BF_UARTAPP_CTRL0_RX_SOURCE(v)   (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL0_RXTO_ENABLE    27
+#define BM_UARTAPP_CTRL0_RXTO_ENABLE    0x8000000
+#define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 27) & 0x8000000)
+#define BP_UARTAPP_CTRL0_RXTIMEOUT      16
+#define BM_UARTAPP_CTRL0_RXTIMEOUT      0x7ff0000
+#define BF_UARTAPP_CTRL0_RXTIMEOUT(v)   (((v) << 16) & 0x7ff0000)
+#define BP_UARTAPP_CTRL0_XFER_COUNT     0
+#define BM_UARTAPP_CTRL0_XFER_COUNT     0xffff
+#define BF_UARTAPP_CTRL0_XFER_COUNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL1(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x0))
+#define HW_UARTAPP_CTRL1_SET(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x4))
+#define HW_UARTAPP_CTRL1_CLR(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x8))
+#define HW_UARTAPP_CTRL1_TOG(d)         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0xc))
+#define BP_UARTAPP_CTRL1_RUN            28
+#define BM_UARTAPP_CTRL1_RUN            0x10000000
+#define BF_UARTAPP_CTRL1_RUN(v)         (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL1_XFER_COUNT     0
+#define BM_UARTAPP_CTRL1_XFER_COUNT     0xffff
+#define BF_UARTAPP_CTRL1_XFER_COUNT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_CTRL2
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_UARTAPP_CTRL2(d)                         (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x0))
+#define HW_UARTAPP_CTRL2_SET(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x4))
+#define HW_UARTAPP_CTRL2_CLR(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x8))
+#define HW_UARTAPP_CTRL2_TOG(d)                     (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0xc))
+#define BP_UARTAPP_CTRL2_INVERT_RTS                 31
+#define BM_UARTAPP_CTRL2_INVERT_RTS                 0x80000000
+#define BF_UARTAPP_CTRL2_INVERT_RTS(v)              (((v) << 31) & 0x80000000)
+#define BP_UARTAPP_CTRL2_INVERT_CTS                 30
+#define BM_UARTAPP_CTRL2_INVERT_CTS                 0x40000000
+#define BF_UARTAPP_CTRL2_INVERT_CTS(v)              (((v) << 30) & 0x40000000)
+#define BP_UARTAPP_CTRL2_INVERT_TX                  29
+#define BM_UARTAPP_CTRL2_INVERT_TX                  0x20000000
+#define BF_UARTAPP_CTRL2_INVERT_TX(v)               (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_CTRL2_INVERT_RX                  28
+#define BM_UARTAPP_CTRL2_INVERT_RX                  0x10000000
+#define BF_UARTAPP_CTRL2_INVERT_RX(v)               (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_CTRL2_RTS_SEMAPHORE              27
+#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE              0x8000000
+#define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v)           (((v) << 27) & 0x8000000)
+#define BP_UARTAPP_CTRL2_DMAONERR                   26
+#define BM_UARTAPP_CTRL2_DMAONERR                   0x4000000
+#define BF_UARTAPP_CTRL2_DMAONERR(v)                (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_CTRL2_TXDMAE                     25
+#define BM_UARTAPP_CTRL2_TXDMAE                     0x2000000
+#define BF_UARTAPP_CTRL2_TXDMAE(v)                  (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_CTRL2_RXDMAE                     24
+#define BM_UARTAPP_CTRL2_RXDMAE                     0x1000000
+#define BF_UARTAPP_CTRL2_RXDMAE(v)                  (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_CTRL2_RXIFLSEL                   20
+#define BM_UARTAPP_CTRL2_RXIFLSEL                   0x700000
+#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY        0x0
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_RXIFLSEL(v)                (((v) << 20) & 0x700000)
+#define BF_UARTAPP_CTRL2_RXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000)
+#define BP_UARTAPP_CTRL2_TXIFLSEL                   16
+#define BM_UARTAPP_CTRL2_TXIFLSEL                   0x70000
+#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY            0x0
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER      0x1
+#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF         0x2
+#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS   0x3
+#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS    0x4
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5         0x5
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6         0x6
+#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7         0x7
+#define BF_UARTAPP_CTRL2_TXIFLSEL(v)                (((v) << 16) & 0x70000)
+#define BF_UARTAPP_CTRL2_TXIFLSEL_V(v)              ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000)
+#define BP_UARTAPP_CTRL2_CTSEN                      15
+#define BM_UARTAPP_CTRL2_CTSEN                      0x8000
+#define BF_UARTAPP_CTRL2_CTSEN(v)                   (((v) << 15) & 0x8000)
+#define BP_UARTAPP_CTRL2_RTSEN                      14
+#define BM_UARTAPP_CTRL2_RTSEN                      0x4000
+#define BF_UARTAPP_CTRL2_RTSEN(v)                   (((v) << 14) & 0x4000)
+#define BP_UARTAPP_CTRL2_OUT2                       13
+#define BM_UARTAPP_CTRL2_OUT2                       0x2000
+#define BF_UARTAPP_CTRL2_OUT2(v)                    (((v) << 13) & 0x2000)
+#define BP_UARTAPP_CTRL2_OUT1                       12
+#define BM_UARTAPP_CTRL2_OUT1                       0x1000
+#define BF_UARTAPP_CTRL2_OUT1(v)                    (((v) << 12) & 0x1000)
+#define BP_UARTAPP_CTRL2_RTS                        11
+#define BM_UARTAPP_CTRL2_RTS                        0x800
+#define BF_UARTAPP_CTRL2_RTS(v)                     (((v) << 11) & 0x800)
+#define BP_UARTAPP_CTRL2_DTR                        10
+#define BM_UARTAPP_CTRL2_DTR                        0x400
+#define BF_UARTAPP_CTRL2_DTR(v)                     (((v) << 10) & 0x400)
+#define BP_UARTAPP_CTRL2_RXE                        9
+#define BM_UARTAPP_CTRL2_RXE                        0x200
+#define BF_UARTAPP_CTRL2_RXE(v)                     (((v) << 9) & 0x200)
+#define BP_UARTAPP_CTRL2_TXE                        8
+#define BM_UARTAPP_CTRL2_TXE                        0x100
+#define BF_UARTAPP_CTRL2_TXE(v)                     (((v) << 8) & 0x100)
+#define BP_UARTAPP_CTRL2_LBE                        7
+#define BM_UARTAPP_CTRL2_LBE                        0x80
+#define BF_UARTAPP_CTRL2_LBE(v)                     (((v) << 7) & 0x80)
+#define BP_UARTAPP_CTRL2_USE_LCR2                   6
+#define BM_UARTAPP_CTRL2_USE_LCR2                   0x40
+#define BF_UARTAPP_CTRL2_USE_LCR2(v)                (((v) << 6) & 0x40)
+#define BP_UARTAPP_CTRL2_SIRLP                      2
+#define BM_UARTAPP_CTRL2_SIRLP                      0x4
+#define BF_UARTAPP_CTRL2_SIRLP(v)                   (((v) << 2) & 0x4)
+#define BP_UARTAPP_CTRL2_SIREN                      1
+#define BM_UARTAPP_CTRL2_SIREN                      0x2
+#define BF_UARTAPP_CTRL2_SIREN(v)                   (((v) << 1) & 0x2)
+#define BP_UARTAPP_CTRL2_UARTEN                     0
+#define BM_UARTAPP_CTRL2_UARTEN                     0x1
+#define BF_UARTAPP_CTRL2_UARTEN(v)                  (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_LINECTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_UARTAPP_LINECTRL(d)              (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x0))
+#define HW_UARTAPP_LINECTRL_SET(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x4))
+#define HW_UARTAPP_LINECTRL_CLR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x8))
+#define HW_UARTAPP_LINECTRL_TOG(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0xc))
+#define BP_UARTAPP_LINECTRL_BAUD_DIVINT     16
+#define BM_UARTAPP_LINECTRL_BAUD_DIVINT     0xffff0000
+#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC    8
+#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC    0x3f00
+#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00)
+#define BP_UARTAPP_LINECTRL_SPS             7
+#define BM_UARTAPP_LINECTRL_SPS             0x80
+#define BF_UARTAPP_LINECTRL_SPS(v)          (((v) << 7) & 0x80)
+#define BP_UARTAPP_LINECTRL_WLEN            5
+#define BM_UARTAPP_LINECTRL_WLEN            0x60
+#define BF_UARTAPP_LINECTRL_WLEN(v)         (((v) << 5) & 0x60)
+#define BP_UARTAPP_LINECTRL_FEN             4
+#define BM_UARTAPP_LINECTRL_FEN             0x10
+#define BF_UARTAPP_LINECTRL_FEN(v)          (((v) << 4) & 0x10)
+#define BP_UARTAPP_LINECTRL_STP2            3
+#define BM_UARTAPP_LINECTRL_STP2            0x8
+#define BF_UARTAPP_LINECTRL_STP2(v)         (((v) << 3) & 0x8)
+#define BP_UARTAPP_LINECTRL_EPS             2
+#define BM_UARTAPP_LINECTRL_EPS             0x4
+#define BF_UARTAPP_LINECTRL_EPS(v)          (((v) << 2) & 0x4)
+#define BP_UARTAPP_LINECTRL_PEN             1
+#define BM_UARTAPP_LINECTRL_PEN             0x2
+#define BF_UARTAPP_LINECTRL_PEN(v)          (((v) << 1) & 0x2)
+#define BP_UARTAPP_LINECTRL_BRK             0
+#define BM_UARTAPP_LINECTRL_BRK             0x1
+#define BF_UARTAPP_LINECTRL_BRK(v)          (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_LINECTRL2
+ * Address: 0x40
+ * SCT: yes
+*/
+#define HW_UARTAPP_LINECTRL2(d)                 (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x0))
+#define HW_UARTAPP_LINECTRL2_SET(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x4))
+#define HW_UARTAPP_LINECTRL2_CLR(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x8))
+#define HW_UARTAPP_LINECTRL2_TOG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0xc))
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT        16
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT        0xffff0000
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v)     (((v) << 16) & 0xffff0000)
+#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC       8
+#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC       0x3f00
+#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v)    (((v) << 8) & 0x3f00)
+#define BP_UARTAPP_LINECTRL2_SPS                7
+#define BM_UARTAPP_LINECTRL2_SPS                0x80
+#define BF_UARTAPP_LINECTRL2_SPS(v)             (((v) << 7) & 0x80)
+#define BP_UARTAPP_LINECTRL2_WLEN               5
+#define BM_UARTAPP_LINECTRL2_WLEN               0x60
+#define BF_UARTAPP_LINECTRL2_WLEN(v)            (((v) << 5) & 0x60)
+#define BP_UARTAPP_LINECTRL2_FEN                4
+#define BM_UARTAPP_LINECTRL2_FEN                0x10
+#define BF_UARTAPP_LINECTRL2_FEN(v)             (((v) << 4) & 0x10)
+#define BP_UARTAPP_LINECTRL2_STP2               3
+#define BM_UARTAPP_LINECTRL2_STP2               0x8
+#define BF_UARTAPP_LINECTRL2_STP2(v)            (((v) << 3) & 0x8)
+#define BP_UARTAPP_LINECTRL2_EPS                2
+#define BM_UARTAPP_LINECTRL2_EPS                0x4
+#define BF_UARTAPP_LINECTRL2_EPS(v)             (((v) << 2) & 0x4)
+#define BP_UARTAPP_LINECTRL2_PEN                1
+#define BM_UARTAPP_LINECTRL2_PEN                0x2
+#define BF_UARTAPP_LINECTRL2_PEN(v)             (((v) << 1) & 0x2)
+
+/**
+ * Register: HW_UARTAPP_INTR
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_UARTAPP_INTR(d)          (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x0))
+#define HW_UARTAPP_INTR_SET(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x4))
+#define HW_UARTAPP_INTR_CLR(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x8))
+#define HW_UARTAPP_INTR_TOG(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0xc))
+#define BP_UARTAPP_INTR_OEIEN       26
+#define BM_UARTAPP_INTR_OEIEN       0x4000000
+#define BF_UARTAPP_INTR_OEIEN(v)    (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_INTR_BEIEN       25
+#define BM_UARTAPP_INTR_BEIEN       0x2000000
+#define BF_UARTAPP_INTR_BEIEN(v)    (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_INTR_PEIEN       24
+#define BM_UARTAPP_INTR_PEIEN       0x1000000
+#define BF_UARTAPP_INTR_PEIEN(v)    (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_INTR_FEIEN       23
+#define BM_UARTAPP_INTR_FEIEN       0x800000
+#define BF_UARTAPP_INTR_FEIEN(v)    (((v) << 23) & 0x800000)
+#define BP_UARTAPP_INTR_RTIEN       22
+#define BM_UARTAPP_INTR_RTIEN       0x400000
+#define BF_UARTAPP_INTR_RTIEN(v)    (((v) << 22) & 0x400000)
+#define BP_UARTAPP_INTR_TXIEN       21
+#define BM_UARTAPP_INTR_TXIEN       0x200000
+#define BF_UARTAPP_INTR_TXIEN(v)    (((v) << 21) & 0x200000)
+#define BP_UARTAPP_INTR_RXIEN       20
+#define BM_UARTAPP_INTR_RXIEN       0x100000
+#define BF_UARTAPP_INTR_RXIEN(v)    (((v) << 20) & 0x100000)
+#define BP_UARTAPP_INTR_DSRMIEN     19
+#define BM_UARTAPP_INTR_DSRMIEN     0x80000
+#define BF_UARTAPP_INTR_DSRMIEN(v)  (((v) << 19) & 0x80000)
+#define BP_UARTAPP_INTR_DCDMIEN     18
+#define BM_UARTAPP_INTR_DCDMIEN     0x40000
+#define BF_UARTAPP_INTR_DCDMIEN(v)  (((v) << 18) & 0x40000)
+#define BP_UARTAPP_INTR_CTSMIEN     17
+#define BM_UARTAPP_INTR_CTSMIEN     0x20000
+#define BF_UARTAPP_INTR_CTSMIEN(v)  (((v) << 17) & 0x20000)
+#define BP_UARTAPP_INTR_RIMIEN      16
+#define BM_UARTAPP_INTR_RIMIEN      0x10000
+#define BF_UARTAPP_INTR_RIMIEN(v)   (((v) << 16) & 0x10000)
+#define BP_UARTAPP_INTR_OEIS        10
+#define BM_UARTAPP_INTR_OEIS        0x400
+#define BF_UARTAPP_INTR_OEIS(v)     (((v) << 10) & 0x400)
+#define BP_UARTAPP_INTR_BEIS        9
+#define BM_UARTAPP_INTR_BEIS        0x200
+#define BF_UARTAPP_INTR_BEIS(v)     (((v) << 9) & 0x200)
+#define BP_UARTAPP_INTR_PEIS        8
+#define BM_UARTAPP_INTR_PEIS        0x100
+#define BF_UARTAPP_INTR_PEIS(v)     (((v) << 8) & 0x100)
+#define BP_UARTAPP_INTR_FEIS        7
+#define BM_UARTAPP_INTR_FEIS        0x80
+#define BF_UARTAPP_INTR_FEIS(v)     (((v) << 7) & 0x80)
+#define BP_UARTAPP_INTR_RTIS        6
+#define BM_UARTAPP_INTR_RTIS        0x40
+#define BF_UARTAPP_INTR_RTIS(v)     (((v) << 6) & 0x40)
+#define BP_UARTAPP_INTR_TXIS        5
+#define BM_UARTAPP_INTR_TXIS        0x20
+#define BF_UARTAPP_INTR_TXIS(v)     (((v) << 5) & 0x20)
+#define BP_UARTAPP_INTR_RXIS        4
+#define BM_UARTAPP_INTR_RXIS        0x10
+#define BF_UARTAPP_INTR_RXIS(v)     (((v) << 4) & 0x10)
+#define BP_UARTAPP_INTR_DSRMIS      3
+#define BM_UARTAPP_INTR_DSRMIS      0x8
+#define BF_UARTAPP_INTR_DSRMIS(v)   (((v) << 3) & 0x8)
+#define BP_UARTAPP_INTR_DCDMIS      2
+#define BM_UARTAPP_INTR_DCDMIS      0x4
+#define BF_UARTAPP_INTR_DCDMIS(v)   (((v) << 2) & 0x4)
+#define BP_UARTAPP_INTR_CTSMIS      1
+#define BM_UARTAPP_INTR_CTSMIS      0x2
+#define BF_UARTAPP_INTR_CTSMIS(v)   (((v) << 1) & 0x2)
+#define BP_UARTAPP_INTR_RIMIS       0
+#define BM_UARTAPP_INTR_RIMIS       0x1
+#define BF_UARTAPP_INTR_RIMIS(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_DATA
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_UARTAPP_DATA(d)      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x60))
+#define BP_UARTAPP_DATA_DATA    0
+#define BM_UARTAPP_DATA_DATA    0xffffffff
+#define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_UARTAPP_STAT
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_UARTAPP_STAT(d)                      (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x70))
+#define BP_UARTAPP_STAT_PRESENT                 31
+#define BM_UARTAPP_STAT_PRESENT                 0x80000000
+#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_PRESENT__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_PRESENT(v)              (((v) << 31) & 0x80000000)
+#define BF_UARTAPP_STAT_PRESENT_V(v)            ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000)
+#define BP_UARTAPP_STAT_HISPEED                 30
+#define BM_UARTAPP_STAT_HISPEED                 0x40000000
+#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE    0x0
+#define BV_UARTAPP_STAT_HISPEED__AVAILABLE      0x1
+#define BF_UARTAPP_STAT_HISPEED(v)              (((v) << 30) & 0x40000000)
+#define BF_UARTAPP_STAT_HISPEED_V(v)            ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000)
+#define BP_UARTAPP_STAT_BUSY                    29
+#define BM_UARTAPP_STAT_BUSY                    0x20000000
+#define BF_UARTAPP_STAT_BUSY(v)                 (((v) << 29) & 0x20000000)
+#define BP_UARTAPP_STAT_CTS                     28
+#define BM_UARTAPP_STAT_CTS                     0x10000000
+#define BF_UARTAPP_STAT_CTS(v)                  (((v) << 28) & 0x10000000)
+#define BP_UARTAPP_STAT_TXFE                    27
+#define BM_UARTAPP_STAT_TXFE                    0x8000000
+#define BF_UARTAPP_STAT_TXFE(v)                 (((v) << 27) & 0x8000000)
+#define BP_UARTAPP_STAT_RXFF                    26
+#define BM_UARTAPP_STAT_RXFF                    0x4000000
+#define BF_UARTAPP_STAT_RXFF(v)                 (((v) << 26) & 0x4000000)
+#define BP_UARTAPP_STAT_TXFF                    25
+#define BM_UARTAPP_STAT_TXFF                    0x2000000
+#define BF_UARTAPP_STAT_TXFF(v)                 (((v) << 25) & 0x2000000)
+#define BP_UARTAPP_STAT_RXFE                    24
+#define BM_UARTAPP_STAT_RXFE                    0x1000000
+#define BF_UARTAPP_STAT_RXFE(v)                 (((v) << 24) & 0x1000000)
+#define BP_UARTAPP_STAT_RXBYTE_INVALID          20
+#define BM_UARTAPP_STAT_RXBYTE_INVALID          0xf00000
+#define BF_UARTAPP_STAT_RXBYTE_INVALID(v)       (((v) << 20) & 0xf00000)
+#define BP_UARTAPP_STAT_OERR                    19
+#define BM_UARTAPP_STAT_OERR                    0x80000
+#define BF_UARTAPP_STAT_OERR(v)                 (((v) << 19) & 0x80000)
+#define BP_UARTAPP_STAT_BERR                    18
+#define BM_UARTAPP_STAT_BERR                    0x40000
+#define BF_UARTAPP_STAT_BERR(v)                 (((v) << 18) & 0x40000)
+#define BP_UARTAPP_STAT_PERR                    17
+#define BM_UARTAPP_STAT_PERR                    0x20000
+#define BF_UARTAPP_STAT_PERR(v)                 (((v) << 17) & 0x20000)
+#define BP_UARTAPP_STAT_FERR                    16
+#define BM_UARTAPP_STAT_FERR                    0x10000
+#define BF_UARTAPP_STAT_FERR(v)                 (((v) << 16) & 0x10000)
+#define BP_UARTAPP_STAT_RXCOUNT                 0
+#define BM_UARTAPP_STAT_RXCOUNT                 0xffff
+#define BF_UARTAPP_STAT_RXCOUNT(v)              (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTAPP_DEBUG
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_UARTAPP_DEBUG(d)             (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x80))
+#define BP_UARTAPP_DEBUG_TXDMARUN       5
+#define BM_UARTAPP_DEBUG_TXDMARUN       0x20
+#define BF_UARTAPP_DEBUG_TXDMARUN(v)    (((v) << 5) & 0x20)
+#define BP_UARTAPP_DEBUG_RXDMARUN       4
+#define BM_UARTAPP_DEBUG_RXDMARUN       0x10
+#define BF_UARTAPP_DEBUG_RXDMARUN(v)    (((v) << 4) & 0x10)
+#define BP_UARTAPP_DEBUG_TXCMDEND       3
+#define BM_UARTAPP_DEBUG_TXCMDEND       0x8
+#define BF_UARTAPP_DEBUG_TXCMDEND(v)    (((v) << 3) & 0x8)
+#define BP_UARTAPP_DEBUG_RXCMDEND       2
+#define BM_UARTAPP_DEBUG_RXCMDEND       0x4
+#define BF_UARTAPP_DEBUG_RXCMDEND(v)    (((v) << 2) & 0x4)
+#define BP_UARTAPP_DEBUG_TXDMARQ        1
+#define BM_UARTAPP_DEBUG_TXDMARQ        0x2
+#define BF_UARTAPP_DEBUG_TXDMARQ(v)     (((v) << 1) & 0x2)
+#define BP_UARTAPP_DEBUG_RXDMARQ        0
+#define BM_UARTAPP_DEBUG_RXDMARQ        0x1
+#define BF_UARTAPP_DEBUG_RXDMARQ(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTAPP_VERSION
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_UARTAPP_VERSION(d)       (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x90))
+#define BP_UARTAPP_VERSION_MAJOR    24
+#define BM_UARTAPP_VERSION_MAJOR    0xff000000
+#define BF_UARTAPP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
+#define BP_UARTAPP_VERSION_MINOR    16
+#define BM_UARTAPP_VERSION_MINOR    0xff0000
+#define BF_UARTAPP_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
+#define BP_UARTAPP_VERSION_STEP     0
+#define BM_UARTAPP_VERSION_STEP     0xffff
+#define BF_UARTAPP_VERSION_STEP(v)  (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__UARTAPP__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h
new file mode 100644
index 0000000000..d1ef6f2608
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h
@@ -0,0 +1,491 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__UARTDBG__H__
+#define __HEADERGEN__STMP3700__UARTDBG__H__
+
+#define REGS_UARTDBG_BASE (0x80070000)
+
+#define REGS_UARTDBG_VERSION "3.2.0"
+
+/**
+ * Register: HW_UARTDBG_DR
+ * Address: 0
+ * SCT: no
+*/
+#define HW_UARTDBG_DR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0))
+#define BP_UARTDBG_DR_UNAVAILABLE       16
+#define BM_UARTDBG_DR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_DR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_DR_RESERVED          12
+#define BM_UARTDBG_DR_RESERVED          0xf000
+#define BF_UARTDBG_DR_RESERVED(v)       (((v) << 12) & 0xf000)
+#define BP_UARTDBG_DR_OE                11
+#define BM_UARTDBG_DR_OE                0x800
+#define BF_UARTDBG_DR_OE(v)             (((v) << 11) & 0x800)
+#define BP_UARTDBG_DR_BE                10
+#define BM_UARTDBG_DR_BE                0x400
+#define BF_UARTDBG_DR_BE(v)             (((v) << 10) & 0x400)
+#define BP_UARTDBG_DR_PE                9
+#define BM_UARTDBG_DR_PE                0x200
+#define BF_UARTDBG_DR_PE(v)             (((v) << 9) & 0x200)
+#define BP_UARTDBG_DR_FE                8
+#define BM_UARTDBG_DR_FE                0x100
+#define BF_UARTDBG_DR_FE(v)             (((v) << 8) & 0x100)
+#define BP_UARTDBG_DR_DATA              0
+#define BM_UARTDBG_DR_DATA              0xff
+#define BF_UARTDBG_DR_DATA(v)           (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_UARTDBG_RSR_ECR
+ * Address: 0x4
+ * SCT: no
+*/
+#define HW_UARTDBG_RSR_ECR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4))
+#define BP_UARTDBG_RSR_ECR_UNAVAILABLE      8
+#define BM_UARTDBG_RSR_ECR_UNAVAILABLE      0xffffff00
+#define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v)   (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_RSR_ECR_EC               4
+#define BM_UARTDBG_RSR_ECR_EC               0xf0
+#define BF_UARTDBG_RSR_ECR_EC(v)            (((v) << 4) & 0xf0)
+#define BP_UARTDBG_RSR_ECR_OE               3
+#define BM_UARTDBG_RSR_ECR_OE               0x8
+#define BF_UARTDBG_RSR_ECR_OE(v)            (((v) << 3) & 0x8)
+#define BP_UARTDBG_RSR_ECR_BE               2
+#define BM_UARTDBG_RSR_ECR_BE               0x4
+#define BF_UARTDBG_RSR_ECR_BE(v)            (((v) << 2) & 0x4)
+#define BP_UARTDBG_RSR_ECR_PE               1
+#define BM_UARTDBG_RSR_ECR_PE               0x2
+#define BF_UARTDBG_RSR_ECR_PE(v)            (((v) << 1) & 0x2)
+#define BP_UARTDBG_RSR_ECR_FE               0
+#define BM_UARTDBG_RSR_ECR_FE               0x1
+#define BF_UARTDBG_RSR_ECR_FE(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_FR
+ * Address: 0x18
+ * SCT: no
+*/
+#define HW_UARTDBG_FR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18))
+#define BP_UARTDBG_FR_UNAVAILABLE       16
+#define BM_UARTDBG_FR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_FR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_FR_RESERVED          9
+#define BM_UARTDBG_FR_RESERVED          0xfe00
+#define BF_UARTDBG_FR_RESERVED(v)       (((v) << 9) & 0xfe00)
+#define BP_UARTDBG_FR_RI                8
+#define BM_UARTDBG_FR_RI                0x100
+#define BF_UARTDBG_FR_RI(v)             (((v) << 8) & 0x100)
+#define BP_UARTDBG_FR_TXFE              7
+#define BM_UARTDBG_FR_TXFE              0x80
+#define BF_UARTDBG_FR_TXFE(v)           (((v) << 7) & 0x80)
+#define BP_UARTDBG_FR_RXFF              6
+#define BM_UARTDBG_FR_RXFF              0x40
+#define BF_UARTDBG_FR_RXFF(v)           (((v) << 6) & 0x40)
+#define BP_UARTDBG_FR_TXFF              5
+#define BM_UARTDBG_FR_TXFF              0x20
+#define BF_UARTDBG_FR_TXFF(v)           (((v) << 5) & 0x20)
+#define BP_UARTDBG_FR_RXFE              4
+#define BM_UARTDBG_FR_RXFE              0x10
+#define BF_UARTDBG_FR_RXFE(v)           (((v) << 4) & 0x10)
+#define BP_UARTDBG_FR_BUSY              3
+#define BM_UARTDBG_FR_BUSY              0x8
+#define BF_UARTDBG_FR_BUSY(v)           (((v) << 3) & 0x8)
+#define BP_UARTDBG_FR_DCD               2
+#define BM_UARTDBG_FR_DCD               0x4
+#define BF_UARTDBG_FR_DCD(v)            (((v) << 2) & 0x4)
+#define BP_UARTDBG_FR_DSR               1
+#define BM_UARTDBG_FR_DSR               0x2
+#define BF_UARTDBG_FR_DSR(v)            (((v) << 1) & 0x2)
+#define BP_UARTDBG_FR_CTS               0
+#define BM_UARTDBG_FR_CTS               0x1
+#define BF_UARTDBG_FR_CTS(v)            (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_ILPR
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_UARTDBG_ILPR                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20))
+#define BP_UARTDBG_ILPR_UNAVAILABLE     8
+#define BM_UARTDBG_ILPR_UNAVAILABLE     0xffffff00
+#define BF_UARTDBG_ILPR_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_ILPR_ILPDVSR         0
+#define BM_UARTDBG_ILPR_ILPDVSR         0xff
+#define BF_UARTDBG_ILPR_ILPDVSR(v)      (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_UARTDBG_IBRD
+ * Address: 0x24
+ * SCT: no
+*/
+#define HW_UARTDBG_IBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24))
+#define BP_UARTDBG_IBRD_UNAVAILABLE     16
+#define BM_UARTDBG_IBRD_UNAVAILABLE     0xffff0000
+#define BF_UARTDBG_IBRD_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IBRD_BAUD_DIVINT     0
+#define BM_UARTDBG_IBRD_BAUD_DIVINT     0xffff
+#define BF_UARTDBG_IBRD_BAUD_DIVINT(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_UARTDBG_FBRD
+ * Address: 0x28
+ * SCT: no
+*/
+#define HW_UARTDBG_FBRD                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28))
+#define BP_UARTDBG_FBRD_UNAVAILABLE     8
+#define BM_UARTDBG_FBRD_UNAVAILABLE     0xffffff00
+#define BF_UARTDBG_FBRD_UNAVAILABLE(v)  (((v) << 8) & 0xffffff00)
+#define BP_UARTDBG_FBRD_RESERVED        6
+#define BM_UARTDBG_FBRD_RESERVED        0xc0
+#define BF_UARTDBG_FBRD_RESERVED(v)     (((v) << 6) & 0xc0)
+#define BP_UARTDBG_FBRD_BAUD_DIVFRAC    0
+#define BM_UARTDBG_FBRD_BAUD_DIVFRAC    0x3f
+#define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f)
+
+/**
+ * Register: HW_UARTDBG_LCR_H
+ * Address: 0x2c
+ * SCT: no
+*/
+#define HW_UARTDBG_LCR_H                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c))
+#define BP_UARTDBG_LCR_H_UNAVAILABLE    16
+#define BM_UARTDBG_LCR_H_UNAVAILABLE    0xffff0000
+#define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_LCR_H_RESERVED       8
+#define BM_UARTDBG_LCR_H_RESERVED       0xff00
+#define BF_UARTDBG_LCR_H_RESERVED(v)    (((v) << 8) & 0xff00)
+#define BP_UARTDBG_LCR_H_SPS            7
+#define BM_UARTDBG_LCR_H_SPS            0x80
+#define BF_UARTDBG_LCR_H_SPS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_LCR_H_WLEN           5
+#define BM_UARTDBG_LCR_H_WLEN           0x60
+#define BF_UARTDBG_LCR_H_WLEN(v)        (((v) << 5) & 0x60)
+#define BP_UARTDBG_LCR_H_FEN            4
+#define BM_UARTDBG_LCR_H_FEN            0x10
+#define BF_UARTDBG_LCR_H_FEN(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_LCR_H_STP2           3
+#define BM_UARTDBG_LCR_H_STP2           0x8
+#define BF_UARTDBG_LCR_H_STP2(v)        (((v) << 3) & 0x8)
+#define BP_UARTDBG_LCR_H_EPS            2
+#define BM_UARTDBG_LCR_H_EPS            0x4
+#define BF_UARTDBG_LCR_H_EPS(v)         (((v) << 2) & 0x4)
+#define BP_UARTDBG_LCR_H_PEN            1
+#define BM_UARTDBG_LCR_H_PEN            0x2
+#define BF_UARTDBG_LCR_H_PEN(v)         (((v) << 1) & 0x2)
+#define BP_UARTDBG_LCR_H_BRK            0
+#define BM_UARTDBG_LCR_H_BRK            0x1
+#define BF_UARTDBG_LCR_H_BRK(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_CR
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_UARTDBG_CR                   (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30))
+#define BP_UARTDBG_CR_UNAVAILABLE       16
+#define BM_UARTDBG_CR_UNAVAILABLE       0xffff0000
+#define BF_UARTDBG_CR_UNAVAILABLE(v)    (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_CR_CTSEN             15
+#define BM_UARTDBG_CR_CTSEN             0x8000
+#define BF_UARTDBG_CR_CTSEN(v)          (((v) << 15) & 0x8000)
+#define BP_UARTDBG_CR_RTSEN             14
+#define BM_UARTDBG_CR_RTSEN             0x4000
+#define BF_UARTDBG_CR_RTSEN(v)          (((v) << 14) & 0x4000)
+#define BP_UARTDBG_CR_OUT2              13
+#define BM_UARTDBG_CR_OUT2              0x2000
+#define BF_UARTDBG_CR_OUT2(v)           (((v) << 13) & 0x2000)
+#define BP_UARTDBG_CR_OUT1              12
+#define BM_UARTDBG_CR_OUT1              0x1000
+#define BF_UARTDBG_CR_OUT1(v)           (((v) << 12) & 0x1000)
+#define BP_UARTDBG_CR_RTS               11
+#define BM_UARTDBG_CR_RTS               0x800
+#define BF_UARTDBG_CR_RTS(v)            (((v) << 11) & 0x800)
+#define BP_UARTDBG_CR_DTR               10
+#define BM_UARTDBG_CR_DTR               0x400
+#define BF_UARTDBG_CR_DTR(v)            (((v) << 10) & 0x400)
+#define BP_UARTDBG_CR_RXE               9
+#define BM_UARTDBG_CR_RXE               0x200
+#define BF_UARTDBG_CR_RXE(v)            (((v) << 9) & 0x200)
+#define BP_UARTDBG_CR_TXE               8
+#define BM_UARTDBG_CR_TXE               0x100
+#define BF_UARTDBG_CR_TXE(v)            (((v) << 8) & 0x100)
+#define BP_UARTDBG_CR_LBE               7
+#define BM_UARTDBG_CR_LBE               0x80
+#define BF_UARTDBG_CR_LBE(v)            (((v) << 7) & 0x80)
+#define BP_UARTDBG_CR_RESERVED          3
+#define BM_UARTDBG_CR_RESERVED          0x78
+#define BF_UARTDBG_CR_RESERVED(v)       (((v) << 3) & 0x78)
+#define BP_UARTDBG_CR_SIRLP             2
+#define BM_UARTDBG_CR_SIRLP             0x4
+#define BF_UARTDBG_CR_SIRLP(v)          (((v) << 2) & 0x4)
+#define BP_UARTDBG_CR_SIREN             1
+#define BM_UARTDBG_CR_SIREN             0x2
+#define BF_UARTDBG_CR_SIREN(v)          (((v) << 1) & 0x2)
+#define BP_UARTDBG_CR_UARTEN            0
+#define BM_UARTDBG_CR_UARTEN            0x1
+#define BF_UARTDBG_CR_UARTEN(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_IFLS
+ * Address: 0x34
+ * SCT: no
+*/
+#define HW_UARTDBG_IFLS                             (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34))
+#define BP_UARTDBG_IFLS_UNAVAILABLE                 16
+#define BM_UARTDBG_IFLS_UNAVAILABLE                 0xffff0000
+#define BF_UARTDBG_IFLS_UNAVAILABLE(v)              (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IFLS_RESERVED                    6
+#define BM_UARTDBG_IFLS_RESERVED                    0xffc0
+#define BF_UARTDBG_IFLS_RESERVED(v)                 (((v) << 6) & 0xffc0)
+#define BP_UARTDBG_IFLS_RXIFLSEL                    3
+#define BM_UARTDBG_IFLS_RXIFLSEL                    0x38
+#define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY         0x0
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_RXIFLSEL(v)                 (((v) << 3) & 0x38)
+#define BF_UARTDBG_IFLS_RXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38)
+#define BP_UARTDBG_IFLS_TXIFLSEL                    0
+#define BM_UARTDBG_IFLS_TXIFLSEL                    0x7
+#define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY             0x0
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER       0x1
+#define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF          0x2
+#define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS    0x3
+#define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS     0x4
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5          0x5
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6          0x6
+#define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7          0x7
+#define BF_UARTDBG_IFLS_TXIFLSEL(v)                 (((v) << 0) & 0x7)
+#define BF_UARTDBG_IFLS_TXIFLSEL_V(v)               ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7)
+
+/**
+ * Register: HW_UARTDBG_IMSC
+ * Address: 0x38
+ * SCT: no
+*/
+#define HW_UARTDBG_IMSC                 (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38))
+#define BP_UARTDBG_IMSC_UNAVAILABLE     16
+#define BM_UARTDBG_IMSC_UNAVAILABLE     0xffff0000
+#define BF_UARTDBG_IMSC_UNAVAILABLE(v)  (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_IMSC_RESERVED        11
+#define BM_UARTDBG_IMSC_RESERVED        0xf800
+#define BF_UARTDBG_IMSC_RESERVED(v)     (((v) << 11) & 0xf800)
+#define BP_UARTDBG_IMSC_OEIM            10
+#define BM_UARTDBG_IMSC_OEIM            0x400
+#define BF_UARTDBG_IMSC_OEIM(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_IMSC_BEIM            9
+#define BM_UARTDBG_IMSC_BEIM            0x200
+#define BF_UARTDBG_IMSC_BEIM(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_IMSC_PEIM            8
+#define BM_UARTDBG_IMSC_PEIM            0x100
+#define BF_UARTDBG_IMSC_PEIM(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_IMSC_FEIM            7
+#define BM_UARTDBG_IMSC_FEIM            0x80
+#define BF_UARTDBG_IMSC_FEIM(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_IMSC_RTIM            6
+#define BM_UARTDBG_IMSC_RTIM            0x40
+#define BF_UARTDBG_IMSC_RTIM(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_IMSC_TXIM            5
+#define BM_UARTDBG_IMSC_TXIM            0x20
+#define BF_UARTDBG_IMSC_TXIM(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_IMSC_RXIM            4
+#define BM_UARTDBG_IMSC_RXIM            0x10
+#define BF_UARTDBG_IMSC_RXIM(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_IMSC_DSRMIM          3
+#define BM_UARTDBG_IMSC_DSRMIM          0x8
+#define BF_UARTDBG_IMSC_DSRMIM(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_IMSC_DCDMIM          2
+#define BM_UARTDBG_IMSC_DCDMIM          0x4
+#define BF_UARTDBG_IMSC_DCDMIM(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_IMSC_CTSMIM          1
+#define BM_UARTDBG_IMSC_CTSMIM          0x2
+#define BF_UARTDBG_IMSC_CTSMIM(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_IMSC_RIMIM           0
+#define BM_UARTDBG_IMSC_RIMIM           0x1
+#define BF_UARTDBG_IMSC_RIMIM(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_RIS
+ * Address: 0x3c
+ * SCT: no
+*/
+#define HW_UARTDBG_RIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c))
+#define BP_UARTDBG_RIS_UNAVAILABLE      16
+#define BM_UARTDBG_RIS_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_RIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_RIS_RESERVED         11
+#define BM_UARTDBG_RIS_RESERVED         0xf800
+#define BF_UARTDBG_RIS_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_RIS_OERIS            10
+#define BM_UARTDBG_RIS_OERIS            0x400
+#define BF_UARTDBG_RIS_OERIS(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_RIS_BERIS            9
+#define BM_UARTDBG_RIS_BERIS            0x200
+#define BF_UARTDBG_RIS_BERIS(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_RIS_PERIS            8
+#define BM_UARTDBG_RIS_PERIS            0x100
+#define BF_UARTDBG_RIS_PERIS(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_RIS_FERIS            7
+#define BM_UARTDBG_RIS_FERIS            0x80
+#define BF_UARTDBG_RIS_FERIS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_RIS_RTRIS            6
+#define BM_UARTDBG_RIS_RTRIS            0x40
+#define BF_UARTDBG_RIS_RTRIS(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_RIS_TXRIS            5
+#define BM_UARTDBG_RIS_TXRIS            0x20
+#define BF_UARTDBG_RIS_TXRIS(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_RIS_RXRIS            4
+#define BM_UARTDBG_RIS_RXRIS            0x10
+#define BF_UARTDBG_RIS_RXRIS(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_RIS_DSRRMIS          3
+#define BM_UARTDBG_RIS_DSRRMIS          0x8
+#define BF_UARTDBG_RIS_DSRRMIS(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_RIS_DCDRMIS          2
+#define BM_UARTDBG_RIS_DCDRMIS          0x4
+#define BF_UARTDBG_RIS_DCDRMIS(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_RIS_CTSRMIS          1
+#define BM_UARTDBG_RIS_CTSRMIS          0x2
+#define BF_UARTDBG_RIS_CTSRMIS(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_RIS_RIRMIS           0
+#define BM_UARTDBG_RIS_RIRMIS           0x1
+#define BF_UARTDBG_RIS_RIRMIS(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_MIS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_UARTDBG_MIS                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40))
+#define BP_UARTDBG_MIS_UNAVAILABLE      16
+#define BM_UARTDBG_MIS_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_MIS_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_MIS_RESERVED         11
+#define BM_UARTDBG_MIS_RESERVED         0xf800
+#define BF_UARTDBG_MIS_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_MIS_OEMIS            10
+#define BM_UARTDBG_MIS_OEMIS            0x400
+#define BF_UARTDBG_MIS_OEMIS(v)         (((v) << 10) & 0x400)
+#define BP_UARTDBG_MIS_BEMIS            9
+#define BM_UARTDBG_MIS_BEMIS            0x200
+#define BF_UARTDBG_MIS_BEMIS(v)         (((v) << 9) & 0x200)
+#define BP_UARTDBG_MIS_PEMIS            8
+#define BM_UARTDBG_MIS_PEMIS            0x100
+#define BF_UARTDBG_MIS_PEMIS(v)         (((v) << 8) & 0x100)
+#define BP_UARTDBG_MIS_FEMIS            7
+#define BM_UARTDBG_MIS_FEMIS            0x80
+#define BF_UARTDBG_MIS_FEMIS(v)         (((v) << 7) & 0x80)
+#define BP_UARTDBG_MIS_RTMIS            6
+#define BM_UARTDBG_MIS_RTMIS            0x40
+#define BF_UARTDBG_MIS_RTMIS(v)         (((v) << 6) & 0x40)
+#define BP_UARTDBG_MIS_TXMIS            5
+#define BM_UARTDBG_MIS_TXMIS            0x20
+#define BF_UARTDBG_MIS_TXMIS(v)         (((v) << 5) & 0x20)
+#define BP_UARTDBG_MIS_RXMIS            4
+#define BM_UARTDBG_MIS_RXMIS            0x10
+#define BF_UARTDBG_MIS_RXMIS(v)         (((v) << 4) & 0x10)
+#define BP_UARTDBG_MIS_DSRMMIS          3
+#define BM_UARTDBG_MIS_DSRMMIS          0x8
+#define BF_UARTDBG_MIS_DSRMMIS(v)       (((v) << 3) & 0x8)
+#define BP_UARTDBG_MIS_DCDMMIS          2
+#define BM_UARTDBG_MIS_DCDMMIS          0x4
+#define BF_UARTDBG_MIS_DCDMMIS(v)       (((v) << 2) & 0x4)
+#define BP_UARTDBG_MIS_CTSMMIS          1
+#define BM_UARTDBG_MIS_CTSMMIS          0x2
+#define BF_UARTDBG_MIS_CTSMMIS(v)       (((v) << 1) & 0x2)
+#define BP_UARTDBG_MIS_RIMMIS           0
+#define BM_UARTDBG_MIS_RIMMIS           0x1
+#define BF_UARTDBG_MIS_RIMMIS(v)        (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_ICR
+ * Address: 0x44
+ * SCT: no
+*/
+#define HW_UARTDBG_ICR                  (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44))
+#define BP_UARTDBG_ICR_UNAVAILABLE      16
+#define BM_UARTDBG_ICR_UNAVAILABLE      0xffff0000
+#define BF_UARTDBG_ICR_UNAVAILABLE(v)   (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_ICR_RESERVED         11
+#define BM_UARTDBG_ICR_RESERVED         0xf800
+#define BF_UARTDBG_ICR_RESERVED(v)      (((v) << 11) & 0xf800)
+#define BP_UARTDBG_ICR_OEIC             10
+#define BM_UARTDBG_ICR_OEIC             0x400
+#define BF_UARTDBG_ICR_OEIC(v)          (((v) << 10) & 0x400)
+#define BP_UARTDBG_ICR_BEIC             9
+#define BM_UARTDBG_ICR_BEIC             0x200
+#define BF_UARTDBG_ICR_BEIC(v)          (((v) << 9) & 0x200)
+#define BP_UARTDBG_ICR_PEIC             8
+#define BM_UARTDBG_ICR_PEIC             0x100
+#define BF_UARTDBG_ICR_PEIC(v)          (((v) << 8) & 0x100)
+#define BP_UARTDBG_ICR_FEIC             7
+#define BM_UARTDBG_ICR_FEIC             0x80
+#define BF_UARTDBG_ICR_FEIC(v)          (((v) << 7) & 0x80)
+#define BP_UARTDBG_ICR_RTIC             6
+#define BM_UARTDBG_ICR_RTIC             0x40
+#define BF_UARTDBG_ICR_RTIC(v)          (((v) << 6) & 0x40)
+#define BP_UARTDBG_ICR_TXIC             5
+#define BM_UARTDBG_ICR_TXIC             0x20
+#define BF_UARTDBG_ICR_TXIC(v)          (((v) << 5) & 0x20)
+#define BP_UARTDBG_ICR_RXIC             4
+#define BM_UARTDBG_ICR_RXIC             0x10
+#define BF_UARTDBG_ICR_RXIC(v)          (((v) << 4) & 0x10)
+#define BP_UARTDBG_ICR_DSRMIC           3
+#define BM_UARTDBG_ICR_DSRMIC           0x8
+#define BF_UARTDBG_ICR_DSRMIC(v)        (((v) << 3) & 0x8)
+#define BP_UARTDBG_ICR_DCDMIC           2
+#define BM_UARTDBG_ICR_DCDMIC           0x4
+#define BF_UARTDBG_ICR_DCDMIC(v)        (((v) << 2) & 0x4)
+#define BP_UARTDBG_ICR_CTSMIC           1
+#define BM_UARTDBG_ICR_CTSMIC           0x2
+#define BF_UARTDBG_ICR_CTSMIC(v)        (((v) << 1) & 0x2)
+#define BP_UARTDBG_ICR_RIMIC            0
+#define BM_UARTDBG_ICR_RIMIC            0x1
+#define BF_UARTDBG_ICR_RIMIC(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_UARTDBG_DMACR
+ * Address: 0x48
+ * SCT: no
+*/
+#define HW_UARTDBG_DMACR                (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48))
+#define BP_UARTDBG_DMACR_UNAVAILABLE    16
+#define BM_UARTDBG_DMACR_UNAVAILABLE    0xffff0000
+#define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000)
+#define BP_UARTDBG_DMACR_RESERVED       3
+#define BM_UARTDBG_DMACR_RESERVED       0xfff8
+#define BF_UARTDBG_DMACR_RESERVED(v)    (((v) << 3) & 0xfff8)
+#define BP_UARTDBG_DMACR_DMAONERR       2
+#define BM_UARTDBG_DMACR_DMAONERR       0x4
+#define BF_UARTDBG_DMACR_DMAONERR(v)    (((v) << 2) & 0x4)
+#define BP_UARTDBG_DMACR_TXDMAE         1
+#define BM_UARTDBG_DMACR_TXDMAE         0x2
+#define BF_UARTDBG_DMACR_TXDMAE(v)      (((v) << 1) & 0x2)
+#define BP_UARTDBG_DMACR_RXDMAE         0
+#define BM_UARTDBG_DMACR_RXDMAE         0x1
+#define BF_UARTDBG_DMACR_RXDMAE(v)      (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3700__UARTDBG__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h
new file mode 100644
index 0000000000..d621bac1e9
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h
@@ -0,0 +1,877 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__USBCTRL__H__
+#define __HEADERGEN__STMP3700__USBCTRL__H__
+
+#define REGS_USBCTRL_BASE (0x80080000)
+
+#define REGS_USBCTRL_VERSION "3.2.0"
+
+/**
+ * Register: HW_USBCTRL_ID
+ * Address: 0
+ * SCT: no
+*/
+#define HW_USBCTRL_ID           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x0))
+#define BP_USBCTRL_ID_REV       16
+#define BM_USBCTRL_ID_REV       0xff0000
+#define BF_USBCTRL_ID_REV(v)    (((v) << 16) & 0xff0000)
+#define BP_USBCTRL_ID_ID_N      8
+#define BM_USBCTRL_ID_ID_N      0xff00
+#define BF_USBCTRL_ID_ID_N(v)   (((v) << 8) & 0xff00)
+#define BP_USBCTRL_ID_ID        0
+#define BM_USBCTRL_ID_ID        0xff
+#define BF_USBCTRL_ID_ID(v)     (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_GENERAL
+ * Address: 0x4
+ * SCT: no
+*/
+#define HW_USBCTRL_GENERAL          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x4))
+#define BP_USBCTRL_GENERAL_SM       9
+#define BM_USBCTRL_GENERAL_SM       0x200
+#define BF_USBCTRL_GENERAL_SM(v)    (((v) << 9) & 0x200)
+#define BP_USBCTRL_GENERAL_PHYM     6
+#define BM_USBCTRL_GENERAL_PHYM     0x1c0
+#define BF_USBCTRL_GENERAL_PHYM(v)  (((v) << 6) & 0x1c0)
+#define BP_USBCTRL_GENERAL_PHYW     4
+#define BM_USBCTRL_GENERAL_PHYW     0x30
+#define BF_USBCTRL_GENERAL_PHYW(v)  (((v) << 4) & 0x30)
+#define BP_USBCTRL_GENERAL_BWT      3
+#define BM_USBCTRL_GENERAL_BWT      0x8
+#define BF_USBCTRL_GENERAL_BWT(v)   (((v) << 3) & 0x8)
+#define BP_USBCTRL_GENERAL_CLKC     1
+#define BM_USBCTRL_GENERAL_CLKC     0x6
+#define BF_USBCTRL_GENERAL_CLKC(v)  (((v) << 1) & 0x6)
+#define BP_USBCTRL_GENERAL_RT       0
+#define BM_USBCTRL_GENERAL_RT       0x1
+#define BF_USBCTRL_GENERAL_RT(v)    (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_HOST
+ * Address: 0x8
+ * SCT: no
+*/
+#define HW_USBCTRL_HOST             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8))
+#define BP_USBCTRL_HOST_TTPER       24
+#define BM_USBCTRL_HOST_TTPER       0xff000000
+#define BF_USBCTRL_HOST_TTPER(v)    (((v) << 24) & 0xff000000)
+#define BP_USBCTRL_HOST_TTASY       16
+#define BM_USBCTRL_HOST_TTASY       0xff0000
+#define BF_USBCTRL_HOST_TTASY(v)    (((v) << 16) & 0xff0000)
+#define BP_USBCTRL_HOST_NPORT       1
+#define BM_USBCTRL_HOST_NPORT       0xe
+#define BF_USBCTRL_HOST_NPORT(v)    (((v) << 1) & 0xe)
+#define BP_USBCTRL_HOST_HC          0
+#define BM_USBCTRL_HOST_HC          0x1
+#define BF_USBCTRL_HOST_HC(v)       (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_DEVICE
+ * Address: 0xc
+ * SCT: no
+*/
+#define HW_USBCTRL_DEVICE           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0xc))
+#define BP_USBCTRL_DEVICE_DEVEP     1
+#define BM_USBCTRL_DEVICE_DEVEP     0x3e
+#define BF_USBCTRL_DEVICE_DEVEP(v)  (((v) << 1) & 0x3e)
+#define BP_USBCTRL_DEVICE_DC        0
+#define BM_USBCTRL_DEVICE_DC        0x1
+#define BF_USBCTRL_DEVICE_DC(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_TXBUF
+ * Address: 0x10
+ * SCT: no
+*/
+#define HW_USBCTRL_TXBUF                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x10))
+#define BP_USBCTRL_TXBUF_TXLCR          31
+#define BM_USBCTRL_TXBUF_TXLCR          0x80000000
+#define BF_USBCTRL_TXBUF_TXLCR(v)       (((v) << 31) & 0x80000000)
+#define BP_USBCTRL_TXBUF_TXCHANADD      16
+#define BM_USBCTRL_TXBUF_TXCHANADD      0xff0000
+#define BF_USBCTRL_TXBUF_TXCHANADD(v)   (((v) << 16) & 0xff0000)
+#define BP_USBCTRL_TXBUF_TXADD          8
+#define BM_USBCTRL_TXBUF_TXADD          0xff00
+#define BF_USBCTRL_TXBUF_TXADD(v)       (((v) << 8) & 0xff00)
+#define BP_USBCTRL_TXBUF_TXBURST        0
+#define BM_USBCTRL_TXBUF_TXBURST        0xff
+#define BF_USBCTRL_TXBUF_TXBURST(v)     (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_RXBUF
+ * Address: 0x14
+ * SCT: no
+*/
+#define HW_USBCTRL_RXBUF            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14))
+#define BP_USBCTRL_RXBUF_RXADD      8
+#define BM_USBCTRL_RXBUF_RXADD      0xff00
+#define BF_USBCTRL_RXBUF_RXADD(v)   (((v) << 8) & 0xff00)
+#define BP_USBCTRL_RXBUF_RXBURST    0
+#define BM_USBCTRL_RXBUF_RXBURST    0xff
+#define BF_USBCTRL_RXBUF_RXBURST(v) (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_TTTXBUF
+ * Address: 0x18
+ * SCT: no
+*/
+#define HW_USBCTRL_TTTXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x18))
+#define BP_USBCTRL_TTTXBUF_TTTXBUF      0
+#define BM_USBCTRL_TTTXBUF_TTTXBUF      0xffffffff
+#define BF_USBCTRL_TTTXBUF_TTTXBUF(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_USBCTRL_TTRXBUF
+ * Address: 0x1c
+ * SCT: no
+*/
+#define HW_USBCTRL_TTRXBUF              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c))
+#define BP_USBCTRL_TTRXBUF_TTRXBUF      0
+#define BM_USBCTRL_TTRXBUF_TTRXBUF      0xffffffff
+#define BF_USBCTRL_TTRXBUF_TTRXBUF(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_USBCTRL_CAPLENGTH
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_USBCTRL_CAPLENGTH            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x100))
+#define BP_USBCTRL_CAPLENGTH_HCIVER     16
+#define BM_USBCTRL_CAPLENGTH_HCIVER     0xffff0000
+#define BF_USBCTRL_CAPLENGTH_HCIVER(v)  (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_CAPLENGTH_LENGTH     0
+#define BM_USBCTRL_CAPLENGTH_LENGTH     0xff
+#define BF_USBCTRL_CAPLENGTH_LENGTH(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_HCSPARAMS
+ * Address: 0x104
+ * SCT: no
+*/
+#define HW_USBCTRL_HCSPARAMS            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x104))
+#define BP_USBCTRL_HCSPARAMS_NPORTS     0
+#define BM_USBCTRL_HCSPARAMS_NPORTS     0xf
+#define BF_USBCTRL_HCSPARAMS_NPORTS(v)  (((v) << 0) & 0xf)
+#define BP_USBCTRL_HCSPARAMS_PPC        4
+#define BM_USBCTRL_HCSPARAMS_PPC        0x10
+#define BF_USBCTRL_HCSPARAMS_PPC(v)     (((v) << 4) & 0x10)
+#define BP_USBCTRL_HCSPARAMS_NPCC       8
+#define BM_USBCTRL_HCSPARAMS_NPCC       0xf00
+#define BF_USBCTRL_HCSPARAMS_NPCC(v)    (((v) << 8) & 0xf00)
+#define BP_USBCTRL_HCSPARAMS_NCC        12
+#define BM_USBCTRL_HCSPARAMS_NCC        0xf000
+#define BF_USBCTRL_HCSPARAMS_NCC(v)     (((v) << 12) & 0xf000)
+#define BP_USBCTRL_HCSPARAMS_PI         16
+#define BM_USBCTRL_HCSPARAMS_PI         0x10000
+#define BF_USBCTRL_HCSPARAMS_PI(v)      (((v) << 16) & 0x10000)
+#define BP_USBCTRL_HCSPARAMS_NPTT       20
+#define BM_USBCTRL_HCSPARAMS_NPTT       0xf00000
+#define BF_USBCTRL_HCSPARAMS_NPTT(v)    (((v) << 20) & 0xf00000)
+#define BP_USBCTRL_HCSPARAMS_NTT        24
+#define BM_USBCTRL_HCSPARAMS_NTT        0xf000000
+#define BF_USBCTRL_HCSPARAMS_NTT(v)     (((v) << 24) & 0xf000000)
+
+/**
+ * Register: HW_USBCTRL_HCCPARAMS
+ * Address: 0x108
+ * SCT: no
+*/
+#define HW_USBCTRL_HCCPARAMS                        (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x108))
+#define BP_USBCTRL_HCCPARAMS_ADDR64BITCAP           0
+#define BM_USBCTRL_HCCPARAMS_ADDR64BITCAP           0x1
+#define BF_USBCTRL_HCCPARAMS_ADDR64BITCAP(v)        (((v) << 0) & 0x1)
+#define BP_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG      1
+#define BM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG      0x2
+#define BF_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG(v)   (((v) << 1) & 0x2)
+#define BP_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP         2
+#define BM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP         0x4
+#define BF_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP(v)      (((v) << 2) & 0x4)
+#define BP_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD      8
+#define BM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD      0xff00
+#define BF_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD(v)   (((v) << 8) & 0xff00)
+
+/**
+ * Register: HW_USBCTRL_DCIVERSION
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_USBCTRL_DCIVERSION           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x120))
+#define BP_USBCTRL_DCIVERSION_DCIVER    0
+#define BM_USBCTRL_DCIVERSION_DCIVER    0xffff
+#define BF_USBCTRL_DCIVERSION_DCIVER(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_DCCPARAMS
+ * Address: 0x124
+ * SCT: no
+*/
+#define HW_USBCTRL_DCCPARAMS        (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x124))
+#define BP_USBCTRL_DCCPARAMS_HC     8
+#define BM_USBCTRL_DCCPARAMS_HC     0x100
+#define BF_USBCTRL_DCCPARAMS_HC(v)  (((v) << 8) & 0x100)
+#define BP_USBCTRL_DCCPARAMS_DC     7
+#define BM_USBCTRL_DCCPARAMS_DC     0x80
+#define BF_USBCTRL_DCCPARAMS_DC(v)  (((v) << 7) & 0x80)
+#define BP_USBCTRL_DCCPARAMS_DEN    0
+#define BM_USBCTRL_DCCPARAMS_DEN    0x1f
+#define BF_USBCTRL_DCCPARAMS_DEN(v) (((v) << 0) & 0x1f)
+
+/**
+ * Register: HW_USBCTRL_USBCMD
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_USBCTRL_USBCMD           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x140))
+#define BP_USBCTRL_USBCMD_RS        0
+#define BM_USBCTRL_USBCMD_RS        0x1
+#define BF_USBCTRL_USBCMD_RS(v)     (((v) << 0) & 0x1)
+#define BP_USBCTRL_USBCMD_RST       1
+#define BM_USBCTRL_USBCMD_RST       0x2
+#define BF_USBCTRL_USBCMD_RST(v)    (((v) << 1) & 0x2)
+#define BP_USBCTRL_USBCMD_FS0       2
+#define BM_USBCTRL_USBCMD_FS0       0x4
+#define BF_USBCTRL_USBCMD_FS0(v)    (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBCMD_FS1       3
+#define BM_USBCTRL_USBCMD_FS1       0x8
+#define BF_USBCTRL_USBCMD_FS1(v)    (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBCMD_PSE       4
+#define BM_USBCTRL_USBCMD_PSE       0x10
+#define BF_USBCTRL_USBCMD_PSE(v)    (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBCMD_ASE       5
+#define BM_USBCTRL_USBCMD_ASE       0x20
+#define BF_USBCTRL_USBCMD_ASE(v)    (((v) << 5) & 0x20)
+#define BP_USBCTRL_USBCMD_IAA       6
+#define BM_USBCTRL_USBCMD_IAA       0x40
+#define BF_USBCTRL_USBCMD_IAA(v)    (((v) << 6) & 0x40)
+#define BP_USBCTRL_USBCMD_LR        7
+#define BM_USBCTRL_USBCMD_LR        0x80
+#define BF_USBCTRL_USBCMD_LR(v)     (((v) << 7) & 0x80)
+#define BP_USBCTRL_USBCMD_ASP0      8
+#define BM_USBCTRL_USBCMD_ASP0      0x100
+#define BF_USBCTRL_USBCMD_ASP0(v)   (((v) << 8) & 0x100)
+#define BP_USBCTRL_USBCMD_ASP1      9
+#define BM_USBCTRL_USBCMD_ASP1      0x200
+#define BF_USBCTRL_USBCMD_ASP1(v)   (((v) << 9) & 0x200)
+#define BP_USBCTRL_USBCMD_ASPE      11
+#define BM_USBCTRL_USBCMD_ASPE      0x800
+#define BF_USBCTRL_USBCMD_ASPE(v)   (((v) << 11) & 0x800)
+#define BP_USBCTRL_USBCMD_FS2       15
+#define BM_USBCTRL_USBCMD_FS2       0x8000
+#define BF_USBCTRL_USBCMD_FS2(v)    (((v) << 15) & 0x8000)
+#define BP_USBCTRL_USBCMD_ITC       16
+#define BM_USBCTRL_USBCMD_ITC       0xff0000
+#define BF_USBCTRL_USBCMD_ITC(v)    (((v) << 16) & 0xff0000)
+
+/**
+ * Register: HW_USBCTRL_USBSTS
+ * Address: 0x144
+ * SCT: no
+*/
+#define HW_USBCTRL_USBSTS           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x144))
+#define BP_USBCTRL_USBSTS_UI        0
+#define BM_USBCTRL_USBSTS_UI        0x1
+#define BF_USBCTRL_USBSTS_UI(v)     (((v) << 0) & 0x1)
+#define BP_USBCTRL_USBSTS_UEI       1
+#define BM_USBCTRL_USBSTS_UEI       0x2
+#define BF_USBCTRL_USBSTS_UEI(v)    (((v) << 1) & 0x2)
+#define BP_USBCTRL_USBSTS_PCI       2
+#define BM_USBCTRL_USBSTS_PCI       0x4
+#define BF_USBCTRL_USBSTS_PCI(v)    (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBSTS_FRI       3
+#define BM_USBCTRL_USBSTS_FRI       0x8
+#define BF_USBCTRL_USBSTS_FRI(v)    (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBSTS_SEI       4
+#define BM_USBCTRL_USBSTS_SEI       0x10
+#define BF_USBCTRL_USBSTS_SEI(v)    (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBSTS_AAI       5
+#define BM_USBCTRL_USBSTS_AAI       0x20
+#define BF_USBCTRL_USBSTS_AAI(v)    (((v) << 5) & 0x20)
+#define BP_USBCTRL_USBSTS_URI       6
+#define BM_USBCTRL_USBSTS_URI       0x40
+#define BF_USBCTRL_USBSTS_URI(v)    (((v) << 6) & 0x40)
+#define BP_USBCTRL_USBSTS_SRI       7
+#define BM_USBCTRL_USBSTS_SRI       0x80
+#define BF_USBCTRL_USBSTS_SRI(v)    (((v) << 7) & 0x80)
+#define BP_USBCTRL_USBSTS_SLI       8
+#define BM_USBCTRL_USBSTS_SLI       0x100
+#define BF_USBCTRL_USBSTS_SLI(v)    (((v) << 8) & 0x100)
+#define BP_USBCTRL_USBSTS_ULPII     10
+#define BM_USBCTRL_USBSTS_ULPII     0x400
+#define BF_USBCTRL_USBSTS_ULPII(v)  (((v) << 10) & 0x400)
+#define BP_USBCTRL_USBSTS_HCH       12
+#define BM_USBCTRL_USBSTS_HCH       0x1000
+#define BF_USBCTRL_USBSTS_HCH(v)    (((v) << 12) & 0x1000)
+#define BP_USBCTRL_USBSTS_RCL       13
+#define BM_USBCTRL_USBSTS_RCL       0x2000
+#define BF_USBCTRL_USBSTS_RCL(v)    (((v) << 13) & 0x2000)
+#define BP_USBCTRL_USBSTS_PS        14
+#define BM_USBCTRL_USBSTS_PS        0x4000
+#define BF_USBCTRL_USBSTS_PS(v)     (((v) << 14) & 0x4000)
+#define BP_USBCTRL_USBSTS_AS        15
+#define BM_USBCTRL_USBSTS_AS        0x8000
+#define BF_USBCTRL_USBSTS_AS(v)     (((v) << 15) & 0x8000)
+#define BP_USBCTRL_USBSTS_NAKI      16
+#define BM_USBCTRL_USBSTS_NAKI      0x10000
+#define BF_USBCTRL_USBSTS_NAKI(v)   (((v) << 16) & 0x10000)
+
+/**
+ * Register: HW_USBCTRL_USBINTR
+ * Address: 0x148
+ * SCT: no
+*/
+#define HW_USBCTRL_USBINTR          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x148))
+#define BP_USBCTRL_USBINTR_UE       0
+#define BM_USBCTRL_USBINTR_UE       0x1
+#define BF_USBCTRL_USBINTR_UE(v)    (((v) << 0) & 0x1)
+#define BP_USBCTRL_USBINTR_UEE      1
+#define BM_USBCTRL_USBINTR_UEE      0x2
+#define BF_USBCTRL_USBINTR_UEE(v)   (((v) << 1) & 0x2)
+#define BP_USBCTRL_USBINTR_PCE      2
+#define BM_USBCTRL_USBINTR_PCE      0x4
+#define BF_USBCTRL_USBINTR_PCE(v)   (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBINTR_FRE      3
+#define BM_USBCTRL_USBINTR_FRE      0x8
+#define BF_USBCTRL_USBINTR_FRE(v)   (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBINTR_SEE      4
+#define BM_USBCTRL_USBINTR_SEE      0x10
+#define BF_USBCTRL_USBINTR_SEE(v)   (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBINTR_AAE      5
+#define BM_USBCTRL_USBINTR_AAE      0x20
+#define BF_USBCTRL_USBINTR_AAE(v)   (((v) << 5) & 0x20)
+#define BP_USBCTRL_USBINTR_URE      6
+#define BM_USBCTRL_USBINTR_URE      0x40
+#define BF_USBCTRL_USBINTR_URE(v)   (((v) << 6) & 0x40)
+#define BP_USBCTRL_USBINTR_SRE      7
+#define BM_USBCTRL_USBINTR_SRE      0x80
+#define BF_USBCTRL_USBINTR_SRE(v)   (((v) << 7) & 0x80)
+#define BP_USBCTRL_USBINTR_SLE      8
+#define BM_USBCTRL_USBINTR_SLE      0x100
+#define BF_USBCTRL_USBINTR_SLE(v)   (((v) << 8) & 0x100)
+#define BP_USBCTRL_USBINTR_ULPIE    10
+#define BM_USBCTRL_USBINTR_ULPIE    0x400
+#define BF_USBCTRL_USBINTR_ULPIE(v) (((v) << 10) & 0x400)
+#define BP_USBCTRL_USBINTR_NAKE     16
+#define BM_USBCTRL_USBINTR_NAKE     0x10000
+#define BF_USBCTRL_USBINTR_NAKE(v)  (((v) << 16) & 0x10000)
+
+/**
+ * Register: HW_USBCTRL_FRINDEX
+ * Address: 0x14c
+ * SCT: no
+*/
+#define HW_USBCTRL_FRINDEX              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14c))
+#define BP_USBCTRL_FRINDEX_LISTINDEX    3
+#define BM_USBCTRL_FRINDEX_LISTINDEX    0x3ff8
+#define BF_USBCTRL_FRINDEX_LISTINDEX(v) (((v) << 3) & 0x3ff8)
+#define BP_USBCTRL_FRINDEX_UINDEX       0
+#define BM_USBCTRL_FRINDEX_UINDEX       0x7
+#define BF_USBCTRL_FRINDEX_UINDEX(v)    (((v) << 0) & 0x7)
+
+/**
+ * Register: HW_USBCTRL_CTRLDSSEGMENT
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_USBCTRL_CTRLDSSEGMENT            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x150))
+#define BP_USBCTRL_CTRLDSSEGMENT_EMPTY      0
+#define BM_USBCTRL_CTRLDSSEGMENT_EMPTY      0xffffffff
+#define BF_USBCTRL_CTRLDSSEGMENT_EMPTY(v)   (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_USBCTRL_PERIODICLISTBASE
+ * Address: 0x154
+ * SCT: no
+*/
+#define HW_USBCTRL_PERIODICLISTBASE             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154))
+#define BP_USBCTRL_PERIODICLISTBASE_BASEADDR    12
+#define BM_USBCTRL_PERIODICLISTBASE_BASEADDR    0xfffff000
+#define BF_USBCTRL_PERIODICLISTBASE_BASEADDR(v) (((v) << 12) & 0xfffff000)
+
+/**
+ * Register: HW_USBCTRL_ASYNCLISTADDR
+ * Address: 0x158
+ * SCT: no
+*/
+#define HW_USBCTRL_ASYNCLISTADDR            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158))
+#define BP_USBCTRL_ASYNCLISTADDR_ASYBASE    5
+#define BM_USBCTRL_ASYNCLISTADDR_ASYBASE    0xffffffe0
+#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) (((v) << 5) & 0xffffffe0)
+
+/**
+ * Register: HW_USBCTRL_TTCTRL
+ * Address: 0x15c
+ * SCT: no
+*/
+#define HW_USBCTRL_TTCTRL           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x15c))
+#define BP_USBCTRL_TTCTRL_TTHA      24
+#define BM_USBCTRL_TTCTRL_TTHA      0x7f000000
+#define BF_USBCTRL_TTCTRL_TTHA(v)   (((v) << 24) & 0x7f000000)
+
+/**
+ * Register: HW_USBCTRL_BURSTSIZE
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_USBCTRL_BURSTSIZE        (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x160))
+#define BP_USBCTRL_BURSTSIZE_TX     8
+#define BM_USBCTRL_BURSTSIZE_TX     0xff00
+#define BF_USBCTRL_BURSTSIZE_TX(v)  (((v) << 8) & 0xff00)
+#define BP_USBCTRL_BURSTSIZE_RX     0
+#define BM_USBCTRL_BURSTSIZE_RX     0xff
+#define BF_USBCTRL_BURSTSIZE_RX(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_TXFILLTUNING
+ * Address: 0x164
+ * SCT: no
+*/
+#define HW_USBCTRL_TXFILLTUNING                 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x164))
+#define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES     16
+#define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES     0x3f0000
+#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v)  (((v) << 16) & 0x3f0000)
+#define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH      8
+#define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH      0x1f00
+#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v)   (((v) << 8) & 0x1f00)
+#define BP_USBCTRL_TXFILLTUNING_TXSCHOH         0
+#define BM_USBCTRL_TXFILLTUNING_TXSCHOH         0xff
+#define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v)      (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_TXTTFILLTUNING
+ * Address: 0x168
+ * SCT: no
+*/
+#define HW_USBCTRL_TXTTFILLTUNING           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x168))
+#define BP_USBCTRL_TXTTFILLTUNING_EMPTY     0
+#define BM_USBCTRL_TXTTFILLTUNING_EMPTY     0xffffffff
+#define BF_USBCTRL_TXTTFILLTUNING_EMPTY(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_USBCTRL_ULPI
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_USBCTRL_ULPI             (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x170))
+#define BP_USBCTRL_ULPI_WAKEUP      31
+#define BM_USBCTRL_ULPI_WAKEUP      0x80000000
+#define BF_USBCTRL_ULPI_WAKEUP(v)   (((v) << 31) & 0x80000000)
+#define BP_USBCTRL_ULPI_RUN         30
+#define BM_USBCTRL_ULPI_RUN         0x40000000
+#define BF_USBCTRL_ULPI_RUN(v)      (((v) << 30) & 0x40000000)
+#define BP_USBCTRL_ULPI_RDWR        29
+#define BM_USBCTRL_ULPI_RDWR        0x20000000
+#define BF_USBCTRL_ULPI_RDWR(v)     (((v) << 29) & 0x20000000)
+#define BP_USBCTRL_ULPI_ERROR       28
+#define BM_USBCTRL_ULPI_ERROR       0x10000000
+#define BF_USBCTRL_ULPI_ERROR(v)    (((v) << 28) & 0x10000000)
+#define BP_USBCTRL_ULPI_SYNC        27
+#define BM_USBCTRL_ULPI_SYNC        0x8000000
+#define BF_USBCTRL_ULPI_SYNC(v)     (((v) << 27) & 0x8000000)
+#define BP_USBCTRL_ULPI_PORT        24
+#define BM_USBCTRL_ULPI_PORT        0x7000000
+#define BF_USBCTRL_ULPI_PORT(v)     (((v) << 24) & 0x7000000)
+#define BP_USBCTRL_ULPI_ADDR        16
+#define BM_USBCTRL_ULPI_ADDR        0xff0000
+#define BF_USBCTRL_ULPI_ADDR(v)     (((v) << 16) & 0xff0000)
+#define BP_USBCTRL_ULPI_DATARD      8
+#define BM_USBCTRL_ULPI_DATARD      0xff00
+#define BF_USBCTRL_ULPI_DATARD(v)   (((v) << 8) & 0xff00)
+#define BP_USBCTRL_ULPI_DATAWR      0
+#define BM_USBCTRL_ULPI_DATAWR      0xff
+#define BF_USBCTRL_ULPI_DATAWR(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_USBCTRL_VFRAME
+ * Address: 0x174
+ * SCT: no
+*/
+#define HW_USBCTRL_VFRAME           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x174))
+#define BP_USBCTRL_VFRAME_EMPTY     0
+#define BM_USBCTRL_VFRAME_EMPTY     0xffffffff
+#define BF_USBCTRL_VFRAME_EMPTY(v)  (((v) << 0) & 0xffffffff)
+
+/**
+ * Register: HW_USBCTRL_EPNAK
+ * Address: 0x178
+ * SCT: no
+*/
+#define HW_USBCTRL_EPNAK            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x178))
+#define BP_USBCTRL_EPNAK_EPTN       16
+#define BM_USBCTRL_EPNAK_EPTN       0xffff0000
+#define BF_USBCTRL_EPNAK_EPTN(v)    (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_EPNAK_EPRN       0
+#define BM_USBCTRL_EPNAK_EPRN       0xffff
+#define BF_USBCTRL_EPNAK_EPRN(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_EPNAKEN
+ * Address: 0x17c
+ * SCT: no
+*/
+#define HW_USBCTRL_EPNAKEN          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x17c))
+#define BP_USBCTRL_EPNAKEN_EPTNE    16
+#define BM_USBCTRL_EPNAKEN_EPTNE    0xffff0000
+#define BF_USBCTRL_EPNAKEN_EPTNE(v) (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_EPNAKEN_EPRNE    0
+#define BM_USBCTRL_EPNAKEN_EPRNE    0xffff
+#define BF_USBCTRL_EPNAKEN_EPRNE(v) (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_CONFIGFLAG
+ * Address: 0x180
+ * SCT: no
+*/
+#define HW_USBCTRL_CONFIGFLAG           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x180))
+#define BP_USBCTRL_CONFIGFLAG_FLAG      0
+#define BM_USBCTRL_CONFIGFLAG_FLAG      0x1
+#define BF_USBCTRL_CONFIGFLAG_FLAG(v)   (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_PORTSC1
+ * Address: 0x184
+ * SCT: no
+*/
+#define HW_USBCTRL_PORTSC1                      (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x184))
+#define BP_USBCTRL_PORTSC1_PTS                  30
+#define BM_USBCTRL_PORTSC1_PTS                  0xc0000000
+#define BV_USBCTRL_PORTSC1_PTS__UTMI            0x0
+#define BV_USBCTRL_PORTSC1_PTS__PHIL            0x1
+#define BV_USBCTRL_PORTSC1_PTS__ULPI            0x2
+#define BV_USBCTRL_PORTSC1_PTS__SERIAL          0x3
+#define BF_USBCTRL_PORTSC1_PTS(v)               (((v) << 30) & 0xc0000000)
+#define BF_USBCTRL_PORTSC1_PTS_V(v)             ((BV_USBCTRL_PORTSC1_PTS__##v << 30) & 0xc0000000)
+#define BP_USBCTRL_PORTSC1_STS                  29
+#define BM_USBCTRL_PORTSC1_STS                  0x20000000
+#define BF_USBCTRL_PORTSC1_STS(v)               (((v) << 29) & 0x20000000)
+#define BP_USBCTRL_PORTSC1_PTW                  28
+#define BM_USBCTRL_PORTSC1_PTW                  0x10000000
+#define BF_USBCTRL_PORTSC1_PTW(v)               (((v) << 28) & 0x10000000)
+#define BP_USBCTRL_PORTSC1_PSPD                 26
+#define BM_USBCTRL_PORTSC1_PSPD                 0xc000000
+#define BV_USBCTRL_PORTSC1_PSPD__FULL           0x0
+#define BV_USBCTRL_PORTSC1_PSPD__LO             0x1
+#define BV_USBCTRL_PORTSC1_PSPD__HI             0x2
+#define BF_USBCTRL_PORTSC1_PSPD(v)              (((v) << 26) & 0xc000000)
+#define BF_USBCTRL_PORTSC1_PSPD_V(v)            ((BV_USBCTRL_PORTSC1_PSPD__##v << 26) & 0xc000000)
+#define BP_USBCTRL_PORTSC1_PFSC                 24
+#define BM_USBCTRL_PORTSC1_PFSC                 0x1000000
+#define BF_USBCTRL_PORTSC1_PFSC(v)              (((v) << 24) & 0x1000000)
+#define BP_USBCTRL_PORTSC1_PHCD                 23
+#define BM_USBCTRL_PORTSC1_PHCD                 0x800000
+#define BF_USBCTRL_PORTSC1_PHCD(v)              (((v) << 23) & 0x800000)
+#define BP_USBCTRL_PORTSC1_WKOC                 22
+#define BM_USBCTRL_PORTSC1_WKOC                 0x400000
+#define BF_USBCTRL_PORTSC1_WKOC(v)              (((v) << 22) & 0x400000)
+#define BP_USBCTRL_PORTSC1_WKDS                 21
+#define BM_USBCTRL_PORTSC1_WKDS                 0x200000
+#define BF_USBCTRL_PORTSC1_WKDS(v)              (((v) << 21) & 0x200000)
+#define BP_USBCTRL_PORTSC1_WKCN                 20
+#define BM_USBCTRL_PORTSC1_WKCN                 0x100000
+#define BF_USBCTRL_PORTSC1_WKCN(v)              (((v) << 20) & 0x100000)
+#define BP_USBCTRL_PORTSC1_PTC                  16
+#define BM_USBCTRL_PORTSC1_PTC                  0xf0000
+#define BV_USBCTRL_PORTSC1_PTC__DISABLE         0x0
+#define BV_USBCTRL_PORTSC1_PTC__J               0x1
+#define BV_USBCTRL_PORTSC1_PTC__K               0x2
+#define BV_USBCTRL_PORTSC1_PTC__SE0orNAK        0x3
+#define BV_USBCTRL_PORTSC1_PTC__Packet          0x4
+#define BV_USBCTRL_PORTSC1_PTC__ForceEnableHS   0x5
+#define BV_USBCTRL_PORTSC1_PTC__ForceEnableFS   0x6
+#define BV_USBCTRL_PORTSC1_PTC__ForceEnableLS   0x7
+#define BF_USBCTRL_PORTSC1_PTC(v)               (((v) << 16) & 0xf0000)
+#define BF_USBCTRL_PORTSC1_PTC_V(v)             ((BV_USBCTRL_PORTSC1_PTC__##v << 16) & 0xf0000)
+#define BP_USBCTRL_PORTSC1_PIC                  14
+#define BM_USBCTRL_PORTSC1_PIC                  0xc000
+#define BV_USBCTRL_PORTSC1_PIC__OFF             0x0
+#define BV_USBCTRL_PORTSC1_PIC__AMBER           0x1
+#define BV_USBCTRL_PORTSC1_PIC__GREEN           0x2
+#define BV_USBCTRL_PORTSC1_PIC__UNDEF           0x3
+#define BF_USBCTRL_PORTSC1_PIC(v)               (((v) << 14) & 0xc000)
+#define BF_USBCTRL_PORTSC1_PIC_V(v)             ((BV_USBCTRL_PORTSC1_PIC__##v << 14) & 0xc000)
+#define BP_USBCTRL_PORTSC1_PO                   13
+#define BM_USBCTRL_PORTSC1_PO                   0x2000
+#define BF_USBCTRL_PORTSC1_PO(v)                (((v) << 13) & 0x2000)
+#define BP_USBCTRL_PORTSC1_PP                   12
+#define BM_USBCTRL_PORTSC1_PP                   0x1000
+#define BF_USBCTRL_PORTSC1_PP(v)                (((v) << 12) & 0x1000)
+#define BP_USBCTRL_PORTSC1_LS                   10
+#define BM_USBCTRL_PORTSC1_LS                   0xc00
+#define BV_USBCTRL_PORTSC1_LS__SE0              0x0
+#define BV_USBCTRL_PORTSC1_LS__K                0x1
+#define BV_USBCTRL_PORTSC1_LS__J                0x2
+#define BF_USBCTRL_PORTSC1_LS(v)                (((v) << 10) & 0xc00)
+#define BF_USBCTRL_PORTSC1_LS_V(v)              ((BV_USBCTRL_PORTSC1_LS__##v << 10) & 0xc00)
+#define BP_USBCTRL_PORTSC1_HSP                  9
+#define BM_USBCTRL_PORTSC1_HSP                  0x200
+#define BF_USBCTRL_PORTSC1_HSP(v)               (((v) << 9) & 0x200)
+#define BP_USBCTRL_PORTSC1_PR                   8
+#define BM_USBCTRL_PORTSC1_PR                   0x100
+#define BF_USBCTRL_PORTSC1_PR(v)                (((v) << 8) & 0x100)
+#define BP_USBCTRL_PORTSC1_SUSP                 7
+#define BM_USBCTRL_PORTSC1_SUSP                 0x80
+#define BF_USBCTRL_PORTSC1_SUSP(v)              (((v) << 7) & 0x80)
+#define BP_USBCTRL_PORTSC1_FPR                  6
+#define BM_USBCTRL_PORTSC1_FPR                  0x40
+#define BF_USBCTRL_PORTSC1_FPR(v)               (((v) << 6) & 0x40)
+#define BP_USBCTRL_PORTSC1_OCC                  5
+#define BM_USBCTRL_PORTSC1_OCC                  0x20
+#define BF_USBCTRL_PORTSC1_OCC(v)               (((v) << 5) & 0x20)
+#define BP_USBCTRL_PORTSC1_OCA                  4
+#define BM_USBCTRL_PORTSC1_OCA                  0x10
+#define BF_USBCTRL_PORTSC1_OCA(v)               (((v) << 4) & 0x10)
+#define BP_USBCTRL_PORTSC1_PEC                  3
+#define BM_USBCTRL_PORTSC1_PEC                  0x8
+#define BF_USBCTRL_PORTSC1_PEC(v)               (((v) << 3) & 0x8)
+#define BP_USBCTRL_PORTSC1_PE                   2
+#define BM_USBCTRL_PORTSC1_PE                   0x4
+#define BF_USBCTRL_PORTSC1_PE(v)                (((v) << 2) & 0x4)
+#define BP_USBCTRL_PORTSC1_CSC                  1
+#define BM_USBCTRL_PORTSC1_CSC                  0x2
+#define BF_USBCTRL_PORTSC1_CSC(v)               (((v) << 1) & 0x2)
+#define BP_USBCTRL_PORTSC1_CCS                  0
+#define BM_USBCTRL_PORTSC1_CCS                  0x1
+#define BF_USBCTRL_PORTSC1_CCS(v)               (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_OTGSC
+ * Address: 0x1a4
+ * SCT: no
+*/
+#define HW_USBCTRL_OTGSC            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a4))
+#define BP_USBCTRL_OTGSC_DPIE       30
+#define BM_USBCTRL_OTGSC_DPIE       0x40000000
+#define BF_USBCTRL_OTGSC_DPIE(v)    (((v) << 30) & 0x40000000)
+#define BP_USBCTRL_OTGSC_ONEMSE     29
+#define BM_USBCTRL_OTGSC_ONEMSE     0x20000000
+#define BF_USBCTRL_OTGSC_ONEMSE(v)  (((v) << 29) & 0x20000000)
+#define BP_USBCTRL_OTGSC_BSEIE      28
+#define BM_USBCTRL_OTGSC_BSEIE      0x10000000
+#define BF_USBCTRL_OTGSC_BSEIE(v)   (((v) << 28) & 0x10000000)
+#define BP_USBCTRL_OTGSC_BSVIE      27
+#define BM_USBCTRL_OTGSC_BSVIE      0x8000000
+#define BF_USBCTRL_OTGSC_BSVIE(v)   (((v) << 27) & 0x8000000)
+#define BP_USBCTRL_OTGSC_ASVIE      26
+#define BM_USBCTRL_OTGSC_ASVIE      0x4000000
+#define BF_USBCTRL_OTGSC_ASVIE(v)   (((v) << 26) & 0x4000000)
+#define BP_USBCTRL_OTGSC_AVVIE      25
+#define BM_USBCTRL_OTGSC_AVVIE      0x2000000
+#define BF_USBCTRL_OTGSC_AVVIE(v)   (((v) << 25) & 0x2000000)
+#define BP_USBCTRL_OTGSC_IDIE       24
+#define BM_USBCTRL_OTGSC_IDIE       0x1000000
+#define BF_USBCTRL_OTGSC_IDIE(v)    (((v) << 24) & 0x1000000)
+#define BP_USBCTRL_OTGSC_DPIS       22
+#define BM_USBCTRL_OTGSC_DPIS       0x400000
+#define BF_USBCTRL_OTGSC_DPIS(v)    (((v) << 22) & 0x400000)
+#define BP_USBCTRL_OTGSC_ONEMSS     21
+#define BM_USBCTRL_OTGSC_ONEMSS     0x200000
+#define BF_USBCTRL_OTGSC_ONEMSS(v)  (((v) << 21) & 0x200000)
+#define BP_USBCTRL_OTGSC_BSEIS      20
+#define BM_USBCTRL_OTGSC_BSEIS      0x100000
+#define BF_USBCTRL_OTGSC_BSEIS(v)   (((v) << 20) & 0x100000)
+#define BP_USBCTRL_OTGSC_BSVIS      19
+#define BM_USBCTRL_OTGSC_BSVIS      0x80000
+#define BF_USBCTRL_OTGSC_BSVIS(v)   (((v) << 19) & 0x80000)
+#define BP_USBCTRL_OTGSC_ASVIS      18
+#define BM_USBCTRL_OTGSC_ASVIS      0x40000
+#define BF_USBCTRL_OTGSC_ASVIS(v)   (((v) << 18) & 0x40000)
+#define BP_USBCTRL_OTGSC_AVVIS      17
+#define BM_USBCTRL_OTGSC_AVVIS      0x20000
+#define BF_USBCTRL_OTGSC_AVVIS(v)   (((v) << 17) & 0x20000)
+#define BP_USBCTRL_OTGSC_IDIS       16
+#define BM_USBCTRL_OTGSC_IDIS       0x10000
+#define BF_USBCTRL_OTGSC_IDIS(v)    (((v) << 16) & 0x10000)
+#define BP_USBCTRL_OTGSC_DPS        14
+#define BM_USBCTRL_OTGSC_DPS        0x4000
+#define BF_USBCTRL_OTGSC_DPS(v)     (((v) << 14) & 0x4000)
+#define BP_USBCTRL_OTGSC_ONEMST     13
+#define BM_USBCTRL_OTGSC_ONEMST     0x2000
+#define BF_USBCTRL_OTGSC_ONEMST(v)  (((v) << 13) & 0x2000)
+#define BP_USBCTRL_OTGSC_BSE        12
+#define BM_USBCTRL_OTGSC_BSE        0x1000
+#define BF_USBCTRL_OTGSC_BSE(v)     (((v) << 12) & 0x1000)
+#define BP_USBCTRL_OTGSC_BSV        11
+#define BM_USBCTRL_OTGSC_BSV        0x800
+#define BF_USBCTRL_OTGSC_BSV(v)     (((v) << 11) & 0x800)
+#define BP_USBCTRL_OTGSC_ASV        10
+#define BM_USBCTRL_OTGSC_ASV        0x400
+#define BF_USBCTRL_OTGSC_ASV(v)     (((v) << 10) & 0x400)
+#define BP_USBCTRL_OTGSC_AVV        9
+#define BM_USBCTRL_OTGSC_AVV        0x200
+#define BF_USBCTRL_OTGSC_AVV(v)     (((v) << 9) & 0x200)
+#define BP_USBCTRL_OTGSC_ID         8
+#define BM_USBCTRL_OTGSC_ID         0x100
+#define BF_USBCTRL_OTGSC_ID(v)      (((v) << 8) & 0x100)
+#define BP_USBCTRL_OTGSC_HABA       7
+#define BM_USBCTRL_OTGSC_HABA       0x80
+#define BF_USBCTRL_OTGSC_HABA(v)    (((v) << 7) & 0x80)
+#define BP_USBCTRL_OTGSC_HADP       6
+#define BM_USBCTRL_OTGSC_HADP       0x40
+#define BF_USBCTRL_OTGSC_HADP(v)    (((v) << 6) & 0x40)
+#define BP_USBCTRL_OTGSC_IDPU       5
+#define BM_USBCTRL_OTGSC_IDPU       0x20
+#define BF_USBCTRL_OTGSC_IDPU(v)    (((v) << 5) & 0x20)
+#define BP_USBCTRL_OTGSC_DP         4
+#define BM_USBCTRL_OTGSC_DP         0x10
+#define BF_USBCTRL_OTGSC_DP(v)      (((v) << 4) & 0x10)
+#define BP_USBCTRL_OTGSC_OT         3
+#define BM_USBCTRL_OTGSC_OT         0x8
+#define BF_USBCTRL_OTGSC_OT(v)      (((v) << 3) & 0x8)
+#define BP_USBCTRL_OTGSC_HAAR       2
+#define BM_USBCTRL_OTGSC_HAAR       0x4
+#define BF_USBCTRL_OTGSC_HAAR(v)    (((v) << 2) & 0x4)
+#define BP_USBCTRL_OTGSC_VC         1
+#define BM_USBCTRL_OTGSC_VC         0x2
+#define BF_USBCTRL_OTGSC_VC(v)      (((v) << 1) & 0x2)
+#define BP_USBCTRL_OTGSC_VD         0
+#define BM_USBCTRL_OTGSC_VD         0x1
+#define BF_USBCTRL_OTGSC_VD(v)      (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBCTRL_USBMODE
+ * Address: 0x1a8
+ * SCT: no
+*/
+#define HW_USBCTRL_USBMODE              (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a8))
+#define BP_USBCTRL_USBMODE_SDIS         4
+#define BM_USBCTRL_USBMODE_SDIS         0x10
+#define BF_USBCTRL_USBMODE_SDIS(v)      (((v) << 4) & 0x10)
+#define BP_USBCTRL_USBMODE_SLOM         3
+#define BM_USBCTRL_USBMODE_SLOM         0x8
+#define BF_USBCTRL_USBMODE_SLOM(v)      (((v) << 3) & 0x8)
+#define BP_USBCTRL_USBMODE_ES           2
+#define BM_USBCTRL_USBMODE_ES           0x4
+#define BF_USBCTRL_USBMODE_ES(v)        (((v) << 2) & 0x4)
+#define BP_USBCTRL_USBMODE_CM           0
+#define BM_USBCTRL_USBMODE_CM           0x3
+#define BV_USBCTRL_USBMODE_CM__IDLE     0x0
+#define BV_USBCTRL_USBMODE_CM__DEVICE   0x2
+#define BV_USBCTRL_USBMODE_CM__HOST     0x3
+#define BF_USBCTRL_USBMODE_CM(v)        (((v) << 0) & 0x3)
+#define BF_USBCTRL_USBMODE_CM_V(v)      ((BV_USBCTRL_USBMODE_CM__##v << 0) & 0x3)
+
+/**
+ * Register: HW_USBCTRL_ENDPTSETUPSTAT
+ * Address: 0x1ac
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTSETUPSTAT           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1ac))
+#define BP_USBCTRL_ENDPTSETUPSTAT_STS       0
+#define BM_USBCTRL_ENDPTSETUPSTAT_STS       0xffff
+#define BF_USBCTRL_ENDPTSETUPSTAT_STS(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_ENDPTPRIME
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTPRIME           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b0))
+#define BP_USBCTRL_ENDPTPRIME_PETB      16
+#define BM_USBCTRL_ENDPTPRIME_PETB      0xffff0000
+#define BF_USBCTRL_ENDPTPRIME_PETB(v)   (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_ENDPTPRIME_PERB      0
+#define BM_USBCTRL_ENDPTPRIME_PERB      0xffff
+#define BF_USBCTRL_ENDPTPRIME_PERB(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_ENDPTFLUSH
+ * Address: 0x1b4
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTFLUSH           (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b4))
+#define BP_USBCTRL_ENDPTFLUSH_FETB      16
+#define BM_USBCTRL_ENDPTFLUSH_FETB      0xffff0000
+#define BF_USBCTRL_ENDPTFLUSH_FETB(v)   (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_ENDPTFLUSH_FERB      0
+#define BM_USBCTRL_ENDPTFLUSH_FERB      0xffff
+#define BF_USBCTRL_ENDPTFLUSH_FERB(v)   (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_ENDPTSTATUS
+ * Address: 0x1b8
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTSTATUS          (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b8))
+#define BP_USBCTRL_ENDPTSTATUS_ETBR     16
+#define BM_USBCTRL_ENDPTSTATUS_ETBR     0xffff0000
+#define BF_USBCTRL_ENDPTSTATUS_ETBR(v)  (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_ENDPTSTATUS_ERBR     0
+#define BM_USBCTRL_ENDPTSTATUS_ERBR     0xffff
+#define BF_USBCTRL_ENDPTSTATUS_ERBR(v)  (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_ENDPTCOMPLETE
+ * Address: 0x1bc
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTCOMPLETE            (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1bc))
+#define BP_USBCTRL_ENDPTCOMPLETE_ETCE       16
+#define BM_USBCTRL_ENDPTCOMPLETE_ETCE       0xffff0000
+#define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v)    (((v) << 16) & 0xffff0000)
+#define BP_USBCTRL_ENDPTCOMPLETE_ERCE       0
+#define BM_USBCTRL_ENDPTCOMPLETE_ERCE       0xffff
+#define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBCTRL_ENDPTCTRLn
+ * Address: 0x1c0+n*0x4
+ * SCT: no
+*/
+#define HW_USBCTRL_ENDPTCTRLn(n)                (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c0+(n)*0x4))
+#define BP_USBCTRL_ENDPTCTRLn_TXE               23
+#define BM_USBCTRL_ENDPTCTRLn_TXE               0x800000
+#define BF_USBCTRL_ENDPTCTRLn_TXE(v)            (((v) << 23) & 0x800000)
+#define BP_USBCTRL_ENDPTCTRLn_TXR               22
+#define BM_USBCTRL_ENDPTCTRLn_TXR               0x400000
+#define BF_USBCTRL_ENDPTCTRLn_TXR(v)            (((v) << 22) & 0x400000)
+#define BP_USBCTRL_ENDPTCTRLn_TXI               21
+#define BM_USBCTRL_ENDPTCTRLn_TXI               0x200000
+#define BF_USBCTRL_ENDPTCTRLn_TXI(v)            (((v) << 21) & 0x200000)
+#define BP_USBCTRL_ENDPTCTRLn_TXT               18
+#define BM_USBCTRL_ENDPTCTRLn_TXT               0xc0000
+#define BV_USBCTRL_ENDPTCTRLn_TXT__ISOCHRONOUS  0x1
+#define BV_USBCTRL_ENDPTCTRLn_TXT__BULK         0x2
+#define BV_USBCTRL_ENDPTCTRLn_TXT__INT          0x3
+#define BF_USBCTRL_ENDPTCTRLn_TXT(v)            (((v) << 18) & 0xc0000)
+#define BF_USBCTRL_ENDPTCTRLn_TXT_V(v)          ((BV_USBCTRL_ENDPTCTRLn_TXT__##v << 18) & 0xc0000)
+#define BP_USBCTRL_ENDPTCTRLn_TXS               16
+#define BM_USBCTRL_ENDPTCTRLn_TXS               0x10000
+#define BF_USBCTRL_ENDPTCTRLn_TXS(v)            (((v) << 16) & 0x10000)
+#define BP_USBCTRL_ENDPTCTRLn_RXE               7
+#define BM_USBCTRL_ENDPTCTRLn_RXE               0x80
+#define BF_USBCTRL_ENDPTCTRLn_RXE(v)            (((v) << 7) & 0x80)
+#define BP_USBCTRL_ENDPTCTRLn_RXR               6
+#define BM_USBCTRL_ENDPTCTRLn_RXR               0x40
+#define BF_USBCTRL_ENDPTCTRLn_RXR(v)            (((v) << 6) & 0x40)
+#define BP_USBCTRL_ENDPTCTRLn_RXI               5
+#define BM_USBCTRL_ENDPTCTRLn_RXI               0x20
+#define BF_USBCTRL_ENDPTCTRLn_RXI(v)            (((v) << 5) & 0x20)
+#define BP_USBCTRL_ENDPTCTRLn_RXT               2
+#define BM_USBCTRL_ENDPTCTRLn_RXT               0xc
+#define BF_USBCTRL_ENDPTCTRLn_RXT(v)            (((v) << 2) & 0xc)
+#define BP_USBCTRL_ENDPTCTRLn_RXS               0
+#define BM_USBCTRL_ENDPTCTRLn_RXS               0x1
+#define BF_USBCTRL_ENDPTCTRLn_RXS(v)            (((v) << 0) & 0x1)
+
+#endif /* __HEADERGEN__STMP3700__USBCTRL__H__ */
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h
new file mode 100644
index 0000000000..ae9359e1dd
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h
@@ -0,0 +1,300 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__USBPHY__H__
+#define __HEADERGEN__STMP3700__USBPHY__H__
+
+#define REGS_USBPHY_BASE (0x8007c000)
+
+#define REGS_USBPHY_VERSION "3.2.0"
+
+/**
+ * Register: HW_USBPHY_PWD
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_USBPHY_PWD               (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0))
+#define HW_USBPHY_PWD_SET           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4))
+#define HW_USBPHY_PWD_CLR           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8))
+#define HW_USBPHY_PWD_TOG           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc))
+#define BP_USBPHY_PWD_RXPWDRX       20
+#define BM_USBPHY_PWD_RXPWDRX       0x100000
+#define BF_USBPHY_PWD_RXPWDRX(v)    (((v) << 20) & 0x100000)
+#define BP_USBPHY_PWD_RXPWDDIFF     19
+#define BM_USBPHY_PWD_RXPWDDIFF     0x80000
+#define BF_USBPHY_PWD_RXPWDDIFF(v)  (((v) << 19) & 0x80000)
+#define BP_USBPHY_PWD_RXPWD1PT1     18
+#define BM_USBPHY_PWD_RXPWD1PT1     0x40000
+#define BF_USBPHY_PWD_RXPWD1PT1(v)  (((v) << 18) & 0x40000)
+#define BP_USBPHY_PWD_RXPWDENV      17
+#define BM_USBPHY_PWD_RXPWDENV      0x20000
+#define BF_USBPHY_PWD_RXPWDENV(v)   (((v) << 17) & 0x20000)
+#define BP_USBPHY_PWD_TXPWDCOMP     14
+#define BM_USBPHY_PWD_TXPWDCOMP     0x4000
+#define BF_USBPHY_PWD_TXPWDCOMP(v)  (((v) << 14) & 0x4000)
+#define BP_USBPHY_PWD_TXPWDVBG      13
+#define BM_USBPHY_PWD_TXPWDVBG      0x2000
+#define BF_USBPHY_PWD_TXPWDVBG(v)   (((v) << 13) & 0x2000)
+#define BP_USBPHY_PWD_TXPWDV2I      12
+#define BM_USBPHY_PWD_TXPWDV2I      0x1000
+#define BF_USBPHY_PWD_TXPWDV2I(v)   (((v) << 12) & 0x1000)
+#define BP_USBPHY_PWD_TXPWDIBIAS    11
+#define BM_USBPHY_PWD_TXPWDIBIAS    0x800
+#define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800)
+#define BP_USBPHY_PWD_TXPWDFS       10
+#define BM_USBPHY_PWD_TXPWDFS       0x400
+#define BF_USBPHY_PWD_TXPWDFS(v)    (((v) << 10) & 0x400)
+
+/**
+ * Register: HW_USBPHY_TX
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_USBPHY_TX                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0))
+#define HW_USBPHY_TX_SET                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4))
+#define HW_USBPHY_TX_CLR                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8))
+#define HW_USBPHY_TX_TOG                        (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc))
+#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL         26
+#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL         0x1c000000
+#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v)      (((v) << 26) & 0x1c000000)
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT      25
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT      0x2000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v)   (((v) << 25) & 0x2000000)
+#define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX         24
+#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX         0x1000000
+#define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v)      (((v) << 24) & 0x1000000)
+#define BP_USBPHY_TX_TXCMPOUT_STATUS            23
+#define BM_USBPHY_TX_TXCMPOUT_STATUS            0x800000
+#define BF_USBPHY_TX_TXCMPOUT_STATUS(v)         (((v) << 23) & 0x800000)
+#define BP_USBPHY_TX_TXENCAL45DP                21
+#define BM_USBPHY_TX_TXENCAL45DP                0x200000
+#define BF_USBPHY_TX_TXENCAL45DP(v)             (((v) << 21) & 0x200000)
+#define BP_USBPHY_TX_TXCAL45DP                  16
+#define BM_USBPHY_TX_TXCAL45DP                  0xf0000
+#define BF_USBPHY_TX_TXCAL45DP(v)               (((v) << 16) & 0xf0000)
+#define BP_USBPHY_TX_TXENCAL45DN                13
+#define BM_USBPHY_TX_TXENCAL45DN                0x2000
+#define BF_USBPHY_TX_TXENCAL45DN(v)             (((v) << 13) & 0x2000)
+#define BP_USBPHY_TX_TXCAL45DN                  8
+#define BM_USBPHY_TX_TXCAL45DN                  0xf00
+#define BF_USBPHY_TX_TXCAL45DN(v)               (((v) << 8) & 0xf00)
+#define BP_USBPHY_TX_TXCALIBRATE                7
+#define BM_USBPHY_TX_TXCALIBRATE                0x80
+#define BF_USBPHY_TX_TXCALIBRATE(v)             (((v) << 7) & 0x80)
+#define BP_USBPHY_TX_D_CAL                      0
+#define BM_USBPHY_TX_D_CAL                      0xf
+#define BF_USBPHY_TX_D_CAL(v)                   (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_USBPHY_RX
+ * Address: 0x20
+ * SCT: yes
+*/
+#define HW_USBPHY_RX                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0))
+#define HW_USBPHY_RX_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4))
+#define HW_USBPHY_RX_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8))
+#define HW_USBPHY_RX_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc))
+#define BP_USBPHY_RX_RXDBYPASS      22
+#define BM_USBPHY_RX_RXDBYPASS      0x400000
+#define BF_USBPHY_RX_RXDBYPASS(v)   (((v) << 22) & 0x400000)
+#define BP_USBPHY_RX_DISCONADJ      4
+#define BM_USBPHY_RX_DISCONADJ      0x30
+#define BF_USBPHY_RX_DISCONADJ(v)   (((v) << 4) & 0x30)
+#define BP_USBPHY_RX_ENVADJ         0
+#define BM_USBPHY_RX_ENVADJ         0x3
+#define BF_USBPHY_RX_ENVADJ(v)      (((v) << 0) & 0x3)
+
+/**
+ * Register: HW_USBPHY_CTRL
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_USBPHY_CTRL                          (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0))
+#define HW_USBPHY_CTRL_SET                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4))
+#define HW_USBPHY_CTRL_CLR                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8))
+#define HW_USBPHY_CTRL_TOG                      (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc))
+#define BP_USBPHY_CTRL_SFTRST                   31
+#define BM_USBPHY_CTRL_SFTRST                   0x80000000
+#define BF_USBPHY_CTRL_SFTRST(v)                (((v) << 31) & 0x80000000)
+#define BP_USBPHY_CTRL_CLKGATE                  30
+#define BM_USBPHY_CTRL_CLKGATE                  0x40000000
+#define BF_USBPHY_CTRL_CLKGATE(v)               (((v) << 30) & 0x40000000)
+#define BP_USBPHY_CTRL_UTMI_SUSPENDM            29
+#define BM_USBPHY_CTRL_UTMI_SUSPENDM            0x20000000
+#define BF_USBPHY_CTRL_UTMI_SUSPENDM(v)         (((v) << 29) & 0x20000000)
+#define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0        28
+#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0        0x10000000
+#define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v)     (((v) << 28) & 0x10000000)
+#define BP_USBPHY_CTRL_DATA_ON_LRADC            13
+#define BM_USBPHY_CTRL_DATA_ON_LRADC            0x2000
+#define BF_USBPHY_CTRL_DATA_ON_LRADC(v)         (((v) << 13) & 0x2000)
+#define BP_USBPHY_CTRL_DEVPLUGIN_IRQ            12
+#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ            0x1000
+#define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v)         (((v) << 12) & 0x1000)
+#define BP_USBPHY_CTRL_ENIRQDEVPLUGIN           11
+#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN           0x800
+#define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v)        (((v) << 11) & 0x800)
+#define BP_USBPHY_CTRL_RESUME_IRQ               10
+#define BM_USBPHY_CTRL_RESUME_IRQ               0x400
+#define BF_USBPHY_CTRL_RESUME_IRQ(v)            (((v) << 10) & 0x400)
+#define BP_USBPHY_CTRL_ENIRQRESUMEDETECT        9
+#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT        0x200
+#define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v)     (((v) << 9) & 0x200)
+#define BP_USBPHY_CTRL_ENOTGIDDETECT            7
+#define BM_USBPHY_CTRL_ENOTGIDDETECT            0x80
+#define BF_USBPHY_CTRL_ENOTGIDDETECT(v)         (((v) << 7) & 0x80)
+#define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY       5
+#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY       0x20
+#define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v)    (((v) << 5) & 0x20)
+#define BP_USBPHY_CTRL_ENDEVPLUGINDETECT        4
+#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT        0x10
+#define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v)     (((v) << 4) & 0x10)
+#define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     3
+#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ     0x8
+#define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v)  (((v) << 3) & 0x8)
+#define BP_USBPHY_CTRL_ENIRQHOSTDISCON          2
+#define BM_USBPHY_CTRL_ENIRQHOSTDISCON          0x4
+#define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v)       (((v) << 2) & 0x4)
+#define BP_USBPHY_CTRL_ENHOSTDISCONDETECT       1
+#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT       0x2
+#define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v)    (((v) << 1) & 0x2)
+#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT        0
+#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT        0x1
+#define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v)     (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBPHY_STATUS
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_USBPHY_STATUS                            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40))
+#define BP_USBPHY_STATUS_RESUME_STATUS              10
+#define BM_USBPHY_STATUS_RESUME_STATUS              0x400
+#define BF_USBPHY_STATUS_RESUME_STATUS(v)           (((v) << 10) & 0x400)
+#define BP_USBPHY_STATUS_OTGID_STATUS               8
+#define BM_USBPHY_STATUS_OTGID_STATUS               0x100
+#define BF_USBPHY_STATUS_OTGID_STATUS(v)            (((v) << 8) & 0x100)
+#define BP_USBPHY_STATUS_DEVPLUGIN_STATUS           6
+#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS           0x40
+#define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v)        (((v) << 6) & 0x40)
+#define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    3
+#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS    0x8
+#define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8)
+
+/**
+ * Register: HW_USBPHY_DEBUG
+ * Address: 0x50
+ * SCT: yes
+*/
+#define HW_USBPHY_DEBUG                         (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0))
+#define HW_USBPHY_DEBUG_SET                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4))
+#define HW_USBPHY_DEBUG_CLR                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8))
+#define HW_USBPHY_DEBUG_TOG                     (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc))
+#define BP_USBPHY_DEBUG_CLKGATE                 30
+#define BM_USBPHY_DEBUG_CLKGATE                 0x40000000
+#define BF_USBPHY_DEBUG_CLKGATE(v)              (((v) << 30) & 0x40000000)
+#define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG       29
+#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG       0x20000000
+#define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v)    (((v) << 29) & 0x20000000)
+#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH      25
+#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH      0x1e000000
+#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v)   (((v) << 25) & 0x1e000000)
+#define BP_USBPHY_DEBUG_ENSQUELCHRESET          24
+#define BM_USBPHY_DEBUG_ENSQUELCHRESET          0x1000000
+#define BF_USBPHY_DEBUG_ENSQUELCHRESET(v)       (((v) << 24) & 0x1000000)
+#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT       16
+#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT       0x1f0000
+#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v)    (((v) << 16) & 0x1f0000)
+#define BP_USBPHY_DEBUG_ENTX2RXCOUNT            12
+#define BM_USBPHY_DEBUG_ENTX2RXCOUNT            0x1000
+#define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v)         (((v) << 12) & 0x1000)
+#define BP_USBPHY_DEBUG_TX2RXCOUNT              8
+#define BM_USBPHY_DEBUG_TX2RXCOUNT              0xf00
+#define BF_USBPHY_DEBUG_TX2RXCOUNT(v)           (((v) << 8) & 0xf00)
+#define BP_USBPHY_DEBUG_ENHSTPULLDOWN           4
+#define BM_USBPHY_DEBUG_ENHSTPULLDOWN           0x30
+#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v)        (((v) << 4) & 0x30)
+#define BP_USBPHY_DEBUG_HSTPULLDOWN             2
+#define BM_USBPHY_DEBUG_HSTPULLDOWN             0xc
+#define BF_USBPHY_DEBUG_HSTPULLDOWN(v)          (((v) << 2) & 0xc)
+#define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    1
+#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD    0x2
+#define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2)
+#define BP_USBPHY_DEBUG_OTGIDPIOLOCK            0
+#define BM_USBPHY_DEBUG_OTGIDPIOLOCK            0x1
+#define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v)         (((v) << 0) & 0x1)
+
+/**
+ * Register: HW_USBPHY_DEBUG0_STATUS
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_USBPHY_DEBUG0_STATUS                             (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60))
+#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               26
+#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT               0xfc000000
+#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v)            (((v) << 26) & 0xfc000000)
+#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     16
+#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT     0x3ff0000
+#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v)  (((v) << 16) & 0x3ff0000)
+#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0
+#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT        0xffff
+#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v)     (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_USBPHY_DEBUG1
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_USBPHY_DEBUG1                (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x0))
+#define HW_USBPHY_DEBUG1_SET            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x4))
+#define HW_USBPHY_DEBUG1_CLR            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x8))
+#define HW_USBPHY_DEBUG1_TOG            (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0xc))
+#define BP_USBPHY_DEBUG1_ENTAILADJVD    13
+#define BM_USBPHY_DEBUG1_ENTAILADJVD    0x6000
+#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) (((v) << 13) & 0x6000)
+#define BP_USBPHY_DEBUG1_ENTX2TX        12
+#define BM_USBPHY_DEBUG1_ENTX2TX        0x1000
+#define BF_USBPHY_DEBUG1_ENTX2TX(v)     (((v) << 12) & 0x1000)
+#define BP_USBPHY_DEBUG1_PLL_IS_240     8
+#define BM_USBPHY_DEBUG1_PLL_IS_240     0x100
+#define BF_USBPHY_DEBUG1_PLL_IS_240(v)  (((v) << 8) & 0x100)
+#define BP_USBPHY_DEBUG1_DBG_ADDRESS    0
+#define BM_USBPHY_DEBUG1_DBG_ADDRESS    0xf
+#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) (((v) << 0) & 0xf)
+
+/**
+ * Register: HW_USBPHY_VERSION
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_USBPHY_VERSION           (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80))
+#define BP_USBPHY_VERSION_MAJOR     24
+#define BM_USBPHY_VERSION_MAJOR     0xff000000
+#define BF_USBPHY_VERSION_MAJOR(v)  (((v) << 24) & 0xff000000)
+#define BP_USBPHY_VERSION_MINOR     16
+#define BM_USBPHY_VERSION_MINOR     0xff0000
+#define BF_USBPHY_VERSION_MINOR(v)  (((v) << 16) & 0xff0000)
+#define BP_USBPHY_VERSION_STEP      0
+#define BM_USBPHY_VERSION_STEP      0xffff
+#define BF_USBPHY_VERSION_STEP(v)   (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__USBPHY__H__ */