diff options
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h | 344 |
1 files changed, 344 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h new file mode 100644 index 0000000000..218298b69d --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-clkctrl.h | |||
@@ -0,0 +1,344 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__CLKCTRL__H__ | ||
24 | #define __HEADERGEN__STMP3600__CLKCTRL__H__ | ||
25 | |||
26 | #define REGS_CLKCTRL_BASE (0x80040000) | ||
27 | |||
28 | #define REGS_CLKCTRL_VERSION "2.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_CLKCTRL_PLLCTRL0 | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0)) | ||
36 | #define HW_CLKCTRL_PLLCTRL0_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4)) | ||
37 | #define HW_CLKCTRL_PLLCTRL0_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8)) | ||
38 | #define HW_CLKCTRL_PLLCTRL0_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc)) | ||
39 | #define BP_CLKCTRL_PLLCTRL0_PLLVCOKSTART 30 | ||
40 | #define BM_CLKCTRL_PLLCTRL0_PLLVCOKSTART 0x40000000 | ||
41 | #define BF_CLKCTRL_PLLCTRL0_PLLVCOKSTART(v) (((v) << 30) & 0x40000000) | ||
42 | #define BP_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 29 | ||
43 | #define BM_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR 0x20000000 | ||
44 | #define BF_CLKCTRL_PLLCTRL0_PLLCPSHORTLFR(v) (((v) << 29) & 0x20000000) | ||
45 | #define BP_CLKCTRL_PLLCTRL0_PLLCPDBLIP 28 | ||
46 | #define BM_CLKCTRL_PLLCTRL0_PLLCPDBLIP 0x10000000 | ||
47 | #define BF_CLKCTRL_PLLCTRL0_PLLCPDBLIP(v) (((v) << 28) & 0x10000000) | ||
48 | #define BP_CLKCTRL_PLLCTRL0_PLLCPNSEL 24 | ||
49 | #define BM_CLKCTRL_PLLCTRL0_PLLCPNSEL 0x7000000 | ||
50 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__DEFAULT 0x0 | ||
51 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_15 0x2 | ||
52 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_075 0x3 | ||
53 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_05 0x4 | ||
54 | #define BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__TIMES_04 0x7 | ||
55 | #define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL(v) (((v) << 24) & 0x7000000) | ||
56 | #define BF_CLKCTRL_PLLCTRL0_PLLCPNSEL_V(v) ((BV_CLKCTRL_PLLCTRL0_PLLCPNSEL__##v << 24) & 0x7000000) | ||
57 | #define BP_CLKCTRL_PLLCTRL0_PLLV2ISEL 20 | ||
58 | #define BM_CLKCTRL_PLLCTRL0_PLLV2ISEL 0x300000 | ||
59 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__NORMAL 0x0 | ||
60 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWER 0x1 | ||
61 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__LOWEST 0x2 | ||
62 | #define BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__HIGHEST 0x3 | ||
63 | #define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL(v) (((v) << 20) & 0x300000) | ||
64 | #define BF_CLKCTRL_PLLCTRL0_PLLV2ISEL_V(v) ((BV_CLKCTRL_PLLCTRL0_PLLV2ISEL__##v << 20) & 0x300000) | ||
65 | #define BP_CLKCTRL_PLLCTRL0_FORCE_FREQ 19 | ||
66 | #define BM_CLKCTRL_PLLCTRL0_FORCE_FREQ 0x80000 | ||
67 | #define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__FORCE_SAME_FREQ 0x1 | ||
68 | #define BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__HONOR_SAME_FREQ_RULE 0x0 | ||
69 | #define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ(v) (((v) << 19) & 0x80000) | ||
70 | #define BF_CLKCTRL_PLLCTRL0_FORCE_FREQ_V(v) ((BV_CLKCTRL_PLLCTRL0_FORCE_FREQ__##v << 19) & 0x80000) | ||
71 | #define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 | ||
72 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 | ||
73 | #define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) << 18) & 0x40000) | ||
74 | #define BP_CLKCTRL_PLLCTRL0_BYPASS 17 | ||
75 | #define BM_CLKCTRL_PLLCTRL0_BYPASS 0x20000 | ||
76 | #define BF_CLKCTRL_PLLCTRL0_BYPASS(v) (((v) << 17) & 0x20000) | ||
77 | #define BP_CLKCTRL_PLLCTRL0_POWER 16 | ||
78 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 | ||
79 | #define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) << 16) & 0x10000) | ||
80 | #define BP_CLKCTRL_PLLCTRL0_FREQ 0 | ||
81 | #define BM_CLKCTRL_PLLCTRL0_FREQ 0x1ff | ||
82 | #define BF_CLKCTRL_PLLCTRL0_FREQ(v) (((v) << 0) & 0x1ff) | ||
83 | |||
84 | /** | ||
85 | * Register: HW_CLKCTRL_PLLCTRL1 | ||
86 | * Address: 0x10 | ||
87 | * SCT: yes | ||
88 | */ | ||
89 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x0)) | ||
90 | #define HW_CLKCTRL_PLLCTRL1_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x4)) | ||
91 | #define HW_CLKCTRL_PLLCTRL1_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0x8)) | ||
92 | #define HW_CLKCTRL_PLLCTRL1_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10 + 0xc)) | ||
93 | #define BP_CLKCTRL_PLLCTRL1_LOCK 31 | ||
94 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
95 | #define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) << 31) & 0x80000000) | ||
96 | #define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 | ||
97 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
98 | #define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) << 30) & 0x40000000) | ||
99 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
100 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff | ||
101 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) << 0) & 0xffff) | ||
102 | |||
103 | /** | ||
104 | * Register: HW_CLKCTRL_CPU | ||
105 | * Address: 0x20 | ||
106 | * SCT: no | ||
107 | */ | ||
108 | #define HW_CLKCTRL_CPU (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20)) | ||
109 | #define BP_CLKCTRL_CPU_WAIT_PLL_LOCK 30 | ||
110 | #define BM_CLKCTRL_CPU_WAIT_PLL_LOCK 0x40000000 | ||
111 | #define BF_CLKCTRL_CPU_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
112 | #define BP_CLKCTRL_CPU_BUSY 29 | ||
113 | #define BM_CLKCTRL_CPU_BUSY 0x20000000 | ||
114 | #define BF_CLKCTRL_CPU_BUSY(v) (((v) << 29) & 0x20000000) | ||
115 | #define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 | ||
116 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 | ||
117 | #define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) << 12) & 0x1000) | ||
118 | #define BP_CLKCTRL_CPU_DIV 0 | ||
119 | #define BM_CLKCTRL_CPU_DIV 0x3ff | ||
120 | #define BF_CLKCTRL_CPU_DIV(v) (((v) << 0) & 0x3ff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_CLKCTRL_HBUS | ||
124 | * Address: 0x30 | ||
125 | * SCT: no | ||
126 | */ | ||
127 | #define HW_CLKCTRL_HBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30)) | ||
128 | #define BP_CLKCTRL_HBUS_WAIT_PLL_LOCK 30 | ||
129 | #define BM_CLKCTRL_HBUS_WAIT_PLL_LOCK 0x40000000 | ||
130 | #define BF_CLKCTRL_HBUS_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
131 | #define BP_CLKCTRL_HBUS_BUSY 29 | ||
132 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
133 | #define BF_CLKCTRL_HBUS_BUSY(v) (((v) << 29) & 0x20000000) | ||
134 | #define BP_CLKCTRL_HBUS_EMI_BUSY_FAST 27 | ||
135 | #define BM_CLKCTRL_HBUS_EMI_BUSY_FAST 0x8000000 | ||
136 | #define BF_CLKCTRL_HBUS_EMI_BUSY_FAST(v) (((v) << 27) & 0x8000000) | ||
137 | #define BP_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 26 | ||
138 | #define BM_CLKCTRL_HBUS_APBHDMA_BUSY_FAST 0x4000000 | ||
139 | #define BF_CLKCTRL_HBUS_APBHDMA_BUSY_FAST(v) (((v) << 26) & 0x4000000) | ||
140 | #define BP_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 25 | ||
141 | #define BM_CLKCTRL_HBUS_APBXDMA_BUSY_FAST 0x2000000 | ||
142 | #define BF_CLKCTRL_HBUS_APBXDMA_BUSY_FAST(v) (((v) << 25) & 0x2000000) | ||
143 | #define BP_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 24 | ||
144 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_FAST 0x1000000 | ||
145 | #define BF_CLKCTRL_HBUS_TRAFFIC_JAM_FAST(v) (((v) << 24) & 0x1000000) | ||
146 | #define BP_CLKCTRL_HBUS_TRAFFIC_FAST 23 | ||
147 | #define BM_CLKCTRL_HBUS_TRAFFIC_FAST 0x800000 | ||
148 | #define BF_CLKCTRL_HBUS_TRAFFIC_FAST(v) (((v) << 23) & 0x800000) | ||
149 | #define BP_CLKCTRL_HBUS_CPU_DATA_FAST 22 | ||
150 | #define BM_CLKCTRL_HBUS_CPU_DATA_FAST 0x400000 | ||
151 | #define BF_CLKCTRL_HBUS_CPU_DATA_FAST(v) (((v) << 22) & 0x400000) | ||
152 | #define BP_CLKCTRL_HBUS_CPU_INSTR_FAST 21 | ||
153 | #define BM_CLKCTRL_HBUS_CPU_INSTR_FAST 0x200000 | ||
154 | #define BF_CLKCTRL_HBUS_CPU_INSTR_FAST(v) (((v) << 21) & 0x200000) | ||
155 | #define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 | ||
156 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 | ||
157 | #define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) << 20) & 0x100000) | ||
158 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
159 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x30000 | ||
160 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
161 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
162 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
163 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
164 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) << 16) & 0x30000) | ||
165 | #define BF_CLKCTRL_HBUS_SLOW_DIV_V(v) ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x30000) | ||
166 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
167 | #define BM_CLKCTRL_HBUS_DIV 0x1f | ||
168 | #define BF_CLKCTRL_HBUS_DIV(v) (((v) << 0) & 0x1f) | ||
169 | |||
170 | /** | ||
171 | * Register: HW_CLKCTRL_XBUS | ||
172 | * Address: 0x40 | ||
173 | * SCT: no | ||
174 | */ | ||
175 | #define HW_CLKCTRL_XBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40)) | ||
176 | #define BP_CLKCTRL_XBUS_BUSY 31 | ||
177 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
178 | #define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000) | ||
179 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
180 | #define BM_CLKCTRL_XBUS_DIV 0x3ff | ||
181 | #define BF_CLKCTRL_XBUS_DIV(v) (((v) << 0) & 0x3ff) | ||
182 | |||
183 | /** | ||
184 | * Register: HW_CLKCTRL_XTAL | ||
185 | * Address: 0x50 | ||
186 | * SCT: no | ||
187 | */ | ||
188 | #define HW_CLKCTRL_XTAL (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50)) | ||
189 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
190 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
191 | #define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) << 31) & 0x80000000) | ||
192 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
193 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
194 | #define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) << 30) & 0x40000000) | ||
195 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
196 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
197 | #define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) << 29) & 0x20000000) | ||
198 | #define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 | ||
199 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
200 | #define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) << 28) & 0x10000000) | ||
201 | #define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 | ||
202 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 | ||
203 | #define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) << 27) & 0x8000000) | ||
204 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
205 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 | ||
206 | #define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) << 26) & 0x4000000) | ||
207 | #define BP_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 25 | ||
208 | #define BM_CLKCTRL_XTAL_EXRAM_CLK16K_GATE 0x2000000 | ||
209 | #define BF_CLKCTRL_XTAL_EXRAM_CLK16K_GATE(v) (((v) << 25) & 0x2000000) | ||
210 | #define BP_CLKCTRL_XTAL_LRADC_CLK2K_GATE 24 | ||
211 | #define BM_CLKCTRL_XTAL_LRADC_CLK2K_GATE 0x1000000 | ||
212 | #define BF_CLKCTRL_XTAL_LRADC_CLK2K_GATE(v) (((v) << 24) & 0x1000000) | ||
213 | |||
214 | /** | ||
215 | * Register: HW_CLKCTRL_OCRAM | ||
216 | * Address: 0x60 | ||
217 | * SCT: no | ||
218 | */ | ||
219 | #define HW_CLKCTRL_OCRAM (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60)) | ||
220 | #define BP_CLKCTRL_OCRAM_CLKGATE 31 | ||
221 | #define BM_CLKCTRL_OCRAM_CLKGATE 0x80000000 | ||
222 | #define BF_CLKCTRL_OCRAM_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
223 | #define BP_CLKCTRL_OCRAM_BUSY 30 | ||
224 | #define BM_CLKCTRL_OCRAM_BUSY 0x40000000 | ||
225 | #define BF_CLKCTRL_OCRAM_BUSY(v) (((v) << 30) & 0x40000000) | ||
226 | #define BP_CLKCTRL_OCRAM_DIV 0 | ||
227 | #define BM_CLKCTRL_OCRAM_DIV 0x3ff | ||
228 | #define BF_CLKCTRL_OCRAM_DIV(v) (((v) << 0) & 0x3ff) | ||
229 | |||
230 | /** | ||
231 | * Register: HW_CLKCTRL_UTMI | ||
232 | * Address: 0x70 | ||
233 | * SCT: no | ||
234 | */ | ||
235 | #define HW_CLKCTRL_UTMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70)) | ||
236 | #define BP_CLKCTRL_UTMI_UTMI_CLK120M_GATE 31 | ||
237 | #define BM_CLKCTRL_UTMI_UTMI_CLK120M_GATE 0x80000000 | ||
238 | #define BF_CLKCTRL_UTMI_UTMI_CLK120M_GATE(v) (((v) << 31) & 0x80000000) | ||
239 | #define BP_CLKCTRL_UTMI_UTMI_CLK30M_GATE 30 | ||
240 | #define BM_CLKCTRL_UTMI_UTMI_CLK30M_GATE 0x40000000 | ||
241 | #define BF_CLKCTRL_UTMI_UTMI_CLK30M_GATE(v) (((v) << 30) & 0x40000000) | ||
242 | |||
243 | /** | ||
244 | * Register: HW_CLKCTRL_SSP | ||
245 | * Address: 0x80 | ||
246 | * SCT: no | ||
247 | */ | ||
248 | #define HW_CLKCTRL_SSP (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80)) | ||
249 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
250 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
251 | #define BF_CLKCTRL_SSP_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
252 | #define BP_CLKCTRL_SSP_WAIT_PLL_LOCK 30 | ||
253 | #define BM_CLKCTRL_SSP_WAIT_PLL_LOCK 0x40000000 | ||
254 | #define BF_CLKCTRL_SSP_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
255 | #define BP_CLKCTRL_SSP_BUSY 29 | ||
256 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
257 | #define BF_CLKCTRL_SSP_BUSY(v) (((v) << 29) & 0x20000000) | ||
258 | #define BP_CLKCTRL_SSP_DIV 0 | ||
259 | #define BM_CLKCTRL_SSP_DIV 0x1ff | ||
260 | #define BF_CLKCTRL_SSP_DIV(v) (((v) << 0) & 0x1ff) | ||
261 | |||
262 | /** | ||
263 | * Register: HW_CLKCTRL_GPMI | ||
264 | * Address: 0x90 | ||
265 | * SCT: no | ||
266 | */ | ||
267 | #define HW_CLKCTRL_GPMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90)) | ||
268 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
269 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
270 | #define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
271 | #define BP_CLKCTRL_GPMI_WAIT_PLL_LOCK 30 | ||
272 | #define BM_CLKCTRL_GPMI_WAIT_PLL_LOCK 0x40000000 | ||
273 | #define BF_CLKCTRL_GPMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
274 | #define BP_CLKCTRL_GPMI_BUSY 29 | ||
275 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
276 | #define BF_CLKCTRL_GPMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
277 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
278 | #define BM_CLKCTRL_GPMI_DIV 0x3ff | ||
279 | #define BF_CLKCTRL_GPMI_DIV(v) (((v) << 0) & 0x3ff) | ||
280 | |||
281 | /** | ||
282 | * Register: HW_CLKCTRL_SPDIF | ||
283 | * Address: 0xa0 | ||
284 | * SCT: no | ||
285 | */ | ||
286 | #define HW_CLKCTRL_SPDIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0)) | ||
287 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
288 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
289 | #define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
290 | #define BP_CLKCTRL_SPDIF_BUSY 30 | ||
291 | #define BM_CLKCTRL_SPDIF_BUSY 0x40000000 | ||
292 | #define BF_CLKCTRL_SPDIF_BUSY(v) (((v) << 30) & 0x40000000) | ||
293 | #define BP_CLKCTRL_SPDIF_DIV 0 | ||
294 | #define BM_CLKCTRL_SPDIF_DIV 0x7 | ||
295 | #define BF_CLKCTRL_SPDIF_DIV(v) (((v) << 0) & 0x7) | ||
296 | |||
297 | /** | ||
298 | * Register: HW_CLKCTRL_EMI | ||
299 | * Address: 0xb0 | ||
300 | * SCT: no | ||
301 | */ | ||
302 | #define HW_CLKCTRL_EMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0)) | ||
303 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
304 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
305 | #define BF_CLKCTRL_EMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
306 | #define BP_CLKCTRL_EMI_WAIT_PLL_LOCK 30 | ||
307 | #define BM_CLKCTRL_EMI_WAIT_PLL_LOCK 0x40000000 | ||
308 | #define BF_CLKCTRL_EMI_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
309 | #define BP_CLKCTRL_EMI_BUSY 29 | ||
310 | #define BM_CLKCTRL_EMI_BUSY 0x20000000 | ||
311 | #define BF_CLKCTRL_EMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
312 | #define BP_CLKCTRL_EMI_DIV 0 | ||
313 | #define BM_CLKCTRL_EMI_DIV 0x7 | ||
314 | #define BF_CLKCTRL_EMI_DIV(v) (((v) << 0) & 0x7) | ||
315 | |||
316 | /** | ||
317 | * Register: HW_CLKCTRL_IR | ||
318 | * Address: 0xc0 | ||
319 | * SCT: no | ||
320 | */ | ||
321 | #define HW_CLKCTRL_IR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0)) | ||
322 | #define BP_CLKCTRL_IR_CLKGATE 31 | ||
323 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
324 | #define BF_CLKCTRL_IR_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
325 | #define BP_CLKCTRL_IR_WAIT_PLL_LOCK 30 | ||
326 | #define BM_CLKCTRL_IR_WAIT_PLL_LOCK 0x40000000 | ||
327 | #define BF_CLKCTRL_IR_WAIT_PLL_LOCK(v) (((v) << 30) & 0x40000000) | ||
328 | #define BP_CLKCTRL_IR_AUTO_DIV 29 | ||
329 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
330 | #define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) << 29) & 0x20000000) | ||
331 | #define BP_CLKCTRL_IR_IR_BUSY 28 | ||
332 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
333 | #define BF_CLKCTRL_IR_IR_BUSY(v) (((v) << 28) & 0x10000000) | ||
334 | #define BP_CLKCTRL_IR_IROV_BUSY 27 | ||
335 | #define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 | ||
336 | #define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) << 27) & 0x8000000) | ||
337 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
338 | #define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 | ||
339 | #define BF_CLKCTRL_IR_IROV_DIV(v) (((v) << 16) & 0x1ff0000) | ||
340 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
341 | #define BM_CLKCTRL_IR_IR_DIV 0x3ff | ||
342 | #define BF_CLKCTRL_IR_IR_DIV(v) (((v) << 0) & 0x3ff) | ||
343 | |||
344 | #endif /* __HEADERGEN__STMP3600__CLKCTRL__H__ */ | ||