1 files changed, 886 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h b/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h
new file mode 100644
index 0000000000..2e56999191
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/imx233/regs-lcdif.h
@@ -0,0 +1,886 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: imx233:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__IMX233__LCDIF__H__
+#define __HEADERGEN__IMX233__LCDIF__H__
+#define REGS_LCDIF_BASE (0x80030000)
+#define REGS_LCDIF_VERSION "3.2.0"
+/**
+ * Register: HW_LCDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL                                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
+#define HW_LCDIF_CTRL_SET                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
+#define HW_LCDIF_CTRL_CLR                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
+#define HW_LCDIF_CTRL_TOG                                               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
+#define BP_LCDIF_CTRL_SFTRST                                            31
+#define BM_LCDIF_CTRL_SFTRST                                            0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                                         (((v) << 31) & 0x80000000)
+#define BP_LCDIF_CTRL_CLKGATE                                           30
+#define BM_LCDIF_CTRL_CLKGATE                                           0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                                        (((v) << 30) & 0x40000000)
+#define BP_LCDIF_CTRL_YCBCR422_INPUT                                    29
+#define BM_LCDIF_CTRL_YCBCR422_INPUT                                    0x20000000
+#define BF_LCDIF_CTRL_YCBCR422_INPUT(v)                                 (((v) << 29) & 0x20000000)
+#define BP_LCDIF_CTRL_RSRVD0                                            28
+#define BM_LCDIF_CTRL_RSRVD0                                            0x10000000
+#define BF_LCDIF_CTRL_RSRVD0(v)                                         (((v) << 28) & 0x10000000)
+#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               27
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                               0x8000000
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                            (((v) << 27) & 0x8000000)
+#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                                    26
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                                    0x4000000
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT                 0x0
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT                0x1
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                                 (((v) << 26) & 0x4000000)
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                               ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 26) & 0x4000000)
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                                    21
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                                    0x3e00000
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                                 (((v) << 21) & 0x3e00000)
+#define BP_LCDIF_CTRL_DVI_MODE                                          20
+#define BM_LCDIF_CTRL_DVI_MODE                                          0x100000
+#define BF_LCDIF_CTRL_DVI_MODE(v)                                       (((v) << 20) & 0x100000)
+#define BP_LCDIF_CTRL_BYPASS_COUNT                                      19
+#define BM_LCDIF_CTRL_BYPASS_COUNT                                      0x80000
+#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                                   (((v) << 19) & 0x80000)
+#define BP_LCDIF_CTRL_VSYNC_MODE                                        18
+#define BM_LCDIF_CTRL_VSYNC_MODE                                        0x40000
+#define BF_LCDIF_CTRL_VSYNC_MODE(v)                                     (((v) << 18) & 0x40000)
+#define BP_LCDIF_CTRL_DOTCLK_MODE                                       17
+#define BM_LCDIF_CTRL_DOTCLK_MODE                                       0x20000
+#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                                    (((v) << 17) & 0x20000)
+#define BP_LCDIF_CTRL_DATA_SELECT                                       16
+#define BM_LCDIF_CTRL_DATA_SELECT                                       0x10000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                             0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                            0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                                    (((v) << 16) & 0x10000)
+#define BF_LCDIF_CTRL_DATA_SELECT_V(v)                                  ((BV_LCDIF_CTRL_DATA_SELECT__##v << 16) & 0x10000)
+#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                14
+#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE                                0xc000
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP                       0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN                 0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP               0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES                0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP                      0x2
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP                 0x3
+#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v)                             (((v) << 14) & 0xc000)
+#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE_V(v)                           ((BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__##v << 14) & 0xc000)
+#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  12
+#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE                                  0x3000
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP                         0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN                   0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP                 0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES                  0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP                        0x2
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP                   0x3
+#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v)                               (((v) << 12) & 0x3000)
+#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE_V(v)                             ((BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__##v << 12) & 0x3000)
+#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 10
+#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH                                 0xc00
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT                         0x0
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT                          0x1
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT                         0x2
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT                         0x3
+#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v)                              (((v) << 10) & 0xc00)
+#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH_V(v)                            ((BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__##v << 10) & 0xc00)
+#define BP_LCDIF_CTRL_WORD_LENGTH                                       8
+#define BM_LCDIF_CTRL_WORD_LENGTH                                       0x300
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                               0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                                0x1
+#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT                               0x2
+#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT                               0x3
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                                    (((v) << 8) & 0x300)
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)                                  ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 8) & 0x300)
+#define BP_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               7
+#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC                               0x80
+#define BF_LCDIF_CTRL_RGB_TO_YCBCR422_CSC(v)                            (((v) << 7) & 0x80)
+#define BP_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              6
+#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE                              0x40
+#define BF_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(v)                           (((v) << 6) & 0x40)
+#define BP_LCDIF_CTRL_LCDIF_MASTER                                      5
+#define BM_LCDIF_CTRL_LCDIF_MASTER                                      0x20
+#define BF_LCDIF_CTRL_LCDIF_MASTER(v)                                   (((v) << 5) & 0x20)
+#define BP_LCDIF_CTRL_DMA_BURST_LENGTH                                  4
+#define BM_LCDIF_CTRL_DMA_BURST_LENGTH                                  0x10
+#define BF_LCDIF_CTRL_DMA_BURST_LENGTH(v)                               (((v) << 4) & 0x10)
+#define BP_LCDIF_CTRL_DATA_FORMAT_16_BIT                                3
+#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT                                0x8
+#define BF_LCDIF_CTRL_DATA_FORMAT_16_BIT(v)                             (((v) << 3) & 0x8)
+#define BP_LCDIF_CTRL_DATA_FORMAT_18_BIT                                2
+#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT                                0x4
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID           0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID           0x1
+#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT(v)                             (((v) << 2) & 0x4)
+#define BF_LCDIF_CTRL_DATA_FORMAT_18_BIT_V(v)                           ((BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__##v << 2) & 0x4)
+#define BP_LCDIF_CTRL_DATA_FORMAT_24_BIT                                1
+#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT                                0x2
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID             0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE    0x1
+#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT(v)                             (((v) << 1) & 0x2)
+#define BF_LCDIF_CTRL_DATA_FORMAT_24_BIT_V(v)                           ((BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__##v << 1) & 0x2)
+#define BP_LCDIF_CTRL_RUN                                               0
+#define BM_LCDIF_CTRL_RUN                                               0x1
+#define BF_LCDIF_CTRL_RUN(v)                                            (((v) << 0) & 0x1)
+/**
+ * Register: HW_LCDIF_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL1                                      (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0))
+#define HW_LCDIF_CTRL1_SET                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4))
+#define HW_LCDIF_CTRL1_CLR                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8))
+#define HW_LCDIF_CTRL1_TOG                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc))
+#define BP_LCDIF_CTRL1_RSRVD1                               27
+#define BM_LCDIF_CTRL1_RSRVD1                               0xf8000000
+#define BF_LCDIF_CTRL1_RSRVD1(v)                            (((v) << 27) & 0xf8000000)
+#define BP_LCDIF_CTRL1_BM_ERROR_IRQ_EN                      26
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN                      0x4000000
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_EN(v)                   (((v) << 26) & 0x4000000)
+#define BP_LCDIF_CTRL1_BM_ERROR_IRQ                         25
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ                         0x2000000
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST             0x0
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST                0x1
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ(v)                      (((v) << 25) & 0x2000000)
+#define BF_LCDIF_CTRL1_BM_ERROR_IRQ_V(v)                    ((BV_LCDIF_CTRL1_BM_ERROR_IRQ__##v << 25) & 0x2000000)
+#define BP_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                 24
+#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW                 0x1000000
+#define BF_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(v)              (((v) << 24) & 0x1000000)
+#define BP_LCDIF_CTRL1_INTERLACE_FIELDS                     23
+#define BM_LCDIF_CTRL1_INTERLACE_FIELDS                     0x800000
+#define BF_LCDIF_CTRL1_INTERLACE_FIELDS(v)                  (((v) << 23) & 0x800000)
+#define BP_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD    22
+#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD    0x400000
+#define BF_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(v) (((v) << 22) & 0x400000)
+#define BP_LCDIF_CTRL1_FIFO_CLEAR                           21
+#define BM_LCDIF_CTRL1_FIFO_CLEAR                           0x200000
+#define BF_LCDIF_CTRL1_FIFO_CLEAR(v)                        (((v) << 21) & 0x200000)
+#define BP_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS              20
+#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS              0x100000
+#define BF_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(v)           (((v) << 20) & 0x100000)
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  16
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT                  0xf0000
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)               (((v) << 16) & 0xf0000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      15
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                      0x8000
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)                   (((v) << 15) & 0x8000)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     14
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                     0x4000
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)                  (((v) << 14) & 0x4000)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                13
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN                0x2000
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)             (((v) << 13) & 0x2000)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    12
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                    0x1000
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)                 (((v) << 12) & 0x1000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                         11
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                         0x800
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST             0x0
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST                0x1
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                      (((v) << 11) & 0x800)
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                    ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                        10
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                        0x400
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST            0x0
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST               0x1
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                     (((v) << 10) & 0x400)
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)                   ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   9
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ                   0x200
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST       0x0
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST          0x1
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)                (((v) << 9) & 0x200)
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)              ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       8
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                       0x100
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST           0x0
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST              0x1
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                    (((v) << 8) & 0x100)
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)                  ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100)
+#define BP_LCDIF_CTRL1_RSRVD0                               7
+#define BM_LCDIF_CTRL1_RSRVD0                               0x80
+#define BF_LCDIF_CTRL1_RSRVD0(v)                            (((v) << 7) & 0x80)
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER                       6
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER                       0x40
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER(v)                    (((v) << 6) & 0x40)
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                5
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN                0x20
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN(v)             (((v) << 5) & 0x20)
+#define BP_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                   4
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ                   0x10
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST       0x0
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST          0x1
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ(v)                (((v) << 4) & 0x10)
+#define BF_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_V(v)              ((BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__##v << 4) & 0x10)
+#define BP_LCDIF_CTRL1_LCD_CS_CTRL                          3
+#define BM_LCDIF_CTRL1_LCD_CS_CTRL                          0x8
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                       (((v) << 3) & 0x8)
+#define BP_LCDIF_CTRL1_BUSY_ENABLE                          2
+#define BM_LCDIF_CTRL1_BUSY_ENABLE                          0x4
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED           0x0
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED            0x1
+#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                       (((v) << 2) & 0x4)
+#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v)                     ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4)
+#define BP_LCDIF_CTRL1_MODE86                               1
+#define BM_LCDIF_CTRL1_MODE86                               0x2
+#define BV_LCDIF_CTRL1_MODE86__8080_MODE                    0x0
+#define BV_LCDIF_CTRL1_MODE86__6800_MODE                    0x1
+#define BF_LCDIF_CTRL1_MODE86(v)                            (((v) << 1) & 0x2)
+#define BF_LCDIF_CTRL1_MODE86_V(v)                          ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2)
+#define BP_LCDIF_CTRL1_RESET                                0
+#define BM_LCDIF_CTRL1_RESET                                0x1
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW                  0x0
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH                 0x1
+#define BF_LCDIF_CTRL1_RESET(v)                             (((v) << 0) & 0x1)
+#define BF_LCDIF_CTRL1_RESET_V(v)                           ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1)
+/**
+ * Register: HW_LCDIF_TRANSFER_COUNT
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_LCDIF_TRANSFER_COUNT             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
+#define BP_LCDIF_TRANSFER_COUNT_V_COUNT     16
+#define BM_LCDIF_TRANSFER_COUNT_V_COUNT     0xffff0000
+#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v)  (((v) << 16) & 0xffff0000)
+#define BP_LCDIF_TRANSFER_COUNT_H_COUNT     0
+#define BM_LCDIF_TRANSFER_COUNT_H_COUNT     0xffff
+#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v)  (((v) << 0) & 0xffff)
+/**
+ * Register: HW_LCDIF_CUR_BUF
+ * Address: 0x30
+ * SCT: no
+*/
+#define HW_LCDIF_CUR_BUF            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30))
+#define BP_LCDIF_CUR_BUF_ADDR       0
+#define BM_LCDIF_CUR_BUF_ADDR       0xffffffff
+#define BF_LCDIF_CUR_BUF_ADDR(v)    (((v) << 0) & 0xffffffff)
+/**
+ * Register: HW_LCDIF_NEXT_BUF
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_LCDIF_NEXT_BUF           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40))
+#define BP_LCDIF_NEXT_BUF_ADDR      0
+#define BM_LCDIF_NEXT_BUF_ADDR      0xffffffff
+#define BF_LCDIF_NEXT_BUF_ADDR(v)   (((v) << 0) & 0xffffffff)
+/**
+ * Register: HW_LCDIF_PAGETABLE
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_LCDIF_PAGETABLE              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50))
+#define BP_LCDIF_PAGETABLE_BASE         14
+#define BM_LCDIF_PAGETABLE_BASE         0xffffc000
+#define BF_LCDIF_PAGETABLE_BASE(v)      (((v) << 14) & 0xffffc000)
+#define BP_LCDIF_PAGETABLE_RSVD1        2
+#define BM_LCDIF_PAGETABLE_RSVD1        0x3ffc
+#define BF_LCDIF_PAGETABLE_RSVD1(v)     (((v) << 2) & 0x3ffc)
+#define BP_LCDIF_PAGETABLE_FLUSH        1
+#define BM_LCDIF_PAGETABLE_FLUSH        0x2
+#define BF_LCDIF_PAGETABLE_FLUSH(v)     (((v) << 1) & 0x2)
+#define BP_LCDIF_PAGETABLE_ENABLE       0
+#define BM_LCDIF_PAGETABLE_ENABLE       0x1
+#define BF_LCDIF_PAGETABLE_ENABLE(v)    (((v) << 0) & 0x1)
+/**
+ * Register: HW_LCDIF_TIMING
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60))
+#define BP_LCDIF_TIMING_CMD_HOLD        24
+#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
+#define BP_LCDIF_TIMING_CMD_SETUP       16
+#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_LCDIF_TIMING_DATA_HOLD       8
+#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_LCDIF_TIMING_DATA_SETUP      0
+#define BM_LCDIF_TIMING_DATA_SETUP      0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
+/**
+ * Register: HW_LCDIF_VDCTRL0
+ * Address: 0x70
+ * SCT: yes
+*/
+#define HW_LCDIF_VDCTRL0                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x0))
+#define HW_LCDIF_VDCTRL0_SET                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x4))
+#define HW_LCDIF_VDCTRL0_CLR                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0x8))
+#define HW_LCDIF_VDCTRL0_TOG                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70 + 0xc))
+#define BP_LCDIF_VDCTRL0_RSRVD2                     30
+#define BM_LCDIF_VDCTRL0_RSRVD2                     0xc0000000
+#define BF_LCDIF_VDCTRL0_RSRVD2(v)                  (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_OEB                  29
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB                  0x20000000
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT    0x0
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT     0x1
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)               (((v) << 29) & 0x20000000)
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v)             ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT             28
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT             0x10000000
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)          (((v) << 28) & 0x10000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_POL                  27
+#define BM_LCDIF_VDCTRL0_VSYNC_POL                  0x8000000
+#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)               (((v) << 27) & 0x8000000)
+#define BP_LCDIF_VDCTRL0_HSYNC_POL                  26
+#define BM_LCDIF_VDCTRL0_HSYNC_POL                  0x4000000
+#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)               (((v) << 26) & 0x4000000)
+#define BP_LCDIF_VDCTRL0_DOTCLK_POL                 25
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL                 0x2000000
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)              (((v) << 25) & 0x2000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_POL                 24
+#define BM_LCDIF_VDCTRL0_ENABLE_POL                 0x1000000
+#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)              (((v) << 24) & 0x1000000)
+#define BP_LCDIF_VDCTRL0_RSRVD1                     22
+#define BM_LCDIF_VDCTRL0_RSRVD1                     0xc00000
+#define BF_LCDIF_VDCTRL0_RSRVD1(v)                  (((v) << 22) & 0xc00000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          21
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          0x200000
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)       (((v) << 21) & 0x200000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     20
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     0x100000
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)  (((v) << 20) & 0x100000)
+#define BP_LCDIF_VDCTRL0_HALF_LINE                  19
+#define BM_LCDIF_VDCTRL0_HALF_LINE                  0x80000
+#define BF_LCDIF_VDCTRL0_HALF_LINE(v)               (((v) << 19) & 0x80000)
+#define BP_LCDIF_VDCTRL0_HALF_LINE_MODE             18
+#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE             0x40000
+#define BF_LCDIF_VDCTRL0_HALF_LINE_MODE(v)          (((v) << 18) & 0x40000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH          0
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH          0x3ffff
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v)       (((v) << 0) & 0x3ffff)
+/**
+ * Register: HW_LCDIF_VDCTRL1
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL1                    (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80))
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD       0
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD       0xffffffff
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)    (((v) << 0) & 0xffffffff)
+/**
+ * Register: HW_LCDIF_VDCTRL2
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL2                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90))
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      24
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH      0xff000000
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_VDCTRL2_RSRVD0                 18
+#define BM_LCDIF_VDCTRL2_RSRVD0                 0xfc0000
+#define BF_LCDIF_VDCTRL2_RSRVD0(v)              (((v) << 18) & 0xfc0000)
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD           0
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD           0x3ffff
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)        (((v) << 0) & 0x3ffff)
+/**
+ * Register: HW_LCDIF_VDCTRL3
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL3                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0))
+#define BP_LCDIF_VDCTRL3_RSRVD0                 30
+#define BM_LCDIF_VDCTRL3_RSRVD0                 0xc0000000
+#define BF_LCDIF_VDCTRL3_RSRVD0(v)              (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS       29
+#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS       0x20000000
+#define BF_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(v)    (((v) << 29) & 0x20000000)
+#define BP_LCDIF_VDCTRL3_VSYNC_ONLY             28
+#define BM_LCDIF_VDCTRL3_VSYNC_ONLY             0x10000000
+#define BF_LCDIF_VDCTRL3_VSYNC_ONLY(v)          (((v) << 28) & 0x10000000)
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    16
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0xfff0000
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 16) & 0xfff0000)
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0xffff
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)   (((v) << 0) & 0xffff)
+/**
+ * Register: HW_LCDIF_VDCTRL4
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL4                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0))
+#define BP_LCDIF_VDCTRL4_RSRVD0                     19
+#define BM_LCDIF_VDCTRL4_RSRVD0                     0xfff80000
+#define BF_LCDIF_VDCTRL4_RSRVD0(v)                  (((v) << 19) & 0xfff80000)
+#define BP_LCDIF_VDCTRL4_SYNC_SIGNALS_ON            18
+#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON            0x40000
+#define BF_LCDIF_VDCTRL4_SYNC_SIGNALS_ON(v)         (((v) << 18) & 0x40000)
+#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT    0
+#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT    0x3ffff
+#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x3ffff)
+/**
+ * Register: HW_LCDIF_DVICTRL0
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL0                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0))
+#define BP_LCDIF_DVICTRL0_START_TRS         31
+#define BM_LCDIF_DVICTRL0_START_TRS         0x80000000
+#define BF_LCDIF_DVICTRL0_START_TRS(v)      (((v) << 31) & 0x80000000)
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT      20
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT      0x7ff00000
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)   (((v) << 20) & 0x7ff00000)
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT    10
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT    0xffc00
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT       0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT       0x3ff
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)    (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_DVICTRL1
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL1                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0))
+#define BP_LCDIF_DVICTRL1_RSRVD0            30
+#define BM_LCDIF_DVICTRL1_RSRVD0            0xc0000000
+#define BF_LCDIF_DVICTRL1_RSRVD0(v)         (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_DVICTRL1_F1_START_LINE     20
+#define BM_LCDIF_DVICTRL1_F1_START_LINE     0x3ff00000
+#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)  (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL1_F1_END_LINE       10
+#define BM_LCDIF_DVICTRL1_F1_END_LINE       0xffc00
+#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL1_F2_START_LINE     0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE     0x3ff
+#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)  (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_DVICTRL2
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL2                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0))
+#define BP_LCDIF_DVICTRL2_RSRVD0                    30
+#define BM_LCDIF_DVICTRL2_RSRVD0                    0xc0000000
+#define BF_LCDIF_DVICTRL2_RSRVD0(v)                 (((v) << 30) & 0xc0000000)
+#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
+#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
+#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_DVICTRL3
+ * Address: 0xf0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL3                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xf0))
+#define BP_LCDIF_DVICTRL3_RSRVD1                    26
+#define BM_LCDIF_DVICTRL3_RSRVD1                    0xfc000000
+#define BF_LCDIF_DVICTRL3_RSRVD1(v)                 (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_DVICTRL3_RSRVD0                    10
+#define BM_LCDIF_DVICTRL3_RSRVD0                    0xfc00
+#define BF_LCDIF_DVICTRL3_RSRVD0(v)                 (((v) << 10) & 0xfc00)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_DVICTRL4
+ * Address: 0x100
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL4                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x100))
+#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE      24
+#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE      0xff000000
+#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE     16
+#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE     0xff0000
+#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v)  (((v) << 16) & 0xff0000)
+#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE     8
+#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE     0xff00
+#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v)  (((v) << 8) & 0xff00)
+#define BP_LCDIF_DVICTRL4_H_FILL_CNT        0
+#define BM_LCDIF_DVICTRL4_H_FILL_CNT        0xff
+#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v)     (((v) << 0) & 0xff)
+/**
+ * Register: HW_LCDIF_CSC_COEFF0
+ * Address: 0x110
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF0                                         (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x110))
+#define BP_LCDIF_CSC_COEFF0_RSRVD1                                  26
+#define BM_LCDIF_CSC_COEFF0_RSRVD1                                  0xfc000000
+#define BF_LCDIF_CSC_COEFF0_RSRVD1(v)                               (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF0_C0                                      16
+#define BM_LCDIF_CSC_COEFF0_C0                                      0x3ff0000
+#define BF_LCDIF_CSC_COEFF0_C0(v)                                   (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF0_RSRVD0                                  2
+#define BM_LCDIF_CSC_COEFF0_RSRVD0                                  0xfffc
+#define BF_LCDIF_CSC_COEFF0_RSRVD0(v)                               (((v) << 2) & 0xfffc)
+#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0
+#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER                    0x3
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD   0x0
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD             0x1
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL      0x2
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED           0x3
+#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v)                 (((v) << 0) & 0x3)
+#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_V(v)               ((BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__##v << 0) & 0x3)
+/**
+ * Register: HW_LCDIF_CSC_COEFF1
+ * Address: 0x120
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF1             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x120))
+#define BP_LCDIF_CSC_COEFF1_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF1_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF1_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF1_C2          16
+#define BM_LCDIF_CSC_COEFF1_C2          0x3ff0000
+#define BF_LCDIF_CSC_COEFF1_C2(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF1_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF1_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF1_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF1_C1          0
+#define BM_LCDIF_CSC_COEFF1_C1          0x3ff
+#define BF_LCDIF_CSC_COEFF1_C1(v)       (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_CSC_COEFF2
+ * Address: 0x130
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF2             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x130))
+#define BP_LCDIF_CSC_COEFF2_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF2_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF2_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF2_C4          16
+#define BM_LCDIF_CSC_COEFF2_C4          0x3ff0000
+#define BF_LCDIF_CSC_COEFF2_C4(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF2_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF2_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF2_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF2_C3          0
+#define BM_LCDIF_CSC_COEFF2_C3          0x3ff
+#define BF_LCDIF_CSC_COEFF2_C3(v)       (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_CSC_COEFF3
+ * Address: 0x140
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF3             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x140))
+#define BP_LCDIF_CSC_COEFF3_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF3_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF3_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF3_C6          16
+#define BM_LCDIF_CSC_COEFF3_C6          0x3ff0000
+#define BF_LCDIF_CSC_COEFF3_C6(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF3_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF3_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF3_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF3_C5          0
+#define BM_LCDIF_CSC_COEFF3_C5          0x3ff
+#define BF_LCDIF_CSC_COEFF3_C5(v)       (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_CSC_COEFF4
+ * Address: 0x150
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_COEFF4             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x150))
+#define BP_LCDIF_CSC_COEFF4_RSRVD1      26
+#define BM_LCDIF_CSC_COEFF4_RSRVD1      0xfc000000
+#define BF_LCDIF_CSC_COEFF4_RSRVD1(v)   (((v) << 26) & 0xfc000000)
+#define BP_LCDIF_CSC_COEFF4_C8          16
+#define BM_LCDIF_CSC_COEFF4_C8          0x3ff0000
+#define BF_LCDIF_CSC_COEFF4_C8(v)       (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_CSC_COEFF4_RSRVD0      10
+#define BM_LCDIF_CSC_COEFF4_RSRVD0      0xfc00
+#define BF_LCDIF_CSC_COEFF4_RSRVD0(v)   (((v) << 10) & 0xfc00)
+#define BP_LCDIF_CSC_COEFF4_C7          0
+#define BM_LCDIF_CSC_COEFF4_C7          0x3ff
+#define BF_LCDIF_CSC_COEFF4_C7(v)       (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_CSC_OFFSET
+ * Address: 0x160
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_OFFSET                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x160))
+#define BP_LCDIF_CSC_OFFSET_RSRVD1          25
+#define BM_LCDIF_CSC_OFFSET_RSRVD1          0xfe000000
+#define BF_LCDIF_CSC_OFFSET_RSRVD1(v)       (((v) << 25) & 0xfe000000)
+#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET     16
+#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET     0x1ff0000
+#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v)  (((v) << 16) & 0x1ff0000)
+#define BP_LCDIF_CSC_OFFSET_RSRVD0          9
+#define BM_LCDIF_CSC_OFFSET_RSRVD0          0xfe00
+#define BF_LCDIF_CSC_OFFSET_RSRVD0(v)       (((v) << 9) & 0xfe00)
+#define BP_LCDIF_CSC_OFFSET_Y_OFFSET        0
+#define BM_LCDIF_CSC_OFFSET_Y_OFFSET        0x1ff
+#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v)     (((v) << 0) & 0x1ff)
+/**
+ * Register: HW_LCDIF_CSC_LIMIT
+ * Address: 0x170
+ * SCT: no
+*/
+#define HW_LCDIF_CSC_LIMIT              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x170))
+#define BP_LCDIF_CSC_LIMIT_CBCR_MIN     24
+#define BM_LCDIF_CSC_LIMIT_CBCR_MIN     0xff000000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v)  (((v) << 24) & 0xff000000)
+#define BP_LCDIF_CSC_LIMIT_CBCR_MAX     16
+#define BM_LCDIF_CSC_LIMIT_CBCR_MAX     0xff0000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v)  (((v) << 16) & 0xff0000)
+#define BP_LCDIF_CSC_LIMIT_Y_MIN        8
+#define BM_LCDIF_CSC_LIMIT_Y_MIN        0xff00
+#define BF_LCDIF_CSC_LIMIT_Y_MIN(v)     (((v) << 8) & 0xff00)
+#define BP_LCDIF_CSC_LIMIT_Y_MAX        0
+#define BM_LCDIF_CSC_LIMIT_Y_MAX        0xff
+#define BF_LCDIF_CSC_LIMIT_Y_MAX(v)     (((v) << 0) & 0xff)
+/**
+ * Register: HW_LCDIF_PIN_SHARING_CTRL0
+ * Address: 0x180
+ * SCT: yes
+*/
+#define HW_LCDIF_PIN_SHARING_CTRL0                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x0))
+#define HW_LCDIF_PIN_SHARING_CTRL0_SET                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x4))
+#define HW_LCDIF_PIN_SHARING_CTRL0_CLR                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0x8))
+#define HW_LCDIF_PIN_SHARING_CTRL0_TOG                          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x180 + 0xc))
+#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       6
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1                       0xffffffc0
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v)                    (((v) << 6) & 0xffffffc0)
+#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 4
+#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE                 0x30
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE    0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD          0x1
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL      0x2
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL       0x3
+#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v)              (((v) << 4) & 0x30)
+#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE_V(v)            ((BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__##v << 4) & 0x30)
+#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       3
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0                       0x8
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD0(v)                    (((v) << 3) & 0x8)
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           2
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN           0x4
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN(v)        (((v) << 2) & 0x4)
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              1
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ              0x2
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST  0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST     0x1
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ(v)           (((v) << 1) & 0x2)
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_V(v)         ((BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__##v << 1) & 0x2)
+#define BP_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE           0x1
+#define BF_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE(v)        (((v) << 0) & 0x1)
+/**
+ * Register: HW_LCDIF_PIN_SHARING_CTRL1
+ * Address: 0x190
+ * SCT: no
+*/
+#define HW_LCDIF_PIN_SHARING_CTRL1                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x190))
+#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0
+#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1       0xffffffff
+#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v)    (((v) << 0) & 0xffffffff)
+/**
+ * Register: HW_LCDIF_PIN_SHARING_CTRL2
+ * Address: 0x1a0
+ * SCT: no
+*/
+#define HW_LCDIF_PIN_SHARING_CTRL2                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1a0))
+#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0
+#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2       0xffffffff
+#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v)    (((v) << 0) & 0xffffffff)
+/**
+ * Register: HW_LCDIF_DATA
+ * Address: 0x1b0
+ * SCT: no
+*/
+#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1b0))
+#define BP_LCDIF_DATA_DATA_THREE    24
+#define BM_LCDIF_DATA_DATA_THREE    0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
+#define BP_LCDIF_DATA_DATA_TWO      16
+#define BM_LCDIF_DATA_DATA_TWO      0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_DATA_DATA_ONE      8
+#define BM_LCDIF_DATA_DATA_ONE      0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
+#define BP_LCDIF_DATA_DATA_ZERO     0
+#define BM_LCDIF_DATA_DATA_ZERO     0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
+/**
+ * Register: HW_LCDIF_BM_ERROR_STAT
+ * Address: 0x1c0
+ * SCT: no
+*/
+#define HW_LCDIF_BM_ERROR_STAT          (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1c0))
+#define BP_LCDIF_BM_ERROR_STAT_ADDR     0
+#define BM_LCDIF_BM_ERROR_STAT_ADDR     0xffffffff
+#define BF_LCDIF_BM_ERROR_STAT_ADDR(v)  (((v) << 0) & 0xffffffff)
+/**
+ * Register: HW_LCDIF_STAT
+ * Address: 0x1d0
+ * SCT: no
+*/
+#define HW_LCDIF_STAT                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1d0))
+#define BP_LCDIF_STAT_PRESENT               31
+#define BM_LCDIF_STAT_PRESENT               0x80000000
+#define BF_LCDIF_STAT_PRESENT(v)            (((v) << 31) & 0x80000000)
+#define BP_LCDIF_STAT_DMA_REQ               30
+#define BM_LCDIF_STAT_DMA_REQ               0x40000000
+#define BF_LCDIF_STAT_DMA_REQ(v)            (((v) << 30) & 0x40000000)
+#define BP_LCDIF_STAT_LFIFO_FULL            29
+#define BM_LCDIF_STAT_LFIFO_FULL            0x20000000
+#define BF_LCDIF_STAT_LFIFO_FULL(v)         (((v) << 29) & 0x20000000)
+#define BP_LCDIF_STAT_LFIFO_EMPTY           28
+#define BM_LCDIF_STAT_LFIFO_EMPTY           0x10000000
+#define BF_LCDIF_STAT_LFIFO_EMPTY(v)        (((v) << 28) & 0x10000000)
+#define BP_LCDIF_STAT_TXFIFO_FULL           27
+#define BM_LCDIF_STAT_TXFIFO_FULL           0x8000000
+#define BF_LCDIF_STAT_TXFIFO_FULL(v)        (((v) << 27) & 0x8000000)
+#define BP_LCDIF_STAT_TXFIFO_EMPTY          26
+#define BM_LCDIF_STAT_TXFIFO_EMPTY          0x4000000
+#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)       (((v) << 26) & 0x4000000)
+#define BP_LCDIF_STAT_BUSY                  25
+#define BM_LCDIF_STAT_BUSY                  0x2000000
+#define BF_LCDIF_STAT_BUSY(v)               (((v) << 25) & 0x2000000)
+#define BP_LCDIF_STAT_DVI_CURRENT_FIELD     24
+#define BM_LCDIF_STAT_DVI_CURRENT_FIELD     0x1000000
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)  (((v) << 24) & 0x1000000)
+#define BP_LCDIF_STAT_RSRVD0                0
+#define BM_LCDIF_STAT_RSRVD0                0xffffff
+#define BF_LCDIF_STAT_RSRVD0(v)             (((v) << 0) & 0xffffff)
+/**
+ * Register: HW_LCDIF_VERSION
+ * Address: 0x1e0
+ * SCT: no
+*/
+#define HW_LCDIF_VERSION            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1e0))
+#define BP_LCDIF_VERSION_MAJOR      24
+#define BM_LCDIF_VERSION_MAJOR      0xff000000
+#define BF_LCDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_VERSION_MINOR      16
+#define BM_LCDIF_VERSION_MINOR      0xff0000
+#define BF_LCDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_VERSION_STEP       0
+#define BM_LCDIF_VERSION_STEP       0xffff
+#define BF_LCDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+/**
+ * Register: HW_LCDIF_DEBUG0
+ * Address: 0x1f0
+ * SCT: no
+*/
+#define HW_LCDIF_DEBUG0                             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x1f0))
+#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED      31
+#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED      0x80000000
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)   (((v) << 31) & 0x80000000)
+#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     30
+#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     0x40000000
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)  (((v) << 30) & 0x40000000)
+#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         29
+#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         0x20000000
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)      (((v) << 29) & 0x20000000)
+#define BP_LCDIF_DEBUG0_DMACMDKICK                  28
+#define BM_LCDIF_DEBUG0_DMACMDKICK                  0x10000000
+#define BF_LCDIF_DEBUG0_DMACMDKICK(v)               (((v) << 28) & 0x10000000)
+#define BP_LCDIF_DEBUG0_ENABLE                      27
+#define BM_LCDIF_DEBUG0_ENABLE                      0x8000000
+#define BF_LCDIF_DEBUG0_ENABLE(v)                   (((v) << 27) & 0x8000000)
+#define BP_LCDIF_DEBUG0_HSYNC                       26
+#define BM_LCDIF_DEBUG0_HSYNC                       0x4000000
+#define BF_LCDIF_DEBUG0_HSYNC(v)                    (((v) << 26) & 0x4000000)
+#define BP_LCDIF_DEBUG0_VSYNC                       25
+#define BM_LCDIF_DEBUG0_VSYNC                       0x2000000
+#define BF_LCDIF_DEBUG0_VSYNC(v)                    (((v) << 25) & 0x2000000)
+#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                24
+#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                0x1000000
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)             (((v) << 24) & 0x1000000)
+#define BP_LCDIF_DEBUG0_EMPTY_WORD                  23
+#define BM_LCDIF_DEBUG0_EMPTY_WORD                  0x800000
+#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)               (((v) << 23) & 0x800000)
+#define BP_LCDIF_DEBUG0_CUR_STATE                   16
+#define BM_LCDIF_DEBUG0_CUR_STATE                   0x7f0000
+#define BF_LCDIF_DEBUG0_CUR_STATE(v)                (((v) << 16) & 0x7f0000)
+#define BP_LCDIF_DEBUG0_PXP_LCDIF_B0_READY          15
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY          0x8000
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B0_READY(v)       (((v) << 15) & 0x8000)
+#define BP_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE           14
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE           0x4000
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE(v)        (((v) << 14) & 0x4000)
+#define BP_LCDIF_DEBUG0_PXP_LCDIF_B1_READY          13
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY          0x2000
+#define BF_LCDIF_DEBUG0_PXP_LCDIF_B1_READY(v)       (((v) << 13) & 0x2000)
+#define BP_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE           12
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE           0x1000
+#define BF_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE(v)        (((v) << 12) & 0x1000)
+#define BP_LCDIF_DEBUG0_GPMI_LCDIF_REQ              11
+#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ              0x800
+#define BF_LCDIF_DEBUG0_GPMI_LCDIF_REQ(v)           (((v) << 11) & 0x800)
+#define BP_LCDIF_DEBUG0_LCDIF_GPMI_GRANT            10
+#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT            0x400
+#define BF_LCDIF_DEBUG0_LCDIF_GPMI_GRANT(v)         (((v) << 10) & 0x400)
+#define BP_LCDIF_DEBUG0_RSRVD0                      0
+#define BM_LCDIF_DEBUG0_RSRVD0                      0x3ff
+#define BF_LCDIF_DEBUG0_RSRVD0(v)                   (((v) << 0) & 0x3ff)
+/**
+ * Register: HW_LCDIF_DEBUG1
+ * Address: 0x200
+ * SCT: no
+*/
+#define HW_LCDIF_DEBUG1                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x200))
+#define BP_LCDIF_DEBUG1_H_DATA_COUNT    16
+#define BM_LCDIF_DEBUG1_H_DATA_COUNT    0xffff0000
+#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) (((v) << 16) & 0xffff0000)
+#define BP_LCDIF_DEBUG1_V_DATA_COUNT    0
+#define BM_LCDIF_DEBUG1_V_DATA_COUNT    0xffff
+#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) (((v) << 0) & 0xffff)
+#endif /* __HEADERGEN__IMX233__LCDIF__H__ */