diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000')
18 files changed, 5578 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h new file mode 100644 index 0000000000..e9c68511d7 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h | |||
| @@ -0,0 +1,359 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_AIC_H__ | ||
| 25 | #define __HEADERGEN_AIC_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_AIC_CFG jz_reg(AIC_CFG) | ||
| 30 | #define JA_AIC_CFG (0xb0020000 + 0x0) | ||
| 31 | #define JT_AIC_CFG JIO_32_RW | ||
| 32 | #define JN_AIC_CFG AIC_CFG | ||
| 33 | #define JI_AIC_CFG | ||
| 34 | #define BP_AIC_CFG_RFTH 24 | ||
| 35 | #define BM_AIC_CFG_RFTH 0xf000000 | ||
| 36 | #define BF_AIC_CFG_RFTH(v) (((v) & 0xf) << 24) | ||
| 37 | #define BFM_AIC_CFG_RFTH(v) BM_AIC_CFG_RFTH | ||
| 38 | #define BF_AIC_CFG_RFTH_V(e) BF_AIC_CFG_RFTH(BV_AIC_CFG_RFTH__##e) | ||
| 39 | #define BFM_AIC_CFG_RFTH_V(v) BM_AIC_CFG_RFTH | ||
| 40 | #define BP_AIC_CFG_TFTH 16 | ||
| 41 | #define BM_AIC_CFG_TFTH 0x1f0000 | ||
| 42 | #define BF_AIC_CFG_TFTH(v) (((v) & 0x1f) << 16) | ||
| 43 | #define BFM_AIC_CFG_TFTH(v) BM_AIC_CFG_TFTH | ||
| 44 | #define BF_AIC_CFG_TFTH_V(e) BF_AIC_CFG_TFTH(BV_AIC_CFG_TFTH__##e) | ||
| 45 | #define BFM_AIC_CFG_TFTH_V(v) BM_AIC_CFG_TFTH | ||
| 46 | #define BP_AIC_CFG_MSB 12 | ||
| 47 | #define BM_AIC_CFG_MSB 0x1000 | ||
| 48 | #define BF_AIC_CFG_MSB(v) (((v) & 0x1) << 12) | ||
| 49 | #define BFM_AIC_CFG_MSB(v) BM_AIC_CFG_MSB | ||
| 50 | #define BF_AIC_CFG_MSB_V(e) BF_AIC_CFG_MSB(BV_AIC_CFG_MSB__##e) | ||
| 51 | #define BFM_AIC_CFG_MSB_V(v) BM_AIC_CFG_MSB | ||
| 52 | #define BP_AIC_CFG_IBCKD 10 | ||
| 53 | #define BM_AIC_CFG_IBCKD 0x400 | ||
| 54 | #define BF_AIC_CFG_IBCKD(v) (((v) & 0x1) << 10) | ||
| 55 | #define BFM_AIC_CFG_IBCKD(v) BM_AIC_CFG_IBCKD | ||
| 56 | #define BF_AIC_CFG_IBCKD_V(e) BF_AIC_CFG_IBCKD(BV_AIC_CFG_IBCKD__##e) | ||
| 57 | #define BFM_AIC_CFG_IBCKD_V(v) BM_AIC_CFG_IBCKD | ||
| 58 | #define BP_AIC_CFG_ISYNCD 9 | ||
| 59 | #define BM_AIC_CFG_ISYNCD 0x200 | ||
| 60 | #define BF_AIC_CFG_ISYNCD(v) (((v) & 0x1) << 9) | ||
| 61 | #define BFM_AIC_CFG_ISYNCD(v) BM_AIC_CFG_ISYNCD | ||
| 62 | #define BF_AIC_CFG_ISYNCD_V(e) BF_AIC_CFG_ISYNCD(BV_AIC_CFG_ISYNCD__##e) | ||
| 63 | #define BFM_AIC_CFG_ISYNCD_V(v) BM_AIC_CFG_ISYNCD | ||
| 64 | #define BP_AIC_CFG_DMODE 8 | ||
| 65 | #define BM_AIC_CFG_DMODE 0x100 | ||
| 66 | #define BF_AIC_CFG_DMODE(v) (((v) & 0x1) << 8) | ||
| 67 | #define BFM_AIC_CFG_DMODE(v) BM_AIC_CFG_DMODE | ||
| 68 | #define BF_AIC_CFG_DMODE_V(e) BF_AIC_CFG_DMODE(BV_AIC_CFG_DMODE__##e) | ||
| 69 | #define BFM_AIC_CFG_DMODE_V(v) BM_AIC_CFG_DMODE | ||
| 70 | #define BP_AIC_CFG_CDC_SLAVE 7 | ||
| 71 | #define BM_AIC_CFG_CDC_SLAVE 0x80 | ||
| 72 | #define BF_AIC_CFG_CDC_SLAVE(v) (((v) & 0x1) << 7) | ||
| 73 | #define BFM_AIC_CFG_CDC_SLAVE(v) BM_AIC_CFG_CDC_SLAVE | ||
| 74 | #define BF_AIC_CFG_CDC_SLAVE_V(e) BF_AIC_CFG_CDC_SLAVE(BV_AIC_CFG_CDC_SLAVE__##e) | ||
| 75 | #define BFM_AIC_CFG_CDC_SLAVE_V(v) BM_AIC_CFG_CDC_SLAVE | ||
| 76 | #define BP_AIC_CFG_LSMP 6 | ||
| 77 | #define BM_AIC_CFG_LSMP 0x40 | ||
| 78 | #define BF_AIC_CFG_LSMP(v) (((v) & 0x1) << 6) | ||
| 79 | #define BFM_AIC_CFG_LSMP(v) BM_AIC_CFG_LSMP | ||
| 80 | #define BF_AIC_CFG_LSMP_V(e) BF_AIC_CFG_LSMP(BV_AIC_CFG_LSMP__##e) | ||
| 81 | #define BFM_AIC_CFG_LSMP_V(v) BM_AIC_CFG_LSMP | ||
| 82 | #define BP_AIC_CFG_ICDC 5 | ||
| 83 | #define BM_AIC_CFG_ICDC 0x20 | ||
| 84 | #define BF_AIC_CFG_ICDC(v) (((v) & 0x1) << 5) | ||
| 85 | #define BFM_AIC_CFG_ICDC(v) BM_AIC_CFG_ICDC | ||
| 86 | #define BF_AIC_CFG_ICDC_V(e) BF_AIC_CFG_ICDC(BV_AIC_CFG_ICDC__##e) | ||
| 87 | #define BFM_AIC_CFG_ICDC_V(v) BM_AIC_CFG_ICDC | ||
| 88 | #define BP_AIC_CFG_AUSEL 4 | ||
| 89 | #define BM_AIC_CFG_AUSEL 0x10 | ||
| 90 | #define BF_AIC_CFG_AUSEL(v) (((v) & 0x1) << 4) | ||
| 91 | #define BFM_AIC_CFG_AUSEL(v) BM_AIC_CFG_AUSEL | ||
| 92 | #define BF_AIC_CFG_AUSEL_V(e) BF_AIC_CFG_AUSEL(BV_AIC_CFG_AUSEL__##e) | ||
| 93 | #define BFM_AIC_CFG_AUSEL_V(v) BM_AIC_CFG_AUSEL | ||
| 94 | #define BP_AIC_CFG_RST 3 | ||
| 95 | #define BM_AIC_CFG_RST 0x8 | ||
| 96 | #define BF_AIC_CFG_RST(v) (((v) & 0x1) << 3) | ||
| 97 | #define BFM_AIC_CFG_RST(v) BM_AIC_CFG_RST | ||
| 98 | #define BF_AIC_CFG_RST_V(e) BF_AIC_CFG_RST(BV_AIC_CFG_RST__##e) | ||
| 99 | #define BFM_AIC_CFG_RST_V(v) BM_AIC_CFG_RST | ||
| 100 | #define BP_AIC_CFG_BCKD 2 | ||
| 101 | #define BM_AIC_CFG_BCKD 0x4 | ||
| 102 | #define BF_AIC_CFG_BCKD(v) (((v) & 0x1) << 2) | ||
| 103 | #define BFM_AIC_CFG_BCKD(v) BM_AIC_CFG_BCKD | ||
| 104 | #define BF_AIC_CFG_BCKD_V(e) BF_AIC_CFG_BCKD(BV_AIC_CFG_BCKD__##e) | ||
| 105 | #define BFM_AIC_CFG_BCKD_V(v) BM_AIC_CFG_BCKD | ||
| 106 | #define BP_AIC_CFG_SYNCD 1 | ||
| 107 | #define BM_AIC_CFG_SYNCD 0x2 | ||
| 108 | #define BF_AIC_CFG_SYNCD(v) (((v) & 0x1) << 1) | ||
| 109 | #define BFM_AIC_CFG_SYNCD(v) BM_AIC_CFG_SYNCD | ||
| 110 | #define BF_AIC_CFG_SYNCD_V(e) BF_AIC_CFG_SYNCD(BV_AIC_CFG_SYNCD__##e) | ||
| 111 | #define BFM_AIC_CFG_SYNCD_V(v) BM_AIC_CFG_SYNCD | ||
| 112 | #define BP_AIC_CFG_ENABLE 0 | ||
| 113 | #define BM_AIC_CFG_ENABLE 0x1 | ||
| 114 | #define BF_AIC_CFG_ENABLE(v) (((v) & 0x1) << 0) | ||
| 115 | #define BFM_AIC_CFG_ENABLE(v) BM_AIC_CFG_ENABLE | ||
| 116 | #define BF_AIC_CFG_ENABLE_V(e) BF_AIC_CFG_ENABLE(BV_AIC_CFG_ENABLE__##e) | ||
| 117 | #define BFM_AIC_CFG_ENABLE_V(v) BM_AIC_CFG_ENABLE | ||
| 118 | |||
| 119 | #define REG_AIC_CCR jz_reg(AIC_CCR) | ||
| 120 | #define JA_AIC_CCR (0xb0020000 + 0x4) | ||
| 121 | #define JT_AIC_CCR JIO_32_RW | ||
| 122 | #define JN_AIC_CCR AIC_CCR | ||
| 123 | #define JI_AIC_CCR | ||
| 124 | #define BP_AIC_CCR_CHANNEL 24 | ||
| 125 | #define BM_AIC_CCR_CHANNEL 0x7000000 | ||
| 126 | #define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) | ||
| 127 | #define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL | ||
| 128 | #define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) | ||
| 129 | #define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL | ||
| 130 | #define BP_AIC_CCR_OSS 19 | ||
| 131 | #define BM_AIC_CCR_OSS 0x380000 | ||
| 132 | #define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) | ||
| 133 | #define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS | ||
| 134 | #define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) | ||
| 135 | #define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS | ||
| 136 | #define BP_AIC_CCR_ISS 16 | ||
| 137 | #define BM_AIC_CCR_ISS 0x70000 | ||
| 138 | #define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) | ||
| 139 | #define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS | ||
| 140 | #define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) | ||
| 141 | #define BFM_AIC_CCR_ISS_V(v) BM_AIC_CCR_ISS | ||
| 142 | #define BP_AIC_CCR_PACK16 28 | ||
| 143 | #define BM_AIC_CCR_PACK16 0x10000000 | ||
| 144 | #define BF_AIC_CCR_PACK16(v) (((v) & 0x1) << 28) | ||
| 145 | #define BFM_AIC_CCR_PACK16(v) BM_AIC_CCR_PACK16 | ||
| 146 | #define BF_AIC_CCR_PACK16_V(e) BF_AIC_CCR_PACK16(BV_AIC_CCR_PACK16__##e) | ||
| 147 | #define BFM_AIC_CCR_PACK16_V(v) BM_AIC_CCR_PACK16 | ||
| 148 | #define BP_AIC_CCR_RDMS 15 | ||
| 149 | #define BM_AIC_CCR_RDMS 0x8000 | ||
| 150 | #define BF_AIC_CCR_RDMS(v) (((v) & 0x1) << 15) | ||
| 151 | #define BFM_AIC_CCR_RDMS(v) BM_AIC_CCR_RDMS | ||
| 152 | #define BF_AIC_CCR_RDMS_V(e) BF_AIC_CCR_RDMS(BV_AIC_CCR_RDMS__##e) | ||
| 153 | #define BFM_AIC_CCR_RDMS_V(v) BM_AIC_CCR_RDMS | ||
| 154 | #define BP_AIC_CCR_TDMS 14 | ||
| 155 | #define BM_AIC_CCR_TDMS 0x4000 | ||
| 156 | #define BF_AIC_CCR_TDMS(v) (((v) & 0x1) << 14) | ||
| 157 | #define BFM_AIC_CCR_TDMS(v) BM_AIC_CCR_TDMS | ||
| 158 | #define BF_AIC_CCR_TDMS_V(e) BF_AIC_CCR_TDMS(BV_AIC_CCR_TDMS__##e) | ||
| 159 | #define BFM_AIC_CCR_TDMS_V(v) BM_AIC_CCR_TDMS | ||
| 160 | #define BP_AIC_CCR_M2S 11 | ||
| 161 | #define BM_AIC_CCR_M2S 0x800 | ||
| 162 | #define BF_AIC_CCR_M2S(v) (((v) & 0x1) << 11) | ||
| 163 | #define BFM_AIC_CCR_M2S(v) BM_AIC_CCR_M2S | ||
| 164 | #define BF_AIC_CCR_M2S_V(e) BF_AIC_CCR_M2S(BV_AIC_CCR_M2S__##e) | ||
| 165 | #define BFM_AIC_CCR_M2S_V(v) BM_AIC_CCR_M2S | ||
| 166 | #define BP_AIC_CCR_ENDSW 10 | ||
| 167 | #define BM_AIC_CCR_ENDSW 0x400 | ||
| 168 | #define BF_AIC_CCR_ENDSW(v) (((v) & 0x1) << 10) | ||
| 169 | #define BFM_AIC_CCR_ENDSW(v) BM_AIC_CCR_ENDSW | ||
| 170 | #define BF_AIC_CCR_ENDSW_V(e) BF_AIC_CCR_ENDSW(BV_AIC_CCR_ENDSW__##e) | ||
| 171 | #define BFM_AIC_CCR_ENDSW_V(v) BM_AIC_CCR_ENDSW | ||
| 172 | #define BP_AIC_CCR_ASVTSU 9 | ||
| 173 | #define BM_AIC_CCR_ASVTSU 0x200 | ||
| 174 | #define BF_AIC_CCR_ASVTSU(v) (((v) & 0x1) << 9) | ||
| 175 | #define BFM_AIC_CCR_ASVTSU(v) BM_AIC_CCR_ASVTSU | ||
| 176 | #define BF_AIC_CCR_ASVTSU_V(e) BF_AIC_CCR_ASVTSU(BV_AIC_CCR_ASVTSU__##e) | ||
| 177 | #define BFM_AIC_CCR_ASVTSU_V(v) BM_AIC_CCR_ASVTSU | ||
| 178 | #define BP_AIC_CCR_TFLUSH 8 | ||
| 179 | #define BM_AIC_CCR_TFLUSH 0x100 | ||
| 180 | #define BF_AIC_CCR_TFLUSH(v) (((v) & 0x1) << 8) | ||
| 181 | #define BFM_AIC_CCR_TFLUSH(v) BM_AIC_CCR_TFLUSH | ||
| 182 | #define BF_AIC_CCR_TFLUSH_V(e) BF_AIC_CCR_TFLUSH(BV_AIC_CCR_TFLUSH__##e) | ||
| 183 | #define BFM_AIC_CCR_TFLUSH_V(v) BM_AIC_CCR_TFLUSH | ||
| 184 | #define BP_AIC_CCR_RFLUSH 7 | ||
| 185 | #define BM_AIC_CCR_RFLUSH 0x80 | ||
| 186 | #define BF_AIC_CCR_RFLUSH(v) (((v) & 0x1) << 7) | ||
| 187 | #define BFM_AIC_CCR_RFLUSH(v) BM_AIC_CCR_RFLUSH | ||
| 188 | #define BF_AIC_CCR_RFLUSH_V(e) BF_AIC_CCR_RFLUSH(BV_AIC_CCR_RFLUSH__##e) | ||
| 189 | #define BFM_AIC_CCR_RFLUSH_V(v) BM_AIC_CCR_RFLUSH | ||
| 190 | #define BP_AIC_CCR_EROR 6 | ||
| 191 | #define BM_AIC_CCR_EROR 0x40 | ||
| 192 | #define BF_AIC_CCR_EROR(v) (((v) & 0x1) << 6) | ||
| 193 | #define BFM_AIC_CCR_EROR(v) BM_AIC_CCR_EROR | ||
| 194 | #define BF_AIC_CCR_EROR_V(e) BF_AIC_CCR_EROR(BV_AIC_CCR_EROR__##e) | ||
| 195 | #define BFM_AIC_CCR_EROR_V(v) BM_AIC_CCR_EROR | ||
| 196 | #define BP_AIC_CCR_ETUR 5 | ||
| 197 | #define BM_AIC_CCR_ETUR 0x20 | ||
| 198 | #define BF_AIC_CCR_ETUR(v) (((v) & 0x1) << 5) | ||
| 199 | #define BFM_AIC_CCR_ETUR(v) BM_AIC_CCR_ETUR | ||
| 200 | #define BF_AIC_CCR_ETUR_V(e) BF_AIC_CCR_ETUR(BV_AIC_CCR_ETUR__##e) | ||
| 201 | #define BFM_AIC_CCR_ETUR_V(v) BM_AIC_CCR_ETUR | ||
| 202 | #define BP_AIC_CCR_ERFS 4 | ||
| 203 | #define BM_AIC_CCR_ERFS 0x10 | ||
| 204 | #define BF_AIC_CCR_ERFS(v) (((v) & 0x1) << 4) | ||
| 205 | #define BFM_AIC_CCR_ERFS(v) BM_AIC_CCR_ERFS | ||
| 206 | #define BF_AIC_CCR_ERFS_V(e) BF_AIC_CCR_ERFS(BV_AIC_CCR_ERFS__##e) | ||
| 207 | #define BFM_AIC_CCR_ERFS_V(v) BM_AIC_CCR_ERFS | ||
| 208 | #define BP_AIC_CCR_ETFS 3 | ||
| 209 | #define BM_AIC_CCR_ETFS 0x8 | ||
| 210 | #define BF_AIC_CCR_ETFS(v) (((v) & 0x1) << 3) | ||
| 211 | #define BFM_AIC_CCR_ETFS(v) BM_AIC_CCR_ETFS | ||
| 212 | #define BF_AIC_CCR_ETFS_V(e) BF_AIC_CCR_ETFS(BV_AIC_CCR_ETFS__##e) | ||
| 213 | #define BFM_AIC_CCR_ETFS_V(v) BM_AIC_CCR_ETFS | ||
| 214 | #define BP_AIC_CCR_ENLBF 2 | ||
| 215 | #define BM_AIC_CCR_ENLBF 0x4 | ||
| 216 | #define BF_AIC_CCR_ENLBF(v) (((v) & 0x1) << 2) | ||
| 217 | #define BFM_AIC_CCR_ENLBF(v) BM_AIC_CCR_ENLBF | ||
| 218 | #define BF_AIC_CCR_ENLBF_V(e) BF_AIC_CCR_ENLBF(BV_AIC_CCR_ENLBF__##e) | ||
| 219 | #define BFM_AIC_CCR_ENLBF_V(v) BM_AIC_CCR_ENLBF | ||
| 220 | #define BP_AIC_CCR_ERPL 1 | ||
| 221 | #define BM_AIC_CCR_ERPL 0x2 | ||
| 222 | #define BF_AIC_CCR_ERPL(v) (((v) & 0x1) << 1) | ||
| 223 | #define BFM_AIC_CCR_ERPL(v) BM_AIC_CCR_ERPL | ||
| 224 | #define BF_AIC_CCR_ERPL_V(e) BF_AIC_CCR_ERPL(BV_AIC_CCR_ERPL__##e) | ||
| 225 | #define BFM_AIC_CCR_ERPL_V(v) BM_AIC_CCR_ERPL | ||
| 226 | #define BP_AIC_CCR_EREC 0 | ||
| 227 | #define BM_AIC_CCR_EREC 0x1 | ||
| 228 | #define BF_AIC_CCR_EREC(v) (((v) & 0x1) << 0) | ||
| 229 | #define BFM_AIC_CCR_EREC(v) BM_AIC_CCR_EREC | ||
| 230 | #define BF_AIC_CCR_EREC_V(e) BF_AIC_CCR_EREC(BV_AIC_CCR_EREC__##e) | ||
| 231 | #define BFM_AIC_CCR_EREC_V(v) BM_AIC_CCR_EREC | ||
| 232 | |||
| 233 | #define REG_AIC_I2SCR jz_reg(AIC_I2SCR) | ||
| 234 | #define JA_AIC_I2SCR (0xb0020000 + 0x10) | ||
| 235 | #define JT_AIC_I2SCR JIO_32_RW | ||
| 236 | #define JN_AIC_I2SCR AIC_I2SCR | ||
| 237 | #define JI_AIC_I2SCR | ||
| 238 | #define BP_AIC_I2SCR_RFIRST 17 | ||
| 239 | #define BM_AIC_I2SCR_RFIRST 0x20000 | ||
| 240 | #define BF_AIC_I2SCR_RFIRST(v) (((v) & 0x1) << 17) | ||
| 241 | #define BFM_AIC_I2SCR_RFIRST(v) BM_AIC_I2SCR_RFIRST | ||
| 242 | #define BF_AIC_I2SCR_RFIRST_V(e) BF_AIC_I2SCR_RFIRST(BV_AIC_I2SCR_RFIRST__##e) | ||
| 243 | #define BFM_AIC_I2SCR_RFIRST_V(v) BM_AIC_I2SCR_RFIRST | ||
| 244 | #define BP_AIC_I2SCR_SWLH 16 | ||
| 245 | #define BM_AIC_I2SCR_SWLH 0x10000 | ||
| 246 | #define BF_AIC_I2SCR_SWLH(v) (((v) & 0x1) << 16) | ||
| 247 | #define BFM_AIC_I2SCR_SWLH(v) BM_AIC_I2SCR_SWLH | ||
| 248 | #define BF_AIC_I2SCR_SWLH_V(e) BF_AIC_I2SCR_SWLH(BV_AIC_I2SCR_SWLH__##e) | ||
| 249 | #define BFM_AIC_I2SCR_SWLH_V(v) BM_AIC_I2SCR_SWLH | ||
| 250 | #define BP_AIC_I2SCR_ISTPBK 13 | ||
| 251 | #define BM_AIC_I2SCR_ISTPBK 0x2000 | ||
| 252 | #define BF_AIC_I2SCR_ISTPBK(v) (((v) & 0x1) << 13) | ||
| 253 | #define BFM_AIC_I2SCR_ISTPBK(v) BM_AIC_I2SCR_ISTPBK | ||
| 254 | #define BF_AIC_I2SCR_ISTPBK_V(e) BF_AIC_I2SCR_ISTPBK(BV_AIC_I2SCR_ISTPBK__##e) | ||
| 255 | #define BFM_AIC_I2SCR_ISTPBK_V(v) BM_AIC_I2SCR_ISTPBK | ||
| 256 | #define BP_AIC_I2SCR_STPBK 12 | ||
| 257 | #define BM_AIC_I2SCR_STPBK 0x1000 | ||
| 258 | #define BF_AIC_I2SCR_STPBK(v) (((v) & 0x1) << 12) | ||
| 259 | #define BFM_AIC_I2SCR_STPBK(v) BM_AIC_I2SCR_STPBK | ||
| 260 | #define BF_AIC_I2SCR_STPBK_V(e) BF_AIC_I2SCR_STPBK(BV_AIC_I2SCR_STPBK__##e) | ||
| 261 | #define BFM_AIC_I2SCR_STPBK_V(v) BM_AIC_I2SCR_STPBK | ||
| 262 | #define BP_AIC_I2SCR_ESCLK 4 | ||
| 263 | #define BM_AIC_I2SCR_ESCLK 0x10 | ||
| 264 | #define BF_AIC_I2SCR_ESCLK(v) (((v) & 0x1) << 4) | ||
| 265 | #define BFM_AIC_I2SCR_ESCLK(v) BM_AIC_I2SCR_ESCLK | ||
| 266 | #define BF_AIC_I2SCR_ESCLK_V(e) BF_AIC_I2SCR_ESCLK(BV_AIC_I2SCR_ESCLK__##e) | ||
| 267 | #define BFM_AIC_I2SCR_ESCLK_V(v) BM_AIC_I2SCR_ESCLK | ||
| 268 | #define BP_AIC_I2SCR_AMSL 0 | ||
| 269 | #define BM_AIC_I2SCR_AMSL 0x1 | ||
| 270 | #define BF_AIC_I2SCR_AMSL(v) (((v) & 0x1) << 0) | ||
| 271 | #define BFM_AIC_I2SCR_AMSL(v) BM_AIC_I2SCR_AMSL | ||
| 272 | #define BF_AIC_I2SCR_AMSL_V(e) BF_AIC_I2SCR_AMSL(BV_AIC_I2SCR_AMSL__##e) | ||
| 273 | #define BFM_AIC_I2SCR_AMSL_V(v) BM_AIC_I2SCR_AMSL | ||
| 274 | |||
| 275 | #define REG_AIC_SR jz_reg(AIC_SR) | ||
| 276 | #define JA_AIC_SR (0xb0020000 + 0x14) | ||
| 277 | #define JT_AIC_SR JIO_32_RW | ||
| 278 | #define JN_AIC_SR AIC_SR | ||
| 279 | #define JI_AIC_SR | ||
| 280 | #define BP_AIC_SR_RFL 24 | ||
| 281 | #define BM_AIC_SR_RFL 0x3f000000 | ||
| 282 | #define BF_AIC_SR_RFL(v) (((v) & 0x3f) << 24) | ||
| 283 | #define BFM_AIC_SR_RFL(v) BM_AIC_SR_RFL | ||
| 284 | #define BF_AIC_SR_RFL_V(e) BF_AIC_SR_RFL(BV_AIC_SR_RFL__##e) | ||
| 285 | #define BFM_AIC_SR_RFL_V(v) BM_AIC_SR_RFL | ||
| 286 | #define BP_AIC_SR_TFL 8 | ||
| 287 | #define BM_AIC_SR_TFL 0x3f00 | ||
| 288 | #define BF_AIC_SR_TFL(v) (((v) & 0x3f) << 8) | ||
| 289 | #define BFM_AIC_SR_TFL(v) BM_AIC_SR_TFL | ||
| 290 | #define BF_AIC_SR_TFL_V(e) BF_AIC_SR_TFL(BV_AIC_SR_TFL__##e) | ||
| 291 | #define BFM_AIC_SR_TFL_V(v) BM_AIC_SR_TFL | ||
| 292 | #define BP_AIC_SR_ROR 6 | ||
| 293 | #define BM_AIC_SR_ROR 0x40 | ||
| 294 | #define BF_AIC_SR_ROR(v) (((v) & 0x1) << 6) | ||
| 295 | #define BFM_AIC_SR_ROR(v) BM_AIC_SR_ROR | ||
| 296 | #define BF_AIC_SR_ROR_V(e) BF_AIC_SR_ROR(BV_AIC_SR_ROR__##e) | ||
| 297 | #define BFM_AIC_SR_ROR_V(v) BM_AIC_SR_ROR | ||
| 298 | #define BP_AIC_SR_TUR 5 | ||
| 299 | #define BM_AIC_SR_TUR 0x20 | ||
| 300 | #define BF_AIC_SR_TUR(v) (((v) & 0x1) << 5) | ||
| 301 | #define BFM_AIC_SR_TUR(v) BM_AIC_SR_TUR | ||
| 302 | #define BF_AIC_SR_TUR_V(e) BF_AIC_SR_TUR(BV_AIC_SR_TUR__##e) | ||
| 303 | #define BFM_AIC_SR_TUR_V(v) BM_AIC_SR_TUR | ||
| 304 | #define BP_AIC_SR_RFS 4 | ||
| 305 | #define BM_AIC_SR_RFS 0x10 | ||
| 306 | #define BF_AIC_SR_RFS(v) (((v) & 0x1) << 4) | ||
| 307 | #define BFM_AIC_SR_RFS(v) BM_AIC_SR_RFS | ||
| 308 | #define BF_AIC_SR_RFS_V(e) BF_AIC_SR_RFS(BV_AIC_SR_RFS__##e) | ||
| 309 | #define BFM_AIC_SR_RFS_V(v) BM_AIC_SR_RFS | ||
| 310 | #define BP_AIC_SR_TFS 3 | ||
| 311 | #define BM_AIC_SR_TFS 0x8 | ||
| 312 | #define BF_AIC_SR_TFS(v) (((v) & 0x1) << 3) | ||
| 313 | #define BFM_AIC_SR_TFS(v) BM_AIC_SR_TFS | ||
| 314 | #define BF_AIC_SR_TFS_V(e) BF_AIC_SR_TFS(BV_AIC_SR_TFS__##e) | ||
| 315 | #define BFM_AIC_SR_TFS_V(v) BM_AIC_SR_TFS | ||
| 316 | |||
| 317 | #define REG_AIC_I2SSR jz_reg(AIC_I2SSR) | ||
| 318 | #define JA_AIC_I2SSR (0xb0020000 + 0x1c) | ||
| 319 | #define JT_AIC_I2SSR JIO_32_RW | ||
| 320 | #define JN_AIC_I2SSR AIC_I2SSR | ||
| 321 | #define JI_AIC_I2SSR | ||
| 322 | #define BP_AIC_I2SSR_CHBSY 5 | ||
| 323 | #define BM_AIC_I2SSR_CHBSY 0x20 | ||
| 324 | #define BF_AIC_I2SSR_CHBSY(v) (((v) & 0x1) << 5) | ||
| 325 | #define BFM_AIC_I2SSR_CHBSY(v) BM_AIC_I2SSR_CHBSY | ||
| 326 | #define BF_AIC_I2SSR_CHBSY_V(e) BF_AIC_I2SSR_CHBSY(BV_AIC_I2SSR_CHBSY__##e) | ||
| 327 | #define BFM_AIC_I2SSR_CHBSY_V(v) BM_AIC_I2SSR_CHBSY | ||
| 328 | #define BP_AIC_I2SSR_TBSY 4 | ||
| 329 | #define BM_AIC_I2SSR_TBSY 0x10 | ||
| 330 | #define BF_AIC_I2SSR_TBSY(v) (((v) & 0x1) << 4) | ||
| 331 | #define BFM_AIC_I2SSR_TBSY(v) BM_AIC_I2SSR_TBSY | ||
| 332 | #define BF_AIC_I2SSR_TBSY_V(e) BF_AIC_I2SSR_TBSY(BV_AIC_I2SSR_TBSY__##e) | ||
| 333 | #define BFM_AIC_I2SSR_TBSY_V(v) BM_AIC_I2SSR_TBSY | ||
| 334 | #define BP_AIC_I2SSR_RBSY 3 | ||
| 335 | #define BM_AIC_I2SSR_RBSY 0x8 | ||
| 336 | #define BF_AIC_I2SSR_RBSY(v) (((v) & 0x1) << 3) | ||
| 337 | #define BFM_AIC_I2SSR_RBSY(v) BM_AIC_I2SSR_RBSY | ||
| 338 | #define BF_AIC_I2SSR_RBSY_V(e) BF_AIC_I2SSR_RBSY(BV_AIC_I2SSR_RBSY__##e) | ||
| 339 | #define BFM_AIC_I2SSR_RBSY_V(v) BM_AIC_I2SSR_RBSY | ||
| 340 | #define BP_AIC_I2SSR_BSY 2 | ||
| 341 | #define BM_AIC_I2SSR_BSY 0x4 | ||
| 342 | #define BF_AIC_I2SSR_BSY(v) (((v) & 0x1) << 2) | ||
| 343 | #define BFM_AIC_I2SSR_BSY(v) BM_AIC_I2SSR_BSY | ||
| 344 | #define BF_AIC_I2SSR_BSY_V(e) BF_AIC_I2SSR_BSY(BV_AIC_I2SSR_BSY__##e) | ||
| 345 | #define BFM_AIC_I2SSR_BSY_V(v) BM_AIC_I2SSR_BSY | ||
| 346 | |||
| 347 | #define REG_AIC_I2SDIV jz_reg(AIC_I2SDIV) | ||
| 348 | #define JA_AIC_I2SDIV (0xb0020000 + 0x30) | ||
| 349 | #define JT_AIC_I2SDIV JIO_32_RW | ||
| 350 | #define JN_AIC_I2SDIV AIC_I2SDIV | ||
| 351 | #define JI_AIC_I2SDIV | ||
| 352 | |||
| 353 | #define REG_AIC_DR jz_reg(AIC_DR) | ||
| 354 | #define JA_AIC_DR (0xb0020000 + 0x34) | ||
| 355 | #define JT_AIC_DR JIO_32_RW | ||
| 356 | #define JN_AIC_DR AIC_DR | ||
| 357 | #define JI_AIC_DR | ||
| 358 | |||
| 359 | #endif /* __HEADERGEN_AIC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/cpm.h b/firmware/target/mips/ingenic_x1000/x1000/cpm.h new file mode 100644 index 0000000000..752d270f20 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/cpm.h | |||
| @@ -0,0 +1,896 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_CPM_H__ | ||
| 25 | #define __HEADERGEN_CPM_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_CPM_CCR jz_reg(CPM_CCR) | ||
| 30 | #define JA_CPM_CCR (0xb0000000 + 0x0) | ||
| 31 | #define JT_CPM_CCR JIO_32_RW | ||
| 32 | #define JN_CPM_CCR CPM_CCR | ||
| 33 | #define JI_CPM_CCR | ||
| 34 | #define BP_CPM_CCR_SEL_SRC 30 | ||
| 35 | #define BM_CPM_CCR_SEL_SRC 0xc0000000 | ||
| 36 | #define BV_CPM_CCR_SEL_SRC__STOP 0x0 | ||
| 37 | #define BV_CPM_CCR_SEL_SRC__EXCLK 0x1 | ||
| 38 | #define BV_CPM_CCR_SEL_SRC__APLL 0x2 | ||
| 39 | #define BF_CPM_CCR_SEL_SRC(v) (((v) & 0x3) << 30) | ||
| 40 | #define BFM_CPM_CCR_SEL_SRC(v) BM_CPM_CCR_SEL_SRC | ||
| 41 | #define BF_CPM_CCR_SEL_SRC_V(e) BF_CPM_CCR_SEL_SRC(BV_CPM_CCR_SEL_SRC__##e) | ||
| 42 | #define BFM_CPM_CCR_SEL_SRC_V(v) BM_CPM_CCR_SEL_SRC | ||
| 43 | #define BP_CPM_CCR_SEL_CPLL 28 | ||
| 44 | #define BM_CPM_CCR_SEL_CPLL 0x30000000 | ||
| 45 | #define BV_CPM_CCR_SEL_CPLL__STOP 0x0 | ||
| 46 | #define BV_CPM_CCR_SEL_CPLL__SCLK_A 0x1 | ||
| 47 | #define BV_CPM_CCR_SEL_CPLL__MPLL 0x2 | ||
| 48 | #define BF_CPM_CCR_SEL_CPLL(v) (((v) & 0x3) << 28) | ||
| 49 | #define BFM_CPM_CCR_SEL_CPLL(v) BM_CPM_CCR_SEL_CPLL | ||
| 50 | #define BF_CPM_CCR_SEL_CPLL_V(e) BF_CPM_CCR_SEL_CPLL(BV_CPM_CCR_SEL_CPLL__##e) | ||
| 51 | #define BFM_CPM_CCR_SEL_CPLL_V(v) BM_CPM_CCR_SEL_CPLL | ||
| 52 | #define BP_CPM_CCR_SEL_H0PLL 26 | ||
| 53 | #define BM_CPM_CCR_SEL_H0PLL 0xc000000 | ||
| 54 | #define BV_CPM_CCR_SEL_H0PLL__STOP 0x0 | ||
| 55 | #define BV_CPM_CCR_SEL_H0PLL__SCLK_A 0x1 | ||
| 56 | #define BV_CPM_CCR_SEL_H0PLL__MPLL 0x2 | ||
| 57 | #define BF_CPM_CCR_SEL_H0PLL(v) (((v) & 0x3) << 26) | ||
| 58 | #define BFM_CPM_CCR_SEL_H0PLL(v) BM_CPM_CCR_SEL_H0PLL | ||
| 59 | #define BF_CPM_CCR_SEL_H0PLL_V(e) BF_CPM_CCR_SEL_H0PLL(BV_CPM_CCR_SEL_H0PLL__##e) | ||
| 60 | #define BFM_CPM_CCR_SEL_H0PLL_V(v) BM_CPM_CCR_SEL_H0PLL | ||
| 61 | #define BP_CPM_CCR_SEL_H2PLL 24 | ||
| 62 | #define BM_CPM_CCR_SEL_H2PLL 0x3000000 | ||
| 63 | #define BV_CPM_CCR_SEL_H2PLL__STOP 0x0 | ||
| 64 | #define BV_CPM_CCR_SEL_H2PLL__SCLK_A 0x1 | ||
| 65 | #define BV_CPM_CCR_SEL_H2PLL__MPLL 0x2 | ||
| 66 | #define BF_CPM_CCR_SEL_H2PLL(v) (((v) & 0x3) << 24) | ||
| 67 | #define BFM_CPM_CCR_SEL_H2PLL(v) BM_CPM_CCR_SEL_H2PLL | ||
| 68 | #define BF_CPM_CCR_SEL_H2PLL_V(e) BF_CPM_CCR_SEL_H2PLL(BV_CPM_CCR_SEL_H2PLL__##e) | ||
| 69 | #define BFM_CPM_CCR_SEL_H2PLL_V(v) BM_CPM_CCR_SEL_H2PLL | ||
| 70 | #define BP_CPM_CCR_PDIV 16 | ||
| 71 | #define BM_CPM_CCR_PDIV 0xf0000 | ||
| 72 | #define BF_CPM_CCR_PDIV(v) (((v) & 0xf) << 16) | ||
| 73 | #define BFM_CPM_CCR_PDIV(v) BM_CPM_CCR_PDIV | ||
| 74 | #define BF_CPM_CCR_PDIV_V(e) BF_CPM_CCR_PDIV(BV_CPM_CCR_PDIV__##e) | ||
| 75 | #define BFM_CPM_CCR_PDIV_V(v) BM_CPM_CCR_PDIV | ||
| 76 | #define BP_CPM_CCR_H2DIV 12 | ||
| 77 | #define BM_CPM_CCR_H2DIV 0xf000 | ||
| 78 | #define BF_CPM_CCR_H2DIV(v) (((v) & 0xf) << 12) | ||
| 79 | #define BFM_CPM_CCR_H2DIV(v) BM_CPM_CCR_H2DIV | ||
| 80 | #define BF_CPM_CCR_H2DIV_V(e) BF_CPM_CCR_H2DIV(BV_CPM_CCR_H2DIV__##e) | ||
| 81 | #define BFM_CPM_CCR_H2DIV_V(v) BM_CPM_CCR_H2DIV | ||
| 82 | #define BP_CPM_CCR_H0DIV 8 | ||
| 83 | #define BM_CPM_CCR_H0DIV 0xf00 | ||
| 84 | #define BF_CPM_CCR_H0DIV(v) (((v) & 0xf) << 8) | ||
| 85 | #define BFM_CPM_CCR_H0DIV(v) BM_CPM_CCR_H0DIV | ||
| 86 | #define BF_CPM_CCR_H0DIV_V(e) BF_CPM_CCR_H0DIV(BV_CPM_CCR_H0DIV__##e) | ||
| 87 | #define BFM_CPM_CCR_H0DIV_V(v) BM_CPM_CCR_H0DIV | ||
| 88 | #define BP_CPM_CCR_L2DIV 4 | ||
| 89 | #define BM_CPM_CCR_L2DIV 0xf0 | ||
| 90 | #define BF_CPM_CCR_L2DIV(v) (((v) & 0xf) << 4) | ||
| 91 | #define BFM_CPM_CCR_L2DIV(v) BM_CPM_CCR_L2DIV | ||
| 92 | #define BF_CPM_CCR_L2DIV_V(e) BF_CPM_CCR_L2DIV(BV_CPM_CCR_L2DIV__##e) | ||
| 93 | #define BFM_CPM_CCR_L2DIV_V(v) BM_CPM_CCR_L2DIV | ||
| 94 | #define BP_CPM_CCR_CDIV 0 | ||
| 95 | #define BM_CPM_CCR_CDIV 0xf | ||
| 96 | #define BF_CPM_CCR_CDIV(v) (((v) & 0xf) << 0) | ||
| 97 | #define BFM_CPM_CCR_CDIV(v) BM_CPM_CCR_CDIV | ||
| 98 | #define BF_CPM_CCR_CDIV_V(e) BF_CPM_CCR_CDIV(BV_CPM_CCR_CDIV__##e) | ||
| 99 | #define BFM_CPM_CCR_CDIV_V(v) BM_CPM_CCR_CDIV | ||
| 100 | #define BP_CPM_CCR_GATE_SCLKA 23 | ||
| 101 | #define BM_CPM_CCR_GATE_SCLKA 0x800000 | ||
| 102 | #define BF_CPM_CCR_GATE_SCLKA(v) (((v) & 0x1) << 23) | ||
| 103 | #define BFM_CPM_CCR_GATE_SCLKA(v) BM_CPM_CCR_GATE_SCLKA | ||
| 104 | #define BF_CPM_CCR_GATE_SCLKA_V(e) BF_CPM_CCR_GATE_SCLKA(BV_CPM_CCR_GATE_SCLKA__##e) | ||
| 105 | #define BFM_CPM_CCR_GATE_SCLKA_V(v) BM_CPM_CCR_GATE_SCLKA | ||
| 106 | #define BP_CPM_CCR_CE_CPU 22 | ||
| 107 | #define BM_CPM_CCR_CE_CPU 0x400000 | ||
| 108 | #define BF_CPM_CCR_CE_CPU(v) (((v) & 0x1) << 22) | ||
| 109 | #define BFM_CPM_CCR_CE_CPU(v) BM_CPM_CCR_CE_CPU | ||
| 110 | #define BF_CPM_CCR_CE_CPU_V(e) BF_CPM_CCR_CE_CPU(BV_CPM_CCR_CE_CPU__##e) | ||
| 111 | #define BFM_CPM_CCR_CE_CPU_V(v) BM_CPM_CCR_CE_CPU | ||
| 112 | #define BP_CPM_CCR_CE_AHB0 21 | ||
| 113 | #define BM_CPM_CCR_CE_AHB0 0x200000 | ||
| 114 | #define BF_CPM_CCR_CE_AHB0(v) (((v) & 0x1) << 21) | ||
| 115 | #define BFM_CPM_CCR_CE_AHB0(v) BM_CPM_CCR_CE_AHB0 | ||
| 116 | #define BF_CPM_CCR_CE_AHB0_V(e) BF_CPM_CCR_CE_AHB0(BV_CPM_CCR_CE_AHB0__##e) | ||
| 117 | #define BFM_CPM_CCR_CE_AHB0_V(v) BM_CPM_CCR_CE_AHB0 | ||
| 118 | #define BP_CPM_CCR_CE_AHB2 20 | ||
| 119 | #define BM_CPM_CCR_CE_AHB2 0x100000 | ||
| 120 | #define BF_CPM_CCR_CE_AHB2(v) (((v) & 0x1) << 20) | ||
| 121 | #define BFM_CPM_CCR_CE_AHB2(v) BM_CPM_CCR_CE_AHB2 | ||
| 122 | #define BF_CPM_CCR_CE_AHB2_V(e) BF_CPM_CCR_CE_AHB2(BV_CPM_CCR_CE_AHB2__##e) | ||
| 123 | #define BFM_CPM_CCR_CE_AHB2_V(v) BM_CPM_CCR_CE_AHB2 | ||
| 124 | |||
| 125 | #define REG_CPM_CSR jz_reg(CPM_CSR) | ||
| 126 | #define JA_CPM_CSR (0xb0000000 + 0xd4) | ||
| 127 | #define JT_CPM_CSR JIO_32_RW | ||
| 128 | #define JN_CPM_CSR CPM_CSR | ||
| 129 | #define JI_CPM_CSR | ||
| 130 | #define BP_CPM_CSR_SRC_MUX 31 | ||
| 131 | #define BM_CPM_CSR_SRC_MUX 0x80000000 | ||
| 132 | #define BF_CPM_CSR_SRC_MUX(v) (((v) & 0x1) << 31) | ||
| 133 | #define BFM_CPM_CSR_SRC_MUX(v) BM_CPM_CSR_SRC_MUX | ||
| 134 | #define BF_CPM_CSR_SRC_MUX_V(e) BF_CPM_CSR_SRC_MUX(BV_CPM_CSR_SRC_MUX__##e) | ||
| 135 | #define BFM_CPM_CSR_SRC_MUX_V(v) BM_CPM_CSR_SRC_MUX | ||
| 136 | #define BP_CPM_CSR_CPU_MUX 30 | ||
| 137 | #define BM_CPM_CSR_CPU_MUX 0x40000000 | ||
| 138 | #define BF_CPM_CSR_CPU_MUX(v) (((v) & 0x1) << 30) | ||
| 139 | #define BFM_CPM_CSR_CPU_MUX(v) BM_CPM_CSR_CPU_MUX | ||
| 140 | #define BF_CPM_CSR_CPU_MUX_V(e) BF_CPM_CSR_CPU_MUX(BV_CPM_CSR_CPU_MUX__##e) | ||
| 141 | #define BFM_CPM_CSR_CPU_MUX_V(v) BM_CPM_CSR_CPU_MUX | ||
| 142 | #define BP_CPM_CSR_AHB0_MUX 29 | ||
| 143 | #define BM_CPM_CSR_AHB0_MUX 0x20000000 | ||
| 144 | #define BF_CPM_CSR_AHB0_MUX(v) (((v) & 0x1) << 29) | ||
| 145 | #define BFM_CPM_CSR_AHB0_MUX(v) BM_CPM_CSR_AHB0_MUX | ||
| 146 | #define BF_CPM_CSR_AHB0_MUX_V(e) BF_CPM_CSR_AHB0_MUX(BV_CPM_CSR_AHB0_MUX__##e) | ||
| 147 | #define BFM_CPM_CSR_AHB0_MUX_V(v) BM_CPM_CSR_AHB0_MUX | ||
| 148 | #define BP_CPM_CSR_AHB2_MUX 28 | ||
| 149 | #define BM_CPM_CSR_AHB2_MUX 0x10000000 | ||
| 150 | #define BF_CPM_CSR_AHB2_MUX(v) (((v) & 0x1) << 28) | ||
| 151 | #define BFM_CPM_CSR_AHB2_MUX(v) BM_CPM_CSR_AHB2_MUX | ||
| 152 | #define BF_CPM_CSR_AHB2_MUX_V(e) BF_CPM_CSR_AHB2_MUX(BV_CPM_CSR_AHB2_MUX__##e) | ||
| 153 | #define BFM_CPM_CSR_AHB2_MUX_V(v) BM_CPM_CSR_AHB2_MUX | ||
| 154 | #define BP_CPM_CSR_DDR_MUX 27 | ||
| 155 | #define BM_CPM_CSR_DDR_MUX 0x8000000 | ||
| 156 | #define BF_CPM_CSR_DDR_MUX(v) (((v) & 0x1) << 27) | ||
| 157 | #define BFM_CPM_CSR_DDR_MUX(v) BM_CPM_CSR_DDR_MUX | ||
| 158 | #define BF_CPM_CSR_DDR_MUX_V(e) BF_CPM_CSR_DDR_MUX(BV_CPM_CSR_DDR_MUX__##e) | ||
| 159 | #define BFM_CPM_CSR_DDR_MUX_V(v) BM_CPM_CSR_DDR_MUX | ||
| 160 | #define BP_CPM_CSR_H2DIV_BUSY 2 | ||
| 161 | #define BM_CPM_CSR_H2DIV_BUSY 0x4 | ||
| 162 | #define BF_CPM_CSR_H2DIV_BUSY(v) (((v) & 0x1) << 2) | ||
| 163 | #define BFM_CPM_CSR_H2DIV_BUSY(v) BM_CPM_CSR_H2DIV_BUSY | ||
| 164 | #define BF_CPM_CSR_H2DIV_BUSY_V(e) BF_CPM_CSR_H2DIV_BUSY(BV_CPM_CSR_H2DIV_BUSY__##e) | ||
| 165 | #define BFM_CPM_CSR_H2DIV_BUSY_V(v) BM_CPM_CSR_H2DIV_BUSY | ||
| 166 | #define BP_CPM_CSR_H0DIV_BUSY 1 | ||
| 167 | #define BM_CPM_CSR_H0DIV_BUSY 0x2 | ||
| 168 | #define BF_CPM_CSR_H0DIV_BUSY(v) (((v) & 0x1) << 1) | ||
| 169 | #define BFM_CPM_CSR_H0DIV_BUSY(v) BM_CPM_CSR_H0DIV_BUSY | ||
| 170 | #define BF_CPM_CSR_H0DIV_BUSY_V(e) BF_CPM_CSR_H0DIV_BUSY(BV_CPM_CSR_H0DIV_BUSY__##e) | ||
| 171 | #define BFM_CPM_CSR_H0DIV_BUSY_V(v) BM_CPM_CSR_H0DIV_BUSY | ||
| 172 | #define BP_CPM_CSR_CDIV_BUSY 0 | ||
| 173 | #define BM_CPM_CSR_CDIV_BUSY 0x1 | ||
| 174 | #define BF_CPM_CSR_CDIV_BUSY(v) (((v) & 0x1) << 0) | ||
| 175 | #define BFM_CPM_CSR_CDIV_BUSY(v) BM_CPM_CSR_CDIV_BUSY | ||
| 176 | #define BF_CPM_CSR_CDIV_BUSY_V(e) BF_CPM_CSR_CDIV_BUSY(BV_CPM_CSR_CDIV_BUSY__##e) | ||
| 177 | #define BFM_CPM_CSR_CDIV_BUSY_V(v) BM_CPM_CSR_CDIV_BUSY | ||
| 178 | |||
| 179 | #define REG_CPM_DDRCDR jz_reg(CPM_DDRCDR) | ||
| 180 | #define JA_CPM_DDRCDR (0xb0000000 + 0x2c) | ||
| 181 | #define JT_CPM_DDRCDR JIO_32_RW | ||
| 182 | #define JN_CPM_DDRCDR CPM_DDRCDR | ||
| 183 | #define JI_CPM_DDRCDR | ||
| 184 | #define BP_CPM_DDRCDR_CLKSRC 30 | ||
| 185 | #define BM_CPM_DDRCDR_CLKSRC 0xc0000000 | ||
| 186 | #define BV_CPM_DDRCDR_CLKSRC__STOP 0x0 | ||
| 187 | #define BV_CPM_DDRCDR_CLKSRC__SCLK_A 0x1 | ||
| 188 | #define BV_CPM_DDRCDR_CLKSRC__MPLL 0x2 | ||
| 189 | #define BF_CPM_DDRCDR_CLKSRC(v) (((v) & 0x3) << 30) | ||
| 190 | #define BFM_CPM_DDRCDR_CLKSRC(v) BM_CPM_DDRCDR_CLKSRC | ||
| 191 | #define BF_CPM_DDRCDR_CLKSRC_V(e) BF_CPM_DDRCDR_CLKSRC(BV_CPM_DDRCDR_CLKSRC__##e) | ||
| 192 | #define BFM_CPM_DDRCDR_CLKSRC_V(v) BM_CPM_DDRCDR_CLKSRC | ||
| 193 | #define BP_CPM_DDRCDR_CLKDIV 0 | ||
| 194 | #define BM_CPM_DDRCDR_CLKDIV 0xf | ||
| 195 | #define BF_CPM_DDRCDR_CLKDIV(v) (((v) & 0xf) << 0) | ||
| 196 | #define BFM_CPM_DDRCDR_CLKDIV(v) BM_CPM_DDRCDR_CLKDIV | ||
| 197 | #define BF_CPM_DDRCDR_CLKDIV_V(e) BF_CPM_DDRCDR_CLKDIV(BV_CPM_DDRCDR_CLKDIV__##e) | ||
| 198 | #define BFM_CPM_DDRCDR_CLKDIV_V(v) BM_CPM_DDRCDR_CLKDIV | ||
| 199 | #define BP_CPM_DDRCDR_CE 29 | ||
| 200 | #define BM_CPM_DDRCDR_CE 0x20000000 | ||
| 201 | #define BF_CPM_DDRCDR_CE(v) (((v) & 0x1) << 29) | ||
| 202 | #define BFM_CPM_DDRCDR_CE(v) BM_CPM_DDRCDR_CE | ||
| 203 | #define BF_CPM_DDRCDR_CE_V(e) BF_CPM_DDRCDR_CE(BV_CPM_DDRCDR_CE__##e) | ||
| 204 | #define BFM_CPM_DDRCDR_CE_V(v) BM_CPM_DDRCDR_CE | ||
| 205 | #define BP_CPM_DDRCDR_BUSY 28 | ||
| 206 | #define BM_CPM_DDRCDR_BUSY 0x10000000 | ||
| 207 | #define BF_CPM_DDRCDR_BUSY(v) (((v) & 0x1) << 28) | ||
| 208 | #define BFM_CPM_DDRCDR_BUSY(v) BM_CPM_DDRCDR_BUSY | ||
| 209 | #define BF_CPM_DDRCDR_BUSY_V(e) BF_CPM_DDRCDR_BUSY(BV_CPM_DDRCDR_BUSY__##e) | ||
| 210 | #define BFM_CPM_DDRCDR_BUSY_V(v) BM_CPM_DDRCDR_BUSY | ||
| 211 | #define BP_CPM_DDRCDR_STOP 27 | ||
| 212 | #define BM_CPM_DDRCDR_STOP 0x8000000 | ||
| 213 | #define BF_CPM_DDRCDR_STOP(v) (((v) & 0x1) << 27) | ||
| 214 | #define BFM_CPM_DDRCDR_STOP(v) BM_CPM_DDRCDR_STOP | ||
| 215 | #define BF_CPM_DDRCDR_STOP_V(e) BF_CPM_DDRCDR_STOP(BV_CPM_DDRCDR_STOP__##e) | ||
| 216 | #define BFM_CPM_DDRCDR_STOP_V(v) BM_CPM_DDRCDR_STOP | ||
| 217 | #define BP_CPM_DDRCDR_GATE_EN 26 | ||
| 218 | #define BM_CPM_DDRCDR_GATE_EN 0x4000000 | ||
| 219 | #define BF_CPM_DDRCDR_GATE_EN(v) (((v) & 0x1) << 26) | ||
| 220 | #define BFM_CPM_DDRCDR_GATE_EN(v) BM_CPM_DDRCDR_GATE_EN | ||
| 221 | #define BF_CPM_DDRCDR_GATE_EN_V(e) BF_CPM_DDRCDR_GATE_EN(BV_CPM_DDRCDR_GATE_EN__##e) | ||
| 222 | #define BFM_CPM_DDRCDR_GATE_EN_V(v) BM_CPM_DDRCDR_GATE_EN | ||
| 223 | #define BP_CPM_DDRCDR_CHANGE_EN 25 | ||
| 224 | #define BM_CPM_DDRCDR_CHANGE_EN 0x2000000 | ||
| 225 | #define BF_CPM_DDRCDR_CHANGE_EN(v) (((v) & 0x1) << 25) | ||
| 226 | #define BFM_CPM_DDRCDR_CHANGE_EN(v) BM_CPM_DDRCDR_CHANGE_EN | ||
| 227 | #define BF_CPM_DDRCDR_CHANGE_EN_V(e) BF_CPM_DDRCDR_CHANGE_EN(BV_CPM_DDRCDR_CHANGE_EN__##e) | ||
| 228 | #define BFM_CPM_DDRCDR_CHANGE_EN_V(v) BM_CPM_DDRCDR_CHANGE_EN | ||
| 229 | #define BP_CPM_DDRCDR_FLAG 24 | ||
| 230 | #define BM_CPM_DDRCDR_FLAG 0x1000000 | ||
| 231 | #define BF_CPM_DDRCDR_FLAG(v) (((v) & 0x1) << 24) | ||
| 232 | #define BFM_CPM_DDRCDR_FLAG(v) BM_CPM_DDRCDR_FLAG | ||
| 233 | #define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e) | ||
| 234 | #define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG | ||
| 235 | |||
| 236 | #define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR) | ||
| 237 | #define JA_CPM_I2SCDR (0xb0000000 + 0x60) | ||
| 238 | #define JT_CPM_I2SCDR JIO_32_RW | ||
| 239 | #define JN_CPM_I2SCDR CPM_I2SCDR | ||
| 240 | #define JI_CPM_I2SCDR | ||
| 241 | #define BP_CPM_I2SCDR_DIV_M 13 | ||
| 242 | #define BM_CPM_I2SCDR_DIV_M 0x3fe000 | ||
| 243 | #define BF_CPM_I2SCDR_DIV_M(v) (((v) & 0x1ff) << 13) | ||
| 244 | #define BFM_CPM_I2SCDR_DIV_M(v) BM_CPM_I2SCDR_DIV_M | ||
| 245 | #define BF_CPM_I2SCDR_DIV_M_V(e) BF_CPM_I2SCDR_DIV_M(BV_CPM_I2SCDR_DIV_M__##e) | ||
| 246 | #define BFM_CPM_I2SCDR_DIV_M_V(v) BM_CPM_I2SCDR_DIV_M | ||
| 247 | #define BP_CPM_I2SCDR_DIV_N 0 | ||
| 248 | #define BM_CPM_I2SCDR_DIV_N 0x1fff | ||
| 249 | #define BF_CPM_I2SCDR_DIV_N(v) (((v) & 0x1fff) << 0) | ||
| 250 | #define BFM_CPM_I2SCDR_DIV_N(v) BM_CPM_I2SCDR_DIV_N | ||
| 251 | #define BF_CPM_I2SCDR_DIV_N_V(e) BF_CPM_I2SCDR_DIV_N(BV_CPM_I2SCDR_DIV_N__##e) | ||
| 252 | #define BFM_CPM_I2SCDR_DIV_N_V(v) BM_CPM_I2SCDR_DIV_N | ||
| 253 | #define BP_CPM_I2SCDR_PCS 31 | ||
| 254 | #define BM_CPM_I2SCDR_PCS 0x80000000 | ||
| 255 | #define BV_CPM_I2SCDR_PCS__SCLK_A 0x0 | ||
| 256 | #define BV_CPM_I2SCDR_PCS__MPLL 0x1 | ||
| 257 | #define BF_CPM_I2SCDR_PCS(v) (((v) & 0x1) << 31) | ||
| 258 | #define BFM_CPM_I2SCDR_PCS(v) BM_CPM_I2SCDR_PCS | ||
| 259 | #define BF_CPM_I2SCDR_PCS_V(e) BF_CPM_I2SCDR_PCS(BV_CPM_I2SCDR_PCS__##e) | ||
| 260 | #define BFM_CPM_I2SCDR_PCS_V(v) BM_CPM_I2SCDR_PCS | ||
| 261 | #define BP_CPM_I2SCDR_CS 30 | ||
| 262 | #define BM_CPM_I2SCDR_CS 0x40000000 | ||
| 263 | #define BV_CPM_I2SCDR_CS__EXCLK 0x0 | ||
| 264 | #define BV_CPM_I2SCDR_CS__PLL 0x1 | ||
| 265 | #define BF_CPM_I2SCDR_CS(v) (((v) & 0x1) << 30) | ||
| 266 | #define BFM_CPM_I2SCDR_CS(v) BM_CPM_I2SCDR_CS | ||
| 267 | #define BF_CPM_I2SCDR_CS_V(e) BF_CPM_I2SCDR_CS(BV_CPM_I2SCDR_CS__##e) | ||
| 268 | #define BFM_CPM_I2SCDR_CS_V(v) BM_CPM_I2SCDR_CS | ||
| 269 | #define BP_CPM_I2SCDR_CE 29 | ||
| 270 | #define BM_CPM_I2SCDR_CE 0x20000000 | ||
| 271 | #define BF_CPM_I2SCDR_CE(v) (((v) & 0x1) << 29) | ||
| 272 | #define BFM_CPM_I2SCDR_CE(v) BM_CPM_I2SCDR_CE | ||
| 273 | #define BF_CPM_I2SCDR_CE_V(e) BF_CPM_I2SCDR_CE(BV_CPM_I2SCDR_CE__##e) | ||
| 274 | #define BFM_CPM_I2SCDR_CE_V(v) BM_CPM_I2SCDR_CE | ||
| 275 | |||
| 276 | #define REG_CPM_I2SCDR1 jz_reg(CPM_I2SCDR1) | ||
| 277 | #define JA_CPM_I2SCDR1 (0xb0000000 + 0x70) | ||
| 278 | #define JT_CPM_I2SCDR1 JIO_32_RW | ||
| 279 | #define JN_CPM_I2SCDR1 CPM_I2SCDR1 | ||
| 280 | #define JI_CPM_I2SCDR1 | ||
| 281 | |||
| 282 | #define REG_CPM_LPCDR jz_reg(CPM_LPCDR) | ||
| 283 | #define JA_CPM_LPCDR (0xb0000000 + 0x64) | ||
| 284 | #define JT_CPM_LPCDR JIO_32_RW | ||
| 285 | #define JN_CPM_LPCDR CPM_LPCDR | ||
| 286 | #define JI_CPM_LPCDR | ||
| 287 | #define BP_CPM_LPCDR_CLKDIV 0 | ||
| 288 | #define BM_CPM_LPCDR_CLKDIV 0xff | ||
| 289 | #define BF_CPM_LPCDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
| 290 | #define BFM_CPM_LPCDR_CLKDIV(v) BM_CPM_LPCDR_CLKDIV | ||
| 291 | #define BF_CPM_LPCDR_CLKDIV_V(e) BF_CPM_LPCDR_CLKDIV(BV_CPM_LPCDR_CLKDIV__##e) | ||
| 292 | #define BFM_CPM_LPCDR_CLKDIV_V(v) BM_CPM_LPCDR_CLKDIV | ||
| 293 | #define BP_CPM_LPCDR_CLKSRC 31 | ||
| 294 | #define BM_CPM_LPCDR_CLKSRC 0x80000000 | ||
| 295 | #define BV_CPM_LPCDR_CLKSRC__SCLK_A 0x0 | ||
| 296 | #define BV_CPM_LPCDR_CLKSRC__MPLL 0x1 | ||
| 297 | #define BF_CPM_LPCDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
| 298 | #define BFM_CPM_LPCDR_CLKSRC(v) BM_CPM_LPCDR_CLKSRC | ||
| 299 | #define BF_CPM_LPCDR_CLKSRC_V(e) BF_CPM_LPCDR_CLKSRC(BV_CPM_LPCDR_CLKSRC__##e) | ||
| 300 | #define BFM_CPM_LPCDR_CLKSRC_V(v) BM_CPM_LPCDR_CLKSRC | ||
| 301 | #define BP_CPM_LPCDR_CE 28 | ||
| 302 | #define BM_CPM_LPCDR_CE 0x10000000 | ||
| 303 | #define BF_CPM_LPCDR_CE(v) (((v) & 0x1) << 28) | ||
| 304 | #define BFM_CPM_LPCDR_CE(v) BM_CPM_LPCDR_CE | ||
| 305 | #define BF_CPM_LPCDR_CE_V(e) BF_CPM_LPCDR_CE(BV_CPM_LPCDR_CE__##e) | ||
| 306 | #define BFM_CPM_LPCDR_CE_V(v) BM_CPM_LPCDR_CE | ||
| 307 | #define BP_CPM_LPCDR_BUSY 27 | ||
| 308 | #define BM_CPM_LPCDR_BUSY 0x8000000 | ||
| 309 | #define BF_CPM_LPCDR_BUSY(v) (((v) & 0x1) << 27) | ||
| 310 | #define BFM_CPM_LPCDR_BUSY(v) BM_CPM_LPCDR_BUSY | ||
| 311 | #define BF_CPM_LPCDR_BUSY_V(e) BF_CPM_LPCDR_BUSY(BV_CPM_LPCDR_BUSY__##e) | ||
| 312 | #define BFM_CPM_LPCDR_BUSY_V(v) BM_CPM_LPCDR_BUSY | ||
| 313 | #define BP_CPM_LPCDR_STOP 26 | ||
| 314 | #define BM_CPM_LPCDR_STOP 0x4000000 | ||
| 315 | #define BF_CPM_LPCDR_STOP(v) (((v) & 0x1) << 26) | ||
| 316 | #define BFM_CPM_LPCDR_STOP(v) BM_CPM_LPCDR_STOP | ||
| 317 | #define BF_CPM_LPCDR_STOP_V(e) BF_CPM_LPCDR_STOP(BV_CPM_LPCDR_STOP__##e) | ||
| 318 | #define BFM_CPM_LPCDR_STOP_V(v) BM_CPM_LPCDR_STOP | ||
| 319 | |||
| 320 | #define REG_CPM_MSC0CDR jz_reg(CPM_MSC0CDR) | ||
| 321 | #define JA_CPM_MSC0CDR (0xb0000000 + 0x68) | ||
| 322 | #define JT_CPM_MSC0CDR JIO_32_RW | ||
| 323 | #define JN_CPM_MSC0CDR CPM_MSC0CDR | ||
| 324 | #define JI_CPM_MSC0CDR | ||
| 325 | #define BP_CPM_MSC0CDR_CLKDIV 0 | ||
| 326 | #define BM_CPM_MSC0CDR_CLKDIV 0xff | ||
| 327 | #define BF_CPM_MSC0CDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
| 328 | #define BFM_CPM_MSC0CDR_CLKDIV(v) BM_CPM_MSC0CDR_CLKDIV | ||
| 329 | #define BF_CPM_MSC0CDR_CLKDIV_V(e) BF_CPM_MSC0CDR_CLKDIV(BV_CPM_MSC0CDR_CLKDIV__##e) | ||
| 330 | #define BFM_CPM_MSC0CDR_CLKDIV_V(v) BM_CPM_MSC0CDR_CLKDIV | ||
| 331 | #define BP_CPM_MSC0CDR_CLKSRC 31 | ||
| 332 | #define BM_CPM_MSC0CDR_CLKSRC 0x80000000 | ||
| 333 | #define BV_CPM_MSC0CDR_CLKSRC__SCLK_A 0x0 | ||
| 334 | #define BV_CPM_MSC0CDR_CLKSRC__MPLL 0x1 | ||
| 335 | #define BF_CPM_MSC0CDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
| 336 | #define BFM_CPM_MSC0CDR_CLKSRC(v) BM_CPM_MSC0CDR_CLKSRC | ||
| 337 | #define BF_CPM_MSC0CDR_CLKSRC_V(e) BF_CPM_MSC0CDR_CLKSRC(BV_CPM_MSC0CDR_CLKSRC__##e) | ||
| 338 | #define BFM_CPM_MSC0CDR_CLKSRC_V(v) BM_CPM_MSC0CDR_CLKSRC | ||
| 339 | #define BP_CPM_MSC0CDR_CE 29 | ||
| 340 | #define BM_CPM_MSC0CDR_CE 0x20000000 | ||
| 341 | #define BF_CPM_MSC0CDR_CE(v) (((v) & 0x1) << 29) | ||
| 342 | #define BFM_CPM_MSC0CDR_CE(v) BM_CPM_MSC0CDR_CE | ||
| 343 | #define BF_CPM_MSC0CDR_CE_V(e) BF_CPM_MSC0CDR_CE(BV_CPM_MSC0CDR_CE__##e) | ||
| 344 | #define BFM_CPM_MSC0CDR_CE_V(v) BM_CPM_MSC0CDR_CE | ||
| 345 | #define BP_CPM_MSC0CDR_BUSY 28 | ||
| 346 | #define BM_CPM_MSC0CDR_BUSY 0x10000000 | ||
| 347 | #define BF_CPM_MSC0CDR_BUSY(v) (((v) & 0x1) << 28) | ||
| 348 | #define BFM_CPM_MSC0CDR_BUSY(v) BM_CPM_MSC0CDR_BUSY | ||
| 349 | #define BF_CPM_MSC0CDR_BUSY_V(e) BF_CPM_MSC0CDR_BUSY(BV_CPM_MSC0CDR_BUSY__##e) | ||
| 350 | #define BFM_CPM_MSC0CDR_BUSY_V(v) BM_CPM_MSC0CDR_BUSY | ||
| 351 | #define BP_CPM_MSC0CDR_STOP 27 | ||
| 352 | #define BM_CPM_MSC0CDR_STOP 0x8000000 | ||
| 353 | #define BF_CPM_MSC0CDR_STOP(v) (((v) & 0x1) << 27) | ||
| 354 | #define BFM_CPM_MSC0CDR_STOP(v) BM_CPM_MSC0CDR_STOP | ||
| 355 | #define BF_CPM_MSC0CDR_STOP_V(e) BF_CPM_MSC0CDR_STOP(BV_CPM_MSC0CDR_STOP__##e) | ||
| 356 | #define BFM_CPM_MSC0CDR_STOP_V(v) BM_CPM_MSC0CDR_STOP | ||
| 357 | #define BP_CPM_MSC0CDR_S_CLK0_SEL 15 | ||
| 358 | #define BM_CPM_MSC0CDR_S_CLK0_SEL 0x8000 | ||
| 359 | #define BV_CPM_MSC0CDR_S_CLK0_SEL__90DEG 0x0 | ||
| 360 | #define BV_CPM_MSC0CDR_S_CLK0_SEL__180DEG 0x1 | ||
| 361 | #define BF_CPM_MSC0CDR_S_CLK0_SEL(v) (((v) & 0x1) << 15) | ||
| 362 | #define BFM_CPM_MSC0CDR_S_CLK0_SEL(v) BM_CPM_MSC0CDR_S_CLK0_SEL | ||
| 363 | #define BF_CPM_MSC0CDR_S_CLK0_SEL_V(e) BF_CPM_MSC0CDR_S_CLK0_SEL(BV_CPM_MSC0CDR_S_CLK0_SEL__##e) | ||
| 364 | #define BFM_CPM_MSC0CDR_S_CLK0_SEL_V(v) BM_CPM_MSC0CDR_S_CLK0_SEL | ||
| 365 | |||
| 366 | #define REG_CPM_MSC1CDR jz_reg(CPM_MSC1CDR) | ||
| 367 | #define JA_CPM_MSC1CDR (0xb0000000 + 0xa4) | ||
| 368 | #define JT_CPM_MSC1CDR JIO_32_RW | ||
| 369 | #define JN_CPM_MSC1CDR CPM_MSC1CDR | ||
| 370 | #define JI_CPM_MSC1CDR | ||
| 371 | #define BP_CPM_MSC1CDR_CLKDIV 0 | ||
| 372 | #define BM_CPM_MSC1CDR_CLKDIV 0xff | ||
| 373 | #define BF_CPM_MSC1CDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
| 374 | #define BFM_CPM_MSC1CDR_CLKDIV(v) BM_CPM_MSC1CDR_CLKDIV | ||
| 375 | #define BF_CPM_MSC1CDR_CLKDIV_V(e) BF_CPM_MSC1CDR_CLKDIV(BV_CPM_MSC1CDR_CLKDIV__##e) | ||
| 376 | #define BFM_CPM_MSC1CDR_CLKDIV_V(v) BM_CPM_MSC1CDR_CLKDIV | ||
| 377 | #define BP_CPM_MSC1CDR_CE 29 | ||
| 378 | #define BM_CPM_MSC1CDR_CE 0x20000000 | ||
| 379 | #define BF_CPM_MSC1CDR_CE(v) (((v) & 0x1) << 29) | ||
| 380 | #define BFM_CPM_MSC1CDR_CE(v) BM_CPM_MSC1CDR_CE | ||
| 381 | #define BF_CPM_MSC1CDR_CE_V(e) BF_CPM_MSC1CDR_CE(BV_CPM_MSC1CDR_CE__##e) | ||
| 382 | #define BFM_CPM_MSC1CDR_CE_V(v) BM_CPM_MSC1CDR_CE | ||
| 383 | #define BP_CPM_MSC1CDR_BUSY 28 | ||
| 384 | #define BM_CPM_MSC1CDR_BUSY 0x10000000 | ||
| 385 | #define BF_CPM_MSC1CDR_BUSY(v) (((v) & 0x1) << 28) | ||
| 386 | #define BFM_CPM_MSC1CDR_BUSY(v) BM_CPM_MSC1CDR_BUSY | ||
| 387 | #define BF_CPM_MSC1CDR_BUSY_V(e) BF_CPM_MSC1CDR_BUSY(BV_CPM_MSC1CDR_BUSY__##e) | ||
| 388 | #define BFM_CPM_MSC1CDR_BUSY_V(v) BM_CPM_MSC1CDR_BUSY | ||
| 389 | #define BP_CPM_MSC1CDR_STOP 27 | ||
| 390 | #define BM_CPM_MSC1CDR_STOP 0x8000000 | ||
| 391 | #define BF_CPM_MSC1CDR_STOP(v) (((v) & 0x1) << 27) | ||
| 392 | #define BFM_CPM_MSC1CDR_STOP(v) BM_CPM_MSC1CDR_STOP | ||
| 393 | #define BF_CPM_MSC1CDR_STOP_V(e) BF_CPM_MSC1CDR_STOP(BV_CPM_MSC1CDR_STOP__##e) | ||
| 394 | #define BFM_CPM_MSC1CDR_STOP_V(v) BM_CPM_MSC1CDR_STOP | ||
| 395 | #define BP_CPM_MSC1CDR_S_CLK1_SEL 15 | ||
| 396 | #define BM_CPM_MSC1CDR_S_CLK1_SEL 0x8000 | ||
| 397 | #define BV_CPM_MSC1CDR_S_CLK1_SEL__90DEG 0x0 | ||
| 398 | #define BV_CPM_MSC1CDR_S_CLK1_SEL__180DEG 0x1 | ||
| 399 | #define BF_CPM_MSC1CDR_S_CLK1_SEL(v) (((v) & 0x1) << 15) | ||
| 400 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL(v) BM_CPM_MSC1CDR_S_CLK1_SEL | ||
| 401 | #define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e) BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e) | ||
| 402 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v) BM_CPM_MSC1CDR_S_CLK1_SEL | ||
| 403 | |||
| 404 | #define REG_CPM_SSICDR jz_reg(CPM_SSICDR) | ||
| 405 | #define JA_CPM_SSICDR (0xb0000000 + 0x74) | ||
| 406 | #define JT_CPM_SSICDR JIO_32_RW | ||
| 407 | #define JN_CPM_SSICDR CPM_SSICDR | ||
| 408 | #define JI_CPM_SSICDR | ||
| 409 | #define BP_CPM_SSICDR_CLKDIV 0 | ||
| 410 | #define BM_CPM_SSICDR_CLKDIV 0xff | ||
| 411 | #define BF_CPM_SSICDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
| 412 | #define BFM_CPM_SSICDR_CLKDIV(v) BM_CPM_SSICDR_CLKDIV | ||
| 413 | #define BF_CPM_SSICDR_CLKDIV_V(e) BF_CPM_SSICDR_CLKDIV(BV_CPM_SSICDR_CLKDIV__##e) | ||
| 414 | #define BFM_CPM_SSICDR_CLKDIV_V(v) BM_CPM_SSICDR_CLKDIV | ||
| 415 | #define BP_CPM_SSICDR_SFC_CS 31 | ||
| 416 | #define BM_CPM_SSICDR_SFC_CS 0x80000000 | ||
| 417 | #define BV_CPM_SSICDR_SFC_CS__SCLK_A 0x0 | ||
| 418 | #define BV_CPM_SSICDR_SFC_CS__MPLL 0x1 | ||
| 419 | #define BF_CPM_SSICDR_SFC_CS(v) (((v) & 0x1) << 31) | ||
| 420 | #define BFM_CPM_SSICDR_SFC_CS(v) BM_CPM_SSICDR_SFC_CS | ||
| 421 | #define BF_CPM_SSICDR_SFC_CS_V(e) BF_CPM_SSICDR_SFC_CS(BV_CPM_SSICDR_SFC_CS__##e) | ||
| 422 | #define BFM_CPM_SSICDR_SFC_CS_V(v) BM_CPM_SSICDR_SFC_CS | ||
| 423 | #define BP_CPM_SSICDR_SSI_CS 30 | ||
| 424 | #define BM_CPM_SSICDR_SSI_CS 0x40000000 | ||
| 425 | #define BV_CPM_SSICDR_SSI_CS__EXCLK 0x0 | ||
| 426 | #define BV_CPM_SSICDR_SSI_CS__HALF_SFC 0x1 | ||
| 427 | #define BF_CPM_SSICDR_SSI_CS(v) (((v) & 0x1) << 30) | ||
| 428 | #define BFM_CPM_SSICDR_SSI_CS(v) BM_CPM_SSICDR_SSI_CS | ||
| 429 | #define BF_CPM_SSICDR_SSI_CS_V(e) BF_CPM_SSICDR_SSI_CS(BV_CPM_SSICDR_SSI_CS__##e) | ||
| 430 | #define BFM_CPM_SSICDR_SSI_CS_V(v) BM_CPM_SSICDR_SSI_CS | ||
| 431 | #define BP_CPM_SSICDR_CE 29 | ||
| 432 | #define BM_CPM_SSICDR_CE 0x20000000 | ||
| 433 | #define BF_CPM_SSICDR_CE(v) (((v) & 0x1) << 29) | ||
| 434 | #define BFM_CPM_SSICDR_CE(v) BM_CPM_SSICDR_CE | ||
| 435 | #define BF_CPM_SSICDR_CE_V(e) BF_CPM_SSICDR_CE(BV_CPM_SSICDR_CE__##e) | ||
| 436 | #define BFM_CPM_SSICDR_CE_V(v) BM_CPM_SSICDR_CE | ||
| 437 | #define BP_CPM_SSICDR_BUSY 28 | ||
| 438 | #define BM_CPM_SSICDR_BUSY 0x10000000 | ||
| 439 | #define BF_CPM_SSICDR_BUSY(v) (((v) & 0x1) << 28) | ||
| 440 | #define BFM_CPM_SSICDR_BUSY(v) BM_CPM_SSICDR_BUSY | ||
| 441 | #define BF_CPM_SSICDR_BUSY_V(e) BF_CPM_SSICDR_BUSY(BV_CPM_SSICDR_BUSY__##e) | ||
| 442 | #define BFM_CPM_SSICDR_BUSY_V(v) BM_CPM_SSICDR_BUSY | ||
| 443 | #define BP_CPM_SSICDR_STOP 27 | ||
| 444 | #define BM_CPM_SSICDR_STOP 0x8000000 | ||
| 445 | #define BF_CPM_SSICDR_STOP(v) (((v) & 0x1) << 27) | ||
| 446 | #define BFM_CPM_SSICDR_STOP(v) BM_CPM_SSICDR_STOP | ||
| 447 | #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) | ||
| 448 | #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP | ||
| 449 | |||
| 450 | #define REG_CPM_DRCG jz_reg(CPM_DRCG) | ||
| 451 | #define JA_CPM_DRCG (0xb0000000 + 0xd0) | ||
| 452 | #define JT_CPM_DRCG JIO_32_RW | ||
| 453 | #define JN_CPM_DRCG CPM_DRCG | ||
| 454 | #define JI_CPM_DRCG | ||
| 455 | |||
| 456 | #define REG_CPM_APCR jz_reg(CPM_APCR) | ||
| 457 | #define JA_CPM_APCR (0xb0000000 + 0x10) | ||
| 458 | #define JT_CPM_APCR JIO_32_RW | ||
| 459 | #define JN_CPM_APCR CPM_APCR | ||
| 460 | #define JI_CPM_APCR | ||
| 461 | #define BP_CPM_APCR_PLLM 24 | ||
| 462 | #define BM_CPM_APCR_PLLM 0x7f000000 | ||
| 463 | #define BF_CPM_APCR_PLLM(v) (((v) & 0x7f) << 24) | ||
| 464 | #define BFM_CPM_APCR_PLLM(v) BM_CPM_APCR_PLLM | ||
| 465 | #define BF_CPM_APCR_PLLM_V(e) BF_CPM_APCR_PLLM(BV_CPM_APCR_PLLM__##e) | ||
| 466 | #define BFM_CPM_APCR_PLLM_V(v) BM_CPM_APCR_PLLM | ||
| 467 | #define BP_CPM_APCR_PLLN 18 | ||
| 468 | #define BM_CPM_APCR_PLLN 0x7c0000 | ||
| 469 | #define BF_CPM_APCR_PLLN(v) (((v) & 0x1f) << 18) | ||
| 470 | #define BFM_CPM_APCR_PLLN(v) BM_CPM_APCR_PLLN | ||
| 471 | #define BF_CPM_APCR_PLLN_V(e) BF_CPM_APCR_PLLN(BV_CPM_APCR_PLLN__##e) | ||
| 472 | #define BFM_CPM_APCR_PLLN_V(v) BM_CPM_APCR_PLLN | ||
| 473 | #define BP_CPM_APCR_PLLOD 16 | ||
| 474 | #define BM_CPM_APCR_PLLOD 0x30000 | ||
| 475 | #define BF_CPM_APCR_PLLOD(v) (((v) & 0x3) << 16) | ||
| 476 | #define BFM_CPM_APCR_PLLOD(v) BM_CPM_APCR_PLLOD | ||
| 477 | #define BF_CPM_APCR_PLLOD_V(e) BF_CPM_APCR_PLLOD(BV_CPM_APCR_PLLOD__##e) | ||
| 478 | #define BFM_CPM_APCR_PLLOD_V(v) BM_CPM_APCR_PLLOD | ||
| 479 | #define BP_CPM_APCR_PLLST 0 | ||
| 480 | #define BM_CPM_APCR_PLLST 0xff | ||
| 481 | #define BF_CPM_APCR_PLLST(v) (((v) & 0xff) << 0) | ||
| 482 | #define BFM_CPM_APCR_PLLST(v) BM_CPM_APCR_PLLST | ||
| 483 | #define BF_CPM_APCR_PLLST_V(e) BF_CPM_APCR_PLLST(BV_CPM_APCR_PLLST__##e) | ||
| 484 | #define BFM_CPM_APCR_PLLST_V(v) BM_CPM_APCR_PLLST | ||
| 485 | #define BP_CPM_APCR_BS 31 | ||
| 486 | #define BM_CPM_APCR_BS 0x80000000 | ||
| 487 | #define BF_CPM_APCR_BS(v) (((v) & 0x1) << 31) | ||
| 488 | #define BFM_CPM_APCR_BS(v) BM_CPM_APCR_BS | ||
| 489 | #define BF_CPM_APCR_BS_V(e) BF_CPM_APCR_BS(BV_CPM_APCR_BS__##e) | ||
| 490 | #define BFM_CPM_APCR_BS_V(v) BM_CPM_APCR_BS | ||
| 491 | #define BP_CPM_APCR_LOCK 15 | ||
| 492 | #define BM_CPM_APCR_LOCK 0x8000 | ||
| 493 | #define BF_CPM_APCR_LOCK(v) (((v) & 0x1) << 15) | ||
| 494 | #define BFM_CPM_APCR_LOCK(v) BM_CPM_APCR_LOCK | ||
| 495 | #define BF_CPM_APCR_LOCK_V(e) BF_CPM_APCR_LOCK(BV_CPM_APCR_LOCK__##e) | ||
| 496 | #define BFM_CPM_APCR_LOCK_V(v) BM_CPM_APCR_LOCK | ||
| 497 | #define BP_CPM_APCR_ON 10 | ||
| 498 | #define BM_CPM_APCR_ON 0x400 | ||
| 499 | #define BF_CPM_APCR_ON(v) (((v) & 0x1) << 10) | ||
| 500 | #define BFM_CPM_APCR_ON(v) BM_CPM_APCR_ON | ||
| 501 | #define BF_CPM_APCR_ON_V(e) BF_CPM_APCR_ON(BV_CPM_APCR_ON__##e) | ||
| 502 | #define BFM_CPM_APCR_ON_V(v) BM_CPM_APCR_ON | ||
| 503 | #define BP_CPM_APCR_BYPASS 9 | ||
| 504 | #define BM_CPM_APCR_BYPASS 0x200 | ||
| 505 | #define BF_CPM_APCR_BYPASS(v) (((v) & 0x1) << 9) | ||
| 506 | #define BFM_CPM_APCR_BYPASS(v) BM_CPM_APCR_BYPASS | ||
| 507 | #define BF_CPM_APCR_BYPASS_V(e) BF_CPM_APCR_BYPASS(BV_CPM_APCR_BYPASS__##e) | ||
| 508 | #define BFM_CPM_APCR_BYPASS_V(v) BM_CPM_APCR_BYPASS | ||
| 509 | #define BP_CPM_APCR_ENABLE 8 | ||
| 510 | #define BM_CPM_APCR_ENABLE 0x100 | ||
| 511 | #define BF_CPM_APCR_ENABLE(v) (((v) & 0x1) << 8) | ||
| 512 | #define BFM_CPM_APCR_ENABLE(v) BM_CPM_APCR_ENABLE | ||
| 513 | #define BF_CPM_APCR_ENABLE_V(e) BF_CPM_APCR_ENABLE(BV_CPM_APCR_ENABLE__##e) | ||
| 514 | #define BFM_CPM_APCR_ENABLE_V(v) BM_CPM_APCR_ENABLE | ||
| 515 | |||
| 516 | #define REG_CPM_MPCR jz_reg(CPM_MPCR) | ||
| 517 | #define JA_CPM_MPCR (0xb0000000 + 0x14) | ||
| 518 | #define JT_CPM_MPCR JIO_32_RW | ||
| 519 | #define JN_CPM_MPCR CPM_MPCR | ||
| 520 | #define JI_CPM_MPCR | ||
| 521 | #define BP_CPM_MPCR_PLLM 24 | ||
| 522 | #define BM_CPM_MPCR_PLLM 0x7f000000 | ||
| 523 | #define BF_CPM_MPCR_PLLM(v) (((v) & 0x7f) << 24) | ||
| 524 | #define BFM_CPM_MPCR_PLLM(v) BM_CPM_MPCR_PLLM | ||
| 525 | #define BF_CPM_MPCR_PLLM_V(e) BF_CPM_MPCR_PLLM(BV_CPM_MPCR_PLLM__##e) | ||
| 526 | #define BFM_CPM_MPCR_PLLM_V(v) BM_CPM_MPCR_PLLM | ||
| 527 | #define BP_CPM_MPCR_PLLN 18 | ||
| 528 | #define BM_CPM_MPCR_PLLN 0x7c0000 | ||
| 529 | #define BF_CPM_MPCR_PLLN(v) (((v) & 0x1f) << 18) | ||
| 530 | #define BFM_CPM_MPCR_PLLN(v) BM_CPM_MPCR_PLLN | ||
| 531 | #define BF_CPM_MPCR_PLLN_V(e) BF_CPM_MPCR_PLLN(BV_CPM_MPCR_PLLN__##e) | ||
| 532 | #define BFM_CPM_MPCR_PLLN_V(v) BM_CPM_MPCR_PLLN | ||
| 533 | #define BP_CPM_MPCR_PLLOD 16 | ||
| 534 | #define BM_CPM_MPCR_PLLOD 0x30000 | ||
| 535 | #define BF_CPM_MPCR_PLLOD(v) (((v) & 0x3) << 16) | ||
| 536 | #define BFM_CPM_MPCR_PLLOD(v) BM_CPM_MPCR_PLLOD | ||
| 537 | #define BF_CPM_MPCR_PLLOD_V(e) BF_CPM_MPCR_PLLOD(BV_CPM_MPCR_PLLOD__##e) | ||
| 538 | #define BFM_CPM_MPCR_PLLOD_V(v) BM_CPM_MPCR_PLLOD | ||
| 539 | #define BP_CPM_MPCR_BS 31 | ||
| 540 | #define BM_CPM_MPCR_BS 0x80000000 | ||
| 541 | #define BF_CPM_MPCR_BS(v) (((v) & 0x1) << 31) | ||
| 542 | #define BFM_CPM_MPCR_BS(v) BM_CPM_MPCR_BS | ||
| 543 | #define BF_CPM_MPCR_BS_V(e) BF_CPM_MPCR_BS(BV_CPM_MPCR_BS__##e) | ||
| 544 | #define BFM_CPM_MPCR_BS_V(v) BM_CPM_MPCR_BS | ||
| 545 | #define BP_CPM_MPCR_ENABLE 7 | ||
| 546 | #define BM_CPM_MPCR_ENABLE 0x80 | ||
| 547 | #define BF_CPM_MPCR_ENABLE(v) (((v) & 0x1) << 7) | ||
| 548 | #define BFM_CPM_MPCR_ENABLE(v) BM_CPM_MPCR_ENABLE | ||
| 549 | #define BF_CPM_MPCR_ENABLE_V(e) BF_CPM_MPCR_ENABLE(BV_CPM_MPCR_ENABLE__##e) | ||
| 550 | #define BFM_CPM_MPCR_ENABLE_V(v) BM_CPM_MPCR_ENABLE | ||
| 551 | #define BP_CPM_MPCR_BYPASS 6 | ||
| 552 | #define BM_CPM_MPCR_BYPASS 0x40 | ||
| 553 | #define BF_CPM_MPCR_BYPASS(v) (((v) & 0x1) << 6) | ||
| 554 | #define BFM_CPM_MPCR_BYPASS(v) BM_CPM_MPCR_BYPASS | ||
| 555 | #define BF_CPM_MPCR_BYPASS_V(e) BF_CPM_MPCR_BYPASS(BV_CPM_MPCR_BYPASS__##e) | ||
| 556 | #define BFM_CPM_MPCR_BYPASS_V(v) BM_CPM_MPCR_BYPASS | ||
| 557 | #define BP_CPM_MPCR_LOCK 1 | ||
| 558 | #define BM_CPM_MPCR_LOCK 0x2 | ||
| 559 | #define BF_CPM_MPCR_LOCK(v) (((v) & 0x1) << 1) | ||
| 560 | #define BFM_CPM_MPCR_LOCK(v) BM_CPM_MPCR_LOCK | ||
| 561 | #define BF_CPM_MPCR_LOCK_V(e) BF_CPM_MPCR_LOCK(BV_CPM_MPCR_LOCK__##e) | ||
| 562 | #define BFM_CPM_MPCR_LOCK_V(v) BM_CPM_MPCR_LOCK | ||
| 563 | #define BP_CPM_MPCR_ON 0 | ||
| 564 | #define BM_CPM_MPCR_ON 0x1 | ||
| 565 | #define BF_CPM_MPCR_ON(v) (((v) & 0x1) << 0) | ||
| 566 | #define BFM_CPM_MPCR_ON(v) BM_CPM_MPCR_ON | ||
| 567 | #define BF_CPM_MPCR_ON_V(e) BF_CPM_MPCR_ON(BV_CPM_MPCR_ON__##e) | ||
| 568 | #define BFM_CPM_MPCR_ON_V(v) BM_CPM_MPCR_ON | ||
| 569 | |||
| 570 | #define REG_CPM_LCR jz_reg(CPM_LCR) | ||
| 571 | #define JA_CPM_LCR (0xb0000000 + 0x4) | ||
| 572 | #define JT_CPM_LCR JIO_32_RW | ||
| 573 | #define JN_CPM_LCR CPM_LCR | ||
| 574 | #define JI_CPM_LCR | ||
| 575 | #define BP_CPM_LCR_PST 8 | ||
| 576 | #define BM_CPM_LCR_PST 0xfff00 | ||
| 577 | #define BF_CPM_LCR_PST(v) (((v) & 0xfff) << 8) | ||
| 578 | #define BFM_CPM_LCR_PST(v) BM_CPM_LCR_PST | ||
| 579 | #define BF_CPM_LCR_PST_V(e) BF_CPM_LCR_PST(BV_CPM_LCR_PST__##e) | ||
| 580 | #define BFM_CPM_LCR_PST_V(v) BM_CPM_LCR_PST | ||
| 581 | #define BP_CPM_LCR_LPM 0 | ||
| 582 | #define BM_CPM_LCR_LPM 0x3 | ||
| 583 | #define BV_CPM_LCR_LPM__IDLE 0x0 | ||
| 584 | #define BV_CPM_LCR_LPM__SLEEP 0x1 | ||
| 585 | #define BF_CPM_LCR_LPM(v) (((v) & 0x3) << 0) | ||
| 586 | #define BFM_CPM_LCR_LPM(v) BM_CPM_LCR_LPM | ||
| 587 | #define BF_CPM_LCR_LPM_V(e) BF_CPM_LCR_LPM(BV_CPM_LCR_LPM__##e) | ||
| 588 | #define BFM_CPM_LCR_LPM_V(v) BM_CPM_LCR_LPM | ||
| 589 | |||
| 590 | #define REG_CPM_PSWC0ST jz_reg(CPM_PSWC0ST) | ||
| 591 | #define JA_CPM_PSWC0ST (0xb0000000 + 0x90) | ||
| 592 | #define JT_CPM_PSWC0ST JIO_32_RW | ||
| 593 | #define JN_CPM_PSWC0ST CPM_PSWC0ST | ||
| 594 | #define JI_CPM_PSWC0ST | ||
| 595 | |||
| 596 | #define REG_CPM_PSWC1ST jz_reg(CPM_PSWC1ST) | ||
| 597 | #define JA_CPM_PSWC1ST (0xb0000000 + 0x94) | ||
| 598 | #define JT_CPM_PSWC1ST JIO_32_RW | ||
| 599 | #define JN_CPM_PSWC1ST CPM_PSWC1ST | ||
| 600 | #define JI_CPM_PSWC1ST | ||
| 601 | |||
| 602 | #define REG_CPM_PSWC2ST jz_reg(CPM_PSWC2ST) | ||
| 603 | #define JA_CPM_PSWC2ST (0xb0000000 + 0x98) | ||
| 604 | #define JT_CPM_PSWC2ST JIO_32_RW | ||
| 605 | #define JN_CPM_PSWC2ST CPM_PSWC2ST | ||
| 606 | #define JI_CPM_PSWC2ST | ||
| 607 | |||
| 608 | #define REG_CPM_PSWC3ST jz_reg(CPM_PSWC3ST) | ||
| 609 | #define JA_CPM_PSWC3ST (0xb0000000 + 0x9c) | ||
| 610 | #define JT_CPM_PSWC3ST JIO_32_RW | ||
| 611 | #define JN_CPM_PSWC3ST CPM_PSWC3ST | ||
| 612 | #define JI_CPM_PSWC3ST | ||
| 613 | |||
| 614 | #define REG_CPM_CLKGR jz_reg(CPM_CLKGR) | ||
| 615 | #define JA_CPM_CLKGR (0xb0000000 + 0x20) | ||
| 616 | #define JT_CPM_CLKGR JIO_32_RW | ||
| 617 | #define JN_CPM_CLKGR CPM_CLKGR | ||
| 618 | #define JI_CPM_CLKGR | ||
| 619 | #define BP_CPM_CLKGR_DDR 31 | ||
| 620 | #define BM_CPM_CLKGR_DDR 0x80000000 | ||
| 621 | #define BF_CPM_CLKGR_DDR(v) (((v) & 0x1) << 31) | ||
| 622 | #define BFM_CPM_CLKGR_DDR(v) BM_CPM_CLKGR_DDR | ||
| 623 | #define BF_CPM_CLKGR_DDR_V(e) BF_CPM_CLKGR_DDR(BV_CPM_CLKGR_DDR__##e) | ||
| 624 | #define BFM_CPM_CLKGR_DDR_V(v) BM_CPM_CLKGR_DDR | ||
| 625 | #define BP_CPM_CLKGR_CPU_BIT 30 | ||
| 626 | #define BM_CPM_CLKGR_CPU_BIT 0x40000000 | ||
| 627 | #define BF_CPM_CLKGR_CPU_BIT(v) (((v) & 0x1) << 30) | ||
| 628 | #define BFM_CPM_CLKGR_CPU_BIT(v) BM_CPM_CLKGR_CPU_BIT | ||
| 629 | #define BF_CPM_CLKGR_CPU_BIT_V(e) BF_CPM_CLKGR_CPU_BIT(BV_CPM_CLKGR_CPU_BIT__##e) | ||
| 630 | #define BFM_CPM_CLKGR_CPU_BIT_V(v) BM_CPM_CLKGR_CPU_BIT | ||
| 631 | #define BP_CPM_CLKGR_AHB0 29 | ||
| 632 | #define BM_CPM_CLKGR_AHB0 0x20000000 | ||
| 633 | #define BF_CPM_CLKGR_AHB0(v) (((v) & 0x1) << 29) | ||
| 634 | #define BFM_CPM_CLKGR_AHB0(v) BM_CPM_CLKGR_AHB0 | ||
| 635 | #define BF_CPM_CLKGR_AHB0_V(e) BF_CPM_CLKGR_AHB0(BV_CPM_CLKGR_AHB0__##e) | ||
| 636 | #define BFM_CPM_CLKGR_AHB0_V(v) BM_CPM_CLKGR_AHB0 | ||
| 637 | #define BP_CPM_CLKGR_APB0 28 | ||
| 638 | #define BM_CPM_CLKGR_APB0 0x10000000 | ||
| 639 | #define BF_CPM_CLKGR_APB0(v) (((v) & 0x1) << 28) | ||
| 640 | #define BFM_CPM_CLKGR_APB0(v) BM_CPM_CLKGR_APB0 | ||
| 641 | #define BF_CPM_CLKGR_APB0_V(e) BF_CPM_CLKGR_APB0(BV_CPM_CLKGR_APB0__##e) | ||
| 642 | #define BFM_CPM_CLKGR_APB0_V(v) BM_CPM_CLKGR_APB0 | ||
| 643 | #define BP_CPM_CLKGR_RTC 27 | ||
| 644 | #define BM_CPM_CLKGR_RTC 0x8000000 | ||
| 645 | #define BF_CPM_CLKGR_RTC(v) (((v) & 0x1) << 27) | ||
| 646 | #define BFM_CPM_CLKGR_RTC(v) BM_CPM_CLKGR_RTC | ||
| 647 | #define BF_CPM_CLKGR_RTC_V(e) BF_CPM_CLKGR_RTC(BV_CPM_CLKGR_RTC__##e) | ||
| 648 | #define BFM_CPM_CLKGR_RTC_V(v) BM_CPM_CLKGR_RTC | ||
| 649 | #define BP_CPM_CLKGR_PCM 26 | ||
| 650 | #define BM_CPM_CLKGR_PCM 0x4000000 | ||
| 651 | #define BF_CPM_CLKGR_PCM(v) (((v) & 0x1) << 26) | ||
| 652 | #define BFM_CPM_CLKGR_PCM(v) BM_CPM_CLKGR_PCM | ||
| 653 | #define BF_CPM_CLKGR_PCM_V(e) BF_CPM_CLKGR_PCM(BV_CPM_CLKGR_PCM__##e) | ||
| 654 | #define BFM_CPM_CLKGR_PCM_V(v) BM_CPM_CLKGR_PCM | ||
| 655 | #define BP_CPM_CLKGR_MAC 25 | ||
| 656 | #define BM_CPM_CLKGR_MAC 0x2000000 | ||
| 657 | #define BF_CPM_CLKGR_MAC(v) (((v) & 0x1) << 25) | ||
| 658 | #define BFM_CPM_CLKGR_MAC(v) BM_CPM_CLKGR_MAC | ||
| 659 | #define BF_CPM_CLKGR_MAC_V(e) BF_CPM_CLKGR_MAC(BV_CPM_CLKGR_MAC__##e) | ||
| 660 | #define BFM_CPM_CLKGR_MAC_V(v) BM_CPM_CLKGR_MAC | ||
| 661 | #define BP_CPM_CLKGR_AES 24 | ||
| 662 | #define BM_CPM_CLKGR_AES 0x1000000 | ||
| 663 | #define BF_CPM_CLKGR_AES(v) (((v) & 0x1) << 24) | ||
| 664 | #define BFM_CPM_CLKGR_AES(v) BM_CPM_CLKGR_AES | ||
| 665 | #define BF_CPM_CLKGR_AES_V(e) BF_CPM_CLKGR_AES(BV_CPM_CLKGR_AES__##e) | ||
| 666 | #define BFM_CPM_CLKGR_AES_V(v) BM_CPM_CLKGR_AES | ||
| 667 | #define BP_CPM_CLKGR_LCD 23 | ||
| 668 | #define BM_CPM_CLKGR_LCD 0x800000 | ||
| 669 | #define BF_CPM_CLKGR_LCD(v) (((v) & 0x1) << 23) | ||
| 670 | #define BFM_CPM_CLKGR_LCD(v) BM_CPM_CLKGR_LCD | ||
| 671 | #define BF_CPM_CLKGR_LCD_V(e) BF_CPM_CLKGR_LCD(BV_CPM_CLKGR_LCD__##e) | ||
| 672 | #define BFM_CPM_CLKGR_LCD_V(v) BM_CPM_CLKGR_LCD | ||
| 673 | #define BP_CPM_CLKGR_CIM 22 | ||
| 674 | #define BM_CPM_CLKGR_CIM 0x400000 | ||
| 675 | #define BF_CPM_CLKGR_CIM(v) (((v) & 0x1) << 22) | ||
| 676 | #define BFM_CPM_CLKGR_CIM(v) BM_CPM_CLKGR_CIM | ||
| 677 | #define BF_CPM_CLKGR_CIM_V(e) BF_CPM_CLKGR_CIM(BV_CPM_CLKGR_CIM__##e) | ||
| 678 | #define BFM_CPM_CLKGR_CIM_V(v) BM_CPM_CLKGR_CIM | ||
| 679 | #define BP_CPM_CLKGR_PDMA 21 | ||
| 680 | #define BM_CPM_CLKGR_PDMA 0x200000 | ||
| 681 | #define BF_CPM_CLKGR_PDMA(v) (((v) & 0x1) << 21) | ||
| 682 | #define BFM_CPM_CLKGR_PDMA(v) BM_CPM_CLKGR_PDMA | ||
| 683 | #define BF_CPM_CLKGR_PDMA_V(e) BF_CPM_CLKGR_PDMA(BV_CPM_CLKGR_PDMA__##e) | ||
| 684 | #define BFM_CPM_CLKGR_PDMA_V(v) BM_CPM_CLKGR_PDMA | ||
| 685 | #define BP_CPM_CLKGR_OST 20 | ||
| 686 | #define BM_CPM_CLKGR_OST 0x100000 | ||
| 687 | #define BF_CPM_CLKGR_OST(v) (((v) & 0x1) << 20) | ||
| 688 | #define BFM_CPM_CLKGR_OST(v) BM_CPM_CLKGR_OST | ||
| 689 | #define BF_CPM_CLKGR_OST_V(e) BF_CPM_CLKGR_OST(BV_CPM_CLKGR_OST__##e) | ||
| 690 | #define BFM_CPM_CLKGR_OST_V(v) BM_CPM_CLKGR_OST | ||
| 691 | #define BP_CPM_CLKGR_SSI 19 | ||
| 692 | #define BM_CPM_CLKGR_SSI 0x80000 | ||
| 693 | #define BF_CPM_CLKGR_SSI(v) (((v) & 0x1) << 19) | ||
| 694 | #define BFM_CPM_CLKGR_SSI(v) BM_CPM_CLKGR_SSI | ||
| 695 | #define BF_CPM_CLKGR_SSI_V(e) BF_CPM_CLKGR_SSI(BV_CPM_CLKGR_SSI__##e) | ||
| 696 | #define BFM_CPM_CLKGR_SSI_V(v) BM_CPM_CLKGR_SSI | ||
| 697 | #define BP_CPM_CLKGR_TCU 18 | ||
| 698 | #define BM_CPM_CLKGR_TCU 0x40000 | ||
| 699 | #define BF_CPM_CLKGR_TCU(v) (((v) & 0x1) << 18) | ||
| 700 | #define BFM_CPM_CLKGR_TCU(v) BM_CPM_CLKGR_TCU | ||
| 701 | #define BF_CPM_CLKGR_TCU_V(e) BF_CPM_CLKGR_TCU(BV_CPM_CLKGR_TCU__##e) | ||
| 702 | #define BFM_CPM_CLKGR_TCU_V(v) BM_CPM_CLKGR_TCU | ||
| 703 | #define BP_CPM_CLKGR_DMIC 17 | ||
| 704 | #define BM_CPM_CLKGR_DMIC 0x20000 | ||
| 705 | #define BF_CPM_CLKGR_DMIC(v) (((v) & 0x1) << 17) | ||
| 706 | #define BFM_CPM_CLKGR_DMIC(v) BM_CPM_CLKGR_DMIC | ||
| 707 | #define BF_CPM_CLKGR_DMIC_V(e) BF_CPM_CLKGR_DMIC(BV_CPM_CLKGR_DMIC__##e) | ||
| 708 | #define BFM_CPM_CLKGR_DMIC_V(v) BM_CPM_CLKGR_DMIC | ||
| 709 | #define BP_CPM_CLKGR_UART2 16 | ||
| 710 | #define BM_CPM_CLKGR_UART2 0x10000 | ||
| 711 | #define BF_CPM_CLKGR_UART2(v) (((v) & 0x1) << 16) | ||
| 712 | #define BFM_CPM_CLKGR_UART2(v) BM_CPM_CLKGR_UART2 | ||
| 713 | #define BF_CPM_CLKGR_UART2_V(e) BF_CPM_CLKGR_UART2(BV_CPM_CLKGR_UART2__##e) | ||
| 714 | #define BFM_CPM_CLKGR_UART2_V(v) BM_CPM_CLKGR_UART2 | ||
| 715 | #define BP_CPM_CLKGR_UART1 15 | ||
| 716 | #define BM_CPM_CLKGR_UART1 0x8000 | ||
| 717 | #define BF_CPM_CLKGR_UART1(v) (((v) & 0x1) << 15) | ||
| 718 | #define BFM_CPM_CLKGR_UART1(v) BM_CPM_CLKGR_UART1 | ||
| 719 | #define BF_CPM_CLKGR_UART1_V(e) BF_CPM_CLKGR_UART1(BV_CPM_CLKGR_UART1__##e) | ||
| 720 | #define BFM_CPM_CLKGR_UART1_V(v) BM_CPM_CLKGR_UART1 | ||
| 721 | #define BP_CPM_CLKGR_UART0 14 | ||
| 722 | #define BM_CPM_CLKGR_UART0 0x4000 | ||
| 723 | #define BF_CPM_CLKGR_UART0(v) (((v) & 0x1) << 14) | ||
| 724 | #define BFM_CPM_CLKGR_UART0(v) BM_CPM_CLKGR_UART0 | ||
| 725 | #define BF_CPM_CLKGR_UART0_V(e) BF_CPM_CLKGR_UART0(BV_CPM_CLKGR_UART0__##e) | ||
| 726 | #define BFM_CPM_CLKGR_UART0_V(v) BM_CPM_CLKGR_UART0 | ||
| 727 | #define BP_CPM_CLKGR_JPEG 12 | ||
| 728 | #define BM_CPM_CLKGR_JPEG 0x1000 | ||
| 729 | #define BF_CPM_CLKGR_JPEG(v) (((v) & 0x1) << 12) | ||
| 730 | #define BFM_CPM_CLKGR_JPEG(v) BM_CPM_CLKGR_JPEG | ||
| 731 | #define BF_CPM_CLKGR_JPEG_V(e) BF_CPM_CLKGR_JPEG(BV_CPM_CLKGR_JPEG__##e) | ||
| 732 | #define BFM_CPM_CLKGR_JPEG_V(v) BM_CPM_CLKGR_JPEG | ||
| 733 | #define BP_CPM_CLKGR_AIC 11 | ||
| 734 | #define BM_CPM_CLKGR_AIC 0x800 | ||
| 735 | #define BF_CPM_CLKGR_AIC(v) (((v) & 0x1) << 11) | ||
| 736 | #define BFM_CPM_CLKGR_AIC(v) BM_CPM_CLKGR_AIC | ||
| 737 | #define BF_CPM_CLKGR_AIC_V(e) BF_CPM_CLKGR_AIC(BV_CPM_CLKGR_AIC__##e) | ||
| 738 | #define BFM_CPM_CLKGR_AIC_V(v) BM_CPM_CLKGR_AIC | ||
| 739 | #define BP_CPM_CLKGR_I2C2 9 | ||
| 740 | #define BM_CPM_CLKGR_I2C2 0x200 | ||
| 741 | #define BF_CPM_CLKGR_I2C2(v) (((v) & 0x1) << 9) | ||
| 742 | #define BFM_CPM_CLKGR_I2C2(v) BM_CPM_CLKGR_I2C2 | ||
| 743 | #define BF_CPM_CLKGR_I2C2_V(e) BF_CPM_CLKGR_I2C2(BV_CPM_CLKGR_I2C2__##e) | ||
| 744 | #define BFM_CPM_CLKGR_I2C2_V(v) BM_CPM_CLKGR_I2C2 | ||
| 745 | #define BP_CPM_CLKGR_I2C1 8 | ||
| 746 | #define BM_CPM_CLKGR_I2C1 0x100 | ||
| 747 | #define BF_CPM_CLKGR_I2C1(v) (((v) & 0x1) << 8) | ||
| 748 | #define BFM_CPM_CLKGR_I2C1(v) BM_CPM_CLKGR_I2C1 | ||
| 749 | #define BF_CPM_CLKGR_I2C1_V(e) BF_CPM_CLKGR_I2C1(BV_CPM_CLKGR_I2C1__##e) | ||
| 750 | #define BFM_CPM_CLKGR_I2C1_V(v) BM_CPM_CLKGR_I2C1 | ||
| 751 | #define BP_CPM_CLKGR_I2C0 7 | ||
| 752 | #define BM_CPM_CLKGR_I2C0 0x80 | ||
| 753 | #define BF_CPM_CLKGR_I2C0(v) (((v) & 0x1) << 7) | ||
| 754 | #define BFM_CPM_CLKGR_I2C0(v) BM_CPM_CLKGR_I2C0 | ||
| 755 | #define BF_CPM_CLKGR_I2C0_V(e) BF_CPM_CLKGR_I2C0(BV_CPM_CLKGR_I2C0__##e) | ||
| 756 | #define BFM_CPM_CLKGR_I2C0_V(v) BM_CPM_CLKGR_I2C0 | ||
| 757 | #define BP_CPM_CLKGR_SCC 6 | ||
| 758 | #define BM_CPM_CLKGR_SCC 0x40 | ||
| 759 | #define BF_CPM_CLKGR_SCC(v) (((v) & 0x1) << 6) | ||
| 760 | #define BFM_CPM_CLKGR_SCC(v) BM_CPM_CLKGR_SCC | ||
| 761 | #define BF_CPM_CLKGR_SCC_V(e) BF_CPM_CLKGR_SCC(BV_CPM_CLKGR_SCC__##e) | ||
| 762 | #define BFM_CPM_CLKGR_SCC_V(v) BM_CPM_CLKGR_SCC | ||
| 763 | #define BP_CPM_CLKGR_MSC1 5 | ||
| 764 | #define BM_CPM_CLKGR_MSC1 0x20 | ||
| 765 | #define BF_CPM_CLKGR_MSC1(v) (((v) & 0x1) << 5) | ||
| 766 | #define BFM_CPM_CLKGR_MSC1(v) BM_CPM_CLKGR_MSC1 | ||
| 767 | #define BF_CPM_CLKGR_MSC1_V(e) BF_CPM_CLKGR_MSC1(BV_CPM_CLKGR_MSC1__##e) | ||
| 768 | #define BFM_CPM_CLKGR_MSC1_V(v) BM_CPM_CLKGR_MSC1 | ||
| 769 | #define BP_CPM_CLKGR_MSC0 4 | ||
| 770 | #define BM_CPM_CLKGR_MSC0 0x10 | ||
| 771 | #define BF_CPM_CLKGR_MSC0(v) (((v) & 0x1) << 4) | ||
| 772 | #define BFM_CPM_CLKGR_MSC0(v) BM_CPM_CLKGR_MSC0 | ||
| 773 | #define BF_CPM_CLKGR_MSC0_V(e) BF_CPM_CLKGR_MSC0(BV_CPM_CLKGR_MSC0__##e) | ||
| 774 | #define BFM_CPM_CLKGR_MSC0_V(v) BM_CPM_CLKGR_MSC0 | ||
| 775 | #define BP_CPM_CLKGR_OTG 3 | ||
| 776 | #define BM_CPM_CLKGR_OTG 0x8 | ||
| 777 | #define BF_CPM_CLKGR_OTG(v) (((v) & 0x1) << 3) | ||
| 778 | #define BFM_CPM_CLKGR_OTG(v) BM_CPM_CLKGR_OTG | ||
| 779 | #define BF_CPM_CLKGR_OTG_V(e) BF_CPM_CLKGR_OTG(BV_CPM_CLKGR_OTG__##e) | ||
| 780 | #define BFM_CPM_CLKGR_OTG_V(v) BM_CPM_CLKGR_OTG | ||
| 781 | #define BP_CPM_CLKGR_SFC 2 | ||
| 782 | #define BM_CPM_CLKGR_SFC 0x4 | ||
| 783 | #define BF_CPM_CLKGR_SFC(v) (((v) & 0x1) << 2) | ||
| 784 | #define BFM_CPM_CLKGR_SFC(v) BM_CPM_CLKGR_SFC | ||
| 785 | #define BF_CPM_CLKGR_SFC_V(e) BF_CPM_CLKGR_SFC(BV_CPM_CLKGR_SFC__##e) | ||
| 786 | #define BFM_CPM_CLKGR_SFC_V(v) BM_CPM_CLKGR_SFC | ||
| 787 | #define BP_CPM_CLKGR_EFUSE 1 | ||
| 788 | #define BM_CPM_CLKGR_EFUSE 0x2 | ||
| 789 | #define BF_CPM_CLKGR_EFUSE(v) (((v) & 0x1) << 1) | ||
| 790 | #define BFM_CPM_CLKGR_EFUSE(v) BM_CPM_CLKGR_EFUSE | ||
| 791 | #define BF_CPM_CLKGR_EFUSE_V(e) BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e) | ||
| 792 | #define BFM_CPM_CLKGR_EFUSE_V(v) BM_CPM_CLKGR_EFUSE | ||
| 793 | |||
| 794 | #define REG_CPM_OPCR jz_reg(CPM_OPCR) | ||
| 795 | #define JA_CPM_OPCR (0xb0000000 + 0x24) | ||
| 796 | #define JT_CPM_OPCR JIO_32_RW | ||
| 797 | #define JN_CPM_OPCR CPM_OPCR | ||
| 798 | #define JI_CPM_OPCR | ||
| 799 | #define BP_CPM_OPCR_O1ST 8 | ||
| 800 | #define BM_CPM_OPCR_O1ST 0xfff00 | ||
| 801 | #define BF_CPM_OPCR_O1ST(v) (((v) & 0xfff) << 8) | ||
| 802 | #define BFM_CPM_OPCR_O1ST(v) BM_CPM_OPCR_O1ST | ||
| 803 | #define BF_CPM_OPCR_O1ST_V(e) BF_CPM_OPCR_O1ST(BV_CPM_OPCR_O1ST__##e) | ||
| 804 | #define BFM_CPM_OPCR_O1ST_V(v) BM_CPM_OPCR_O1ST | ||
| 805 | #define BP_CPM_OPCR_IDLE_DIS 31 | ||
| 806 | #define BM_CPM_OPCR_IDLE_DIS 0x80000000 | ||
| 807 | #define BF_CPM_OPCR_IDLE_DIS(v) (((v) & 0x1) << 31) | ||
| 808 | #define BFM_CPM_OPCR_IDLE_DIS(v) BM_CPM_OPCR_IDLE_DIS | ||
| 809 | #define BF_CPM_OPCR_IDLE_DIS_V(e) BF_CPM_OPCR_IDLE_DIS(BV_CPM_OPCR_IDLE_DIS__##e) | ||
| 810 | #define BFM_CPM_OPCR_IDLE_DIS_V(v) BM_CPM_OPCR_IDLE_DIS | ||
| 811 | #define BP_CPM_OPCR_MASK_INT 30 | ||
| 812 | #define BM_CPM_OPCR_MASK_INT 0x40000000 | ||
| 813 | #define BF_CPM_OPCR_MASK_INT(v) (((v) & 0x1) << 30) | ||
| 814 | #define BFM_CPM_OPCR_MASK_INT(v) BM_CPM_OPCR_MASK_INT | ||
| 815 | #define BF_CPM_OPCR_MASK_INT_V(e) BF_CPM_OPCR_MASK_INT(BV_CPM_OPCR_MASK_INT__##e) | ||
| 816 | #define BFM_CPM_OPCR_MASK_INT_V(v) BM_CPM_OPCR_MASK_INT | ||
| 817 | #define BP_CPM_OPCR_MASK_VPU 29 | ||
| 818 | #define BM_CPM_OPCR_MASK_VPU 0x20000000 | ||
| 819 | #define BF_CPM_OPCR_MASK_VPU(v) (((v) & 0x1) << 29) | ||
| 820 | #define BFM_CPM_OPCR_MASK_VPU(v) BM_CPM_OPCR_MASK_VPU | ||
| 821 | #define BF_CPM_OPCR_MASK_VPU_V(e) BF_CPM_OPCR_MASK_VPU(BV_CPM_OPCR_MASK_VPU__##e) | ||
| 822 | #define BFM_CPM_OPCR_MASK_VPU_V(v) BM_CPM_OPCR_MASK_VPU | ||
| 823 | #define BP_CPM_OPCR_GATE_SCLK_A_BUS 28 | ||
| 824 | #define BM_CPM_OPCR_GATE_SCLK_A_BUS 0x10000000 | ||
| 825 | #define BF_CPM_OPCR_GATE_SCLK_A_BUS(v) (((v) & 0x1) << 28) | ||
| 826 | #define BFM_CPM_OPCR_GATE_SCLK_A_BUS(v) BM_CPM_OPCR_GATE_SCLK_A_BUS | ||
| 827 | #define BF_CPM_OPCR_GATE_SCLK_A_BUS_V(e) BF_CPM_OPCR_GATE_SCLK_A_BUS(BV_CPM_OPCR_GATE_SCLK_A_BUS__##e) | ||
| 828 | #define BFM_CPM_OPCR_GATE_SCLK_A_BUS_V(v) BM_CPM_OPCR_GATE_SCLK_A_BUS | ||
| 829 | #define BP_CPM_OPCR_L2C_PD 25 | ||
| 830 | #define BM_CPM_OPCR_L2C_PD 0x2000000 | ||
| 831 | #define BF_CPM_OPCR_L2C_PD(v) (((v) & 0x1) << 25) | ||
| 832 | #define BFM_CPM_OPCR_L2C_PD(v) BM_CPM_OPCR_L2C_PD | ||
| 833 | #define BF_CPM_OPCR_L2C_PD_V(e) BF_CPM_OPCR_L2C_PD(BV_CPM_OPCR_L2C_PD__##e) | ||
| 834 | #define BFM_CPM_OPCR_L2C_PD_V(v) BM_CPM_OPCR_L2C_PD | ||
| 835 | #define BP_CPM_OPCR_REQ_MODE 24 | ||
| 836 | #define BM_CPM_OPCR_REQ_MODE 0x1000000 | ||
| 837 | #define BF_CPM_OPCR_REQ_MODE(v) (((v) & 0x1) << 24) | ||
| 838 | #define BFM_CPM_OPCR_REQ_MODE(v) BM_CPM_OPCR_REQ_MODE | ||
| 839 | #define BF_CPM_OPCR_REQ_MODE_V(e) BF_CPM_OPCR_REQ_MODE(BV_CPM_OPCR_REQ_MODE__##e) | ||
| 840 | #define BFM_CPM_OPCR_REQ_MODE_V(v) BM_CPM_OPCR_REQ_MODE | ||
| 841 | #define BP_CPM_OPCR_GATE_USBPHY_CLK 23 | ||
| 842 | #define BM_CPM_OPCR_GATE_USBPHY_CLK 0x800000 | ||
| 843 | #define BF_CPM_OPCR_GATE_USBPHY_CLK(v) (((v) & 0x1) << 23) | ||
| 844 | #define BFM_CPM_OPCR_GATE_USBPHY_CLK(v) BM_CPM_OPCR_GATE_USBPHY_CLK | ||
| 845 | #define BF_CPM_OPCR_GATE_USBPHY_CLK_V(e) BF_CPM_OPCR_GATE_USBPHY_CLK(BV_CPM_OPCR_GATE_USBPHY_CLK__##e) | ||
| 846 | #define BFM_CPM_OPCR_GATE_USBPHY_CLK_V(v) BM_CPM_OPCR_GATE_USBPHY_CLK | ||
| 847 | #define BP_CPM_OPCR_DIS_STOP_MUX 22 | ||
| 848 | #define BM_CPM_OPCR_DIS_STOP_MUX 0x400000 | ||
| 849 | #define BF_CPM_OPCR_DIS_STOP_MUX(v) (((v) & 0x1) << 22) | ||
| 850 | #define BFM_CPM_OPCR_DIS_STOP_MUX(v) BM_CPM_OPCR_DIS_STOP_MUX | ||
| 851 | #define BF_CPM_OPCR_DIS_STOP_MUX_V(e) BF_CPM_OPCR_DIS_STOP_MUX(BV_CPM_OPCR_DIS_STOP_MUX__##e) | ||
| 852 | #define BFM_CPM_OPCR_DIS_STOP_MUX_V(v) BM_CPM_OPCR_DIS_STOP_MUX | ||
| 853 | #define BP_CPM_OPCR_SPENDN0 7 | ||
| 854 | #define BM_CPM_OPCR_SPENDN0 0x80 | ||
| 855 | #define BF_CPM_OPCR_SPENDN0(v) (((v) & 0x1) << 7) | ||
| 856 | #define BFM_CPM_OPCR_SPENDN0(v) BM_CPM_OPCR_SPENDN0 | ||
| 857 | #define BF_CPM_OPCR_SPENDN0_V(e) BF_CPM_OPCR_SPENDN0(BV_CPM_OPCR_SPENDN0__##e) | ||
| 858 | #define BFM_CPM_OPCR_SPENDN0_V(v) BM_CPM_OPCR_SPENDN0 | ||
| 859 | #define BP_CPM_OPCR_SPENDN1 6 | ||
| 860 | #define BM_CPM_OPCR_SPENDN1 0x40 | ||
| 861 | #define BF_CPM_OPCR_SPENDN1(v) (((v) & 0x1) << 6) | ||
| 862 | #define BFM_CPM_OPCR_SPENDN1(v) BM_CPM_OPCR_SPENDN1 | ||
| 863 | #define BF_CPM_OPCR_SPENDN1_V(e) BF_CPM_OPCR_SPENDN1(BV_CPM_OPCR_SPENDN1__##e) | ||
| 864 | #define BFM_CPM_OPCR_SPENDN1_V(v) BM_CPM_OPCR_SPENDN1 | ||
| 865 | #define BP_CPM_OPCR_CPU_MODE 5 | ||
| 866 | #define BM_CPM_OPCR_CPU_MODE 0x20 | ||
| 867 | #define BF_CPM_OPCR_CPU_MODE(v) (((v) & 0x1) << 5) | ||
| 868 | #define BFM_CPM_OPCR_CPU_MODE(v) BM_CPM_OPCR_CPU_MODE | ||
| 869 | #define BF_CPM_OPCR_CPU_MODE_V(e) BF_CPM_OPCR_CPU_MODE(BV_CPM_OPCR_CPU_MODE__##e) | ||
| 870 | #define BFM_CPM_OPCR_CPU_MODE_V(v) BM_CPM_OPCR_CPU_MODE | ||
| 871 | #define BP_CPM_OPCR_O1SE 4 | ||
| 872 | #define BM_CPM_OPCR_O1SE 0x10 | ||
| 873 | #define BF_CPM_OPCR_O1SE(v) (((v) & 0x1) << 4) | ||
| 874 | #define BFM_CPM_OPCR_O1SE(v) BM_CPM_OPCR_O1SE | ||
| 875 | #define BF_CPM_OPCR_O1SE_V(e) BF_CPM_OPCR_O1SE(BV_CPM_OPCR_O1SE__##e) | ||
| 876 | #define BFM_CPM_OPCR_O1SE_V(v) BM_CPM_OPCR_O1SE | ||
| 877 | #define BP_CPM_OPCR_PD 3 | ||
| 878 | #define BM_CPM_OPCR_PD 0x8 | ||
| 879 | #define BF_CPM_OPCR_PD(v) (((v) & 0x1) << 3) | ||
| 880 | #define BFM_CPM_OPCR_PD(v) BM_CPM_OPCR_PD | ||
| 881 | #define BF_CPM_OPCR_PD_V(e) BF_CPM_OPCR_PD(BV_CPM_OPCR_PD__##e) | ||
| 882 | #define BFM_CPM_OPCR_PD_V(v) BM_CPM_OPCR_PD | ||
| 883 | #define BP_CPM_OPCR_ERCS 2 | ||
| 884 | #define BM_CPM_OPCR_ERCS 0x4 | ||
| 885 | #define BF_CPM_OPCR_ERCS(v) (((v) & 0x1) << 2) | ||
| 886 | #define BFM_CPM_OPCR_ERCS(v) BM_CPM_OPCR_ERCS | ||
| 887 | #define BF_CPM_OPCR_ERCS_V(e) BF_CPM_OPCR_ERCS(BV_CPM_OPCR_ERCS__##e) | ||
| 888 | #define BFM_CPM_OPCR_ERCS_V(v) BM_CPM_OPCR_ERCS | ||
| 889 | #define BP_CPM_OPCR_BUS_MODE 1 | ||
| 890 | #define BM_CPM_OPCR_BUS_MODE 0x2 | ||
| 891 | #define BF_CPM_OPCR_BUS_MODE(v) (((v) & 0x1) << 1) | ||
| 892 | #define BFM_CPM_OPCR_BUS_MODE(v) BM_CPM_OPCR_BUS_MODE | ||
| 893 | #define BF_CPM_OPCR_BUS_MODE_V(e) BF_CPM_OPCR_BUS_MODE(BV_CPM_OPCR_BUS_MODE__##e) | ||
| 894 | #define BFM_CPM_OPCR_BUS_MODE_V(v) BM_CPM_OPCR_BUS_MODE | ||
| 895 | |||
| 896 | #endif /* __HEADERGEN_CPM_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrc.h b/firmware/target/mips/ingenic_x1000/x1000/ddrc.h new file mode 100644 index 0000000000..f482969a4e --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrc.h | |||
| @@ -0,0 +1,149 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_DDRC_H__ | ||
| 25 | #define __HEADERGEN_DDRC_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_DDRC_STATUS jz_reg(DDRC_STATUS) | ||
| 30 | #define JA_DDRC_STATUS (0xb34f0000 + 0x0) | ||
| 31 | #define JT_DDRC_STATUS JIO_32_RW | ||
| 32 | #define JN_DDRC_STATUS DDRC_STATUS | ||
| 33 | #define JI_DDRC_STATUS | ||
| 34 | |||
| 35 | #define REG_DDRC_CFG jz_reg(DDRC_CFG) | ||
| 36 | #define JA_DDRC_CFG (0xb34f0000 + 0x4) | ||
| 37 | #define JT_DDRC_CFG JIO_32_RW | ||
| 38 | #define JN_DDRC_CFG DDRC_CFG | ||
| 39 | #define JI_DDRC_CFG | ||
| 40 | |||
| 41 | #define REG_DDRC_CTRL jz_reg(DDRC_CTRL) | ||
| 42 | #define JA_DDRC_CTRL (0xb34f0000 + 0x8) | ||
| 43 | #define JT_DDRC_CTRL JIO_32_RW | ||
| 44 | #define JN_DDRC_CTRL DDRC_CTRL | ||
| 45 | #define JI_DDRC_CTRL | ||
| 46 | |||
| 47 | #define REG_DDRC_TIMING1 jz_reg(DDRC_TIMING1) | ||
| 48 | #define JA_DDRC_TIMING1 (0xb34f0000 + 0x60) | ||
| 49 | #define JT_DDRC_TIMING1 JIO_32_RW | ||
| 50 | #define JN_DDRC_TIMING1 DDRC_TIMING1 | ||
| 51 | #define JI_DDRC_TIMING1 | ||
| 52 | |||
| 53 | #define REG_DDRC_TIMING2 jz_reg(DDRC_TIMING2) | ||
| 54 | #define JA_DDRC_TIMING2 (0xb34f0000 + 0x64) | ||
| 55 | #define JT_DDRC_TIMING2 JIO_32_RW | ||
| 56 | #define JN_DDRC_TIMING2 DDRC_TIMING2 | ||
| 57 | #define JI_DDRC_TIMING2 | ||
| 58 | |||
| 59 | #define REG_DDRC_TIMING3 jz_reg(DDRC_TIMING3) | ||
| 60 | #define JA_DDRC_TIMING3 (0xb34f0000 + 0x68) | ||
| 61 | #define JT_DDRC_TIMING3 JIO_32_RW | ||
| 62 | #define JN_DDRC_TIMING3 DDRC_TIMING3 | ||
| 63 | #define JI_DDRC_TIMING3 | ||
| 64 | |||
| 65 | #define REG_DDRC_TIMING4 jz_reg(DDRC_TIMING4) | ||
| 66 | #define JA_DDRC_TIMING4 (0xb34f0000 + 0x6c) | ||
| 67 | #define JT_DDRC_TIMING4 JIO_32_RW | ||
| 68 | #define JN_DDRC_TIMING4 DDRC_TIMING4 | ||
| 69 | #define JI_DDRC_TIMING4 | ||
| 70 | |||
| 71 | #define REG_DDRC_TIMING5 jz_reg(DDRC_TIMING5) | ||
| 72 | #define JA_DDRC_TIMING5 (0xb34f0000 + 0x70) | ||
| 73 | #define JT_DDRC_TIMING5 JIO_32_RW | ||
| 74 | #define JN_DDRC_TIMING5 DDRC_TIMING5 | ||
| 75 | #define JI_DDRC_TIMING5 | ||
| 76 | |||
| 77 | #define REG_DDRC_TIMING6 jz_reg(DDRC_TIMING6) | ||
| 78 | #define JA_DDRC_TIMING6 (0xb34f0000 + 0x74) | ||
| 79 | #define JT_DDRC_TIMING6 JIO_32_RW | ||
| 80 | #define JN_DDRC_TIMING6 DDRC_TIMING6 | ||
| 81 | #define JI_DDRC_TIMING6 | ||
| 82 | |||
| 83 | #define REG_DDRC_REFCNT jz_reg(DDRC_REFCNT) | ||
| 84 | #define JA_DDRC_REFCNT (0xb34f0000 + 0x18) | ||
| 85 | #define JT_DDRC_REFCNT JIO_32_RW | ||
| 86 | #define JN_DDRC_REFCNT DDRC_REFCNT | ||
| 87 | #define JI_DDRC_REFCNT | ||
| 88 | |||
| 89 | #define REG_DDRC_MMAP0 jz_reg(DDRC_MMAP0) | ||
| 90 | #define JA_DDRC_MMAP0 (0xb34f0000 + 0x24) | ||
| 91 | #define JT_DDRC_MMAP0 JIO_32_RW | ||
| 92 | #define JN_DDRC_MMAP0 DDRC_MMAP0 | ||
| 93 | #define JI_DDRC_MMAP0 | ||
| 94 | |||
| 95 | #define REG_DDRC_MMAP1 jz_reg(DDRC_MMAP1) | ||
| 96 | #define JA_DDRC_MMAP1 (0xb34f0000 + 0x28) | ||
| 97 | #define JT_DDRC_MMAP1 JIO_32_RW | ||
| 98 | #define JN_DDRC_MMAP1 DDRC_MMAP1 | ||
| 99 | #define JI_DDRC_MMAP1 | ||
| 100 | |||
| 101 | #define REG_DDRC_DLP jz_reg(DDRC_DLP) | ||
| 102 | #define JA_DDRC_DLP (0xb34f0000 + 0xbc) | ||
| 103 | #define JT_DDRC_DLP JIO_32_RW | ||
| 104 | #define JN_DDRC_DLP DDRC_DLP | ||
| 105 | #define JI_DDRC_DLP | ||
| 106 | |||
| 107 | #define REG_DDRC_REMAP1 jz_reg(DDRC_REMAP1) | ||
| 108 | #define JA_DDRC_REMAP1 (0xb34f0000 + 0x9c) | ||
| 109 | #define JT_DDRC_REMAP1 JIO_32_RW | ||
| 110 | #define JN_DDRC_REMAP1 DDRC_REMAP1 | ||
| 111 | #define JI_DDRC_REMAP1 | ||
| 112 | |||
| 113 | #define REG_DDRC_REMAP2 jz_reg(DDRC_REMAP2) | ||
| 114 | #define JA_DDRC_REMAP2 (0xb34f0000 + 0xa0) | ||
| 115 | #define JT_DDRC_REMAP2 JIO_32_RW | ||
| 116 | #define JN_DDRC_REMAP2 DDRC_REMAP2 | ||
| 117 | #define JI_DDRC_REMAP2 | ||
| 118 | |||
| 119 | #define REG_DDRC_REMAP3 jz_reg(DDRC_REMAP3) | ||
| 120 | #define JA_DDRC_REMAP3 (0xb34f0000 + 0xa4) | ||
| 121 | #define JT_DDRC_REMAP3 JIO_32_RW | ||
| 122 | #define JN_DDRC_REMAP3 DDRC_REMAP3 | ||
| 123 | #define JI_DDRC_REMAP3 | ||
| 124 | |||
| 125 | #define REG_DDRC_REMAP4 jz_reg(DDRC_REMAP4) | ||
| 126 | #define JA_DDRC_REMAP4 (0xb34f0000 + 0xa8) | ||
| 127 | #define JT_DDRC_REMAP4 JIO_32_RW | ||
| 128 | #define JN_DDRC_REMAP4 DDRC_REMAP4 | ||
| 129 | #define JI_DDRC_REMAP4 | ||
| 130 | |||
| 131 | #define REG_DDRC_REMAP5 jz_reg(DDRC_REMAP5) | ||
| 132 | #define JA_DDRC_REMAP5 (0xb34f0000 + 0xac) | ||
| 133 | #define JT_DDRC_REMAP5 JIO_32_RW | ||
| 134 | #define JN_DDRC_REMAP5 DDRC_REMAP5 | ||
| 135 | #define JI_DDRC_REMAP5 | ||
| 136 | |||
| 137 | #define REG_DDRC_AUTOSR_CNT jz_reg(DDRC_AUTOSR_CNT) | ||
| 138 | #define JA_DDRC_AUTOSR_CNT (0xb34f0000 + 0x308) | ||
| 139 | #define JT_DDRC_AUTOSR_CNT JIO_32_RW | ||
| 140 | #define JN_DDRC_AUTOSR_CNT DDRC_AUTOSR_CNT | ||
| 141 | #define JI_DDRC_AUTOSR_CNT | ||
| 142 | |||
| 143 | #define REG_DDRC_AUTOSR_EN jz_reg(DDRC_AUTOSR_EN) | ||
| 144 | #define JA_DDRC_AUTOSR_EN (0xb34f0000 + 0x304) | ||
| 145 | #define JT_DDRC_AUTOSR_EN JIO_32_RW | ||
| 146 | #define JN_DDRC_AUTOSR_EN DDRC_AUTOSR_EN | ||
| 147 | #define JI_DDRC_AUTOSR_EN | ||
| 148 | |||
| 149 | #endif /* __HEADERGEN_DDRC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrc_apb.h b/firmware/target/mips/ingenic_x1000/x1000/ddrc_apb.h new file mode 100644 index 0000000000..bcb880624f --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrc_apb.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_DDRC_APB_H__ | ||
| 25 | #define __HEADERGEN_DDRC_APB_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_DDRC_APB_CLKSTP_CFG jz_reg(DDRC_APB_CLKSTP_CFG) | ||
| 30 | #define JA_DDRC_APB_CLKSTP_CFG (0xb3012000 + 0x68) | ||
| 31 | #define JT_DDRC_APB_CLKSTP_CFG JIO_32_RW | ||
| 32 | #define JN_DDRC_APB_CLKSTP_CFG DDRC_APB_CLKSTP_CFG | ||
| 33 | #define JI_DDRC_APB_CLKSTP_CFG | ||
| 34 | |||
| 35 | #define REG_DDRC_APB_PHYRST_CFG jz_reg(DDRC_APB_PHYRST_CFG) | ||
| 36 | #define JA_DDRC_APB_PHYRST_CFG (0xb3012000 + 0x80) | ||
| 37 | #define JT_DDRC_APB_PHYRST_CFG JIO_32_RW | ||
| 38 | #define JN_DDRC_APB_PHYRST_CFG DDRC_APB_PHYRST_CFG | ||
| 39 | #define JI_DDRC_APB_PHYRST_CFG | ||
| 40 | |||
| 41 | #endif /* __HEADERGEN_DDRC_APB_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h b/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h new file mode 100644 index 0000000000..2ac0563090 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h | |||
| @@ -0,0 +1,155 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_DDRPHY_H__ | ||
| 25 | #define __HEADERGEN_DDRPHY_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_DDRPHY_PIR jz_reg(DDRPHY_PIR) | ||
| 30 | #define JA_DDRPHY_PIR (0xb3011000 + 0x4) | ||
| 31 | #define JT_DDRPHY_PIR JIO_32_RW | ||
| 32 | #define JN_DDRPHY_PIR DDRPHY_PIR | ||
| 33 | #define JI_DDRPHY_PIR | ||
| 34 | |||
| 35 | #define REG_DDRPHY_PGCR jz_reg(DDRPHY_PGCR) | ||
| 36 | #define JA_DDRPHY_PGCR (0xb3011000 + 0x8) | ||
| 37 | #define JT_DDRPHY_PGCR JIO_32_RW | ||
| 38 | #define JN_DDRPHY_PGCR DDRPHY_PGCR | ||
| 39 | #define JI_DDRPHY_PGCR | ||
| 40 | |||
| 41 | #define REG_DDRPHY_PGSR jz_reg(DDRPHY_PGSR) | ||
| 42 | #define JA_DDRPHY_PGSR (0xb3011000 + 0xc) | ||
| 43 | #define JT_DDRPHY_PGSR JIO_32_RW | ||
| 44 | #define JN_DDRPHY_PGSR DDRPHY_PGSR | ||
| 45 | #define JI_DDRPHY_PGSR | ||
| 46 | |||
| 47 | #define REG_DDRPHY_DLLGCR jz_reg(DDRPHY_DLLGCR) | ||
| 48 | #define JA_DDRPHY_DLLGCR (0xb3011000 + 0x10) | ||
| 49 | #define JT_DDRPHY_DLLGCR JIO_32_RW | ||
| 50 | #define JN_DDRPHY_DLLGCR DDRPHY_DLLGCR | ||
| 51 | #define JI_DDRPHY_DLLGCR | ||
| 52 | |||
| 53 | #define REG_DDRPHY_ACDLLCR jz_reg(DDRPHY_ACDLLCR) | ||
| 54 | #define JA_DDRPHY_ACDLLCR (0xb3011000 + 0x14) | ||
| 55 | #define JT_DDRPHY_ACDLLCR JIO_32_RW | ||
| 56 | #define JN_DDRPHY_ACDLLCR DDRPHY_ACDLLCR | ||
| 57 | #define JI_DDRPHY_ACDLLCR | ||
| 58 | |||
| 59 | #define REG_DDRPHY_PTR0 jz_reg(DDRPHY_PTR0) | ||
| 60 | #define JA_DDRPHY_PTR0 (0xb3011000 + 0x18) | ||
| 61 | #define JT_DDRPHY_PTR0 JIO_32_RW | ||
| 62 | #define JN_DDRPHY_PTR0 DDRPHY_PTR0 | ||
| 63 | #define JI_DDRPHY_PTR0 | ||
| 64 | |||
| 65 | #define REG_DDRPHY_PTR1 jz_reg(DDRPHY_PTR1) | ||
| 66 | #define JA_DDRPHY_PTR1 (0xb3011000 + 0x1c) | ||
| 67 | #define JT_DDRPHY_PTR1 JIO_32_RW | ||
| 68 | #define JN_DDRPHY_PTR1 DDRPHY_PTR1 | ||
| 69 | #define JI_DDRPHY_PTR1 | ||
| 70 | |||
| 71 | #define REG_DDRPHY_PTR2 jz_reg(DDRPHY_PTR2) | ||
| 72 | #define JA_DDRPHY_PTR2 (0xb3011000 + 0x20) | ||
| 73 | #define JT_DDRPHY_PTR2 JIO_32_RW | ||
| 74 | #define JN_DDRPHY_PTR2 DDRPHY_PTR2 | ||
| 75 | #define JI_DDRPHY_PTR2 | ||
| 76 | |||
| 77 | #define REG_DDRPHY_ACIOCR jz_reg(DDRPHY_ACIOCR) | ||
| 78 | #define JA_DDRPHY_ACIOCR (0xb3011000 + 0x24) | ||
| 79 | #define JT_DDRPHY_ACIOCR JIO_32_RW | ||
| 80 | #define JN_DDRPHY_ACIOCR DDRPHY_ACIOCR | ||
| 81 | #define JI_DDRPHY_ACIOCR | ||
| 82 | |||
| 83 | #define REG_DDRPHY_DXCCR jz_reg(DDRPHY_DXCCR) | ||
| 84 | #define JA_DDRPHY_DXCCR (0xb3011000 + 0x28) | ||
| 85 | #define JT_DDRPHY_DXCCR JIO_32_RW | ||
| 86 | #define JN_DDRPHY_DXCCR DDRPHY_DXCCR | ||
| 87 | #define JI_DDRPHY_DXCCR | ||
| 88 | |||
| 89 | #define REG_DDRPHY_DSGCR jz_reg(DDRPHY_DSGCR) | ||
| 90 | #define JA_DDRPHY_DSGCR (0xb3011000 + 0x2c) | ||
| 91 | #define JT_DDRPHY_DSGCR JIO_32_RW | ||
| 92 | #define JN_DDRPHY_DSGCR DDRPHY_DSGCR | ||
| 93 | #define JI_DDRPHY_DSGCR | ||
| 94 | |||
| 95 | #define REG_DDRPHY_DCR jz_reg(DDRPHY_DCR) | ||
| 96 | #define JA_DDRPHY_DCR (0xb3011000 + 0x30) | ||
| 97 | #define JT_DDRPHY_DCR JIO_32_RW | ||
| 98 | #define JN_DDRPHY_DCR DDRPHY_DCR | ||
| 99 | #define JI_DDRPHY_DCR | ||
| 100 | |||
| 101 | #define REG_DDRPHY_DTPR0 jz_reg(DDRPHY_DTPR0) | ||
| 102 | #define JA_DDRPHY_DTPR0 (0xb3011000 + 0x34) | ||
| 103 | #define JT_DDRPHY_DTPR0 JIO_32_RW | ||
| 104 | #define JN_DDRPHY_DTPR0 DDRPHY_DTPR0 | ||
| 105 | #define JI_DDRPHY_DTPR0 | ||
| 106 | |||
| 107 | #define REG_DDRPHY_DTPR1 jz_reg(DDRPHY_DTPR1) | ||
| 108 | #define JA_DDRPHY_DTPR1 (0xb3011000 + 0x38) | ||
| 109 | #define JT_DDRPHY_DTPR1 JIO_32_RW | ||
| 110 | #define JN_DDRPHY_DTPR1 DDRPHY_DTPR1 | ||
| 111 | #define JI_DDRPHY_DTPR1 | ||
| 112 | |||
| 113 | #define REG_DDRPHY_DTPR2 jz_reg(DDRPHY_DTPR2) | ||
| 114 | #define JA_DDRPHY_DTPR2 (0xb3011000 + 0x3c) | ||
| 115 | #define JT_DDRPHY_DTPR2 JIO_32_RW | ||
| 116 | #define JN_DDRPHY_DTPR2 DDRPHY_DTPR2 | ||
| 117 | #define JI_DDRPHY_DTPR2 | ||
| 118 | |||
| 119 | #define REG_DDRPHY_MR0 jz_reg(DDRPHY_MR0) | ||
| 120 | #define JA_DDRPHY_MR0 (0xb3011000 + 0x40) | ||
| 121 | #define JT_DDRPHY_MR0 JIO_32_RW | ||
| 122 | #define JN_DDRPHY_MR0 DDRPHY_MR0 | ||
| 123 | #define JI_DDRPHY_MR0 | ||
| 124 | |||
| 125 | #define REG_DDRPHY_MR1 jz_reg(DDRPHY_MR1) | ||
| 126 | #define JA_DDRPHY_MR1 (0xb3011000 + 0x44) | ||
| 127 | #define JT_DDRPHY_MR1 JIO_32_RW | ||
| 128 | #define JN_DDRPHY_MR1 DDRPHY_MR1 | ||
| 129 | #define JI_DDRPHY_MR1 | ||
| 130 | |||
| 131 | #define REG_DDRPHY_MR2 jz_reg(DDRPHY_MR2) | ||
| 132 | #define JA_DDRPHY_MR2 (0xb3011000 + 0x48) | ||
| 133 | #define JT_DDRPHY_MR2 JIO_32_RW | ||
| 134 | #define JN_DDRPHY_MR2 DDRPHY_MR2 | ||
| 135 | #define JI_DDRPHY_MR2 | ||
| 136 | |||
| 137 | #define REG_DDRPHY_MR3 jz_reg(DDRPHY_MR3) | ||
| 138 | #define JA_DDRPHY_MR3 (0xb3011000 + 0x4c) | ||
| 139 | #define JT_DDRPHY_MR3 JIO_32_RW | ||
| 140 | #define JN_DDRPHY_MR3 DDRPHY_MR3 | ||
| 141 | #define JI_DDRPHY_MR3 | ||
| 142 | |||
| 143 | #define REG_DDRPHY_DTAR jz_reg(DDRPHY_DTAR) | ||
| 144 | #define JA_DDRPHY_DTAR (0xb3011000 + 0x54) | ||
| 145 | #define JT_DDRPHY_DTAR JIO_32_RW | ||
| 146 | #define JN_DDRPHY_DTAR DDRPHY_DTAR | ||
| 147 | #define JI_DDRPHY_DTAR | ||
| 148 | |||
| 149 | #define REG_DDRPHY_DXGCR(_n1) jz_reg(DDRPHY_DXGCR(_n1)) | ||
| 150 | #define JA_DDRPHY_DXGCR(_n1) (0xb3011000 + 0x1c0 + (_n1) * 0x40) | ||
| 151 | #define JT_DDRPHY_DXGCR(_n1) JIO_32_RW | ||
| 152 | #define JN_DDRPHY_DXGCR(_n1) DDRPHY_DXGCR | ||
| 153 | #define JI_DDRPHY_DXGCR(_n1) (_n1) | ||
| 154 | |||
| 155 | #endif /* __HEADERGEN_DDRPHY_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/dma.h b/firmware/target/mips/ingenic_x1000/x1000/dma.h new file mode 100644 index 0000000000..516c6e6849 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/dma.h | |||
| @@ -0,0 +1,112 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_DMA_H__ | ||
| 25 | #define __HEADERGEN_DMA_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_DMA_CTRL jz_reg(DMA_CTRL) | ||
| 30 | #define JA_DMA_CTRL (0xb3421000 + 0x0) | ||
| 31 | #define JT_DMA_CTRL JIO_32_RW | ||
| 32 | #define JN_DMA_CTRL DMA_CTRL | ||
| 33 | #define JI_DMA_CTRL | ||
| 34 | #define BP_DMA_CTRL_FMSC 31 | ||
| 35 | #define BM_DMA_CTRL_FMSC 0x80000000 | ||
| 36 | #define BF_DMA_CTRL_FMSC(v) (((v) & 0x1) << 31) | ||
| 37 | #define BFM_DMA_CTRL_FMSC(v) BM_DMA_CTRL_FMSC | ||
| 38 | #define BF_DMA_CTRL_FMSC_V(e) BF_DMA_CTRL_FMSC(BV_DMA_CTRL_FMSC__##e) | ||
| 39 | #define BFM_DMA_CTRL_FMSC_V(v) BM_DMA_CTRL_FMSC | ||
| 40 | #define BP_DMA_CTRL_FSSI 30 | ||
| 41 | #define BM_DMA_CTRL_FSSI 0x40000000 | ||
| 42 | #define BF_DMA_CTRL_FSSI(v) (((v) & 0x1) << 30) | ||
| 43 | #define BFM_DMA_CTRL_FSSI(v) BM_DMA_CTRL_FSSI | ||
| 44 | #define BF_DMA_CTRL_FSSI_V(e) BF_DMA_CTRL_FSSI(BV_DMA_CTRL_FSSI__##e) | ||
| 45 | #define BFM_DMA_CTRL_FSSI_V(v) BM_DMA_CTRL_FSSI | ||
| 46 | #define BP_DMA_CTRL_FTSSI 29 | ||
| 47 | #define BM_DMA_CTRL_FTSSI 0x20000000 | ||
| 48 | #define BF_DMA_CTRL_FTSSI(v) (((v) & 0x1) << 29) | ||
| 49 | #define BFM_DMA_CTRL_FTSSI(v) BM_DMA_CTRL_FTSSI | ||
| 50 | #define BF_DMA_CTRL_FTSSI_V(e) BF_DMA_CTRL_FTSSI(BV_DMA_CTRL_FTSSI__##e) | ||
| 51 | #define BFM_DMA_CTRL_FTSSI_V(v) BM_DMA_CTRL_FTSSI | ||
| 52 | #define BP_DMA_CTRL_FUART 28 | ||
| 53 | #define BM_DMA_CTRL_FUART 0x10000000 | ||
| 54 | #define BF_DMA_CTRL_FUART(v) (((v) & 0x1) << 28) | ||
| 55 | #define BFM_DMA_CTRL_FUART(v) BM_DMA_CTRL_FUART | ||
| 56 | #define BF_DMA_CTRL_FUART_V(e) BF_DMA_CTRL_FUART(BV_DMA_CTRL_FUART__##e) | ||
| 57 | #define BFM_DMA_CTRL_FUART_V(v) BM_DMA_CTRL_FUART | ||
| 58 | #define BP_DMA_CTRL_FAIC 27 | ||
| 59 | #define BM_DMA_CTRL_FAIC 0x8000000 | ||
| 60 | #define BF_DMA_CTRL_FAIC(v) (((v) & 0x1) << 27) | ||
| 61 | #define BFM_DMA_CTRL_FAIC(v) BM_DMA_CTRL_FAIC | ||
| 62 | #define BF_DMA_CTRL_FAIC_V(e) BF_DMA_CTRL_FAIC(BV_DMA_CTRL_FAIC__##e) | ||
| 63 | #define BFM_DMA_CTRL_FAIC_V(v) BM_DMA_CTRL_FAIC | ||
| 64 | #define BP_DMA_CTRL_HALT 3 | ||
| 65 | #define BM_DMA_CTRL_HALT 0x8 | ||
| 66 | #define BF_DMA_CTRL_HALT(v) (((v) & 0x1) << 3) | ||
| 67 | #define BFM_DMA_CTRL_HALT(v) BM_DMA_CTRL_HALT | ||
| 68 | #define BF_DMA_CTRL_HALT_V(e) BF_DMA_CTRL_HALT(BV_DMA_CTRL_HALT__##e) | ||
| 69 | #define BFM_DMA_CTRL_HALT_V(v) BM_DMA_CTRL_HALT | ||
| 70 | #define BP_DMA_CTRL_AR 2 | ||
| 71 | #define BM_DMA_CTRL_AR 0x4 | ||
| 72 | #define BF_DMA_CTRL_AR(v) (((v) & 0x1) << 2) | ||
| 73 | #define BFM_DMA_CTRL_AR(v) BM_DMA_CTRL_AR | ||
| 74 | #define BF_DMA_CTRL_AR_V(e) BF_DMA_CTRL_AR(BV_DMA_CTRL_AR__##e) | ||
| 75 | #define BFM_DMA_CTRL_AR_V(v) BM_DMA_CTRL_AR | ||
| 76 | #define BP_DMA_CTRL_ENABLE 0 | ||
| 77 | #define BM_DMA_CTRL_ENABLE 0x1 | ||
| 78 | #define BF_DMA_CTRL_ENABLE(v) (((v) & 0x1) << 0) | ||
| 79 | #define BFM_DMA_CTRL_ENABLE(v) BM_DMA_CTRL_ENABLE | ||
| 80 | #define BF_DMA_CTRL_ENABLE_V(e) BF_DMA_CTRL_ENABLE(BV_DMA_CTRL_ENABLE__##e) | ||
| 81 | #define BFM_DMA_CTRL_ENABLE_V(v) BM_DMA_CTRL_ENABLE | ||
| 82 | |||
| 83 | #define REG_DMA_IRQP jz_reg(DMA_IRQP) | ||
| 84 | #define JA_DMA_IRQP (0xb3421000 + 0x4) | ||
| 85 | #define JT_DMA_IRQP JIO_32_RW | ||
| 86 | #define JN_DMA_IRQP DMA_IRQP | ||
| 87 | #define JI_DMA_IRQP | ||
| 88 | |||
| 89 | #define REG_DMA_DB jz_reg(DMA_DB) | ||
| 90 | #define JA_DMA_DB (0xb3421000 + 0x8) | ||
| 91 | #define JT_DMA_DB JIO_32_RW | ||
| 92 | #define JN_DMA_DB DMA_DB | ||
| 93 | #define JI_DMA_DB | ||
| 94 | #define REG_DMA_DB_SET jz_reg(DMA_DB_SET) | ||
| 95 | #define JA_DMA_DB_SET (JA_DMA_DB + 0x4) | ||
| 96 | #define JT_DMA_DB_SET JIO_32_WO | ||
| 97 | #define JN_DMA_DB_SET DMA_DB | ||
| 98 | #define JI_DMA_DB_SET | ||
| 99 | |||
| 100 | #define REG_DMA_DIP jz_reg(DMA_DIP) | ||
| 101 | #define JA_DMA_DIP (0xb3421000 + 0x10) | ||
| 102 | #define JT_DMA_DIP JIO_32_RW | ||
| 103 | #define JN_DMA_DIP DMA_DIP | ||
| 104 | #define JI_DMA_DIP | ||
| 105 | |||
| 106 | #define REG_DMA_DIC jz_reg(DMA_DIC) | ||
| 107 | #define JA_DMA_DIC (0xb3421000 + 0x14) | ||
| 108 | #define JT_DMA_DIC JIO_32_RW | ||
| 109 | #define JN_DMA_DIC DMA_DIC | ||
| 110 | #define JI_DMA_DIC | ||
| 111 | |||
| 112 | #endif /* __HEADERGEN_DMA_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h b/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h new file mode 100644 index 0000000000..56eb2a8cc1 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h | |||
| @@ -0,0 +1,253 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_DMA_CHN_H__ | ||
| 25 | #define __HEADERGEN_DMA_CHN_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_DMA_CHN_SA(_n1) jz_reg(DMA_CHN_SA(_n1)) | ||
| 30 | #define JA_DMA_CHN_SA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x0) | ||
| 31 | #define JT_DMA_CHN_SA(_n1) JIO_32_RW | ||
| 32 | #define JN_DMA_CHN_SA(_n1) DMA_CHN_SA | ||
| 33 | #define JI_DMA_CHN_SA(_n1) (_n1) | ||
| 34 | |||
| 35 | #define REG_DMA_CHN_TA(_n1) jz_reg(DMA_CHN_TA(_n1)) | ||
| 36 | #define JA_DMA_CHN_TA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x4) | ||
| 37 | #define JT_DMA_CHN_TA(_n1) JIO_32_RW | ||
| 38 | #define JN_DMA_CHN_TA(_n1) DMA_CHN_TA | ||
| 39 | #define JI_DMA_CHN_TA(_n1) (_n1) | ||
| 40 | |||
| 41 | #define REG_DMA_CHN_TC(_n1) jz_reg(DMA_CHN_TC(_n1)) | ||
| 42 | #define JA_DMA_CHN_TC(_n1) (0xb3420000 + (_n1) * 0x20 + 0x8) | ||
| 43 | #define JT_DMA_CHN_TC(_n1) JIO_32_RW | ||
| 44 | #define JN_DMA_CHN_TC(_n1) DMA_CHN_TC | ||
| 45 | #define JI_DMA_CHN_TC(_n1) (_n1) | ||
| 46 | #define BP_DMA_CHN_TC_DOA 24 | ||
| 47 | #define BM_DMA_CHN_TC_DOA 0xff000000 | ||
| 48 | #define BF_DMA_CHN_TC_DOA(v) (((v) & 0xff) << 24) | ||
| 49 | #define BFM_DMA_CHN_TC_DOA(v) BM_DMA_CHN_TC_DOA | ||
| 50 | #define BF_DMA_CHN_TC_DOA_V(e) BF_DMA_CHN_TC_DOA(BV_DMA_CHN_TC_DOA__##e) | ||
| 51 | #define BFM_DMA_CHN_TC_DOA_V(v) BM_DMA_CHN_TC_DOA | ||
| 52 | #define BP_DMA_CHN_TC_CNT 0 | ||
| 53 | #define BM_DMA_CHN_TC_CNT 0xffffff | ||
| 54 | #define BF_DMA_CHN_TC_CNT(v) (((v) & 0xffffff) << 0) | ||
| 55 | #define BFM_DMA_CHN_TC_CNT(v) BM_DMA_CHN_TC_CNT | ||
| 56 | #define BF_DMA_CHN_TC_CNT_V(e) BF_DMA_CHN_TC_CNT(BV_DMA_CHN_TC_CNT__##e) | ||
| 57 | #define BFM_DMA_CHN_TC_CNT_V(v) BM_DMA_CHN_TC_CNT | ||
| 58 | |||
| 59 | #define REG_DMA_CHN_RT(_n1) jz_reg(DMA_CHN_RT(_n1)) | ||
| 60 | #define JA_DMA_CHN_RT(_n1) (0xb3420000 + (_n1) * 0x20 + 0xc) | ||
| 61 | #define JT_DMA_CHN_RT(_n1) JIO_32_RW | ||
| 62 | #define JN_DMA_CHN_RT(_n1) DMA_CHN_RT | ||
| 63 | #define JI_DMA_CHN_RT(_n1) (_n1) | ||
| 64 | #define BP_DMA_CHN_RT_TYPE 0 | ||
| 65 | #define BM_DMA_CHN_RT_TYPE 0x3f | ||
| 66 | #define BV_DMA_CHN_RT_TYPE__DMIC_RX 0x5 | ||
| 67 | #define BV_DMA_CHN_RT_TYPE__I2S_TX 0x6 | ||
| 68 | #define BV_DMA_CHN_RT_TYPE__I2S_RX 0x7 | ||
| 69 | #define BV_DMA_CHN_RT_TYPE__AUTO 0x8 | ||
| 70 | #define BV_DMA_CHN_RT_TYPE__UART2_TX 0x10 | ||
| 71 | #define BV_DMA_CHN_RT_TYPE__UART2_RX 0x11 | ||
| 72 | #define BV_DMA_CHN_RT_TYPE__UART1_TX 0x12 | ||
| 73 | #define BV_DMA_CHN_RT_TYPE__UART1_RX 0x13 | ||
| 74 | #define BV_DMA_CHN_RT_TYPE__UART0_TX 0x14 | ||
| 75 | #define BV_DMA_CHN_RT_TYPE__UART0_RX 0x15 | ||
| 76 | #define BV_DMA_CHN_RT_TYPE__SSI_TX 0x16 | ||
| 77 | #define BV_DMA_CHN_RT_TYPE__SSI_RX 0x17 | ||
| 78 | #define BV_DMA_CHN_RT_TYPE__MSC0_TX 0x1a | ||
| 79 | #define BV_DMA_CHN_RT_TYPE__MSC0_RX 0x1b | ||
| 80 | #define BV_DMA_CHN_RT_TYPE__MSC1_TX 0x1c | ||
| 81 | #define BV_DMA_CHN_RT_TYPE__MSC1_RX 0x1d | ||
| 82 | #define BV_DMA_CHN_RT_TYPE__PCM_TX 0x20 | ||
| 83 | #define BV_DMA_CHN_RT_TYPE__PCM_RX 0x21 | ||
| 84 | #define BV_DMA_CHN_RT_TYPE__I2C0_TX 0x24 | ||
| 85 | #define BV_DMA_CHN_RT_TYPE__I2C0_RX 0x25 | ||
| 86 | #define BV_DMA_CHN_RT_TYPE__I2C1_TX 0x26 | ||
| 87 | #define BV_DMA_CHN_RT_TYPE__I2C1_RX 0x27 | ||
| 88 | #define BV_DMA_CHN_RT_TYPE__I2C2_TX 0x28 | ||
| 89 | #define BV_DMA_CHN_RT_TYPE__I2C2_RX 0x29 | ||
| 90 | #define BF_DMA_CHN_RT_TYPE(v) (((v) & 0x3f) << 0) | ||
| 91 | #define BFM_DMA_CHN_RT_TYPE(v) BM_DMA_CHN_RT_TYPE | ||
| 92 | #define BF_DMA_CHN_RT_TYPE_V(e) BF_DMA_CHN_RT_TYPE(BV_DMA_CHN_RT_TYPE__##e) | ||
| 93 | #define BFM_DMA_CHN_RT_TYPE_V(v) BM_DMA_CHN_RT_TYPE | ||
| 94 | |||
| 95 | #define REG_DMA_CHN_CS(_n1) jz_reg(DMA_CHN_CS(_n1)) | ||
| 96 | #define JA_DMA_CHN_CS(_n1) (0xb3420000 + (_n1) * 0x20 + 0x10) | ||
| 97 | #define JT_DMA_CHN_CS(_n1) JIO_32_RW | ||
| 98 | #define JN_DMA_CHN_CS(_n1) DMA_CHN_CS | ||
| 99 | #define JI_DMA_CHN_CS(_n1) (_n1) | ||
| 100 | #define BP_DMA_CHN_CS_CDOA 8 | ||
| 101 | #define BM_DMA_CHN_CS_CDOA 0xff00 | ||
| 102 | #define BF_DMA_CHN_CS_CDOA(v) (((v) & 0xff) << 8) | ||
| 103 | #define BFM_DMA_CHN_CS_CDOA(v) BM_DMA_CHN_CS_CDOA | ||
| 104 | #define BF_DMA_CHN_CS_CDOA_V(e) BF_DMA_CHN_CS_CDOA(BV_DMA_CHN_CS_CDOA__##e) | ||
| 105 | #define BFM_DMA_CHN_CS_CDOA_V(v) BM_DMA_CHN_CS_CDOA | ||
| 106 | #define BP_DMA_CHN_CS_NDES 31 | ||
| 107 | #define BM_DMA_CHN_CS_NDES 0x80000000 | ||
| 108 | #define BF_DMA_CHN_CS_NDES(v) (((v) & 0x1) << 31) | ||
| 109 | #define BFM_DMA_CHN_CS_NDES(v) BM_DMA_CHN_CS_NDES | ||
| 110 | #define BF_DMA_CHN_CS_NDES_V(e) BF_DMA_CHN_CS_NDES(BV_DMA_CHN_CS_NDES__##e) | ||
| 111 | #define BFM_DMA_CHN_CS_NDES_V(v) BM_DMA_CHN_CS_NDES | ||
| 112 | #define BP_DMA_CHN_CS_DES8 30 | ||
| 113 | #define BM_DMA_CHN_CS_DES8 0x40000000 | ||
| 114 | #define BF_DMA_CHN_CS_DES8(v) (((v) & 0x1) << 30) | ||
| 115 | #define BFM_DMA_CHN_CS_DES8(v) BM_DMA_CHN_CS_DES8 | ||
| 116 | #define BF_DMA_CHN_CS_DES8_V(e) BF_DMA_CHN_CS_DES8(BV_DMA_CHN_CS_DES8__##e) | ||
| 117 | #define BFM_DMA_CHN_CS_DES8_V(v) BM_DMA_CHN_CS_DES8 | ||
| 118 | #define BP_DMA_CHN_CS_AR 4 | ||
| 119 | #define BM_DMA_CHN_CS_AR 0x10 | ||
| 120 | #define BF_DMA_CHN_CS_AR(v) (((v) & 0x1) << 4) | ||
| 121 | #define BFM_DMA_CHN_CS_AR(v) BM_DMA_CHN_CS_AR | ||
| 122 | #define BF_DMA_CHN_CS_AR_V(e) BF_DMA_CHN_CS_AR(BV_DMA_CHN_CS_AR__##e) | ||
| 123 | #define BFM_DMA_CHN_CS_AR_V(v) BM_DMA_CHN_CS_AR | ||
| 124 | #define BP_DMA_CHN_CS_TT 3 | ||
| 125 | #define BM_DMA_CHN_CS_TT 0x8 | ||
| 126 | #define BF_DMA_CHN_CS_TT(v) (((v) & 0x1) << 3) | ||
| 127 | #define BFM_DMA_CHN_CS_TT(v) BM_DMA_CHN_CS_TT | ||
| 128 | #define BF_DMA_CHN_CS_TT_V(e) BF_DMA_CHN_CS_TT(BV_DMA_CHN_CS_TT__##e) | ||
| 129 | #define BFM_DMA_CHN_CS_TT_V(v) BM_DMA_CHN_CS_TT | ||
| 130 | #define BP_DMA_CHN_CS_HLT 2 | ||
| 131 | #define BM_DMA_CHN_CS_HLT 0x4 | ||
| 132 | #define BF_DMA_CHN_CS_HLT(v) (((v) & 0x1) << 2) | ||
| 133 | #define BFM_DMA_CHN_CS_HLT(v) BM_DMA_CHN_CS_HLT | ||
| 134 | #define BF_DMA_CHN_CS_HLT_V(e) BF_DMA_CHN_CS_HLT(BV_DMA_CHN_CS_HLT__##e) | ||
| 135 | #define BFM_DMA_CHN_CS_HLT_V(v) BM_DMA_CHN_CS_HLT | ||
| 136 | #define BP_DMA_CHN_CS_CTE 0 | ||
| 137 | #define BM_DMA_CHN_CS_CTE 0x1 | ||
| 138 | #define BF_DMA_CHN_CS_CTE(v) (((v) & 0x1) << 0) | ||
| 139 | #define BFM_DMA_CHN_CS_CTE(v) BM_DMA_CHN_CS_CTE | ||
| 140 | #define BF_DMA_CHN_CS_CTE_V(e) BF_DMA_CHN_CS_CTE(BV_DMA_CHN_CS_CTE__##e) | ||
| 141 | #define BFM_DMA_CHN_CS_CTE_V(v) BM_DMA_CHN_CS_CTE | ||
| 142 | |||
| 143 | #define REG_DMA_CHN_CM(_n1) jz_reg(DMA_CHN_CM(_n1)) | ||
| 144 | #define JA_DMA_CHN_CM(_n1) (0xb3420000 + (_n1) * 0x20 + 0x14) | ||
| 145 | #define JT_DMA_CHN_CM(_n1) JIO_32_RW | ||
| 146 | #define JN_DMA_CHN_CM(_n1) DMA_CHN_CM | ||
| 147 | #define JI_DMA_CHN_CM(_n1) (_n1) | ||
| 148 | #define BP_DMA_CHN_CM_RDIL 16 | ||
| 149 | #define BM_DMA_CHN_CM_RDIL 0xf0000 | ||
| 150 | #define BF_DMA_CHN_CM_RDIL(v) (((v) & 0xf) << 16) | ||
| 151 | #define BFM_DMA_CHN_CM_RDIL(v) BM_DMA_CHN_CM_RDIL | ||
| 152 | #define BF_DMA_CHN_CM_RDIL_V(e) BF_DMA_CHN_CM_RDIL(BV_DMA_CHN_CM_RDIL__##e) | ||
| 153 | #define BFM_DMA_CHN_CM_RDIL_V(v) BM_DMA_CHN_CM_RDIL | ||
| 154 | #define BP_DMA_CHN_CM_SP 14 | ||
| 155 | #define BM_DMA_CHN_CM_SP 0xc000 | ||
| 156 | #define BV_DMA_CHN_CM_SP__32BIT 0x0 | ||
| 157 | #define BV_DMA_CHN_CM_SP__8BIT 0x1 | ||
| 158 | #define BV_DMA_CHN_CM_SP__16BIT 0x2 | ||
| 159 | #define BF_DMA_CHN_CM_SP(v) (((v) & 0x3) << 14) | ||
| 160 | #define BFM_DMA_CHN_CM_SP(v) BM_DMA_CHN_CM_SP | ||
| 161 | #define BF_DMA_CHN_CM_SP_V(e) BF_DMA_CHN_CM_SP(BV_DMA_CHN_CM_SP__##e) | ||
| 162 | #define BFM_DMA_CHN_CM_SP_V(v) BM_DMA_CHN_CM_SP | ||
| 163 | #define BP_DMA_CHN_CM_DP 12 | ||
| 164 | #define BM_DMA_CHN_CM_DP 0x3000 | ||
| 165 | #define BV_DMA_CHN_CM_DP__32BIT 0x0 | ||
| 166 | #define BV_DMA_CHN_CM_DP__8BIT 0x1 | ||
| 167 | #define BV_DMA_CHN_CM_DP__16BIT 0x2 | ||
| 168 | #define BF_DMA_CHN_CM_DP(v) (((v) & 0x3) << 12) | ||
| 169 | #define BFM_DMA_CHN_CM_DP(v) BM_DMA_CHN_CM_DP | ||
| 170 | #define BF_DMA_CHN_CM_DP_V(e) BF_DMA_CHN_CM_DP(BV_DMA_CHN_CM_DP__##e) | ||
| 171 | #define BFM_DMA_CHN_CM_DP_V(v) BM_DMA_CHN_CM_DP | ||
| 172 | #define BP_DMA_CHN_CM_TSZ 8 | ||
| 173 | #define BM_DMA_CHN_CM_TSZ 0x700 | ||
| 174 | #define BV_DMA_CHN_CM_TSZ__32BIT 0x0 | ||
| 175 | #define BV_DMA_CHN_CM_TSZ__8BIT 0x1 | ||
| 176 | #define BV_DMA_CHN_CM_TSZ__16BIT 0x2 | ||
| 177 | #define BV_DMA_CHN_CM_TSZ__16BYTE 0x3 | ||
| 178 | #define BV_DMA_CHN_CM_TSZ__32BYTE 0x4 | ||
| 179 | #define BV_DMA_CHN_CM_TSZ__64BYTE 0x5 | ||
| 180 | #define BV_DMA_CHN_CM_TSZ__128BYTE 0x6 | ||
| 181 | #define BV_DMA_CHN_CM_TSZ__AUTO 0x7 | ||
| 182 | #define BF_DMA_CHN_CM_TSZ(v) (((v) & 0x7) << 8) | ||
| 183 | #define BFM_DMA_CHN_CM_TSZ(v) BM_DMA_CHN_CM_TSZ | ||
| 184 | #define BF_DMA_CHN_CM_TSZ_V(e) BF_DMA_CHN_CM_TSZ(BV_DMA_CHN_CM_TSZ__##e) | ||
| 185 | #define BFM_DMA_CHN_CM_TSZ_V(v) BM_DMA_CHN_CM_TSZ | ||
| 186 | #define BP_DMA_CHN_CM_SAI 23 | ||
| 187 | #define BM_DMA_CHN_CM_SAI 0x800000 | ||
| 188 | #define BF_DMA_CHN_CM_SAI(v) (((v) & 0x1) << 23) | ||
| 189 | #define BFM_DMA_CHN_CM_SAI(v) BM_DMA_CHN_CM_SAI | ||
| 190 | #define BF_DMA_CHN_CM_SAI_V(e) BF_DMA_CHN_CM_SAI(BV_DMA_CHN_CM_SAI__##e) | ||
| 191 | #define BFM_DMA_CHN_CM_SAI_V(v) BM_DMA_CHN_CM_SAI | ||
| 192 | #define BP_DMA_CHN_CM_DAI 22 | ||
| 193 | #define BM_DMA_CHN_CM_DAI 0x400000 | ||
| 194 | #define BF_DMA_CHN_CM_DAI(v) (((v) & 0x1) << 22) | ||
| 195 | #define BFM_DMA_CHN_CM_DAI(v) BM_DMA_CHN_CM_DAI | ||
| 196 | #define BF_DMA_CHN_CM_DAI_V(e) BF_DMA_CHN_CM_DAI(BV_DMA_CHN_CM_DAI__##e) | ||
| 197 | #define BFM_DMA_CHN_CM_DAI_V(v) BM_DMA_CHN_CM_DAI | ||
| 198 | #define BP_DMA_CHN_CM_STDE 2 | ||
| 199 | #define BM_DMA_CHN_CM_STDE 0x4 | ||
| 200 | #define BF_DMA_CHN_CM_STDE(v) (((v) & 0x1) << 2) | ||
| 201 | #define BFM_DMA_CHN_CM_STDE(v) BM_DMA_CHN_CM_STDE | ||
| 202 | #define BF_DMA_CHN_CM_STDE_V(e) BF_DMA_CHN_CM_STDE(BV_DMA_CHN_CM_STDE__##e) | ||
| 203 | #define BFM_DMA_CHN_CM_STDE_V(v) BM_DMA_CHN_CM_STDE | ||
| 204 | #define BP_DMA_CHN_CM_TIE 1 | ||
| 205 | #define BM_DMA_CHN_CM_TIE 0x2 | ||
| 206 | #define BF_DMA_CHN_CM_TIE(v) (((v) & 0x1) << 1) | ||
| 207 | #define BFM_DMA_CHN_CM_TIE(v) BM_DMA_CHN_CM_TIE | ||
| 208 | #define BF_DMA_CHN_CM_TIE_V(e) BF_DMA_CHN_CM_TIE(BV_DMA_CHN_CM_TIE__##e) | ||
| 209 | #define BFM_DMA_CHN_CM_TIE_V(v) BM_DMA_CHN_CM_TIE | ||
| 210 | #define BP_DMA_CHN_CM_LINK 0 | ||
| 211 | #define BM_DMA_CHN_CM_LINK 0x1 | ||
| 212 | #define BF_DMA_CHN_CM_LINK(v) (((v) & 0x1) << 0) | ||
| 213 | #define BFM_DMA_CHN_CM_LINK(v) BM_DMA_CHN_CM_LINK | ||
| 214 | #define BF_DMA_CHN_CM_LINK_V(e) BF_DMA_CHN_CM_LINK(BV_DMA_CHN_CM_LINK__##e) | ||
| 215 | #define BFM_DMA_CHN_CM_LINK_V(v) BM_DMA_CHN_CM_LINK | ||
| 216 | |||
| 217 | #define REG_DMA_CHN_DA(_n1) jz_reg(DMA_CHN_DA(_n1)) | ||
| 218 | #define JA_DMA_CHN_DA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x18) | ||
| 219 | #define JT_DMA_CHN_DA(_n1) JIO_32_RW | ||
| 220 | #define JN_DMA_CHN_DA(_n1) DMA_CHN_DA | ||
| 221 | #define JI_DMA_CHN_DA(_n1) (_n1) | ||
| 222 | #define BP_DMA_CHN_DA_DBA 12 | ||
| 223 | #define BM_DMA_CHN_DA_DBA 0xfffff000 | ||
| 224 | #define BF_DMA_CHN_DA_DBA(v) (((v) & 0xfffff) << 12) | ||
| 225 | #define BFM_DMA_CHN_DA_DBA(v) BM_DMA_CHN_DA_DBA | ||
| 226 | #define BF_DMA_CHN_DA_DBA_V(e) BF_DMA_CHN_DA_DBA(BV_DMA_CHN_DA_DBA__##e) | ||
| 227 | #define BFM_DMA_CHN_DA_DBA_V(v) BM_DMA_CHN_DA_DBA | ||
| 228 | #define BP_DMA_CHN_DA_DOA 4 | ||
| 229 | #define BM_DMA_CHN_DA_DOA 0xff0 | ||
| 230 | #define BF_DMA_CHN_DA_DOA(v) (((v) & 0xff) << 4) | ||
| 231 | #define BFM_DMA_CHN_DA_DOA(v) BM_DMA_CHN_DA_DOA | ||
| 232 | #define BF_DMA_CHN_DA_DOA_V(e) BF_DMA_CHN_DA_DOA(BV_DMA_CHN_DA_DOA__##e) | ||
| 233 | #define BFM_DMA_CHN_DA_DOA_V(v) BM_DMA_CHN_DA_DOA | ||
| 234 | |||
| 235 | #define REG_DMA_CHN_SD(_n1) jz_reg(DMA_CHN_SD(_n1)) | ||
| 236 | #define JA_DMA_CHN_SD(_n1) (0xb3420000 + (_n1) * 0x20 + 0x1c) | ||
| 237 | #define JT_DMA_CHN_SD(_n1) JIO_32_RW | ||
| 238 | #define JN_DMA_CHN_SD(_n1) DMA_CHN_SD | ||
| 239 | #define JI_DMA_CHN_SD(_n1) (_n1) | ||
| 240 | #define BP_DMA_CHN_SD_TSD 16 | ||
| 241 | #define BM_DMA_CHN_SD_TSD 0xffff0000 | ||
| 242 | #define BF_DMA_CHN_SD_TSD(v) (((v) & 0xffff) << 16) | ||
| 243 | #define BFM_DMA_CHN_SD_TSD(v) BM_DMA_CHN_SD_TSD | ||
| 244 | #define BF_DMA_CHN_SD_TSD_V(e) BF_DMA_CHN_SD_TSD(BV_DMA_CHN_SD_TSD__##e) | ||
| 245 | #define BFM_DMA_CHN_SD_TSD_V(v) BM_DMA_CHN_SD_TSD | ||
| 246 | #define BP_DMA_CHN_SD_SSD 0 | ||
| 247 | #define BM_DMA_CHN_SD_SSD 0xffff | ||
| 248 | #define BF_DMA_CHN_SD_SSD(v) (((v) & 0xffff) << 0) | ||
| 249 | #define BFM_DMA_CHN_SD_SSD(v) BM_DMA_CHN_SD_SSD | ||
| 250 | #define BF_DMA_CHN_SD_SSD_V(e) BF_DMA_CHN_SD_SSD(BV_DMA_CHN_SD_SSD__##e) | ||
| 251 | #define BFM_DMA_CHN_SD_SSD_V(v) BM_DMA_CHN_SD_SSD | ||
| 252 | |||
| 253 | #endif /* __HEADERGEN_DMA_CHN_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/gpio.h b/firmware/target/mips/ingenic_x1000/x1000/gpio.h new file mode 100644 index 0000000000..6bba343cf6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/gpio.h | |||
| @@ -0,0 +1,196 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_GPIO_H__ | ||
| 25 | #define __HEADERGEN_GPIO_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_GPIO_C_GLITCH_CFG0 jz_reg(GPIO_C_GLITCH_CFG0) | ||
| 30 | #define JA_GPIO_C_GLITCH_CFG0 (0xb0010000 + 0x200 + 0x800) | ||
| 31 | #define JT_GPIO_C_GLITCH_CFG0 JIO_32_RW | ||
| 32 | #define JN_GPIO_C_GLITCH_CFG0 GPIO_C_GLITCH_CFG0 | ||
| 33 | #define JI_GPIO_C_GLITCH_CFG0 | ||
| 34 | #define REG_GPIO_C_GLITCH_CFG0_SET jz_reg(GPIO_C_GLITCH_CFG0_SET) | ||
| 35 | #define JA_GPIO_C_GLITCH_CFG0_SET (JA_GPIO_C_GLITCH_CFG0 + 0x4) | ||
| 36 | #define JT_GPIO_C_GLITCH_CFG0_SET JIO_32_WO | ||
| 37 | #define JN_GPIO_C_GLITCH_CFG0_SET GPIO_C_GLITCH_CFG0 | ||
| 38 | #define JI_GPIO_C_GLITCH_CFG0_SET | ||
| 39 | #define REG_GPIO_C_GLITCH_CFG0_CLR jz_reg(GPIO_C_GLITCH_CFG0_CLR) | ||
| 40 | #define JA_GPIO_C_GLITCH_CFG0_CLR (JA_GPIO_C_GLITCH_CFG0 + 0x8) | ||
| 41 | #define JT_GPIO_C_GLITCH_CFG0_CLR JIO_32_WO | ||
| 42 | #define JN_GPIO_C_GLITCH_CFG0_CLR GPIO_C_GLITCH_CFG0 | ||
| 43 | #define JI_GPIO_C_GLITCH_CFG0_CLR | ||
| 44 | |||
| 45 | #define REG_GPIO_C_GLITCH_CFG1 jz_reg(GPIO_C_GLITCH_CFG1) | ||
| 46 | #define JA_GPIO_C_GLITCH_CFG1 (0xb0010000 + 0x200 + 0x810) | ||
| 47 | #define JT_GPIO_C_GLITCH_CFG1 JIO_32_RW | ||
| 48 | #define JN_GPIO_C_GLITCH_CFG1 GPIO_C_GLITCH_CFG1 | ||
| 49 | #define JI_GPIO_C_GLITCH_CFG1 | ||
| 50 | #define REG_GPIO_C_GLITCH_CFG1_SET jz_reg(GPIO_C_GLITCH_CFG1_SET) | ||
| 51 | #define JA_GPIO_C_GLITCH_CFG1_SET (JA_GPIO_C_GLITCH_CFG1 + 0x4) | ||
| 52 | #define JT_GPIO_C_GLITCH_CFG1_SET JIO_32_WO | ||
| 53 | #define JN_GPIO_C_GLITCH_CFG1_SET GPIO_C_GLITCH_CFG1 | ||
| 54 | #define JI_GPIO_C_GLITCH_CFG1_SET | ||
| 55 | #define REG_GPIO_C_GLITCH_CFG1_CLR jz_reg(GPIO_C_GLITCH_CFG1_CLR) | ||
| 56 | #define JA_GPIO_C_GLITCH_CFG1_CLR (JA_GPIO_C_GLITCH_CFG1 + 0x8) | ||
| 57 | #define JT_GPIO_C_GLITCH_CFG1_CLR JIO_32_WO | ||
| 58 | #define JN_GPIO_C_GLITCH_CFG1_CLR GPIO_C_GLITCH_CFG1 | ||
| 59 | #define JI_GPIO_C_GLITCH_CFG1_CLR | ||
| 60 | |||
| 61 | #define REG_GPIO_C_GLITCH_CFG2 jz_reg(GPIO_C_GLITCH_CFG2) | ||
| 62 | #define JA_GPIO_C_GLITCH_CFG2 (0xb0010000 + 0x200 + 0x820) | ||
| 63 | #define JT_GPIO_C_GLITCH_CFG2 JIO_32_RW | ||
| 64 | #define JN_GPIO_C_GLITCH_CFG2 GPIO_C_GLITCH_CFG2 | ||
| 65 | #define JI_GPIO_C_GLITCH_CFG2 | ||
| 66 | #define REG_GPIO_C_GLITCH_CFG2_SET jz_reg(GPIO_C_GLITCH_CFG2_SET) | ||
| 67 | #define JA_GPIO_C_GLITCH_CFG2_SET (JA_GPIO_C_GLITCH_CFG2 + 0x4) | ||
| 68 | #define JT_GPIO_C_GLITCH_CFG2_SET JIO_32_WO | ||
| 69 | #define JN_GPIO_C_GLITCH_CFG2_SET GPIO_C_GLITCH_CFG2 | ||
| 70 | #define JI_GPIO_C_GLITCH_CFG2_SET | ||
| 71 | #define REG_GPIO_C_GLITCH_CFG2_CLR jz_reg(GPIO_C_GLITCH_CFG2_CLR) | ||
| 72 | #define JA_GPIO_C_GLITCH_CFG2_CLR (JA_GPIO_C_GLITCH_CFG2 + 0x8) | ||
| 73 | #define JT_GPIO_C_GLITCH_CFG2_CLR JIO_32_WO | ||
| 74 | #define JN_GPIO_C_GLITCH_CFG2_CLR GPIO_C_GLITCH_CFG2 | ||
| 75 | #define JI_GPIO_C_GLITCH_CFG2_CLR | ||
| 76 | |||
| 77 | #define REG_GPIO_C_GLITCH_CFG3 jz_reg(GPIO_C_GLITCH_CFG3) | ||
| 78 | #define JA_GPIO_C_GLITCH_CFG3 (0xb0010000 + 0x200 + 0x830) | ||
| 79 | #define JT_GPIO_C_GLITCH_CFG3 JIO_32_RW | ||
| 80 | #define JN_GPIO_C_GLITCH_CFG3 GPIO_C_GLITCH_CFG3 | ||
| 81 | #define JI_GPIO_C_GLITCH_CFG3 | ||
| 82 | #define REG_GPIO_C_GLITCH_CFG3_SET jz_reg(GPIO_C_GLITCH_CFG3_SET) | ||
| 83 | #define JA_GPIO_C_GLITCH_CFG3_SET (JA_GPIO_C_GLITCH_CFG3 + 0x4) | ||
| 84 | #define JT_GPIO_C_GLITCH_CFG3_SET JIO_32_WO | ||
| 85 | #define JN_GPIO_C_GLITCH_CFG3_SET GPIO_C_GLITCH_CFG3 | ||
| 86 | #define JI_GPIO_C_GLITCH_CFG3_SET | ||
| 87 | #define REG_GPIO_C_GLITCH_CFG3_CLR jz_reg(GPIO_C_GLITCH_CFG3_CLR) | ||
| 88 | #define JA_GPIO_C_GLITCH_CFG3_CLR (JA_GPIO_C_GLITCH_CFG3 + 0x8) | ||
| 89 | #define JT_GPIO_C_GLITCH_CFG3_CLR JIO_32_WO | ||
| 90 | #define JN_GPIO_C_GLITCH_CFG3_CLR GPIO_C_GLITCH_CFG3 | ||
| 91 | #define JI_GPIO_C_GLITCH_CFG3_CLR | ||
| 92 | |||
| 93 | #define REG_GPIO_PIN(_n1) jz_reg(GPIO_PIN(_n1)) | ||
| 94 | #define JA_GPIO_PIN(_n1) (0xb0010000 + 0x0 + (_n1) * 0x100) | ||
| 95 | #define JT_GPIO_PIN(_n1) JIO_32_RW | ||
| 96 | #define JN_GPIO_PIN(_n1) GPIO_PIN | ||
| 97 | #define JI_GPIO_PIN(_n1) (_n1) | ||
| 98 | |||
| 99 | #define REG_GPIO_INT(_n1) jz_reg(GPIO_INT(_n1)) | ||
| 100 | #define JA_GPIO_INT(_n1) (0xb0010000 + 0x10 + (_n1) * 0x100) | ||
| 101 | #define JT_GPIO_INT(_n1) JIO_32_RW | ||
| 102 | #define JN_GPIO_INT(_n1) GPIO_INT | ||
| 103 | #define JI_GPIO_INT(_n1) (_n1) | ||
| 104 | #define REG_GPIO_INT_SET(_n1) jz_reg(GPIO_INT_SET(_n1)) | ||
| 105 | #define JA_GPIO_INT_SET(_n1) (JA_GPIO_INT(_n1) + 0x4) | ||
| 106 | #define JT_GPIO_INT_SET(_n1) JIO_32_WO | ||
| 107 | #define JN_GPIO_INT_SET(_n1) GPIO_INT | ||
| 108 | #define JI_GPIO_INT_SET(_n1) (_n1) | ||
| 109 | #define REG_GPIO_INT_CLR(_n1) jz_reg(GPIO_INT_CLR(_n1)) | ||
| 110 | #define JA_GPIO_INT_CLR(_n1) (JA_GPIO_INT(_n1) + 0x8) | ||
| 111 | #define JT_GPIO_INT_CLR(_n1) JIO_32_WO | ||
| 112 | #define JN_GPIO_INT_CLR(_n1) GPIO_INT | ||
| 113 | #define JI_GPIO_INT_CLR(_n1) (_n1) | ||
| 114 | |||
| 115 | #define REG_GPIO_MSK(_n1) jz_reg(GPIO_MSK(_n1)) | ||
| 116 | #define JA_GPIO_MSK(_n1) (0xb0010000 + 0x20 + (_n1) * 0x100) | ||
| 117 | #define JT_GPIO_MSK(_n1) JIO_32_RW | ||
| 118 | #define JN_GPIO_MSK(_n1) GPIO_MSK | ||
| 119 | #define JI_GPIO_MSK(_n1) (_n1) | ||
| 120 | #define REG_GPIO_MSK_SET(_n1) jz_reg(GPIO_MSK_SET(_n1)) | ||
| 121 | #define JA_GPIO_MSK_SET(_n1) (JA_GPIO_MSK(_n1) + 0x4) | ||
| 122 | #define JT_GPIO_MSK_SET(_n1) JIO_32_WO | ||
| 123 | #define JN_GPIO_MSK_SET(_n1) GPIO_MSK | ||
| 124 | #define JI_GPIO_MSK_SET(_n1) (_n1) | ||
| 125 | #define REG_GPIO_MSK_CLR(_n1) jz_reg(GPIO_MSK_CLR(_n1)) | ||
| 126 | #define JA_GPIO_MSK_CLR(_n1) (JA_GPIO_MSK(_n1) + 0x8) | ||
| 127 | #define JT_GPIO_MSK_CLR(_n1) JIO_32_WO | ||
| 128 | #define JN_GPIO_MSK_CLR(_n1) GPIO_MSK | ||
| 129 | #define JI_GPIO_MSK_CLR(_n1) (_n1) | ||
| 130 | |||
| 131 | #define REG_GPIO_PAT1(_n1) jz_reg(GPIO_PAT1(_n1)) | ||
| 132 | #define JA_GPIO_PAT1(_n1) (0xb0010000 + 0x30 + (_n1) * 0x100) | ||
| 133 | #define JT_GPIO_PAT1(_n1) JIO_32_RW | ||
| 134 | #define JN_GPIO_PAT1(_n1) GPIO_PAT1 | ||
| 135 | #define JI_GPIO_PAT1(_n1) (_n1) | ||
| 136 | #define REG_GPIO_PAT1_SET(_n1) jz_reg(GPIO_PAT1_SET(_n1)) | ||
| 137 | #define JA_GPIO_PAT1_SET(_n1) (JA_GPIO_PAT1(_n1) + 0x4) | ||
| 138 | #define JT_GPIO_PAT1_SET(_n1) JIO_32_WO | ||
| 139 | #define JN_GPIO_PAT1_SET(_n1) GPIO_PAT1 | ||
| 140 | #define JI_GPIO_PAT1_SET(_n1) (_n1) | ||
| 141 | #define REG_GPIO_PAT1_CLR(_n1) jz_reg(GPIO_PAT1_CLR(_n1)) | ||
| 142 | #define JA_GPIO_PAT1_CLR(_n1) (JA_GPIO_PAT1(_n1) + 0x8) | ||
| 143 | #define JT_GPIO_PAT1_CLR(_n1) JIO_32_WO | ||
| 144 | #define JN_GPIO_PAT1_CLR(_n1) GPIO_PAT1 | ||
| 145 | #define JI_GPIO_PAT1_CLR(_n1) (_n1) | ||
| 146 | |||
| 147 | #define REG_GPIO_PAT0(_n1) jz_reg(GPIO_PAT0(_n1)) | ||
| 148 | #define JA_GPIO_PAT0(_n1) (0xb0010000 + 0x40 + (_n1) * 0x100) | ||
| 149 | #define JT_GPIO_PAT0(_n1) JIO_32_RW | ||
| 150 | #define JN_GPIO_PAT0(_n1) GPIO_PAT0 | ||
| 151 | #define JI_GPIO_PAT0(_n1) (_n1) | ||
| 152 | #define REG_GPIO_PAT0_SET(_n1) jz_reg(GPIO_PAT0_SET(_n1)) | ||
| 153 | #define JA_GPIO_PAT0_SET(_n1) (JA_GPIO_PAT0(_n1) + 0x4) | ||
| 154 | #define JT_GPIO_PAT0_SET(_n1) JIO_32_WO | ||
| 155 | #define JN_GPIO_PAT0_SET(_n1) GPIO_PAT0 | ||
| 156 | #define JI_GPIO_PAT0_SET(_n1) (_n1) | ||
| 157 | #define REG_GPIO_PAT0_CLR(_n1) jz_reg(GPIO_PAT0_CLR(_n1)) | ||
| 158 | #define JA_GPIO_PAT0_CLR(_n1) (JA_GPIO_PAT0(_n1) + 0x8) | ||
| 159 | #define JT_GPIO_PAT0_CLR(_n1) JIO_32_WO | ||
| 160 | #define JN_GPIO_PAT0_CLR(_n1) GPIO_PAT0 | ||
| 161 | #define JI_GPIO_PAT0_CLR(_n1) (_n1) | ||
| 162 | |||
| 163 | #define REG_GPIO_FLAG(_n1) jz_reg(GPIO_FLAG(_n1)) | ||
| 164 | #define JA_GPIO_FLAG(_n1) (0xb0010000 + 0x50 + (_n1) * 0x100) | ||
| 165 | #define JT_GPIO_FLAG(_n1) JIO_32_RW | ||
| 166 | #define JN_GPIO_FLAG(_n1) GPIO_FLAG | ||
| 167 | #define JI_GPIO_FLAG(_n1) (_n1) | ||
| 168 | #define REG_GPIO_FLAG_CLR(_n1) jz_reg(GPIO_FLAG_CLR(_n1)) | ||
| 169 | #define JA_GPIO_FLAG_CLR(_n1) (JA_GPIO_FLAG(_n1) + 0x8) | ||
| 170 | #define JT_GPIO_FLAG_CLR(_n1) JIO_32_WO | ||
| 171 | #define JN_GPIO_FLAG_CLR(_n1) GPIO_FLAG | ||
| 172 | #define JI_GPIO_FLAG_CLR(_n1) (_n1) | ||
| 173 | |||
| 174 | #define REG_GPIO_PULL(_n1) jz_reg(GPIO_PULL(_n1)) | ||
| 175 | #define JA_GPIO_PULL(_n1) (0xb0010000 + 0x70 + (_n1) * 0x100) | ||
| 176 | #define JT_GPIO_PULL(_n1) JIO_32_RW | ||
| 177 | #define JN_GPIO_PULL(_n1) GPIO_PULL | ||
| 178 | #define JI_GPIO_PULL(_n1) (_n1) | ||
| 179 | #define REG_GPIO_PULL_SET(_n1) jz_reg(GPIO_PULL_SET(_n1)) | ||
| 180 | #define JA_GPIO_PULL_SET(_n1) (JA_GPIO_PULL(_n1) + 0x4) | ||
| 181 | #define JT_GPIO_PULL_SET(_n1) JIO_32_WO | ||
| 182 | #define JN_GPIO_PULL_SET(_n1) GPIO_PULL | ||
| 183 | #define JI_GPIO_PULL_SET(_n1) (_n1) | ||
| 184 | #define REG_GPIO_PULL_CLR(_n1) jz_reg(GPIO_PULL_CLR(_n1)) | ||
| 185 | #define JA_GPIO_PULL_CLR(_n1) (JA_GPIO_PULL(_n1) + 0x8) | ||
| 186 | #define JT_GPIO_PULL_CLR(_n1) JIO_32_WO | ||
| 187 | #define JN_GPIO_PULL_CLR(_n1) GPIO_PULL | ||
| 188 | #define JI_GPIO_PULL_CLR(_n1) (_n1) | ||
| 189 | |||
| 190 | #define REG_GPIO_Z_GID2LD jz_reg(GPIO_Z_GID2LD) | ||
| 191 | #define JA_GPIO_Z_GID2LD (0xb0010000 + 0x7f0) | ||
| 192 | #define JT_GPIO_Z_GID2LD JIO_32_RW | ||
| 193 | #define JN_GPIO_Z_GID2LD GPIO_Z_GID2LD | ||
| 194 | #define JI_GPIO_Z_GID2LD | ||
| 195 | |||
| 196 | #endif /* __HEADERGEN_GPIO_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/i2c.h b/firmware/target/mips/ingenic_x1000/x1000/i2c.h new file mode 100644 index 0000000000..29f24bf82e --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/i2c.h | |||
| @@ -0,0 +1,625 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_I2C_H__ | ||
| 25 | #define __HEADERGEN_I2C_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_I2C_CON(_n1) jz_reg(I2C_CON(_n1)) | ||
| 30 | #define JA_I2C_CON(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x0) | ||
| 31 | #define JT_I2C_CON(_n1) JIO_32_RW | ||
| 32 | #define JN_I2C_CON(_n1) I2C_CON | ||
| 33 | #define JI_I2C_CON(_n1) (_n1) | ||
| 34 | #define BP_I2C_CON_SPEED 1 | ||
| 35 | #define BM_I2C_CON_SPEED 0x6 | ||
| 36 | #define BV_I2C_CON_SPEED__100K 0x1 | ||
| 37 | #define BV_I2C_CON_SPEED__400K 0x2 | ||
| 38 | #define BF_I2C_CON_SPEED(v) (((v) & 0x3) << 1) | ||
| 39 | #define BFM_I2C_CON_SPEED(v) BM_I2C_CON_SPEED | ||
| 40 | #define BF_I2C_CON_SPEED_V(e) BF_I2C_CON_SPEED(BV_I2C_CON_SPEED__##e) | ||
| 41 | #define BFM_I2C_CON_SPEED_V(v) BM_I2C_CON_SPEED | ||
| 42 | #define BP_I2C_CON_SLVDIS 6 | ||
| 43 | #define BM_I2C_CON_SLVDIS 0x40 | ||
| 44 | #define BF_I2C_CON_SLVDIS(v) (((v) & 0x1) << 6) | ||
| 45 | #define BFM_I2C_CON_SLVDIS(v) BM_I2C_CON_SLVDIS | ||
| 46 | #define BF_I2C_CON_SLVDIS_V(e) BF_I2C_CON_SLVDIS(BV_I2C_CON_SLVDIS__##e) | ||
| 47 | #define BFM_I2C_CON_SLVDIS_V(v) BM_I2C_CON_SLVDIS | ||
| 48 | #define BP_I2C_CON_RESTART 5 | ||
| 49 | #define BM_I2C_CON_RESTART 0x20 | ||
| 50 | #define BF_I2C_CON_RESTART(v) (((v) & 0x1) << 5) | ||
| 51 | #define BFM_I2C_CON_RESTART(v) BM_I2C_CON_RESTART | ||
| 52 | #define BF_I2C_CON_RESTART_V(e) BF_I2C_CON_RESTART(BV_I2C_CON_RESTART__##e) | ||
| 53 | #define BFM_I2C_CON_RESTART_V(v) BM_I2C_CON_RESTART | ||
| 54 | #define BP_I2C_CON_MATP 4 | ||
| 55 | #define BM_I2C_CON_MATP 0x10 | ||
| 56 | #define BF_I2C_CON_MATP(v) (((v) & 0x1) << 4) | ||
| 57 | #define BFM_I2C_CON_MATP(v) BM_I2C_CON_MATP | ||
| 58 | #define BF_I2C_CON_MATP_V(e) BF_I2C_CON_MATP(BV_I2C_CON_MATP__##e) | ||
| 59 | #define BFM_I2C_CON_MATP_V(v) BM_I2C_CON_MATP | ||
| 60 | #define BP_I2C_CON_SATP 3 | ||
| 61 | #define BM_I2C_CON_SATP 0x8 | ||
| 62 | #define BF_I2C_CON_SATP(v) (((v) & 0x1) << 3) | ||
| 63 | #define BFM_I2C_CON_SATP(v) BM_I2C_CON_SATP | ||
| 64 | #define BF_I2C_CON_SATP_V(e) BF_I2C_CON_SATP(BV_I2C_CON_SATP__##e) | ||
| 65 | #define BFM_I2C_CON_SATP_V(v) BM_I2C_CON_SATP | ||
| 66 | #define BP_I2C_CON_MD 0 | ||
| 67 | #define BM_I2C_CON_MD 0x1 | ||
| 68 | #define BF_I2C_CON_MD(v) (((v) & 0x1) << 0) | ||
| 69 | #define BFM_I2C_CON_MD(v) BM_I2C_CON_MD | ||
| 70 | #define BF_I2C_CON_MD_V(e) BF_I2C_CON_MD(BV_I2C_CON_MD__##e) | ||
| 71 | #define BFM_I2C_CON_MD_V(v) BM_I2C_CON_MD | ||
| 72 | |||
| 73 | #define REG_I2C_DC(_n1) jz_reg(I2C_DC(_n1)) | ||
| 74 | #define JA_I2C_DC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x10) | ||
| 75 | #define JT_I2C_DC(_n1) JIO_32_RW | ||
| 76 | #define JN_I2C_DC(_n1) I2C_DC | ||
| 77 | #define JI_I2C_DC(_n1) (_n1) | ||
| 78 | #define BP_I2C_DC_DAT 0 | ||
| 79 | #define BM_I2C_DC_DAT 0xff | ||
| 80 | #define BF_I2C_DC_DAT(v) (((v) & 0xff) << 0) | ||
| 81 | #define BFM_I2C_DC_DAT(v) BM_I2C_DC_DAT | ||
| 82 | #define BF_I2C_DC_DAT_V(e) BF_I2C_DC_DAT(BV_I2C_DC_DAT__##e) | ||
| 83 | #define BFM_I2C_DC_DAT_V(v) BM_I2C_DC_DAT | ||
| 84 | #define BP_I2C_DC_RESTART 10 | ||
| 85 | #define BM_I2C_DC_RESTART 0x400 | ||
| 86 | #define BF_I2C_DC_RESTART(v) (((v) & 0x1) << 10) | ||
| 87 | #define BFM_I2C_DC_RESTART(v) BM_I2C_DC_RESTART | ||
| 88 | #define BF_I2C_DC_RESTART_V(e) BF_I2C_DC_RESTART(BV_I2C_DC_RESTART__##e) | ||
| 89 | #define BFM_I2C_DC_RESTART_V(v) BM_I2C_DC_RESTART | ||
| 90 | #define BP_I2C_DC_STOP 9 | ||
| 91 | #define BM_I2C_DC_STOP 0x200 | ||
| 92 | #define BF_I2C_DC_STOP(v) (((v) & 0x1) << 9) | ||
| 93 | #define BFM_I2C_DC_STOP(v) BM_I2C_DC_STOP | ||
| 94 | #define BF_I2C_DC_STOP_V(e) BF_I2C_DC_STOP(BV_I2C_DC_STOP__##e) | ||
| 95 | #define BFM_I2C_DC_STOP_V(v) BM_I2C_DC_STOP | ||
| 96 | #define BP_I2C_DC_CMD 8 | ||
| 97 | #define BM_I2C_DC_CMD 0x100 | ||
| 98 | #define BF_I2C_DC_CMD(v) (((v) & 0x1) << 8) | ||
| 99 | #define BFM_I2C_DC_CMD(v) BM_I2C_DC_CMD | ||
| 100 | #define BF_I2C_DC_CMD_V(e) BF_I2C_DC_CMD(BV_I2C_DC_CMD__##e) | ||
| 101 | #define BFM_I2C_DC_CMD_V(v) BM_I2C_DC_CMD | ||
| 102 | |||
| 103 | #define REG_I2C_INTST(_n1) jz_reg(I2C_INTST(_n1)) | ||
| 104 | #define JA_I2C_INTST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x2c) | ||
| 105 | #define JT_I2C_INTST(_n1) JIO_32_RW | ||
| 106 | #define JN_I2C_INTST(_n1) I2C_INTST | ||
| 107 | #define JI_I2C_INTST(_n1) (_n1) | ||
| 108 | #define BP_I2C_INTST_GC 11 | ||
| 109 | #define BM_I2C_INTST_GC 0x800 | ||
| 110 | #define BF_I2C_INTST_GC(v) (((v) & 0x1) << 11) | ||
| 111 | #define BFM_I2C_INTST_GC(v) BM_I2C_INTST_GC | ||
| 112 | #define BF_I2C_INTST_GC_V(e) BF_I2C_INTST_GC(BV_I2C_INTST_GC__##e) | ||
| 113 | #define BFM_I2C_INTST_GC_V(v) BM_I2C_INTST_GC | ||
| 114 | #define BP_I2C_INTST_STT 10 | ||
| 115 | #define BM_I2C_INTST_STT 0x400 | ||
| 116 | #define BF_I2C_INTST_STT(v) (((v) & 0x1) << 10) | ||
| 117 | #define BFM_I2C_INTST_STT(v) BM_I2C_INTST_STT | ||
| 118 | #define BF_I2C_INTST_STT_V(e) BF_I2C_INTST_STT(BV_I2C_INTST_STT__##e) | ||
| 119 | #define BFM_I2C_INTST_STT_V(v) BM_I2C_INTST_STT | ||
| 120 | #define BP_I2C_INTST_STP 9 | ||
| 121 | #define BM_I2C_INTST_STP 0x200 | ||
| 122 | #define BF_I2C_INTST_STP(v) (((v) & 0x1) << 9) | ||
| 123 | #define BFM_I2C_INTST_STP(v) BM_I2C_INTST_STP | ||
| 124 | #define BF_I2C_INTST_STP_V(e) BF_I2C_INTST_STP(BV_I2C_INTST_STP__##e) | ||
| 125 | #define BFM_I2C_INTST_STP_V(v) BM_I2C_INTST_STP | ||
| 126 | #define BP_I2C_INTST_ACT 8 | ||
| 127 | #define BM_I2C_INTST_ACT 0x100 | ||
| 128 | #define BF_I2C_INTST_ACT(v) (((v) & 0x1) << 8) | ||
| 129 | #define BFM_I2C_INTST_ACT(v) BM_I2C_INTST_ACT | ||
| 130 | #define BF_I2C_INTST_ACT_V(e) BF_I2C_INTST_ACT(BV_I2C_INTST_ACT__##e) | ||
| 131 | #define BFM_I2C_INTST_ACT_V(v) BM_I2C_INTST_ACT | ||
| 132 | #define BP_I2C_INTST_RXDN 7 | ||
| 133 | #define BM_I2C_INTST_RXDN 0x80 | ||
| 134 | #define BF_I2C_INTST_RXDN(v) (((v) & 0x1) << 7) | ||
| 135 | #define BFM_I2C_INTST_RXDN(v) BM_I2C_INTST_RXDN | ||
| 136 | #define BF_I2C_INTST_RXDN_V(e) BF_I2C_INTST_RXDN(BV_I2C_INTST_RXDN__##e) | ||
| 137 | #define BFM_I2C_INTST_RXDN_V(v) BM_I2C_INTST_RXDN | ||
| 138 | #define BP_I2C_INTST_TXABT 6 | ||
| 139 | #define BM_I2C_INTST_TXABT 0x40 | ||
| 140 | #define BF_I2C_INTST_TXABT(v) (((v) & 0x1) << 6) | ||
| 141 | #define BFM_I2C_INTST_TXABT(v) BM_I2C_INTST_TXABT | ||
| 142 | #define BF_I2C_INTST_TXABT_V(e) BF_I2C_INTST_TXABT(BV_I2C_INTST_TXABT__##e) | ||
| 143 | #define BFM_I2C_INTST_TXABT_V(v) BM_I2C_INTST_TXABT | ||
| 144 | #define BP_I2C_INTST_RDREQ 5 | ||
| 145 | #define BM_I2C_INTST_RDREQ 0x20 | ||
| 146 | #define BF_I2C_INTST_RDREQ(v) (((v) & 0x1) << 5) | ||
| 147 | #define BFM_I2C_INTST_RDREQ(v) BM_I2C_INTST_RDREQ | ||
| 148 | #define BF_I2C_INTST_RDREQ_V(e) BF_I2C_INTST_RDREQ(BV_I2C_INTST_RDREQ__##e) | ||
| 149 | #define BFM_I2C_INTST_RDREQ_V(v) BM_I2C_INTST_RDREQ | ||
| 150 | #define BP_I2C_INTST_TXEMP 4 | ||
| 151 | #define BM_I2C_INTST_TXEMP 0x10 | ||
| 152 | #define BF_I2C_INTST_TXEMP(v) (((v) & 0x1) << 4) | ||
| 153 | #define BFM_I2C_INTST_TXEMP(v) BM_I2C_INTST_TXEMP | ||
| 154 | #define BF_I2C_INTST_TXEMP_V(e) BF_I2C_INTST_TXEMP(BV_I2C_INTST_TXEMP__##e) | ||
| 155 | #define BFM_I2C_INTST_TXEMP_V(v) BM_I2C_INTST_TXEMP | ||
| 156 | #define BP_I2C_INTST_TXOF 3 | ||
| 157 | #define BM_I2C_INTST_TXOF 0x8 | ||
| 158 | #define BF_I2C_INTST_TXOF(v) (((v) & 0x1) << 3) | ||
| 159 | #define BFM_I2C_INTST_TXOF(v) BM_I2C_INTST_TXOF | ||
| 160 | #define BF_I2C_INTST_TXOF_V(e) BF_I2C_INTST_TXOF(BV_I2C_INTST_TXOF__##e) | ||
| 161 | #define BFM_I2C_INTST_TXOF_V(v) BM_I2C_INTST_TXOF | ||
| 162 | #define BP_I2C_INTST_RXFL 2 | ||
| 163 | #define BM_I2C_INTST_RXFL 0x4 | ||
| 164 | #define BF_I2C_INTST_RXFL(v) (((v) & 0x1) << 2) | ||
| 165 | #define BFM_I2C_INTST_RXFL(v) BM_I2C_INTST_RXFL | ||
| 166 | #define BF_I2C_INTST_RXFL_V(e) BF_I2C_INTST_RXFL(BV_I2C_INTST_RXFL__##e) | ||
| 167 | #define BFM_I2C_INTST_RXFL_V(v) BM_I2C_INTST_RXFL | ||
| 168 | #define BP_I2C_INTST_RXOF 1 | ||
| 169 | #define BM_I2C_INTST_RXOF 0x2 | ||
| 170 | #define BF_I2C_INTST_RXOF(v) (((v) & 0x1) << 1) | ||
| 171 | #define BFM_I2C_INTST_RXOF(v) BM_I2C_INTST_RXOF | ||
| 172 | #define BF_I2C_INTST_RXOF_V(e) BF_I2C_INTST_RXOF(BV_I2C_INTST_RXOF__##e) | ||
| 173 | #define BFM_I2C_INTST_RXOF_V(v) BM_I2C_INTST_RXOF | ||
| 174 | #define BP_I2C_INTST_RXUF 0 | ||
| 175 | #define BM_I2C_INTST_RXUF 0x1 | ||
| 176 | #define BF_I2C_INTST_RXUF(v) (((v) & 0x1) << 0) | ||
| 177 | #define BFM_I2C_INTST_RXUF(v) BM_I2C_INTST_RXUF | ||
| 178 | #define BF_I2C_INTST_RXUF_V(e) BF_I2C_INTST_RXUF(BV_I2C_INTST_RXUF__##e) | ||
| 179 | #define BFM_I2C_INTST_RXUF_V(v) BM_I2C_INTST_RXUF | ||
| 180 | |||
| 181 | #define REG_I2C_INTMSK(_n1) jz_reg(I2C_INTMSK(_n1)) | ||
| 182 | #define JA_I2C_INTMSK(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x30) | ||
| 183 | #define JT_I2C_INTMSK(_n1) JIO_32_RW | ||
| 184 | #define JN_I2C_INTMSK(_n1) I2C_INTMSK | ||
| 185 | #define JI_I2C_INTMSK(_n1) (_n1) | ||
| 186 | #define BP_I2C_INTMSK_GC 11 | ||
| 187 | #define BM_I2C_INTMSK_GC 0x800 | ||
| 188 | #define BF_I2C_INTMSK_GC(v) (((v) & 0x1) << 11) | ||
| 189 | #define BFM_I2C_INTMSK_GC(v) BM_I2C_INTMSK_GC | ||
| 190 | #define BF_I2C_INTMSK_GC_V(e) BF_I2C_INTMSK_GC(BV_I2C_INTMSK_GC__##e) | ||
| 191 | #define BFM_I2C_INTMSK_GC_V(v) BM_I2C_INTMSK_GC | ||
| 192 | #define BP_I2C_INTMSK_STT 10 | ||
| 193 | #define BM_I2C_INTMSK_STT 0x400 | ||
| 194 | #define BF_I2C_INTMSK_STT(v) (((v) & 0x1) << 10) | ||
| 195 | #define BFM_I2C_INTMSK_STT(v) BM_I2C_INTMSK_STT | ||
| 196 | #define BF_I2C_INTMSK_STT_V(e) BF_I2C_INTMSK_STT(BV_I2C_INTMSK_STT__##e) | ||
| 197 | #define BFM_I2C_INTMSK_STT_V(v) BM_I2C_INTMSK_STT | ||
| 198 | #define BP_I2C_INTMSK_STP 9 | ||
| 199 | #define BM_I2C_INTMSK_STP 0x200 | ||
| 200 | #define BF_I2C_INTMSK_STP(v) (((v) & 0x1) << 9) | ||
| 201 | #define BFM_I2C_INTMSK_STP(v) BM_I2C_INTMSK_STP | ||
| 202 | #define BF_I2C_INTMSK_STP_V(e) BF_I2C_INTMSK_STP(BV_I2C_INTMSK_STP__##e) | ||
| 203 | #define BFM_I2C_INTMSK_STP_V(v) BM_I2C_INTMSK_STP | ||
| 204 | #define BP_I2C_INTMSK_ACT 8 | ||
| 205 | #define BM_I2C_INTMSK_ACT 0x100 | ||
| 206 | #define BF_I2C_INTMSK_ACT(v) (((v) & 0x1) << 8) | ||
| 207 | #define BFM_I2C_INTMSK_ACT(v) BM_I2C_INTMSK_ACT | ||
| 208 | #define BF_I2C_INTMSK_ACT_V(e) BF_I2C_INTMSK_ACT(BV_I2C_INTMSK_ACT__##e) | ||
| 209 | #define BFM_I2C_INTMSK_ACT_V(v) BM_I2C_INTMSK_ACT | ||
| 210 | #define BP_I2C_INTMSK_RXDN 7 | ||
| 211 | #define BM_I2C_INTMSK_RXDN 0x80 | ||
| 212 | #define BF_I2C_INTMSK_RXDN(v) (((v) & 0x1) << 7) | ||
| 213 | #define BFM_I2C_INTMSK_RXDN(v) BM_I2C_INTMSK_RXDN | ||
| 214 | #define BF_I2C_INTMSK_RXDN_V(e) BF_I2C_INTMSK_RXDN(BV_I2C_INTMSK_RXDN__##e) | ||
| 215 | #define BFM_I2C_INTMSK_RXDN_V(v) BM_I2C_INTMSK_RXDN | ||
| 216 | #define BP_I2C_INTMSK_TXABT 6 | ||
| 217 | #define BM_I2C_INTMSK_TXABT 0x40 | ||
| 218 | #define BF_I2C_INTMSK_TXABT(v) (((v) & 0x1) << 6) | ||
| 219 | #define BFM_I2C_INTMSK_TXABT(v) BM_I2C_INTMSK_TXABT | ||
| 220 | #define BF_I2C_INTMSK_TXABT_V(e) BF_I2C_INTMSK_TXABT(BV_I2C_INTMSK_TXABT__##e) | ||
| 221 | #define BFM_I2C_INTMSK_TXABT_V(v) BM_I2C_INTMSK_TXABT | ||
| 222 | #define BP_I2C_INTMSK_RDREQ 5 | ||
| 223 | #define BM_I2C_INTMSK_RDREQ 0x20 | ||
| 224 | #define BF_I2C_INTMSK_RDREQ(v) (((v) & 0x1) << 5) | ||
| 225 | #define BFM_I2C_INTMSK_RDREQ(v) BM_I2C_INTMSK_RDREQ | ||
| 226 | #define BF_I2C_INTMSK_RDREQ_V(e) BF_I2C_INTMSK_RDREQ(BV_I2C_INTMSK_RDREQ__##e) | ||
| 227 | #define BFM_I2C_INTMSK_RDREQ_V(v) BM_I2C_INTMSK_RDREQ | ||
| 228 | #define BP_I2C_INTMSK_TXEMP 4 | ||
| 229 | #define BM_I2C_INTMSK_TXEMP 0x10 | ||
| 230 | #define BF_I2C_INTMSK_TXEMP(v) (((v) & 0x1) << 4) | ||
| 231 | #define BFM_I2C_INTMSK_TXEMP(v) BM_I2C_INTMSK_TXEMP | ||
| 232 | #define BF_I2C_INTMSK_TXEMP_V(e) BF_I2C_INTMSK_TXEMP(BV_I2C_INTMSK_TXEMP__##e) | ||
| 233 | #define BFM_I2C_INTMSK_TXEMP_V(v) BM_I2C_INTMSK_TXEMP | ||
| 234 | #define BP_I2C_INTMSK_TXOF 3 | ||
| 235 | #define BM_I2C_INTMSK_TXOF 0x8 | ||
| 236 | #define BF_I2C_INTMSK_TXOF(v) (((v) & 0x1) << 3) | ||
| 237 | #define BFM_I2C_INTMSK_TXOF(v) BM_I2C_INTMSK_TXOF | ||
| 238 | #define BF_I2C_INTMSK_TXOF_V(e) BF_I2C_INTMSK_TXOF(BV_I2C_INTMSK_TXOF__##e) | ||
| 239 | #define BFM_I2C_INTMSK_TXOF_V(v) BM_I2C_INTMSK_TXOF | ||
| 240 | #define BP_I2C_INTMSK_RXFL 2 | ||
| 241 | #define BM_I2C_INTMSK_RXFL 0x4 | ||
| 242 | #define BF_I2C_INTMSK_RXFL(v) (((v) & 0x1) << 2) | ||
| 243 | #define BFM_I2C_INTMSK_RXFL(v) BM_I2C_INTMSK_RXFL | ||
| 244 | #define BF_I2C_INTMSK_RXFL_V(e) BF_I2C_INTMSK_RXFL(BV_I2C_INTMSK_RXFL__##e) | ||
| 245 | #define BFM_I2C_INTMSK_RXFL_V(v) BM_I2C_INTMSK_RXFL | ||
| 246 | #define BP_I2C_INTMSK_RXOF 1 | ||
| 247 | #define BM_I2C_INTMSK_RXOF 0x2 | ||
| 248 | #define BF_I2C_INTMSK_RXOF(v) (((v) & 0x1) << 1) | ||
| 249 | #define BFM_I2C_INTMSK_RXOF(v) BM_I2C_INTMSK_RXOF | ||
| 250 | #define BF_I2C_INTMSK_RXOF_V(e) BF_I2C_INTMSK_RXOF(BV_I2C_INTMSK_RXOF__##e) | ||
| 251 | #define BFM_I2C_INTMSK_RXOF_V(v) BM_I2C_INTMSK_RXOF | ||
| 252 | #define BP_I2C_INTMSK_RXUF 0 | ||
| 253 | #define BM_I2C_INTMSK_RXUF 0x1 | ||
| 254 | #define BF_I2C_INTMSK_RXUF(v) (((v) & 0x1) << 0) | ||
| 255 | #define BFM_I2C_INTMSK_RXUF(v) BM_I2C_INTMSK_RXUF | ||
| 256 | #define BF_I2C_INTMSK_RXUF_V(e) BF_I2C_INTMSK_RXUF(BV_I2C_INTMSK_RXUF__##e) | ||
| 257 | #define BFM_I2C_INTMSK_RXUF_V(v) BM_I2C_INTMSK_RXUF | ||
| 258 | |||
| 259 | #define REG_I2C_RINTST(_n1) jz_reg(I2C_RINTST(_n1)) | ||
| 260 | #define JA_I2C_RINTST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x34) | ||
| 261 | #define JT_I2C_RINTST(_n1) JIO_32_RW | ||
| 262 | #define JN_I2C_RINTST(_n1) I2C_RINTST | ||
| 263 | #define JI_I2C_RINTST(_n1) (_n1) | ||
| 264 | #define BP_I2C_RINTST_GC 11 | ||
| 265 | #define BM_I2C_RINTST_GC 0x800 | ||
| 266 | #define BF_I2C_RINTST_GC(v) (((v) & 0x1) << 11) | ||
| 267 | #define BFM_I2C_RINTST_GC(v) BM_I2C_RINTST_GC | ||
| 268 | #define BF_I2C_RINTST_GC_V(e) BF_I2C_RINTST_GC(BV_I2C_RINTST_GC__##e) | ||
| 269 | #define BFM_I2C_RINTST_GC_V(v) BM_I2C_RINTST_GC | ||
| 270 | #define BP_I2C_RINTST_STT 10 | ||
| 271 | #define BM_I2C_RINTST_STT 0x400 | ||
| 272 | #define BF_I2C_RINTST_STT(v) (((v) & 0x1) << 10) | ||
| 273 | #define BFM_I2C_RINTST_STT(v) BM_I2C_RINTST_STT | ||
| 274 | #define BF_I2C_RINTST_STT_V(e) BF_I2C_RINTST_STT(BV_I2C_RINTST_STT__##e) | ||
| 275 | #define BFM_I2C_RINTST_STT_V(v) BM_I2C_RINTST_STT | ||
| 276 | #define BP_I2C_RINTST_STP 9 | ||
| 277 | #define BM_I2C_RINTST_STP 0x200 | ||
| 278 | #define BF_I2C_RINTST_STP(v) (((v) & 0x1) << 9) | ||
| 279 | #define BFM_I2C_RINTST_STP(v) BM_I2C_RINTST_STP | ||
| 280 | #define BF_I2C_RINTST_STP_V(e) BF_I2C_RINTST_STP(BV_I2C_RINTST_STP__##e) | ||
| 281 | #define BFM_I2C_RINTST_STP_V(v) BM_I2C_RINTST_STP | ||
| 282 | #define BP_I2C_RINTST_ACT 8 | ||
| 283 | #define BM_I2C_RINTST_ACT 0x100 | ||
| 284 | #define BF_I2C_RINTST_ACT(v) (((v) & 0x1) << 8) | ||
| 285 | #define BFM_I2C_RINTST_ACT(v) BM_I2C_RINTST_ACT | ||
| 286 | #define BF_I2C_RINTST_ACT_V(e) BF_I2C_RINTST_ACT(BV_I2C_RINTST_ACT__##e) | ||
| 287 | #define BFM_I2C_RINTST_ACT_V(v) BM_I2C_RINTST_ACT | ||
| 288 | #define BP_I2C_RINTST_RXDN 7 | ||
| 289 | #define BM_I2C_RINTST_RXDN 0x80 | ||
| 290 | #define BF_I2C_RINTST_RXDN(v) (((v) & 0x1) << 7) | ||
| 291 | #define BFM_I2C_RINTST_RXDN(v) BM_I2C_RINTST_RXDN | ||
| 292 | #define BF_I2C_RINTST_RXDN_V(e) BF_I2C_RINTST_RXDN(BV_I2C_RINTST_RXDN__##e) | ||
| 293 | #define BFM_I2C_RINTST_RXDN_V(v) BM_I2C_RINTST_RXDN | ||
| 294 | #define BP_I2C_RINTST_TXABT 6 | ||
| 295 | #define BM_I2C_RINTST_TXABT 0x40 | ||
| 296 | #define BF_I2C_RINTST_TXABT(v) (((v) & 0x1) << 6) | ||
| 297 | #define BFM_I2C_RINTST_TXABT(v) BM_I2C_RINTST_TXABT | ||
| 298 | #define BF_I2C_RINTST_TXABT_V(e) BF_I2C_RINTST_TXABT(BV_I2C_RINTST_TXABT__##e) | ||
| 299 | #define BFM_I2C_RINTST_TXABT_V(v) BM_I2C_RINTST_TXABT | ||
| 300 | #define BP_I2C_RINTST_RDREQ 5 | ||
| 301 | #define BM_I2C_RINTST_RDREQ 0x20 | ||
| 302 | #define BF_I2C_RINTST_RDREQ(v) (((v) & 0x1) << 5) | ||
| 303 | #define BFM_I2C_RINTST_RDREQ(v) BM_I2C_RINTST_RDREQ | ||
| 304 | #define BF_I2C_RINTST_RDREQ_V(e) BF_I2C_RINTST_RDREQ(BV_I2C_RINTST_RDREQ__##e) | ||
| 305 | #define BFM_I2C_RINTST_RDREQ_V(v) BM_I2C_RINTST_RDREQ | ||
| 306 | #define BP_I2C_RINTST_TXEMP 4 | ||
| 307 | #define BM_I2C_RINTST_TXEMP 0x10 | ||
| 308 | #define BF_I2C_RINTST_TXEMP(v) (((v) & 0x1) << 4) | ||
| 309 | #define BFM_I2C_RINTST_TXEMP(v) BM_I2C_RINTST_TXEMP | ||
| 310 | #define BF_I2C_RINTST_TXEMP_V(e) BF_I2C_RINTST_TXEMP(BV_I2C_RINTST_TXEMP__##e) | ||
| 311 | #define BFM_I2C_RINTST_TXEMP_V(v) BM_I2C_RINTST_TXEMP | ||
| 312 | #define BP_I2C_RINTST_TXOF 3 | ||
| 313 | #define BM_I2C_RINTST_TXOF 0x8 | ||
| 314 | #define BF_I2C_RINTST_TXOF(v) (((v) & 0x1) << 3) | ||
| 315 | #define BFM_I2C_RINTST_TXOF(v) BM_I2C_RINTST_TXOF | ||
| 316 | #define BF_I2C_RINTST_TXOF_V(e) BF_I2C_RINTST_TXOF(BV_I2C_RINTST_TXOF__##e) | ||
| 317 | #define BFM_I2C_RINTST_TXOF_V(v) BM_I2C_RINTST_TXOF | ||
| 318 | #define BP_I2C_RINTST_RXFL 2 | ||
| 319 | #define BM_I2C_RINTST_RXFL 0x4 | ||
| 320 | #define BF_I2C_RINTST_RXFL(v) (((v) & 0x1) << 2) | ||
| 321 | #define BFM_I2C_RINTST_RXFL(v) BM_I2C_RINTST_RXFL | ||
| 322 | #define BF_I2C_RINTST_RXFL_V(e) BF_I2C_RINTST_RXFL(BV_I2C_RINTST_RXFL__##e) | ||
| 323 | #define BFM_I2C_RINTST_RXFL_V(v) BM_I2C_RINTST_RXFL | ||
| 324 | #define BP_I2C_RINTST_RXOF 1 | ||
| 325 | #define BM_I2C_RINTST_RXOF 0x2 | ||
| 326 | #define BF_I2C_RINTST_RXOF(v) (((v) & 0x1) << 1) | ||
| 327 | #define BFM_I2C_RINTST_RXOF(v) BM_I2C_RINTST_RXOF | ||
| 328 | #define BF_I2C_RINTST_RXOF_V(e) BF_I2C_RINTST_RXOF(BV_I2C_RINTST_RXOF__##e) | ||
| 329 | #define BFM_I2C_RINTST_RXOF_V(v) BM_I2C_RINTST_RXOF | ||
| 330 | #define BP_I2C_RINTST_RXUF 0 | ||
| 331 | #define BM_I2C_RINTST_RXUF 0x1 | ||
| 332 | #define BF_I2C_RINTST_RXUF(v) (((v) & 0x1) << 0) | ||
| 333 | #define BFM_I2C_RINTST_RXUF(v) BM_I2C_RINTST_RXUF | ||
| 334 | #define BF_I2C_RINTST_RXUF_V(e) BF_I2C_RINTST_RXUF(BV_I2C_RINTST_RXUF__##e) | ||
| 335 | #define BFM_I2C_RINTST_RXUF_V(v) BM_I2C_RINTST_RXUF | ||
| 336 | |||
| 337 | #define REG_I2C_ENABLE(_n1) jz_reg(I2C_ENABLE(_n1)) | ||
| 338 | #define JA_I2C_ENABLE(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x6c) | ||
| 339 | #define JT_I2C_ENABLE(_n1) JIO_32_RW | ||
| 340 | #define JN_I2C_ENABLE(_n1) I2C_ENABLE | ||
| 341 | #define JI_I2C_ENABLE(_n1) (_n1) | ||
| 342 | #define BP_I2C_ENABLE_ABORT 1 | ||
| 343 | #define BM_I2C_ENABLE_ABORT 0x2 | ||
| 344 | #define BF_I2C_ENABLE_ABORT(v) (((v) & 0x1) << 1) | ||
| 345 | #define BFM_I2C_ENABLE_ABORT(v) BM_I2C_ENABLE_ABORT | ||
| 346 | #define BF_I2C_ENABLE_ABORT_V(e) BF_I2C_ENABLE_ABORT(BV_I2C_ENABLE_ABORT__##e) | ||
| 347 | #define BFM_I2C_ENABLE_ABORT_V(v) BM_I2C_ENABLE_ABORT | ||
| 348 | #define BP_I2C_ENABLE_ACTIVE 0 | ||
| 349 | #define BM_I2C_ENABLE_ACTIVE 0x1 | ||
| 350 | #define BF_I2C_ENABLE_ACTIVE(v) (((v) & 0x1) << 0) | ||
| 351 | #define BFM_I2C_ENABLE_ACTIVE(v) BM_I2C_ENABLE_ACTIVE | ||
| 352 | #define BF_I2C_ENABLE_ACTIVE_V(e) BF_I2C_ENABLE_ACTIVE(BV_I2C_ENABLE_ACTIVE__##e) | ||
| 353 | #define BFM_I2C_ENABLE_ACTIVE_V(v) BM_I2C_ENABLE_ACTIVE | ||
| 354 | |||
| 355 | #define REG_I2C_STATUS(_n1) jz_reg(I2C_STATUS(_n1)) | ||
| 356 | #define JA_I2C_STATUS(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x70) | ||
| 357 | #define JT_I2C_STATUS(_n1) JIO_32_RW | ||
| 358 | #define JN_I2C_STATUS(_n1) I2C_STATUS | ||
| 359 | #define JI_I2C_STATUS(_n1) (_n1) | ||
| 360 | #define BP_I2C_STATUS_SLVACT 6 | ||
| 361 | #define BM_I2C_STATUS_SLVACT 0x40 | ||
| 362 | #define BF_I2C_STATUS_SLVACT(v) (((v) & 0x1) << 6) | ||
| 363 | #define BFM_I2C_STATUS_SLVACT(v) BM_I2C_STATUS_SLVACT | ||
| 364 | #define BF_I2C_STATUS_SLVACT_V(e) BF_I2C_STATUS_SLVACT(BV_I2C_STATUS_SLVACT__##e) | ||
| 365 | #define BFM_I2C_STATUS_SLVACT_V(v) BM_I2C_STATUS_SLVACT | ||
| 366 | #define BP_I2C_STATUS_MSTACT 5 | ||
| 367 | #define BM_I2C_STATUS_MSTACT 0x20 | ||
| 368 | #define BF_I2C_STATUS_MSTACT(v) (((v) & 0x1) << 5) | ||
| 369 | #define BFM_I2C_STATUS_MSTACT(v) BM_I2C_STATUS_MSTACT | ||
| 370 | #define BF_I2C_STATUS_MSTACT_V(e) BF_I2C_STATUS_MSTACT(BV_I2C_STATUS_MSTACT__##e) | ||
| 371 | #define BFM_I2C_STATUS_MSTACT_V(v) BM_I2C_STATUS_MSTACT | ||
| 372 | #define BP_I2C_STATUS_RFF 4 | ||
| 373 | #define BM_I2C_STATUS_RFF 0x10 | ||
| 374 | #define BF_I2C_STATUS_RFF(v) (((v) & 0x1) << 4) | ||
| 375 | #define BFM_I2C_STATUS_RFF(v) BM_I2C_STATUS_RFF | ||
| 376 | #define BF_I2C_STATUS_RFF_V(e) BF_I2C_STATUS_RFF(BV_I2C_STATUS_RFF__##e) | ||
| 377 | #define BFM_I2C_STATUS_RFF_V(v) BM_I2C_STATUS_RFF | ||
| 378 | #define BP_I2C_STATUS_RFNE 3 | ||
| 379 | #define BM_I2C_STATUS_RFNE 0x8 | ||
| 380 | #define BF_I2C_STATUS_RFNE(v) (((v) & 0x1) << 3) | ||
| 381 | #define BFM_I2C_STATUS_RFNE(v) BM_I2C_STATUS_RFNE | ||
| 382 | #define BF_I2C_STATUS_RFNE_V(e) BF_I2C_STATUS_RFNE(BV_I2C_STATUS_RFNE__##e) | ||
| 383 | #define BFM_I2C_STATUS_RFNE_V(v) BM_I2C_STATUS_RFNE | ||
| 384 | #define BP_I2C_STATUS_TFE 2 | ||
| 385 | #define BM_I2C_STATUS_TFE 0x4 | ||
| 386 | #define BF_I2C_STATUS_TFE(v) (((v) & 0x1) << 2) | ||
| 387 | #define BFM_I2C_STATUS_TFE(v) BM_I2C_STATUS_TFE | ||
| 388 | #define BF_I2C_STATUS_TFE_V(e) BF_I2C_STATUS_TFE(BV_I2C_STATUS_TFE__##e) | ||
| 389 | #define BFM_I2C_STATUS_TFE_V(v) BM_I2C_STATUS_TFE | ||
| 390 | #define BP_I2C_STATUS_TFNF 1 | ||
| 391 | #define BM_I2C_STATUS_TFNF 0x2 | ||
| 392 | #define BF_I2C_STATUS_TFNF(v) (((v) & 0x1) << 1) | ||
| 393 | #define BFM_I2C_STATUS_TFNF(v) BM_I2C_STATUS_TFNF | ||
| 394 | #define BF_I2C_STATUS_TFNF_V(e) BF_I2C_STATUS_TFNF(BV_I2C_STATUS_TFNF__##e) | ||
| 395 | #define BFM_I2C_STATUS_TFNF_V(v) BM_I2C_STATUS_TFNF | ||
| 396 | #define BP_I2C_STATUS_ACT 0 | ||
| 397 | #define BM_I2C_STATUS_ACT 0x1 | ||
| 398 | #define BF_I2C_STATUS_ACT(v) (((v) & 0x1) << 0) | ||
| 399 | #define BFM_I2C_STATUS_ACT(v) BM_I2C_STATUS_ACT | ||
| 400 | #define BF_I2C_STATUS_ACT_V(e) BF_I2C_STATUS_ACT(BV_I2C_STATUS_ACT__##e) | ||
| 401 | #define BFM_I2C_STATUS_ACT_V(v) BM_I2C_STATUS_ACT | ||
| 402 | |||
| 403 | #define REG_I2C_ENBST(_n1) jz_reg(I2C_ENBST(_n1)) | ||
| 404 | #define JA_I2C_ENBST(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x9c) | ||
| 405 | #define JT_I2C_ENBST(_n1) JIO_32_RW | ||
| 406 | #define JN_I2C_ENBST(_n1) I2C_ENBST | ||
| 407 | #define JI_I2C_ENBST(_n1) (_n1) | ||
| 408 | #define BP_I2C_ENBST_SLVRDLST 2 | ||
| 409 | #define BM_I2C_ENBST_SLVRDLST 0x4 | ||
| 410 | #define BF_I2C_ENBST_SLVRDLST(v) (((v) & 0x1) << 2) | ||
| 411 | #define BFM_I2C_ENBST_SLVRDLST(v) BM_I2C_ENBST_SLVRDLST | ||
| 412 | #define BF_I2C_ENBST_SLVRDLST_V(e) BF_I2C_ENBST_SLVRDLST(BV_I2C_ENBST_SLVRDLST__##e) | ||
| 413 | #define BFM_I2C_ENBST_SLVRDLST_V(v) BM_I2C_ENBST_SLVRDLST | ||
| 414 | #define BP_I2C_ENBST_SLVDISB 1 | ||
| 415 | #define BM_I2C_ENBST_SLVDISB 0x2 | ||
| 416 | #define BF_I2C_ENBST_SLVDISB(v) (((v) & 0x1) << 1) | ||
| 417 | #define BFM_I2C_ENBST_SLVDISB(v) BM_I2C_ENBST_SLVDISB | ||
| 418 | #define BF_I2C_ENBST_SLVDISB_V(e) BF_I2C_ENBST_SLVDISB(BV_I2C_ENBST_SLVDISB__##e) | ||
| 419 | #define BFM_I2C_ENBST_SLVDISB_V(v) BM_I2C_ENBST_SLVDISB | ||
| 420 | #define BP_I2C_ENBST_ACTIVE 0 | ||
| 421 | #define BM_I2C_ENBST_ACTIVE 0x1 | ||
| 422 | #define BF_I2C_ENBST_ACTIVE(v) (((v) & 0x1) << 0) | ||
| 423 | #define BFM_I2C_ENBST_ACTIVE(v) BM_I2C_ENBST_ACTIVE | ||
| 424 | #define BF_I2C_ENBST_ACTIVE_V(e) BF_I2C_ENBST_ACTIVE(BV_I2C_ENBST_ACTIVE__##e) | ||
| 425 | #define BFM_I2C_ENBST_ACTIVE_V(v) BM_I2C_ENBST_ACTIVE | ||
| 426 | |||
| 427 | #define REG_I2C_TAR(_n1) jz_reg(I2C_TAR(_n1)) | ||
| 428 | #define JA_I2C_TAR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x4) | ||
| 429 | #define JT_I2C_TAR(_n1) JIO_32_RW | ||
| 430 | #define JN_I2C_TAR(_n1) I2C_TAR | ||
| 431 | #define JI_I2C_TAR(_n1) (_n1) | ||
| 432 | #define BP_I2C_TAR_ADDR 0 | ||
| 433 | #define BM_I2C_TAR_ADDR 0x3ff | ||
| 434 | #define BF_I2C_TAR_ADDR(v) (((v) & 0x3ff) << 0) | ||
| 435 | #define BFM_I2C_TAR_ADDR(v) BM_I2C_TAR_ADDR | ||
| 436 | #define BF_I2C_TAR_ADDR_V(e) BF_I2C_TAR_ADDR(BV_I2C_TAR_ADDR__##e) | ||
| 437 | #define BFM_I2C_TAR_ADDR_V(v) BM_I2C_TAR_ADDR | ||
| 438 | #define BP_I2C_TAR_10BITS 12 | ||
| 439 | #define BM_I2C_TAR_10BITS 0x1000 | ||
| 440 | #define BF_I2C_TAR_10BITS(v) (((v) & 0x1) << 12) | ||
| 441 | #define BFM_I2C_TAR_10BITS(v) BM_I2C_TAR_10BITS | ||
| 442 | #define BF_I2C_TAR_10BITS_V(e) BF_I2C_TAR_10BITS(BV_I2C_TAR_10BITS__##e) | ||
| 443 | #define BFM_I2C_TAR_10BITS_V(v) BM_I2C_TAR_10BITS | ||
| 444 | #define BP_I2C_TAR_SPECIAL 11 | ||
| 445 | #define BM_I2C_TAR_SPECIAL 0x800 | ||
| 446 | #define BF_I2C_TAR_SPECIAL(v) (((v) & 0x1) << 11) | ||
| 447 | #define BFM_I2C_TAR_SPECIAL(v) BM_I2C_TAR_SPECIAL | ||
| 448 | #define BF_I2C_TAR_SPECIAL_V(e) BF_I2C_TAR_SPECIAL(BV_I2C_TAR_SPECIAL__##e) | ||
| 449 | #define BFM_I2C_TAR_SPECIAL_V(v) BM_I2C_TAR_SPECIAL | ||
| 450 | #define BP_I2C_TAR_GC_OR_START 10 | ||
| 451 | #define BM_I2C_TAR_GC_OR_START 0x400 | ||
| 452 | #define BF_I2C_TAR_GC_OR_START(v) (((v) & 0x1) << 10) | ||
| 453 | #define BFM_I2C_TAR_GC_OR_START(v) BM_I2C_TAR_GC_OR_START | ||
| 454 | #define BF_I2C_TAR_GC_OR_START_V(e) BF_I2C_TAR_GC_OR_START(BV_I2C_TAR_GC_OR_START__##e) | ||
| 455 | #define BFM_I2C_TAR_GC_OR_START_V(v) BM_I2C_TAR_GC_OR_START | ||
| 456 | |||
| 457 | #define REG_I2C_SAR(_n1) jz_reg(I2C_SAR(_n1)) | ||
| 458 | #define JA_I2C_SAR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x8) | ||
| 459 | #define JT_I2C_SAR(_n1) JIO_32_RW | ||
| 460 | #define JN_I2C_SAR(_n1) I2C_SAR | ||
| 461 | #define JI_I2C_SAR(_n1) (_n1) | ||
| 462 | |||
| 463 | #define REG_I2C_SHCNT(_n1) jz_reg(I2C_SHCNT(_n1)) | ||
| 464 | #define JA_I2C_SHCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x14) | ||
| 465 | #define JT_I2C_SHCNT(_n1) JIO_32_RW | ||
| 466 | #define JN_I2C_SHCNT(_n1) I2C_SHCNT | ||
| 467 | #define JI_I2C_SHCNT(_n1) (_n1) | ||
| 468 | |||
| 469 | #define REG_I2C_SLCNT(_n1) jz_reg(I2C_SLCNT(_n1)) | ||
| 470 | #define JA_I2C_SLCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x18) | ||
| 471 | #define JT_I2C_SLCNT(_n1) JIO_32_RW | ||
| 472 | #define JN_I2C_SLCNT(_n1) I2C_SLCNT | ||
| 473 | #define JI_I2C_SLCNT(_n1) (_n1) | ||
| 474 | |||
| 475 | #define REG_I2C_FHCNT(_n1) jz_reg(I2C_FHCNT(_n1)) | ||
| 476 | #define JA_I2C_FHCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x1c) | ||
| 477 | #define JT_I2C_FHCNT(_n1) JIO_32_RW | ||
| 478 | #define JN_I2C_FHCNT(_n1) I2C_FHCNT | ||
| 479 | #define JI_I2C_FHCNT(_n1) (_n1) | ||
| 480 | |||
| 481 | #define REG_I2C_FLCNT(_n1) jz_reg(I2C_FLCNT(_n1)) | ||
| 482 | #define JA_I2C_FLCNT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x20) | ||
| 483 | #define JT_I2C_FLCNT(_n1) JIO_32_RW | ||
| 484 | #define JN_I2C_FLCNT(_n1) I2C_FLCNT | ||
| 485 | #define JI_I2C_FLCNT(_n1) (_n1) | ||
| 486 | |||
| 487 | #define REG_I2C_RXTL(_n1) jz_reg(I2C_RXTL(_n1)) | ||
| 488 | #define JA_I2C_RXTL(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x38) | ||
| 489 | #define JT_I2C_RXTL(_n1) JIO_32_RW | ||
| 490 | #define JN_I2C_RXTL(_n1) I2C_RXTL | ||
| 491 | #define JI_I2C_RXTL(_n1) (_n1) | ||
| 492 | |||
| 493 | #define REG_I2C_TXTL(_n1) jz_reg(I2C_TXTL(_n1)) | ||
| 494 | #define JA_I2C_TXTL(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x3c) | ||
| 495 | #define JT_I2C_TXTL(_n1) JIO_32_RW | ||
| 496 | #define JN_I2C_TXTL(_n1) I2C_TXTL | ||
| 497 | #define JI_I2C_TXTL(_n1) (_n1) | ||
| 498 | |||
| 499 | #define REG_I2C_TXFLR(_n1) jz_reg(I2C_TXFLR(_n1)) | ||
| 500 | #define JA_I2C_TXFLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x74) | ||
| 501 | #define JT_I2C_TXFLR(_n1) JIO_32_RW | ||
| 502 | #define JN_I2C_TXFLR(_n1) I2C_TXFLR | ||
| 503 | #define JI_I2C_TXFLR(_n1) (_n1) | ||
| 504 | |||
| 505 | #define REG_I2C_RXFLR(_n1) jz_reg(I2C_RXFLR(_n1)) | ||
| 506 | #define JA_I2C_RXFLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x78) | ||
| 507 | #define JT_I2C_RXFLR(_n1) JIO_32_RW | ||
| 508 | #define JN_I2C_RXFLR(_n1) I2C_RXFLR | ||
| 509 | #define JI_I2C_RXFLR(_n1) (_n1) | ||
| 510 | |||
| 511 | #define REG_I2C_SDAHD(_n1) jz_reg(I2C_SDAHD(_n1)) | ||
| 512 | #define JA_I2C_SDAHD(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x7c) | ||
| 513 | #define JT_I2C_SDAHD(_n1) JIO_32_RW | ||
| 514 | #define JN_I2C_SDAHD(_n1) I2C_SDAHD | ||
| 515 | #define JI_I2C_SDAHD(_n1) (_n1) | ||
| 516 | |||
| 517 | #define REG_I2C_ABTSRC(_n1) jz_reg(I2C_ABTSRC(_n1)) | ||
| 518 | #define JA_I2C_ABTSRC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x80) | ||
| 519 | #define JT_I2C_ABTSRC(_n1) JIO_32_RW | ||
| 520 | #define JN_I2C_ABTSRC(_n1) I2C_ABTSRC | ||
| 521 | #define JI_I2C_ABTSRC(_n1) (_n1) | ||
| 522 | |||
| 523 | #define REG_I2C_DMACR(_n1) jz_reg(I2C_DMACR(_n1)) | ||
| 524 | #define JA_I2C_DMACR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x88) | ||
| 525 | #define JT_I2C_DMACR(_n1) JIO_32_RW | ||
| 526 | #define JN_I2C_DMACR(_n1) I2C_DMACR | ||
| 527 | #define JI_I2C_DMACR(_n1) (_n1) | ||
| 528 | |||
| 529 | #define REG_I2C_DMATDLR(_n1) jz_reg(I2C_DMATDLR(_n1)) | ||
| 530 | #define JA_I2C_DMATDLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x8c) | ||
| 531 | #define JT_I2C_DMATDLR(_n1) JIO_32_RW | ||
| 532 | #define JN_I2C_DMATDLR(_n1) I2C_DMATDLR | ||
| 533 | #define JI_I2C_DMATDLR(_n1) (_n1) | ||
| 534 | |||
| 535 | #define REG_I2C_DMARDLR(_n1) jz_reg(I2C_DMARDLR(_n1)) | ||
| 536 | #define JA_I2C_DMARDLR(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x90) | ||
| 537 | #define JT_I2C_DMARDLR(_n1) JIO_32_RW | ||
| 538 | #define JN_I2C_DMARDLR(_n1) I2C_DMARDLR | ||
| 539 | #define JI_I2C_DMARDLR(_n1) (_n1) | ||
| 540 | |||
| 541 | #define REG_I2C_SDASU(_n1) jz_reg(I2C_SDASU(_n1)) | ||
| 542 | #define JA_I2C_SDASU(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x94) | ||
| 543 | #define JT_I2C_SDASU(_n1) JIO_32_RW | ||
| 544 | #define JN_I2C_SDASU(_n1) I2C_SDASU | ||
| 545 | #define JI_I2C_SDASU(_n1) (_n1) | ||
| 546 | |||
| 547 | #define REG_I2C_ACKGC(_n1) jz_reg(I2C_ACKGC(_n1)) | ||
| 548 | #define JA_I2C_ACKGC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x98) | ||
| 549 | #define JT_I2C_ACKGC(_n1) JIO_32_RW | ||
| 550 | #define JN_I2C_ACKGC(_n1) I2C_ACKGC | ||
| 551 | #define JI_I2C_ACKGC(_n1) (_n1) | ||
| 552 | |||
| 553 | #define REG_I2C_FLT(_n1) jz_reg(I2C_FLT(_n1)) | ||
| 554 | #define JA_I2C_FLT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0xa0) | ||
| 555 | #define JT_I2C_FLT(_n1) JIO_32_RW | ||
| 556 | #define JN_I2C_FLT(_n1) I2C_FLT | ||
| 557 | #define JI_I2C_FLT(_n1) (_n1) | ||
| 558 | |||
| 559 | #define REG_I2C_CINT(_n1) jz_reg(I2C_CINT(_n1)) | ||
| 560 | #define JA_I2C_CINT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x40) | ||
| 561 | #define JT_I2C_CINT(_n1) JIO_32_RW | ||
| 562 | #define JN_I2C_CINT(_n1) I2C_CINT | ||
| 563 | #define JI_I2C_CINT(_n1) (_n1) | ||
| 564 | |||
| 565 | #define REG_I2C_CRXUF(_n1) jz_reg(I2C_CRXUF(_n1)) | ||
| 566 | #define JA_I2C_CRXUF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x44) | ||
| 567 | #define JT_I2C_CRXUF(_n1) JIO_32_RW | ||
| 568 | #define JN_I2C_CRXUF(_n1) I2C_CRXUF | ||
| 569 | #define JI_I2C_CRXUF(_n1) (_n1) | ||
| 570 | |||
| 571 | #define REG_I2C_CRXOF(_n1) jz_reg(I2C_CRXOF(_n1)) | ||
| 572 | #define JA_I2C_CRXOF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x48) | ||
| 573 | #define JT_I2C_CRXOF(_n1) JIO_32_RW | ||
| 574 | #define JN_I2C_CRXOF(_n1) I2C_CRXOF | ||
| 575 | #define JI_I2C_CRXOF(_n1) (_n1) | ||
| 576 | |||
| 577 | #define REG_I2C_CTXOF(_n1) jz_reg(I2C_CTXOF(_n1)) | ||
| 578 | #define JA_I2C_CTXOF(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x4c) | ||
| 579 | #define JT_I2C_CTXOF(_n1) JIO_32_RW | ||
| 580 | #define JN_I2C_CTXOF(_n1) I2C_CTXOF | ||
| 581 | #define JI_I2C_CTXOF(_n1) (_n1) | ||
| 582 | |||
| 583 | #define REG_I2C_CRXREQ(_n1) jz_reg(I2C_CRXREQ(_n1)) | ||
| 584 | #define JA_I2C_CRXREQ(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x50) | ||
| 585 | #define JT_I2C_CRXREQ(_n1) JIO_32_RW | ||
| 586 | #define JN_I2C_CRXREQ(_n1) I2C_CRXREQ | ||
| 587 | #define JI_I2C_CRXREQ(_n1) (_n1) | ||
| 588 | |||
| 589 | #define REG_I2C_CTXABT(_n1) jz_reg(I2C_CTXABT(_n1)) | ||
| 590 | #define JA_I2C_CTXABT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x54) | ||
| 591 | #define JT_I2C_CTXABT(_n1) JIO_32_RW | ||
| 592 | #define JN_I2C_CTXABT(_n1) I2C_CTXABT | ||
| 593 | #define JI_I2C_CTXABT(_n1) (_n1) | ||
| 594 | |||
| 595 | #define REG_I2C_CRXDN(_n1) jz_reg(I2C_CRXDN(_n1)) | ||
| 596 | #define JA_I2C_CRXDN(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x58) | ||
| 597 | #define JT_I2C_CRXDN(_n1) JIO_32_RW | ||
| 598 | #define JN_I2C_CRXDN(_n1) I2C_CRXDN | ||
| 599 | #define JI_I2C_CRXDN(_n1) (_n1) | ||
| 600 | |||
| 601 | #define REG_I2C_CACT(_n1) jz_reg(I2C_CACT(_n1)) | ||
| 602 | #define JA_I2C_CACT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x5c) | ||
| 603 | #define JT_I2C_CACT(_n1) JIO_32_RW | ||
| 604 | #define JN_I2C_CACT(_n1) I2C_CACT | ||
| 605 | #define JI_I2C_CACT(_n1) (_n1) | ||
| 606 | |||
| 607 | #define REG_I2C_CSTP(_n1) jz_reg(I2C_CSTP(_n1)) | ||
| 608 | #define JA_I2C_CSTP(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x60) | ||
| 609 | #define JT_I2C_CSTP(_n1) JIO_32_RW | ||
| 610 | #define JN_I2C_CSTP(_n1) I2C_CSTP | ||
| 611 | #define JI_I2C_CSTP(_n1) (_n1) | ||
| 612 | |||
| 613 | #define REG_I2C_CSTT(_n1) jz_reg(I2C_CSTT(_n1)) | ||
| 614 | #define JA_I2C_CSTT(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x64) | ||
| 615 | #define JT_I2C_CSTT(_n1) JIO_32_RW | ||
| 616 | #define JN_I2C_CSTT(_n1) I2C_CSTT | ||
| 617 | #define JI_I2C_CSTT(_n1) (_n1) | ||
| 618 | |||
| 619 | #define REG_I2C_CGC(_n1) jz_reg(I2C_CGC(_n1)) | ||
| 620 | #define JA_I2C_CGC(_n1) (0xb0050000 + (_n1) * 0x1000 + 0x68) | ||
| 621 | #define JT_I2C_CGC(_n1) JIO_32_RW | ||
| 622 | #define JN_I2C_CGC(_n1) I2C_CGC | ||
| 623 | #define JI_I2C_CGC(_n1) (_n1) | ||
| 624 | |||
| 625 | #endif /* __HEADERGEN_I2C_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/intc.h b/firmware/target/mips/ingenic_x1000/x1000/intc.h new file mode 100644 index 0000000000..37fbf33fb6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/intc.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_INTC_H__ | ||
| 25 | #define __HEADERGEN_INTC_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_INTC_SRC(_n1) jz_reg(INTC_SRC(_n1)) | ||
| 30 | #define JA_INTC_SRC(_n1) (0xb0001000 + 0x0 + (_n1) * 0x20) | ||
| 31 | #define JT_INTC_SRC(_n1) JIO_32_RW | ||
| 32 | #define JN_INTC_SRC(_n1) INTC_SRC | ||
| 33 | #define JI_INTC_SRC(_n1) (_n1) | ||
| 34 | |||
| 35 | #define REG_INTC_MSK(_n1) jz_reg(INTC_MSK(_n1)) | ||
| 36 | #define JA_INTC_MSK(_n1) (0xb0001000 + 0x4 + (_n1) * 0x20) | ||
| 37 | #define JT_INTC_MSK(_n1) JIO_32_RW | ||
| 38 | #define JN_INTC_MSK(_n1) INTC_MSK | ||
| 39 | #define JI_INTC_MSK(_n1) (_n1) | ||
| 40 | #define REG_INTC_MSK_SET(_n1) jz_reg(INTC_MSK_SET(_n1)) | ||
| 41 | #define JA_INTC_MSK_SET(_n1) (JA_INTC_MSK(_n1) + 0x4) | ||
| 42 | #define JT_INTC_MSK_SET(_n1) JIO_32_WO | ||
| 43 | #define JN_INTC_MSK_SET(_n1) INTC_MSK | ||
| 44 | #define JI_INTC_MSK_SET(_n1) (_n1) | ||
| 45 | #define REG_INTC_MSK_CLR(_n1) jz_reg(INTC_MSK_CLR(_n1)) | ||
| 46 | #define JA_INTC_MSK_CLR(_n1) (JA_INTC_MSK(_n1) + 0x8) | ||
| 47 | #define JT_INTC_MSK_CLR(_n1) JIO_32_WO | ||
| 48 | #define JN_INTC_MSK_CLR(_n1) INTC_MSK | ||
| 49 | #define JI_INTC_MSK_CLR(_n1) (_n1) | ||
| 50 | |||
| 51 | #define REG_INTC_PND(_n1) jz_reg(INTC_PND(_n1)) | ||
| 52 | #define JA_INTC_PND(_n1) (0xb0001000 + 0x10 + (_n1) * 0x20) | ||
| 53 | #define JT_INTC_PND(_n1) JIO_32_RW | ||
| 54 | #define JN_INTC_PND(_n1) INTC_PND | ||
| 55 | #define JI_INTC_PND(_n1) (_n1) | ||
| 56 | |||
| 57 | #endif /* __HEADERGEN_INTC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/lcd.h b/firmware/target/mips/ingenic_x1000/x1000/lcd.h new file mode 100644 index 0000000000..d4c1fe1878 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/lcd.h | |||
| @@ -0,0 +1,446 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_LCD_H__ | ||
| 25 | #define __HEADERGEN_LCD_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_LCD_CFG jz_reg(LCD_CFG) | ||
| 30 | #define JA_LCD_CFG (0xb3050000 + 0x0) | ||
| 31 | #define JT_LCD_CFG JIO_32_RW | ||
| 32 | #define JN_LCD_CFG LCD_CFG | ||
| 33 | #define JI_LCD_CFG | ||
| 34 | #define BP_LCD_CFG_INVDAT 17 | ||
| 35 | #define BM_LCD_CFG_INVDAT 0x20000 | ||
| 36 | #define BF_LCD_CFG_INVDAT(v) (((v) & 0x1) << 17) | ||
| 37 | #define BFM_LCD_CFG_INVDAT(v) BM_LCD_CFG_INVDAT | ||
| 38 | #define BF_LCD_CFG_INVDAT_V(e) BF_LCD_CFG_INVDAT(BV_LCD_CFG_INVDAT__##e) | ||
| 39 | #define BFM_LCD_CFG_INVDAT_V(v) BM_LCD_CFG_INVDAT | ||
| 40 | |||
| 41 | #define REG_LCD_CTRL jz_reg(LCD_CTRL) | ||
| 42 | #define JA_LCD_CTRL (0xb3050000 + 0x30) | ||
| 43 | #define JT_LCD_CTRL JIO_32_RW | ||
| 44 | #define JN_LCD_CTRL LCD_CTRL | ||
| 45 | #define JI_LCD_CTRL | ||
| 46 | #define BP_LCD_CTRL_BURST 28 | ||
| 47 | #define BM_LCD_CTRL_BURST 0x70000000 | ||
| 48 | #define BV_LCD_CTRL_BURST__4WORD 0x0 | ||
| 49 | #define BV_LCD_CTRL_BURST__8WORD 0x1 | ||
| 50 | #define BV_LCD_CTRL_BURST__16WORD 0x2 | ||
| 51 | #define BV_LCD_CTRL_BURST__32WORD 0x3 | ||
| 52 | #define BV_LCD_CTRL_BURST__64WORD 0x4 | ||
| 53 | #define BF_LCD_CTRL_BURST(v) (((v) & 0x7) << 28) | ||
| 54 | #define BFM_LCD_CTRL_BURST(v) BM_LCD_CTRL_BURST | ||
| 55 | #define BF_LCD_CTRL_BURST_V(e) BF_LCD_CTRL_BURST(BV_LCD_CTRL_BURST__##e) | ||
| 56 | #define BFM_LCD_CTRL_BURST_V(v) BM_LCD_CTRL_BURST | ||
| 57 | #define BP_LCD_CTRL_BPP 0 | ||
| 58 | #define BM_LCD_CTRL_BPP 0x7 | ||
| 59 | #define BV_LCD_CTRL_BPP__15BIT_OR_16BIT 0x4 | ||
| 60 | #define BV_LCD_CTRL_BPP__18BIT_OR_24BIT 0x5 | ||
| 61 | #define BV_LCD_CTRL_BPP__24BIT_COMPRESSED 0x6 | ||
| 62 | #define BV_LCD_CTRL_BPP__30BIT 0x7 | ||
| 63 | #define BF_LCD_CTRL_BPP(v) (((v) & 0x7) << 0) | ||
| 64 | #define BFM_LCD_CTRL_BPP(v) BM_LCD_CTRL_BPP | ||
| 65 | #define BF_LCD_CTRL_BPP_V(e) BF_LCD_CTRL_BPP(BV_LCD_CTRL_BPP__##e) | ||
| 66 | #define BFM_LCD_CTRL_BPP_V(v) BM_LCD_CTRL_BPP | ||
| 67 | #define BP_LCD_CTRL_EOFM 13 | ||
| 68 | #define BM_LCD_CTRL_EOFM 0x2000 | ||
| 69 | #define BF_LCD_CTRL_EOFM(v) (((v) & 0x1) << 13) | ||
| 70 | #define BFM_LCD_CTRL_EOFM(v) BM_LCD_CTRL_EOFM | ||
| 71 | #define BF_LCD_CTRL_EOFM_V(e) BF_LCD_CTRL_EOFM(BV_LCD_CTRL_EOFM__##e) | ||
| 72 | #define BFM_LCD_CTRL_EOFM_V(v) BM_LCD_CTRL_EOFM | ||
| 73 | #define BP_LCD_CTRL_SOFM 12 | ||
| 74 | #define BM_LCD_CTRL_SOFM 0x1000 | ||
| 75 | #define BF_LCD_CTRL_SOFM(v) (((v) & 0x1) << 12) | ||
| 76 | #define BFM_LCD_CTRL_SOFM(v) BM_LCD_CTRL_SOFM | ||
| 77 | #define BF_LCD_CTRL_SOFM_V(e) BF_LCD_CTRL_SOFM(BV_LCD_CTRL_SOFM__##e) | ||
| 78 | #define BFM_LCD_CTRL_SOFM_V(v) BM_LCD_CTRL_SOFM | ||
| 79 | #define BP_LCD_CTRL_IFUM 10 | ||
| 80 | #define BM_LCD_CTRL_IFUM 0x400 | ||
| 81 | #define BF_LCD_CTRL_IFUM(v) (((v) & 0x1) << 10) | ||
| 82 | #define BFM_LCD_CTRL_IFUM(v) BM_LCD_CTRL_IFUM | ||
| 83 | #define BF_LCD_CTRL_IFUM_V(e) BF_LCD_CTRL_IFUM(BV_LCD_CTRL_IFUM__##e) | ||
| 84 | #define BFM_LCD_CTRL_IFUM_V(v) BM_LCD_CTRL_IFUM | ||
| 85 | #define BP_LCD_CTRL_QDM 7 | ||
| 86 | #define BM_LCD_CTRL_QDM 0x80 | ||
| 87 | #define BF_LCD_CTRL_QDM(v) (((v) & 0x1) << 7) | ||
| 88 | #define BFM_LCD_CTRL_QDM(v) BM_LCD_CTRL_QDM | ||
| 89 | #define BF_LCD_CTRL_QDM_V(e) BF_LCD_CTRL_QDM(BV_LCD_CTRL_QDM__##e) | ||
| 90 | #define BFM_LCD_CTRL_QDM_V(v) BM_LCD_CTRL_QDM | ||
| 91 | #define BP_LCD_CTRL_BEDN 6 | ||
| 92 | #define BM_LCD_CTRL_BEDN 0x40 | ||
| 93 | #define BF_LCD_CTRL_BEDN(v) (((v) & 0x1) << 6) | ||
| 94 | #define BFM_LCD_CTRL_BEDN(v) BM_LCD_CTRL_BEDN | ||
| 95 | #define BF_LCD_CTRL_BEDN_V(e) BF_LCD_CTRL_BEDN(BV_LCD_CTRL_BEDN__##e) | ||
| 96 | #define BFM_LCD_CTRL_BEDN_V(v) BM_LCD_CTRL_BEDN | ||
| 97 | #define BP_LCD_CTRL_PEDN 5 | ||
| 98 | #define BM_LCD_CTRL_PEDN 0x20 | ||
| 99 | #define BF_LCD_CTRL_PEDN(v) (((v) & 0x1) << 5) | ||
| 100 | #define BFM_LCD_CTRL_PEDN(v) BM_LCD_CTRL_PEDN | ||
| 101 | #define BF_LCD_CTRL_PEDN_V(e) BF_LCD_CTRL_PEDN(BV_LCD_CTRL_PEDN__##e) | ||
| 102 | #define BFM_LCD_CTRL_PEDN_V(v) BM_LCD_CTRL_PEDN | ||
| 103 | #define BP_LCD_CTRL_ENABLE 3 | ||
| 104 | #define BM_LCD_CTRL_ENABLE 0x8 | ||
| 105 | #define BF_LCD_CTRL_ENABLE(v) (((v) & 0x1) << 3) | ||
| 106 | #define BFM_LCD_CTRL_ENABLE(v) BM_LCD_CTRL_ENABLE | ||
| 107 | #define BF_LCD_CTRL_ENABLE_V(e) BF_LCD_CTRL_ENABLE(BV_LCD_CTRL_ENABLE__##e) | ||
| 108 | #define BFM_LCD_CTRL_ENABLE_V(v) BM_LCD_CTRL_ENABLE | ||
| 109 | |||
| 110 | #define REG_LCD_STATE jz_reg(LCD_STATE) | ||
| 111 | #define JA_LCD_STATE (0xb3050000 + 0x34) | ||
| 112 | #define JT_LCD_STATE JIO_32_RW | ||
| 113 | #define JN_LCD_STATE LCD_STATE | ||
| 114 | #define JI_LCD_STATE | ||
| 115 | #define BP_LCD_STATE_QD 7 | ||
| 116 | #define BM_LCD_STATE_QD 0x80 | ||
| 117 | #define BF_LCD_STATE_QD(v) (((v) & 0x1) << 7) | ||
| 118 | #define BFM_LCD_STATE_QD(v) BM_LCD_STATE_QD | ||
| 119 | #define BF_LCD_STATE_QD_V(e) BF_LCD_STATE_QD(BV_LCD_STATE_QD__##e) | ||
| 120 | #define BFM_LCD_STATE_QD_V(v) BM_LCD_STATE_QD | ||
| 121 | #define BP_LCD_STATE_EOF 5 | ||
| 122 | #define BM_LCD_STATE_EOF 0x20 | ||
| 123 | #define BF_LCD_STATE_EOF(v) (((v) & 0x1) << 5) | ||
| 124 | #define BFM_LCD_STATE_EOF(v) BM_LCD_STATE_EOF | ||
| 125 | #define BF_LCD_STATE_EOF_V(e) BF_LCD_STATE_EOF(BV_LCD_STATE_EOF__##e) | ||
| 126 | #define BFM_LCD_STATE_EOF_V(v) BM_LCD_STATE_EOF | ||
| 127 | #define BP_LCD_STATE_SOF 4 | ||
| 128 | #define BM_LCD_STATE_SOF 0x10 | ||
| 129 | #define BF_LCD_STATE_SOF(v) (((v) & 0x1) << 4) | ||
| 130 | #define BFM_LCD_STATE_SOF(v) BM_LCD_STATE_SOF | ||
| 131 | #define BF_LCD_STATE_SOF_V(e) BF_LCD_STATE_SOF(BV_LCD_STATE_SOF__##e) | ||
| 132 | #define BFM_LCD_STATE_SOF_V(v) BM_LCD_STATE_SOF | ||
| 133 | #define BP_LCD_STATE_IFU 2 | ||
| 134 | #define BM_LCD_STATE_IFU 0x4 | ||
| 135 | #define BF_LCD_STATE_IFU(v) (((v) & 0x1) << 2) | ||
| 136 | #define BFM_LCD_STATE_IFU(v) BM_LCD_STATE_IFU | ||
| 137 | #define BF_LCD_STATE_IFU_V(e) BF_LCD_STATE_IFU(BV_LCD_STATE_IFU__##e) | ||
| 138 | #define BFM_LCD_STATE_IFU_V(v) BM_LCD_STATE_IFU | ||
| 139 | |||
| 140 | #define REG_LCD_OSDCTRL jz_reg(LCD_OSDCTRL) | ||
| 141 | #define JA_LCD_OSDCTRL (0xb3050000 + 0x104) | ||
| 142 | #define JT_LCD_OSDCTRL JIO_32_RW | ||
| 143 | #define JN_LCD_OSDCTRL LCD_OSDCTRL | ||
| 144 | #define JI_LCD_OSDCTRL | ||
| 145 | |||
| 146 | #define REG_LCD_BGC jz_reg(LCD_BGC) | ||
| 147 | #define JA_LCD_BGC (0xb3050000 + 0x10c) | ||
| 148 | #define JT_LCD_BGC JIO_32_RW | ||
| 149 | #define JN_LCD_BGC LCD_BGC | ||
| 150 | #define JI_LCD_BGC | ||
| 151 | |||
| 152 | #define REG_LCD_DAH jz_reg(LCD_DAH) | ||
| 153 | #define JA_LCD_DAH (0xb3050000 + 0x10) | ||
| 154 | #define JT_LCD_DAH JIO_32_RW | ||
| 155 | #define JN_LCD_DAH LCD_DAH | ||
| 156 | #define JI_LCD_DAH | ||
| 157 | |||
| 158 | #define REG_LCD_DAV jz_reg(LCD_DAV) | ||
| 159 | #define JA_LCD_DAV (0xb3050000 + 0x14) | ||
| 160 | #define JT_LCD_DAV JIO_32_RW | ||
| 161 | #define JN_LCD_DAV LCD_DAV | ||
| 162 | #define JI_LCD_DAV | ||
| 163 | |||
| 164 | #define REG_LCD_VAT jz_reg(LCD_VAT) | ||
| 165 | #define JA_LCD_VAT (0xb3050000 + 0xc) | ||
| 166 | #define JT_LCD_VAT JIO_32_RW | ||
| 167 | #define JN_LCD_VAT LCD_VAT | ||
| 168 | #define JI_LCD_VAT | ||
| 169 | |||
| 170 | #define REG_LCD_VSYNC jz_reg(LCD_VSYNC) | ||
| 171 | #define JA_LCD_VSYNC (0xb3050000 + 0x4) | ||
| 172 | #define JT_LCD_VSYNC JIO_32_RW | ||
| 173 | #define JN_LCD_VSYNC LCD_VSYNC | ||
| 174 | #define JI_LCD_VSYNC | ||
| 175 | |||
| 176 | #define REG_LCD_HSYNC jz_reg(LCD_HSYNC) | ||
| 177 | #define JA_LCD_HSYNC (0xb3050000 + 0x8) | ||
| 178 | #define JT_LCD_HSYNC JIO_32_RW | ||
| 179 | #define JN_LCD_HSYNC LCD_HSYNC | ||
| 180 | #define JI_LCD_HSYNC | ||
| 181 | |||
| 182 | #define REG_LCD_IID jz_reg(LCD_IID) | ||
| 183 | #define JA_LCD_IID (0xb3050000 + 0x38) | ||
| 184 | #define JT_LCD_IID JIO_32_RW | ||
| 185 | #define JN_LCD_IID LCD_IID | ||
| 186 | #define JI_LCD_IID | ||
| 187 | |||
| 188 | #define REG_LCD_DA jz_reg(LCD_DA) | ||
| 189 | #define JA_LCD_DA (0xb3050000 + 0x40) | ||
| 190 | #define JT_LCD_DA JIO_32_RW | ||
| 191 | #define JN_LCD_DA LCD_DA | ||
| 192 | #define JI_LCD_DA | ||
| 193 | |||
| 194 | #define REG_LCD_MCFG jz_reg(LCD_MCFG) | ||
| 195 | #define JA_LCD_MCFG (0xb3050000 + 0xa0) | ||
| 196 | #define JT_LCD_MCFG JIO_32_RW | ||
| 197 | #define JN_LCD_MCFG LCD_MCFG | ||
| 198 | #define JI_LCD_MCFG | ||
| 199 | #define BP_LCD_MCFG_CWIDTH 8 | ||
| 200 | #define BM_LCD_MCFG_CWIDTH 0x300 | ||
| 201 | #define BV_LCD_MCFG_CWIDTH__16BIT_OR_9BIT 0x0 | ||
| 202 | #define BV_LCD_MCFG_CWIDTH__8BIT 0x1 | ||
| 203 | #define BV_LCD_MCFG_CWIDTH__18BIT 0x2 | ||
| 204 | #define BV_LCD_MCFG_CWIDTH__24BIT 0x3 | ||
| 205 | #define BF_LCD_MCFG_CWIDTH(v) (((v) & 0x3) << 8) | ||
| 206 | #define BFM_LCD_MCFG_CWIDTH(v) BM_LCD_MCFG_CWIDTH | ||
| 207 | #define BF_LCD_MCFG_CWIDTH_V(e) BF_LCD_MCFG_CWIDTH(BV_LCD_MCFG_CWIDTH__##e) | ||
| 208 | #define BFM_LCD_MCFG_CWIDTH_V(v) BM_LCD_MCFG_CWIDTH | ||
| 209 | |||
| 210 | #define REG_LCD_MCFG_NEW jz_reg(LCD_MCFG_NEW) | ||
| 211 | #define JA_LCD_MCFG_NEW (0xb3050000 + 0xb8) | ||
| 212 | #define JT_LCD_MCFG_NEW JIO_32_RW | ||
| 213 | #define JN_LCD_MCFG_NEW LCD_MCFG_NEW | ||
| 214 | #define JI_LCD_MCFG_NEW | ||
| 215 | #define BP_LCD_MCFG_NEW_DWIDTH 13 | ||
| 216 | #define BM_LCD_MCFG_NEW_DWIDTH 0xe000 | ||
| 217 | #define BV_LCD_MCFG_NEW_DWIDTH__8BIT 0x0 | ||
| 218 | #define BV_LCD_MCFG_NEW_DWIDTH__9BIT 0x1 | ||
| 219 | #define BV_LCD_MCFG_NEW_DWIDTH__16BIT 0x2 | ||
| 220 | #define BV_LCD_MCFG_NEW_DWIDTH__18BIT 0x3 | ||
| 221 | #define BV_LCD_MCFG_NEW_DWIDTH__24BIT 0x4 | ||
| 222 | #define BF_LCD_MCFG_NEW_DWIDTH(v) (((v) & 0x7) << 13) | ||
| 223 | #define BFM_LCD_MCFG_NEW_DWIDTH(v) BM_LCD_MCFG_NEW_DWIDTH | ||
| 224 | #define BF_LCD_MCFG_NEW_DWIDTH_V(e) BF_LCD_MCFG_NEW_DWIDTH(BV_LCD_MCFG_NEW_DWIDTH__##e) | ||
| 225 | #define BFM_LCD_MCFG_NEW_DWIDTH_V(v) BM_LCD_MCFG_NEW_DWIDTH | ||
| 226 | #define BP_LCD_MCFG_NEW_DTIMES 8 | ||
| 227 | #define BM_LCD_MCFG_NEW_DTIMES 0x300 | ||
| 228 | #define BV_LCD_MCFG_NEW_DTIMES__1TIME 0x0 | ||
| 229 | #define BV_LCD_MCFG_NEW_DTIMES__2TIME 0x1 | ||
| 230 | #define BV_LCD_MCFG_NEW_DTIMES__3TIME 0x2 | ||
| 231 | #define BF_LCD_MCFG_NEW_DTIMES(v) (((v) & 0x3) << 8) | ||
| 232 | #define BFM_LCD_MCFG_NEW_DTIMES(v) BM_LCD_MCFG_NEW_DTIMES | ||
| 233 | #define BF_LCD_MCFG_NEW_DTIMES_V(e) BF_LCD_MCFG_NEW_DTIMES(BV_LCD_MCFG_NEW_DTIMES__##e) | ||
| 234 | #define BFM_LCD_MCFG_NEW_DTIMES_V(v) BM_LCD_MCFG_NEW_DTIMES | ||
| 235 | #define BP_LCD_MCFG_NEW_6800_MODE 11 | ||
| 236 | #define BM_LCD_MCFG_NEW_6800_MODE 0x800 | ||
| 237 | #define BF_LCD_MCFG_NEW_6800_MODE(v) (((v) & 0x1) << 11) | ||
| 238 | #define BFM_LCD_MCFG_NEW_6800_MODE(v) BM_LCD_MCFG_NEW_6800_MODE | ||
| 239 | #define BF_LCD_MCFG_NEW_6800_MODE_V(e) BF_LCD_MCFG_NEW_6800_MODE(BV_LCD_MCFG_NEW_6800_MODE__##e) | ||
| 240 | #define BFM_LCD_MCFG_NEW_6800_MODE_V(v) BM_LCD_MCFG_NEW_6800_MODE | ||
| 241 | #define BP_LCD_MCFG_NEW_CMD_9BIT 10 | ||
| 242 | #define BM_LCD_MCFG_NEW_CMD_9BIT 0x400 | ||
| 243 | #define BF_LCD_MCFG_NEW_CMD_9BIT(v) (((v) & 0x1) << 10) | ||
| 244 | #define BFM_LCD_MCFG_NEW_CMD_9BIT(v) BM_LCD_MCFG_NEW_CMD_9BIT | ||
| 245 | #define BF_LCD_MCFG_NEW_CMD_9BIT_V(e) BF_LCD_MCFG_NEW_CMD_9BIT(BV_LCD_MCFG_NEW_CMD_9BIT__##e) | ||
| 246 | #define BFM_LCD_MCFG_NEW_CMD_9BIT_V(v) BM_LCD_MCFG_NEW_CMD_9BIT | ||
| 247 | #define BP_LCD_MCFG_NEW_CSPLY 5 | ||
| 248 | #define BM_LCD_MCFG_NEW_CSPLY 0x20 | ||
| 249 | #define BF_LCD_MCFG_NEW_CSPLY(v) (((v) & 0x1) << 5) | ||
| 250 | #define BFM_LCD_MCFG_NEW_CSPLY(v) BM_LCD_MCFG_NEW_CSPLY | ||
| 251 | #define BF_LCD_MCFG_NEW_CSPLY_V(e) BF_LCD_MCFG_NEW_CSPLY(BV_LCD_MCFG_NEW_CSPLY__##e) | ||
| 252 | #define BFM_LCD_MCFG_NEW_CSPLY_V(v) BM_LCD_MCFG_NEW_CSPLY | ||
| 253 | #define BP_LCD_MCFG_NEW_RSPLY 4 | ||
| 254 | #define BM_LCD_MCFG_NEW_RSPLY 0x10 | ||
| 255 | #define BF_LCD_MCFG_NEW_RSPLY(v) (((v) & 0x1) << 4) | ||
| 256 | #define BFM_LCD_MCFG_NEW_RSPLY(v) BM_LCD_MCFG_NEW_RSPLY | ||
| 257 | #define BF_LCD_MCFG_NEW_RSPLY_V(e) BF_LCD_MCFG_NEW_RSPLY(BV_LCD_MCFG_NEW_RSPLY__##e) | ||
| 258 | #define BFM_LCD_MCFG_NEW_RSPLY_V(v) BM_LCD_MCFG_NEW_RSPLY | ||
| 259 | #define BP_LCD_MCFG_NEW_CLKPLY 3 | ||
| 260 | #define BM_LCD_MCFG_NEW_CLKPLY 0x8 | ||
| 261 | #define BF_LCD_MCFG_NEW_CLKPLY(v) (((v) & 0x1) << 3) | ||
| 262 | #define BFM_LCD_MCFG_NEW_CLKPLY(v) BM_LCD_MCFG_NEW_CLKPLY | ||
| 263 | #define BF_LCD_MCFG_NEW_CLKPLY_V(e) BF_LCD_MCFG_NEW_CLKPLY(BV_LCD_MCFG_NEW_CLKPLY__##e) | ||
| 264 | #define BFM_LCD_MCFG_NEW_CLKPLY_V(v) BM_LCD_MCFG_NEW_CLKPLY | ||
| 265 | #define BP_LCD_MCFG_NEW_DTYPE 2 | ||
| 266 | #define BM_LCD_MCFG_NEW_DTYPE 0x4 | ||
| 267 | #define BV_LCD_MCFG_NEW_DTYPE__SERIAL 0x1 | ||
| 268 | #define BV_LCD_MCFG_NEW_DTYPE__PARALLEL 0x0 | ||
| 269 | #define BF_LCD_MCFG_NEW_DTYPE(v) (((v) & 0x1) << 2) | ||
| 270 | #define BFM_LCD_MCFG_NEW_DTYPE(v) BM_LCD_MCFG_NEW_DTYPE | ||
| 271 | #define BF_LCD_MCFG_NEW_DTYPE_V(e) BF_LCD_MCFG_NEW_DTYPE(BV_LCD_MCFG_NEW_DTYPE__##e) | ||
| 272 | #define BFM_LCD_MCFG_NEW_DTYPE_V(v) BM_LCD_MCFG_NEW_DTYPE | ||
| 273 | #define BP_LCD_MCFG_NEW_CTYPE 1 | ||
| 274 | #define BM_LCD_MCFG_NEW_CTYPE 0x2 | ||
| 275 | #define BV_LCD_MCFG_NEW_CTYPE__SERIAL 0x1 | ||
| 276 | #define BV_LCD_MCFG_NEW_CTYPE__PARALLEL 0x0 | ||
| 277 | #define BF_LCD_MCFG_NEW_CTYPE(v) (((v) & 0x1) << 1) | ||
| 278 | #define BFM_LCD_MCFG_NEW_CTYPE(v) BM_LCD_MCFG_NEW_CTYPE | ||
| 279 | #define BF_LCD_MCFG_NEW_CTYPE_V(e) BF_LCD_MCFG_NEW_CTYPE(BV_LCD_MCFG_NEW_CTYPE__##e) | ||
| 280 | #define BFM_LCD_MCFG_NEW_CTYPE_V(v) BM_LCD_MCFG_NEW_CTYPE | ||
| 281 | #define BP_LCD_MCFG_NEW_FMT_CONV 0 | ||
| 282 | #define BM_LCD_MCFG_NEW_FMT_CONV 0x1 | ||
| 283 | #define BF_LCD_MCFG_NEW_FMT_CONV(v) (((v) & 0x1) << 0) | ||
| 284 | #define BFM_LCD_MCFG_NEW_FMT_CONV(v) BM_LCD_MCFG_NEW_FMT_CONV | ||
| 285 | #define BF_LCD_MCFG_NEW_FMT_CONV_V(e) BF_LCD_MCFG_NEW_FMT_CONV(BV_LCD_MCFG_NEW_FMT_CONV__##e) | ||
| 286 | #define BFM_LCD_MCFG_NEW_FMT_CONV_V(v) BM_LCD_MCFG_NEW_FMT_CONV | ||
| 287 | |||
| 288 | #define REG_LCD_MCTRL jz_reg(LCD_MCTRL) | ||
| 289 | #define JA_LCD_MCTRL (0xb3050000 + 0xa4) | ||
| 290 | #define JT_LCD_MCTRL JIO_32_RW | ||
| 291 | #define JN_LCD_MCTRL LCD_MCTRL | ||
| 292 | #define JI_LCD_MCTRL | ||
| 293 | #define BP_LCD_MCTRL_NARROW_TE 10 | ||
| 294 | #define BM_LCD_MCTRL_NARROW_TE 0x400 | ||
| 295 | #define BF_LCD_MCTRL_NARROW_TE(v) (((v) & 0x1) << 10) | ||
| 296 | #define BFM_LCD_MCTRL_NARROW_TE(v) BM_LCD_MCTRL_NARROW_TE | ||
| 297 | #define BF_LCD_MCTRL_NARROW_TE_V(e) BF_LCD_MCTRL_NARROW_TE(BV_LCD_MCTRL_NARROW_TE__##e) | ||
| 298 | #define BFM_LCD_MCTRL_NARROW_TE_V(v) BM_LCD_MCTRL_NARROW_TE | ||
| 299 | #define BP_LCD_MCTRL_TE_INV 9 | ||
| 300 | #define BM_LCD_MCTRL_TE_INV 0x200 | ||
| 301 | #define BF_LCD_MCTRL_TE_INV(v) (((v) & 0x1) << 9) | ||
| 302 | #define BFM_LCD_MCTRL_TE_INV(v) BM_LCD_MCTRL_TE_INV | ||
| 303 | #define BF_LCD_MCTRL_TE_INV_V(e) BF_LCD_MCTRL_TE_INV(BV_LCD_MCTRL_TE_INV__##e) | ||
| 304 | #define BFM_LCD_MCTRL_TE_INV_V(v) BM_LCD_MCTRL_TE_INV | ||
| 305 | #define BP_LCD_MCTRL_NOT_USE_TE 8 | ||
| 306 | #define BM_LCD_MCTRL_NOT_USE_TE 0x100 | ||
| 307 | #define BF_LCD_MCTRL_NOT_USE_TE(v) (((v) & 0x1) << 8) | ||
| 308 | #define BFM_LCD_MCTRL_NOT_USE_TE(v) BM_LCD_MCTRL_NOT_USE_TE | ||
| 309 | #define BF_LCD_MCTRL_NOT_USE_TE_V(e) BF_LCD_MCTRL_NOT_USE_TE(BV_LCD_MCTRL_NOT_USE_TE__##e) | ||
| 310 | #define BFM_LCD_MCTRL_NOT_USE_TE_V(v) BM_LCD_MCTRL_NOT_USE_TE | ||
| 311 | #define BP_LCD_MCTRL_DCSI_SEL 7 | ||
| 312 | #define BM_LCD_MCTRL_DCSI_SEL 0x80 | ||
| 313 | #define BF_LCD_MCTRL_DCSI_SEL(v) (((v) & 0x1) << 7) | ||
| 314 | #define BFM_LCD_MCTRL_DCSI_SEL(v) BM_LCD_MCTRL_DCSI_SEL | ||
| 315 | #define BF_LCD_MCTRL_DCSI_SEL_V(e) BF_LCD_MCTRL_DCSI_SEL(BV_LCD_MCTRL_DCSI_SEL__##e) | ||
| 316 | #define BFM_LCD_MCTRL_DCSI_SEL_V(v) BM_LCD_MCTRL_DCSI_SEL | ||
| 317 | #define BP_LCD_MCTRL_MIPI_SLCD 6 | ||
| 318 | #define BM_LCD_MCTRL_MIPI_SLCD 0x40 | ||
| 319 | #define BF_LCD_MCTRL_MIPI_SLCD(v) (((v) & 0x1) << 6) | ||
| 320 | #define BFM_LCD_MCTRL_MIPI_SLCD(v) BM_LCD_MCTRL_MIPI_SLCD | ||
| 321 | #define BF_LCD_MCTRL_MIPI_SLCD_V(e) BF_LCD_MCTRL_MIPI_SLCD(BV_LCD_MCTRL_MIPI_SLCD__##e) | ||
| 322 | #define BFM_LCD_MCTRL_MIPI_SLCD_V(v) BM_LCD_MCTRL_MIPI_SLCD | ||
| 323 | #define BP_LCD_MCTRL_FAST_MODE 4 | ||
| 324 | #define BM_LCD_MCTRL_FAST_MODE 0x10 | ||
| 325 | #define BF_LCD_MCTRL_FAST_MODE(v) (((v) & 0x1) << 4) | ||
| 326 | #define BFM_LCD_MCTRL_FAST_MODE(v) BM_LCD_MCTRL_FAST_MODE | ||
| 327 | #define BF_LCD_MCTRL_FAST_MODE_V(e) BF_LCD_MCTRL_FAST_MODE(BV_LCD_MCTRL_FAST_MODE__##e) | ||
| 328 | #define BFM_LCD_MCTRL_FAST_MODE_V(v) BM_LCD_MCTRL_FAST_MODE | ||
| 329 | #define BP_LCD_MCTRL_GATE_MASK 3 | ||
| 330 | #define BM_LCD_MCTRL_GATE_MASK 0x8 | ||
| 331 | #define BF_LCD_MCTRL_GATE_MASK(v) (((v) & 0x1) << 3) | ||
| 332 | #define BFM_LCD_MCTRL_GATE_MASK(v) BM_LCD_MCTRL_GATE_MASK | ||
| 333 | #define BF_LCD_MCTRL_GATE_MASK_V(e) BF_LCD_MCTRL_GATE_MASK(BV_LCD_MCTRL_GATE_MASK__##e) | ||
| 334 | #define BFM_LCD_MCTRL_GATE_MASK_V(v) BM_LCD_MCTRL_GATE_MASK | ||
| 335 | #define BP_LCD_MCTRL_DMA_MODE 2 | ||
| 336 | #define BM_LCD_MCTRL_DMA_MODE 0x4 | ||
| 337 | #define BF_LCD_MCTRL_DMA_MODE(v) (((v) & 0x1) << 2) | ||
| 338 | #define BFM_LCD_MCTRL_DMA_MODE(v) BM_LCD_MCTRL_DMA_MODE | ||
| 339 | #define BF_LCD_MCTRL_DMA_MODE_V(e) BF_LCD_MCTRL_DMA_MODE(BV_LCD_MCTRL_DMA_MODE__##e) | ||
| 340 | #define BFM_LCD_MCTRL_DMA_MODE_V(v) BM_LCD_MCTRL_DMA_MODE | ||
| 341 | #define BP_LCD_MCTRL_DMA_START 1 | ||
| 342 | #define BM_LCD_MCTRL_DMA_START 0x2 | ||
| 343 | #define BF_LCD_MCTRL_DMA_START(v) (((v) & 0x1) << 1) | ||
| 344 | #define BFM_LCD_MCTRL_DMA_START(v) BM_LCD_MCTRL_DMA_START | ||
| 345 | #define BF_LCD_MCTRL_DMA_START_V(e) BF_LCD_MCTRL_DMA_START(BV_LCD_MCTRL_DMA_START__##e) | ||
| 346 | #define BFM_LCD_MCTRL_DMA_START_V(v) BM_LCD_MCTRL_DMA_START | ||
| 347 | #define BP_LCD_MCTRL_DMA_TX_EN 0 | ||
| 348 | #define BM_LCD_MCTRL_DMA_TX_EN 0x1 | ||
| 349 | #define BF_LCD_MCTRL_DMA_TX_EN(v) (((v) & 0x1) << 0) | ||
| 350 | #define BFM_LCD_MCTRL_DMA_TX_EN(v) BM_LCD_MCTRL_DMA_TX_EN | ||
| 351 | #define BF_LCD_MCTRL_DMA_TX_EN_V(e) BF_LCD_MCTRL_DMA_TX_EN(BV_LCD_MCTRL_DMA_TX_EN__##e) | ||
| 352 | #define BFM_LCD_MCTRL_DMA_TX_EN_V(v) BM_LCD_MCTRL_DMA_TX_EN | ||
| 353 | |||
| 354 | #define REG_LCD_MSTATE jz_reg(LCD_MSTATE) | ||
| 355 | #define JA_LCD_MSTATE (0xb3050000 + 0xa8) | ||
| 356 | #define JT_LCD_MSTATE JIO_32_RW | ||
| 357 | #define JN_LCD_MSTATE LCD_MSTATE | ||
| 358 | #define JI_LCD_MSTATE | ||
| 359 | #define BP_LCD_MSTATE_LCD_ID 16 | ||
| 360 | #define BM_LCD_MSTATE_LCD_ID 0xffff0000 | ||
| 361 | #define BF_LCD_MSTATE_LCD_ID(v) (((v) & 0xffff) << 16) | ||
| 362 | #define BFM_LCD_MSTATE_LCD_ID(v) BM_LCD_MSTATE_LCD_ID | ||
| 363 | #define BF_LCD_MSTATE_LCD_ID_V(e) BF_LCD_MSTATE_LCD_ID(BV_LCD_MSTATE_LCD_ID__##e) | ||
| 364 | #define BFM_LCD_MSTATE_LCD_ID_V(v) BM_LCD_MSTATE_LCD_ID | ||
| 365 | #define BP_LCD_MSTATE_BUSY 0 | ||
| 366 | #define BM_LCD_MSTATE_BUSY 0x1 | ||
| 367 | #define BF_LCD_MSTATE_BUSY(v) (((v) & 0x1) << 0) | ||
| 368 | #define BFM_LCD_MSTATE_BUSY(v) BM_LCD_MSTATE_BUSY | ||
| 369 | #define BF_LCD_MSTATE_BUSY_V(e) BF_LCD_MSTATE_BUSY(BV_LCD_MSTATE_BUSY__##e) | ||
| 370 | #define BFM_LCD_MSTATE_BUSY_V(v) BM_LCD_MSTATE_BUSY | ||
| 371 | |||
| 372 | #define REG_LCD_MDATA jz_reg(LCD_MDATA) | ||
| 373 | #define JA_LCD_MDATA (0xb3050000 + 0xac) | ||
| 374 | #define JT_LCD_MDATA JIO_32_RW | ||
| 375 | #define JN_LCD_MDATA LCD_MDATA | ||
| 376 | #define JI_LCD_MDATA | ||
| 377 | #define BP_LCD_MDATA_TYPE 30 | ||
| 378 | #define BM_LCD_MDATA_TYPE 0xc0000000 | ||
| 379 | #define BV_LCD_MDATA_TYPE__CMD 0x1 | ||
| 380 | #define BV_LCD_MDATA_TYPE__DAT 0x0 | ||
| 381 | #define BF_LCD_MDATA_TYPE(v) (((v) & 0x3) << 30) | ||
| 382 | #define BFM_LCD_MDATA_TYPE(v) BM_LCD_MDATA_TYPE | ||
| 383 | #define BF_LCD_MDATA_TYPE_V(e) BF_LCD_MDATA_TYPE(BV_LCD_MDATA_TYPE__##e) | ||
| 384 | #define BFM_LCD_MDATA_TYPE_V(v) BM_LCD_MDATA_TYPE | ||
| 385 | #define BP_LCD_MDATA_DATA 0 | ||
| 386 | #define BM_LCD_MDATA_DATA 0xffffff | ||
| 387 | #define BF_LCD_MDATA_DATA(v) (((v) & 0xffffff) << 0) | ||
| 388 | #define BFM_LCD_MDATA_DATA(v) BM_LCD_MDATA_DATA | ||
| 389 | #define BF_LCD_MDATA_DATA_V(e) BF_LCD_MDATA_DATA(BV_LCD_MDATA_DATA__##e) | ||
| 390 | #define BFM_LCD_MDATA_DATA_V(v) BM_LCD_MDATA_DATA | ||
| 391 | |||
| 392 | #define REG_LCD_WTIME jz_reg(LCD_WTIME) | ||
| 393 | #define JA_LCD_WTIME (0xb3050000 + 0xb0) | ||
| 394 | #define JT_LCD_WTIME JIO_32_RW | ||
| 395 | #define JN_LCD_WTIME LCD_WTIME | ||
| 396 | #define JI_LCD_WTIME | ||
| 397 | #define BP_LCD_WTIME_DHTIME 24 | ||
| 398 | #define BM_LCD_WTIME_DHTIME 0xff000000 | ||
| 399 | #define BF_LCD_WTIME_DHTIME(v) (((v) & 0xff) << 24) | ||
| 400 | #define BFM_LCD_WTIME_DHTIME(v) BM_LCD_WTIME_DHTIME | ||
| 401 | #define BF_LCD_WTIME_DHTIME_V(e) BF_LCD_WTIME_DHTIME(BV_LCD_WTIME_DHTIME__##e) | ||
| 402 | #define BFM_LCD_WTIME_DHTIME_V(v) BM_LCD_WTIME_DHTIME | ||
| 403 | #define BP_LCD_WTIME_DLTIME 16 | ||
| 404 | #define BM_LCD_WTIME_DLTIME 0xff0000 | ||
| 405 | #define BF_LCD_WTIME_DLTIME(v) (((v) & 0xff) << 16) | ||
| 406 | #define BFM_LCD_WTIME_DLTIME(v) BM_LCD_WTIME_DLTIME | ||
| 407 | #define BF_LCD_WTIME_DLTIME_V(e) BF_LCD_WTIME_DLTIME(BV_LCD_WTIME_DLTIME__##e) | ||
| 408 | #define BFM_LCD_WTIME_DLTIME_V(v) BM_LCD_WTIME_DLTIME | ||
| 409 | #define BP_LCD_WTIME_CHTIME 8 | ||
| 410 | #define BM_LCD_WTIME_CHTIME 0xff00 | ||
| 411 | #define BF_LCD_WTIME_CHTIME(v) (((v) & 0xff) << 8) | ||
| 412 | #define BFM_LCD_WTIME_CHTIME(v) BM_LCD_WTIME_CHTIME | ||
| 413 | #define BF_LCD_WTIME_CHTIME_V(e) BF_LCD_WTIME_CHTIME(BV_LCD_WTIME_CHTIME__##e) | ||
| 414 | #define BFM_LCD_WTIME_CHTIME_V(v) BM_LCD_WTIME_CHTIME | ||
| 415 | #define BP_LCD_WTIME_CLTIME 0 | ||
| 416 | #define BM_LCD_WTIME_CLTIME 0xff | ||
| 417 | #define BF_LCD_WTIME_CLTIME(v) (((v) & 0xff) << 0) | ||
| 418 | #define BFM_LCD_WTIME_CLTIME(v) BM_LCD_WTIME_CLTIME | ||
| 419 | #define BF_LCD_WTIME_CLTIME_V(e) BF_LCD_WTIME_CLTIME(BV_LCD_WTIME_CLTIME__##e) | ||
| 420 | #define BFM_LCD_WTIME_CLTIME_V(v) BM_LCD_WTIME_CLTIME | ||
| 421 | |||
| 422 | #define REG_LCD_TASH jz_reg(LCD_TASH) | ||
| 423 | #define JA_LCD_TASH (0xb3050000 + 0xb4) | ||
| 424 | #define JT_LCD_TASH JIO_32_RW | ||
| 425 | #define JN_LCD_TASH LCD_TASH | ||
| 426 | #define JI_LCD_TASH | ||
| 427 | #define BP_LCD_TASH_TAH 8 | ||
| 428 | #define BM_LCD_TASH_TAH 0xff00 | ||
| 429 | #define BF_LCD_TASH_TAH(v) (((v) & 0xff) << 8) | ||
| 430 | #define BFM_LCD_TASH_TAH(v) BM_LCD_TASH_TAH | ||
| 431 | #define BF_LCD_TASH_TAH_V(e) BF_LCD_TASH_TAH(BV_LCD_TASH_TAH__##e) | ||
| 432 | #define BFM_LCD_TASH_TAH_V(v) BM_LCD_TASH_TAH | ||
| 433 | #define BP_LCD_TASH_TAS 0 | ||
| 434 | #define BM_LCD_TASH_TAS 0xff | ||
| 435 | #define BF_LCD_TASH_TAS(v) (((v) & 0xff) << 0) | ||
| 436 | #define BFM_LCD_TASH_TAS(v) BM_LCD_TASH_TAS | ||
| 437 | #define BF_LCD_TASH_TAS_V(e) BF_LCD_TASH_TAS(BV_LCD_TASH_TAS__##e) | ||
| 438 | #define BFM_LCD_TASH_TAS_V(v) BM_LCD_TASH_TAS | ||
| 439 | |||
| 440 | #define REG_LCD_SMWT jz_reg(LCD_SMWT) | ||
| 441 | #define JA_LCD_SMWT (0xb3050000 + 0xbc) | ||
| 442 | #define JT_LCD_SMWT JIO_32_RW | ||
| 443 | #define JN_LCD_SMWT LCD_SMWT | ||
| 444 | #define JI_LCD_SMWT | ||
| 445 | |||
| 446 | #endif /* __HEADERGEN_LCD_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/macro.h b/firmware/target/mips/ingenic_x1000/x1000/macro.h new file mode 100644 index 0000000000..bfe8708a91 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/macro.h | |||
| @@ -0,0 +1,356 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * | ||
| 11 | * Copyright (C) 2015 by the authors | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or | ||
| 14 | * modify it under the terms of the GNU General Public License | ||
| 15 | * as published by the Free Software Foundation; either version 2 | ||
| 16 | * of the License, or (at your option) any later version. | ||
| 17 | * | ||
| 18 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 19 | * KIND, either express or implied. | ||
| 20 | * | ||
| 21 | ****************************************************************************/ | ||
| 22 | #ifndef __HEADERGEN_MACRO_H__ | ||
| 23 | #define __HEADERGEN_MACRO_H__ | ||
| 24 | |||
| 25 | #include <stdint.h> | ||
| 26 | |||
| 27 | #define __VAR_OR1(prefix, suffix) \ | ||
| 28 | (prefix##suffix) | ||
| 29 | #define __VAR_OR2(pre, s1, s2) \ | ||
| 30 | (__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2)) | ||
| 31 | #define __VAR_OR3(pre, s1, s2, s3) \ | ||
| 32 | (__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3)) | ||
| 33 | #define __VAR_OR4(pre, s1, s2, s3, s4) \ | ||
| 34 | (__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4)) | ||
| 35 | #define __VAR_OR5(pre, s1, s2, s3, s4, s5) \ | ||
| 36 | (__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5)) | ||
| 37 | #define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \ | ||
| 38 | (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6)) | ||
| 39 | #define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \ | ||
| 40 | (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7)) | ||
| 41 | #define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \ | ||
| 42 | (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8)) | ||
| 43 | #define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \ | ||
| 44 | (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9)) | ||
| 45 | #define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \ | ||
| 46 | (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10)) | ||
| 47 | #define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \ | ||
| 48 | (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11)) | ||
| 49 | #define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \ | ||
| 50 | (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12)) | ||
| 51 | #define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \ | ||
| 52 | (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13)) | ||
| 53 | |||
| 54 | #define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1) | ||
| 55 | #define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, N, ...) N | ||
| 56 | |||
| 57 | #define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__) | ||
| 58 | #define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__) | ||
| 59 | #define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__) | ||
| 60 | #define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__) | ||
| 61 | |||
| 62 | #define JIO_8_RO(op, name, ...) JIO_8_RO_##op(name, __VA_ARGS__) | ||
| 63 | #define JIO_8_RO_RD(name, ...) (*(const volatile uint8_t *)(JA_##name)) | ||
| 64 | #define JIO_8_RO_WR(name, val) _Static_assert(0, #name " is read-only") | ||
| 65 | #define JIO_8_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") | ||
| 66 | #define JIO_8_RO_VAR(name, ...) (*(const volatile uint8_t *)(JA_##name)) | ||
| 67 | |||
| 68 | #define JIO_16_RO(op, name, ...) JIO_16_RO_##op(name, __VA_ARGS__) | ||
| 69 | #define JIO_16_RO_RD(name, ...) (*(const volatile uint16_t *)(JA_##name)) | ||
| 70 | #define JIO_16_RO_WR(name, val) _Static_assert(0, #name " is read-only") | ||
| 71 | #define JIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") | ||
| 72 | #define JIO_16_RO_VAR(name, ...) (*(const volatile uint16_t *)(JA_##name)) | ||
| 73 | |||
| 74 | #define JIO_32_RO(op, name, ...) JIO_32_RO_##op(name, __VA_ARGS__) | ||
| 75 | #define JIO_32_RO_RD(name, ...) (*(const volatile uint32_t *)(JA_##name)) | ||
| 76 | #define JIO_32_RO_WR(name, val) _Static_assert(0, #name " is read-only") | ||
| 77 | #define JIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") | ||
| 78 | #define JIO_32_RO_VAR(name, ...) (*(const volatile uint32_t *)(JA_##name)) | ||
| 79 | |||
| 80 | #define JIO_8_RW(op, name, ...) JIO_8_RW_##op(name, __VA_ARGS__) | ||
| 81 | #define JIO_8_RW_RD(name, ...) (*(volatile uint8_t *)(JA_##name)) | ||
| 82 | #define JIO_8_RW_WR(name, val) (*(volatile uint8_t *)(JA_##name)) = (val) | ||
| 83 | #define JIO_8_RW_RMW(name, vand, vor) JIO_8_RW_WR(name, (JIO_8_RW_RD(name) & (vand)) | (vor)) | ||
| 84 | #define JIO_8_RW_VAR(name, ...) (*(volatile uint8_t *)(JA_##name)) | ||
| 85 | |||
| 86 | #define JIO_16_RW(op, name, ...) JIO_16_RW_##op(name, __VA_ARGS__) | ||
| 87 | #define JIO_16_RW_RD(name, ...) (*(volatile uint16_t *)(JA_##name)) | ||
| 88 | #define JIO_16_RW_WR(name, val) (*(volatile uint16_t *)(JA_##name)) = (val) | ||
| 89 | #define JIO_16_RW_RMW(name, vand, vor) JIO_16_RW_WR(name, (JIO_16_RW_RD(name) & (vand)) | (vor)) | ||
| 90 | #define JIO_16_RW_VAR(name, ...) (*(volatile uint16_t *)(JA_##name)) | ||
| 91 | |||
| 92 | #define JIO_32_RW(op, name, ...) JIO_32_RW_##op(name, __VA_ARGS__) | ||
| 93 | #define JIO_32_RW_RD(name, ...) (*(volatile uint32_t *)(JA_##name)) | ||
| 94 | #define JIO_32_RW_WR(name, val) (*(volatile uint32_t *)(JA_##name)) = (val) | ||
| 95 | #define JIO_32_RW_RMW(name, vand, vor) JIO_32_RW_WR(name, (JIO_32_RW_RD(name) & (vand)) | (vor)) | ||
| 96 | #define JIO_32_RW_VAR(name, ...) (*(volatile uint32_t *)(JA_##name)) | ||
| 97 | |||
| 98 | #define JIO_8_WO(op, name, ...) JIO_8_WO_##op(name, __VA_ARGS__) | ||
| 99 | #define JIO_8_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) | ||
| 100 | #define JIO_8_WO_WR(name, val) (*(volatile uint8_t *)(JA_##name)) = (val) | ||
| 101 | #define JIO_8_WO_RMW(name, vand, vor) JIO_8_WO_WR(name, vor) | ||
| 102 | #define JIO_8_WO_VAR(name, ...) (*(volatile uint8_t *)(JA_##name)) | ||
| 103 | |||
| 104 | #define JIO_16_WO(op, name, ...) JIO_16_WO_##op(name, __VA_ARGS__) | ||
| 105 | #define JIO_16_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) | ||
| 106 | #define JIO_16_WO_WR(name, val) (*(volatile uint16_t *)(JA_##name)) = (val) | ||
| 107 | #define JIO_16_WO_RMW(name, vand, vor) JIO_16_WO_WR(name, vor) | ||
| 108 | #define JIO_16_WO_VAR(name, ...) (*(volatile uint16_t *)(JA_##name)) | ||
| 109 | |||
| 110 | #define JIO_32_WO(op, name, ...) JIO_32_WO_##op(name, __VA_ARGS__) | ||
| 111 | #define JIO_32_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) | ||
| 112 | #define JIO_32_WO_WR(name, val) (*(volatile uint32_t *)(JA_##name)) = (val) | ||
| 113 | #define JIO_32_WO_RMW(name, vand, vor) JIO_32_WO_WR(name, vor) | ||
| 114 | #define JIO_32_WO_VAR(name, ...) (*(volatile uint32_t *)(JA_##name)) | ||
| 115 | |||
| 116 | |||
| 117 | /** __jz_variant | ||
| 118 | * | ||
| 119 | * usage: __jz_variant(register, variant_prefix, variant_postfix) | ||
| 120 | * | ||
| 121 | * effect: expands to register variant given as argument | ||
| 122 | * note: internal usage | ||
| 123 | * note: register must be fully qualified if indexed | ||
| 124 | * | ||
| 125 | * example: __jz_variant(ICOLL_CTRL, , _SET) | ||
| 126 | * example: __jz_variant(ICOLL_ENABLE(3), , _CLR) | ||
| 127 | */ | ||
| 128 | #define __jz_variant(name, varp, vars) __jz_variant_(JN_##name, JI_##name, varp, vars) | ||
| 129 | #define __jz_variant_(...) __jz_variant__(__VA_ARGS__) | ||
| 130 | #define __jz_variant__(name, index, varp, vars) varp##name##vars index | ||
| 131 | |||
| 132 | /** jz_orf | ||
| 133 | * | ||
| 134 | * usage: jz_orf(register, f1(v1), f2(v2), ...) | ||
| 135 | * | ||
| 136 | * effect: expands to the register value where each field fi has value vi. | ||
| 137 | * Informally: reg_f1(v1) | reg_f2(v2) | ... | ||
| 138 | * note: enumerated values for fields can be obtained by using the syntax: | ||
| 139 | * f1_V(name) | ||
| 140 | * | ||
| 141 | * example: jz_orf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
| 142 | */ | ||
| 143 | #define jz_orf(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__) | ||
| 144 | |||
| 145 | /** __jz_orfm | ||
| 146 | * | ||
| 147 | * usage: __jz_orfm(register, f1(v1), f2(v2), ...) | ||
| 148 | * | ||
| 149 | * effect: expands to the register value where each field fi has maximum value (vi is ignored). | ||
| 150 | * note: internal usage | ||
| 151 | * | ||
| 152 | * example: __jz_orfm(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
| 153 | */ | ||
| 154 | #define __jz_orfm(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__) | ||
| 155 | |||
| 156 | /** jz_orm | ||
| 157 | * | ||
| 158 | * usage: jz_orm(register, f1, f2, ...) | ||
| 159 | * | ||
| 160 | * effect: expands to the register value where each field fi is set to its maximum value. | ||
| 161 | * Informally: reg_f1_mask | reg_f2_mask | ... | ||
| 162 | * | ||
| 163 | * example: jz_orm(ICOLL_CTRL, SFTRST, CLKGATE) | ||
| 164 | */ | ||
| 165 | #define jz_orm(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__) | ||
| 166 | |||
| 167 | |||
| 168 | /** jz_read | ||
| 169 | * | ||
| 170 | * usage: jz_read(register) | ||
| 171 | * | ||
| 172 | * effect: read a register and return its value | ||
| 173 | * note: register must be fully qualified if indexed | ||
| 174 | * | ||
| 175 | * example: jz_read(ICOLL_STATUS) | ||
| 176 | * jz_read(ICOLL_ENABLE(42)) | ||
| 177 | */ | ||
| 178 | #define jz_read(name) JT_##name(RD, name) | ||
| 179 | |||
| 180 | /** jz_vreadf | ||
| 181 | * | ||
| 182 | * usage: jz_vreadf(value, register, field) | ||
| 183 | * | ||
| 184 | * effect: given a register value, return the value of a particular field | ||
| 185 | * note: this macro does NOT read any register | ||
| 186 | * | ||
| 187 | * example: jz_vreadf(0xc0000000, ICOLL_CTRL, SFTRST) | ||
| 188 | * jz_vreadf(0x46ff, ICOLL_ENABLE, CPU0_PRIO) | ||
| 189 | */ | ||
| 190 | #define jz_vreadf(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field) | ||
| 191 | |||
| 192 | /** jz_readf | ||
| 193 | * | ||
| 194 | * usage: jz_readf(register, field) | ||
| 195 | * | ||
| 196 | * effect: read a register and return the value of a particular field | ||
| 197 | * note: register must be fully qualified if indexed | ||
| 198 | * | ||
| 199 | * example: jz_readf(ICOLL_CTRL, SFTRST) | ||
| 200 | * jz_readf(ICOLL_ENABLE(3), CPU0_PRIO) | ||
| 201 | */ | ||
| 202 | #define jz_readf(name, field) jz_readf_(jz_read(name), JN_##name, field) | ||
| 203 | #define jz_readf_(...) jz_vreadf(__VA_ARGS__) | ||
| 204 | |||
| 205 | /** jz_write | ||
| 206 | * | ||
| 207 | * usage: jz_write(register, value) | ||
| 208 | * | ||
| 209 | * effect: write a register | ||
| 210 | * note: register must be fully qualified if indexed | ||
| 211 | * | ||
| 212 | * example: jz_write(ICOLL_CTRL, 0x42) | ||
| 213 | * jz_write(ICOLL_ENABLE_SET(3), 0x37) | ||
| 214 | */ | ||
| 215 | #define jz_write(name, val) JT_##name(WR, name, val) | ||
| 216 | |||
| 217 | /** jz_writef | ||
| 218 | * | ||
| 219 | * usage: jz_writef(register, f1(v1), f2(v2), ...) | ||
| 220 | * | ||
| 221 | * effect: change the register value so that field fi has value vi | ||
| 222 | * note: register must be fully qualified if indexed | ||
| 223 | * note: this macro may perform a read-modify-write | ||
| 224 | * | ||
| 225 | * example: jz_writef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
| 226 | * jz_writef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
| 227 | */ | ||
| 228 | #define jz_writef(name, ...) jz_writef_(name, JN_##name, __VA_ARGS__) | ||
| 229 | #define jz_writef_(name, name2, ...) JT_##name(RMW, name, ~__jz_orfm(name2, __VA_ARGS__), jz_orf(name2, __VA_ARGS__)) | ||
| 230 | |||
| 231 | /** jz_overwritef | ||
| 232 | * | ||
| 233 | * usage: jz_overwritef(register, f1(v1), f2(v2), ...) | ||
| 234 | * | ||
| 235 | * effect: change the register value so that field fi has value vi and other fields have value zero | ||
| 236 | * thus this macro is equivalent to: | ||
| 237 | * jz_write(register, jz_orf(register, f1(v1), ...)) | ||
| 238 | * note: register must be fully qualified if indexed | ||
| 239 | * note: this macro will overwrite the register (it is NOT a read-modify-write) | ||
| 240 | * | ||
| 241 | * example: jz_overwritef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
| 242 | * jz_overwritef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
| 243 | */ | ||
| 244 | #define jz_overwritef(name, ...) jz_overwritef_(name, JN_##name, __VA_ARGS__) | ||
| 245 | #define jz_overwritef_(name, name2, ...) JT_##name(WR, name, jz_orf(name2, __VA_ARGS__)) | ||
| 246 | |||
| 247 | /** jz_vwritef | ||
| 248 | * | ||
| 249 | * usage: jz_vwritef(var, register, f1(v1), f2(v2), ...) | ||
| 250 | * | ||
| 251 | * effect: change the variable value so that field fi has value vi | ||
| 252 | * note: this macro will perform a read-modify-write | ||
| 253 | * | ||
| 254 | * example: jz_vwritef(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
| 255 | * jz_vwritef(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
| 256 | */ | ||
| 257 | #define jz_vwritef(var, name, ...) (var) = jz_orf(name, __VA_ARGS__) | (~__jz_orfm(name, __VA_ARGS__) & (var)) | ||
| 258 | |||
| 259 | /** jz_setf | ||
| 260 | * | ||
| 261 | * usage: jz_setf(register, f1, f2, ...) | ||
| 262 | * | ||
| 263 | * effect: change the register value so that field fi has maximum value | ||
| 264 | * IMPORTANT: this macro performs a write to the set variant of the register | ||
| 265 | * note: register must be fully qualified if indexed | ||
| 266 | * | ||
| 267 | * example: jz_setf(ICOLL_CTRL, SFTRST, CLKGATE) | ||
| 268 | * jz_setf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) | ||
| 269 | */ | ||
| 270 | #define jz_setf(name, ...) jz_setf_(__jz_variant(name, , _SET), JN_##name, __VA_ARGS__) | ||
| 271 | #define jz_setf_(name, name2, ...) jz_write(name, jz_orm(name2, __VA_ARGS__)) | ||
| 272 | |||
| 273 | /** jz_clrf | ||
| 274 | * | ||
| 275 | * usage: jz_clrf(register, f1, f2, ...) | ||
| 276 | * | ||
| 277 | * effect: change the register value so that field fi has value zero | ||
| 278 | * IMPORTANT: this macro performs a write to the clr variant of the register | ||
| 279 | * note: register must be fully qualified if indexed | ||
| 280 | * | ||
| 281 | * example: jz_clrf(ICOLL_CTRL, SFTRST, CLKGATE) | ||
| 282 | * jz_clrf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) | ||
| 283 | */ | ||
| 284 | #define jz_clrf(name, ...) jz_clrf_(__jz_variant(name, , _CLR), JN_##name, __VA_ARGS__) | ||
| 285 | #define jz_clrf_(name, name2, ...) jz_write(name, jz_orm(name2, __VA_ARGS__)) | ||
| 286 | |||
| 287 | /** jz_set | ||
| 288 | * | ||
| 289 | * usage: jz_set(register, set_value) | ||
| 290 | * | ||
| 291 | * effect: set some bits using set variant | ||
| 292 | * note: register must be fully qualified if indexed | ||
| 293 | * | ||
| 294 | * example: jz_set(ICOLL_CTRL, 0x42) | ||
| 295 | * jz_set(ICOLL_ENABLE(3), 0x37) | ||
| 296 | */ | ||
| 297 | #define jz_set(name, sval) jz_set_(__jz_variant(name, , _SET), sval) | ||
| 298 | #define jz_set_(sname, sval) jz_write(sname, sval) | ||
| 299 | |||
| 300 | /** jz_clr | ||
| 301 | * | ||
| 302 | * usage: jz_clr(register, clr_value) | ||
| 303 | * | ||
| 304 | * effect: clear some bits using clr variant | ||
| 305 | * note: register must be fully qualified if indexed | ||
| 306 | * | ||
| 307 | * example: jz_clr(ICOLL_CTRL, 0x42) | ||
| 308 | * jz_clr(ICOLL_ENABLE(3), 0x37) | ||
| 309 | */ | ||
| 310 | #define jz_clr(name, cval) jz_clr_(__jz_variant(name, , _CLR), cval) | ||
| 311 | #define jz_clr_(cname, cval) jz_write(cname, cval) | ||
| 312 | |||
| 313 | /** jz_cs | ||
| 314 | * | ||
| 315 | * usage: jz_cs(register, clear_value, set_value) | ||
| 316 | * | ||
| 317 | * effect: clear some bits using clr variant and then set some using set variant | ||
| 318 | * note: register must be fully qualified if indexed | ||
| 319 | * | ||
| 320 | * example: jz_cs(ICOLL_CTRL, 0xff, 0x42) | ||
| 321 | * jz_cs(ICOLL_ENABLE(3), 0xff, 0x37) | ||
| 322 | */ | ||
| 323 | #define jz_cs(name, cval, sval) jz_cs_(__jz_variant(name, , _CLR), __jz_variant(name, , _SET), cval, sval) | ||
| 324 | #define jz_cs_(cname, sname, cval, sval) do { jz_write(cname, cval); jz_write(sname, sval); } while(0) | ||
| 325 | |||
| 326 | /** jz_csf | ||
| 327 | * | ||
| 328 | * usage: jz_csf(register, f1(v1), f2(v2), ...) | ||
| 329 | * | ||
| 330 | * effect: change the register value so that field fi has value vi using clr and set variants | ||
| 331 | * note: register must be fully qualified if indexed | ||
| 332 | * note: this macro will NOT perform a read-modify-write and is thus safer | ||
| 333 | * IMPORTANT: this macro will set some fields to 0 temporarily, make sure this is acceptable | ||
| 334 | * | ||
| 335 | * example: jz_csf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) | ||
| 336 | * jz_csf(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) | ||
| 337 | */ | ||
| 338 | #define jz_csf(name, ...) jz_csf_(name, JN_##name, __VA_ARGS__) | ||
| 339 | #define jz_csf_(name, name2, ...) jz_cs(name, __jz_orfm(name2, __VA_ARGS__), jz_orf(name2, __VA_ARGS__)) | ||
| 340 | |||
| 341 | /** jz_reg | ||
| 342 | * | ||
| 343 | * usage: jz_reg(register) | ||
| 344 | * | ||
| 345 | * effect: return a variable-like expression that can be read/written | ||
| 346 | * note: register must be fully qualified if indexed | ||
| 347 | * note: read-only registers will yield a constant expression | ||
| 348 | * | ||
| 349 | * example: unsigned x = jz_reg(ICOLL_STATUS) | ||
| 350 | * unsigned x = jz_reg(ICOLL_ENABLE(42)) | ||
| 351 | * jz_reg(ICOLL_ENABLE(42)) = 64 | ||
| 352 | */ | ||
| 353 | #define jz_reg(name) JT_##name(VAR, name) | ||
| 354 | |||
| 355 | |||
| 356 | #endif /* __HEADERGEN_MACRO_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/msc.h b/firmware/target/mips/ingenic_x1000/x1000/msc.h new file mode 100644 index 0000000000..762b4b1461 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/msc.h | |||
| @@ -0,0 +1,824 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_MSC_H__ | ||
| 25 | #define __HEADERGEN_MSC_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_MSC_CTRL(_n1) jz_reg(MSC_CTRL(_n1)) | ||
| 30 | #define JA_MSC_CTRL(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x0) | ||
| 31 | #define JT_MSC_CTRL(_n1) JIO_32_RW | ||
| 32 | #define JN_MSC_CTRL(_n1) MSC_CTRL | ||
| 33 | #define JI_MSC_CTRL(_n1) (_n1) | ||
| 34 | #define BP_MSC_CTRL_CLOCK 0 | ||
| 35 | #define BM_MSC_CTRL_CLOCK 0x3 | ||
| 36 | #define BV_MSC_CTRL_CLOCK__DO_NOTHING 0x0 | ||
| 37 | #define BV_MSC_CTRL_CLOCK__STOP 0x1 | ||
| 38 | #define BV_MSC_CTRL_CLOCK__START 0x2 | ||
| 39 | #define BF_MSC_CTRL_CLOCK(v) (((v) & 0x3) << 0) | ||
| 40 | #define BFM_MSC_CTRL_CLOCK(v) BM_MSC_CTRL_CLOCK | ||
| 41 | #define BF_MSC_CTRL_CLOCK_V(e) BF_MSC_CTRL_CLOCK(BV_MSC_CTRL_CLOCK__##e) | ||
| 42 | #define BFM_MSC_CTRL_CLOCK_V(v) BM_MSC_CTRL_CLOCK | ||
| 43 | #define BP_MSC_CTRL_SEND_CCSD 15 | ||
| 44 | #define BM_MSC_CTRL_SEND_CCSD 0x8000 | ||
| 45 | #define BF_MSC_CTRL_SEND_CCSD(v) (((v) & 0x1) << 15) | ||
| 46 | #define BFM_MSC_CTRL_SEND_CCSD(v) BM_MSC_CTRL_SEND_CCSD | ||
| 47 | #define BF_MSC_CTRL_SEND_CCSD_V(e) BF_MSC_CTRL_SEND_CCSD(BV_MSC_CTRL_SEND_CCSD__##e) | ||
| 48 | #define BFM_MSC_CTRL_SEND_CCSD_V(v) BM_MSC_CTRL_SEND_CCSD | ||
| 49 | #define BP_MSC_CTRL_SEND_AS_CCSD 14 | ||
| 50 | #define BM_MSC_CTRL_SEND_AS_CCSD 0x4000 | ||
| 51 | #define BF_MSC_CTRL_SEND_AS_CCSD(v) (((v) & 0x1) << 14) | ||
| 52 | #define BFM_MSC_CTRL_SEND_AS_CCSD(v) BM_MSC_CTRL_SEND_AS_CCSD | ||
| 53 | #define BF_MSC_CTRL_SEND_AS_CCSD_V(e) BF_MSC_CTRL_SEND_AS_CCSD(BV_MSC_CTRL_SEND_AS_CCSD__##e) | ||
| 54 | #define BFM_MSC_CTRL_SEND_AS_CCSD_V(v) BM_MSC_CTRL_SEND_AS_CCSD | ||
| 55 | #define BP_MSC_CTRL_EXIT_MULTIPLE 7 | ||
| 56 | #define BM_MSC_CTRL_EXIT_MULTIPLE 0x80 | ||
| 57 | #define BF_MSC_CTRL_EXIT_MULTIPLE(v) (((v) & 0x1) << 7) | ||
| 58 | #define BFM_MSC_CTRL_EXIT_MULTIPLE(v) BM_MSC_CTRL_EXIT_MULTIPLE | ||
| 59 | #define BF_MSC_CTRL_EXIT_MULTIPLE_V(e) BF_MSC_CTRL_EXIT_MULTIPLE(BV_MSC_CTRL_EXIT_MULTIPLE__##e) | ||
| 60 | #define BFM_MSC_CTRL_EXIT_MULTIPLE_V(v) BM_MSC_CTRL_EXIT_MULTIPLE | ||
| 61 | #define BP_MSC_CTRL_EXIT_TRANSFER 6 | ||
| 62 | #define BM_MSC_CTRL_EXIT_TRANSFER 0x40 | ||
| 63 | #define BF_MSC_CTRL_EXIT_TRANSFER(v) (((v) & 0x1) << 6) | ||
| 64 | #define BFM_MSC_CTRL_EXIT_TRANSFER(v) BM_MSC_CTRL_EXIT_TRANSFER | ||
| 65 | #define BF_MSC_CTRL_EXIT_TRANSFER_V(e) BF_MSC_CTRL_EXIT_TRANSFER(BV_MSC_CTRL_EXIT_TRANSFER__##e) | ||
| 66 | #define BFM_MSC_CTRL_EXIT_TRANSFER_V(v) BM_MSC_CTRL_EXIT_TRANSFER | ||
| 67 | #define BP_MSC_CTRL_START_READ_WAIT 5 | ||
| 68 | #define BM_MSC_CTRL_START_READ_WAIT 0x20 | ||
| 69 | #define BF_MSC_CTRL_START_READ_WAIT(v) (((v) & 0x1) << 5) | ||
| 70 | #define BFM_MSC_CTRL_START_READ_WAIT(v) BM_MSC_CTRL_START_READ_WAIT | ||
| 71 | #define BF_MSC_CTRL_START_READ_WAIT_V(e) BF_MSC_CTRL_START_READ_WAIT(BV_MSC_CTRL_START_READ_WAIT__##e) | ||
| 72 | #define BFM_MSC_CTRL_START_READ_WAIT_V(v) BM_MSC_CTRL_START_READ_WAIT | ||
| 73 | #define BP_MSC_CTRL_STOP_READ_WAIT 4 | ||
| 74 | #define BM_MSC_CTRL_STOP_READ_WAIT 0x10 | ||
| 75 | #define BF_MSC_CTRL_STOP_READ_WAIT(v) (((v) & 0x1) << 4) | ||
| 76 | #define BFM_MSC_CTRL_STOP_READ_WAIT(v) BM_MSC_CTRL_STOP_READ_WAIT | ||
| 77 | #define BF_MSC_CTRL_STOP_READ_WAIT_V(e) BF_MSC_CTRL_STOP_READ_WAIT(BV_MSC_CTRL_STOP_READ_WAIT__##e) | ||
| 78 | #define BFM_MSC_CTRL_STOP_READ_WAIT_V(v) BM_MSC_CTRL_STOP_READ_WAIT | ||
| 79 | #define BP_MSC_CTRL_RESET 3 | ||
| 80 | #define BM_MSC_CTRL_RESET 0x8 | ||
| 81 | #define BF_MSC_CTRL_RESET(v) (((v) & 0x1) << 3) | ||
| 82 | #define BFM_MSC_CTRL_RESET(v) BM_MSC_CTRL_RESET | ||
| 83 | #define BF_MSC_CTRL_RESET_V(e) BF_MSC_CTRL_RESET(BV_MSC_CTRL_RESET__##e) | ||
| 84 | #define BFM_MSC_CTRL_RESET_V(v) BM_MSC_CTRL_RESET | ||
| 85 | #define BP_MSC_CTRL_START_OP 2 | ||
| 86 | #define BM_MSC_CTRL_START_OP 0x4 | ||
| 87 | #define BF_MSC_CTRL_START_OP(v) (((v) & 0x1) << 2) | ||
| 88 | #define BFM_MSC_CTRL_START_OP(v) BM_MSC_CTRL_START_OP | ||
| 89 | #define BF_MSC_CTRL_START_OP_V(e) BF_MSC_CTRL_START_OP(BV_MSC_CTRL_START_OP__##e) | ||
| 90 | #define BFM_MSC_CTRL_START_OP_V(v) BM_MSC_CTRL_START_OP | ||
| 91 | |||
| 92 | #define REG_MSC_STAT(_n1) jz_reg(MSC_STAT(_n1)) | ||
| 93 | #define JA_MSC_STAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4) | ||
| 94 | #define JT_MSC_STAT(_n1) JIO_32_RW | ||
| 95 | #define JN_MSC_STAT(_n1) MSC_STAT | ||
| 96 | #define JI_MSC_STAT(_n1) (_n1) | ||
| 97 | #define BP_MSC_STAT_PINS 24 | ||
| 98 | #define BM_MSC_STAT_PINS 0x1f000000 | ||
| 99 | #define BF_MSC_STAT_PINS(v) (((v) & 0x1f) << 24) | ||
| 100 | #define BFM_MSC_STAT_PINS(v) BM_MSC_STAT_PINS | ||
| 101 | #define BF_MSC_STAT_PINS_V(e) BF_MSC_STAT_PINS(BV_MSC_STAT_PINS__##e) | ||
| 102 | #define BFM_MSC_STAT_PINS_V(v) BM_MSC_STAT_PINS | ||
| 103 | #define BP_MSC_STAT_CRC_WRITE_ERROR 2 | ||
| 104 | #define BM_MSC_STAT_CRC_WRITE_ERROR 0xc | ||
| 105 | #define BV_MSC_STAT_CRC_WRITE_ERROR__NONE 0x0 | ||
| 106 | #define BV_MSC_STAT_CRC_WRITE_ERROR__BADDATA 0x1 | ||
| 107 | #define BV_MSC_STAT_CRC_WRITE_ERROR__NOCRC 0x2 | ||
| 108 | #define BF_MSC_STAT_CRC_WRITE_ERROR(v) (((v) & 0x3) << 2) | ||
| 109 | #define BFM_MSC_STAT_CRC_WRITE_ERROR(v) BM_MSC_STAT_CRC_WRITE_ERROR | ||
| 110 | #define BF_MSC_STAT_CRC_WRITE_ERROR_V(e) BF_MSC_STAT_CRC_WRITE_ERROR(BV_MSC_STAT_CRC_WRITE_ERROR__##e) | ||
| 111 | #define BFM_MSC_STAT_CRC_WRITE_ERROR_V(v) BM_MSC_STAT_CRC_WRITE_ERROR | ||
| 112 | #define BP_MSC_STAT_AUTO_CMD12_DONE 31 | ||
| 113 | #define BM_MSC_STAT_AUTO_CMD12_DONE 0x80000000 | ||
| 114 | #define BF_MSC_STAT_AUTO_CMD12_DONE(v) (((v) & 0x1) << 31) | ||
| 115 | #define BFM_MSC_STAT_AUTO_CMD12_DONE(v) BM_MSC_STAT_AUTO_CMD12_DONE | ||
| 116 | #define BF_MSC_STAT_AUTO_CMD12_DONE_V(e) BF_MSC_STAT_AUTO_CMD12_DONE(BV_MSC_STAT_AUTO_CMD12_DONE__##e) | ||
| 117 | #define BFM_MSC_STAT_AUTO_CMD12_DONE_V(v) BM_MSC_STAT_AUTO_CMD12_DONE | ||
| 118 | #define BP_MSC_STAT_BCE 20 | ||
| 119 | #define BM_MSC_STAT_BCE 0x100000 | ||
| 120 | #define BF_MSC_STAT_BCE(v) (((v) & 0x1) << 20) | ||
| 121 | #define BFM_MSC_STAT_BCE(v) BM_MSC_STAT_BCE | ||
| 122 | #define BF_MSC_STAT_BCE_V(e) BF_MSC_STAT_BCE(BV_MSC_STAT_BCE__##e) | ||
| 123 | #define BFM_MSC_STAT_BCE_V(v) BM_MSC_STAT_BCE | ||
| 124 | #define BP_MSC_STAT_BDE 19 | ||
| 125 | #define BM_MSC_STAT_BDE 0x80000 | ||
| 126 | #define BF_MSC_STAT_BDE(v) (((v) & 0x1) << 19) | ||
| 127 | #define BFM_MSC_STAT_BDE(v) BM_MSC_STAT_BDE | ||
| 128 | #define BF_MSC_STAT_BDE_V(e) BF_MSC_STAT_BDE(BV_MSC_STAT_BDE__##e) | ||
| 129 | #define BFM_MSC_STAT_BDE_V(v) BM_MSC_STAT_BDE | ||
| 130 | #define BP_MSC_STAT_BAE 18 | ||
| 131 | #define BM_MSC_STAT_BAE 0x40000 | ||
| 132 | #define BF_MSC_STAT_BAE(v) (((v) & 0x1) << 18) | ||
| 133 | #define BFM_MSC_STAT_BAE(v) BM_MSC_STAT_BAE | ||
| 134 | #define BF_MSC_STAT_BAE_V(e) BF_MSC_STAT_BAE(BV_MSC_STAT_BAE__##e) | ||
| 135 | #define BFM_MSC_STAT_BAE_V(v) BM_MSC_STAT_BAE | ||
| 136 | #define BP_MSC_STAT_BAR 17 | ||
| 137 | #define BM_MSC_STAT_BAR 0x20000 | ||
| 138 | #define BF_MSC_STAT_BAR(v) (((v) & 0x1) << 17) | ||
| 139 | #define BFM_MSC_STAT_BAR(v) BM_MSC_STAT_BAR | ||
| 140 | #define BF_MSC_STAT_BAR_V(e) BF_MSC_STAT_BAR(BV_MSC_STAT_BAR__##e) | ||
| 141 | #define BFM_MSC_STAT_BAR_V(v) BM_MSC_STAT_BAR | ||
| 142 | #define BP_MSC_STAT_DMAEND 16 | ||
| 143 | #define BM_MSC_STAT_DMAEND 0x10000 | ||
| 144 | #define BF_MSC_STAT_DMAEND(v) (((v) & 0x1) << 16) | ||
| 145 | #define BFM_MSC_STAT_DMAEND(v) BM_MSC_STAT_DMAEND | ||
| 146 | #define BF_MSC_STAT_DMAEND_V(e) BF_MSC_STAT_DMAEND(BV_MSC_STAT_DMAEND__##e) | ||
| 147 | #define BFM_MSC_STAT_DMAEND_V(v) BM_MSC_STAT_DMAEND | ||
| 148 | #define BP_MSC_STAT_IS_RESETTING 15 | ||
| 149 | #define BM_MSC_STAT_IS_RESETTING 0x8000 | ||
| 150 | #define BF_MSC_STAT_IS_RESETTING(v) (((v) & 0x1) << 15) | ||
| 151 | #define BFM_MSC_STAT_IS_RESETTING(v) BM_MSC_STAT_IS_RESETTING | ||
| 152 | #define BF_MSC_STAT_IS_RESETTING_V(e) BF_MSC_STAT_IS_RESETTING(BV_MSC_STAT_IS_RESETTING__##e) | ||
| 153 | #define BFM_MSC_STAT_IS_RESETTING_V(v) BM_MSC_STAT_IS_RESETTING | ||
| 154 | #define BP_MSC_STAT_SDIO_INT_ACTIVE 14 | ||
| 155 | #define BM_MSC_STAT_SDIO_INT_ACTIVE 0x4000 | ||
| 156 | #define BF_MSC_STAT_SDIO_INT_ACTIVE(v) (((v) & 0x1) << 14) | ||
| 157 | #define BFM_MSC_STAT_SDIO_INT_ACTIVE(v) BM_MSC_STAT_SDIO_INT_ACTIVE | ||
| 158 | #define BF_MSC_STAT_SDIO_INT_ACTIVE_V(e) BF_MSC_STAT_SDIO_INT_ACTIVE(BV_MSC_STAT_SDIO_INT_ACTIVE__##e) | ||
| 159 | #define BFM_MSC_STAT_SDIO_INT_ACTIVE_V(v) BM_MSC_STAT_SDIO_INT_ACTIVE | ||
| 160 | #define BP_MSC_STAT_PROG_DONE 13 | ||
| 161 | #define BM_MSC_STAT_PROG_DONE 0x2000 | ||
| 162 | #define BF_MSC_STAT_PROG_DONE(v) (((v) & 0x1) << 13) | ||
| 163 | #define BFM_MSC_STAT_PROG_DONE(v) BM_MSC_STAT_PROG_DONE | ||
| 164 | #define BF_MSC_STAT_PROG_DONE_V(e) BF_MSC_STAT_PROG_DONE(BV_MSC_STAT_PROG_DONE__##e) | ||
| 165 | #define BFM_MSC_STAT_PROG_DONE_V(v) BM_MSC_STAT_PROG_DONE | ||
| 166 | #define BP_MSC_STAT_DATA_TRAN_DONE 12 | ||
| 167 | #define BM_MSC_STAT_DATA_TRAN_DONE 0x1000 | ||
| 168 | #define BF_MSC_STAT_DATA_TRAN_DONE(v) (((v) & 0x1) << 12) | ||
| 169 | #define BFM_MSC_STAT_DATA_TRAN_DONE(v) BM_MSC_STAT_DATA_TRAN_DONE | ||
| 170 | #define BF_MSC_STAT_DATA_TRAN_DONE_V(e) BF_MSC_STAT_DATA_TRAN_DONE(BV_MSC_STAT_DATA_TRAN_DONE__##e) | ||
| 171 | #define BFM_MSC_STAT_DATA_TRAN_DONE_V(v) BM_MSC_STAT_DATA_TRAN_DONE | ||
| 172 | #define BP_MSC_STAT_END_CMD_RES 11 | ||
| 173 | #define BM_MSC_STAT_END_CMD_RES 0x800 | ||
| 174 | #define BF_MSC_STAT_END_CMD_RES(v) (((v) & 0x1) << 11) | ||
| 175 | #define BFM_MSC_STAT_END_CMD_RES(v) BM_MSC_STAT_END_CMD_RES | ||
| 176 | #define BF_MSC_STAT_END_CMD_RES_V(e) BF_MSC_STAT_END_CMD_RES(BV_MSC_STAT_END_CMD_RES__##e) | ||
| 177 | #define BFM_MSC_STAT_END_CMD_RES_V(v) BM_MSC_STAT_END_CMD_RES | ||
| 178 | #define BP_MSC_STAT_DATA_FIFO_AFULL 10 | ||
| 179 | #define BM_MSC_STAT_DATA_FIFO_AFULL 0x400 | ||
| 180 | #define BF_MSC_STAT_DATA_FIFO_AFULL(v) (((v) & 0x1) << 10) | ||
| 181 | #define BFM_MSC_STAT_DATA_FIFO_AFULL(v) BM_MSC_STAT_DATA_FIFO_AFULL | ||
| 182 | #define BF_MSC_STAT_DATA_FIFO_AFULL_V(e) BF_MSC_STAT_DATA_FIFO_AFULL(BV_MSC_STAT_DATA_FIFO_AFULL__##e) | ||
| 183 | #define BFM_MSC_STAT_DATA_FIFO_AFULL_V(v) BM_MSC_STAT_DATA_FIFO_AFULL | ||
| 184 | #define BP_MSC_STAT_IS_READ_WAIT 9 | ||
| 185 | #define BM_MSC_STAT_IS_READ_WAIT 0x200 | ||
| 186 | #define BF_MSC_STAT_IS_READ_WAIT(v) (((v) & 0x1) << 9) | ||
| 187 | #define BFM_MSC_STAT_IS_READ_WAIT(v) BM_MSC_STAT_IS_READ_WAIT | ||
| 188 | #define BF_MSC_STAT_IS_READ_WAIT_V(e) BF_MSC_STAT_IS_READ_WAIT(BV_MSC_STAT_IS_READ_WAIT__##e) | ||
| 189 | #define BFM_MSC_STAT_IS_READ_WAIT_V(v) BM_MSC_STAT_IS_READ_WAIT | ||
| 190 | #define BP_MSC_STAT_CLOCK_EN 8 | ||
| 191 | #define BM_MSC_STAT_CLOCK_EN 0x100 | ||
| 192 | #define BF_MSC_STAT_CLOCK_EN(v) (((v) & 0x1) << 8) | ||
| 193 | #define BFM_MSC_STAT_CLOCK_EN(v) BM_MSC_STAT_CLOCK_EN | ||
| 194 | #define BF_MSC_STAT_CLOCK_EN_V(e) BF_MSC_STAT_CLOCK_EN(BV_MSC_STAT_CLOCK_EN__##e) | ||
| 195 | #define BFM_MSC_STAT_CLOCK_EN_V(v) BM_MSC_STAT_CLOCK_EN | ||
| 196 | #define BP_MSC_STAT_DATA_FIFO_FULL 7 | ||
| 197 | #define BM_MSC_STAT_DATA_FIFO_FULL 0x80 | ||
| 198 | #define BF_MSC_STAT_DATA_FIFO_FULL(v) (((v) & 0x1) << 7) | ||
| 199 | #define BFM_MSC_STAT_DATA_FIFO_FULL(v) BM_MSC_STAT_DATA_FIFO_FULL | ||
| 200 | #define BF_MSC_STAT_DATA_FIFO_FULL_V(e) BF_MSC_STAT_DATA_FIFO_FULL(BV_MSC_STAT_DATA_FIFO_FULL__##e) | ||
| 201 | #define BFM_MSC_STAT_DATA_FIFO_FULL_V(v) BM_MSC_STAT_DATA_FIFO_FULL | ||
| 202 | #define BP_MSC_STAT_DATA_FIFO_EMPTY 6 | ||
| 203 | #define BM_MSC_STAT_DATA_FIFO_EMPTY 0x40 | ||
| 204 | #define BF_MSC_STAT_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 6) | ||
| 205 | #define BFM_MSC_STAT_DATA_FIFO_EMPTY(v) BM_MSC_STAT_DATA_FIFO_EMPTY | ||
| 206 | #define BF_MSC_STAT_DATA_FIFO_EMPTY_V(e) BF_MSC_STAT_DATA_FIFO_EMPTY(BV_MSC_STAT_DATA_FIFO_EMPTY__##e) | ||
| 207 | #define BFM_MSC_STAT_DATA_FIFO_EMPTY_V(v) BM_MSC_STAT_DATA_FIFO_EMPTY | ||
| 208 | #define BP_MSC_STAT_CRC_RES_ERROR 5 | ||
| 209 | #define BM_MSC_STAT_CRC_RES_ERROR 0x20 | ||
| 210 | #define BF_MSC_STAT_CRC_RES_ERROR(v) (((v) & 0x1) << 5) | ||
| 211 | #define BFM_MSC_STAT_CRC_RES_ERROR(v) BM_MSC_STAT_CRC_RES_ERROR | ||
| 212 | #define BF_MSC_STAT_CRC_RES_ERROR_V(e) BF_MSC_STAT_CRC_RES_ERROR(BV_MSC_STAT_CRC_RES_ERROR__##e) | ||
| 213 | #define BFM_MSC_STAT_CRC_RES_ERROR_V(v) BM_MSC_STAT_CRC_RES_ERROR | ||
| 214 | #define BP_MSC_STAT_CRC_READ_ERROR 4 | ||
| 215 | #define BM_MSC_STAT_CRC_READ_ERROR 0x10 | ||
| 216 | #define BF_MSC_STAT_CRC_READ_ERROR(v) (((v) & 0x1) << 4) | ||
| 217 | #define BFM_MSC_STAT_CRC_READ_ERROR(v) BM_MSC_STAT_CRC_READ_ERROR | ||
| 218 | #define BF_MSC_STAT_CRC_READ_ERROR_V(e) BF_MSC_STAT_CRC_READ_ERROR(BV_MSC_STAT_CRC_READ_ERROR__##e) | ||
| 219 | #define BFM_MSC_STAT_CRC_READ_ERROR_V(v) BM_MSC_STAT_CRC_READ_ERROR | ||
| 220 | #define BP_MSC_STAT_TIME_OUT_RES 1 | ||
| 221 | #define BM_MSC_STAT_TIME_OUT_RES 0x2 | ||
| 222 | #define BF_MSC_STAT_TIME_OUT_RES(v) (((v) & 0x1) << 1) | ||
| 223 | #define BFM_MSC_STAT_TIME_OUT_RES(v) BM_MSC_STAT_TIME_OUT_RES | ||
| 224 | #define BF_MSC_STAT_TIME_OUT_RES_V(e) BF_MSC_STAT_TIME_OUT_RES(BV_MSC_STAT_TIME_OUT_RES__##e) | ||
| 225 | #define BFM_MSC_STAT_TIME_OUT_RES_V(v) BM_MSC_STAT_TIME_OUT_RES | ||
| 226 | #define BP_MSC_STAT_TIME_OUT_READ 0 | ||
| 227 | #define BM_MSC_STAT_TIME_OUT_READ 0x1 | ||
| 228 | #define BF_MSC_STAT_TIME_OUT_READ(v) (((v) & 0x1) << 0) | ||
| 229 | #define BFM_MSC_STAT_TIME_OUT_READ(v) BM_MSC_STAT_TIME_OUT_READ | ||
| 230 | #define BF_MSC_STAT_TIME_OUT_READ_V(e) BF_MSC_STAT_TIME_OUT_READ(BV_MSC_STAT_TIME_OUT_READ__##e) | ||
| 231 | #define BFM_MSC_STAT_TIME_OUT_READ_V(v) BM_MSC_STAT_TIME_OUT_READ | ||
| 232 | |||
| 233 | #define REG_MSC_CMDAT(_n1) jz_reg(MSC_CMDAT(_n1)) | ||
| 234 | #define JA_MSC_CMDAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0xc) | ||
| 235 | #define JT_MSC_CMDAT(_n1) JIO_32_RW | ||
| 236 | #define JN_MSC_CMDAT(_n1) MSC_CMDAT | ||
| 237 | #define JI_MSC_CMDAT(_n1) (_n1) | ||
| 238 | #define BP_MSC_CMDAT_RTRG 14 | ||
| 239 | #define BM_MSC_CMDAT_RTRG 0xc000 | ||
| 240 | #define BV_MSC_CMDAT_RTRG__GE16 0x0 | ||
| 241 | #define BV_MSC_CMDAT_RTRG__GE32 0x1 | ||
| 242 | #define BV_MSC_CMDAT_RTRG__GE64 0x2 | ||
| 243 | #define BV_MSC_CMDAT_RTRG__GE96 0x3 | ||
| 244 | #define BF_MSC_CMDAT_RTRG(v) (((v) & 0x3) << 14) | ||
| 245 | #define BFM_MSC_CMDAT_RTRG(v) BM_MSC_CMDAT_RTRG | ||
| 246 | #define BF_MSC_CMDAT_RTRG_V(e) BF_MSC_CMDAT_RTRG(BV_MSC_CMDAT_RTRG__##e) | ||
| 247 | #define BFM_MSC_CMDAT_RTRG_V(v) BM_MSC_CMDAT_RTRG | ||
| 248 | #define BP_MSC_CMDAT_TTRG 12 | ||
| 249 | #define BM_MSC_CMDAT_TTRG 0x3000 | ||
| 250 | #define BV_MSC_CMDAT_TTRG__LE16 0x0 | ||
| 251 | #define BV_MSC_CMDAT_TTRG__LE32 0x1 | ||
| 252 | #define BV_MSC_CMDAT_TTRG__LE64 0x2 | ||
| 253 | #define BV_MSC_CMDAT_TTRG__LE96 0x3 | ||
| 254 | #define BF_MSC_CMDAT_TTRG(v) (((v) & 0x3) << 12) | ||
| 255 | #define BFM_MSC_CMDAT_TTRG(v) BM_MSC_CMDAT_TTRG | ||
| 256 | #define BF_MSC_CMDAT_TTRG_V(e) BF_MSC_CMDAT_TTRG(BV_MSC_CMDAT_TTRG__##e) | ||
| 257 | #define BFM_MSC_CMDAT_TTRG_V(v) BM_MSC_CMDAT_TTRG | ||
| 258 | #define BP_MSC_CMDAT_BUS_WIDTH 9 | ||
| 259 | #define BM_MSC_CMDAT_BUS_WIDTH 0x600 | ||
| 260 | #define BV_MSC_CMDAT_BUS_WIDTH__1BIT 0x0 | ||
| 261 | #define BV_MSC_CMDAT_BUS_WIDTH__4BIT 0x2 | ||
| 262 | #define BV_MSC_CMDAT_BUS_WIDTH__8BIT 0x3 | ||
| 263 | #define BF_MSC_CMDAT_BUS_WIDTH(v) (((v) & 0x3) << 9) | ||
| 264 | #define BFM_MSC_CMDAT_BUS_WIDTH(v) BM_MSC_CMDAT_BUS_WIDTH | ||
| 265 | #define BF_MSC_CMDAT_BUS_WIDTH_V(e) BF_MSC_CMDAT_BUS_WIDTH(BV_MSC_CMDAT_BUS_WIDTH__##e) | ||
| 266 | #define BFM_MSC_CMDAT_BUS_WIDTH_V(v) BM_MSC_CMDAT_BUS_WIDTH | ||
| 267 | #define BP_MSC_CMDAT_RESP_FMT 0 | ||
| 268 | #define BM_MSC_CMDAT_RESP_FMT 0x7 | ||
| 269 | #define BF_MSC_CMDAT_RESP_FMT(v) (((v) & 0x7) << 0) | ||
| 270 | #define BFM_MSC_CMDAT_RESP_FMT(v) BM_MSC_CMDAT_RESP_FMT | ||
| 271 | #define BF_MSC_CMDAT_RESP_FMT_V(e) BF_MSC_CMDAT_RESP_FMT(BV_MSC_CMDAT_RESP_FMT__##e) | ||
| 272 | #define BFM_MSC_CMDAT_RESP_FMT_V(v) BM_MSC_CMDAT_RESP_FMT | ||
| 273 | #define BP_MSC_CMDAT_CCS_EXPECTED 31 | ||
| 274 | #define BM_MSC_CMDAT_CCS_EXPECTED 0x80000000 | ||
| 275 | #define BF_MSC_CMDAT_CCS_EXPECTED(v) (((v) & 0x1) << 31) | ||
| 276 | #define BFM_MSC_CMDAT_CCS_EXPECTED(v) BM_MSC_CMDAT_CCS_EXPECTED | ||
| 277 | #define BF_MSC_CMDAT_CCS_EXPECTED_V(e) BF_MSC_CMDAT_CCS_EXPECTED(BV_MSC_CMDAT_CCS_EXPECTED__##e) | ||
| 278 | #define BFM_MSC_CMDAT_CCS_EXPECTED_V(v) BM_MSC_CMDAT_CCS_EXPECTED | ||
| 279 | #define BP_MSC_CMDAT_READ_CEATA 30 | ||
| 280 | #define BM_MSC_CMDAT_READ_CEATA 0x40000000 | ||
| 281 | #define BF_MSC_CMDAT_READ_CEATA(v) (((v) & 0x1) << 30) | ||
| 282 | #define BFM_MSC_CMDAT_READ_CEATA(v) BM_MSC_CMDAT_READ_CEATA | ||
| 283 | #define BF_MSC_CMDAT_READ_CEATA_V(e) BF_MSC_CMDAT_READ_CEATA(BV_MSC_CMDAT_READ_CEATA__##e) | ||
| 284 | #define BFM_MSC_CMDAT_READ_CEATA_V(v) BM_MSC_CMDAT_READ_CEATA | ||
| 285 | #define BP_MSC_CMDAT_DIS_BOOT 27 | ||
| 286 | #define BM_MSC_CMDAT_DIS_BOOT 0x8000000 | ||
| 287 | #define BF_MSC_CMDAT_DIS_BOOT(v) (((v) & 0x1) << 27) | ||
| 288 | #define BFM_MSC_CMDAT_DIS_BOOT(v) BM_MSC_CMDAT_DIS_BOOT | ||
| 289 | #define BF_MSC_CMDAT_DIS_BOOT_V(e) BF_MSC_CMDAT_DIS_BOOT(BV_MSC_CMDAT_DIS_BOOT__##e) | ||
| 290 | #define BFM_MSC_CMDAT_DIS_BOOT_V(v) BM_MSC_CMDAT_DIS_BOOT | ||
| 291 | #define BP_MSC_CMDAT_EXP_BOOT_ACK 25 | ||
| 292 | #define BM_MSC_CMDAT_EXP_BOOT_ACK 0x2000000 | ||
| 293 | #define BF_MSC_CMDAT_EXP_BOOT_ACK(v) (((v) & 0x1) << 25) | ||
| 294 | #define BFM_MSC_CMDAT_EXP_BOOT_ACK(v) BM_MSC_CMDAT_EXP_BOOT_ACK | ||
| 295 | #define BF_MSC_CMDAT_EXP_BOOT_ACK_V(e) BF_MSC_CMDAT_EXP_BOOT_ACK(BV_MSC_CMDAT_EXP_BOOT_ACK__##e) | ||
| 296 | #define BFM_MSC_CMDAT_EXP_BOOT_ACK_V(v) BM_MSC_CMDAT_EXP_BOOT_ACK | ||
| 297 | #define BP_MSC_CMDAT_BOOT_MODE 24 | ||
| 298 | #define BM_MSC_CMDAT_BOOT_MODE 0x1000000 | ||
| 299 | #define BF_MSC_CMDAT_BOOT_MODE(v) (((v) & 0x1) << 24) | ||
| 300 | #define BFM_MSC_CMDAT_BOOT_MODE(v) BM_MSC_CMDAT_BOOT_MODE | ||
| 301 | #define BF_MSC_CMDAT_BOOT_MODE_V(e) BF_MSC_CMDAT_BOOT_MODE(BV_MSC_CMDAT_BOOT_MODE__##e) | ||
| 302 | #define BFM_MSC_CMDAT_BOOT_MODE_V(v) BM_MSC_CMDAT_BOOT_MODE | ||
| 303 | #define BP_MSC_CMDAT_SDIO_PRDT 17 | ||
| 304 | #define BM_MSC_CMDAT_SDIO_PRDT 0x20000 | ||
| 305 | #define BF_MSC_CMDAT_SDIO_PRDT(v) (((v) & 0x1) << 17) | ||
| 306 | #define BFM_MSC_CMDAT_SDIO_PRDT(v) BM_MSC_CMDAT_SDIO_PRDT | ||
| 307 | #define BF_MSC_CMDAT_SDIO_PRDT_V(e) BF_MSC_CMDAT_SDIO_PRDT(BV_MSC_CMDAT_SDIO_PRDT__##e) | ||
| 308 | #define BFM_MSC_CMDAT_SDIO_PRDT_V(v) BM_MSC_CMDAT_SDIO_PRDT | ||
| 309 | #define BP_MSC_CMDAT_AUTO_CMD12 16 | ||
| 310 | #define BM_MSC_CMDAT_AUTO_CMD12 0x10000 | ||
| 311 | #define BF_MSC_CMDAT_AUTO_CMD12(v) (((v) & 0x1) << 16) | ||
| 312 | #define BFM_MSC_CMDAT_AUTO_CMD12(v) BM_MSC_CMDAT_AUTO_CMD12 | ||
| 313 | #define BF_MSC_CMDAT_AUTO_CMD12_V(e) BF_MSC_CMDAT_AUTO_CMD12(BV_MSC_CMDAT_AUTO_CMD12__##e) | ||
| 314 | #define BFM_MSC_CMDAT_AUTO_CMD12_V(v) BM_MSC_CMDAT_AUTO_CMD12 | ||
| 315 | #define BP_MSC_CMDAT_IO_ABORT 11 | ||
| 316 | #define BM_MSC_CMDAT_IO_ABORT 0x800 | ||
| 317 | #define BF_MSC_CMDAT_IO_ABORT(v) (((v) & 0x1) << 11) | ||
| 318 | #define BFM_MSC_CMDAT_IO_ABORT(v) BM_MSC_CMDAT_IO_ABORT | ||
| 319 | #define BF_MSC_CMDAT_IO_ABORT_V(e) BF_MSC_CMDAT_IO_ABORT(BV_MSC_CMDAT_IO_ABORT__##e) | ||
| 320 | #define BFM_MSC_CMDAT_IO_ABORT_V(v) BM_MSC_CMDAT_IO_ABORT | ||
| 321 | #define BP_MSC_CMDAT_INIT 7 | ||
| 322 | #define BM_MSC_CMDAT_INIT 0x80 | ||
| 323 | #define BF_MSC_CMDAT_INIT(v) (((v) & 0x1) << 7) | ||
| 324 | #define BFM_MSC_CMDAT_INIT(v) BM_MSC_CMDAT_INIT | ||
| 325 | #define BF_MSC_CMDAT_INIT_V(e) BF_MSC_CMDAT_INIT(BV_MSC_CMDAT_INIT__##e) | ||
| 326 | #define BFM_MSC_CMDAT_INIT_V(v) BM_MSC_CMDAT_INIT | ||
| 327 | #define BP_MSC_CMDAT_BUSY 6 | ||
| 328 | #define BM_MSC_CMDAT_BUSY 0x40 | ||
| 329 | #define BF_MSC_CMDAT_BUSY(v) (((v) & 0x1) << 6) | ||
| 330 | #define BFM_MSC_CMDAT_BUSY(v) BM_MSC_CMDAT_BUSY | ||
| 331 | #define BF_MSC_CMDAT_BUSY_V(e) BF_MSC_CMDAT_BUSY(BV_MSC_CMDAT_BUSY__##e) | ||
| 332 | #define BFM_MSC_CMDAT_BUSY_V(v) BM_MSC_CMDAT_BUSY | ||
| 333 | #define BP_MSC_CMDAT_STREAM_BLOCK 5 | ||
| 334 | #define BM_MSC_CMDAT_STREAM_BLOCK 0x20 | ||
| 335 | #define BF_MSC_CMDAT_STREAM_BLOCK(v) (((v) & 0x1) << 5) | ||
| 336 | #define BFM_MSC_CMDAT_STREAM_BLOCK(v) BM_MSC_CMDAT_STREAM_BLOCK | ||
| 337 | #define BF_MSC_CMDAT_STREAM_BLOCK_V(e) BF_MSC_CMDAT_STREAM_BLOCK(BV_MSC_CMDAT_STREAM_BLOCK__##e) | ||
| 338 | #define BFM_MSC_CMDAT_STREAM_BLOCK_V(v) BM_MSC_CMDAT_STREAM_BLOCK | ||
| 339 | #define BP_MSC_CMDAT_WRITE_READ 4 | ||
| 340 | #define BM_MSC_CMDAT_WRITE_READ 0x10 | ||
| 341 | #define BF_MSC_CMDAT_WRITE_READ(v) (((v) & 0x1) << 4) | ||
| 342 | #define BFM_MSC_CMDAT_WRITE_READ(v) BM_MSC_CMDAT_WRITE_READ | ||
| 343 | #define BF_MSC_CMDAT_WRITE_READ_V(e) BF_MSC_CMDAT_WRITE_READ(BV_MSC_CMDAT_WRITE_READ__##e) | ||
| 344 | #define BFM_MSC_CMDAT_WRITE_READ_V(v) BM_MSC_CMDAT_WRITE_READ | ||
| 345 | #define BP_MSC_CMDAT_DATA_EN 3 | ||
| 346 | #define BM_MSC_CMDAT_DATA_EN 0x8 | ||
| 347 | #define BF_MSC_CMDAT_DATA_EN(v) (((v) & 0x1) << 3) | ||
| 348 | #define BFM_MSC_CMDAT_DATA_EN(v) BM_MSC_CMDAT_DATA_EN | ||
| 349 | #define BF_MSC_CMDAT_DATA_EN_V(e) BF_MSC_CMDAT_DATA_EN(BV_MSC_CMDAT_DATA_EN__##e) | ||
| 350 | #define BFM_MSC_CMDAT_DATA_EN_V(v) BM_MSC_CMDAT_DATA_EN | ||
| 351 | |||
| 352 | #define REG_MSC_IMASK(_n1) jz_reg(MSC_IMASK(_n1)) | ||
| 353 | #define JA_MSC_IMASK(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x24) | ||
| 354 | #define JT_MSC_IMASK(_n1) JIO_32_RW | ||
| 355 | #define JN_MSC_IMASK(_n1) MSC_IMASK | ||
| 356 | #define JI_MSC_IMASK(_n1) (_n1) | ||
| 357 | #define BP_MSC_IMASK_PINS 24 | ||
| 358 | #define BM_MSC_IMASK_PINS 0x1f000000 | ||
| 359 | #define BF_MSC_IMASK_PINS(v) (((v) & 0x1f) << 24) | ||
| 360 | #define BFM_MSC_IMASK_PINS(v) BM_MSC_IMASK_PINS | ||
| 361 | #define BF_MSC_IMASK_PINS_V(e) BF_MSC_IMASK_PINS(BV_MSC_IMASK_PINS__##e) | ||
| 362 | #define BFM_MSC_IMASK_PINS_V(v) BM_MSC_IMASK_PINS | ||
| 363 | #define BP_MSC_IMASK_DMA_DATA_DONE 31 | ||
| 364 | #define BM_MSC_IMASK_DMA_DATA_DONE 0x80000000 | ||
| 365 | #define BF_MSC_IMASK_DMA_DATA_DONE(v) (((v) & 0x1) << 31) | ||
| 366 | #define BFM_MSC_IMASK_DMA_DATA_DONE(v) BM_MSC_IMASK_DMA_DATA_DONE | ||
| 367 | #define BF_MSC_IMASK_DMA_DATA_DONE_V(e) BF_MSC_IMASK_DMA_DATA_DONE(BV_MSC_IMASK_DMA_DATA_DONE__##e) | ||
| 368 | #define BFM_MSC_IMASK_DMA_DATA_DONE_V(v) BM_MSC_IMASK_DMA_DATA_DONE | ||
| 369 | #define BP_MSC_IMASK_WR_ALL_DONE 23 | ||
| 370 | #define BM_MSC_IMASK_WR_ALL_DONE 0x800000 | ||
| 371 | #define BF_MSC_IMASK_WR_ALL_DONE(v) (((v) & 0x1) << 23) | ||
| 372 | #define BFM_MSC_IMASK_WR_ALL_DONE(v) BM_MSC_IMASK_WR_ALL_DONE | ||
| 373 | #define BF_MSC_IMASK_WR_ALL_DONE_V(e) BF_MSC_IMASK_WR_ALL_DONE(BV_MSC_IMASK_WR_ALL_DONE__##e) | ||
| 374 | #define BFM_MSC_IMASK_WR_ALL_DONE_V(v) BM_MSC_IMASK_WR_ALL_DONE | ||
| 375 | #define BP_MSC_IMASK_BCE 20 | ||
| 376 | #define BM_MSC_IMASK_BCE 0x100000 | ||
| 377 | #define BF_MSC_IMASK_BCE(v) (((v) & 0x1) << 20) | ||
| 378 | #define BFM_MSC_IMASK_BCE(v) BM_MSC_IMASK_BCE | ||
| 379 | #define BF_MSC_IMASK_BCE_V(e) BF_MSC_IMASK_BCE(BV_MSC_IMASK_BCE__##e) | ||
| 380 | #define BFM_MSC_IMASK_BCE_V(v) BM_MSC_IMASK_BCE | ||
| 381 | #define BP_MSC_IMASK_BDE 19 | ||
| 382 | #define BM_MSC_IMASK_BDE 0x80000 | ||
| 383 | #define BF_MSC_IMASK_BDE(v) (((v) & 0x1) << 19) | ||
| 384 | #define BFM_MSC_IMASK_BDE(v) BM_MSC_IMASK_BDE | ||
| 385 | #define BF_MSC_IMASK_BDE_V(e) BF_MSC_IMASK_BDE(BV_MSC_IMASK_BDE__##e) | ||
| 386 | #define BFM_MSC_IMASK_BDE_V(v) BM_MSC_IMASK_BDE | ||
| 387 | #define BP_MSC_IMASK_BAE 18 | ||
| 388 | #define BM_MSC_IMASK_BAE 0x40000 | ||
| 389 | #define BF_MSC_IMASK_BAE(v) (((v) & 0x1) << 18) | ||
| 390 | #define BFM_MSC_IMASK_BAE(v) BM_MSC_IMASK_BAE | ||
| 391 | #define BF_MSC_IMASK_BAE_V(e) BF_MSC_IMASK_BAE(BV_MSC_IMASK_BAE__##e) | ||
| 392 | #define BFM_MSC_IMASK_BAE_V(v) BM_MSC_IMASK_BAE | ||
| 393 | #define BP_MSC_IMASK_BAR 17 | ||
| 394 | #define BM_MSC_IMASK_BAR 0x20000 | ||
| 395 | #define BF_MSC_IMASK_BAR(v) (((v) & 0x1) << 17) | ||
| 396 | #define BFM_MSC_IMASK_BAR(v) BM_MSC_IMASK_BAR | ||
| 397 | #define BF_MSC_IMASK_BAR_V(e) BF_MSC_IMASK_BAR(BV_MSC_IMASK_BAR__##e) | ||
| 398 | #define BFM_MSC_IMASK_BAR_V(v) BM_MSC_IMASK_BAR | ||
| 399 | #define BP_MSC_IMASK_DMAEND 16 | ||
| 400 | #define BM_MSC_IMASK_DMAEND 0x10000 | ||
| 401 | #define BF_MSC_IMASK_DMAEND(v) (((v) & 0x1) << 16) | ||
| 402 | #define BFM_MSC_IMASK_DMAEND(v) BM_MSC_IMASK_DMAEND | ||
| 403 | #define BF_MSC_IMASK_DMAEND_V(e) BF_MSC_IMASK_DMAEND(BV_MSC_IMASK_DMAEND__##e) | ||
| 404 | #define BFM_MSC_IMASK_DMAEND_V(v) BM_MSC_IMASK_DMAEND | ||
| 405 | #define BP_MSC_IMASK_AUTO_CMD12_DONE 15 | ||
| 406 | #define BM_MSC_IMASK_AUTO_CMD12_DONE 0x8000 | ||
| 407 | #define BF_MSC_IMASK_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) | ||
| 408 | #define BFM_MSC_IMASK_AUTO_CMD12_DONE(v) BM_MSC_IMASK_AUTO_CMD12_DONE | ||
| 409 | #define BF_MSC_IMASK_AUTO_CMD12_DONE_V(e) BF_MSC_IMASK_AUTO_CMD12_DONE(BV_MSC_IMASK_AUTO_CMD12_DONE__##e) | ||
| 410 | #define BFM_MSC_IMASK_AUTO_CMD12_DONE_V(v) BM_MSC_IMASK_AUTO_CMD12_DONE | ||
| 411 | #define BP_MSC_IMASK_DATA_FIFO_FULL 14 | ||
| 412 | #define BM_MSC_IMASK_DATA_FIFO_FULL 0x4000 | ||
| 413 | #define BF_MSC_IMASK_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) | ||
| 414 | #define BFM_MSC_IMASK_DATA_FIFO_FULL(v) BM_MSC_IMASK_DATA_FIFO_FULL | ||
| 415 | #define BF_MSC_IMASK_DATA_FIFO_FULL_V(e) BF_MSC_IMASK_DATA_FIFO_FULL(BV_MSC_IMASK_DATA_FIFO_FULL__##e) | ||
| 416 | #define BFM_MSC_IMASK_DATA_FIFO_FULL_V(v) BM_MSC_IMASK_DATA_FIFO_FULL | ||
| 417 | #define BP_MSC_IMASK_DATA_FIFO_EMPTY 13 | ||
| 418 | #define BM_MSC_IMASK_DATA_FIFO_EMPTY 0x2000 | ||
| 419 | #define BF_MSC_IMASK_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) | ||
| 420 | #define BFM_MSC_IMASK_DATA_FIFO_EMPTY(v) BM_MSC_IMASK_DATA_FIFO_EMPTY | ||
| 421 | #define BF_MSC_IMASK_DATA_FIFO_EMPTY_V(e) BF_MSC_IMASK_DATA_FIFO_EMPTY(BV_MSC_IMASK_DATA_FIFO_EMPTY__##e) | ||
| 422 | #define BFM_MSC_IMASK_DATA_FIFO_EMPTY_V(v) BM_MSC_IMASK_DATA_FIFO_EMPTY | ||
| 423 | #define BP_MSC_IMASK_CRC_RES_ERROR 12 | ||
| 424 | #define BM_MSC_IMASK_CRC_RES_ERROR 0x1000 | ||
| 425 | #define BF_MSC_IMASK_CRC_RES_ERROR(v) (((v) & 0x1) << 12) | ||
| 426 | #define BFM_MSC_IMASK_CRC_RES_ERROR(v) BM_MSC_IMASK_CRC_RES_ERROR | ||
| 427 | #define BF_MSC_IMASK_CRC_RES_ERROR_V(e) BF_MSC_IMASK_CRC_RES_ERROR(BV_MSC_IMASK_CRC_RES_ERROR__##e) | ||
| 428 | #define BFM_MSC_IMASK_CRC_RES_ERROR_V(v) BM_MSC_IMASK_CRC_RES_ERROR | ||
| 429 | #define BP_MSC_IMASK_CRC_READ_ERROR 11 | ||
| 430 | #define BM_MSC_IMASK_CRC_READ_ERROR 0x800 | ||
| 431 | #define BF_MSC_IMASK_CRC_READ_ERROR(v) (((v) & 0x1) << 11) | ||
| 432 | #define BFM_MSC_IMASK_CRC_READ_ERROR(v) BM_MSC_IMASK_CRC_READ_ERROR | ||
| 433 | #define BF_MSC_IMASK_CRC_READ_ERROR_V(e) BF_MSC_IMASK_CRC_READ_ERROR(BV_MSC_IMASK_CRC_READ_ERROR__##e) | ||
| 434 | #define BFM_MSC_IMASK_CRC_READ_ERROR_V(v) BM_MSC_IMASK_CRC_READ_ERROR | ||
| 435 | #define BP_MSC_IMASK_CRC_WRITE_ERROR 10 | ||
| 436 | #define BM_MSC_IMASK_CRC_WRITE_ERROR 0x400 | ||
| 437 | #define BF_MSC_IMASK_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) | ||
| 438 | #define BFM_MSC_IMASK_CRC_WRITE_ERROR(v) BM_MSC_IMASK_CRC_WRITE_ERROR | ||
| 439 | #define BF_MSC_IMASK_CRC_WRITE_ERROR_V(e) BF_MSC_IMASK_CRC_WRITE_ERROR(BV_MSC_IMASK_CRC_WRITE_ERROR__##e) | ||
| 440 | #define BFM_MSC_IMASK_CRC_WRITE_ERROR_V(v) BM_MSC_IMASK_CRC_WRITE_ERROR | ||
| 441 | #define BP_MSC_IMASK_TIME_OUT_RES 9 | ||
| 442 | #define BM_MSC_IMASK_TIME_OUT_RES 0x200 | ||
| 443 | #define BF_MSC_IMASK_TIME_OUT_RES(v) (((v) & 0x1) << 9) | ||
| 444 | #define BFM_MSC_IMASK_TIME_OUT_RES(v) BM_MSC_IMASK_TIME_OUT_RES | ||
| 445 | #define BF_MSC_IMASK_TIME_OUT_RES_V(e) BF_MSC_IMASK_TIME_OUT_RES(BV_MSC_IMASK_TIME_OUT_RES__##e) | ||
| 446 | #define BFM_MSC_IMASK_TIME_OUT_RES_V(v) BM_MSC_IMASK_TIME_OUT_RES | ||
| 447 | #define BP_MSC_IMASK_TIME_OUT_READ 8 | ||
| 448 | #define BM_MSC_IMASK_TIME_OUT_READ 0x100 | ||
| 449 | #define BF_MSC_IMASK_TIME_OUT_READ(v) (((v) & 0x1) << 8) | ||
| 450 | #define BFM_MSC_IMASK_TIME_OUT_READ(v) BM_MSC_IMASK_TIME_OUT_READ | ||
| 451 | #define BF_MSC_IMASK_TIME_OUT_READ_V(e) BF_MSC_IMASK_TIME_OUT_READ(BV_MSC_IMASK_TIME_OUT_READ__##e) | ||
| 452 | #define BFM_MSC_IMASK_TIME_OUT_READ_V(v) BM_MSC_IMASK_TIME_OUT_READ | ||
| 453 | #define BP_MSC_IMASK_SDIO 7 | ||
| 454 | #define BM_MSC_IMASK_SDIO 0x80 | ||
| 455 | #define BF_MSC_IMASK_SDIO(v) (((v) & 0x1) << 7) | ||
| 456 | #define BFM_MSC_IMASK_SDIO(v) BM_MSC_IMASK_SDIO | ||
| 457 | #define BF_MSC_IMASK_SDIO_V(e) BF_MSC_IMASK_SDIO(BV_MSC_IMASK_SDIO__##e) | ||
| 458 | #define BFM_MSC_IMASK_SDIO_V(v) BM_MSC_IMASK_SDIO | ||
| 459 | #define BP_MSC_IMASK_TXFIFO_WR_REQ 6 | ||
| 460 | #define BM_MSC_IMASK_TXFIFO_WR_REQ 0x40 | ||
| 461 | #define BF_MSC_IMASK_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) | ||
| 462 | #define BFM_MSC_IMASK_TXFIFO_WR_REQ(v) BM_MSC_IMASK_TXFIFO_WR_REQ | ||
| 463 | #define BF_MSC_IMASK_TXFIFO_WR_REQ_V(e) BF_MSC_IMASK_TXFIFO_WR_REQ(BV_MSC_IMASK_TXFIFO_WR_REQ__##e) | ||
| 464 | #define BFM_MSC_IMASK_TXFIFO_WR_REQ_V(v) BM_MSC_IMASK_TXFIFO_WR_REQ | ||
| 465 | #define BP_MSC_IMASK_RXFIFO_RD_REQ 5 | ||
| 466 | #define BM_MSC_IMASK_RXFIFO_RD_REQ 0x20 | ||
| 467 | #define BF_MSC_IMASK_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) | ||
| 468 | #define BFM_MSC_IMASK_RXFIFO_RD_REQ(v) BM_MSC_IMASK_RXFIFO_RD_REQ | ||
| 469 | #define BF_MSC_IMASK_RXFIFO_RD_REQ_V(e) BF_MSC_IMASK_RXFIFO_RD_REQ(BV_MSC_IMASK_RXFIFO_RD_REQ__##e) | ||
| 470 | #define BFM_MSC_IMASK_RXFIFO_RD_REQ_V(v) BM_MSC_IMASK_RXFIFO_RD_REQ | ||
| 471 | #define BP_MSC_IMASK_END_CMD_RES 2 | ||
| 472 | #define BM_MSC_IMASK_END_CMD_RES 0x4 | ||
| 473 | #define BF_MSC_IMASK_END_CMD_RES(v) (((v) & 0x1) << 2) | ||
| 474 | #define BFM_MSC_IMASK_END_CMD_RES(v) BM_MSC_IMASK_END_CMD_RES | ||
| 475 | #define BF_MSC_IMASK_END_CMD_RES_V(e) BF_MSC_IMASK_END_CMD_RES(BV_MSC_IMASK_END_CMD_RES__##e) | ||
| 476 | #define BFM_MSC_IMASK_END_CMD_RES_V(v) BM_MSC_IMASK_END_CMD_RES | ||
| 477 | #define BP_MSC_IMASK_PROG_DONE 1 | ||
| 478 | #define BM_MSC_IMASK_PROG_DONE 0x2 | ||
| 479 | #define BF_MSC_IMASK_PROG_DONE(v) (((v) & 0x1) << 1) | ||
| 480 | #define BFM_MSC_IMASK_PROG_DONE(v) BM_MSC_IMASK_PROG_DONE | ||
| 481 | #define BF_MSC_IMASK_PROG_DONE_V(e) BF_MSC_IMASK_PROG_DONE(BV_MSC_IMASK_PROG_DONE__##e) | ||
| 482 | #define BFM_MSC_IMASK_PROG_DONE_V(v) BM_MSC_IMASK_PROG_DONE | ||
| 483 | #define BP_MSC_IMASK_DATA_TRAN_DONE 0 | ||
| 484 | #define BM_MSC_IMASK_DATA_TRAN_DONE 0x1 | ||
| 485 | #define BF_MSC_IMASK_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) | ||
| 486 | #define BFM_MSC_IMASK_DATA_TRAN_DONE(v) BM_MSC_IMASK_DATA_TRAN_DONE | ||
| 487 | #define BF_MSC_IMASK_DATA_TRAN_DONE_V(e) BF_MSC_IMASK_DATA_TRAN_DONE(BV_MSC_IMASK_DATA_TRAN_DONE__##e) | ||
| 488 | #define BFM_MSC_IMASK_DATA_TRAN_DONE_V(v) BM_MSC_IMASK_DATA_TRAN_DONE | ||
| 489 | |||
| 490 | #define REG_MSC_IFLAG(_n1) jz_reg(MSC_IFLAG(_n1)) | ||
| 491 | #define JA_MSC_IFLAG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x28) | ||
| 492 | #define JT_MSC_IFLAG(_n1) JIO_32_RW | ||
| 493 | #define JN_MSC_IFLAG(_n1) MSC_IFLAG | ||
| 494 | #define JI_MSC_IFLAG(_n1) (_n1) | ||
| 495 | #define BP_MSC_IFLAG_PINS 24 | ||
| 496 | #define BM_MSC_IFLAG_PINS 0x1f000000 | ||
| 497 | #define BF_MSC_IFLAG_PINS(v) (((v) & 0x1f) << 24) | ||
| 498 | #define BFM_MSC_IFLAG_PINS(v) BM_MSC_IFLAG_PINS | ||
| 499 | #define BF_MSC_IFLAG_PINS_V(e) BF_MSC_IFLAG_PINS(BV_MSC_IFLAG_PINS__##e) | ||
| 500 | #define BFM_MSC_IFLAG_PINS_V(v) BM_MSC_IFLAG_PINS | ||
| 501 | #define BP_MSC_IFLAG_DMA_DATA_DONE 31 | ||
| 502 | #define BM_MSC_IFLAG_DMA_DATA_DONE 0x80000000 | ||
| 503 | #define BF_MSC_IFLAG_DMA_DATA_DONE(v) (((v) & 0x1) << 31) | ||
| 504 | #define BFM_MSC_IFLAG_DMA_DATA_DONE(v) BM_MSC_IFLAG_DMA_DATA_DONE | ||
| 505 | #define BF_MSC_IFLAG_DMA_DATA_DONE_V(e) BF_MSC_IFLAG_DMA_DATA_DONE(BV_MSC_IFLAG_DMA_DATA_DONE__##e) | ||
| 506 | #define BFM_MSC_IFLAG_DMA_DATA_DONE_V(v) BM_MSC_IFLAG_DMA_DATA_DONE | ||
| 507 | #define BP_MSC_IFLAG_WR_ALL_DONE 23 | ||
| 508 | #define BM_MSC_IFLAG_WR_ALL_DONE 0x800000 | ||
| 509 | #define BF_MSC_IFLAG_WR_ALL_DONE(v) (((v) & 0x1) << 23) | ||
| 510 | #define BFM_MSC_IFLAG_WR_ALL_DONE(v) BM_MSC_IFLAG_WR_ALL_DONE | ||
| 511 | #define BF_MSC_IFLAG_WR_ALL_DONE_V(e) BF_MSC_IFLAG_WR_ALL_DONE(BV_MSC_IFLAG_WR_ALL_DONE__##e) | ||
| 512 | #define BFM_MSC_IFLAG_WR_ALL_DONE_V(v) BM_MSC_IFLAG_WR_ALL_DONE | ||
| 513 | #define BP_MSC_IFLAG_BCE 20 | ||
| 514 | #define BM_MSC_IFLAG_BCE 0x100000 | ||
| 515 | #define BF_MSC_IFLAG_BCE(v) (((v) & 0x1) << 20) | ||
| 516 | #define BFM_MSC_IFLAG_BCE(v) BM_MSC_IFLAG_BCE | ||
| 517 | #define BF_MSC_IFLAG_BCE_V(e) BF_MSC_IFLAG_BCE(BV_MSC_IFLAG_BCE__##e) | ||
| 518 | #define BFM_MSC_IFLAG_BCE_V(v) BM_MSC_IFLAG_BCE | ||
| 519 | #define BP_MSC_IFLAG_BDE 19 | ||
| 520 | #define BM_MSC_IFLAG_BDE 0x80000 | ||
| 521 | #define BF_MSC_IFLAG_BDE(v) (((v) & 0x1) << 19) | ||
| 522 | #define BFM_MSC_IFLAG_BDE(v) BM_MSC_IFLAG_BDE | ||
| 523 | #define BF_MSC_IFLAG_BDE_V(e) BF_MSC_IFLAG_BDE(BV_MSC_IFLAG_BDE__##e) | ||
| 524 | #define BFM_MSC_IFLAG_BDE_V(v) BM_MSC_IFLAG_BDE | ||
| 525 | #define BP_MSC_IFLAG_BAE 18 | ||
| 526 | #define BM_MSC_IFLAG_BAE 0x40000 | ||
| 527 | #define BF_MSC_IFLAG_BAE(v) (((v) & 0x1) << 18) | ||
| 528 | #define BFM_MSC_IFLAG_BAE(v) BM_MSC_IFLAG_BAE | ||
| 529 | #define BF_MSC_IFLAG_BAE_V(e) BF_MSC_IFLAG_BAE(BV_MSC_IFLAG_BAE__##e) | ||
| 530 | #define BFM_MSC_IFLAG_BAE_V(v) BM_MSC_IFLAG_BAE | ||
| 531 | #define BP_MSC_IFLAG_BAR 17 | ||
| 532 | #define BM_MSC_IFLAG_BAR 0x20000 | ||
| 533 | #define BF_MSC_IFLAG_BAR(v) (((v) & 0x1) << 17) | ||
| 534 | #define BFM_MSC_IFLAG_BAR(v) BM_MSC_IFLAG_BAR | ||
| 535 | #define BF_MSC_IFLAG_BAR_V(e) BF_MSC_IFLAG_BAR(BV_MSC_IFLAG_BAR__##e) | ||
| 536 | #define BFM_MSC_IFLAG_BAR_V(v) BM_MSC_IFLAG_BAR | ||
| 537 | #define BP_MSC_IFLAG_DMAEND 16 | ||
| 538 | #define BM_MSC_IFLAG_DMAEND 0x10000 | ||
| 539 | #define BF_MSC_IFLAG_DMAEND(v) (((v) & 0x1) << 16) | ||
| 540 | #define BFM_MSC_IFLAG_DMAEND(v) BM_MSC_IFLAG_DMAEND | ||
| 541 | #define BF_MSC_IFLAG_DMAEND_V(e) BF_MSC_IFLAG_DMAEND(BV_MSC_IFLAG_DMAEND__##e) | ||
| 542 | #define BFM_MSC_IFLAG_DMAEND_V(v) BM_MSC_IFLAG_DMAEND | ||
| 543 | #define BP_MSC_IFLAG_AUTO_CMD12_DONE 15 | ||
| 544 | #define BM_MSC_IFLAG_AUTO_CMD12_DONE 0x8000 | ||
| 545 | #define BF_MSC_IFLAG_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) | ||
| 546 | #define BFM_MSC_IFLAG_AUTO_CMD12_DONE(v) BM_MSC_IFLAG_AUTO_CMD12_DONE | ||
| 547 | #define BF_MSC_IFLAG_AUTO_CMD12_DONE_V(e) BF_MSC_IFLAG_AUTO_CMD12_DONE(BV_MSC_IFLAG_AUTO_CMD12_DONE__##e) | ||
| 548 | #define BFM_MSC_IFLAG_AUTO_CMD12_DONE_V(v) BM_MSC_IFLAG_AUTO_CMD12_DONE | ||
| 549 | #define BP_MSC_IFLAG_DATA_FIFO_FULL 14 | ||
| 550 | #define BM_MSC_IFLAG_DATA_FIFO_FULL 0x4000 | ||
| 551 | #define BF_MSC_IFLAG_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) | ||
| 552 | #define BFM_MSC_IFLAG_DATA_FIFO_FULL(v) BM_MSC_IFLAG_DATA_FIFO_FULL | ||
| 553 | #define BF_MSC_IFLAG_DATA_FIFO_FULL_V(e) BF_MSC_IFLAG_DATA_FIFO_FULL(BV_MSC_IFLAG_DATA_FIFO_FULL__##e) | ||
| 554 | #define BFM_MSC_IFLAG_DATA_FIFO_FULL_V(v) BM_MSC_IFLAG_DATA_FIFO_FULL | ||
| 555 | #define BP_MSC_IFLAG_DATA_FIFO_EMPTY 13 | ||
| 556 | #define BM_MSC_IFLAG_DATA_FIFO_EMPTY 0x2000 | ||
| 557 | #define BF_MSC_IFLAG_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) | ||
| 558 | #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY | ||
| 559 | #define BF_MSC_IFLAG_DATA_FIFO_EMPTY_V(e) BF_MSC_IFLAG_DATA_FIFO_EMPTY(BV_MSC_IFLAG_DATA_FIFO_EMPTY__##e) | ||
| 560 | #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY_V(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY | ||
| 561 | #define BP_MSC_IFLAG_CRC_RES_ERROR 12 | ||
| 562 | #define BM_MSC_IFLAG_CRC_RES_ERROR 0x1000 | ||
| 563 | #define BF_MSC_IFLAG_CRC_RES_ERROR(v) (((v) & 0x1) << 12) | ||
| 564 | #define BFM_MSC_IFLAG_CRC_RES_ERROR(v) BM_MSC_IFLAG_CRC_RES_ERROR | ||
| 565 | #define BF_MSC_IFLAG_CRC_RES_ERROR_V(e) BF_MSC_IFLAG_CRC_RES_ERROR(BV_MSC_IFLAG_CRC_RES_ERROR__##e) | ||
| 566 | #define BFM_MSC_IFLAG_CRC_RES_ERROR_V(v) BM_MSC_IFLAG_CRC_RES_ERROR | ||
| 567 | #define BP_MSC_IFLAG_CRC_READ_ERROR 11 | ||
| 568 | #define BM_MSC_IFLAG_CRC_READ_ERROR 0x800 | ||
| 569 | #define BF_MSC_IFLAG_CRC_READ_ERROR(v) (((v) & 0x1) << 11) | ||
| 570 | #define BFM_MSC_IFLAG_CRC_READ_ERROR(v) BM_MSC_IFLAG_CRC_READ_ERROR | ||
| 571 | #define BF_MSC_IFLAG_CRC_READ_ERROR_V(e) BF_MSC_IFLAG_CRC_READ_ERROR(BV_MSC_IFLAG_CRC_READ_ERROR__##e) | ||
| 572 | #define BFM_MSC_IFLAG_CRC_READ_ERROR_V(v) BM_MSC_IFLAG_CRC_READ_ERROR | ||
| 573 | #define BP_MSC_IFLAG_CRC_WRITE_ERROR 10 | ||
| 574 | #define BM_MSC_IFLAG_CRC_WRITE_ERROR 0x400 | ||
| 575 | #define BF_MSC_IFLAG_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) | ||
| 576 | #define BFM_MSC_IFLAG_CRC_WRITE_ERROR(v) BM_MSC_IFLAG_CRC_WRITE_ERROR | ||
| 577 | #define BF_MSC_IFLAG_CRC_WRITE_ERROR_V(e) BF_MSC_IFLAG_CRC_WRITE_ERROR(BV_MSC_IFLAG_CRC_WRITE_ERROR__##e) | ||
| 578 | #define BFM_MSC_IFLAG_CRC_WRITE_ERROR_V(v) BM_MSC_IFLAG_CRC_WRITE_ERROR | ||
| 579 | #define BP_MSC_IFLAG_TIME_OUT_RES 9 | ||
| 580 | #define BM_MSC_IFLAG_TIME_OUT_RES 0x200 | ||
| 581 | #define BF_MSC_IFLAG_TIME_OUT_RES(v) (((v) & 0x1) << 9) | ||
| 582 | #define BFM_MSC_IFLAG_TIME_OUT_RES(v) BM_MSC_IFLAG_TIME_OUT_RES | ||
| 583 | #define BF_MSC_IFLAG_TIME_OUT_RES_V(e) BF_MSC_IFLAG_TIME_OUT_RES(BV_MSC_IFLAG_TIME_OUT_RES__##e) | ||
| 584 | #define BFM_MSC_IFLAG_TIME_OUT_RES_V(v) BM_MSC_IFLAG_TIME_OUT_RES | ||
| 585 | #define BP_MSC_IFLAG_TIME_OUT_READ 8 | ||
| 586 | #define BM_MSC_IFLAG_TIME_OUT_READ 0x100 | ||
| 587 | #define BF_MSC_IFLAG_TIME_OUT_READ(v) (((v) & 0x1) << 8) | ||
| 588 | #define BFM_MSC_IFLAG_TIME_OUT_READ(v) BM_MSC_IFLAG_TIME_OUT_READ | ||
| 589 | #define BF_MSC_IFLAG_TIME_OUT_READ_V(e) BF_MSC_IFLAG_TIME_OUT_READ(BV_MSC_IFLAG_TIME_OUT_READ__##e) | ||
| 590 | #define BFM_MSC_IFLAG_TIME_OUT_READ_V(v) BM_MSC_IFLAG_TIME_OUT_READ | ||
| 591 | #define BP_MSC_IFLAG_SDIO 7 | ||
| 592 | #define BM_MSC_IFLAG_SDIO 0x80 | ||
| 593 | #define BF_MSC_IFLAG_SDIO(v) (((v) & 0x1) << 7) | ||
| 594 | #define BFM_MSC_IFLAG_SDIO(v) BM_MSC_IFLAG_SDIO | ||
| 595 | #define BF_MSC_IFLAG_SDIO_V(e) BF_MSC_IFLAG_SDIO(BV_MSC_IFLAG_SDIO__##e) | ||
| 596 | #define BFM_MSC_IFLAG_SDIO_V(v) BM_MSC_IFLAG_SDIO | ||
| 597 | #define BP_MSC_IFLAG_TXFIFO_WR_REQ 6 | ||
| 598 | #define BM_MSC_IFLAG_TXFIFO_WR_REQ 0x40 | ||
| 599 | #define BF_MSC_IFLAG_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) | ||
| 600 | #define BFM_MSC_IFLAG_TXFIFO_WR_REQ(v) BM_MSC_IFLAG_TXFIFO_WR_REQ | ||
| 601 | #define BF_MSC_IFLAG_TXFIFO_WR_REQ_V(e) BF_MSC_IFLAG_TXFIFO_WR_REQ(BV_MSC_IFLAG_TXFIFO_WR_REQ__##e) | ||
| 602 | #define BFM_MSC_IFLAG_TXFIFO_WR_REQ_V(v) BM_MSC_IFLAG_TXFIFO_WR_REQ | ||
| 603 | #define BP_MSC_IFLAG_RXFIFO_RD_REQ 5 | ||
| 604 | #define BM_MSC_IFLAG_RXFIFO_RD_REQ 0x20 | ||
| 605 | #define BF_MSC_IFLAG_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) | ||
| 606 | #define BFM_MSC_IFLAG_RXFIFO_RD_REQ(v) BM_MSC_IFLAG_RXFIFO_RD_REQ | ||
| 607 | #define BF_MSC_IFLAG_RXFIFO_RD_REQ_V(e) BF_MSC_IFLAG_RXFIFO_RD_REQ(BV_MSC_IFLAG_RXFIFO_RD_REQ__##e) | ||
| 608 | #define BFM_MSC_IFLAG_RXFIFO_RD_REQ_V(v) BM_MSC_IFLAG_RXFIFO_RD_REQ | ||
| 609 | #define BP_MSC_IFLAG_END_CMD_RES 2 | ||
| 610 | #define BM_MSC_IFLAG_END_CMD_RES 0x4 | ||
| 611 | #define BF_MSC_IFLAG_END_CMD_RES(v) (((v) & 0x1) << 2) | ||
| 612 | #define BFM_MSC_IFLAG_END_CMD_RES(v) BM_MSC_IFLAG_END_CMD_RES | ||
| 613 | #define BF_MSC_IFLAG_END_CMD_RES_V(e) BF_MSC_IFLAG_END_CMD_RES(BV_MSC_IFLAG_END_CMD_RES__##e) | ||
| 614 | #define BFM_MSC_IFLAG_END_CMD_RES_V(v) BM_MSC_IFLAG_END_CMD_RES | ||
| 615 | #define BP_MSC_IFLAG_PROG_DONE 1 | ||
| 616 | #define BM_MSC_IFLAG_PROG_DONE 0x2 | ||
| 617 | #define BF_MSC_IFLAG_PROG_DONE(v) (((v) & 0x1) << 1) | ||
| 618 | #define BFM_MSC_IFLAG_PROG_DONE(v) BM_MSC_IFLAG_PROG_DONE | ||
| 619 | #define BF_MSC_IFLAG_PROG_DONE_V(e) BF_MSC_IFLAG_PROG_DONE(BV_MSC_IFLAG_PROG_DONE__##e) | ||
| 620 | #define BFM_MSC_IFLAG_PROG_DONE_V(v) BM_MSC_IFLAG_PROG_DONE | ||
| 621 | #define BP_MSC_IFLAG_DATA_TRAN_DONE 0 | ||
| 622 | #define BM_MSC_IFLAG_DATA_TRAN_DONE 0x1 | ||
| 623 | #define BF_MSC_IFLAG_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) | ||
| 624 | #define BFM_MSC_IFLAG_DATA_TRAN_DONE(v) BM_MSC_IFLAG_DATA_TRAN_DONE | ||
| 625 | #define BF_MSC_IFLAG_DATA_TRAN_DONE_V(e) BF_MSC_IFLAG_DATA_TRAN_DONE(BV_MSC_IFLAG_DATA_TRAN_DONE__##e) | ||
| 626 | #define BFM_MSC_IFLAG_DATA_TRAN_DONE_V(v) BM_MSC_IFLAG_DATA_TRAN_DONE | ||
| 627 | |||
| 628 | #define REG_MSC_LPM(_n1) jz_reg(MSC_LPM(_n1)) | ||
| 629 | #define JA_MSC_LPM(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x40) | ||
| 630 | #define JT_MSC_LPM(_n1) JIO_32_RW | ||
| 631 | #define JN_MSC_LPM(_n1) MSC_LPM | ||
| 632 | #define JI_MSC_LPM(_n1) (_n1) | ||
| 633 | #define BP_MSC_LPM_DRV_SEL 30 | ||
| 634 | #define BM_MSC_LPM_DRV_SEL 0xc0000000 | ||
| 635 | #define BV_MSC_LPM_DRV_SEL__FALL_EDGE 0x0 | ||
| 636 | #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_1NS 0x1 | ||
| 637 | #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_QTR_PHASE 0x2 | ||
| 638 | #define BF_MSC_LPM_DRV_SEL(v) (((v) & 0x3) << 30) | ||
| 639 | #define BFM_MSC_LPM_DRV_SEL(v) BM_MSC_LPM_DRV_SEL | ||
| 640 | #define BF_MSC_LPM_DRV_SEL_V(e) BF_MSC_LPM_DRV_SEL(BV_MSC_LPM_DRV_SEL__##e) | ||
| 641 | #define BFM_MSC_LPM_DRV_SEL_V(v) BM_MSC_LPM_DRV_SEL | ||
| 642 | #define BP_MSC_LPM_SMP_SEL 28 | ||
| 643 | #define BM_MSC_LPM_SMP_SEL 0x30000000 | ||
| 644 | #define BV_MSC_LPM_SMP_SEL__RISE_EDGE 0x0 | ||
| 645 | #define BV_MSC_LPM_SMP_SEL__RISE_EDGE_DELAYED 0x1 | ||
| 646 | #define BF_MSC_LPM_SMP_SEL(v) (((v) & 0x3) << 28) | ||
| 647 | #define BFM_MSC_LPM_SMP_SEL(v) BM_MSC_LPM_SMP_SEL | ||
| 648 | #define BF_MSC_LPM_SMP_SEL_V(e) BF_MSC_LPM_SMP_SEL(BV_MSC_LPM_SMP_SEL__##e) | ||
| 649 | #define BFM_MSC_LPM_SMP_SEL_V(v) BM_MSC_LPM_SMP_SEL | ||
| 650 | #define BP_MSC_LPM_ENABLE 0 | ||
| 651 | #define BM_MSC_LPM_ENABLE 0x1 | ||
| 652 | #define BF_MSC_LPM_ENABLE(v) (((v) & 0x1) << 0) | ||
| 653 | #define BFM_MSC_LPM_ENABLE(v) BM_MSC_LPM_ENABLE | ||
| 654 | #define BF_MSC_LPM_ENABLE_V(e) BF_MSC_LPM_ENABLE(BV_MSC_LPM_ENABLE__##e) | ||
| 655 | #define BFM_MSC_LPM_ENABLE_V(v) BM_MSC_LPM_ENABLE | ||
| 656 | |||
| 657 | #define REG_MSC_DMAC(_n1) jz_reg(MSC_DMAC(_n1)) | ||
| 658 | #define JA_MSC_DMAC(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x44) | ||
| 659 | #define JT_MSC_DMAC(_n1) JIO_32_RW | ||
| 660 | #define JN_MSC_DMAC(_n1) MSC_DMAC | ||
| 661 | #define JI_MSC_DMAC(_n1) (_n1) | ||
| 662 | #define BP_MSC_DMAC_ADDR_OFFSET 5 | ||
| 663 | #define BM_MSC_DMAC_ADDR_OFFSET 0x60 | ||
| 664 | #define BF_MSC_DMAC_ADDR_OFFSET(v) (((v) & 0x3) << 5) | ||
| 665 | #define BFM_MSC_DMAC_ADDR_OFFSET(v) BM_MSC_DMAC_ADDR_OFFSET | ||
| 666 | #define BF_MSC_DMAC_ADDR_OFFSET_V(e) BF_MSC_DMAC_ADDR_OFFSET(BV_MSC_DMAC_ADDR_OFFSET__##e) | ||
| 667 | #define BFM_MSC_DMAC_ADDR_OFFSET_V(v) BM_MSC_DMAC_ADDR_OFFSET | ||
| 668 | #define BP_MSC_DMAC_INCR 2 | ||
| 669 | #define BM_MSC_DMAC_INCR 0xc | ||
| 670 | #define BF_MSC_DMAC_INCR(v) (((v) & 0x3) << 2) | ||
| 671 | #define BFM_MSC_DMAC_INCR(v) BM_MSC_DMAC_INCR | ||
| 672 | #define BF_MSC_DMAC_INCR_V(e) BF_MSC_DMAC_INCR(BV_MSC_DMAC_INCR__##e) | ||
| 673 | #define BFM_MSC_DMAC_INCR_V(v) BM_MSC_DMAC_INCR | ||
| 674 | #define BP_MSC_DMAC_MODE_SEL 7 | ||
| 675 | #define BM_MSC_DMAC_MODE_SEL 0x80 | ||
| 676 | #define BF_MSC_DMAC_MODE_SEL(v) (((v) & 0x1) << 7) | ||
| 677 | #define BFM_MSC_DMAC_MODE_SEL(v) BM_MSC_DMAC_MODE_SEL | ||
| 678 | #define BF_MSC_DMAC_MODE_SEL_V(e) BF_MSC_DMAC_MODE_SEL(BV_MSC_DMAC_MODE_SEL__##e) | ||
| 679 | #define BFM_MSC_DMAC_MODE_SEL_V(v) BM_MSC_DMAC_MODE_SEL | ||
| 680 | #define BP_MSC_DMAC_ALIGN_EN 4 | ||
| 681 | #define BM_MSC_DMAC_ALIGN_EN 0x10 | ||
| 682 | #define BF_MSC_DMAC_ALIGN_EN(v) (((v) & 0x1) << 4) | ||
| 683 | #define BFM_MSC_DMAC_ALIGN_EN(v) BM_MSC_DMAC_ALIGN_EN | ||
| 684 | #define BF_MSC_DMAC_ALIGN_EN_V(e) BF_MSC_DMAC_ALIGN_EN(BV_MSC_DMAC_ALIGN_EN__##e) | ||
| 685 | #define BFM_MSC_DMAC_ALIGN_EN_V(v) BM_MSC_DMAC_ALIGN_EN | ||
| 686 | #define BP_MSC_DMAC_DMASEL 1 | ||
| 687 | #define BM_MSC_DMAC_DMASEL 0x2 | ||
| 688 | #define BF_MSC_DMAC_DMASEL(v) (((v) & 0x1) << 1) | ||
| 689 | #define BFM_MSC_DMAC_DMASEL(v) BM_MSC_DMAC_DMASEL | ||
| 690 | #define BF_MSC_DMAC_DMASEL_V(e) BF_MSC_DMAC_DMASEL(BV_MSC_DMAC_DMASEL__##e) | ||
| 691 | #define BFM_MSC_DMAC_DMASEL_V(v) BM_MSC_DMAC_DMASEL | ||
| 692 | #define BP_MSC_DMAC_ENABLE 0 | ||
| 693 | #define BM_MSC_DMAC_ENABLE 0x1 | ||
| 694 | #define BF_MSC_DMAC_ENABLE(v) (((v) & 0x1) << 0) | ||
| 695 | #define BFM_MSC_DMAC_ENABLE(v) BM_MSC_DMAC_ENABLE | ||
| 696 | #define BF_MSC_DMAC_ENABLE_V(e) BF_MSC_DMAC_ENABLE(BV_MSC_DMAC_ENABLE__##e) | ||
| 697 | #define BFM_MSC_DMAC_ENABLE_V(v) BM_MSC_DMAC_ENABLE | ||
| 698 | |||
| 699 | #define REG_MSC_CTRL2(_n1) jz_reg(MSC_CTRL2(_n1)) | ||
| 700 | #define JA_MSC_CTRL2(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x58) | ||
| 701 | #define JT_MSC_CTRL2(_n1) JIO_32_RW | ||
| 702 | #define JN_MSC_CTRL2(_n1) MSC_CTRL2 | ||
| 703 | #define JI_MSC_CTRL2(_n1) (_n1) | ||
| 704 | #define BP_MSC_CTRL2_PIN_INT_POLARITY 24 | ||
| 705 | #define BM_MSC_CTRL2_PIN_INT_POLARITY 0x1f000000 | ||
| 706 | #define BF_MSC_CTRL2_PIN_INT_POLARITY(v) (((v) & 0x1f) << 24) | ||
| 707 | #define BFM_MSC_CTRL2_PIN_INT_POLARITY(v) BM_MSC_CTRL2_PIN_INT_POLARITY | ||
| 708 | #define BF_MSC_CTRL2_PIN_INT_POLARITY_V(e) BF_MSC_CTRL2_PIN_INT_POLARITY(BV_MSC_CTRL2_PIN_INT_POLARITY__##e) | ||
| 709 | #define BFM_MSC_CTRL2_PIN_INT_POLARITY_V(v) BM_MSC_CTRL2_PIN_INT_POLARITY | ||
| 710 | #define BP_MSC_CTRL2_SPEED 0 | ||
| 711 | #define BM_MSC_CTRL2_SPEED 0x7 | ||
| 712 | #define BV_MSC_CTRL2_SPEED__DEFAULT 0x0 | ||
| 713 | #define BV_MSC_CTRL2_SPEED__HIGHSPEED 0x1 | ||
| 714 | #define BV_MSC_CTRL2_SPEED__SDR12 0x2 | ||
| 715 | #define BV_MSC_CTRL2_SPEED__SDR25 0x3 | ||
| 716 | #define BV_MSC_CTRL2_SPEED__SDR50 0x4 | ||
| 717 | #define BF_MSC_CTRL2_SPEED(v) (((v) & 0x7) << 0) | ||
| 718 | #define BFM_MSC_CTRL2_SPEED(v) BM_MSC_CTRL2_SPEED | ||
| 719 | #define BF_MSC_CTRL2_SPEED_V(e) BF_MSC_CTRL2_SPEED(BV_MSC_CTRL2_SPEED__##e) | ||
| 720 | #define BFM_MSC_CTRL2_SPEED_V(v) BM_MSC_CTRL2_SPEED | ||
| 721 | #define BP_MSC_CTRL2_STPRM 4 | ||
| 722 | #define BM_MSC_CTRL2_STPRM 0x10 | ||
| 723 | #define BF_MSC_CTRL2_STPRM(v) (((v) & 0x1) << 4) | ||
| 724 | #define BFM_MSC_CTRL2_STPRM(v) BM_MSC_CTRL2_STPRM | ||
| 725 | #define BF_MSC_CTRL2_STPRM_V(e) BF_MSC_CTRL2_STPRM(BV_MSC_CTRL2_STPRM__##e) | ||
| 726 | #define BFM_MSC_CTRL2_STPRM_V(v) BM_MSC_CTRL2_STPRM | ||
| 727 | |||
| 728 | #define REG_MSC_CLKRT(_n1) jz_reg(MSC_CLKRT(_n1)) | ||
| 729 | #define JA_MSC_CLKRT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x8) | ||
| 730 | #define JT_MSC_CLKRT(_n1) JIO_32_RW | ||
| 731 | #define JN_MSC_CLKRT(_n1) MSC_CLKRT | ||
| 732 | #define JI_MSC_CLKRT(_n1) (_n1) | ||
| 733 | |||
| 734 | #define REG_MSC_RESTO(_n1) jz_reg(MSC_RESTO(_n1)) | ||
| 735 | #define JA_MSC_RESTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x10) | ||
| 736 | #define JT_MSC_RESTO(_n1) JIO_32_RW | ||
| 737 | #define JN_MSC_RESTO(_n1) MSC_RESTO | ||
| 738 | #define JI_MSC_RESTO(_n1) (_n1) | ||
| 739 | |||
| 740 | #define REG_MSC_RDTO(_n1) jz_reg(MSC_RDTO(_n1)) | ||
| 741 | #define JA_MSC_RDTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x14) | ||
| 742 | #define JT_MSC_RDTO(_n1) JIO_32_RW | ||
| 743 | #define JN_MSC_RDTO(_n1) MSC_RDTO | ||
| 744 | #define JI_MSC_RDTO(_n1) (_n1) | ||
| 745 | |||
| 746 | #define REG_MSC_BLKLEN(_n1) jz_reg(MSC_BLKLEN(_n1)) | ||
| 747 | #define JA_MSC_BLKLEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x18) | ||
| 748 | #define JT_MSC_BLKLEN(_n1) JIO_32_RW | ||
| 749 | #define JN_MSC_BLKLEN(_n1) MSC_BLKLEN | ||
| 750 | #define JI_MSC_BLKLEN(_n1) (_n1) | ||
| 751 | |||
| 752 | #define REG_MSC_NOB(_n1) jz_reg(MSC_NOB(_n1)) | ||
| 753 | #define JA_MSC_NOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x1c) | ||
| 754 | #define JT_MSC_NOB(_n1) JIO_32_RW | ||
| 755 | #define JN_MSC_NOB(_n1) MSC_NOB | ||
| 756 | #define JI_MSC_NOB(_n1) (_n1) | ||
| 757 | |||
| 758 | #define REG_MSC_SNOB(_n1) jz_reg(MSC_SNOB(_n1)) | ||
| 759 | #define JA_MSC_SNOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x20) | ||
| 760 | #define JT_MSC_SNOB(_n1) JIO_32_RW | ||
| 761 | #define JN_MSC_SNOB(_n1) MSC_SNOB | ||
| 762 | #define JI_MSC_SNOB(_n1) (_n1) | ||
| 763 | |||
| 764 | #define REG_MSC_CMD(_n1) jz_reg(MSC_CMD(_n1)) | ||
| 765 | #define JA_MSC_CMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x2c) | ||
| 766 | #define JT_MSC_CMD(_n1) JIO_32_RW | ||
| 767 | #define JN_MSC_CMD(_n1) MSC_CMD | ||
| 768 | #define JI_MSC_CMD(_n1) (_n1) | ||
| 769 | |||
| 770 | #define REG_MSC_ARG(_n1) jz_reg(MSC_ARG(_n1)) | ||
| 771 | #define JA_MSC_ARG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x30) | ||
| 772 | #define JT_MSC_ARG(_n1) JIO_32_RW | ||
| 773 | #define JN_MSC_ARG(_n1) MSC_ARG | ||
| 774 | #define JI_MSC_ARG(_n1) (_n1) | ||
| 775 | |||
| 776 | #define REG_MSC_RES(_n1) jz_reg(MSC_RES(_n1)) | ||
| 777 | #define JA_MSC_RES(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x34) | ||
| 778 | #define JT_MSC_RES(_n1) JIO_32_RW | ||
| 779 | #define JN_MSC_RES(_n1) MSC_RES | ||
| 780 | #define JI_MSC_RES(_n1) (_n1) | ||
| 781 | |||
| 782 | #define REG_MSC_RXFIFO(_n1) jz_reg(MSC_RXFIFO(_n1)) | ||
| 783 | #define JA_MSC_RXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x38) | ||
| 784 | #define JT_MSC_RXFIFO(_n1) JIO_32_RW | ||
| 785 | #define JN_MSC_RXFIFO(_n1) MSC_RXFIFO | ||
| 786 | #define JI_MSC_RXFIFO(_n1) (_n1) | ||
| 787 | |||
| 788 | #define REG_MSC_TXFIFO(_n1) jz_reg(MSC_TXFIFO(_n1)) | ||
| 789 | #define JA_MSC_TXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x3c) | ||
| 790 | #define JT_MSC_TXFIFO(_n1) JIO_32_RW | ||
| 791 | #define JN_MSC_TXFIFO(_n1) MSC_TXFIFO | ||
| 792 | #define JI_MSC_TXFIFO(_n1) (_n1) | ||
| 793 | |||
| 794 | #define REG_MSC_DMANDA(_n1) jz_reg(MSC_DMANDA(_n1)) | ||
| 795 | #define JA_MSC_DMANDA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x48) | ||
| 796 | #define JT_MSC_DMANDA(_n1) JIO_32_RW | ||
| 797 | #define JN_MSC_DMANDA(_n1) MSC_DMANDA | ||
| 798 | #define JI_MSC_DMANDA(_n1) (_n1) | ||
| 799 | |||
| 800 | #define REG_MSC_DMADA(_n1) jz_reg(MSC_DMADA(_n1)) | ||
| 801 | #define JA_MSC_DMADA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4c) | ||
| 802 | #define JT_MSC_DMADA(_n1) JIO_32_RW | ||
| 803 | #define JN_MSC_DMADA(_n1) MSC_DMADA | ||
| 804 | #define JI_MSC_DMADA(_n1) (_n1) | ||
| 805 | |||
| 806 | #define REG_MSC_DMALEN(_n1) jz_reg(MSC_DMALEN(_n1)) | ||
| 807 | #define JA_MSC_DMALEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x50) | ||
| 808 | #define JT_MSC_DMALEN(_n1) JIO_32_RW | ||
| 809 | #define JN_MSC_DMALEN(_n1) MSC_DMALEN | ||
| 810 | #define JI_MSC_DMALEN(_n1) (_n1) | ||
| 811 | |||
| 812 | #define REG_MSC_DMACMD(_n1) jz_reg(MSC_DMACMD(_n1)) | ||
| 813 | #define JA_MSC_DMACMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x54) | ||
| 814 | #define JT_MSC_DMACMD(_n1) JIO_32_RW | ||
| 815 | #define JN_MSC_DMACMD(_n1) MSC_DMACMD | ||
| 816 | #define JI_MSC_DMACMD(_n1) (_n1) | ||
| 817 | |||
| 818 | #define REG_MSC_RTCNT(_n1) jz_reg(MSC_RTCNT(_n1)) | ||
| 819 | #define JA_MSC_RTCNT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x5c) | ||
| 820 | #define JT_MSC_RTCNT(_n1) JIO_32_RW | ||
| 821 | #define JN_MSC_RTCNT(_n1) MSC_RTCNT | ||
| 822 | #define JI_MSC_RTCNT(_n1) (_n1) | ||
| 823 | |||
| 824 | #endif /* __HEADERGEN_MSC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ost.h b/firmware/target/mips/ingenic_x1000/x1000/ost.h new file mode 100644 index 0000000000..8f2619e0e7 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ost.h | |||
| @@ -0,0 +1,141 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_OST_H__ | ||
| 25 | #define __HEADERGEN_OST_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_OST_CTRL jz_reg(OST_CTRL) | ||
| 30 | #define JA_OST_CTRL (0xb2000000 + 0x0) | ||
| 31 | #define JT_OST_CTRL JIO_32_RW | ||
| 32 | #define JN_OST_CTRL OST_CTRL | ||
| 33 | #define JI_OST_CTRL | ||
| 34 | #define BP_OST_CTRL_PRESCALE2 3 | ||
| 35 | #define BM_OST_CTRL_PRESCALE2 0x38 | ||
| 36 | #define BV_OST_CTRL_PRESCALE2__BY_1 0x0 | ||
| 37 | #define BV_OST_CTRL_PRESCALE2__BY_4 0x1 | ||
| 38 | #define BV_OST_CTRL_PRESCALE2__BY_16 0x2 | ||
| 39 | #define BF_OST_CTRL_PRESCALE2(v) (((v) & 0x7) << 3) | ||
| 40 | #define BFM_OST_CTRL_PRESCALE2(v) BM_OST_CTRL_PRESCALE2 | ||
| 41 | #define BF_OST_CTRL_PRESCALE2_V(e) BF_OST_CTRL_PRESCALE2(BV_OST_CTRL_PRESCALE2__##e) | ||
| 42 | #define BFM_OST_CTRL_PRESCALE2_V(v) BM_OST_CTRL_PRESCALE2 | ||
| 43 | #define BP_OST_CTRL_PRESCALE1 0 | ||
| 44 | #define BM_OST_CTRL_PRESCALE1 0x7 | ||
| 45 | #define BV_OST_CTRL_PRESCALE1__BY_1 0x0 | ||
| 46 | #define BV_OST_CTRL_PRESCALE1__BY_4 0x1 | ||
| 47 | #define BV_OST_CTRL_PRESCALE1__BY_16 0x2 | ||
| 48 | #define BF_OST_CTRL_PRESCALE1(v) (((v) & 0x7) << 0) | ||
| 49 | #define BFM_OST_CTRL_PRESCALE1(v) BM_OST_CTRL_PRESCALE1 | ||
| 50 | #define BF_OST_CTRL_PRESCALE1_V(e) BF_OST_CTRL_PRESCALE1(BV_OST_CTRL_PRESCALE1__##e) | ||
| 51 | #define BFM_OST_CTRL_PRESCALE1_V(v) BM_OST_CTRL_PRESCALE1 | ||
| 52 | |||
| 53 | #define REG_OST_ENABLE jz_reg(OST_ENABLE) | ||
| 54 | #define JA_OST_ENABLE (0xb2000000 + 0x4) | ||
| 55 | #define JT_OST_ENABLE JIO_32_RW | ||
| 56 | #define JN_OST_ENABLE OST_ENABLE | ||
| 57 | #define JI_OST_ENABLE | ||
| 58 | #define REG_OST_ENABLE_SET jz_reg(OST_ENABLE_SET) | ||
| 59 | #define JA_OST_ENABLE_SET (JA_OST_ENABLE + 0x30) | ||
| 60 | #define JT_OST_ENABLE_SET JIO_32_WO | ||
| 61 | #define JN_OST_ENABLE_SET OST_ENABLE | ||
| 62 | #define JI_OST_ENABLE_SET | ||
| 63 | #define REG_OST_ENABLE_CLR jz_reg(OST_ENABLE_CLR) | ||
| 64 | #define JA_OST_ENABLE_CLR (JA_OST_ENABLE + 0x34) | ||
| 65 | #define JT_OST_ENABLE_CLR JIO_32_WO | ||
| 66 | #define JN_OST_ENABLE_CLR OST_ENABLE | ||
| 67 | #define JI_OST_ENABLE_CLR | ||
| 68 | #define BP_OST_ENABLE_OST1 0 | ||
| 69 | #define BM_OST_ENABLE_OST1 0x1 | ||
| 70 | #define BF_OST_ENABLE_OST1(v) (((v) & 0x1) << 0) | ||
| 71 | #define BFM_OST_ENABLE_OST1(v) BM_OST_ENABLE_OST1 | ||
| 72 | #define BF_OST_ENABLE_OST1_V(e) BF_OST_ENABLE_OST1(BV_OST_ENABLE_OST1__##e) | ||
| 73 | #define BFM_OST_ENABLE_OST1_V(v) BM_OST_ENABLE_OST1 | ||
| 74 | #define BP_OST_ENABLE_OST2 1 | ||
| 75 | #define BM_OST_ENABLE_OST2 0x2 | ||
| 76 | #define BF_OST_ENABLE_OST2(v) (((v) & 0x1) << 1) | ||
| 77 | #define BFM_OST_ENABLE_OST2(v) BM_OST_ENABLE_OST2 | ||
| 78 | #define BF_OST_ENABLE_OST2_V(e) BF_OST_ENABLE_OST2(BV_OST_ENABLE_OST2__##e) | ||
| 79 | #define BFM_OST_ENABLE_OST2_V(v) BM_OST_ENABLE_OST2 | ||
| 80 | |||
| 81 | #define REG_OST_CLEAR jz_reg(OST_CLEAR) | ||
| 82 | #define JA_OST_CLEAR (0xb2000000 + 0x8) | ||
| 83 | #define JT_OST_CLEAR JIO_32_RW | ||
| 84 | #define JN_OST_CLEAR OST_CLEAR | ||
| 85 | #define JI_OST_CLEAR | ||
| 86 | #define BP_OST_CLEAR_OST1 0 | ||
| 87 | #define BM_OST_CLEAR_OST1 0x1 | ||
| 88 | #define BF_OST_CLEAR_OST1(v) (((v) & 0x1) << 0) | ||
| 89 | #define BFM_OST_CLEAR_OST1(v) BM_OST_CLEAR_OST1 | ||
| 90 | #define BF_OST_CLEAR_OST1_V(e) BF_OST_CLEAR_OST1(BV_OST_CLEAR_OST1__##e) | ||
| 91 | #define BFM_OST_CLEAR_OST1_V(v) BM_OST_CLEAR_OST1 | ||
| 92 | #define BP_OST_CLEAR_OST2 1 | ||
| 93 | #define BM_OST_CLEAR_OST2 0x2 | ||
| 94 | #define BF_OST_CLEAR_OST2(v) (((v) & 0x1) << 1) | ||
| 95 | #define BFM_OST_CLEAR_OST2(v) BM_OST_CLEAR_OST2 | ||
| 96 | #define BF_OST_CLEAR_OST2_V(e) BF_OST_CLEAR_OST2(BV_OST_CLEAR_OST2__##e) | ||
| 97 | #define BFM_OST_CLEAR_OST2_V(v) BM_OST_CLEAR_OST2 | ||
| 98 | |||
| 99 | #define REG_OST_1FLG jz_reg(OST_1FLG) | ||
| 100 | #define JA_OST_1FLG (0xb2000000 + 0xc) | ||
| 101 | #define JT_OST_1FLG JIO_32_RW | ||
| 102 | #define JN_OST_1FLG OST_1FLG | ||
| 103 | #define JI_OST_1FLG | ||
| 104 | |||
| 105 | #define REG_OST_1MSK jz_reg(OST_1MSK) | ||
| 106 | #define JA_OST_1MSK (0xb2000000 + 0x10) | ||
| 107 | #define JT_OST_1MSK JIO_32_RW | ||
| 108 | #define JN_OST_1MSK OST_1MSK | ||
| 109 | #define JI_OST_1MSK | ||
| 110 | |||
| 111 | #define REG_OST_1DFR jz_reg(OST_1DFR) | ||
| 112 | #define JA_OST_1DFR (0xb2000000 + 0x14) | ||
| 113 | #define JT_OST_1DFR JIO_32_RW | ||
| 114 | #define JN_OST_1DFR OST_1DFR | ||
| 115 | #define JI_OST_1DFR | ||
| 116 | |||
| 117 | #define REG_OST_1CNT jz_reg(OST_1CNT) | ||
| 118 | #define JA_OST_1CNT (0xb2000000 + 0x18) | ||
| 119 | #define JT_OST_1CNT JIO_32_RW | ||
| 120 | #define JN_OST_1CNT OST_1CNT | ||
| 121 | #define JI_OST_1CNT | ||
| 122 | |||
| 123 | #define REG_OST_2CNTH jz_reg(OST_2CNTH) | ||
| 124 | #define JA_OST_2CNTH (0xb2000000 + 0x1c) | ||
| 125 | #define JT_OST_2CNTH JIO_32_RW | ||
| 126 | #define JN_OST_2CNTH OST_2CNTH | ||
| 127 | #define JI_OST_2CNTH | ||
| 128 | |||
| 129 | #define REG_OST_2CNTL jz_reg(OST_2CNTL) | ||
| 130 | #define JA_OST_2CNTL (0xb2000000 + 0x20) | ||
| 131 | #define JT_OST_2CNTL JIO_32_RW | ||
| 132 | #define JN_OST_2CNTL OST_2CNTL | ||
| 133 | #define JI_OST_2CNTL | ||
| 134 | |||
| 135 | #define REG_OST_2CNTHB jz_reg(OST_2CNTHB) | ||
| 136 | #define JA_OST_2CNTHB (0xb2000000 + 0x24) | ||
| 137 | #define JT_OST_2CNTHB JIO_32_RW | ||
| 138 | #define JN_OST_2CNTHB OST_2CNTHB | ||
| 139 | #define JI_OST_2CNTHB | ||
| 140 | |||
| 141 | #endif /* __HEADERGEN_OST_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/rtc.h b/firmware/target/mips/ingenic_x1000/x1000/rtc.h new file mode 100644 index 0000000000..38f82e7d0d --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/rtc.h | |||
| @@ -0,0 +1,221 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_RTC_H__ | ||
| 25 | #define __HEADERGEN_RTC_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_RTC_CR jz_reg(RTC_CR) | ||
| 30 | #define JA_RTC_CR (0xb0003000 + 0x0) | ||
| 31 | #define JT_RTC_CR JIO_32_RW | ||
| 32 | #define JN_RTC_CR RTC_CR | ||
| 33 | #define JI_RTC_CR | ||
| 34 | #define BP_RTC_CR_WRDY 7 | ||
| 35 | #define BM_RTC_CR_WRDY 0x80 | ||
| 36 | #define BF_RTC_CR_WRDY(v) (((v) & 0x1) << 7) | ||
| 37 | #define BFM_RTC_CR_WRDY(v) BM_RTC_CR_WRDY | ||
| 38 | #define BF_RTC_CR_WRDY_V(e) BF_RTC_CR_WRDY(BV_RTC_CR_WRDY__##e) | ||
| 39 | #define BFM_RTC_CR_WRDY_V(v) BM_RTC_CR_WRDY | ||
| 40 | #define BP_RTC_CR_1HZ 6 | ||
| 41 | #define BM_RTC_CR_1HZ 0x40 | ||
| 42 | #define BF_RTC_CR_1HZ(v) (((v) & 0x1) << 6) | ||
| 43 | #define BFM_RTC_CR_1HZ(v) BM_RTC_CR_1HZ | ||
| 44 | #define BF_RTC_CR_1HZ_V(e) BF_RTC_CR_1HZ(BV_RTC_CR_1HZ__##e) | ||
| 45 | #define BFM_RTC_CR_1HZ_V(v) BM_RTC_CR_1HZ | ||
| 46 | #define BP_RTC_CR_1HZIE 5 | ||
| 47 | #define BM_RTC_CR_1HZIE 0x20 | ||
| 48 | #define BF_RTC_CR_1HZIE(v) (((v) & 0x1) << 5) | ||
| 49 | #define BFM_RTC_CR_1HZIE(v) BM_RTC_CR_1HZIE | ||
| 50 | #define BF_RTC_CR_1HZIE_V(e) BF_RTC_CR_1HZIE(BV_RTC_CR_1HZIE__##e) | ||
| 51 | #define BFM_RTC_CR_1HZIE_V(v) BM_RTC_CR_1HZIE | ||
| 52 | #define BP_RTC_CR_AF 4 | ||
| 53 | #define BM_RTC_CR_AF 0x10 | ||
| 54 | #define BF_RTC_CR_AF(v) (((v) & 0x1) << 4) | ||
| 55 | #define BFM_RTC_CR_AF(v) BM_RTC_CR_AF | ||
| 56 | #define BF_RTC_CR_AF_V(e) BF_RTC_CR_AF(BV_RTC_CR_AF__##e) | ||
| 57 | #define BFM_RTC_CR_AF_V(v) BM_RTC_CR_AF | ||
| 58 | #define BP_RTC_CR_AIE 3 | ||
| 59 | #define BM_RTC_CR_AIE 0x8 | ||
| 60 | #define BF_RTC_CR_AIE(v) (((v) & 0x1) << 3) | ||
| 61 | #define BFM_RTC_CR_AIE(v) BM_RTC_CR_AIE | ||
| 62 | #define BF_RTC_CR_AIE_V(e) BF_RTC_CR_AIE(BV_RTC_CR_AIE__##e) | ||
| 63 | #define BFM_RTC_CR_AIE_V(v) BM_RTC_CR_AIE | ||
| 64 | #define BP_RTC_CR_AE 2 | ||
| 65 | #define BM_RTC_CR_AE 0x4 | ||
| 66 | #define BF_RTC_CR_AE(v) (((v) & 0x1) << 2) | ||
| 67 | #define BFM_RTC_CR_AE(v) BM_RTC_CR_AE | ||
| 68 | #define BF_RTC_CR_AE_V(e) BF_RTC_CR_AE(BV_RTC_CR_AE__##e) | ||
| 69 | #define BFM_RTC_CR_AE_V(v) BM_RTC_CR_AE | ||
| 70 | #define BP_RTC_CR_SELEXC 1 | ||
| 71 | #define BM_RTC_CR_SELEXC 0x2 | ||
| 72 | #define BF_RTC_CR_SELEXC(v) (((v) & 0x1) << 1) | ||
| 73 | #define BFM_RTC_CR_SELEXC(v) BM_RTC_CR_SELEXC | ||
| 74 | #define BF_RTC_CR_SELEXC_V(e) BF_RTC_CR_SELEXC(BV_RTC_CR_SELEXC__##e) | ||
| 75 | #define BFM_RTC_CR_SELEXC_V(v) BM_RTC_CR_SELEXC | ||
| 76 | #define BP_RTC_CR_ENABLE 0 | ||
| 77 | #define BM_RTC_CR_ENABLE 0x1 | ||
| 78 | #define BF_RTC_CR_ENABLE(v) (((v) & 0x1) << 0) | ||
| 79 | #define BFM_RTC_CR_ENABLE(v) BM_RTC_CR_ENABLE | ||
| 80 | #define BF_RTC_CR_ENABLE_V(e) BF_RTC_CR_ENABLE(BV_RTC_CR_ENABLE__##e) | ||
| 81 | #define BFM_RTC_CR_ENABLE_V(v) BM_RTC_CR_ENABLE | ||
| 82 | |||
| 83 | #define REG_RTC_SR jz_reg(RTC_SR) | ||
| 84 | #define JA_RTC_SR (0xb0003000 + 0x4) | ||
| 85 | #define JT_RTC_SR JIO_32_RW | ||
| 86 | #define JN_RTC_SR RTC_SR | ||
| 87 | #define JI_RTC_SR | ||
| 88 | |||
| 89 | #define REG_RTC_SAR jz_reg(RTC_SAR) | ||
| 90 | #define JA_RTC_SAR (0xb0003000 + 0x8) | ||
| 91 | #define JT_RTC_SAR JIO_32_RW | ||
| 92 | #define JN_RTC_SAR RTC_SAR | ||
| 93 | #define JI_RTC_SAR | ||
| 94 | |||
| 95 | #define REG_RTC_GR jz_reg(RTC_GR) | ||
| 96 | #define JA_RTC_GR (0xb0003000 + 0xc) | ||
| 97 | #define JT_RTC_GR JIO_32_RW | ||
| 98 | #define JN_RTC_GR RTC_GR | ||
| 99 | #define JI_RTC_GR | ||
| 100 | #define BP_RTC_GR_ADJC 16 | ||
| 101 | #define BM_RTC_GR_ADJC 0x3ff0000 | ||
| 102 | #define BF_RTC_GR_ADJC(v) (((v) & 0x3ff) << 16) | ||
| 103 | #define BFM_RTC_GR_ADJC(v) BM_RTC_GR_ADJC | ||
| 104 | #define BF_RTC_GR_ADJC_V(e) BF_RTC_GR_ADJC(BV_RTC_GR_ADJC__##e) | ||
| 105 | #define BFM_RTC_GR_ADJC_V(v) BM_RTC_GR_ADJC | ||
| 106 | #define BP_RTC_GR_NC1HZ 0 | ||
| 107 | #define BM_RTC_GR_NC1HZ 0xffff | ||
| 108 | #define BF_RTC_GR_NC1HZ(v) (((v) & 0xffff) << 0) | ||
| 109 | #define BFM_RTC_GR_NC1HZ(v) BM_RTC_GR_NC1HZ | ||
| 110 | #define BF_RTC_GR_NC1HZ_V(e) BF_RTC_GR_NC1HZ(BV_RTC_GR_NC1HZ__##e) | ||
| 111 | #define BFM_RTC_GR_NC1HZ_V(v) BM_RTC_GR_NC1HZ | ||
| 112 | #define BP_RTC_GR_LOCK 31 | ||
| 113 | #define BM_RTC_GR_LOCK 0x80000000 | ||
| 114 | #define BF_RTC_GR_LOCK(v) (((v) & 0x1) << 31) | ||
| 115 | #define BFM_RTC_GR_LOCK(v) BM_RTC_GR_LOCK | ||
| 116 | #define BF_RTC_GR_LOCK_V(e) BF_RTC_GR_LOCK(BV_RTC_GR_LOCK__##e) | ||
| 117 | #define BFM_RTC_GR_LOCK_V(v) BM_RTC_GR_LOCK | ||
| 118 | |||
| 119 | #define REG_RTC_HCR jz_reg(RTC_HCR) | ||
| 120 | #define JA_RTC_HCR (0xb0003000 + 0x20) | ||
| 121 | #define JT_RTC_HCR JIO_32_RW | ||
| 122 | #define JN_RTC_HCR RTC_HCR | ||
| 123 | #define JI_RTC_HCR | ||
| 124 | |||
| 125 | #define REG_RTC_HWFCR jz_reg(RTC_HWFCR) | ||
| 126 | #define JA_RTC_HWFCR (0xb0003000 + 0x24) | ||
| 127 | #define JT_RTC_HWFCR JIO_32_RW | ||
| 128 | #define JN_RTC_HWFCR RTC_HWFCR | ||
| 129 | #define JI_RTC_HWFCR | ||
| 130 | |||
| 131 | #define REG_RTC_HRCR jz_reg(RTC_HRCR) | ||
| 132 | #define JA_RTC_HRCR (0xb0003000 + 0x28) | ||
| 133 | #define JT_RTC_HRCR JIO_32_RW | ||
| 134 | #define JN_RTC_HRCR RTC_HRCR | ||
| 135 | #define JI_RTC_HRCR | ||
| 136 | |||
| 137 | #define REG_RTC_HWCR jz_reg(RTC_HWCR) | ||
| 138 | #define JA_RTC_HWCR (0xb0003000 + 0x2c) | ||
| 139 | #define JT_RTC_HWCR JIO_32_RW | ||
| 140 | #define JN_RTC_HWCR RTC_HWCR | ||
| 141 | #define JI_RTC_HWCR | ||
| 142 | #define BP_RTC_HWCR_EPDET 3 | ||
| 143 | #define BM_RTC_HWCR_EPDET 0xfffffff8 | ||
| 144 | #define BF_RTC_HWCR_EPDET(v) (((v) & 0x1fffffff) << 3) | ||
| 145 | #define BFM_RTC_HWCR_EPDET(v) BM_RTC_HWCR_EPDET | ||
| 146 | #define BF_RTC_HWCR_EPDET_V(e) BF_RTC_HWCR_EPDET(BV_RTC_HWCR_EPDET__##e) | ||
| 147 | #define BFM_RTC_HWCR_EPDET_V(v) BM_RTC_HWCR_EPDET | ||
| 148 | #define BP_RTC_HWCR_EALM 1 | ||
| 149 | #define BM_RTC_HWCR_EALM 0x2 | ||
| 150 | #define BF_RTC_HWCR_EALM(v) (((v) & 0x1) << 1) | ||
| 151 | #define BFM_RTC_HWCR_EALM(v) BM_RTC_HWCR_EALM | ||
| 152 | #define BF_RTC_HWCR_EALM_V(e) BF_RTC_HWCR_EALM(BV_RTC_HWCR_EALM__##e) | ||
| 153 | #define BFM_RTC_HWCR_EALM_V(v) BM_RTC_HWCR_EALM | ||
| 154 | |||
| 155 | #define REG_RTC_HWRSR jz_reg(RTC_HWRSR) | ||
| 156 | #define JA_RTC_HWRSR (0xb0003000 + 0x30) | ||
| 157 | #define JT_RTC_HWRSR JIO_32_RW | ||
| 158 | #define JN_RTC_HWRSR RTC_HWRSR | ||
| 159 | #define JI_RTC_HWRSR | ||
| 160 | #define BP_RTC_HWRSR_APD 8 | ||
| 161 | #define BM_RTC_HWRSR_APD 0x100 | ||
| 162 | #define BF_RTC_HWRSR_APD(v) (((v) & 0x1) << 8) | ||
| 163 | #define BFM_RTC_HWRSR_APD(v) BM_RTC_HWRSR_APD | ||
| 164 | #define BF_RTC_HWRSR_APD_V(e) BF_RTC_HWRSR_APD(BV_RTC_HWRSR_APD__##e) | ||
| 165 | #define BFM_RTC_HWRSR_APD_V(v) BM_RTC_HWRSR_APD | ||
| 166 | #define BP_RTC_HWRSR_HR 5 | ||
| 167 | #define BM_RTC_HWRSR_HR 0x20 | ||
| 168 | #define BF_RTC_HWRSR_HR(v) (((v) & 0x1) << 5) | ||
| 169 | #define BFM_RTC_HWRSR_HR(v) BM_RTC_HWRSR_HR | ||
| 170 | #define BF_RTC_HWRSR_HR_V(e) BF_RTC_HWRSR_HR(BV_RTC_HWRSR_HR__##e) | ||
| 171 | #define BFM_RTC_HWRSR_HR_V(v) BM_RTC_HWRSR_HR | ||
| 172 | #define BP_RTC_HWRSR_PPR 4 | ||
| 173 | #define BM_RTC_HWRSR_PPR 0x10 | ||
| 174 | #define BF_RTC_HWRSR_PPR(v) (((v) & 0x1) << 4) | ||
| 175 | #define BFM_RTC_HWRSR_PPR(v) BM_RTC_HWRSR_PPR | ||
| 176 | #define BF_RTC_HWRSR_PPR_V(e) BF_RTC_HWRSR_PPR(BV_RTC_HWRSR_PPR__##e) | ||
| 177 | #define BFM_RTC_HWRSR_PPR_V(v) BM_RTC_HWRSR_PPR | ||
| 178 | #define BP_RTC_HWRSR_PIN 1 | ||
| 179 | #define BM_RTC_HWRSR_PIN 0x2 | ||
| 180 | #define BF_RTC_HWRSR_PIN(v) (((v) & 0x1) << 1) | ||
| 181 | #define BFM_RTC_HWRSR_PIN(v) BM_RTC_HWRSR_PIN | ||
| 182 | #define BF_RTC_HWRSR_PIN_V(e) BF_RTC_HWRSR_PIN(BV_RTC_HWRSR_PIN__##e) | ||
| 183 | #define BFM_RTC_HWRSR_PIN_V(v) BM_RTC_HWRSR_PIN | ||
| 184 | #define BP_RTC_HWRSR_ALM 0 | ||
| 185 | #define BM_RTC_HWRSR_ALM 0x1 | ||
| 186 | #define BF_RTC_HWRSR_ALM(v) (((v) & 0x1) << 0) | ||
| 187 | #define BFM_RTC_HWRSR_ALM(v) BM_RTC_HWRSR_ALM | ||
| 188 | #define BF_RTC_HWRSR_ALM_V(e) BF_RTC_HWRSR_ALM(BV_RTC_HWRSR_ALM__##e) | ||
| 189 | #define BFM_RTC_HWRSR_ALM_V(v) BM_RTC_HWRSR_ALM | ||
| 190 | |||
| 191 | #define REG_RTC_HSPR jz_reg(RTC_HSPR) | ||
| 192 | #define JA_RTC_HSPR (0xb0003000 + 0x34) | ||
| 193 | #define JT_RTC_HSPR JIO_32_RW | ||
| 194 | #define JN_RTC_HSPR RTC_HSPR | ||
| 195 | #define JI_RTC_HSPR | ||
| 196 | |||
| 197 | #define REG_RTC_WENR jz_reg(RTC_WENR) | ||
| 198 | #define JA_RTC_WENR (0xb0003000 + 0x3c) | ||
| 199 | #define JT_RTC_WENR JIO_32_RW | ||
| 200 | #define JN_RTC_WENR RTC_WENR | ||
| 201 | #define JI_RTC_WENR | ||
| 202 | #define BP_RTC_WENR_WEN 31 | ||
| 203 | #define BM_RTC_WENR_WEN 0x80000000 | ||
| 204 | #define BF_RTC_WENR_WEN(v) (((v) & 0x1) << 31) | ||
| 205 | #define BFM_RTC_WENR_WEN(v) BM_RTC_WENR_WEN | ||
| 206 | #define BF_RTC_WENR_WEN_V(e) BF_RTC_WENR_WEN(BV_RTC_WENR_WEN__##e) | ||
| 207 | #define BFM_RTC_WENR_WEN_V(v) BM_RTC_WENR_WEN | ||
| 208 | #define BP_RTC_WENR_WENPAT 0 | ||
| 209 | #define BM_RTC_WENR_WENPAT 0xffff | ||
| 210 | #define BF_RTC_WENR_WENPAT(v) (((v) & 0xffff) << 0) | ||
| 211 | #define BFM_RTC_WENR_WENPAT(v) BM_RTC_WENR_WENPAT | ||
| 212 | #define BF_RTC_WENR_WENPAT_V(e) BF_RTC_WENR_WENPAT(BV_RTC_WENR_WENPAT__##e) | ||
| 213 | #define BFM_RTC_WENR_WENPAT_V(v) BM_RTC_WENR_WENPAT | ||
| 214 | |||
| 215 | #define REG_RTC_WKUPPINCR jz_reg(RTC_WKUPPINCR) | ||
| 216 | #define JA_RTC_WKUPPINCR (0xb0003000 + 0x48) | ||
| 217 | #define JT_RTC_WKUPPINCR JIO_32_RW | ||
| 218 | #define JN_RTC_WKUPPINCR RTC_WKUPPINCR | ||
| 219 | #define JI_RTC_WKUPPINCR | ||
| 220 | |||
| 221 | #endif /* __HEADERGEN_RTC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/sfc.h b/firmware/target/mips/ingenic_x1000/x1000/sfc.h new file mode 100644 index 0000000000..1a3c102c64 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/sfc.h | |||
| @@ -0,0 +1,481 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_SFC_H__ | ||
| 25 | #define __HEADERGEN_SFC_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_SFC_GLB jz_reg(SFC_GLB) | ||
| 30 | #define JA_SFC_GLB (0xb3440000 + 0x0) | ||
| 31 | #define JT_SFC_GLB JIO_32_RW | ||
| 32 | #define JN_SFC_GLB SFC_GLB | ||
| 33 | #define JI_SFC_GLB | ||
| 34 | #define BP_SFC_GLB_THRESHOLD 7 | ||
| 35 | #define BM_SFC_GLB_THRESHOLD 0x1f80 | ||
| 36 | #define BF_SFC_GLB_THRESHOLD(v) (((v) & 0x3f) << 7) | ||
| 37 | #define BFM_SFC_GLB_THRESHOLD(v) BM_SFC_GLB_THRESHOLD | ||
| 38 | #define BF_SFC_GLB_THRESHOLD_V(e) BF_SFC_GLB_THRESHOLD(BV_SFC_GLB_THRESHOLD__##e) | ||
| 39 | #define BFM_SFC_GLB_THRESHOLD_V(v) BM_SFC_GLB_THRESHOLD | ||
| 40 | #define BP_SFC_GLB_PHASE_NUM 3 | ||
| 41 | #define BM_SFC_GLB_PHASE_NUM 0x38 | ||
| 42 | #define BF_SFC_GLB_PHASE_NUM(v) (((v) & 0x7) << 3) | ||
| 43 | #define BFM_SFC_GLB_PHASE_NUM(v) BM_SFC_GLB_PHASE_NUM | ||
| 44 | #define BF_SFC_GLB_PHASE_NUM_V(e) BF_SFC_GLB_PHASE_NUM(BV_SFC_GLB_PHASE_NUM__##e) | ||
| 45 | #define BFM_SFC_GLB_PHASE_NUM_V(v) BM_SFC_GLB_PHASE_NUM | ||
| 46 | #define BP_SFC_GLB_TRAN_DIR 13 | ||
| 47 | #define BM_SFC_GLB_TRAN_DIR 0x2000 | ||
| 48 | #define BV_SFC_GLB_TRAN_DIR__READ 0x0 | ||
| 49 | #define BV_SFC_GLB_TRAN_DIR__WRITE 0x1 | ||
| 50 | #define BF_SFC_GLB_TRAN_DIR(v) (((v) & 0x1) << 13) | ||
| 51 | #define BFM_SFC_GLB_TRAN_DIR(v) BM_SFC_GLB_TRAN_DIR | ||
| 52 | #define BF_SFC_GLB_TRAN_DIR_V(e) BF_SFC_GLB_TRAN_DIR(BV_SFC_GLB_TRAN_DIR__##e) | ||
| 53 | #define BFM_SFC_GLB_TRAN_DIR_V(v) BM_SFC_GLB_TRAN_DIR | ||
| 54 | #define BP_SFC_GLB_OP_MODE 6 | ||
| 55 | #define BM_SFC_GLB_OP_MODE 0x40 | ||
| 56 | #define BV_SFC_GLB_OP_MODE__SLAVE 0x0 | ||
| 57 | #define BV_SFC_GLB_OP_MODE__DMA 0x1 | ||
| 58 | #define BF_SFC_GLB_OP_MODE(v) (((v) & 0x1) << 6) | ||
| 59 | #define BFM_SFC_GLB_OP_MODE(v) BM_SFC_GLB_OP_MODE | ||
| 60 | #define BF_SFC_GLB_OP_MODE_V(e) BF_SFC_GLB_OP_MODE(BV_SFC_GLB_OP_MODE__##e) | ||
| 61 | #define BFM_SFC_GLB_OP_MODE_V(v) BM_SFC_GLB_OP_MODE | ||
| 62 | #define BP_SFC_GLB_WP_EN 2 | ||
| 63 | #define BM_SFC_GLB_WP_EN 0x4 | ||
| 64 | #define BF_SFC_GLB_WP_EN(v) (((v) & 0x1) << 2) | ||
| 65 | #define BFM_SFC_GLB_WP_EN(v) BM_SFC_GLB_WP_EN | ||
| 66 | #define BF_SFC_GLB_WP_EN_V(e) BF_SFC_GLB_WP_EN(BV_SFC_GLB_WP_EN__##e) | ||
| 67 | #define BFM_SFC_GLB_WP_EN_V(v) BM_SFC_GLB_WP_EN | ||
| 68 | #define BP_SFC_GLB_BURST_MD 0 | ||
| 69 | #define BM_SFC_GLB_BURST_MD 0x3 | ||
| 70 | #define BV_SFC_GLB_BURST_MD__INCR4 0x0 | ||
| 71 | #define BV_SFC_GLB_BURST_MD__INCR8 0x1 | ||
| 72 | #define BV_SFC_GLB_BURST_MD__INCR16 0x2 | ||
| 73 | #define BV_SFC_GLB_BURST_MD__INCR32 0x3 | ||
| 74 | #define BF_SFC_GLB_BURST_MD(v) (((v) & 0x3) << 0) | ||
| 75 | #define BFM_SFC_GLB_BURST_MD(v) BM_SFC_GLB_BURST_MD | ||
| 76 | #define BF_SFC_GLB_BURST_MD_V(e) BF_SFC_GLB_BURST_MD(BV_SFC_GLB_BURST_MD__##e) | ||
| 77 | #define BFM_SFC_GLB_BURST_MD_V(v) BM_SFC_GLB_BURST_MD | ||
| 78 | |||
| 79 | #define REG_SFC_DEV_CONF jz_reg(SFC_DEV_CONF) | ||
| 80 | #define JA_SFC_DEV_CONF (0xb3440000 + 0x4) | ||
| 81 | #define JT_SFC_DEV_CONF JIO_32_RW | ||
| 82 | #define JN_SFC_DEV_CONF SFC_DEV_CONF | ||
| 83 | #define JI_SFC_DEV_CONF | ||
| 84 | #define BP_SFC_DEV_CONF_SMP_DELAY 16 | ||
| 85 | #define BM_SFC_DEV_CONF_SMP_DELAY 0x30000 | ||
| 86 | #define BF_SFC_DEV_CONF_SMP_DELAY(v) (((v) & 0x3) << 16) | ||
| 87 | #define BFM_SFC_DEV_CONF_SMP_DELAY(v) BM_SFC_DEV_CONF_SMP_DELAY | ||
| 88 | #define BF_SFC_DEV_CONF_SMP_DELAY_V(e) BF_SFC_DEV_CONF_SMP_DELAY(BV_SFC_DEV_CONF_SMP_DELAY__##e) | ||
| 89 | #define BFM_SFC_DEV_CONF_SMP_DELAY_V(v) BM_SFC_DEV_CONF_SMP_DELAY | ||
| 90 | #define BP_SFC_DEV_CONF_STA_TYPE 13 | ||
| 91 | #define BM_SFC_DEV_CONF_STA_TYPE 0x6000 | ||
| 92 | #define BV_SFC_DEV_CONF_STA_TYPE__1BYTE 0x0 | ||
| 93 | #define BV_SFC_DEV_CONF_STA_TYPE__2BYTE 0x1 | ||
| 94 | #define BV_SFC_DEV_CONF_STA_TYPE__3BYTE 0x2 | ||
| 95 | #define BV_SFC_DEV_CONF_STA_TYPE__4BYTE 0x3 | ||
| 96 | #define BF_SFC_DEV_CONF_STA_TYPE(v) (((v) & 0x3) << 13) | ||
| 97 | #define BFM_SFC_DEV_CONF_STA_TYPE(v) BM_SFC_DEV_CONF_STA_TYPE | ||
| 98 | #define BF_SFC_DEV_CONF_STA_TYPE_V(e) BF_SFC_DEV_CONF_STA_TYPE(BV_SFC_DEV_CONF_STA_TYPE__##e) | ||
| 99 | #define BFM_SFC_DEV_CONF_STA_TYPE_V(v) BM_SFC_DEV_CONF_STA_TYPE | ||
| 100 | #define BP_SFC_DEV_CONF_THOLD 11 | ||
| 101 | #define BM_SFC_DEV_CONF_THOLD 0x1800 | ||
| 102 | #define BF_SFC_DEV_CONF_THOLD(v) (((v) & 0x3) << 11) | ||
| 103 | #define BFM_SFC_DEV_CONF_THOLD(v) BM_SFC_DEV_CONF_THOLD | ||
| 104 | #define BF_SFC_DEV_CONF_THOLD_V(e) BF_SFC_DEV_CONF_THOLD(BV_SFC_DEV_CONF_THOLD__##e) | ||
| 105 | #define BFM_SFC_DEV_CONF_THOLD_V(v) BM_SFC_DEV_CONF_THOLD | ||
| 106 | #define BP_SFC_DEV_CONF_TSETUP 9 | ||
| 107 | #define BM_SFC_DEV_CONF_TSETUP 0x600 | ||
| 108 | #define BF_SFC_DEV_CONF_TSETUP(v) (((v) & 0x3) << 9) | ||
| 109 | #define BFM_SFC_DEV_CONF_TSETUP(v) BM_SFC_DEV_CONF_TSETUP | ||
| 110 | #define BF_SFC_DEV_CONF_TSETUP_V(e) BF_SFC_DEV_CONF_TSETUP(BV_SFC_DEV_CONF_TSETUP__##e) | ||
| 111 | #define BFM_SFC_DEV_CONF_TSETUP_V(v) BM_SFC_DEV_CONF_TSETUP | ||
| 112 | #define BP_SFC_DEV_CONF_TSH 5 | ||
| 113 | #define BM_SFC_DEV_CONF_TSH 0x1e0 | ||
| 114 | #define BF_SFC_DEV_CONF_TSH(v) (((v) & 0xf) << 5) | ||
| 115 | #define BFM_SFC_DEV_CONF_TSH(v) BM_SFC_DEV_CONF_TSH | ||
| 116 | #define BF_SFC_DEV_CONF_TSH_V(e) BF_SFC_DEV_CONF_TSH(BV_SFC_DEV_CONF_TSH__##e) | ||
| 117 | #define BFM_SFC_DEV_CONF_TSH_V(v) BM_SFC_DEV_CONF_TSH | ||
| 118 | #define BP_SFC_DEV_CONF_CMD_TYPE 15 | ||
| 119 | #define BM_SFC_DEV_CONF_CMD_TYPE 0x8000 | ||
| 120 | #define BV_SFC_DEV_CONF_CMD_TYPE__8BITS 0x0 | ||
| 121 | #define BV_SFC_DEV_CONF_CMD_TYPE__16BITS 0x1 | ||
| 122 | #define BF_SFC_DEV_CONF_CMD_TYPE(v) (((v) & 0x1) << 15) | ||
| 123 | #define BFM_SFC_DEV_CONF_CMD_TYPE(v) BM_SFC_DEV_CONF_CMD_TYPE | ||
| 124 | #define BF_SFC_DEV_CONF_CMD_TYPE_V(e) BF_SFC_DEV_CONF_CMD_TYPE(BV_SFC_DEV_CONF_CMD_TYPE__##e) | ||
| 125 | #define BFM_SFC_DEV_CONF_CMD_TYPE_V(v) BM_SFC_DEV_CONF_CMD_TYPE | ||
| 126 | #define BP_SFC_DEV_CONF_CPHA 4 | ||
| 127 | #define BM_SFC_DEV_CONF_CPHA 0x10 | ||
| 128 | #define BF_SFC_DEV_CONF_CPHA(v) (((v) & 0x1) << 4) | ||
| 129 | #define BFM_SFC_DEV_CONF_CPHA(v) BM_SFC_DEV_CONF_CPHA | ||
| 130 | #define BF_SFC_DEV_CONF_CPHA_V(e) BF_SFC_DEV_CONF_CPHA(BV_SFC_DEV_CONF_CPHA__##e) | ||
| 131 | #define BFM_SFC_DEV_CONF_CPHA_V(v) BM_SFC_DEV_CONF_CPHA | ||
| 132 | #define BP_SFC_DEV_CONF_CPOL 3 | ||
| 133 | #define BM_SFC_DEV_CONF_CPOL 0x8 | ||
| 134 | #define BF_SFC_DEV_CONF_CPOL(v) (((v) & 0x1) << 3) | ||
| 135 | #define BFM_SFC_DEV_CONF_CPOL(v) BM_SFC_DEV_CONF_CPOL | ||
| 136 | #define BF_SFC_DEV_CONF_CPOL_V(e) BF_SFC_DEV_CONF_CPOL(BV_SFC_DEV_CONF_CPOL__##e) | ||
| 137 | #define BFM_SFC_DEV_CONF_CPOL_V(v) BM_SFC_DEV_CONF_CPOL | ||
| 138 | #define BP_SFC_DEV_CONF_CE_DL 2 | ||
| 139 | #define BM_SFC_DEV_CONF_CE_DL 0x4 | ||
| 140 | #define BF_SFC_DEV_CONF_CE_DL(v) (((v) & 0x1) << 2) | ||
| 141 | #define BFM_SFC_DEV_CONF_CE_DL(v) BM_SFC_DEV_CONF_CE_DL | ||
| 142 | #define BF_SFC_DEV_CONF_CE_DL_V(e) BF_SFC_DEV_CONF_CE_DL(BV_SFC_DEV_CONF_CE_DL__##e) | ||
| 143 | #define BFM_SFC_DEV_CONF_CE_DL_V(v) BM_SFC_DEV_CONF_CE_DL | ||
| 144 | #define BP_SFC_DEV_CONF_HOLD_DL 1 | ||
| 145 | #define BM_SFC_DEV_CONF_HOLD_DL 0x2 | ||
| 146 | #define BF_SFC_DEV_CONF_HOLD_DL(v) (((v) & 0x1) << 1) | ||
| 147 | #define BFM_SFC_DEV_CONF_HOLD_DL(v) BM_SFC_DEV_CONF_HOLD_DL | ||
| 148 | #define BF_SFC_DEV_CONF_HOLD_DL_V(e) BF_SFC_DEV_CONF_HOLD_DL(BV_SFC_DEV_CONF_HOLD_DL__##e) | ||
| 149 | #define BFM_SFC_DEV_CONF_HOLD_DL_V(v) BM_SFC_DEV_CONF_HOLD_DL | ||
| 150 | #define BP_SFC_DEV_CONF_WP_DL 0 | ||
| 151 | #define BM_SFC_DEV_CONF_WP_DL 0x1 | ||
| 152 | #define BF_SFC_DEV_CONF_WP_DL(v) (((v) & 0x1) << 0) | ||
| 153 | #define BFM_SFC_DEV_CONF_WP_DL(v) BM_SFC_DEV_CONF_WP_DL | ||
| 154 | #define BF_SFC_DEV_CONF_WP_DL_V(e) BF_SFC_DEV_CONF_WP_DL(BV_SFC_DEV_CONF_WP_DL__##e) | ||
| 155 | #define BFM_SFC_DEV_CONF_WP_DL_V(v) BM_SFC_DEV_CONF_WP_DL | ||
| 156 | |||
| 157 | #define REG_SFC_DEV_STA_EXP jz_reg(SFC_DEV_STA_EXP) | ||
| 158 | #define JA_SFC_DEV_STA_EXP (0xb3440000 + 0x8) | ||
| 159 | #define JT_SFC_DEV_STA_EXP JIO_32_RW | ||
| 160 | #define JN_SFC_DEV_STA_EXP SFC_DEV_STA_EXP | ||
| 161 | #define JI_SFC_DEV_STA_EXP | ||
| 162 | |||
| 163 | #define REG_SFC_DEV_STA_RT jz_reg(SFC_DEV_STA_RT) | ||
| 164 | #define JA_SFC_DEV_STA_RT (0xb3440000 + 0xc) | ||
| 165 | #define JT_SFC_DEV_STA_RT JIO_32_RW | ||
| 166 | #define JN_SFC_DEV_STA_RT SFC_DEV_STA_RT | ||
| 167 | #define JI_SFC_DEV_STA_RT | ||
| 168 | |||
| 169 | #define REG_SFC_DEV_STA_MSK jz_reg(SFC_DEV_STA_MSK) | ||
| 170 | #define JA_SFC_DEV_STA_MSK (0xb3440000 + 0x10) | ||
| 171 | #define JT_SFC_DEV_STA_MSK JIO_32_RW | ||
| 172 | #define JN_SFC_DEV_STA_MSK SFC_DEV_STA_MSK | ||
| 173 | #define JI_SFC_DEV_STA_MSK | ||
| 174 | |||
| 175 | #define REG_SFC_TRAN_CONF(_n1) jz_reg(SFC_TRAN_CONF(_n1)) | ||
| 176 | #define JA_SFC_TRAN_CONF(_n1) (0xb3440000 + 0x14 + (_n1) * 0x4) | ||
| 177 | #define JT_SFC_TRAN_CONF(_n1) JIO_32_RW | ||
| 178 | #define JN_SFC_TRAN_CONF(_n1) SFC_TRAN_CONF | ||
| 179 | #define JI_SFC_TRAN_CONF(_n1) (_n1) | ||
| 180 | #define BP_SFC_TRAN_CONF_MODE 29 | ||
| 181 | #define BM_SFC_TRAN_CONF_MODE 0xe0000000 | ||
| 182 | #define BF_SFC_TRAN_CONF_MODE(v) (((v) & 0x7) << 29) | ||
| 183 | #define BFM_SFC_TRAN_CONF_MODE(v) BM_SFC_TRAN_CONF_MODE | ||
| 184 | #define BF_SFC_TRAN_CONF_MODE_V(e) BF_SFC_TRAN_CONF_MODE(BV_SFC_TRAN_CONF_MODE__##e) | ||
| 185 | #define BFM_SFC_TRAN_CONF_MODE_V(v) BM_SFC_TRAN_CONF_MODE | ||
| 186 | #define BP_SFC_TRAN_CONF_ADDR_WIDTH 26 | ||
| 187 | #define BM_SFC_TRAN_CONF_ADDR_WIDTH 0x1c000000 | ||
| 188 | #define BF_SFC_TRAN_CONF_ADDR_WIDTH(v) (((v) & 0x7) << 26) | ||
| 189 | #define BFM_SFC_TRAN_CONF_ADDR_WIDTH(v) BM_SFC_TRAN_CONF_ADDR_WIDTH | ||
| 190 | #define BF_SFC_TRAN_CONF_ADDR_WIDTH_V(e) BF_SFC_TRAN_CONF_ADDR_WIDTH(BV_SFC_TRAN_CONF_ADDR_WIDTH__##e) | ||
| 191 | #define BFM_SFC_TRAN_CONF_ADDR_WIDTH_V(v) BM_SFC_TRAN_CONF_ADDR_WIDTH | ||
| 192 | #define BP_SFC_TRAN_CONF_DUMMY_BITS 17 | ||
| 193 | #define BM_SFC_TRAN_CONF_DUMMY_BITS 0x7e0000 | ||
| 194 | #define BF_SFC_TRAN_CONF_DUMMY_BITS(v) (((v) & 0x3f) << 17) | ||
| 195 | #define BFM_SFC_TRAN_CONF_DUMMY_BITS(v) BM_SFC_TRAN_CONF_DUMMY_BITS | ||
| 196 | #define BF_SFC_TRAN_CONF_DUMMY_BITS_V(e) BF_SFC_TRAN_CONF_DUMMY_BITS(BV_SFC_TRAN_CONF_DUMMY_BITS__##e) | ||
| 197 | #define BFM_SFC_TRAN_CONF_DUMMY_BITS_V(v) BM_SFC_TRAN_CONF_DUMMY_BITS | ||
| 198 | #define BP_SFC_TRAN_CONF_COMMAND 0 | ||
| 199 | #define BM_SFC_TRAN_CONF_COMMAND 0xffff | ||
| 200 | #define BF_SFC_TRAN_CONF_COMMAND(v) (((v) & 0xffff) << 0) | ||
| 201 | #define BFM_SFC_TRAN_CONF_COMMAND(v) BM_SFC_TRAN_CONF_COMMAND | ||
| 202 | #define BF_SFC_TRAN_CONF_COMMAND_V(e) BF_SFC_TRAN_CONF_COMMAND(BV_SFC_TRAN_CONF_COMMAND__##e) | ||
| 203 | #define BFM_SFC_TRAN_CONF_COMMAND_V(v) BM_SFC_TRAN_CONF_COMMAND | ||
| 204 | #define BP_SFC_TRAN_CONF_POLL_EN 25 | ||
| 205 | #define BM_SFC_TRAN_CONF_POLL_EN 0x2000000 | ||
| 206 | #define BF_SFC_TRAN_CONF_POLL_EN(v) (((v) & 0x1) << 25) | ||
| 207 | #define BFM_SFC_TRAN_CONF_POLL_EN(v) BM_SFC_TRAN_CONF_POLL_EN | ||
| 208 | #define BF_SFC_TRAN_CONF_POLL_EN_V(e) BF_SFC_TRAN_CONF_POLL_EN(BV_SFC_TRAN_CONF_POLL_EN__##e) | ||
| 209 | #define BFM_SFC_TRAN_CONF_POLL_EN_V(v) BM_SFC_TRAN_CONF_POLL_EN | ||
| 210 | #define BP_SFC_TRAN_CONF_CMD_EN 24 | ||
| 211 | #define BM_SFC_TRAN_CONF_CMD_EN 0x1000000 | ||
| 212 | #define BF_SFC_TRAN_CONF_CMD_EN(v) (((v) & 0x1) << 24) | ||
| 213 | #define BFM_SFC_TRAN_CONF_CMD_EN(v) BM_SFC_TRAN_CONF_CMD_EN | ||
| 214 | #define BF_SFC_TRAN_CONF_CMD_EN_V(e) BF_SFC_TRAN_CONF_CMD_EN(BV_SFC_TRAN_CONF_CMD_EN__##e) | ||
| 215 | #define BFM_SFC_TRAN_CONF_CMD_EN_V(v) BM_SFC_TRAN_CONF_CMD_EN | ||
| 216 | #define BP_SFC_TRAN_CONF_PHASE_FMT 23 | ||
| 217 | #define BM_SFC_TRAN_CONF_PHASE_FMT 0x800000 | ||
| 218 | #define BF_SFC_TRAN_CONF_PHASE_FMT(v) (((v) & 0x1) << 23) | ||
| 219 | #define BFM_SFC_TRAN_CONF_PHASE_FMT(v) BM_SFC_TRAN_CONF_PHASE_FMT | ||
| 220 | #define BF_SFC_TRAN_CONF_PHASE_FMT_V(e) BF_SFC_TRAN_CONF_PHASE_FMT(BV_SFC_TRAN_CONF_PHASE_FMT__##e) | ||
| 221 | #define BFM_SFC_TRAN_CONF_PHASE_FMT_V(v) BM_SFC_TRAN_CONF_PHASE_FMT | ||
| 222 | #define BP_SFC_TRAN_CONF_DATA_EN 16 | ||
| 223 | #define BM_SFC_TRAN_CONF_DATA_EN 0x10000 | ||
| 224 | #define BF_SFC_TRAN_CONF_DATA_EN(v) (((v) & 0x1) << 16) | ||
| 225 | #define BFM_SFC_TRAN_CONF_DATA_EN(v) BM_SFC_TRAN_CONF_DATA_EN | ||
| 226 | #define BF_SFC_TRAN_CONF_DATA_EN_V(e) BF_SFC_TRAN_CONF_DATA_EN(BV_SFC_TRAN_CONF_DATA_EN__##e) | ||
| 227 | #define BFM_SFC_TRAN_CONF_DATA_EN_V(v) BM_SFC_TRAN_CONF_DATA_EN | ||
| 228 | |||
| 229 | #define REG_SFC_TRAN_LENGTH jz_reg(SFC_TRAN_LENGTH) | ||
| 230 | #define JA_SFC_TRAN_LENGTH (0xb3440000 + 0x2c) | ||
| 231 | #define JT_SFC_TRAN_LENGTH JIO_32_RW | ||
| 232 | #define JN_SFC_TRAN_LENGTH SFC_TRAN_LENGTH | ||
| 233 | #define JI_SFC_TRAN_LENGTH | ||
| 234 | |||
| 235 | #define REG_SFC_DEV_ADDR(_n1) jz_reg(SFC_DEV_ADDR(_n1)) | ||
| 236 | #define JA_SFC_DEV_ADDR(_n1) (0xb3440000 + 0x30 + (_n1) * 0x4) | ||
| 237 | #define JT_SFC_DEV_ADDR(_n1) JIO_32_RW | ||
| 238 | #define JN_SFC_DEV_ADDR(_n1) SFC_DEV_ADDR | ||
| 239 | #define JI_SFC_DEV_ADDR(_n1) (_n1) | ||
| 240 | |||
| 241 | #define REG_SFC_DEV_PLUS(_n1) jz_reg(SFC_DEV_PLUS(_n1)) | ||
| 242 | #define JA_SFC_DEV_PLUS(_n1) (0xb3440000 + 0x48 + (_n1) * 0x40) | ||
| 243 | #define JT_SFC_DEV_PLUS(_n1) JIO_32_RW | ||
| 244 | #define JN_SFC_DEV_PLUS(_n1) SFC_DEV_PLUS | ||
| 245 | #define JI_SFC_DEV_PLUS(_n1) (_n1) | ||
| 246 | |||
| 247 | #define REG_SFC_MEM_ADDR jz_reg(SFC_MEM_ADDR) | ||
| 248 | #define JA_SFC_MEM_ADDR (0xb3440000 + 0x60) | ||
| 249 | #define JT_SFC_MEM_ADDR JIO_32_RW | ||
| 250 | #define JN_SFC_MEM_ADDR SFC_MEM_ADDR | ||
| 251 | #define JI_SFC_MEM_ADDR | ||
| 252 | |||
| 253 | #define REG_SFC_TRIG jz_reg(SFC_TRIG) | ||
| 254 | #define JA_SFC_TRIG (0xb3440000 + 0x64) | ||
| 255 | #define JT_SFC_TRIG JIO_32_RW | ||
| 256 | #define JN_SFC_TRIG SFC_TRIG | ||
| 257 | #define JI_SFC_TRIG | ||
| 258 | #define BP_SFC_TRIG_FLUSH 2 | ||
| 259 | #define BM_SFC_TRIG_FLUSH 0x4 | ||
| 260 | #define BF_SFC_TRIG_FLUSH(v) (((v) & 0x1) << 2) | ||
| 261 | #define BFM_SFC_TRIG_FLUSH(v) BM_SFC_TRIG_FLUSH | ||
| 262 | #define BF_SFC_TRIG_FLUSH_V(e) BF_SFC_TRIG_FLUSH(BV_SFC_TRIG_FLUSH__##e) | ||
| 263 | #define BFM_SFC_TRIG_FLUSH_V(v) BM_SFC_TRIG_FLUSH | ||
| 264 | #define BP_SFC_TRIG_STOP 1 | ||
| 265 | #define BM_SFC_TRIG_STOP 0x2 | ||
| 266 | #define BF_SFC_TRIG_STOP(v) (((v) & 0x1) << 1) | ||
| 267 | #define BFM_SFC_TRIG_STOP(v) BM_SFC_TRIG_STOP | ||
| 268 | #define BF_SFC_TRIG_STOP_V(e) BF_SFC_TRIG_STOP(BV_SFC_TRIG_STOP__##e) | ||
| 269 | #define BFM_SFC_TRIG_STOP_V(v) BM_SFC_TRIG_STOP | ||
| 270 | #define BP_SFC_TRIG_START 0 | ||
| 271 | #define BM_SFC_TRIG_START 0x1 | ||
| 272 | #define BF_SFC_TRIG_START(v) (((v) & 0x1) << 0) | ||
| 273 | #define BFM_SFC_TRIG_START(v) BM_SFC_TRIG_START | ||
| 274 | #define BF_SFC_TRIG_START_V(e) BF_SFC_TRIG_START(BV_SFC_TRIG_START__##e) | ||
| 275 | #define BFM_SFC_TRIG_START_V(v) BM_SFC_TRIG_START | ||
| 276 | |||
| 277 | #define REG_SFC_SR jz_reg(SFC_SR) | ||
| 278 | #define JA_SFC_SR (0xb3440000 + 0x68) | ||
| 279 | #define JT_SFC_SR JIO_32_RW | ||
| 280 | #define JN_SFC_SR SFC_SR | ||
| 281 | #define JI_SFC_SR | ||
| 282 | #define BP_SFC_SR_FIFO_NUM 16 | ||
| 283 | #define BM_SFC_SR_FIFO_NUM 0x7f0000 | ||
| 284 | #define BF_SFC_SR_FIFO_NUM(v) (((v) & 0x7f) << 16) | ||
| 285 | #define BFM_SFC_SR_FIFO_NUM(v) BM_SFC_SR_FIFO_NUM | ||
| 286 | #define BF_SFC_SR_FIFO_NUM_V(e) BF_SFC_SR_FIFO_NUM(BV_SFC_SR_FIFO_NUM__##e) | ||
| 287 | #define BFM_SFC_SR_FIFO_NUM_V(v) BM_SFC_SR_FIFO_NUM | ||
| 288 | #define BP_SFC_SR_BUSY 5 | ||
| 289 | #define BM_SFC_SR_BUSY 0x60 | ||
| 290 | #define BF_SFC_SR_BUSY(v) (((v) & 0x3) << 5) | ||
| 291 | #define BFM_SFC_SR_BUSY(v) BM_SFC_SR_BUSY | ||
| 292 | #define BF_SFC_SR_BUSY_V(e) BF_SFC_SR_BUSY(BV_SFC_SR_BUSY__##e) | ||
| 293 | #define BFM_SFC_SR_BUSY_V(v) BM_SFC_SR_BUSY | ||
| 294 | #define BP_SFC_SR_END 4 | ||
| 295 | #define BM_SFC_SR_END 0x10 | ||
| 296 | #define BF_SFC_SR_END(v) (((v) & 0x1) << 4) | ||
| 297 | #define BFM_SFC_SR_END(v) BM_SFC_SR_END | ||
| 298 | #define BF_SFC_SR_END_V(e) BF_SFC_SR_END(BV_SFC_SR_END__##e) | ||
| 299 | #define BFM_SFC_SR_END_V(v) BM_SFC_SR_END | ||
| 300 | #define BP_SFC_SR_TREQ 3 | ||
| 301 | #define BM_SFC_SR_TREQ 0x8 | ||
| 302 | #define BF_SFC_SR_TREQ(v) (((v) & 0x1) << 3) | ||
| 303 | #define BFM_SFC_SR_TREQ(v) BM_SFC_SR_TREQ | ||
| 304 | #define BF_SFC_SR_TREQ_V(e) BF_SFC_SR_TREQ(BV_SFC_SR_TREQ__##e) | ||
| 305 | #define BFM_SFC_SR_TREQ_V(v) BM_SFC_SR_TREQ | ||
| 306 | #define BP_SFC_SR_RREQ 2 | ||
| 307 | #define BM_SFC_SR_RREQ 0x4 | ||
| 308 | #define BF_SFC_SR_RREQ(v) (((v) & 0x1) << 2) | ||
| 309 | #define BFM_SFC_SR_RREQ(v) BM_SFC_SR_RREQ | ||
| 310 | #define BF_SFC_SR_RREQ_V(e) BF_SFC_SR_RREQ(BV_SFC_SR_RREQ__##e) | ||
| 311 | #define BFM_SFC_SR_RREQ_V(v) BM_SFC_SR_RREQ | ||
| 312 | #define BP_SFC_SR_OVER 1 | ||
| 313 | #define BM_SFC_SR_OVER 0x2 | ||
| 314 | #define BF_SFC_SR_OVER(v) (((v) & 0x1) << 1) | ||
| 315 | #define BFM_SFC_SR_OVER(v) BM_SFC_SR_OVER | ||
| 316 | #define BF_SFC_SR_OVER_V(e) BF_SFC_SR_OVER(BV_SFC_SR_OVER__##e) | ||
| 317 | #define BFM_SFC_SR_OVER_V(v) BM_SFC_SR_OVER | ||
| 318 | #define BP_SFC_SR_UNDER 0 | ||
| 319 | #define BM_SFC_SR_UNDER 0x1 | ||
| 320 | #define BF_SFC_SR_UNDER(v) (((v) & 0x1) << 0) | ||
| 321 | #define BFM_SFC_SR_UNDER(v) BM_SFC_SR_UNDER | ||
| 322 | #define BF_SFC_SR_UNDER_V(e) BF_SFC_SR_UNDER(BV_SFC_SR_UNDER__##e) | ||
| 323 | #define BFM_SFC_SR_UNDER_V(v) BM_SFC_SR_UNDER | ||
| 324 | |||
| 325 | #define REG_SFC_SCR jz_reg(SFC_SCR) | ||
| 326 | #define JA_SFC_SCR (0xb3440000 + 0x6c) | ||
| 327 | #define JT_SFC_SCR JIO_32_RW | ||
| 328 | #define JN_SFC_SCR SFC_SCR | ||
| 329 | #define JI_SFC_SCR | ||
| 330 | #define BP_SFC_SCR_CLR_END 4 | ||
| 331 | #define BM_SFC_SCR_CLR_END 0x10 | ||
| 332 | #define BF_SFC_SCR_CLR_END(v) (((v) & 0x1) << 4) | ||
| 333 | #define BFM_SFC_SCR_CLR_END(v) BM_SFC_SCR_CLR_END | ||
| 334 | #define BF_SFC_SCR_CLR_END_V(e) BF_SFC_SCR_CLR_END(BV_SFC_SCR_CLR_END__##e) | ||
| 335 | #define BFM_SFC_SCR_CLR_END_V(v) BM_SFC_SCR_CLR_END | ||
| 336 | #define BP_SFC_SCR_CLR_TREQ 3 | ||
| 337 | #define BM_SFC_SCR_CLR_TREQ 0x8 | ||
| 338 | #define BF_SFC_SCR_CLR_TREQ(v) (((v) & 0x1) << 3) | ||
| 339 | #define BFM_SFC_SCR_CLR_TREQ(v) BM_SFC_SCR_CLR_TREQ | ||
| 340 | #define BF_SFC_SCR_CLR_TREQ_V(e) BF_SFC_SCR_CLR_TREQ(BV_SFC_SCR_CLR_TREQ__##e) | ||
| 341 | #define BFM_SFC_SCR_CLR_TREQ_V(v) BM_SFC_SCR_CLR_TREQ | ||
| 342 | #define BP_SFC_SCR_CLR_RREQ 2 | ||
| 343 | #define BM_SFC_SCR_CLR_RREQ 0x4 | ||
| 344 | #define BF_SFC_SCR_CLR_RREQ(v) (((v) & 0x1) << 2) | ||
| 345 | #define BFM_SFC_SCR_CLR_RREQ(v) BM_SFC_SCR_CLR_RREQ | ||
| 346 | #define BF_SFC_SCR_CLR_RREQ_V(e) BF_SFC_SCR_CLR_RREQ(BV_SFC_SCR_CLR_RREQ__##e) | ||
| 347 | #define BFM_SFC_SCR_CLR_RREQ_V(v) BM_SFC_SCR_CLR_RREQ | ||
| 348 | #define BP_SFC_SCR_CLR_OVER 1 | ||
| 349 | #define BM_SFC_SCR_CLR_OVER 0x2 | ||
| 350 | #define BF_SFC_SCR_CLR_OVER(v) (((v) & 0x1) << 1) | ||
| 351 | #define BFM_SFC_SCR_CLR_OVER(v) BM_SFC_SCR_CLR_OVER | ||
| 352 | #define BF_SFC_SCR_CLR_OVER_V(e) BF_SFC_SCR_CLR_OVER(BV_SFC_SCR_CLR_OVER__##e) | ||
| 353 | #define BFM_SFC_SCR_CLR_OVER_V(v) BM_SFC_SCR_CLR_OVER | ||
| 354 | #define BP_SFC_SCR_CLR_UNDER 0 | ||
| 355 | #define BM_SFC_SCR_CLR_UNDER 0x1 | ||
| 356 | #define BF_SFC_SCR_CLR_UNDER(v) (((v) & 0x1) << 0) | ||
| 357 | #define BFM_SFC_SCR_CLR_UNDER(v) BM_SFC_SCR_CLR_UNDER | ||
| 358 | #define BF_SFC_SCR_CLR_UNDER_V(e) BF_SFC_SCR_CLR_UNDER(BV_SFC_SCR_CLR_UNDER__##e) | ||
| 359 | #define BFM_SFC_SCR_CLR_UNDER_V(v) BM_SFC_SCR_CLR_UNDER | ||
| 360 | |||
| 361 | #define REG_SFC_INTC jz_reg(SFC_INTC) | ||
| 362 | #define JA_SFC_INTC (0xb3440000 + 0x70) | ||
| 363 | #define JT_SFC_INTC JIO_32_RW | ||
| 364 | #define JN_SFC_INTC SFC_INTC | ||
| 365 | #define JI_SFC_INTC | ||
| 366 | #define BP_SFC_INTC_MSK_END 4 | ||
| 367 | #define BM_SFC_INTC_MSK_END 0x10 | ||
| 368 | #define BF_SFC_INTC_MSK_END(v) (((v) & 0x1) << 4) | ||
| 369 | #define BFM_SFC_INTC_MSK_END(v) BM_SFC_INTC_MSK_END | ||
| 370 | #define BF_SFC_INTC_MSK_END_V(e) BF_SFC_INTC_MSK_END(BV_SFC_INTC_MSK_END__##e) | ||
| 371 | #define BFM_SFC_INTC_MSK_END_V(v) BM_SFC_INTC_MSK_END | ||
| 372 | #define BP_SFC_INTC_MSK_TREQ 3 | ||
| 373 | #define BM_SFC_INTC_MSK_TREQ 0x8 | ||
| 374 | #define BF_SFC_INTC_MSK_TREQ(v) (((v) & 0x1) << 3) | ||
| 375 | #define BFM_SFC_INTC_MSK_TREQ(v) BM_SFC_INTC_MSK_TREQ | ||
| 376 | #define BF_SFC_INTC_MSK_TREQ_V(e) BF_SFC_INTC_MSK_TREQ(BV_SFC_INTC_MSK_TREQ__##e) | ||
| 377 | #define BFM_SFC_INTC_MSK_TREQ_V(v) BM_SFC_INTC_MSK_TREQ | ||
| 378 | #define BP_SFC_INTC_MSK_RREQ 2 | ||
| 379 | #define BM_SFC_INTC_MSK_RREQ 0x4 | ||
| 380 | #define BF_SFC_INTC_MSK_RREQ(v) (((v) & 0x1) << 2) | ||
| 381 | #define BFM_SFC_INTC_MSK_RREQ(v) BM_SFC_INTC_MSK_RREQ | ||
| 382 | #define BF_SFC_INTC_MSK_RREQ_V(e) BF_SFC_INTC_MSK_RREQ(BV_SFC_INTC_MSK_RREQ__##e) | ||
| 383 | #define BFM_SFC_INTC_MSK_RREQ_V(v) BM_SFC_INTC_MSK_RREQ | ||
| 384 | #define BP_SFC_INTC_MSK_OVER 1 | ||
| 385 | #define BM_SFC_INTC_MSK_OVER 0x2 | ||
| 386 | #define BF_SFC_INTC_MSK_OVER(v) (((v) & 0x1) << 1) | ||
| 387 | #define BFM_SFC_INTC_MSK_OVER(v) BM_SFC_INTC_MSK_OVER | ||
| 388 | #define BF_SFC_INTC_MSK_OVER_V(e) BF_SFC_INTC_MSK_OVER(BV_SFC_INTC_MSK_OVER__##e) | ||
| 389 | #define BFM_SFC_INTC_MSK_OVER_V(v) BM_SFC_INTC_MSK_OVER | ||
| 390 | #define BP_SFC_INTC_MSK_UNDER 0 | ||
| 391 | #define BM_SFC_INTC_MSK_UNDER 0x1 | ||
| 392 | #define BF_SFC_INTC_MSK_UNDER(v) (((v) & 0x1) << 0) | ||
| 393 | #define BFM_SFC_INTC_MSK_UNDER(v) BM_SFC_INTC_MSK_UNDER | ||
| 394 | #define BF_SFC_INTC_MSK_UNDER_V(e) BF_SFC_INTC_MSK_UNDER(BV_SFC_INTC_MSK_UNDER__##e) | ||
| 395 | #define BFM_SFC_INTC_MSK_UNDER_V(v) BM_SFC_INTC_MSK_UNDER | ||
| 396 | |||
| 397 | #define REG_SFC_FSM jz_reg(SFC_FSM) | ||
| 398 | #define JA_SFC_FSM (0xb3440000 + 0x74) | ||
| 399 | #define JT_SFC_FSM JIO_32_RW | ||
| 400 | #define JN_SFC_FSM SFC_FSM | ||
| 401 | #define JI_SFC_FSM | ||
| 402 | #define BP_SFC_FSM_STATE_AHB 16 | ||
| 403 | #define BM_SFC_FSM_STATE_AHB 0xf0000 | ||
| 404 | #define BF_SFC_FSM_STATE_AHB(v) (((v) & 0xf) << 16) | ||
| 405 | #define BFM_SFC_FSM_STATE_AHB(v) BM_SFC_FSM_STATE_AHB | ||
| 406 | #define BF_SFC_FSM_STATE_AHB_V(e) BF_SFC_FSM_STATE_AHB(BV_SFC_FSM_STATE_AHB__##e) | ||
| 407 | #define BFM_SFC_FSM_STATE_AHB_V(v) BM_SFC_FSM_STATE_AHB | ||
| 408 | #define BP_SFC_FSM_STATE_SPI 11 | ||
| 409 | #define BM_SFC_FSM_STATE_SPI 0xf800 | ||
| 410 | #define BF_SFC_FSM_STATE_SPI(v) (((v) & 0x1f) << 11) | ||
| 411 | #define BFM_SFC_FSM_STATE_SPI(v) BM_SFC_FSM_STATE_SPI | ||
| 412 | #define BF_SFC_FSM_STATE_SPI_V(e) BF_SFC_FSM_STATE_SPI(BV_SFC_FSM_STATE_SPI__##e) | ||
| 413 | #define BFM_SFC_FSM_STATE_SPI_V(v) BM_SFC_FSM_STATE_SPI | ||
| 414 | #define BP_SFC_FSM_STATE_CLK 6 | ||
| 415 | #define BM_SFC_FSM_STATE_CLK 0x3c0 | ||
| 416 | #define BF_SFC_FSM_STATE_CLK(v) (((v) & 0xf) << 6) | ||
| 417 | #define BFM_SFC_FSM_STATE_CLK(v) BM_SFC_FSM_STATE_CLK | ||
| 418 | #define BF_SFC_FSM_STATE_CLK_V(e) BF_SFC_FSM_STATE_CLK(BV_SFC_FSM_STATE_CLK__##e) | ||
| 419 | #define BFM_SFC_FSM_STATE_CLK_V(v) BM_SFC_FSM_STATE_CLK | ||
| 420 | #define BP_SFC_FSM_STATE_DMAC 3 | ||
| 421 | #define BM_SFC_FSM_STATE_DMAC 0x38 | ||
| 422 | #define BF_SFC_FSM_STATE_DMAC(v) (((v) & 0x7) << 3) | ||
| 423 | #define BFM_SFC_FSM_STATE_DMAC(v) BM_SFC_FSM_STATE_DMAC | ||
| 424 | #define BF_SFC_FSM_STATE_DMAC_V(e) BF_SFC_FSM_STATE_DMAC(BV_SFC_FSM_STATE_DMAC__##e) | ||
| 425 | #define BFM_SFC_FSM_STATE_DMAC_V(v) BM_SFC_FSM_STATE_DMAC | ||
| 426 | #define BP_SFC_FSM_STATE_RMC 0 | ||
| 427 | #define BM_SFC_FSM_STATE_RMC 0x7 | ||
| 428 | #define BF_SFC_FSM_STATE_RMC(v) (((v) & 0x7) << 0) | ||
| 429 | #define BFM_SFC_FSM_STATE_RMC(v) BM_SFC_FSM_STATE_RMC | ||
| 430 | #define BF_SFC_FSM_STATE_RMC_V(e) BF_SFC_FSM_STATE_RMC(BV_SFC_FSM_STATE_RMC__##e) | ||
| 431 | #define BFM_SFC_FSM_STATE_RMC_V(v) BM_SFC_FSM_STATE_RMC | ||
| 432 | |||
| 433 | #define REG_SFC_CGE jz_reg(SFC_CGE) | ||
| 434 | #define JA_SFC_CGE (0xb3440000 + 0x78) | ||
| 435 | #define JT_SFC_CGE JIO_32_RW | ||
| 436 | #define JN_SFC_CGE SFC_CGE | ||
| 437 | #define JI_SFC_CGE | ||
| 438 | #define BP_SFC_CGE_SFC 5 | ||
| 439 | #define BM_SFC_CGE_SFC 0x20 | ||
| 440 | #define BF_SFC_CGE_SFC(v) (((v) & 0x1) << 5) | ||
| 441 | #define BFM_SFC_CGE_SFC(v) BM_SFC_CGE_SFC | ||
| 442 | #define BF_SFC_CGE_SFC_V(e) BF_SFC_CGE_SFC(BV_SFC_CGE_SFC__##e) | ||
| 443 | #define BFM_SFC_CGE_SFC_V(v) BM_SFC_CGE_SFC | ||
| 444 | #define BP_SFC_CGE_FIFO 4 | ||
| 445 | #define BM_SFC_CGE_FIFO 0x10 | ||
| 446 | #define BF_SFC_CGE_FIFO(v) (((v) & 0x1) << 4) | ||
| 447 | #define BFM_SFC_CGE_FIFO(v) BM_SFC_CGE_FIFO | ||
| 448 | #define BF_SFC_CGE_FIFO_V(e) BF_SFC_CGE_FIFO(BV_SFC_CGE_FIFO__##e) | ||
| 449 | #define BFM_SFC_CGE_FIFO_V(v) BM_SFC_CGE_FIFO | ||
| 450 | #define BP_SFC_CGE_DMA 3 | ||
| 451 | #define BM_SFC_CGE_DMA 0x8 | ||
| 452 | #define BF_SFC_CGE_DMA(v) (((v) & 0x1) << 3) | ||
| 453 | #define BFM_SFC_CGE_DMA(v) BM_SFC_CGE_DMA | ||
| 454 | #define BF_SFC_CGE_DMA_V(e) BF_SFC_CGE_DMA(BV_SFC_CGE_DMA__##e) | ||
| 455 | #define BFM_SFC_CGE_DMA_V(v) BM_SFC_CGE_DMA | ||
| 456 | #define BP_SFC_CGE_RMC 2 | ||
| 457 | #define BM_SFC_CGE_RMC 0x4 | ||
| 458 | #define BF_SFC_CGE_RMC(v) (((v) & 0x1) << 2) | ||
| 459 | #define BFM_SFC_CGE_RMC(v) BM_SFC_CGE_RMC | ||
| 460 | #define BF_SFC_CGE_RMC_V(e) BF_SFC_CGE_RMC(BV_SFC_CGE_RMC__##e) | ||
| 461 | #define BFM_SFC_CGE_RMC_V(v) BM_SFC_CGE_RMC | ||
| 462 | #define BP_SFC_CGE_SPI 1 | ||
| 463 | #define BM_SFC_CGE_SPI 0x2 | ||
| 464 | #define BF_SFC_CGE_SPI(v) (((v) & 0x1) << 1) | ||
| 465 | #define BFM_SFC_CGE_SPI(v) BM_SFC_CGE_SPI | ||
| 466 | #define BF_SFC_CGE_SPI_V(e) BF_SFC_CGE_SPI(BV_SFC_CGE_SPI__##e) | ||
| 467 | #define BFM_SFC_CGE_SPI_V(v) BM_SFC_CGE_SPI | ||
| 468 | #define BP_SFC_CGE_REG 0 | ||
| 469 | #define BM_SFC_CGE_REG 0x1 | ||
| 470 | #define BF_SFC_CGE_REG(v) (((v) & 0x1) << 0) | ||
| 471 | #define BFM_SFC_CGE_REG(v) BM_SFC_CGE_REG | ||
| 472 | #define BF_SFC_CGE_REG_V(e) BF_SFC_CGE_REG(BV_SFC_CGE_REG__##e) | ||
| 473 | #define BFM_SFC_CGE_REG_V(v) BM_SFC_CGE_REG | ||
| 474 | |||
| 475 | #define REG_SFC_DATA jz_reg(SFC_DATA) | ||
| 476 | #define JA_SFC_DATA (0xb3440000 + 0x1000) | ||
| 477 | #define JT_SFC_DATA JIO_32_RW | ||
| 478 | #define JN_SFC_DATA SFC_DATA | ||
| 479 | #define JI_SFC_DATA | ||
| 480 | |||
| 481 | #endif /* __HEADERGEN_SFC_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/tcu.h b/firmware/target/mips/ingenic_x1000/x1000/tcu.h new file mode 100644 index 0000000000..9f00692660 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/tcu.h | |||
| @@ -0,0 +1,192 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_TCU_H__ | ||
| 25 | #define __HEADERGEN_TCU_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_TCU_STATUS jz_reg(TCU_STATUS) | ||
| 30 | #define JA_TCU_STATUS (0xb0002000 + 0xf0) | ||
| 31 | #define JT_TCU_STATUS JIO_32_RW | ||
| 32 | #define JN_TCU_STATUS TCU_STATUS | ||
| 33 | #define JI_TCU_STATUS | ||
| 34 | #define REG_TCU_STATUS_SET jz_reg(TCU_STATUS_SET) | ||
| 35 | #define JA_TCU_STATUS_SET (JA_TCU_STATUS + 0x4) | ||
| 36 | #define JT_TCU_STATUS_SET JIO_32_WO | ||
| 37 | #define JN_TCU_STATUS_SET TCU_STATUS | ||
| 38 | #define JI_TCU_STATUS_SET | ||
| 39 | #define REG_TCU_STATUS_CLR jz_reg(TCU_STATUS_CLR) | ||
| 40 | #define JA_TCU_STATUS_CLR (JA_TCU_STATUS + 0x8) | ||
| 41 | #define JT_TCU_STATUS_CLR JIO_32_WO | ||
| 42 | #define JN_TCU_STATUS_CLR TCU_STATUS | ||
| 43 | #define JI_TCU_STATUS_CLR | ||
| 44 | |||
| 45 | #define REG_TCU_STOP jz_reg(TCU_STOP) | ||
| 46 | #define JA_TCU_STOP (0xb0002000 + 0x1c) | ||
| 47 | #define JT_TCU_STOP JIO_32_RW | ||
| 48 | #define JN_TCU_STOP TCU_STOP | ||
| 49 | #define JI_TCU_STOP | ||
| 50 | #define REG_TCU_STOP_SET jz_reg(TCU_STOP_SET) | ||
| 51 | #define JA_TCU_STOP_SET (JA_TCU_STOP + 0x10) | ||
| 52 | #define JT_TCU_STOP_SET JIO_32_WO | ||
| 53 | #define JN_TCU_STOP_SET TCU_STOP | ||
| 54 | #define JI_TCU_STOP_SET | ||
| 55 | #define REG_TCU_STOP_CLR jz_reg(TCU_STOP_CLR) | ||
| 56 | #define JA_TCU_STOP_CLR (JA_TCU_STOP + 0x20) | ||
| 57 | #define JT_TCU_STOP_CLR JIO_32_WO | ||
| 58 | #define JN_TCU_STOP_CLR TCU_STOP | ||
| 59 | #define JI_TCU_STOP_CLR | ||
| 60 | |||
| 61 | #define REG_TCU_ENABLE jz_reg(TCU_ENABLE) | ||
| 62 | #define JA_TCU_ENABLE (0xb0002000 + 0x10) | ||
| 63 | #define JT_TCU_ENABLE JIO_32_RW | ||
| 64 | #define JN_TCU_ENABLE TCU_ENABLE | ||
| 65 | #define JI_TCU_ENABLE | ||
| 66 | #define REG_TCU_ENABLE_SET jz_reg(TCU_ENABLE_SET) | ||
| 67 | #define JA_TCU_ENABLE_SET (JA_TCU_ENABLE + 0x4) | ||
| 68 | #define JT_TCU_ENABLE_SET JIO_32_WO | ||
| 69 | #define JN_TCU_ENABLE_SET TCU_ENABLE | ||
| 70 | #define JI_TCU_ENABLE_SET | ||
| 71 | #define REG_TCU_ENABLE_CLR jz_reg(TCU_ENABLE_CLR) | ||
| 72 | #define JA_TCU_ENABLE_CLR (JA_TCU_ENABLE + 0x8) | ||
| 73 | #define JT_TCU_ENABLE_CLR JIO_32_WO | ||
| 74 | #define JN_TCU_ENABLE_CLR TCU_ENABLE | ||
| 75 | #define JI_TCU_ENABLE_CLR | ||
| 76 | |||
| 77 | #define REG_TCU_FLAG jz_reg(TCU_FLAG) | ||
| 78 | #define JA_TCU_FLAG (0xb0002000 + 0x20) | ||
| 79 | #define JT_TCU_FLAG JIO_32_RW | ||
| 80 | #define JN_TCU_FLAG TCU_FLAG | ||
| 81 | #define JI_TCU_FLAG | ||
| 82 | #define REG_TCU_FLAG_SET jz_reg(TCU_FLAG_SET) | ||
| 83 | #define JA_TCU_FLAG_SET (JA_TCU_FLAG + 0x4) | ||
| 84 | #define JT_TCU_FLAG_SET JIO_32_WO | ||
| 85 | #define JN_TCU_FLAG_SET TCU_FLAG | ||
| 86 | #define JI_TCU_FLAG_SET | ||
| 87 | #define REG_TCU_FLAG_CLR jz_reg(TCU_FLAG_CLR) | ||
| 88 | #define JA_TCU_FLAG_CLR (JA_TCU_FLAG + 0x8) | ||
| 89 | #define JT_TCU_FLAG_CLR JIO_32_WO | ||
| 90 | #define JN_TCU_FLAG_CLR TCU_FLAG | ||
| 91 | #define JI_TCU_FLAG_CLR | ||
| 92 | |||
| 93 | #define REG_TCU_MASK jz_reg(TCU_MASK) | ||
| 94 | #define JA_TCU_MASK (0xb0002000 + 0x30) | ||
| 95 | #define JT_TCU_MASK JIO_32_RW | ||
| 96 | #define JN_TCU_MASK TCU_MASK | ||
| 97 | #define JI_TCU_MASK | ||
| 98 | #define REG_TCU_MASK_SET jz_reg(TCU_MASK_SET) | ||
| 99 | #define JA_TCU_MASK_SET (JA_TCU_MASK + 0x4) | ||
| 100 | #define JT_TCU_MASK_SET JIO_32_WO | ||
| 101 | #define JN_TCU_MASK_SET TCU_MASK | ||
| 102 | #define JI_TCU_MASK_SET | ||
| 103 | #define REG_TCU_MASK_CLR jz_reg(TCU_MASK_CLR) | ||
| 104 | #define JA_TCU_MASK_CLR (JA_TCU_MASK + 0x8) | ||
| 105 | #define JT_TCU_MASK_CLR JIO_32_WO | ||
| 106 | #define JN_TCU_MASK_CLR TCU_MASK | ||
| 107 | #define JI_TCU_MASK_CLR | ||
| 108 | |||
| 109 | #define REG_TCU_CMP_FULL(_n1) jz_reg(TCU_CMP_FULL(_n1)) | ||
| 110 | #define JA_TCU_CMP_FULL(_n1) (0xb0002000 + 0x40 + (_n1) * 0x10) | ||
| 111 | #define JT_TCU_CMP_FULL(_n1) JIO_32_RW | ||
| 112 | #define JN_TCU_CMP_FULL(_n1) TCU_CMP_FULL | ||
| 113 | #define JI_TCU_CMP_FULL(_n1) (_n1) | ||
| 114 | |||
| 115 | #define REG_TCU_CMP_HALF(_n1) jz_reg(TCU_CMP_HALF(_n1)) | ||
| 116 | #define JA_TCU_CMP_HALF(_n1) (0xb0002000 + 0x44 + (_n1) * 0x10) | ||
| 117 | #define JT_TCU_CMP_HALF(_n1) JIO_32_RW | ||
| 118 | #define JN_TCU_CMP_HALF(_n1) TCU_CMP_HALF | ||
| 119 | #define JI_TCU_CMP_HALF(_n1) (_n1) | ||
| 120 | |||
| 121 | #define REG_TCU_COUNT(_n1) jz_reg(TCU_COUNT(_n1)) | ||
| 122 | #define JA_TCU_COUNT(_n1) (0xb0002000 + 0x48 + (_n1) * 0x10) | ||
| 123 | #define JT_TCU_COUNT(_n1) JIO_32_RW | ||
| 124 | #define JN_TCU_COUNT(_n1) TCU_COUNT | ||
| 125 | #define JI_TCU_COUNT(_n1) (_n1) | ||
| 126 | |||
| 127 | #define REG_TCU_CTRL(_n1) jz_reg(TCU_CTRL(_n1)) | ||
| 128 | #define JA_TCU_CTRL(_n1) (0xb0002000 + 0x4c + (_n1) * 0x10) | ||
| 129 | #define JT_TCU_CTRL(_n1) JIO_32_RW | ||
| 130 | #define JN_TCU_CTRL(_n1) TCU_CTRL | ||
| 131 | #define JI_TCU_CTRL(_n1) (_n1) | ||
| 132 | #define BP_TCU_CTRL_PRESCALE 3 | ||
| 133 | #define BM_TCU_CTRL_PRESCALE 0x38 | ||
| 134 | #define BV_TCU_CTRL_PRESCALE__BY_1 0x0 | ||
| 135 | #define BV_TCU_CTRL_PRESCALE__BY_4 0x1 | ||
| 136 | #define BV_TCU_CTRL_PRESCALE__BY_16 0x2 | ||
| 137 | #define BV_TCU_CTRL_PRESCALE__BY_64 0x3 | ||
| 138 | #define BV_TCU_CTRL_PRESCALE__BY_256 0x4 | ||
| 139 | #define BV_TCU_CTRL_PRESCALE__BY_1024 0x5 | ||
| 140 | #define BF_TCU_CTRL_PRESCALE(v) (((v) & 0x7) << 3) | ||
| 141 | #define BFM_TCU_CTRL_PRESCALE(v) BM_TCU_CTRL_PRESCALE | ||
| 142 | #define BF_TCU_CTRL_PRESCALE_V(e) BF_TCU_CTRL_PRESCALE(BV_TCU_CTRL_PRESCALE__##e) | ||
| 143 | #define BFM_TCU_CTRL_PRESCALE_V(v) BM_TCU_CTRL_PRESCALE | ||
| 144 | #define BP_TCU_CTRL_SOURCE 0 | ||
| 145 | #define BM_TCU_CTRL_SOURCE 0x7 | ||
| 146 | #define BV_TCU_CTRL_SOURCE__EXT 0x4 | ||
| 147 | #define BV_TCU_CTRL_SOURCE__RTC 0x2 | ||
| 148 | #define BV_TCU_CTRL_SOURCE__PCLK 0x1 | ||
| 149 | #define BF_TCU_CTRL_SOURCE(v) (((v) & 0x7) << 0) | ||
| 150 | #define BFM_TCU_CTRL_SOURCE(v) BM_TCU_CTRL_SOURCE | ||
| 151 | #define BF_TCU_CTRL_SOURCE_V(e) BF_TCU_CTRL_SOURCE(BV_TCU_CTRL_SOURCE__##e) | ||
| 152 | #define BFM_TCU_CTRL_SOURCE_V(v) BM_TCU_CTRL_SOURCE | ||
| 153 | #define BP_TCU_CTRL_BYPASS 11 | ||
| 154 | #define BM_TCU_CTRL_BYPASS 0x800 | ||
| 155 | #define BF_TCU_CTRL_BYPASS(v) (((v) & 0x1) << 11) | ||
| 156 | #define BFM_TCU_CTRL_BYPASS(v) BM_TCU_CTRL_BYPASS | ||
| 157 | #define BF_TCU_CTRL_BYPASS_V(e) BF_TCU_CTRL_BYPASS(BV_TCU_CTRL_BYPASS__##e) | ||
| 158 | #define BFM_TCU_CTRL_BYPASS_V(v) BM_TCU_CTRL_BYPASS | ||
| 159 | #define BP_TCU_CTRL_CLRZ 10 | ||
| 160 | #define BM_TCU_CTRL_CLRZ 0x400 | ||
| 161 | #define BF_TCU_CTRL_CLRZ(v) (((v) & 0x1) << 10) | ||
| 162 | #define BFM_TCU_CTRL_CLRZ(v) BM_TCU_CTRL_CLRZ | ||
| 163 | #define BF_TCU_CTRL_CLRZ_V(e) BF_TCU_CTRL_CLRZ(BV_TCU_CTRL_CLRZ__##e) | ||
| 164 | #define BFM_TCU_CTRL_CLRZ_V(v) BM_TCU_CTRL_CLRZ | ||
| 165 | #define BP_TCU_CTRL_SHUTDOWN 9 | ||
| 166 | #define BM_TCU_CTRL_SHUTDOWN 0x200 | ||
| 167 | #define BV_TCU_CTRL_SHUTDOWN__GRACEFUL 0x0 | ||
| 168 | #define BV_TCU_CTRL_SHUTDOWN__ABRUPT 0x1 | ||
| 169 | #define BF_TCU_CTRL_SHUTDOWN(v) (((v) & 0x1) << 9) | ||
| 170 | #define BFM_TCU_CTRL_SHUTDOWN(v) BM_TCU_CTRL_SHUTDOWN | ||
| 171 | #define BF_TCU_CTRL_SHUTDOWN_V(e) BF_TCU_CTRL_SHUTDOWN(BV_TCU_CTRL_SHUTDOWN__##e) | ||
| 172 | #define BFM_TCU_CTRL_SHUTDOWN_V(v) BM_TCU_CTRL_SHUTDOWN | ||
| 173 | #define BP_TCU_CTRL_INIT_LVL 8 | ||
| 174 | #define BM_TCU_CTRL_INIT_LVL 0x100 | ||
| 175 | #define BF_TCU_CTRL_INIT_LVL(v) (((v) & 0x1) << 8) | ||
| 176 | #define BFM_TCU_CTRL_INIT_LVL(v) BM_TCU_CTRL_INIT_LVL | ||
| 177 | #define BF_TCU_CTRL_INIT_LVL_V(e) BF_TCU_CTRL_INIT_LVL(BV_TCU_CTRL_INIT_LVL__##e) | ||
| 178 | #define BFM_TCU_CTRL_INIT_LVL_V(v) BM_TCU_CTRL_INIT_LVL | ||
| 179 | #define BP_TCU_CTRL_PWM_EN 7 | ||
| 180 | #define BM_TCU_CTRL_PWM_EN 0x80 | ||
| 181 | #define BF_TCU_CTRL_PWM_EN(v) (((v) & 0x1) << 7) | ||
| 182 | #define BFM_TCU_CTRL_PWM_EN(v) BM_TCU_CTRL_PWM_EN | ||
| 183 | #define BF_TCU_CTRL_PWM_EN_V(e) BF_TCU_CTRL_PWM_EN(BV_TCU_CTRL_PWM_EN__##e) | ||
| 184 | #define BFM_TCU_CTRL_PWM_EN_V(v) BM_TCU_CTRL_PWM_EN | ||
| 185 | #define BP_TCU_CTRL_PWM_IN_EN 6 | ||
| 186 | #define BM_TCU_CTRL_PWM_IN_EN 0x40 | ||
| 187 | #define BF_TCU_CTRL_PWM_IN_EN(v) (((v) & 0x1) << 6) | ||
| 188 | #define BFM_TCU_CTRL_PWM_IN_EN(v) BM_TCU_CTRL_PWM_IN_EN | ||
| 189 | #define BF_TCU_CTRL_PWM_IN_EN_V(e) BF_TCU_CTRL_PWM_IN_EN(BV_TCU_CTRL_PWM_IN_EN__##e) | ||
| 190 | #define BFM_TCU_CTRL_PWM_IN_EN_V(v) BM_TCU_CTRL_PWM_IN_EN | ||
| 191 | |||
| 192 | #endif /* __HEADERGEN_TCU_H__*/ | ||
diff --git a/firmware/target/mips/ingenic_x1000/x1000/wdt.h b/firmware/target/mips/ingenic_x1000/x1000/wdt.h new file mode 100644 index 0000000000..53225e3d7c --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/wdt.h | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 3.0.0 | ||
| 10 | * x1000 version: 1.0 | ||
| 11 | * x1000 authors: Aidan MacDonald | ||
| 12 | * | ||
| 13 | * Copyright (C) 2015 by the authors | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or | ||
| 16 | * modify it under the terms of the GNU General Public License | ||
| 17 | * as published by the Free Software Foundation; either version 2 | ||
| 18 | * of the License, or (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 21 | * KIND, either express or implied. | ||
| 22 | * | ||
| 23 | ****************************************************************************/ | ||
| 24 | #ifndef __HEADERGEN_WDT_H__ | ||
| 25 | #define __HEADERGEN_WDT_H__ | ||
| 26 | |||
| 27 | #include "macro.h" | ||
| 28 | |||
| 29 | #define REG_WDT_DATA jz_reg(WDT_DATA) | ||
| 30 | #define JA_WDT_DATA (0xb0002000 + 0x0) | ||
| 31 | #define JT_WDT_DATA JIO_32_RW | ||
| 32 | #define JN_WDT_DATA WDT_DATA | ||
| 33 | #define JI_WDT_DATA | ||
| 34 | |||
| 35 | #define REG_WDT_ENABLE jz_reg(WDT_ENABLE) | ||
| 36 | #define JA_WDT_ENABLE (0xb0002000 + 0x4) | ||
| 37 | #define JT_WDT_ENABLE JIO_32_RW | ||
| 38 | #define JN_WDT_ENABLE WDT_ENABLE | ||
| 39 | #define JI_WDT_ENABLE | ||
| 40 | |||
| 41 | #define REG_WDT_COUNT jz_reg(WDT_COUNT) | ||
| 42 | #define JA_WDT_COUNT (0xb0002000 + 0x8) | ||
| 43 | #define JT_WDT_COUNT JIO_32_RW | ||
| 44 | #define JN_WDT_COUNT WDT_COUNT | ||
| 45 | #define JI_WDT_COUNT | ||
| 46 | |||
| 47 | #define REG_WDT_CTRL jz_reg(WDT_CTRL) | ||
| 48 | #define JA_WDT_CTRL (0xb0002000 + 0xc) | ||
| 49 | #define JT_WDT_CTRL JIO_32_RW | ||
| 50 | #define JN_WDT_CTRL WDT_CTRL | ||
| 51 | #define JI_WDT_CTRL | ||
| 52 | #define BP_WDT_CTRL_PRESCALE 3 | ||
| 53 | #define BM_WDT_CTRL_PRESCALE 0x38 | ||
| 54 | #define BV_WDT_CTRL_PRESCALE__BY_1 0x0 | ||
| 55 | #define BV_WDT_CTRL_PRESCALE__BY_4 0x1 | ||
| 56 | #define BV_WDT_CTRL_PRESCALE__BY_16 0x2 | ||
| 57 | #define BV_WDT_CTRL_PRESCALE__BY_64 0x3 | ||
| 58 | #define BV_WDT_CTRL_PRESCALE__BY_256 0x4 | ||
| 59 | #define BV_WDT_CTRL_PRESCALE__BY_1024 0x5 | ||
| 60 | #define BF_WDT_CTRL_PRESCALE(v) (((v) & 0x7) << 3) | ||
| 61 | #define BFM_WDT_CTRL_PRESCALE(v) BM_WDT_CTRL_PRESCALE | ||
| 62 | #define BF_WDT_CTRL_PRESCALE_V(e) BF_WDT_CTRL_PRESCALE(BV_WDT_CTRL_PRESCALE__##e) | ||
| 63 | #define BFM_WDT_CTRL_PRESCALE_V(v) BM_WDT_CTRL_PRESCALE | ||
| 64 | #define BP_WDT_CTRL_SOURCE 0 | ||
| 65 | #define BM_WDT_CTRL_SOURCE 0x7 | ||
| 66 | #define BV_WDT_CTRL_SOURCE__EXT 0x4 | ||
| 67 | #define BV_WDT_CTRL_SOURCE__RTC 0x2 | ||
| 68 | #define BV_WDT_CTRL_SOURCE__PLCK 0x1 | ||
| 69 | #define BF_WDT_CTRL_SOURCE(v) (((v) & 0x7) << 0) | ||
| 70 | #define BFM_WDT_CTRL_SOURCE(v) BM_WDT_CTRL_SOURCE | ||
| 71 | #define BF_WDT_CTRL_SOURCE_V(e) BF_WDT_CTRL_SOURCE(BV_WDT_CTRL_SOURCE__##e) | ||
| 72 | #define BFM_WDT_CTRL_SOURCE_V(v) BM_WDT_CTRL_SOURCE | ||
| 73 | |||
| 74 | #endif /* __HEADERGEN_WDT_H__*/ | ||