diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/aic.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/aic.h | 359 |
1 files changed, 359 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/aic.h b/firmware/target/mips/ingenic_x1000/x1000/aic.h new file mode 100644 index 0000000000..e9c68511d7 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/aic.h | |||
@@ -0,0 +1,359 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_AIC_H__ | ||
25 | #define __HEADERGEN_AIC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_AIC_CFG jz_reg(AIC_CFG) | ||
30 | #define JA_AIC_CFG (0xb0020000 + 0x0) | ||
31 | #define JT_AIC_CFG JIO_32_RW | ||
32 | #define JN_AIC_CFG AIC_CFG | ||
33 | #define JI_AIC_CFG | ||
34 | #define BP_AIC_CFG_RFTH 24 | ||
35 | #define BM_AIC_CFG_RFTH 0xf000000 | ||
36 | #define BF_AIC_CFG_RFTH(v) (((v) & 0xf) << 24) | ||
37 | #define BFM_AIC_CFG_RFTH(v) BM_AIC_CFG_RFTH | ||
38 | #define BF_AIC_CFG_RFTH_V(e) BF_AIC_CFG_RFTH(BV_AIC_CFG_RFTH__##e) | ||
39 | #define BFM_AIC_CFG_RFTH_V(v) BM_AIC_CFG_RFTH | ||
40 | #define BP_AIC_CFG_TFTH 16 | ||
41 | #define BM_AIC_CFG_TFTH 0x1f0000 | ||
42 | #define BF_AIC_CFG_TFTH(v) (((v) & 0x1f) << 16) | ||
43 | #define BFM_AIC_CFG_TFTH(v) BM_AIC_CFG_TFTH | ||
44 | #define BF_AIC_CFG_TFTH_V(e) BF_AIC_CFG_TFTH(BV_AIC_CFG_TFTH__##e) | ||
45 | #define BFM_AIC_CFG_TFTH_V(v) BM_AIC_CFG_TFTH | ||
46 | #define BP_AIC_CFG_MSB 12 | ||
47 | #define BM_AIC_CFG_MSB 0x1000 | ||
48 | #define BF_AIC_CFG_MSB(v) (((v) & 0x1) << 12) | ||
49 | #define BFM_AIC_CFG_MSB(v) BM_AIC_CFG_MSB | ||
50 | #define BF_AIC_CFG_MSB_V(e) BF_AIC_CFG_MSB(BV_AIC_CFG_MSB__##e) | ||
51 | #define BFM_AIC_CFG_MSB_V(v) BM_AIC_CFG_MSB | ||
52 | #define BP_AIC_CFG_IBCKD 10 | ||
53 | #define BM_AIC_CFG_IBCKD 0x400 | ||
54 | #define BF_AIC_CFG_IBCKD(v) (((v) & 0x1) << 10) | ||
55 | #define BFM_AIC_CFG_IBCKD(v) BM_AIC_CFG_IBCKD | ||
56 | #define BF_AIC_CFG_IBCKD_V(e) BF_AIC_CFG_IBCKD(BV_AIC_CFG_IBCKD__##e) | ||
57 | #define BFM_AIC_CFG_IBCKD_V(v) BM_AIC_CFG_IBCKD | ||
58 | #define BP_AIC_CFG_ISYNCD 9 | ||
59 | #define BM_AIC_CFG_ISYNCD 0x200 | ||
60 | #define BF_AIC_CFG_ISYNCD(v) (((v) & 0x1) << 9) | ||
61 | #define BFM_AIC_CFG_ISYNCD(v) BM_AIC_CFG_ISYNCD | ||
62 | #define BF_AIC_CFG_ISYNCD_V(e) BF_AIC_CFG_ISYNCD(BV_AIC_CFG_ISYNCD__##e) | ||
63 | #define BFM_AIC_CFG_ISYNCD_V(v) BM_AIC_CFG_ISYNCD | ||
64 | #define BP_AIC_CFG_DMODE 8 | ||
65 | #define BM_AIC_CFG_DMODE 0x100 | ||
66 | #define BF_AIC_CFG_DMODE(v) (((v) & 0x1) << 8) | ||
67 | #define BFM_AIC_CFG_DMODE(v) BM_AIC_CFG_DMODE | ||
68 | #define BF_AIC_CFG_DMODE_V(e) BF_AIC_CFG_DMODE(BV_AIC_CFG_DMODE__##e) | ||
69 | #define BFM_AIC_CFG_DMODE_V(v) BM_AIC_CFG_DMODE | ||
70 | #define BP_AIC_CFG_CDC_SLAVE 7 | ||
71 | #define BM_AIC_CFG_CDC_SLAVE 0x80 | ||
72 | #define BF_AIC_CFG_CDC_SLAVE(v) (((v) & 0x1) << 7) | ||
73 | #define BFM_AIC_CFG_CDC_SLAVE(v) BM_AIC_CFG_CDC_SLAVE | ||
74 | #define BF_AIC_CFG_CDC_SLAVE_V(e) BF_AIC_CFG_CDC_SLAVE(BV_AIC_CFG_CDC_SLAVE__##e) | ||
75 | #define BFM_AIC_CFG_CDC_SLAVE_V(v) BM_AIC_CFG_CDC_SLAVE | ||
76 | #define BP_AIC_CFG_LSMP 6 | ||
77 | #define BM_AIC_CFG_LSMP 0x40 | ||
78 | #define BF_AIC_CFG_LSMP(v) (((v) & 0x1) << 6) | ||
79 | #define BFM_AIC_CFG_LSMP(v) BM_AIC_CFG_LSMP | ||
80 | #define BF_AIC_CFG_LSMP_V(e) BF_AIC_CFG_LSMP(BV_AIC_CFG_LSMP__##e) | ||
81 | #define BFM_AIC_CFG_LSMP_V(v) BM_AIC_CFG_LSMP | ||
82 | #define BP_AIC_CFG_ICDC 5 | ||
83 | #define BM_AIC_CFG_ICDC 0x20 | ||
84 | #define BF_AIC_CFG_ICDC(v) (((v) & 0x1) << 5) | ||
85 | #define BFM_AIC_CFG_ICDC(v) BM_AIC_CFG_ICDC | ||
86 | #define BF_AIC_CFG_ICDC_V(e) BF_AIC_CFG_ICDC(BV_AIC_CFG_ICDC__##e) | ||
87 | #define BFM_AIC_CFG_ICDC_V(v) BM_AIC_CFG_ICDC | ||
88 | #define BP_AIC_CFG_AUSEL 4 | ||
89 | #define BM_AIC_CFG_AUSEL 0x10 | ||
90 | #define BF_AIC_CFG_AUSEL(v) (((v) & 0x1) << 4) | ||
91 | #define BFM_AIC_CFG_AUSEL(v) BM_AIC_CFG_AUSEL | ||
92 | #define BF_AIC_CFG_AUSEL_V(e) BF_AIC_CFG_AUSEL(BV_AIC_CFG_AUSEL__##e) | ||
93 | #define BFM_AIC_CFG_AUSEL_V(v) BM_AIC_CFG_AUSEL | ||
94 | #define BP_AIC_CFG_RST 3 | ||
95 | #define BM_AIC_CFG_RST 0x8 | ||
96 | #define BF_AIC_CFG_RST(v) (((v) & 0x1) << 3) | ||
97 | #define BFM_AIC_CFG_RST(v) BM_AIC_CFG_RST | ||
98 | #define BF_AIC_CFG_RST_V(e) BF_AIC_CFG_RST(BV_AIC_CFG_RST__##e) | ||
99 | #define BFM_AIC_CFG_RST_V(v) BM_AIC_CFG_RST | ||
100 | #define BP_AIC_CFG_BCKD 2 | ||
101 | #define BM_AIC_CFG_BCKD 0x4 | ||
102 | #define BF_AIC_CFG_BCKD(v) (((v) & 0x1) << 2) | ||
103 | #define BFM_AIC_CFG_BCKD(v) BM_AIC_CFG_BCKD | ||
104 | #define BF_AIC_CFG_BCKD_V(e) BF_AIC_CFG_BCKD(BV_AIC_CFG_BCKD__##e) | ||
105 | #define BFM_AIC_CFG_BCKD_V(v) BM_AIC_CFG_BCKD | ||
106 | #define BP_AIC_CFG_SYNCD 1 | ||
107 | #define BM_AIC_CFG_SYNCD 0x2 | ||
108 | #define BF_AIC_CFG_SYNCD(v) (((v) & 0x1) << 1) | ||
109 | #define BFM_AIC_CFG_SYNCD(v) BM_AIC_CFG_SYNCD | ||
110 | #define BF_AIC_CFG_SYNCD_V(e) BF_AIC_CFG_SYNCD(BV_AIC_CFG_SYNCD__##e) | ||
111 | #define BFM_AIC_CFG_SYNCD_V(v) BM_AIC_CFG_SYNCD | ||
112 | #define BP_AIC_CFG_ENABLE 0 | ||
113 | #define BM_AIC_CFG_ENABLE 0x1 | ||
114 | #define BF_AIC_CFG_ENABLE(v) (((v) & 0x1) << 0) | ||
115 | #define BFM_AIC_CFG_ENABLE(v) BM_AIC_CFG_ENABLE | ||
116 | #define BF_AIC_CFG_ENABLE_V(e) BF_AIC_CFG_ENABLE(BV_AIC_CFG_ENABLE__##e) | ||
117 | #define BFM_AIC_CFG_ENABLE_V(v) BM_AIC_CFG_ENABLE | ||
118 | |||
119 | #define REG_AIC_CCR jz_reg(AIC_CCR) | ||
120 | #define JA_AIC_CCR (0xb0020000 + 0x4) | ||
121 | #define JT_AIC_CCR JIO_32_RW | ||
122 | #define JN_AIC_CCR AIC_CCR | ||
123 | #define JI_AIC_CCR | ||
124 | #define BP_AIC_CCR_CHANNEL 24 | ||
125 | #define BM_AIC_CCR_CHANNEL 0x7000000 | ||
126 | #define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) | ||
127 | #define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL | ||
128 | #define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) | ||
129 | #define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL | ||
130 | #define BP_AIC_CCR_OSS 19 | ||
131 | #define BM_AIC_CCR_OSS 0x380000 | ||
132 | #define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) | ||
133 | #define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS | ||
134 | #define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) | ||
135 | #define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS | ||
136 | #define BP_AIC_CCR_ISS 16 | ||
137 | #define BM_AIC_CCR_ISS 0x70000 | ||
138 | #define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) | ||
139 | #define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS | ||
140 | #define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) | ||
141 | #define BFM_AIC_CCR_ISS_V(v) BM_AIC_CCR_ISS | ||
142 | #define BP_AIC_CCR_PACK16 28 | ||
143 | #define BM_AIC_CCR_PACK16 0x10000000 | ||
144 | #define BF_AIC_CCR_PACK16(v) (((v) & 0x1) << 28) | ||
145 | #define BFM_AIC_CCR_PACK16(v) BM_AIC_CCR_PACK16 | ||
146 | #define BF_AIC_CCR_PACK16_V(e) BF_AIC_CCR_PACK16(BV_AIC_CCR_PACK16__##e) | ||
147 | #define BFM_AIC_CCR_PACK16_V(v) BM_AIC_CCR_PACK16 | ||
148 | #define BP_AIC_CCR_RDMS 15 | ||
149 | #define BM_AIC_CCR_RDMS 0x8000 | ||
150 | #define BF_AIC_CCR_RDMS(v) (((v) & 0x1) << 15) | ||
151 | #define BFM_AIC_CCR_RDMS(v) BM_AIC_CCR_RDMS | ||
152 | #define BF_AIC_CCR_RDMS_V(e) BF_AIC_CCR_RDMS(BV_AIC_CCR_RDMS__##e) | ||
153 | #define BFM_AIC_CCR_RDMS_V(v) BM_AIC_CCR_RDMS | ||
154 | #define BP_AIC_CCR_TDMS 14 | ||
155 | #define BM_AIC_CCR_TDMS 0x4000 | ||
156 | #define BF_AIC_CCR_TDMS(v) (((v) & 0x1) << 14) | ||
157 | #define BFM_AIC_CCR_TDMS(v) BM_AIC_CCR_TDMS | ||
158 | #define BF_AIC_CCR_TDMS_V(e) BF_AIC_CCR_TDMS(BV_AIC_CCR_TDMS__##e) | ||
159 | #define BFM_AIC_CCR_TDMS_V(v) BM_AIC_CCR_TDMS | ||
160 | #define BP_AIC_CCR_M2S 11 | ||
161 | #define BM_AIC_CCR_M2S 0x800 | ||
162 | #define BF_AIC_CCR_M2S(v) (((v) & 0x1) << 11) | ||
163 | #define BFM_AIC_CCR_M2S(v) BM_AIC_CCR_M2S | ||
164 | #define BF_AIC_CCR_M2S_V(e) BF_AIC_CCR_M2S(BV_AIC_CCR_M2S__##e) | ||
165 | #define BFM_AIC_CCR_M2S_V(v) BM_AIC_CCR_M2S | ||
166 | #define BP_AIC_CCR_ENDSW 10 | ||
167 | #define BM_AIC_CCR_ENDSW 0x400 | ||
168 | #define BF_AIC_CCR_ENDSW(v) (((v) & 0x1) << 10) | ||
169 | #define BFM_AIC_CCR_ENDSW(v) BM_AIC_CCR_ENDSW | ||
170 | #define BF_AIC_CCR_ENDSW_V(e) BF_AIC_CCR_ENDSW(BV_AIC_CCR_ENDSW__##e) | ||
171 | #define BFM_AIC_CCR_ENDSW_V(v) BM_AIC_CCR_ENDSW | ||
172 | #define BP_AIC_CCR_ASVTSU 9 | ||
173 | #define BM_AIC_CCR_ASVTSU 0x200 | ||
174 | #define BF_AIC_CCR_ASVTSU(v) (((v) & 0x1) << 9) | ||
175 | #define BFM_AIC_CCR_ASVTSU(v) BM_AIC_CCR_ASVTSU | ||
176 | #define BF_AIC_CCR_ASVTSU_V(e) BF_AIC_CCR_ASVTSU(BV_AIC_CCR_ASVTSU__##e) | ||
177 | #define BFM_AIC_CCR_ASVTSU_V(v) BM_AIC_CCR_ASVTSU | ||
178 | #define BP_AIC_CCR_TFLUSH 8 | ||
179 | #define BM_AIC_CCR_TFLUSH 0x100 | ||
180 | #define BF_AIC_CCR_TFLUSH(v) (((v) & 0x1) << 8) | ||
181 | #define BFM_AIC_CCR_TFLUSH(v) BM_AIC_CCR_TFLUSH | ||
182 | #define BF_AIC_CCR_TFLUSH_V(e) BF_AIC_CCR_TFLUSH(BV_AIC_CCR_TFLUSH__##e) | ||
183 | #define BFM_AIC_CCR_TFLUSH_V(v) BM_AIC_CCR_TFLUSH | ||
184 | #define BP_AIC_CCR_RFLUSH 7 | ||
185 | #define BM_AIC_CCR_RFLUSH 0x80 | ||
186 | #define BF_AIC_CCR_RFLUSH(v) (((v) & 0x1) << 7) | ||
187 | #define BFM_AIC_CCR_RFLUSH(v) BM_AIC_CCR_RFLUSH | ||
188 | #define BF_AIC_CCR_RFLUSH_V(e) BF_AIC_CCR_RFLUSH(BV_AIC_CCR_RFLUSH__##e) | ||
189 | #define BFM_AIC_CCR_RFLUSH_V(v) BM_AIC_CCR_RFLUSH | ||
190 | #define BP_AIC_CCR_EROR 6 | ||
191 | #define BM_AIC_CCR_EROR 0x40 | ||
192 | #define BF_AIC_CCR_EROR(v) (((v) & 0x1) << 6) | ||
193 | #define BFM_AIC_CCR_EROR(v) BM_AIC_CCR_EROR | ||
194 | #define BF_AIC_CCR_EROR_V(e) BF_AIC_CCR_EROR(BV_AIC_CCR_EROR__##e) | ||
195 | #define BFM_AIC_CCR_EROR_V(v) BM_AIC_CCR_EROR | ||
196 | #define BP_AIC_CCR_ETUR 5 | ||
197 | #define BM_AIC_CCR_ETUR 0x20 | ||
198 | #define BF_AIC_CCR_ETUR(v) (((v) & 0x1) << 5) | ||
199 | #define BFM_AIC_CCR_ETUR(v) BM_AIC_CCR_ETUR | ||
200 | #define BF_AIC_CCR_ETUR_V(e) BF_AIC_CCR_ETUR(BV_AIC_CCR_ETUR__##e) | ||
201 | #define BFM_AIC_CCR_ETUR_V(v) BM_AIC_CCR_ETUR | ||
202 | #define BP_AIC_CCR_ERFS 4 | ||
203 | #define BM_AIC_CCR_ERFS 0x10 | ||
204 | #define BF_AIC_CCR_ERFS(v) (((v) & 0x1) << 4) | ||
205 | #define BFM_AIC_CCR_ERFS(v) BM_AIC_CCR_ERFS | ||
206 | #define BF_AIC_CCR_ERFS_V(e) BF_AIC_CCR_ERFS(BV_AIC_CCR_ERFS__##e) | ||
207 | #define BFM_AIC_CCR_ERFS_V(v) BM_AIC_CCR_ERFS | ||
208 | #define BP_AIC_CCR_ETFS 3 | ||
209 | #define BM_AIC_CCR_ETFS 0x8 | ||
210 | #define BF_AIC_CCR_ETFS(v) (((v) & 0x1) << 3) | ||
211 | #define BFM_AIC_CCR_ETFS(v) BM_AIC_CCR_ETFS | ||
212 | #define BF_AIC_CCR_ETFS_V(e) BF_AIC_CCR_ETFS(BV_AIC_CCR_ETFS__##e) | ||
213 | #define BFM_AIC_CCR_ETFS_V(v) BM_AIC_CCR_ETFS | ||
214 | #define BP_AIC_CCR_ENLBF 2 | ||
215 | #define BM_AIC_CCR_ENLBF 0x4 | ||
216 | #define BF_AIC_CCR_ENLBF(v) (((v) & 0x1) << 2) | ||
217 | #define BFM_AIC_CCR_ENLBF(v) BM_AIC_CCR_ENLBF | ||
218 | #define BF_AIC_CCR_ENLBF_V(e) BF_AIC_CCR_ENLBF(BV_AIC_CCR_ENLBF__##e) | ||
219 | #define BFM_AIC_CCR_ENLBF_V(v) BM_AIC_CCR_ENLBF | ||
220 | #define BP_AIC_CCR_ERPL 1 | ||
221 | #define BM_AIC_CCR_ERPL 0x2 | ||
222 | #define BF_AIC_CCR_ERPL(v) (((v) & 0x1) << 1) | ||
223 | #define BFM_AIC_CCR_ERPL(v) BM_AIC_CCR_ERPL | ||
224 | #define BF_AIC_CCR_ERPL_V(e) BF_AIC_CCR_ERPL(BV_AIC_CCR_ERPL__##e) | ||
225 | #define BFM_AIC_CCR_ERPL_V(v) BM_AIC_CCR_ERPL | ||
226 | #define BP_AIC_CCR_EREC 0 | ||
227 | #define BM_AIC_CCR_EREC 0x1 | ||
228 | #define BF_AIC_CCR_EREC(v) (((v) & 0x1) << 0) | ||
229 | #define BFM_AIC_CCR_EREC(v) BM_AIC_CCR_EREC | ||
230 | #define BF_AIC_CCR_EREC_V(e) BF_AIC_CCR_EREC(BV_AIC_CCR_EREC__##e) | ||
231 | #define BFM_AIC_CCR_EREC_V(v) BM_AIC_CCR_EREC | ||
232 | |||
233 | #define REG_AIC_I2SCR jz_reg(AIC_I2SCR) | ||
234 | #define JA_AIC_I2SCR (0xb0020000 + 0x10) | ||
235 | #define JT_AIC_I2SCR JIO_32_RW | ||
236 | #define JN_AIC_I2SCR AIC_I2SCR | ||
237 | #define JI_AIC_I2SCR | ||
238 | #define BP_AIC_I2SCR_RFIRST 17 | ||
239 | #define BM_AIC_I2SCR_RFIRST 0x20000 | ||
240 | #define BF_AIC_I2SCR_RFIRST(v) (((v) & 0x1) << 17) | ||
241 | #define BFM_AIC_I2SCR_RFIRST(v) BM_AIC_I2SCR_RFIRST | ||
242 | #define BF_AIC_I2SCR_RFIRST_V(e) BF_AIC_I2SCR_RFIRST(BV_AIC_I2SCR_RFIRST__##e) | ||
243 | #define BFM_AIC_I2SCR_RFIRST_V(v) BM_AIC_I2SCR_RFIRST | ||
244 | #define BP_AIC_I2SCR_SWLH 16 | ||
245 | #define BM_AIC_I2SCR_SWLH 0x10000 | ||
246 | #define BF_AIC_I2SCR_SWLH(v) (((v) & 0x1) << 16) | ||
247 | #define BFM_AIC_I2SCR_SWLH(v) BM_AIC_I2SCR_SWLH | ||
248 | #define BF_AIC_I2SCR_SWLH_V(e) BF_AIC_I2SCR_SWLH(BV_AIC_I2SCR_SWLH__##e) | ||
249 | #define BFM_AIC_I2SCR_SWLH_V(v) BM_AIC_I2SCR_SWLH | ||
250 | #define BP_AIC_I2SCR_ISTPBK 13 | ||
251 | #define BM_AIC_I2SCR_ISTPBK 0x2000 | ||
252 | #define BF_AIC_I2SCR_ISTPBK(v) (((v) & 0x1) << 13) | ||
253 | #define BFM_AIC_I2SCR_ISTPBK(v) BM_AIC_I2SCR_ISTPBK | ||
254 | #define BF_AIC_I2SCR_ISTPBK_V(e) BF_AIC_I2SCR_ISTPBK(BV_AIC_I2SCR_ISTPBK__##e) | ||
255 | #define BFM_AIC_I2SCR_ISTPBK_V(v) BM_AIC_I2SCR_ISTPBK | ||
256 | #define BP_AIC_I2SCR_STPBK 12 | ||
257 | #define BM_AIC_I2SCR_STPBK 0x1000 | ||
258 | #define BF_AIC_I2SCR_STPBK(v) (((v) & 0x1) << 12) | ||
259 | #define BFM_AIC_I2SCR_STPBK(v) BM_AIC_I2SCR_STPBK | ||
260 | #define BF_AIC_I2SCR_STPBK_V(e) BF_AIC_I2SCR_STPBK(BV_AIC_I2SCR_STPBK__##e) | ||
261 | #define BFM_AIC_I2SCR_STPBK_V(v) BM_AIC_I2SCR_STPBK | ||
262 | #define BP_AIC_I2SCR_ESCLK 4 | ||
263 | #define BM_AIC_I2SCR_ESCLK 0x10 | ||
264 | #define BF_AIC_I2SCR_ESCLK(v) (((v) & 0x1) << 4) | ||
265 | #define BFM_AIC_I2SCR_ESCLK(v) BM_AIC_I2SCR_ESCLK | ||
266 | #define BF_AIC_I2SCR_ESCLK_V(e) BF_AIC_I2SCR_ESCLK(BV_AIC_I2SCR_ESCLK__##e) | ||
267 | #define BFM_AIC_I2SCR_ESCLK_V(v) BM_AIC_I2SCR_ESCLK | ||
268 | #define BP_AIC_I2SCR_AMSL 0 | ||
269 | #define BM_AIC_I2SCR_AMSL 0x1 | ||
270 | #define BF_AIC_I2SCR_AMSL(v) (((v) & 0x1) << 0) | ||
271 | #define BFM_AIC_I2SCR_AMSL(v) BM_AIC_I2SCR_AMSL | ||
272 | #define BF_AIC_I2SCR_AMSL_V(e) BF_AIC_I2SCR_AMSL(BV_AIC_I2SCR_AMSL__##e) | ||
273 | #define BFM_AIC_I2SCR_AMSL_V(v) BM_AIC_I2SCR_AMSL | ||
274 | |||
275 | #define REG_AIC_SR jz_reg(AIC_SR) | ||
276 | #define JA_AIC_SR (0xb0020000 + 0x14) | ||
277 | #define JT_AIC_SR JIO_32_RW | ||
278 | #define JN_AIC_SR AIC_SR | ||
279 | #define JI_AIC_SR | ||
280 | #define BP_AIC_SR_RFL 24 | ||
281 | #define BM_AIC_SR_RFL 0x3f000000 | ||
282 | #define BF_AIC_SR_RFL(v) (((v) & 0x3f) << 24) | ||
283 | #define BFM_AIC_SR_RFL(v) BM_AIC_SR_RFL | ||
284 | #define BF_AIC_SR_RFL_V(e) BF_AIC_SR_RFL(BV_AIC_SR_RFL__##e) | ||
285 | #define BFM_AIC_SR_RFL_V(v) BM_AIC_SR_RFL | ||
286 | #define BP_AIC_SR_TFL 8 | ||
287 | #define BM_AIC_SR_TFL 0x3f00 | ||
288 | #define BF_AIC_SR_TFL(v) (((v) & 0x3f) << 8) | ||
289 | #define BFM_AIC_SR_TFL(v) BM_AIC_SR_TFL | ||
290 | #define BF_AIC_SR_TFL_V(e) BF_AIC_SR_TFL(BV_AIC_SR_TFL__##e) | ||
291 | #define BFM_AIC_SR_TFL_V(v) BM_AIC_SR_TFL | ||
292 | #define BP_AIC_SR_ROR 6 | ||
293 | #define BM_AIC_SR_ROR 0x40 | ||
294 | #define BF_AIC_SR_ROR(v) (((v) & 0x1) << 6) | ||
295 | #define BFM_AIC_SR_ROR(v) BM_AIC_SR_ROR | ||
296 | #define BF_AIC_SR_ROR_V(e) BF_AIC_SR_ROR(BV_AIC_SR_ROR__##e) | ||
297 | #define BFM_AIC_SR_ROR_V(v) BM_AIC_SR_ROR | ||
298 | #define BP_AIC_SR_TUR 5 | ||
299 | #define BM_AIC_SR_TUR 0x20 | ||
300 | #define BF_AIC_SR_TUR(v) (((v) & 0x1) << 5) | ||
301 | #define BFM_AIC_SR_TUR(v) BM_AIC_SR_TUR | ||
302 | #define BF_AIC_SR_TUR_V(e) BF_AIC_SR_TUR(BV_AIC_SR_TUR__##e) | ||
303 | #define BFM_AIC_SR_TUR_V(v) BM_AIC_SR_TUR | ||
304 | #define BP_AIC_SR_RFS 4 | ||
305 | #define BM_AIC_SR_RFS 0x10 | ||
306 | #define BF_AIC_SR_RFS(v) (((v) & 0x1) << 4) | ||
307 | #define BFM_AIC_SR_RFS(v) BM_AIC_SR_RFS | ||
308 | #define BF_AIC_SR_RFS_V(e) BF_AIC_SR_RFS(BV_AIC_SR_RFS__##e) | ||
309 | #define BFM_AIC_SR_RFS_V(v) BM_AIC_SR_RFS | ||
310 | #define BP_AIC_SR_TFS 3 | ||
311 | #define BM_AIC_SR_TFS 0x8 | ||
312 | #define BF_AIC_SR_TFS(v) (((v) & 0x1) << 3) | ||
313 | #define BFM_AIC_SR_TFS(v) BM_AIC_SR_TFS | ||
314 | #define BF_AIC_SR_TFS_V(e) BF_AIC_SR_TFS(BV_AIC_SR_TFS__##e) | ||
315 | #define BFM_AIC_SR_TFS_V(v) BM_AIC_SR_TFS | ||
316 | |||
317 | #define REG_AIC_I2SSR jz_reg(AIC_I2SSR) | ||
318 | #define JA_AIC_I2SSR (0xb0020000 + 0x1c) | ||
319 | #define JT_AIC_I2SSR JIO_32_RW | ||
320 | #define JN_AIC_I2SSR AIC_I2SSR | ||
321 | #define JI_AIC_I2SSR | ||
322 | #define BP_AIC_I2SSR_CHBSY 5 | ||
323 | #define BM_AIC_I2SSR_CHBSY 0x20 | ||
324 | #define BF_AIC_I2SSR_CHBSY(v) (((v) & 0x1) << 5) | ||
325 | #define BFM_AIC_I2SSR_CHBSY(v) BM_AIC_I2SSR_CHBSY | ||
326 | #define BF_AIC_I2SSR_CHBSY_V(e) BF_AIC_I2SSR_CHBSY(BV_AIC_I2SSR_CHBSY__##e) | ||
327 | #define BFM_AIC_I2SSR_CHBSY_V(v) BM_AIC_I2SSR_CHBSY | ||
328 | #define BP_AIC_I2SSR_TBSY 4 | ||
329 | #define BM_AIC_I2SSR_TBSY 0x10 | ||
330 | #define BF_AIC_I2SSR_TBSY(v) (((v) & 0x1) << 4) | ||
331 | #define BFM_AIC_I2SSR_TBSY(v) BM_AIC_I2SSR_TBSY | ||
332 | #define BF_AIC_I2SSR_TBSY_V(e) BF_AIC_I2SSR_TBSY(BV_AIC_I2SSR_TBSY__##e) | ||
333 | #define BFM_AIC_I2SSR_TBSY_V(v) BM_AIC_I2SSR_TBSY | ||
334 | #define BP_AIC_I2SSR_RBSY 3 | ||
335 | #define BM_AIC_I2SSR_RBSY 0x8 | ||
336 | #define BF_AIC_I2SSR_RBSY(v) (((v) & 0x1) << 3) | ||
337 | #define BFM_AIC_I2SSR_RBSY(v) BM_AIC_I2SSR_RBSY | ||
338 | #define BF_AIC_I2SSR_RBSY_V(e) BF_AIC_I2SSR_RBSY(BV_AIC_I2SSR_RBSY__##e) | ||
339 | #define BFM_AIC_I2SSR_RBSY_V(v) BM_AIC_I2SSR_RBSY | ||
340 | #define BP_AIC_I2SSR_BSY 2 | ||
341 | #define BM_AIC_I2SSR_BSY 0x4 | ||
342 | #define BF_AIC_I2SSR_BSY(v) (((v) & 0x1) << 2) | ||
343 | #define BFM_AIC_I2SSR_BSY(v) BM_AIC_I2SSR_BSY | ||
344 | #define BF_AIC_I2SSR_BSY_V(e) BF_AIC_I2SSR_BSY(BV_AIC_I2SSR_BSY__##e) | ||
345 | #define BFM_AIC_I2SSR_BSY_V(v) BM_AIC_I2SSR_BSY | ||
346 | |||
347 | #define REG_AIC_I2SDIV jz_reg(AIC_I2SDIV) | ||
348 | #define JA_AIC_I2SDIV (0xb0020000 + 0x30) | ||
349 | #define JT_AIC_I2SDIV JIO_32_RW | ||
350 | #define JN_AIC_I2SDIV AIC_I2SDIV | ||
351 | #define JI_AIC_I2SDIV | ||
352 | |||
353 | #define REG_AIC_DR jz_reg(AIC_DR) | ||
354 | #define JA_AIC_DR (0xb0020000 + 0x34) | ||
355 | #define JT_AIC_DR JIO_32_RW | ||
356 | #define JN_AIC_DR AIC_DR | ||
357 | #define JI_AIC_DR | ||
358 | |||
359 | #endif /* __HEADERGEN_AIC_H__*/ | ||