diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/msc.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/msc.h | 824 |
1 files changed, 824 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/msc.h b/firmware/target/mips/ingenic_x1000/x1000/msc.h new file mode 100644 index 0000000000..762b4b1461 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/msc.h | |||
@@ -0,0 +1,824 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_MSC_H__ | ||
25 | #define __HEADERGEN_MSC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_MSC_CTRL(_n1) jz_reg(MSC_CTRL(_n1)) | ||
30 | #define JA_MSC_CTRL(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x0) | ||
31 | #define JT_MSC_CTRL(_n1) JIO_32_RW | ||
32 | #define JN_MSC_CTRL(_n1) MSC_CTRL | ||
33 | #define JI_MSC_CTRL(_n1) (_n1) | ||
34 | #define BP_MSC_CTRL_CLOCK 0 | ||
35 | #define BM_MSC_CTRL_CLOCK 0x3 | ||
36 | #define BV_MSC_CTRL_CLOCK__DO_NOTHING 0x0 | ||
37 | #define BV_MSC_CTRL_CLOCK__STOP 0x1 | ||
38 | #define BV_MSC_CTRL_CLOCK__START 0x2 | ||
39 | #define BF_MSC_CTRL_CLOCK(v) (((v) & 0x3) << 0) | ||
40 | #define BFM_MSC_CTRL_CLOCK(v) BM_MSC_CTRL_CLOCK | ||
41 | #define BF_MSC_CTRL_CLOCK_V(e) BF_MSC_CTRL_CLOCK(BV_MSC_CTRL_CLOCK__##e) | ||
42 | #define BFM_MSC_CTRL_CLOCK_V(v) BM_MSC_CTRL_CLOCK | ||
43 | #define BP_MSC_CTRL_SEND_CCSD 15 | ||
44 | #define BM_MSC_CTRL_SEND_CCSD 0x8000 | ||
45 | #define BF_MSC_CTRL_SEND_CCSD(v) (((v) & 0x1) << 15) | ||
46 | #define BFM_MSC_CTRL_SEND_CCSD(v) BM_MSC_CTRL_SEND_CCSD | ||
47 | #define BF_MSC_CTRL_SEND_CCSD_V(e) BF_MSC_CTRL_SEND_CCSD(BV_MSC_CTRL_SEND_CCSD__##e) | ||
48 | #define BFM_MSC_CTRL_SEND_CCSD_V(v) BM_MSC_CTRL_SEND_CCSD | ||
49 | #define BP_MSC_CTRL_SEND_AS_CCSD 14 | ||
50 | #define BM_MSC_CTRL_SEND_AS_CCSD 0x4000 | ||
51 | #define BF_MSC_CTRL_SEND_AS_CCSD(v) (((v) & 0x1) << 14) | ||
52 | #define BFM_MSC_CTRL_SEND_AS_CCSD(v) BM_MSC_CTRL_SEND_AS_CCSD | ||
53 | #define BF_MSC_CTRL_SEND_AS_CCSD_V(e) BF_MSC_CTRL_SEND_AS_CCSD(BV_MSC_CTRL_SEND_AS_CCSD__##e) | ||
54 | #define BFM_MSC_CTRL_SEND_AS_CCSD_V(v) BM_MSC_CTRL_SEND_AS_CCSD | ||
55 | #define BP_MSC_CTRL_EXIT_MULTIPLE 7 | ||
56 | #define BM_MSC_CTRL_EXIT_MULTIPLE 0x80 | ||
57 | #define BF_MSC_CTRL_EXIT_MULTIPLE(v) (((v) & 0x1) << 7) | ||
58 | #define BFM_MSC_CTRL_EXIT_MULTIPLE(v) BM_MSC_CTRL_EXIT_MULTIPLE | ||
59 | #define BF_MSC_CTRL_EXIT_MULTIPLE_V(e) BF_MSC_CTRL_EXIT_MULTIPLE(BV_MSC_CTRL_EXIT_MULTIPLE__##e) | ||
60 | #define BFM_MSC_CTRL_EXIT_MULTIPLE_V(v) BM_MSC_CTRL_EXIT_MULTIPLE | ||
61 | #define BP_MSC_CTRL_EXIT_TRANSFER 6 | ||
62 | #define BM_MSC_CTRL_EXIT_TRANSFER 0x40 | ||
63 | #define BF_MSC_CTRL_EXIT_TRANSFER(v) (((v) & 0x1) << 6) | ||
64 | #define BFM_MSC_CTRL_EXIT_TRANSFER(v) BM_MSC_CTRL_EXIT_TRANSFER | ||
65 | #define BF_MSC_CTRL_EXIT_TRANSFER_V(e) BF_MSC_CTRL_EXIT_TRANSFER(BV_MSC_CTRL_EXIT_TRANSFER__##e) | ||
66 | #define BFM_MSC_CTRL_EXIT_TRANSFER_V(v) BM_MSC_CTRL_EXIT_TRANSFER | ||
67 | #define BP_MSC_CTRL_START_READ_WAIT 5 | ||
68 | #define BM_MSC_CTRL_START_READ_WAIT 0x20 | ||
69 | #define BF_MSC_CTRL_START_READ_WAIT(v) (((v) & 0x1) << 5) | ||
70 | #define BFM_MSC_CTRL_START_READ_WAIT(v) BM_MSC_CTRL_START_READ_WAIT | ||
71 | #define BF_MSC_CTRL_START_READ_WAIT_V(e) BF_MSC_CTRL_START_READ_WAIT(BV_MSC_CTRL_START_READ_WAIT__##e) | ||
72 | #define BFM_MSC_CTRL_START_READ_WAIT_V(v) BM_MSC_CTRL_START_READ_WAIT | ||
73 | #define BP_MSC_CTRL_STOP_READ_WAIT 4 | ||
74 | #define BM_MSC_CTRL_STOP_READ_WAIT 0x10 | ||
75 | #define BF_MSC_CTRL_STOP_READ_WAIT(v) (((v) & 0x1) << 4) | ||
76 | #define BFM_MSC_CTRL_STOP_READ_WAIT(v) BM_MSC_CTRL_STOP_READ_WAIT | ||
77 | #define BF_MSC_CTRL_STOP_READ_WAIT_V(e) BF_MSC_CTRL_STOP_READ_WAIT(BV_MSC_CTRL_STOP_READ_WAIT__##e) | ||
78 | #define BFM_MSC_CTRL_STOP_READ_WAIT_V(v) BM_MSC_CTRL_STOP_READ_WAIT | ||
79 | #define BP_MSC_CTRL_RESET 3 | ||
80 | #define BM_MSC_CTRL_RESET 0x8 | ||
81 | #define BF_MSC_CTRL_RESET(v) (((v) & 0x1) << 3) | ||
82 | #define BFM_MSC_CTRL_RESET(v) BM_MSC_CTRL_RESET | ||
83 | #define BF_MSC_CTRL_RESET_V(e) BF_MSC_CTRL_RESET(BV_MSC_CTRL_RESET__##e) | ||
84 | #define BFM_MSC_CTRL_RESET_V(v) BM_MSC_CTRL_RESET | ||
85 | #define BP_MSC_CTRL_START_OP 2 | ||
86 | #define BM_MSC_CTRL_START_OP 0x4 | ||
87 | #define BF_MSC_CTRL_START_OP(v) (((v) & 0x1) << 2) | ||
88 | #define BFM_MSC_CTRL_START_OP(v) BM_MSC_CTRL_START_OP | ||
89 | #define BF_MSC_CTRL_START_OP_V(e) BF_MSC_CTRL_START_OP(BV_MSC_CTRL_START_OP__##e) | ||
90 | #define BFM_MSC_CTRL_START_OP_V(v) BM_MSC_CTRL_START_OP | ||
91 | |||
92 | #define REG_MSC_STAT(_n1) jz_reg(MSC_STAT(_n1)) | ||
93 | #define JA_MSC_STAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4) | ||
94 | #define JT_MSC_STAT(_n1) JIO_32_RW | ||
95 | #define JN_MSC_STAT(_n1) MSC_STAT | ||
96 | #define JI_MSC_STAT(_n1) (_n1) | ||
97 | #define BP_MSC_STAT_PINS 24 | ||
98 | #define BM_MSC_STAT_PINS 0x1f000000 | ||
99 | #define BF_MSC_STAT_PINS(v) (((v) & 0x1f) << 24) | ||
100 | #define BFM_MSC_STAT_PINS(v) BM_MSC_STAT_PINS | ||
101 | #define BF_MSC_STAT_PINS_V(e) BF_MSC_STAT_PINS(BV_MSC_STAT_PINS__##e) | ||
102 | #define BFM_MSC_STAT_PINS_V(v) BM_MSC_STAT_PINS | ||
103 | #define BP_MSC_STAT_CRC_WRITE_ERROR 2 | ||
104 | #define BM_MSC_STAT_CRC_WRITE_ERROR 0xc | ||
105 | #define BV_MSC_STAT_CRC_WRITE_ERROR__NONE 0x0 | ||
106 | #define BV_MSC_STAT_CRC_WRITE_ERROR__BADDATA 0x1 | ||
107 | #define BV_MSC_STAT_CRC_WRITE_ERROR__NOCRC 0x2 | ||
108 | #define BF_MSC_STAT_CRC_WRITE_ERROR(v) (((v) & 0x3) << 2) | ||
109 | #define BFM_MSC_STAT_CRC_WRITE_ERROR(v) BM_MSC_STAT_CRC_WRITE_ERROR | ||
110 | #define BF_MSC_STAT_CRC_WRITE_ERROR_V(e) BF_MSC_STAT_CRC_WRITE_ERROR(BV_MSC_STAT_CRC_WRITE_ERROR__##e) | ||
111 | #define BFM_MSC_STAT_CRC_WRITE_ERROR_V(v) BM_MSC_STAT_CRC_WRITE_ERROR | ||
112 | #define BP_MSC_STAT_AUTO_CMD12_DONE 31 | ||
113 | #define BM_MSC_STAT_AUTO_CMD12_DONE 0x80000000 | ||
114 | #define BF_MSC_STAT_AUTO_CMD12_DONE(v) (((v) & 0x1) << 31) | ||
115 | #define BFM_MSC_STAT_AUTO_CMD12_DONE(v) BM_MSC_STAT_AUTO_CMD12_DONE | ||
116 | #define BF_MSC_STAT_AUTO_CMD12_DONE_V(e) BF_MSC_STAT_AUTO_CMD12_DONE(BV_MSC_STAT_AUTO_CMD12_DONE__##e) | ||
117 | #define BFM_MSC_STAT_AUTO_CMD12_DONE_V(v) BM_MSC_STAT_AUTO_CMD12_DONE | ||
118 | #define BP_MSC_STAT_BCE 20 | ||
119 | #define BM_MSC_STAT_BCE 0x100000 | ||
120 | #define BF_MSC_STAT_BCE(v) (((v) & 0x1) << 20) | ||
121 | #define BFM_MSC_STAT_BCE(v) BM_MSC_STAT_BCE | ||
122 | #define BF_MSC_STAT_BCE_V(e) BF_MSC_STAT_BCE(BV_MSC_STAT_BCE__##e) | ||
123 | #define BFM_MSC_STAT_BCE_V(v) BM_MSC_STAT_BCE | ||
124 | #define BP_MSC_STAT_BDE 19 | ||
125 | #define BM_MSC_STAT_BDE 0x80000 | ||
126 | #define BF_MSC_STAT_BDE(v) (((v) & 0x1) << 19) | ||
127 | #define BFM_MSC_STAT_BDE(v) BM_MSC_STAT_BDE | ||
128 | #define BF_MSC_STAT_BDE_V(e) BF_MSC_STAT_BDE(BV_MSC_STAT_BDE__##e) | ||
129 | #define BFM_MSC_STAT_BDE_V(v) BM_MSC_STAT_BDE | ||
130 | #define BP_MSC_STAT_BAE 18 | ||
131 | #define BM_MSC_STAT_BAE 0x40000 | ||
132 | #define BF_MSC_STAT_BAE(v) (((v) & 0x1) << 18) | ||
133 | #define BFM_MSC_STAT_BAE(v) BM_MSC_STAT_BAE | ||
134 | #define BF_MSC_STAT_BAE_V(e) BF_MSC_STAT_BAE(BV_MSC_STAT_BAE__##e) | ||
135 | #define BFM_MSC_STAT_BAE_V(v) BM_MSC_STAT_BAE | ||
136 | #define BP_MSC_STAT_BAR 17 | ||
137 | #define BM_MSC_STAT_BAR 0x20000 | ||
138 | #define BF_MSC_STAT_BAR(v) (((v) & 0x1) << 17) | ||
139 | #define BFM_MSC_STAT_BAR(v) BM_MSC_STAT_BAR | ||
140 | #define BF_MSC_STAT_BAR_V(e) BF_MSC_STAT_BAR(BV_MSC_STAT_BAR__##e) | ||
141 | #define BFM_MSC_STAT_BAR_V(v) BM_MSC_STAT_BAR | ||
142 | #define BP_MSC_STAT_DMAEND 16 | ||
143 | #define BM_MSC_STAT_DMAEND 0x10000 | ||
144 | #define BF_MSC_STAT_DMAEND(v) (((v) & 0x1) << 16) | ||
145 | #define BFM_MSC_STAT_DMAEND(v) BM_MSC_STAT_DMAEND | ||
146 | #define BF_MSC_STAT_DMAEND_V(e) BF_MSC_STAT_DMAEND(BV_MSC_STAT_DMAEND__##e) | ||
147 | #define BFM_MSC_STAT_DMAEND_V(v) BM_MSC_STAT_DMAEND | ||
148 | #define BP_MSC_STAT_IS_RESETTING 15 | ||
149 | #define BM_MSC_STAT_IS_RESETTING 0x8000 | ||
150 | #define BF_MSC_STAT_IS_RESETTING(v) (((v) & 0x1) << 15) | ||
151 | #define BFM_MSC_STAT_IS_RESETTING(v) BM_MSC_STAT_IS_RESETTING | ||
152 | #define BF_MSC_STAT_IS_RESETTING_V(e) BF_MSC_STAT_IS_RESETTING(BV_MSC_STAT_IS_RESETTING__##e) | ||
153 | #define BFM_MSC_STAT_IS_RESETTING_V(v) BM_MSC_STAT_IS_RESETTING | ||
154 | #define BP_MSC_STAT_SDIO_INT_ACTIVE 14 | ||
155 | #define BM_MSC_STAT_SDIO_INT_ACTIVE 0x4000 | ||
156 | #define BF_MSC_STAT_SDIO_INT_ACTIVE(v) (((v) & 0x1) << 14) | ||
157 | #define BFM_MSC_STAT_SDIO_INT_ACTIVE(v) BM_MSC_STAT_SDIO_INT_ACTIVE | ||
158 | #define BF_MSC_STAT_SDIO_INT_ACTIVE_V(e) BF_MSC_STAT_SDIO_INT_ACTIVE(BV_MSC_STAT_SDIO_INT_ACTIVE__##e) | ||
159 | #define BFM_MSC_STAT_SDIO_INT_ACTIVE_V(v) BM_MSC_STAT_SDIO_INT_ACTIVE | ||
160 | #define BP_MSC_STAT_PROG_DONE 13 | ||
161 | #define BM_MSC_STAT_PROG_DONE 0x2000 | ||
162 | #define BF_MSC_STAT_PROG_DONE(v) (((v) & 0x1) << 13) | ||
163 | #define BFM_MSC_STAT_PROG_DONE(v) BM_MSC_STAT_PROG_DONE | ||
164 | #define BF_MSC_STAT_PROG_DONE_V(e) BF_MSC_STAT_PROG_DONE(BV_MSC_STAT_PROG_DONE__##e) | ||
165 | #define BFM_MSC_STAT_PROG_DONE_V(v) BM_MSC_STAT_PROG_DONE | ||
166 | #define BP_MSC_STAT_DATA_TRAN_DONE 12 | ||
167 | #define BM_MSC_STAT_DATA_TRAN_DONE 0x1000 | ||
168 | #define BF_MSC_STAT_DATA_TRAN_DONE(v) (((v) & 0x1) << 12) | ||
169 | #define BFM_MSC_STAT_DATA_TRAN_DONE(v) BM_MSC_STAT_DATA_TRAN_DONE | ||
170 | #define BF_MSC_STAT_DATA_TRAN_DONE_V(e) BF_MSC_STAT_DATA_TRAN_DONE(BV_MSC_STAT_DATA_TRAN_DONE__##e) | ||
171 | #define BFM_MSC_STAT_DATA_TRAN_DONE_V(v) BM_MSC_STAT_DATA_TRAN_DONE | ||
172 | #define BP_MSC_STAT_END_CMD_RES 11 | ||
173 | #define BM_MSC_STAT_END_CMD_RES 0x800 | ||
174 | #define BF_MSC_STAT_END_CMD_RES(v) (((v) & 0x1) << 11) | ||
175 | #define BFM_MSC_STAT_END_CMD_RES(v) BM_MSC_STAT_END_CMD_RES | ||
176 | #define BF_MSC_STAT_END_CMD_RES_V(e) BF_MSC_STAT_END_CMD_RES(BV_MSC_STAT_END_CMD_RES__##e) | ||
177 | #define BFM_MSC_STAT_END_CMD_RES_V(v) BM_MSC_STAT_END_CMD_RES | ||
178 | #define BP_MSC_STAT_DATA_FIFO_AFULL 10 | ||
179 | #define BM_MSC_STAT_DATA_FIFO_AFULL 0x400 | ||
180 | #define BF_MSC_STAT_DATA_FIFO_AFULL(v) (((v) & 0x1) << 10) | ||
181 | #define BFM_MSC_STAT_DATA_FIFO_AFULL(v) BM_MSC_STAT_DATA_FIFO_AFULL | ||
182 | #define BF_MSC_STAT_DATA_FIFO_AFULL_V(e) BF_MSC_STAT_DATA_FIFO_AFULL(BV_MSC_STAT_DATA_FIFO_AFULL__##e) | ||
183 | #define BFM_MSC_STAT_DATA_FIFO_AFULL_V(v) BM_MSC_STAT_DATA_FIFO_AFULL | ||
184 | #define BP_MSC_STAT_IS_READ_WAIT 9 | ||
185 | #define BM_MSC_STAT_IS_READ_WAIT 0x200 | ||
186 | #define BF_MSC_STAT_IS_READ_WAIT(v) (((v) & 0x1) << 9) | ||
187 | #define BFM_MSC_STAT_IS_READ_WAIT(v) BM_MSC_STAT_IS_READ_WAIT | ||
188 | #define BF_MSC_STAT_IS_READ_WAIT_V(e) BF_MSC_STAT_IS_READ_WAIT(BV_MSC_STAT_IS_READ_WAIT__##e) | ||
189 | #define BFM_MSC_STAT_IS_READ_WAIT_V(v) BM_MSC_STAT_IS_READ_WAIT | ||
190 | #define BP_MSC_STAT_CLOCK_EN 8 | ||
191 | #define BM_MSC_STAT_CLOCK_EN 0x100 | ||
192 | #define BF_MSC_STAT_CLOCK_EN(v) (((v) & 0x1) << 8) | ||
193 | #define BFM_MSC_STAT_CLOCK_EN(v) BM_MSC_STAT_CLOCK_EN | ||
194 | #define BF_MSC_STAT_CLOCK_EN_V(e) BF_MSC_STAT_CLOCK_EN(BV_MSC_STAT_CLOCK_EN__##e) | ||
195 | #define BFM_MSC_STAT_CLOCK_EN_V(v) BM_MSC_STAT_CLOCK_EN | ||
196 | #define BP_MSC_STAT_DATA_FIFO_FULL 7 | ||
197 | #define BM_MSC_STAT_DATA_FIFO_FULL 0x80 | ||
198 | #define BF_MSC_STAT_DATA_FIFO_FULL(v) (((v) & 0x1) << 7) | ||
199 | #define BFM_MSC_STAT_DATA_FIFO_FULL(v) BM_MSC_STAT_DATA_FIFO_FULL | ||
200 | #define BF_MSC_STAT_DATA_FIFO_FULL_V(e) BF_MSC_STAT_DATA_FIFO_FULL(BV_MSC_STAT_DATA_FIFO_FULL__##e) | ||
201 | #define BFM_MSC_STAT_DATA_FIFO_FULL_V(v) BM_MSC_STAT_DATA_FIFO_FULL | ||
202 | #define BP_MSC_STAT_DATA_FIFO_EMPTY 6 | ||
203 | #define BM_MSC_STAT_DATA_FIFO_EMPTY 0x40 | ||
204 | #define BF_MSC_STAT_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 6) | ||
205 | #define BFM_MSC_STAT_DATA_FIFO_EMPTY(v) BM_MSC_STAT_DATA_FIFO_EMPTY | ||
206 | #define BF_MSC_STAT_DATA_FIFO_EMPTY_V(e) BF_MSC_STAT_DATA_FIFO_EMPTY(BV_MSC_STAT_DATA_FIFO_EMPTY__##e) | ||
207 | #define BFM_MSC_STAT_DATA_FIFO_EMPTY_V(v) BM_MSC_STAT_DATA_FIFO_EMPTY | ||
208 | #define BP_MSC_STAT_CRC_RES_ERROR 5 | ||
209 | #define BM_MSC_STAT_CRC_RES_ERROR 0x20 | ||
210 | #define BF_MSC_STAT_CRC_RES_ERROR(v) (((v) & 0x1) << 5) | ||
211 | #define BFM_MSC_STAT_CRC_RES_ERROR(v) BM_MSC_STAT_CRC_RES_ERROR | ||
212 | #define BF_MSC_STAT_CRC_RES_ERROR_V(e) BF_MSC_STAT_CRC_RES_ERROR(BV_MSC_STAT_CRC_RES_ERROR__##e) | ||
213 | #define BFM_MSC_STAT_CRC_RES_ERROR_V(v) BM_MSC_STAT_CRC_RES_ERROR | ||
214 | #define BP_MSC_STAT_CRC_READ_ERROR 4 | ||
215 | #define BM_MSC_STAT_CRC_READ_ERROR 0x10 | ||
216 | #define BF_MSC_STAT_CRC_READ_ERROR(v) (((v) & 0x1) << 4) | ||
217 | #define BFM_MSC_STAT_CRC_READ_ERROR(v) BM_MSC_STAT_CRC_READ_ERROR | ||
218 | #define BF_MSC_STAT_CRC_READ_ERROR_V(e) BF_MSC_STAT_CRC_READ_ERROR(BV_MSC_STAT_CRC_READ_ERROR__##e) | ||
219 | #define BFM_MSC_STAT_CRC_READ_ERROR_V(v) BM_MSC_STAT_CRC_READ_ERROR | ||
220 | #define BP_MSC_STAT_TIME_OUT_RES 1 | ||
221 | #define BM_MSC_STAT_TIME_OUT_RES 0x2 | ||
222 | #define BF_MSC_STAT_TIME_OUT_RES(v) (((v) & 0x1) << 1) | ||
223 | #define BFM_MSC_STAT_TIME_OUT_RES(v) BM_MSC_STAT_TIME_OUT_RES | ||
224 | #define BF_MSC_STAT_TIME_OUT_RES_V(e) BF_MSC_STAT_TIME_OUT_RES(BV_MSC_STAT_TIME_OUT_RES__##e) | ||
225 | #define BFM_MSC_STAT_TIME_OUT_RES_V(v) BM_MSC_STAT_TIME_OUT_RES | ||
226 | #define BP_MSC_STAT_TIME_OUT_READ 0 | ||
227 | #define BM_MSC_STAT_TIME_OUT_READ 0x1 | ||
228 | #define BF_MSC_STAT_TIME_OUT_READ(v) (((v) & 0x1) << 0) | ||
229 | #define BFM_MSC_STAT_TIME_OUT_READ(v) BM_MSC_STAT_TIME_OUT_READ | ||
230 | #define BF_MSC_STAT_TIME_OUT_READ_V(e) BF_MSC_STAT_TIME_OUT_READ(BV_MSC_STAT_TIME_OUT_READ__##e) | ||
231 | #define BFM_MSC_STAT_TIME_OUT_READ_V(v) BM_MSC_STAT_TIME_OUT_READ | ||
232 | |||
233 | #define REG_MSC_CMDAT(_n1) jz_reg(MSC_CMDAT(_n1)) | ||
234 | #define JA_MSC_CMDAT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0xc) | ||
235 | #define JT_MSC_CMDAT(_n1) JIO_32_RW | ||
236 | #define JN_MSC_CMDAT(_n1) MSC_CMDAT | ||
237 | #define JI_MSC_CMDAT(_n1) (_n1) | ||
238 | #define BP_MSC_CMDAT_RTRG 14 | ||
239 | #define BM_MSC_CMDAT_RTRG 0xc000 | ||
240 | #define BV_MSC_CMDAT_RTRG__GE16 0x0 | ||
241 | #define BV_MSC_CMDAT_RTRG__GE32 0x1 | ||
242 | #define BV_MSC_CMDAT_RTRG__GE64 0x2 | ||
243 | #define BV_MSC_CMDAT_RTRG__GE96 0x3 | ||
244 | #define BF_MSC_CMDAT_RTRG(v) (((v) & 0x3) << 14) | ||
245 | #define BFM_MSC_CMDAT_RTRG(v) BM_MSC_CMDAT_RTRG | ||
246 | #define BF_MSC_CMDAT_RTRG_V(e) BF_MSC_CMDAT_RTRG(BV_MSC_CMDAT_RTRG__##e) | ||
247 | #define BFM_MSC_CMDAT_RTRG_V(v) BM_MSC_CMDAT_RTRG | ||
248 | #define BP_MSC_CMDAT_TTRG 12 | ||
249 | #define BM_MSC_CMDAT_TTRG 0x3000 | ||
250 | #define BV_MSC_CMDAT_TTRG__LE16 0x0 | ||
251 | #define BV_MSC_CMDAT_TTRG__LE32 0x1 | ||
252 | #define BV_MSC_CMDAT_TTRG__LE64 0x2 | ||
253 | #define BV_MSC_CMDAT_TTRG__LE96 0x3 | ||
254 | #define BF_MSC_CMDAT_TTRG(v) (((v) & 0x3) << 12) | ||
255 | #define BFM_MSC_CMDAT_TTRG(v) BM_MSC_CMDAT_TTRG | ||
256 | #define BF_MSC_CMDAT_TTRG_V(e) BF_MSC_CMDAT_TTRG(BV_MSC_CMDAT_TTRG__##e) | ||
257 | #define BFM_MSC_CMDAT_TTRG_V(v) BM_MSC_CMDAT_TTRG | ||
258 | #define BP_MSC_CMDAT_BUS_WIDTH 9 | ||
259 | #define BM_MSC_CMDAT_BUS_WIDTH 0x600 | ||
260 | #define BV_MSC_CMDAT_BUS_WIDTH__1BIT 0x0 | ||
261 | #define BV_MSC_CMDAT_BUS_WIDTH__4BIT 0x2 | ||
262 | #define BV_MSC_CMDAT_BUS_WIDTH__8BIT 0x3 | ||
263 | #define BF_MSC_CMDAT_BUS_WIDTH(v) (((v) & 0x3) << 9) | ||
264 | #define BFM_MSC_CMDAT_BUS_WIDTH(v) BM_MSC_CMDAT_BUS_WIDTH | ||
265 | #define BF_MSC_CMDAT_BUS_WIDTH_V(e) BF_MSC_CMDAT_BUS_WIDTH(BV_MSC_CMDAT_BUS_WIDTH__##e) | ||
266 | #define BFM_MSC_CMDAT_BUS_WIDTH_V(v) BM_MSC_CMDAT_BUS_WIDTH | ||
267 | #define BP_MSC_CMDAT_RESP_FMT 0 | ||
268 | #define BM_MSC_CMDAT_RESP_FMT 0x7 | ||
269 | #define BF_MSC_CMDAT_RESP_FMT(v) (((v) & 0x7) << 0) | ||
270 | #define BFM_MSC_CMDAT_RESP_FMT(v) BM_MSC_CMDAT_RESP_FMT | ||
271 | #define BF_MSC_CMDAT_RESP_FMT_V(e) BF_MSC_CMDAT_RESP_FMT(BV_MSC_CMDAT_RESP_FMT__##e) | ||
272 | #define BFM_MSC_CMDAT_RESP_FMT_V(v) BM_MSC_CMDAT_RESP_FMT | ||
273 | #define BP_MSC_CMDAT_CCS_EXPECTED 31 | ||
274 | #define BM_MSC_CMDAT_CCS_EXPECTED 0x80000000 | ||
275 | #define BF_MSC_CMDAT_CCS_EXPECTED(v) (((v) & 0x1) << 31) | ||
276 | #define BFM_MSC_CMDAT_CCS_EXPECTED(v) BM_MSC_CMDAT_CCS_EXPECTED | ||
277 | #define BF_MSC_CMDAT_CCS_EXPECTED_V(e) BF_MSC_CMDAT_CCS_EXPECTED(BV_MSC_CMDAT_CCS_EXPECTED__##e) | ||
278 | #define BFM_MSC_CMDAT_CCS_EXPECTED_V(v) BM_MSC_CMDAT_CCS_EXPECTED | ||
279 | #define BP_MSC_CMDAT_READ_CEATA 30 | ||
280 | #define BM_MSC_CMDAT_READ_CEATA 0x40000000 | ||
281 | #define BF_MSC_CMDAT_READ_CEATA(v) (((v) & 0x1) << 30) | ||
282 | #define BFM_MSC_CMDAT_READ_CEATA(v) BM_MSC_CMDAT_READ_CEATA | ||
283 | #define BF_MSC_CMDAT_READ_CEATA_V(e) BF_MSC_CMDAT_READ_CEATA(BV_MSC_CMDAT_READ_CEATA__##e) | ||
284 | #define BFM_MSC_CMDAT_READ_CEATA_V(v) BM_MSC_CMDAT_READ_CEATA | ||
285 | #define BP_MSC_CMDAT_DIS_BOOT 27 | ||
286 | #define BM_MSC_CMDAT_DIS_BOOT 0x8000000 | ||
287 | #define BF_MSC_CMDAT_DIS_BOOT(v) (((v) & 0x1) << 27) | ||
288 | #define BFM_MSC_CMDAT_DIS_BOOT(v) BM_MSC_CMDAT_DIS_BOOT | ||
289 | #define BF_MSC_CMDAT_DIS_BOOT_V(e) BF_MSC_CMDAT_DIS_BOOT(BV_MSC_CMDAT_DIS_BOOT__##e) | ||
290 | #define BFM_MSC_CMDAT_DIS_BOOT_V(v) BM_MSC_CMDAT_DIS_BOOT | ||
291 | #define BP_MSC_CMDAT_EXP_BOOT_ACK 25 | ||
292 | #define BM_MSC_CMDAT_EXP_BOOT_ACK 0x2000000 | ||
293 | #define BF_MSC_CMDAT_EXP_BOOT_ACK(v) (((v) & 0x1) << 25) | ||
294 | #define BFM_MSC_CMDAT_EXP_BOOT_ACK(v) BM_MSC_CMDAT_EXP_BOOT_ACK | ||
295 | #define BF_MSC_CMDAT_EXP_BOOT_ACK_V(e) BF_MSC_CMDAT_EXP_BOOT_ACK(BV_MSC_CMDAT_EXP_BOOT_ACK__##e) | ||
296 | #define BFM_MSC_CMDAT_EXP_BOOT_ACK_V(v) BM_MSC_CMDAT_EXP_BOOT_ACK | ||
297 | #define BP_MSC_CMDAT_BOOT_MODE 24 | ||
298 | #define BM_MSC_CMDAT_BOOT_MODE 0x1000000 | ||
299 | #define BF_MSC_CMDAT_BOOT_MODE(v) (((v) & 0x1) << 24) | ||
300 | #define BFM_MSC_CMDAT_BOOT_MODE(v) BM_MSC_CMDAT_BOOT_MODE | ||
301 | #define BF_MSC_CMDAT_BOOT_MODE_V(e) BF_MSC_CMDAT_BOOT_MODE(BV_MSC_CMDAT_BOOT_MODE__##e) | ||
302 | #define BFM_MSC_CMDAT_BOOT_MODE_V(v) BM_MSC_CMDAT_BOOT_MODE | ||
303 | #define BP_MSC_CMDAT_SDIO_PRDT 17 | ||
304 | #define BM_MSC_CMDAT_SDIO_PRDT 0x20000 | ||
305 | #define BF_MSC_CMDAT_SDIO_PRDT(v) (((v) & 0x1) << 17) | ||
306 | #define BFM_MSC_CMDAT_SDIO_PRDT(v) BM_MSC_CMDAT_SDIO_PRDT | ||
307 | #define BF_MSC_CMDAT_SDIO_PRDT_V(e) BF_MSC_CMDAT_SDIO_PRDT(BV_MSC_CMDAT_SDIO_PRDT__##e) | ||
308 | #define BFM_MSC_CMDAT_SDIO_PRDT_V(v) BM_MSC_CMDAT_SDIO_PRDT | ||
309 | #define BP_MSC_CMDAT_AUTO_CMD12 16 | ||
310 | #define BM_MSC_CMDAT_AUTO_CMD12 0x10000 | ||
311 | #define BF_MSC_CMDAT_AUTO_CMD12(v) (((v) & 0x1) << 16) | ||
312 | #define BFM_MSC_CMDAT_AUTO_CMD12(v) BM_MSC_CMDAT_AUTO_CMD12 | ||
313 | #define BF_MSC_CMDAT_AUTO_CMD12_V(e) BF_MSC_CMDAT_AUTO_CMD12(BV_MSC_CMDAT_AUTO_CMD12__##e) | ||
314 | #define BFM_MSC_CMDAT_AUTO_CMD12_V(v) BM_MSC_CMDAT_AUTO_CMD12 | ||
315 | #define BP_MSC_CMDAT_IO_ABORT 11 | ||
316 | #define BM_MSC_CMDAT_IO_ABORT 0x800 | ||
317 | #define BF_MSC_CMDAT_IO_ABORT(v) (((v) & 0x1) << 11) | ||
318 | #define BFM_MSC_CMDAT_IO_ABORT(v) BM_MSC_CMDAT_IO_ABORT | ||
319 | #define BF_MSC_CMDAT_IO_ABORT_V(e) BF_MSC_CMDAT_IO_ABORT(BV_MSC_CMDAT_IO_ABORT__##e) | ||
320 | #define BFM_MSC_CMDAT_IO_ABORT_V(v) BM_MSC_CMDAT_IO_ABORT | ||
321 | #define BP_MSC_CMDAT_INIT 7 | ||
322 | #define BM_MSC_CMDAT_INIT 0x80 | ||
323 | #define BF_MSC_CMDAT_INIT(v) (((v) & 0x1) << 7) | ||
324 | #define BFM_MSC_CMDAT_INIT(v) BM_MSC_CMDAT_INIT | ||
325 | #define BF_MSC_CMDAT_INIT_V(e) BF_MSC_CMDAT_INIT(BV_MSC_CMDAT_INIT__##e) | ||
326 | #define BFM_MSC_CMDAT_INIT_V(v) BM_MSC_CMDAT_INIT | ||
327 | #define BP_MSC_CMDAT_BUSY 6 | ||
328 | #define BM_MSC_CMDAT_BUSY 0x40 | ||
329 | #define BF_MSC_CMDAT_BUSY(v) (((v) & 0x1) << 6) | ||
330 | #define BFM_MSC_CMDAT_BUSY(v) BM_MSC_CMDAT_BUSY | ||
331 | #define BF_MSC_CMDAT_BUSY_V(e) BF_MSC_CMDAT_BUSY(BV_MSC_CMDAT_BUSY__##e) | ||
332 | #define BFM_MSC_CMDAT_BUSY_V(v) BM_MSC_CMDAT_BUSY | ||
333 | #define BP_MSC_CMDAT_STREAM_BLOCK 5 | ||
334 | #define BM_MSC_CMDAT_STREAM_BLOCK 0x20 | ||
335 | #define BF_MSC_CMDAT_STREAM_BLOCK(v) (((v) & 0x1) << 5) | ||
336 | #define BFM_MSC_CMDAT_STREAM_BLOCK(v) BM_MSC_CMDAT_STREAM_BLOCK | ||
337 | #define BF_MSC_CMDAT_STREAM_BLOCK_V(e) BF_MSC_CMDAT_STREAM_BLOCK(BV_MSC_CMDAT_STREAM_BLOCK__##e) | ||
338 | #define BFM_MSC_CMDAT_STREAM_BLOCK_V(v) BM_MSC_CMDAT_STREAM_BLOCK | ||
339 | #define BP_MSC_CMDAT_WRITE_READ 4 | ||
340 | #define BM_MSC_CMDAT_WRITE_READ 0x10 | ||
341 | #define BF_MSC_CMDAT_WRITE_READ(v) (((v) & 0x1) << 4) | ||
342 | #define BFM_MSC_CMDAT_WRITE_READ(v) BM_MSC_CMDAT_WRITE_READ | ||
343 | #define BF_MSC_CMDAT_WRITE_READ_V(e) BF_MSC_CMDAT_WRITE_READ(BV_MSC_CMDAT_WRITE_READ__##e) | ||
344 | #define BFM_MSC_CMDAT_WRITE_READ_V(v) BM_MSC_CMDAT_WRITE_READ | ||
345 | #define BP_MSC_CMDAT_DATA_EN 3 | ||
346 | #define BM_MSC_CMDAT_DATA_EN 0x8 | ||
347 | #define BF_MSC_CMDAT_DATA_EN(v) (((v) & 0x1) << 3) | ||
348 | #define BFM_MSC_CMDAT_DATA_EN(v) BM_MSC_CMDAT_DATA_EN | ||
349 | #define BF_MSC_CMDAT_DATA_EN_V(e) BF_MSC_CMDAT_DATA_EN(BV_MSC_CMDAT_DATA_EN__##e) | ||
350 | #define BFM_MSC_CMDAT_DATA_EN_V(v) BM_MSC_CMDAT_DATA_EN | ||
351 | |||
352 | #define REG_MSC_IMASK(_n1) jz_reg(MSC_IMASK(_n1)) | ||
353 | #define JA_MSC_IMASK(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x24) | ||
354 | #define JT_MSC_IMASK(_n1) JIO_32_RW | ||
355 | #define JN_MSC_IMASK(_n1) MSC_IMASK | ||
356 | #define JI_MSC_IMASK(_n1) (_n1) | ||
357 | #define BP_MSC_IMASK_PINS 24 | ||
358 | #define BM_MSC_IMASK_PINS 0x1f000000 | ||
359 | #define BF_MSC_IMASK_PINS(v) (((v) & 0x1f) << 24) | ||
360 | #define BFM_MSC_IMASK_PINS(v) BM_MSC_IMASK_PINS | ||
361 | #define BF_MSC_IMASK_PINS_V(e) BF_MSC_IMASK_PINS(BV_MSC_IMASK_PINS__##e) | ||
362 | #define BFM_MSC_IMASK_PINS_V(v) BM_MSC_IMASK_PINS | ||
363 | #define BP_MSC_IMASK_DMA_DATA_DONE 31 | ||
364 | #define BM_MSC_IMASK_DMA_DATA_DONE 0x80000000 | ||
365 | #define BF_MSC_IMASK_DMA_DATA_DONE(v) (((v) & 0x1) << 31) | ||
366 | #define BFM_MSC_IMASK_DMA_DATA_DONE(v) BM_MSC_IMASK_DMA_DATA_DONE | ||
367 | #define BF_MSC_IMASK_DMA_DATA_DONE_V(e) BF_MSC_IMASK_DMA_DATA_DONE(BV_MSC_IMASK_DMA_DATA_DONE__##e) | ||
368 | #define BFM_MSC_IMASK_DMA_DATA_DONE_V(v) BM_MSC_IMASK_DMA_DATA_DONE | ||
369 | #define BP_MSC_IMASK_WR_ALL_DONE 23 | ||
370 | #define BM_MSC_IMASK_WR_ALL_DONE 0x800000 | ||
371 | #define BF_MSC_IMASK_WR_ALL_DONE(v) (((v) & 0x1) << 23) | ||
372 | #define BFM_MSC_IMASK_WR_ALL_DONE(v) BM_MSC_IMASK_WR_ALL_DONE | ||
373 | #define BF_MSC_IMASK_WR_ALL_DONE_V(e) BF_MSC_IMASK_WR_ALL_DONE(BV_MSC_IMASK_WR_ALL_DONE__##e) | ||
374 | #define BFM_MSC_IMASK_WR_ALL_DONE_V(v) BM_MSC_IMASK_WR_ALL_DONE | ||
375 | #define BP_MSC_IMASK_BCE 20 | ||
376 | #define BM_MSC_IMASK_BCE 0x100000 | ||
377 | #define BF_MSC_IMASK_BCE(v) (((v) & 0x1) << 20) | ||
378 | #define BFM_MSC_IMASK_BCE(v) BM_MSC_IMASK_BCE | ||
379 | #define BF_MSC_IMASK_BCE_V(e) BF_MSC_IMASK_BCE(BV_MSC_IMASK_BCE__##e) | ||
380 | #define BFM_MSC_IMASK_BCE_V(v) BM_MSC_IMASK_BCE | ||
381 | #define BP_MSC_IMASK_BDE 19 | ||
382 | #define BM_MSC_IMASK_BDE 0x80000 | ||
383 | #define BF_MSC_IMASK_BDE(v) (((v) & 0x1) << 19) | ||
384 | #define BFM_MSC_IMASK_BDE(v) BM_MSC_IMASK_BDE | ||
385 | #define BF_MSC_IMASK_BDE_V(e) BF_MSC_IMASK_BDE(BV_MSC_IMASK_BDE__##e) | ||
386 | #define BFM_MSC_IMASK_BDE_V(v) BM_MSC_IMASK_BDE | ||
387 | #define BP_MSC_IMASK_BAE 18 | ||
388 | #define BM_MSC_IMASK_BAE 0x40000 | ||
389 | #define BF_MSC_IMASK_BAE(v) (((v) & 0x1) << 18) | ||
390 | #define BFM_MSC_IMASK_BAE(v) BM_MSC_IMASK_BAE | ||
391 | #define BF_MSC_IMASK_BAE_V(e) BF_MSC_IMASK_BAE(BV_MSC_IMASK_BAE__##e) | ||
392 | #define BFM_MSC_IMASK_BAE_V(v) BM_MSC_IMASK_BAE | ||
393 | #define BP_MSC_IMASK_BAR 17 | ||
394 | #define BM_MSC_IMASK_BAR 0x20000 | ||
395 | #define BF_MSC_IMASK_BAR(v) (((v) & 0x1) << 17) | ||
396 | #define BFM_MSC_IMASK_BAR(v) BM_MSC_IMASK_BAR | ||
397 | #define BF_MSC_IMASK_BAR_V(e) BF_MSC_IMASK_BAR(BV_MSC_IMASK_BAR__##e) | ||
398 | #define BFM_MSC_IMASK_BAR_V(v) BM_MSC_IMASK_BAR | ||
399 | #define BP_MSC_IMASK_DMAEND 16 | ||
400 | #define BM_MSC_IMASK_DMAEND 0x10000 | ||
401 | #define BF_MSC_IMASK_DMAEND(v) (((v) & 0x1) << 16) | ||
402 | #define BFM_MSC_IMASK_DMAEND(v) BM_MSC_IMASK_DMAEND | ||
403 | #define BF_MSC_IMASK_DMAEND_V(e) BF_MSC_IMASK_DMAEND(BV_MSC_IMASK_DMAEND__##e) | ||
404 | #define BFM_MSC_IMASK_DMAEND_V(v) BM_MSC_IMASK_DMAEND | ||
405 | #define BP_MSC_IMASK_AUTO_CMD12_DONE 15 | ||
406 | #define BM_MSC_IMASK_AUTO_CMD12_DONE 0x8000 | ||
407 | #define BF_MSC_IMASK_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) | ||
408 | #define BFM_MSC_IMASK_AUTO_CMD12_DONE(v) BM_MSC_IMASK_AUTO_CMD12_DONE | ||
409 | #define BF_MSC_IMASK_AUTO_CMD12_DONE_V(e) BF_MSC_IMASK_AUTO_CMD12_DONE(BV_MSC_IMASK_AUTO_CMD12_DONE__##e) | ||
410 | #define BFM_MSC_IMASK_AUTO_CMD12_DONE_V(v) BM_MSC_IMASK_AUTO_CMD12_DONE | ||
411 | #define BP_MSC_IMASK_DATA_FIFO_FULL 14 | ||
412 | #define BM_MSC_IMASK_DATA_FIFO_FULL 0x4000 | ||
413 | #define BF_MSC_IMASK_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) | ||
414 | #define BFM_MSC_IMASK_DATA_FIFO_FULL(v) BM_MSC_IMASK_DATA_FIFO_FULL | ||
415 | #define BF_MSC_IMASK_DATA_FIFO_FULL_V(e) BF_MSC_IMASK_DATA_FIFO_FULL(BV_MSC_IMASK_DATA_FIFO_FULL__##e) | ||
416 | #define BFM_MSC_IMASK_DATA_FIFO_FULL_V(v) BM_MSC_IMASK_DATA_FIFO_FULL | ||
417 | #define BP_MSC_IMASK_DATA_FIFO_EMPTY 13 | ||
418 | #define BM_MSC_IMASK_DATA_FIFO_EMPTY 0x2000 | ||
419 | #define BF_MSC_IMASK_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) | ||
420 | #define BFM_MSC_IMASK_DATA_FIFO_EMPTY(v) BM_MSC_IMASK_DATA_FIFO_EMPTY | ||
421 | #define BF_MSC_IMASK_DATA_FIFO_EMPTY_V(e) BF_MSC_IMASK_DATA_FIFO_EMPTY(BV_MSC_IMASK_DATA_FIFO_EMPTY__##e) | ||
422 | #define BFM_MSC_IMASK_DATA_FIFO_EMPTY_V(v) BM_MSC_IMASK_DATA_FIFO_EMPTY | ||
423 | #define BP_MSC_IMASK_CRC_RES_ERROR 12 | ||
424 | #define BM_MSC_IMASK_CRC_RES_ERROR 0x1000 | ||
425 | #define BF_MSC_IMASK_CRC_RES_ERROR(v) (((v) & 0x1) << 12) | ||
426 | #define BFM_MSC_IMASK_CRC_RES_ERROR(v) BM_MSC_IMASK_CRC_RES_ERROR | ||
427 | #define BF_MSC_IMASK_CRC_RES_ERROR_V(e) BF_MSC_IMASK_CRC_RES_ERROR(BV_MSC_IMASK_CRC_RES_ERROR__##e) | ||
428 | #define BFM_MSC_IMASK_CRC_RES_ERROR_V(v) BM_MSC_IMASK_CRC_RES_ERROR | ||
429 | #define BP_MSC_IMASK_CRC_READ_ERROR 11 | ||
430 | #define BM_MSC_IMASK_CRC_READ_ERROR 0x800 | ||
431 | #define BF_MSC_IMASK_CRC_READ_ERROR(v) (((v) & 0x1) << 11) | ||
432 | #define BFM_MSC_IMASK_CRC_READ_ERROR(v) BM_MSC_IMASK_CRC_READ_ERROR | ||
433 | #define BF_MSC_IMASK_CRC_READ_ERROR_V(e) BF_MSC_IMASK_CRC_READ_ERROR(BV_MSC_IMASK_CRC_READ_ERROR__##e) | ||
434 | #define BFM_MSC_IMASK_CRC_READ_ERROR_V(v) BM_MSC_IMASK_CRC_READ_ERROR | ||
435 | #define BP_MSC_IMASK_CRC_WRITE_ERROR 10 | ||
436 | #define BM_MSC_IMASK_CRC_WRITE_ERROR 0x400 | ||
437 | #define BF_MSC_IMASK_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) | ||
438 | #define BFM_MSC_IMASK_CRC_WRITE_ERROR(v) BM_MSC_IMASK_CRC_WRITE_ERROR | ||
439 | #define BF_MSC_IMASK_CRC_WRITE_ERROR_V(e) BF_MSC_IMASK_CRC_WRITE_ERROR(BV_MSC_IMASK_CRC_WRITE_ERROR__##e) | ||
440 | #define BFM_MSC_IMASK_CRC_WRITE_ERROR_V(v) BM_MSC_IMASK_CRC_WRITE_ERROR | ||
441 | #define BP_MSC_IMASK_TIME_OUT_RES 9 | ||
442 | #define BM_MSC_IMASK_TIME_OUT_RES 0x200 | ||
443 | #define BF_MSC_IMASK_TIME_OUT_RES(v) (((v) & 0x1) << 9) | ||
444 | #define BFM_MSC_IMASK_TIME_OUT_RES(v) BM_MSC_IMASK_TIME_OUT_RES | ||
445 | #define BF_MSC_IMASK_TIME_OUT_RES_V(e) BF_MSC_IMASK_TIME_OUT_RES(BV_MSC_IMASK_TIME_OUT_RES__##e) | ||
446 | #define BFM_MSC_IMASK_TIME_OUT_RES_V(v) BM_MSC_IMASK_TIME_OUT_RES | ||
447 | #define BP_MSC_IMASK_TIME_OUT_READ 8 | ||
448 | #define BM_MSC_IMASK_TIME_OUT_READ 0x100 | ||
449 | #define BF_MSC_IMASK_TIME_OUT_READ(v) (((v) & 0x1) << 8) | ||
450 | #define BFM_MSC_IMASK_TIME_OUT_READ(v) BM_MSC_IMASK_TIME_OUT_READ | ||
451 | #define BF_MSC_IMASK_TIME_OUT_READ_V(e) BF_MSC_IMASK_TIME_OUT_READ(BV_MSC_IMASK_TIME_OUT_READ__##e) | ||
452 | #define BFM_MSC_IMASK_TIME_OUT_READ_V(v) BM_MSC_IMASK_TIME_OUT_READ | ||
453 | #define BP_MSC_IMASK_SDIO 7 | ||
454 | #define BM_MSC_IMASK_SDIO 0x80 | ||
455 | #define BF_MSC_IMASK_SDIO(v) (((v) & 0x1) << 7) | ||
456 | #define BFM_MSC_IMASK_SDIO(v) BM_MSC_IMASK_SDIO | ||
457 | #define BF_MSC_IMASK_SDIO_V(e) BF_MSC_IMASK_SDIO(BV_MSC_IMASK_SDIO__##e) | ||
458 | #define BFM_MSC_IMASK_SDIO_V(v) BM_MSC_IMASK_SDIO | ||
459 | #define BP_MSC_IMASK_TXFIFO_WR_REQ 6 | ||
460 | #define BM_MSC_IMASK_TXFIFO_WR_REQ 0x40 | ||
461 | #define BF_MSC_IMASK_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) | ||
462 | #define BFM_MSC_IMASK_TXFIFO_WR_REQ(v) BM_MSC_IMASK_TXFIFO_WR_REQ | ||
463 | #define BF_MSC_IMASK_TXFIFO_WR_REQ_V(e) BF_MSC_IMASK_TXFIFO_WR_REQ(BV_MSC_IMASK_TXFIFO_WR_REQ__##e) | ||
464 | #define BFM_MSC_IMASK_TXFIFO_WR_REQ_V(v) BM_MSC_IMASK_TXFIFO_WR_REQ | ||
465 | #define BP_MSC_IMASK_RXFIFO_RD_REQ 5 | ||
466 | #define BM_MSC_IMASK_RXFIFO_RD_REQ 0x20 | ||
467 | #define BF_MSC_IMASK_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) | ||
468 | #define BFM_MSC_IMASK_RXFIFO_RD_REQ(v) BM_MSC_IMASK_RXFIFO_RD_REQ | ||
469 | #define BF_MSC_IMASK_RXFIFO_RD_REQ_V(e) BF_MSC_IMASK_RXFIFO_RD_REQ(BV_MSC_IMASK_RXFIFO_RD_REQ__##e) | ||
470 | #define BFM_MSC_IMASK_RXFIFO_RD_REQ_V(v) BM_MSC_IMASK_RXFIFO_RD_REQ | ||
471 | #define BP_MSC_IMASK_END_CMD_RES 2 | ||
472 | #define BM_MSC_IMASK_END_CMD_RES 0x4 | ||
473 | #define BF_MSC_IMASK_END_CMD_RES(v) (((v) & 0x1) << 2) | ||
474 | #define BFM_MSC_IMASK_END_CMD_RES(v) BM_MSC_IMASK_END_CMD_RES | ||
475 | #define BF_MSC_IMASK_END_CMD_RES_V(e) BF_MSC_IMASK_END_CMD_RES(BV_MSC_IMASK_END_CMD_RES__##e) | ||
476 | #define BFM_MSC_IMASK_END_CMD_RES_V(v) BM_MSC_IMASK_END_CMD_RES | ||
477 | #define BP_MSC_IMASK_PROG_DONE 1 | ||
478 | #define BM_MSC_IMASK_PROG_DONE 0x2 | ||
479 | #define BF_MSC_IMASK_PROG_DONE(v) (((v) & 0x1) << 1) | ||
480 | #define BFM_MSC_IMASK_PROG_DONE(v) BM_MSC_IMASK_PROG_DONE | ||
481 | #define BF_MSC_IMASK_PROG_DONE_V(e) BF_MSC_IMASK_PROG_DONE(BV_MSC_IMASK_PROG_DONE__##e) | ||
482 | #define BFM_MSC_IMASK_PROG_DONE_V(v) BM_MSC_IMASK_PROG_DONE | ||
483 | #define BP_MSC_IMASK_DATA_TRAN_DONE 0 | ||
484 | #define BM_MSC_IMASK_DATA_TRAN_DONE 0x1 | ||
485 | #define BF_MSC_IMASK_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) | ||
486 | #define BFM_MSC_IMASK_DATA_TRAN_DONE(v) BM_MSC_IMASK_DATA_TRAN_DONE | ||
487 | #define BF_MSC_IMASK_DATA_TRAN_DONE_V(e) BF_MSC_IMASK_DATA_TRAN_DONE(BV_MSC_IMASK_DATA_TRAN_DONE__##e) | ||
488 | #define BFM_MSC_IMASK_DATA_TRAN_DONE_V(v) BM_MSC_IMASK_DATA_TRAN_DONE | ||
489 | |||
490 | #define REG_MSC_IFLAG(_n1) jz_reg(MSC_IFLAG(_n1)) | ||
491 | #define JA_MSC_IFLAG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x28) | ||
492 | #define JT_MSC_IFLAG(_n1) JIO_32_RW | ||
493 | #define JN_MSC_IFLAG(_n1) MSC_IFLAG | ||
494 | #define JI_MSC_IFLAG(_n1) (_n1) | ||
495 | #define BP_MSC_IFLAG_PINS 24 | ||
496 | #define BM_MSC_IFLAG_PINS 0x1f000000 | ||
497 | #define BF_MSC_IFLAG_PINS(v) (((v) & 0x1f) << 24) | ||
498 | #define BFM_MSC_IFLAG_PINS(v) BM_MSC_IFLAG_PINS | ||
499 | #define BF_MSC_IFLAG_PINS_V(e) BF_MSC_IFLAG_PINS(BV_MSC_IFLAG_PINS__##e) | ||
500 | #define BFM_MSC_IFLAG_PINS_V(v) BM_MSC_IFLAG_PINS | ||
501 | #define BP_MSC_IFLAG_DMA_DATA_DONE 31 | ||
502 | #define BM_MSC_IFLAG_DMA_DATA_DONE 0x80000000 | ||
503 | #define BF_MSC_IFLAG_DMA_DATA_DONE(v) (((v) & 0x1) << 31) | ||
504 | #define BFM_MSC_IFLAG_DMA_DATA_DONE(v) BM_MSC_IFLAG_DMA_DATA_DONE | ||
505 | #define BF_MSC_IFLAG_DMA_DATA_DONE_V(e) BF_MSC_IFLAG_DMA_DATA_DONE(BV_MSC_IFLAG_DMA_DATA_DONE__##e) | ||
506 | #define BFM_MSC_IFLAG_DMA_DATA_DONE_V(v) BM_MSC_IFLAG_DMA_DATA_DONE | ||
507 | #define BP_MSC_IFLAG_WR_ALL_DONE 23 | ||
508 | #define BM_MSC_IFLAG_WR_ALL_DONE 0x800000 | ||
509 | #define BF_MSC_IFLAG_WR_ALL_DONE(v) (((v) & 0x1) << 23) | ||
510 | #define BFM_MSC_IFLAG_WR_ALL_DONE(v) BM_MSC_IFLAG_WR_ALL_DONE | ||
511 | #define BF_MSC_IFLAG_WR_ALL_DONE_V(e) BF_MSC_IFLAG_WR_ALL_DONE(BV_MSC_IFLAG_WR_ALL_DONE__##e) | ||
512 | #define BFM_MSC_IFLAG_WR_ALL_DONE_V(v) BM_MSC_IFLAG_WR_ALL_DONE | ||
513 | #define BP_MSC_IFLAG_BCE 20 | ||
514 | #define BM_MSC_IFLAG_BCE 0x100000 | ||
515 | #define BF_MSC_IFLAG_BCE(v) (((v) & 0x1) << 20) | ||
516 | #define BFM_MSC_IFLAG_BCE(v) BM_MSC_IFLAG_BCE | ||
517 | #define BF_MSC_IFLAG_BCE_V(e) BF_MSC_IFLAG_BCE(BV_MSC_IFLAG_BCE__##e) | ||
518 | #define BFM_MSC_IFLAG_BCE_V(v) BM_MSC_IFLAG_BCE | ||
519 | #define BP_MSC_IFLAG_BDE 19 | ||
520 | #define BM_MSC_IFLAG_BDE 0x80000 | ||
521 | #define BF_MSC_IFLAG_BDE(v) (((v) & 0x1) << 19) | ||
522 | #define BFM_MSC_IFLAG_BDE(v) BM_MSC_IFLAG_BDE | ||
523 | #define BF_MSC_IFLAG_BDE_V(e) BF_MSC_IFLAG_BDE(BV_MSC_IFLAG_BDE__##e) | ||
524 | #define BFM_MSC_IFLAG_BDE_V(v) BM_MSC_IFLAG_BDE | ||
525 | #define BP_MSC_IFLAG_BAE 18 | ||
526 | #define BM_MSC_IFLAG_BAE 0x40000 | ||
527 | #define BF_MSC_IFLAG_BAE(v) (((v) & 0x1) << 18) | ||
528 | #define BFM_MSC_IFLAG_BAE(v) BM_MSC_IFLAG_BAE | ||
529 | #define BF_MSC_IFLAG_BAE_V(e) BF_MSC_IFLAG_BAE(BV_MSC_IFLAG_BAE__##e) | ||
530 | #define BFM_MSC_IFLAG_BAE_V(v) BM_MSC_IFLAG_BAE | ||
531 | #define BP_MSC_IFLAG_BAR 17 | ||
532 | #define BM_MSC_IFLAG_BAR 0x20000 | ||
533 | #define BF_MSC_IFLAG_BAR(v) (((v) & 0x1) << 17) | ||
534 | #define BFM_MSC_IFLAG_BAR(v) BM_MSC_IFLAG_BAR | ||
535 | #define BF_MSC_IFLAG_BAR_V(e) BF_MSC_IFLAG_BAR(BV_MSC_IFLAG_BAR__##e) | ||
536 | #define BFM_MSC_IFLAG_BAR_V(v) BM_MSC_IFLAG_BAR | ||
537 | #define BP_MSC_IFLAG_DMAEND 16 | ||
538 | #define BM_MSC_IFLAG_DMAEND 0x10000 | ||
539 | #define BF_MSC_IFLAG_DMAEND(v) (((v) & 0x1) << 16) | ||
540 | #define BFM_MSC_IFLAG_DMAEND(v) BM_MSC_IFLAG_DMAEND | ||
541 | #define BF_MSC_IFLAG_DMAEND_V(e) BF_MSC_IFLAG_DMAEND(BV_MSC_IFLAG_DMAEND__##e) | ||
542 | #define BFM_MSC_IFLAG_DMAEND_V(v) BM_MSC_IFLAG_DMAEND | ||
543 | #define BP_MSC_IFLAG_AUTO_CMD12_DONE 15 | ||
544 | #define BM_MSC_IFLAG_AUTO_CMD12_DONE 0x8000 | ||
545 | #define BF_MSC_IFLAG_AUTO_CMD12_DONE(v) (((v) & 0x1) << 15) | ||
546 | #define BFM_MSC_IFLAG_AUTO_CMD12_DONE(v) BM_MSC_IFLAG_AUTO_CMD12_DONE | ||
547 | #define BF_MSC_IFLAG_AUTO_CMD12_DONE_V(e) BF_MSC_IFLAG_AUTO_CMD12_DONE(BV_MSC_IFLAG_AUTO_CMD12_DONE__##e) | ||
548 | #define BFM_MSC_IFLAG_AUTO_CMD12_DONE_V(v) BM_MSC_IFLAG_AUTO_CMD12_DONE | ||
549 | #define BP_MSC_IFLAG_DATA_FIFO_FULL 14 | ||
550 | #define BM_MSC_IFLAG_DATA_FIFO_FULL 0x4000 | ||
551 | #define BF_MSC_IFLAG_DATA_FIFO_FULL(v) (((v) & 0x1) << 14) | ||
552 | #define BFM_MSC_IFLAG_DATA_FIFO_FULL(v) BM_MSC_IFLAG_DATA_FIFO_FULL | ||
553 | #define BF_MSC_IFLAG_DATA_FIFO_FULL_V(e) BF_MSC_IFLAG_DATA_FIFO_FULL(BV_MSC_IFLAG_DATA_FIFO_FULL__##e) | ||
554 | #define BFM_MSC_IFLAG_DATA_FIFO_FULL_V(v) BM_MSC_IFLAG_DATA_FIFO_FULL | ||
555 | #define BP_MSC_IFLAG_DATA_FIFO_EMPTY 13 | ||
556 | #define BM_MSC_IFLAG_DATA_FIFO_EMPTY 0x2000 | ||
557 | #define BF_MSC_IFLAG_DATA_FIFO_EMPTY(v) (((v) & 0x1) << 13) | ||
558 | #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY | ||
559 | #define BF_MSC_IFLAG_DATA_FIFO_EMPTY_V(e) BF_MSC_IFLAG_DATA_FIFO_EMPTY(BV_MSC_IFLAG_DATA_FIFO_EMPTY__##e) | ||
560 | #define BFM_MSC_IFLAG_DATA_FIFO_EMPTY_V(v) BM_MSC_IFLAG_DATA_FIFO_EMPTY | ||
561 | #define BP_MSC_IFLAG_CRC_RES_ERROR 12 | ||
562 | #define BM_MSC_IFLAG_CRC_RES_ERROR 0x1000 | ||
563 | #define BF_MSC_IFLAG_CRC_RES_ERROR(v) (((v) & 0x1) << 12) | ||
564 | #define BFM_MSC_IFLAG_CRC_RES_ERROR(v) BM_MSC_IFLAG_CRC_RES_ERROR | ||
565 | #define BF_MSC_IFLAG_CRC_RES_ERROR_V(e) BF_MSC_IFLAG_CRC_RES_ERROR(BV_MSC_IFLAG_CRC_RES_ERROR__##e) | ||
566 | #define BFM_MSC_IFLAG_CRC_RES_ERROR_V(v) BM_MSC_IFLAG_CRC_RES_ERROR | ||
567 | #define BP_MSC_IFLAG_CRC_READ_ERROR 11 | ||
568 | #define BM_MSC_IFLAG_CRC_READ_ERROR 0x800 | ||
569 | #define BF_MSC_IFLAG_CRC_READ_ERROR(v) (((v) & 0x1) << 11) | ||
570 | #define BFM_MSC_IFLAG_CRC_READ_ERROR(v) BM_MSC_IFLAG_CRC_READ_ERROR | ||
571 | #define BF_MSC_IFLAG_CRC_READ_ERROR_V(e) BF_MSC_IFLAG_CRC_READ_ERROR(BV_MSC_IFLAG_CRC_READ_ERROR__##e) | ||
572 | #define BFM_MSC_IFLAG_CRC_READ_ERROR_V(v) BM_MSC_IFLAG_CRC_READ_ERROR | ||
573 | #define BP_MSC_IFLAG_CRC_WRITE_ERROR 10 | ||
574 | #define BM_MSC_IFLAG_CRC_WRITE_ERROR 0x400 | ||
575 | #define BF_MSC_IFLAG_CRC_WRITE_ERROR(v) (((v) & 0x1) << 10) | ||
576 | #define BFM_MSC_IFLAG_CRC_WRITE_ERROR(v) BM_MSC_IFLAG_CRC_WRITE_ERROR | ||
577 | #define BF_MSC_IFLAG_CRC_WRITE_ERROR_V(e) BF_MSC_IFLAG_CRC_WRITE_ERROR(BV_MSC_IFLAG_CRC_WRITE_ERROR__##e) | ||
578 | #define BFM_MSC_IFLAG_CRC_WRITE_ERROR_V(v) BM_MSC_IFLAG_CRC_WRITE_ERROR | ||
579 | #define BP_MSC_IFLAG_TIME_OUT_RES 9 | ||
580 | #define BM_MSC_IFLAG_TIME_OUT_RES 0x200 | ||
581 | #define BF_MSC_IFLAG_TIME_OUT_RES(v) (((v) & 0x1) << 9) | ||
582 | #define BFM_MSC_IFLAG_TIME_OUT_RES(v) BM_MSC_IFLAG_TIME_OUT_RES | ||
583 | #define BF_MSC_IFLAG_TIME_OUT_RES_V(e) BF_MSC_IFLAG_TIME_OUT_RES(BV_MSC_IFLAG_TIME_OUT_RES__##e) | ||
584 | #define BFM_MSC_IFLAG_TIME_OUT_RES_V(v) BM_MSC_IFLAG_TIME_OUT_RES | ||
585 | #define BP_MSC_IFLAG_TIME_OUT_READ 8 | ||
586 | #define BM_MSC_IFLAG_TIME_OUT_READ 0x100 | ||
587 | #define BF_MSC_IFLAG_TIME_OUT_READ(v) (((v) & 0x1) << 8) | ||
588 | #define BFM_MSC_IFLAG_TIME_OUT_READ(v) BM_MSC_IFLAG_TIME_OUT_READ | ||
589 | #define BF_MSC_IFLAG_TIME_OUT_READ_V(e) BF_MSC_IFLAG_TIME_OUT_READ(BV_MSC_IFLAG_TIME_OUT_READ__##e) | ||
590 | #define BFM_MSC_IFLAG_TIME_OUT_READ_V(v) BM_MSC_IFLAG_TIME_OUT_READ | ||
591 | #define BP_MSC_IFLAG_SDIO 7 | ||
592 | #define BM_MSC_IFLAG_SDIO 0x80 | ||
593 | #define BF_MSC_IFLAG_SDIO(v) (((v) & 0x1) << 7) | ||
594 | #define BFM_MSC_IFLAG_SDIO(v) BM_MSC_IFLAG_SDIO | ||
595 | #define BF_MSC_IFLAG_SDIO_V(e) BF_MSC_IFLAG_SDIO(BV_MSC_IFLAG_SDIO__##e) | ||
596 | #define BFM_MSC_IFLAG_SDIO_V(v) BM_MSC_IFLAG_SDIO | ||
597 | #define BP_MSC_IFLAG_TXFIFO_WR_REQ 6 | ||
598 | #define BM_MSC_IFLAG_TXFIFO_WR_REQ 0x40 | ||
599 | #define BF_MSC_IFLAG_TXFIFO_WR_REQ(v) (((v) & 0x1) << 6) | ||
600 | #define BFM_MSC_IFLAG_TXFIFO_WR_REQ(v) BM_MSC_IFLAG_TXFIFO_WR_REQ | ||
601 | #define BF_MSC_IFLAG_TXFIFO_WR_REQ_V(e) BF_MSC_IFLAG_TXFIFO_WR_REQ(BV_MSC_IFLAG_TXFIFO_WR_REQ__##e) | ||
602 | #define BFM_MSC_IFLAG_TXFIFO_WR_REQ_V(v) BM_MSC_IFLAG_TXFIFO_WR_REQ | ||
603 | #define BP_MSC_IFLAG_RXFIFO_RD_REQ 5 | ||
604 | #define BM_MSC_IFLAG_RXFIFO_RD_REQ 0x20 | ||
605 | #define BF_MSC_IFLAG_RXFIFO_RD_REQ(v) (((v) & 0x1) << 5) | ||
606 | #define BFM_MSC_IFLAG_RXFIFO_RD_REQ(v) BM_MSC_IFLAG_RXFIFO_RD_REQ | ||
607 | #define BF_MSC_IFLAG_RXFIFO_RD_REQ_V(e) BF_MSC_IFLAG_RXFIFO_RD_REQ(BV_MSC_IFLAG_RXFIFO_RD_REQ__##e) | ||
608 | #define BFM_MSC_IFLAG_RXFIFO_RD_REQ_V(v) BM_MSC_IFLAG_RXFIFO_RD_REQ | ||
609 | #define BP_MSC_IFLAG_END_CMD_RES 2 | ||
610 | #define BM_MSC_IFLAG_END_CMD_RES 0x4 | ||
611 | #define BF_MSC_IFLAG_END_CMD_RES(v) (((v) & 0x1) << 2) | ||
612 | #define BFM_MSC_IFLAG_END_CMD_RES(v) BM_MSC_IFLAG_END_CMD_RES | ||
613 | #define BF_MSC_IFLAG_END_CMD_RES_V(e) BF_MSC_IFLAG_END_CMD_RES(BV_MSC_IFLAG_END_CMD_RES__##e) | ||
614 | #define BFM_MSC_IFLAG_END_CMD_RES_V(v) BM_MSC_IFLAG_END_CMD_RES | ||
615 | #define BP_MSC_IFLAG_PROG_DONE 1 | ||
616 | #define BM_MSC_IFLAG_PROG_DONE 0x2 | ||
617 | #define BF_MSC_IFLAG_PROG_DONE(v) (((v) & 0x1) << 1) | ||
618 | #define BFM_MSC_IFLAG_PROG_DONE(v) BM_MSC_IFLAG_PROG_DONE | ||
619 | #define BF_MSC_IFLAG_PROG_DONE_V(e) BF_MSC_IFLAG_PROG_DONE(BV_MSC_IFLAG_PROG_DONE__##e) | ||
620 | #define BFM_MSC_IFLAG_PROG_DONE_V(v) BM_MSC_IFLAG_PROG_DONE | ||
621 | #define BP_MSC_IFLAG_DATA_TRAN_DONE 0 | ||
622 | #define BM_MSC_IFLAG_DATA_TRAN_DONE 0x1 | ||
623 | #define BF_MSC_IFLAG_DATA_TRAN_DONE(v) (((v) & 0x1) << 0) | ||
624 | #define BFM_MSC_IFLAG_DATA_TRAN_DONE(v) BM_MSC_IFLAG_DATA_TRAN_DONE | ||
625 | #define BF_MSC_IFLAG_DATA_TRAN_DONE_V(e) BF_MSC_IFLAG_DATA_TRAN_DONE(BV_MSC_IFLAG_DATA_TRAN_DONE__##e) | ||
626 | #define BFM_MSC_IFLAG_DATA_TRAN_DONE_V(v) BM_MSC_IFLAG_DATA_TRAN_DONE | ||
627 | |||
628 | #define REG_MSC_LPM(_n1) jz_reg(MSC_LPM(_n1)) | ||
629 | #define JA_MSC_LPM(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x40) | ||
630 | #define JT_MSC_LPM(_n1) JIO_32_RW | ||
631 | #define JN_MSC_LPM(_n1) MSC_LPM | ||
632 | #define JI_MSC_LPM(_n1) (_n1) | ||
633 | #define BP_MSC_LPM_DRV_SEL 30 | ||
634 | #define BM_MSC_LPM_DRV_SEL 0xc0000000 | ||
635 | #define BV_MSC_LPM_DRV_SEL__FALL_EDGE 0x0 | ||
636 | #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_1NS 0x1 | ||
637 | #define BV_MSC_LPM_DRV_SEL__RISE_EDGE_DELAY_QTR_PHASE 0x2 | ||
638 | #define BF_MSC_LPM_DRV_SEL(v) (((v) & 0x3) << 30) | ||
639 | #define BFM_MSC_LPM_DRV_SEL(v) BM_MSC_LPM_DRV_SEL | ||
640 | #define BF_MSC_LPM_DRV_SEL_V(e) BF_MSC_LPM_DRV_SEL(BV_MSC_LPM_DRV_SEL__##e) | ||
641 | #define BFM_MSC_LPM_DRV_SEL_V(v) BM_MSC_LPM_DRV_SEL | ||
642 | #define BP_MSC_LPM_SMP_SEL 28 | ||
643 | #define BM_MSC_LPM_SMP_SEL 0x30000000 | ||
644 | #define BV_MSC_LPM_SMP_SEL__RISE_EDGE 0x0 | ||
645 | #define BV_MSC_LPM_SMP_SEL__RISE_EDGE_DELAYED 0x1 | ||
646 | #define BF_MSC_LPM_SMP_SEL(v) (((v) & 0x3) << 28) | ||
647 | #define BFM_MSC_LPM_SMP_SEL(v) BM_MSC_LPM_SMP_SEL | ||
648 | #define BF_MSC_LPM_SMP_SEL_V(e) BF_MSC_LPM_SMP_SEL(BV_MSC_LPM_SMP_SEL__##e) | ||
649 | #define BFM_MSC_LPM_SMP_SEL_V(v) BM_MSC_LPM_SMP_SEL | ||
650 | #define BP_MSC_LPM_ENABLE 0 | ||
651 | #define BM_MSC_LPM_ENABLE 0x1 | ||
652 | #define BF_MSC_LPM_ENABLE(v) (((v) & 0x1) << 0) | ||
653 | #define BFM_MSC_LPM_ENABLE(v) BM_MSC_LPM_ENABLE | ||
654 | #define BF_MSC_LPM_ENABLE_V(e) BF_MSC_LPM_ENABLE(BV_MSC_LPM_ENABLE__##e) | ||
655 | #define BFM_MSC_LPM_ENABLE_V(v) BM_MSC_LPM_ENABLE | ||
656 | |||
657 | #define REG_MSC_DMAC(_n1) jz_reg(MSC_DMAC(_n1)) | ||
658 | #define JA_MSC_DMAC(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x44) | ||
659 | #define JT_MSC_DMAC(_n1) JIO_32_RW | ||
660 | #define JN_MSC_DMAC(_n1) MSC_DMAC | ||
661 | #define JI_MSC_DMAC(_n1) (_n1) | ||
662 | #define BP_MSC_DMAC_ADDR_OFFSET 5 | ||
663 | #define BM_MSC_DMAC_ADDR_OFFSET 0x60 | ||
664 | #define BF_MSC_DMAC_ADDR_OFFSET(v) (((v) & 0x3) << 5) | ||
665 | #define BFM_MSC_DMAC_ADDR_OFFSET(v) BM_MSC_DMAC_ADDR_OFFSET | ||
666 | #define BF_MSC_DMAC_ADDR_OFFSET_V(e) BF_MSC_DMAC_ADDR_OFFSET(BV_MSC_DMAC_ADDR_OFFSET__##e) | ||
667 | #define BFM_MSC_DMAC_ADDR_OFFSET_V(v) BM_MSC_DMAC_ADDR_OFFSET | ||
668 | #define BP_MSC_DMAC_INCR 2 | ||
669 | #define BM_MSC_DMAC_INCR 0xc | ||
670 | #define BF_MSC_DMAC_INCR(v) (((v) & 0x3) << 2) | ||
671 | #define BFM_MSC_DMAC_INCR(v) BM_MSC_DMAC_INCR | ||
672 | #define BF_MSC_DMAC_INCR_V(e) BF_MSC_DMAC_INCR(BV_MSC_DMAC_INCR__##e) | ||
673 | #define BFM_MSC_DMAC_INCR_V(v) BM_MSC_DMAC_INCR | ||
674 | #define BP_MSC_DMAC_MODE_SEL 7 | ||
675 | #define BM_MSC_DMAC_MODE_SEL 0x80 | ||
676 | #define BF_MSC_DMAC_MODE_SEL(v) (((v) & 0x1) << 7) | ||
677 | #define BFM_MSC_DMAC_MODE_SEL(v) BM_MSC_DMAC_MODE_SEL | ||
678 | #define BF_MSC_DMAC_MODE_SEL_V(e) BF_MSC_DMAC_MODE_SEL(BV_MSC_DMAC_MODE_SEL__##e) | ||
679 | #define BFM_MSC_DMAC_MODE_SEL_V(v) BM_MSC_DMAC_MODE_SEL | ||
680 | #define BP_MSC_DMAC_ALIGN_EN 4 | ||
681 | #define BM_MSC_DMAC_ALIGN_EN 0x10 | ||
682 | #define BF_MSC_DMAC_ALIGN_EN(v) (((v) & 0x1) << 4) | ||
683 | #define BFM_MSC_DMAC_ALIGN_EN(v) BM_MSC_DMAC_ALIGN_EN | ||
684 | #define BF_MSC_DMAC_ALIGN_EN_V(e) BF_MSC_DMAC_ALIGN_EN(BV_MSC_DMAC_ALIGN_EN__##e) | ||
685 | #define BFM_MSC_DMAC_ALIGN_EN_V(v) BM_MSC_DMAC_ALIGN_EN | ||
686 | #define BP_MSC_DMAC_DMASEL 1 | ||
687 | #define BM_MSC_DMAC_DMASEL 0x2 | ||
688 | #define BF_MSC_DMAC_DMASEL(v) (((v) & 0x1) << 1) | ||
689 | #define BFM_MSC_DMAC_DMASEL(v) BM_MSC_DMAC_DMASEL | ||
690 | #define BF_MSC_DMAC_DMASEL_V(e) BF_MSC_DMAC_DMASEL(BV_MSC_DMAC_DMASEL__##e) | ||
691 | #define BFM_MSC_DMAC_DMASEL_V(v) BM_MSC_DMAC_DMASEL | ||
692 | #define BP_MSC_DMAC_ENABLE 0 | ||
693 | #define BM_MSC_DMAC_ENABLE 0x1 | ||
694 | #define BF_MSC_DMAC_ENABLE(v) (((v) & 0x1) << 0) | ||
695 | #define BFM_MSC_DMAC_ENABLE(v) BM_MSC_DMAC_ENABLE | ||
696 | #define BF_MSC_DMAC_ENABLE_V(e) BF_MSC_DMAC_ENABLE(BV_MSC_DMAC_ENABLE__##e) | ||
697 | #define BFM_MSC_DMAC_ENABLE_V(v) BM_MSC_DMAC_ENABLE | ||
698 | |||
699 | #define REG_MSC_CTRL2(_n1) jz_reg(MSC_CTRL2(_n1)) | ||
700 | #define JA_MSC_CTRL2(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x58) | ||
701 | #define JT_MSC_CTRL2(_n1) JIO_32_RW | ||
702 | #define JN_MSC_CTRL2(_n1) MSC_CTRL2 | ||
703 | #define JI_MSC_CTRL2(_n1) (_n1) | ||
704 | #define BP_MSC_CTRL2_PIN_INT_POLARITY 24 | ||
705 | #define BM_MSC_CTRL2_PIN_INT_POLARITY 0x1f000000 | ||
706 | #define BF_MSC_CTRL2_PIN_INT_POLARITY(v) (((v) & 0x1f) << 24) | ||
707 | #define BFM_MSC_CTRL2_PIN_INT_POLARITY(v) BM_MSC_CTRL2_PIN_INT_POLARITY | ||
708 | #define BF_MSC_CTRL2_PIN_INT_POLARITY_V(e) BF_MSC_CTRL2_PIN_INT_POLARITY(BV_MSC_CTRL2_PIN_INT_POLARITY__##e) | ||
709 | #define BFM_MSC_CTRL2_PIN_INT_POLARITY_V(v) BM_MSC_CTRL2_PIN_INT_POLARITY | ||
710 | #define BP_MSC_CTRL2_SPEED 0 | ||
711 | #define BM_MSC_CTRL2_SPEED 0x7 | ||
712 | #define BV_MSC_CTRL2_SPEED__DEFAULT 0x0 | ||
713 | #define BV_MSC_CTRL2_SPEED__HIGHSPEED 0x1 | ||
714 | #define BV_MSC_CTRL2_SPEED__SDR12 0x2 | ||
715 | #define BV_MSC_CTRL2_SPEED__SDR25 0x3 | ||
716 | #define BV_MSC_CTRL2_SPEED__SDR50 0x4 | ||
717 | #define BF_MSC_CTRL2_SPEED(v) (((v) & 0x7) << 0) | ||
718 | #define BFM_MSC_CTRL2_SPEED(v) BM_MSC_CTRL2_SPEED | ||
719 | #define BF_MSC_CTRL2_SPEED_V(e) BF_MSC_CTRL2_SPEED(BV_MSC_CTRL2_SPEED__##e) | ||
720 | #define BFM_MSC_CTRL2_SPEED_V(v) BM_MSC_CTRL2_SPEED | ||
721 | #define BP_MSC_CTRL2_STPRM 4 | ||
722 | #define BM_MSC_CTRL2_STPRM 0x10 | ||
723 | #define BF_MSC_CTRL2_STPRM(v) (((v) & 0x1) << 4) | ||
724 | #define BFM_MSC_CTRL2_STPRM(v) BM_MSC_CTRL2_STPRM | ||
725 | #define BF_MSC_CTRL2_STPRM_V(e) BF_MSC_CTRL2_STPRM(BV_MSC_CTRL2_STPRM__##e) | ||
726 | #define BFM_MSC_CTRL2_STPRM_V(v) BM_MSC_CTRL2_STPRM | ||
727 | |||
728 | #define REG_MSC_CLKRT(_n1) jz_reg(MSC_CLKRT(_n1)) | ||
729 | #define JA_MSC_CLKRT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x8) | ||
730 | #define JT_MSC_CLKRT(_n1) JIO_32_RW | ||
731 | #define JN_MSC_CLKRT(_n1) MSC_CLKRT | ||
732 | #define JI_MSC_CLKRT(_n1) (_n1) | ||
733 | |||
734 | #define REG_MSC_RESTO(_n1) jz_reg(MSC_RESTO(_n1)) | ||
735 | #define JA_MSC_RESTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x10) | ||
736 | #define JT_MSC_RESTO(_n1) JIO_32_RW | ||
737 | #define JN_MSC_RESTO(_n1) MSC_RESTO | ||
738 | #define JI_MSC_RESTO(_n1) (_n1) | ||
739 | |||
740 | #define REG_MSC_RDTO(_n1) jz_reg(MSC_RDTO(_n1)) | ||
741 | #define JA_MSC_RDTO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x14) | ||
742 | #define JT_MSC_RDTO(_n1) JIO_32_RW | ||
743 | #define JN_MSC_RDTO(_n1) MSC_RDTO | ||
744 | #define JI_MSC_RDTO(_n1) (_n1) | ||
745 | |||
746 | #define REG_MSC_BLKLEN(_n1) jz_reg(MSC_BLKLEN(_n1)) | ||
747 | #define JA_MSC_BLKLEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x18) | ||
748 | #define JT_MSC_BLKLEN(_n1) JIO_32_RW | ||
749 | #define JN_MSC_BLKLEN(_n1) MSC_BLKLEN | ||
750 | #define JI_MSC_BLKLEN(_n1) (_n1) | ||
751 | |||
752 | #define REG_MSC_NOB(_n1) jz_reg(MSC_NOB(_n1)) | ||
753 | #define JA_MSC_NOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x1c) | ||
754 | #define JT_MSC_NOB(_n1) JIO_32_RW | ||
755 | #define JN_MSC_NOB(_n1) MSC_NOB | ||
756 | #define JI_MSC_NOB(_n1) (_n1) | ||
757 | |||
758 | #define REG_MSC_SNOB(_n1) jz_reg(MSC_SNOB(_n1)) | ||
759 | #define JA_MSC_SNOB(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x20) | ||
760 | #define JT_MSC_SNOB(_n1) JIO_32_RW | ||
761 | #define JN_MSC_SNOB(_n1) MSC_SNOB | ||
762 | #define JI_MSC_SNOB(_n1) (_n1) | ||
763 | |||
764 | #define REG_MSC_CMD(_n1) jz_reg(MSC_CMD(_n1)) | ||
765 | #define JA_MSC_CMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x2c) | ||
766 | #define JT_MSC_CMD(_n1) JIO_32_RW | ||
767 | #define JN_MSC_CMD(_n1) MSC_CMD | ||
768 | #define JI_MSC_CMD(_n1) (_n1) | ||
769 | |||
770 | #define REG_MSC_ARG(_n1) jz_reg(MSC_ARG(_n1)) | ||
771 | #define JA_MSC_ARG(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x30) | ||
772 | #define JT_MSC_ARG(_n1) JIO_32_RW | ||
773 | #define JN_MSC_ARG(_n1) MSC_ARG | ||
774 | #define JI_MSC_ARG(_n1) (_n1) | ||
775 | |||
776 | #define REG_MSC_RES(_n1) jz_reg(MSC_RES(_n1)) | ||
777 | #define JA_MSC_RES(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x34) | ||
778 | #define JT_MSC_RES(_n1) JIO_32_RW | ||
779 | #define JN_MSC_RES(_n1) MSC_RES | ||
780 | #define JI_MSC_RES(_n1) (_n1) | ||
781 | |||
782 | #define REG_MSC_RXFIFO(_n1) jz_reg(MSC_RXFIFO(_n1)) | ||
783 | #define JA_MSC_RXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x38) | ||
784 | #define JT_MSC_RXFIFO(_n1) JIO_32_RW | ||
785 | #define JN_MSC_RXFIFO(_n1) MSC_RXFIFO | ||
786 | #define JI_MSC_RXFIFO(_n1) (_n1) | ||
787 | |||
788 | #define REG_MSC_TXFIFO(_n1) jz_reg(MSC_TXFIFO(_n1)) | ||
789 | #define JA_MSC_TXFIFO(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x3c) | ||
790 | #define JT_MSC_TXFIFO(_n1) JIO_32_RW | ||
791 | #define JN_MSC_TXFIFO(_n1) MSC_TXFIFO | ||
792 | #define JI_MSC_TXFIFO(_n1) (_n1) | ||
793 | |||
794 | #define REG_MSC_DMANDA(_n1) jz_reg(MSC_DMANDA(_n1)) | ||
795 | #define JA_MSC_DMANDA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x48) | ||
796 | #define JT_MSC_DMANDA(_n1) JIO_32_RW | ||
797 | #define JN_MSC_DMANDA(_n1) MSC_DMANDA | ||
798 | #define JI_MSC_DMANDA(_n1) (_n1) | ||
799 | |||
800 | #define REG_MSC_DMADA(_n1) jz_reg(MSC_DMADA(_n1)) | ||
801 | #define JA_MSC_DMADA(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x4c) | ||
802 | #define JT_MSC_DMADA(_n1) JIO_32_RW | ||
803 | #define JN_MSC_DMADA(_n1) MSC_DMADA | ||
804 | #define JI_MSC_DMADA(_n1) (_n1) | ||
805 | |||
806 | #define REG_MSC_DMALEN(_n1) jz_reg(MSC_DMALEN(_n1)) | ||
807 | #define JA_MSC_DMALEN(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x50) | ||
808 | #define JT_MSC_DMALEN(_n1) JIO_32_RW | ||
809 | #define JN_MSC_DMALEN(_n1) MSC_DMALEN | ||
810 | #define JI_MSC_DMALEN(_n1) (_n1) | ||
811 | |||
812 | #define REG_MSC_DMACMD(_n1) jz_reg(MSC_DMACMD(_n1)) | ||
813 | #define JA_MSC_DMACMD(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x54) | ||
814 | #define JT_MSC_DMACMD(_n1) JIO_32_RW | ||
815 | #define JN_MSC_DMACMD(_n1) MSC_DMACMD | ||
816 | #define JI_MSC_DMACMD(_n1) (_n1) | ||
817 | |||
818 | #define REG_MSC_RTCNT(_n1) jz_reg(MSC_RTCNT(_n1)) | ||
819 | #define JA_MSC_RTCNT(_n1) (0xb3450000 + (_n1) * 0x10000 + 0x5c) | ||
820 | #define JT_MSC_RTCNT(_n1) JIO_32_RW | ||
821 | #define JN_MSC_RTCNT(_n1) MSC_RTCNT | ||
822 | #define JI_MSC_RTCNT(_n1) (_n1) | ||
823 | |||
824 | #endif /* __HEADERGEN_MSC_H__*/ | ||