diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/cpm.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/cpm.h | 896 |
1 files changed, 896 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/cpm.h b/firmware/target/mips/ingenic_x1000/x1000/cpm.h new file mode 100644 index 0000000000..752d270f20 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/cpm.h | |||
@@ -0,0 +1,896 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_CPM_H__ | ||
25 | #define __HEADERGEN_CPM_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_CPM_CCR jz_reg(CPM_CCR) | ||
30 | #define JA_CPM_CCR (0xb0000000 + 0x0) | ||
31 | #define JT_CPM_CCR JIO_32_RW | ||
32 | #define JN_CPM_CCR CPM_CCR | ||
33 | #define JI_CPM_CCR | ||
34 | #define BP_CPM_CCR_SEL_SRC 30 | ||
35 | #define BM_CPM_CCR_SEL_SRC 0xc0000000 | ||
36 | #define BV_CPM_CCR_SEL_SRC__STOP 0x0 | ||
37 | #define BV_CPM_CCR_SEL_SRC__EXCLK 0x1 | ||
38 | #define BV_CPM_CCR_SEL_SRC__APLL 0x2 | ||
39 | #define BF_CPM_CCR_SEL_SRC(v) (((v) & 0x3) << 30) | ||
40 | #define BFM_CPM_CCR_SEL_SRC(v) BM_CPM_CCR_SEL_SRC | ||
41 | #define BF_CPM_CCR_SEL_SRC_V(e) BF_CPM_CCR_SEL_SRC(BV_CPM_CCR_SEL_SRC__##e) | ||
42 | #define BFM_CPM_CCR_SEL_SRC_V(v) BM_CPM_CCR_SEL_SRC | ||
43 | #define BP_CPM_CCR_SEL_CPLL 28 | ||
44 | #define BM_CPM_CCR_SEL_CPLL 0x30000000 | ||
45 | #define BV_CPM_CCR_SEL_CPLL__STOP 0x0 | ||
46 | #define BV_CPM_CCR_SEL_CPLL__SCLK_A 0x1 | ||
47 | #define BV_CPM_CCR_SEL_CPLL__MPLL 0x2 | ||
48 | #define BF_CPM_CCR_SEL_CPLL(v) (((v) & 0x3) << 28) | ||
49 | #define BFM_CPM_CCR_SEL_CPLL(v) BM_CPM_CCR_SEL_CPLL | ||
50 | #define BF_CPM_CCR_SEL_CPLL_V(e) BF_CPM_CCR_SEL_CPLL(BV_CPM_CCR_SEL_CPLL__##e) | ||
51 | #define BFM_CPM_CCR_SEL_CPLL_V(v) BM_CPM_CCR_SEL_CPLL | ||
52 | #define BP_CPM_CCR_SEL_H0PLL 26 | ||
53 | #define BM_CPM_CCR_SEL_H0PLL 0xc000000 | ||
54 | #define BV_CPM_CCR_SEL_H0PLL__STOP 0x0 | ||
55 | #define BV_CPM_CCR_SEL_H0PLL__SCLK_A 0x1 | ||
56 | #define BV_CPM_CCR_SEL_H0PLL__MPLL 0x2 | ||
57 | #define BF_CPM_CCR_SEL_H0PLL(v) (((v) & 0x3) << 26) | ||
58 | #define BFM_CPM_CCR_SEL_H0PLL(v) BM_CPM_CCR_SEL_H0PLL | ||
59 | #define BF_CPM_CCR_SEL_H0PLL_V(e) BF_CPM_CCR_SEL_H0PLL(BV_CPM_CCR_SEL_H0PLL__##e) | ||
60 | #define BFM_CPM_CCR_SEL_H0PLL_V(v) BM_CPM_CCR_SEL_H0PLL | ||
61 | #define BP_CPM_CCR_SEL_H2PLL 24 | ||
62 | #define BM_CPM_CCR_SEL_H2PLL 0x3000000 | ||
63 | #define BV_CPM_CCR_SEL_H2PLL__STOP 0x0 | ||
64 | #define BV_CPM_CCR_SEL_H2PLL__SCLK_A 0x1 | ||
65 | #define BV_CPM_CCR_SEL_H2PLL__MPLL 0x2 | ||
66 | #define BF_CPM_CCR_SEL_H2PLL(v) (((v) & 0x3) << 24) | ||
67 | #define BFM_CPM_CCR_SEL_H2PLL(v) BM_CPM_CCR_SEL_H2PLL | ||
68 | #define BF_CPM_CCR_SEL_H2PLL_V(e) BF_CPM_CCR_SEL_H2PLL(BV_CPM_CCR_SEL_H2PLL__##e) | ||
69 | #define BFM_CPM_CCR_SEL_H2PLL_V(v) BM_CPM_CCR_SEL_H2PLL | ||
70 | #define BP_CPM_CCR_PDIV 16 | ||
71 | #define BM_CPM_CCR_PDIV 0xf0000 | ||
72 | #define BF_CPM_CCR_PDIV(v) (((v) & 0xf) << 16) | ||
73 | #define BFM_CPM_CCR_PDIV(v) BM_CPM_CCR_PDIV | ||
74 | #define BF_CPM_CCR_PDIV_V(e) BF_CPM_CCR_PDIV(BV_CPM_CCR_PDIV__##e) | ||
75 | #define BFM_CPM_CCR_PDIV_V(v) BM_CPM_CCR_PDIV | ||
76 | #define BP_CPM_CCR_H2DIV 12 | ||
77 | #define BM_CPM_CCR_H2DIV 0xf000 | ||
78 | #define BF_CPM_CCR_H2DIV(v) (((v) & 0xf) << 12) | ||
79 | #define BFM_CPM_CCR_H2DIV(v) BM_CPM_CCR_H2DIV | ||
80 | #define BF_CPM_CCR_H2DIV_V(e) BF_CPM_CCR_H2DIV(BV_CPM_CCR_H2DIV__##e) | ||
81 | #define BFM_CPM_CCR_H2DIV_V(v) BM_CPM_CCR_H2DIV | ||
82 | #define BP_CPM_CCR_H0DIV 8 | ||
83 | #define BM_CPM_CCR_H0DIV 0xf00 | ||
84 | #define BF_CPM_CCR_H0DIV(v) (((v) & 0xf) << 8) | ||
85 | #define BFM_CPM_CCR_H0DIV(v) BM_CPM_CCR_H0DIV | ||
86 | #define BF_CPM_CCR_H0DIV_V(e) BF_CPM_CCR_H0DIV(BV_CPM_CCR_H0DIV__##e) | ||
87 | #define BFM_CPM_CCR_H0DIV_V(v) BM_CPM_CCR_H0DIV | ||
88 | #define BP_CPM_CCR_L2DIV 4 | ||
89 | #define BM_CPM_CCR_L2DIV 0xf0 | ||
90 | #define BF_CPM_CCR_L2DIV(v) (((v) & 0xf) << 4) | ||
91 | #define BFM_CPM_CCR_L2DIV(v) BM_CPM_CCR_L2DIV | ||
92 | #define BF_CPM_CCR_L2DIV_V(e) BF_CPM_CCR_L2DIV(BV_CPM_CCR_L2DIV__##e) | ||
93 | #define BFM_CPM_CCR_L2DIV_V(v) BM_CPM_CCR_L2DIV | ||
94 | #define BP_CPM_CCR_CDIV 0 | ||
95 | #define BM_CPM_CCR_CDIV 0xf | ||
96 | #define BF_CPM_CCR_CDIV(v) (((v) & 0xf) << 0) | ||
97 | #define BFM_CPM_CCR_CDIV(v) BM_CPM_CCR_CDIV | ||
98 | #define BF_CPM_CCR_CDIV_V(e) BF_CPM_CCR_CDIV(BV_CPM_CCR_CDIV__##e) | ||
99 | #define BFM_CPM_CCR_CDIV_V(v) BM_CPM_CCR_CDIV | ||
100 | #define BP_CPM_CCR_GATE_SCLKA 23 | ||
101 | #define BM_CPM_CCR_GATE_SCLKA 0x800000 | ||
102 | #define BF_CPM_CCR_GATE_SCLKA(v) (((v) & 0x1) << 23) | ||
103 | #define BFM_CPM_CCR_GATE_SCLKA(v) BM_CPM_CCR_GATE_SCLKA | ||
104 | #define BF_CPM_CCR_GATE_SCLKA_V(e) BF_CPM_CCR_GATE_SCLKA(BV_CPM_CCR_GATE_SCLKA__##e) | ||
105 | #define BFM_CPM_CCR_GATE_SCLKA_V(v) BM_CPM_CCR_GATE_SCLKA | ||
106 | #define BP_CPM_CCR_CE_CPU 22 | ||
107 | #define BM_CPM_CCR_CE_CPU 0x400000 | ||
108 | #define BF_CPM_CCR_CE_CPU(v) (((v) & 0x1) << 22) | ||
109 | #define BFM_CPM_CCR_CE_CPU(v) BM_CPM_CCR_CE_CPU | ||
110 | #define BF_CPM_CCR_CE_CPU_V(e) BF_CPM_CCR_CE_CPU(BV_CPM_CCR_CE_CPU__##e) | ||
111 | #define BFM_CPM_CCR_CE_CPU_V(v) BM_CPM_CCR_CE_CPU | ||
112 | #define BP_CPM_CCR_CE_AHB0 21 | ||
113 | #define BM_CPM_CCR_CE_AHB0 0x200000 | ||
114 | #define BF_CPM_CCR_CE_AHB0(v) (((v) & 0x1) << 21) | ||
115 | #define BFM_CPM_CCR_CE_AHB0(v) BM_CPM_CCR_CE_AHB0 | ||
116 | #define BF_CPM_CCR_CE_AHB0_V(e) BF_CPM_CCR_CE_AHB0(BV_CPM_CCR_CE_AHB0__##e) | ||
117 | #define BFM_CPM_CCR_CE_AHB0_V(v) BM_CPM_CCR_CE_AHB0 | ||
118 | #define BP_CPM_CCR_CE_AHB2 20 | ||
119 | #define BM_CPM_CCR_CE_AHB2 0x100000 | ||
120 | #define BF_CPM_CCR_CE_AHB2(v) (((v) & 0x1) << 20) | ||
121 | #define BFM_CPM_CCR_CE_AHB2(v) BM_CPM_CCR_CE_AHB2 | ||
122 | #define BF_CPM_CCR_CE_AHB2_V(e) BF_CPM_CCR_CE_AHB2(BV_CPM_CCR_CE_AHB2__##e) | ||
123 | #define BFM_CPM_CCR_CE_AHB2_V(v) BM_CPM_CCR_CE_AHB2 | ||
124 | |||
125 | #define REG_CPM_CSR jz_reg(CPM_CSR) | ||
126 | #define JA_CPM_CSR (0xb0000000 + 0xd4) | ||
127 | #define JT_CPM_CSR JIO_32_RW | ||
128 | #define JN_CPM_CSR CPM_CSR | ||
129 | #define JI_CPM_CSR | ||
130 | #define BP_CPM_CSR_SRC_MUX 31 | ||
131 | #define BM_CPM_CSR_SRC_MUX 0x80000000 | ||
132 | #define BF_CPM_CSR_SRC_MUX(v) (((v) & 0x1) << 31) | ||
133 | #define BFM_CPM_CSR_SRC_MUX(v) BM_CPM_CSR_SRC_MUX | ||
134 | #define BF_CPM_CSR_SRC_MUX_V(e) BF_CPM_CSR_SRC_MUX(BV_CPM_CSR_SRC_MUX__##e) | ||
135 | #define BFM_CPM_CSR_SRC_MUX_V(v) BM_CPM_CSR_SRC_MUX | ||
136 | #define BP_CPM_CSR_CPU_MUX 30 | ||
137 | #define BM_CPM_CSR_CPU_MUX 0x40000000 | ||
138 | #define BF_CPM_CSR_CPU_MUX(v) (((v) & 0x1) << 30) | ||
139 | #define BFM_CPM_CSR_CPU_MUX(v) BM_CPM_CSR_CPU_MUX | ||
140 | #define BF_CPM_CSR_CPU_MUX_V(e) BF_CPM_CSR_CPU_MUX(BV_CPM_CSR_CPU_MUX__##e) | ||
141 | #define BFM_CPM_CSR_CPU_MUX_V(v) BM_CPM_CSR_CPU_MUX | ||
142 | #define BP_CPM_CSR_AHB0_MUX 29 | ||
143 | #define BM_CPM_CSR_AHB0_MUX 0x20000000 | ||
144 | #define BF_CPM_CSR_AHB0_MUX(v) (((v) & 0x1) << 29) | ||
145 | #define BFM_CPM_CSR_AHB0_MUX(v) BM_CPM_CSR_AHB0_MUX | ||
146 | #define BF_CPM_CSR_AHB0_MUX_V(e) BF_CPM_CSR_AHB0_MUX(BV_CPM_CSR_AHB0_MUX__##e) | ||
147 | #define BFM_CPM_CSR_AHB0_MUX_V(v) BM_CPM_CSR_AHB0_MUX | ||
148 | #define BP_CPM_CSR_AHB2_MUX 28 | ||
149 | #define BM_CPM_CSR_AHB2_MUX 0x10000000 | ||
150 | #define BF_CPM_CSR_AHB2_MUX(v) (((v) & 0x1) << 28) | ||
151 | #define BFM_CPM_CSR_AHB2_MUX(v) BM_CPM_CSR_AHB2_MUX | ||
152 | #define BF_CPM_CSR_AHB2_MUX_V(e) BF_CPM_CSR_AHB2_MUX(BV_CPM_CSR_AHB2_MUX__##e) | ||
153 | #define BFM_CPM_CSR_AHB2_MUX_V(v) BM_CPM_CSR_AHB2_MUX | ||
154 | #define BP_CPM_CSR_DDR_MUX 27 | ||
155 | #define BM_CPM_CSR_DDR_MUX 0x8000000 | ||
156 | #define BF_CPM_CSR_DDR_MUX(v) (((v) & 0x1) << 27) | ||
157 | #define BFM_CPM_CSR_DDR_MUX(v) BM_CPM_CSR_DDR_MUX | ||
158 | #define BF_CPM_CSR_DDR_MUX_V(e) BF_CPM_CSR_DDR_MUX(BV_CPM_CSR_DDR_MUX__##e) | ||
159 | #define BFM_CPM_CSR_DDR_MUX_V(v) BM_CPM_CSR_DDR_MUX | ||
160 | #define BP_CPM_CSR_H2DIV_BUSY 2 | ||
161 | #define BM_CPM_CSR_H2DIV_BUSY 0x4 | ||
162 | #define BF_CPM_CSR_H2DIV_BUSY(v) (((v) & 0x1) << 2) | ||
163 | #define BFM_CPM_CSR_H2DIV_BUSY(v) BM_CPM_CSR_H2DIV_BUSY | ||
164 | #define BF_CPM_CSR_H2DIV_BUSY_V(e) BF_CPM_CSR_H2DIV_BUSY(BV_CPM_CSR_H2DIV_BUSY__##e) | ||
165 | #define BFM_CPM_CSR_H2DIV_BUSY_V(v) BM_CPM_CSR_H2DIV_BUSY | ||
166 | #define BP_CPM_CSR_H0DIV_BUSY 1 | ||
167 | #define BM_CPM_CSR_H0DIV_BUSY 0x2 | ||
168 | #define BF_CPM_CSR_H0DIV_BUSY(v) (((v) & 0x1) << 1) | ||
169 | #define BFM_CPM_CSR_H0DIV_BUSY(v) BM_CPM_CSR_H0DIV_BUSY | ||
170 | #define BF_CPM_CSR_H0DIV_BUSY_V(e) BF_CPM_CSR_H0DIV_BUSY(BV_CPM_CSR_H0DIV_BUSY__##e) | ||
171 | #define BFM_CPM_CSR_H0DIV_BUSY_V(v) BM_CPM_CSR_H0DIV_BUSY | ||
172 | #define BP_CPM_CSR_CDIV_BUSY 0 | ||
173 | #define BM_CPM_CSR_CDIV_BUSY 0x1 | ||
174 | #define BF_CPM_CSR_CDIV_BUSY(v) (((v) & 0x1) << 0) | ||
175 | #define BFM_CPM_CSR_CDIV_BUSY(v) BM_CPM_CSR_CDIV_BUSY | ||
176 | #define BF_CPM_CSR_CDIV_BUSY_V(e) BF_CPM_CSR_CDIV_BUSY(BV_CPM_CSR_CDIV_BUSY__##e) | ||
177 | #define BFM_CPM_CSR_CDIV_BUSY_V(v) BM_CPM_CSR_CDIV_BUSY | ||
178 | |||
179 | #define REG_CPM_DDRCDR jz_reg(CPM_DDRCDR) | ||
180 | #define JA_CPM_DDRCDR (0xb0000000 + 0x2c) | ||
181 | #define JT_CPM_DDRCDR JIO_32_RW | ||
182 | #define JN_CPM_DDRCDR CPM_DDRCDR | ||
183 | #define JI_CPM_DDRCDR | ||
184 | #define BP_CPM_DDRCDR_CLKSRC 30 | ||
185 | #define BM_CPM_DDRCDR_CLKSRC 0xc0000000 | ||
186 | #define BV_CPM_DDRCDR_CLKSRC__STOP 0x0 | ||
187 | #define BV_CPM_DDRCDR_CLKSRC__SCLK_A 0x1 | ||
188 | #define BV_CPM_DDRCDR_CLKSRC__MPLL 0x2 | ||
189 | #define BF_CPM_DDRCDR_CLKSRC(v) (((v) & 0x3) << 30) | ||
190 | #define BFM_CPM_DDRCDR_CLKSRC(v) BM_CPM_DDRCDR_CLKSRC | ||
191 | #define BF_CPM_DDRCDR_CLKSRC_V(e) BF_CPM_DDRCDR_CLKSRC(BV_CPM_DDRCDR_CLKSRC__##e) | ||
192 | #define BFM_CPM_DDRCDR_CLKSRC_V(v) BM_CPM_DDRCDR_CLKSRC | ||
193 | #define BP_CPM_DDRCDR_CLKDIV 0 | ||
194 | #define BM_CPM_DDRCDR_CLKDIV 0xf | ||
195 | #define BF_CPM_DDRCDR_CLKDIV(v) (((v) & 0xf) << 0) | ||
196 | #define BFM_CPM_DDRCDR_CLKDIV(v) BM_CPM_DDRCDR_CLKDIV | ||
197 | #define BF_CPM_DDRCDR_CLKDIV_V(e) BF_CPM_DDRCDR_CLKDIV(BV_CPM_DDRCDR_CLKDIV__##e) | ||
198 | #define BFM_CPM_DDRCDR_CLKDIV_V(v) BM_CPM_DDRCDR_CLKDIV | ||
199 | #define BP_CPM_DDRCDR_CE 29 | ||
200 | #define BM_CPM_DDRCDR_CE 0x20000000 | ||
201 | #define BF_CPM_DDRCDR_CE(v) (((v) & 0x1) << 29) | ||
202 | #define BFM_CPM_DDRCDR_CE(v) BM_CPM_DDRCDR_CE | ||
203 | #define BF_CPM_DDRCDR_CE_V(e) BF_CPM_DDRCDR_CE(BV_CPM_DDRCDR_CE__##e) | ||
204 | #define BFM_CPM_DDRCDR_CE_V(v) BM_CPM_DDRCDR_CE | ||
205 | #define BP_CPM_DDRCDR_BUSY 28 | ||
206 | #define BM_CPM_DDRCDR_BUSY 0x10000000 | ||
207 | #define BF_CPM_DDRCDR_BUSY(v) (((v) & 0x1) << 28) | ||
208 | #define BFM_CPM_DDRCDR_BUSY(v) BM_CPM_DDRCDR_BUSY | ||
209 | #define BF_CPM_DDRCDR_BUSY_V(e) BF_CPM_DDRCDR_BUSY(BV_CPM_DDRCDR_BUSY__##e) | ||
210 | #define BFM_CPM_DDRCDR_BUSY_V(v) BM_CPM_DDRCDR_BUSY | ||
211 | #define BP_CPM_DDRCDR_STOP 27 | ||
212 | #define BM_CPM_DDRCDR_STOP 0x8000000 | ||
213 | #define BF_CPM_DDRCDR_STOP(v) (((v) & 0x1) << 27) | ||
214 | #define BFM_CPM_DDRCDR_STOP(v) BM_CPM_DDRCDR_STOP | ||
215 | #define BF_CPM_DDRCDR_STOP_V(e) BF_CPM_DDRCDR_STOP(BV_CPM_DDRCDR_STOP__##e) | ||
216 | #define BFM_CPM_DDRCDR_STOP_V(v) BM_CPM_DDRCDR_STOP | ||
217 | #define BP_CPM_DDRCDR_GATE_EN 26 | ||
218 | #define BM_CPM_DDRCDR_GATE_EN 0x4000000 | ||
219 | #define BF_CPM_DDRCDR_GATE_EN(v) (((v) & 0x1) << 26) | ||
220 | #define BFM_CPM_DDRCDR_GATE_EN(v) BM_CPM_DDRCDR_GATE_EN | ||
221 | #define BF_CPM_DDRCDR_GATE_EN_V(e) BF_CPM_DDRCDR_GATE_EN(BV_CPM_DDRCDR_GATE_EN__##e) | ||
222 | #define BFM_CPM_DDRCDR_GATE_EN_V(v) BM_CPM_DDRCDR_GATE_EN | ||
223 | #define BP_CPM_DDRCDR_CHANGE_EN 25 | ||
224 | #define BM_CPM_DDRCDR_CHANGE_EN 0x2000000 | ||
225 | #define BF_CPM_DDRCDR_CHANGE_EN(v) (((v) & 0x1) << 25) | ||
226 | #define BFM_CPM_DDRCDR_CHANGE_EN(v) BM_CPM_DDRCDR_CHANGE_EN | ||
227 | #define BF_CPM_DDRCDR_CHANGE_EN_V(e) BF_CPM_DDRCDR_CHANGE_EN(BV_CPM_DDRCDR_CHANGE_EN__##e) | ||
228 | #define BFM_CPM_DDRCDR_CHANGE_EN_V(v) BM_CPM_DDRCDR_CHANGE_EN | ||
229 | #define BP_CPM_DDRCDR_FLAG 24 | ||
230 | #define BM_CPM_DDRCDR_FLAG 0x1000000 | ||
231 | #define BF_CPM_DDRCDR_FLAG(v) (((v) & 0x1) << 24) | ||
232 | #define BFM_CPM_DDRCDR_FLAG(v) BM_CPM_DDRCDR_FLAG | ||
233 | #define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e) | ||
234 | #define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG | ||
235 | |||
236 | #define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR) | ||
237 | #define JA_CPM_I2SCDR (0xb0000000 + 0x60) | ||
238 | #define JT_CPM_I2SCDR JIO_32_RW | ||
239 | #define JN_CPM_I2SCDR CPM_I2SCDR | ||
240 | #define JI_CPM_I2SCDR | ||
241 | #define BP_CPM_I2SCDR_DIV_M 13 | ||
242 | #define BM_CPM_I2SCDR_DIV_M 0x3fe000 | ||
243 | #define BF_CPM_I2SCDR_DIV_M(v) (((v) & 0x1ff) << 13) | ||
244 | #define BFM_CPM_I2SCDR_DIV_M(v) BM_CPM_I2SCDR_DIV_M | ||
245 | #define BF_CPM_I2SCDR_DIV_M_V(e) BF_CPM_I2SCDR_DIV_M(BV_CPM_I2SCDR_DIV_M__##e) | ||
246 | #define BFM_CPM_I2SCDR_DIV_M_V(v) BM_CPM_I2SCDR_DIV_M | ||
247 | #define BP_CPM_I2SCDR_DIV_N 0 | ||
248 | #define BM_CPM_I2SCDR_DIV_N 0x1fff | ||
249 | #define BF_CPM_I2SCDR_DIV_N(v) (((v) & 0x1fff) << 0) | ||
250 | #define BFM_CPM_I2SCDR_DIV_N(v) BM_CPM_I2SCDR_DIV_N | ||
251 | #define BF_CPM_I2SCDR_DIV_N_V(e) BF_CPM_I2SCDR_DIV_N(BV_CPM_I2SCDR_DIV_N__##e) | ||
252 | #define BFM_CPM_I2SCDR_DIV_N_V(v) BM_CPM_I2SCDR_DIV_N | ||
253 | #define BP_CPM_I2SCDR_PCS 31 | ||
254 | #define BM_CPM_I2SCDR_PCS 0x80000000 | ||
255 | #define BV_CPM_I2SCDR_PCS__SCLK_A 0x0 | ||
256 | #define BV_CPM_I2SCDR_PCS__MPLL 0x1 | ||
257 | #define BF_CPM_I2SCDR_PCS(v) (((v) & 0x1) << 31) | ||
258 | #define BFM_CPM_I2SCDR_PCS(v) BM_CPM_I2SCDR_PCS | ||
259 | #define BF_CPM_I2SCDR_PCS_V(e) BF_CPM_I2SCDR_PCS(BV_CPM_I2SCDR_PCS__##e) | ||
260 | #define BFM_CPM_I2SCDR_PCS_V(v) BM_CPM_I2SCDR_PCS | ||
261 | #define BP_CPM_I2SCDR_CS 30 | ||
262 | #define BM_CPM_I2SCDR_CS 0x40000000 | ||
263 | #define BV_CPM_I2SCDR_CS__EXCLK 0x0 | ||
264 | #define BV_CPM_I2SCDR_CS__PLL 0x1 | ||
265 | #define BF_CPM_I2SCDR_CS(v) (((v) & 0x1) << 30) | ||
266 | #define BFM_CPM_I2SCDR_CS(v) BM_CPM_I2SCDR_CS | ||
267 | #define BF_CPM_I2SCDR_CS_V(e) BF_CPM_I2SCDR_CS(BV_CPM_I2SCDR_CS__##e) | ||
268 | #define BFM_CPM_I2SCDR_CS_V(v) BM_CPM_I2SCDR_CS | ||
269 | #define BP_CPM_I2SCDR_CE 29 | ||
270 | #define BM_CPM_I2SCDR_CE 0x20000000 | ||
271 | #define BF_CPM_I2SCDR_CE(v) (((v) & 0x1) << 29) | ||
272 | #define BFM_CPM_I2SCDR_CE(v) BM_CPM_I2SCDR_CE | ||
273 | #define BF_CPM_I2SCDR_CE_V(e) BF_CPM_I2SCDR_CE(BV_CPM_I2SCDR_CE__##e) | ||
274 | #define BFM_CPM_I2SCDR_CE_V(v) BM_CPM_I2SCDR_CE | ||
275 | |||
276 | #define REG_CPM_I2SCDR1 jz_reg(CPM_I2SCDR1) | ||
277 | #define JA_CPM_I2SCDR1 (0xb0000000 + 0x70) | ||
278 | #define JT_CPM_I2SCDR1 JIO_32_RW | ||
279 | #define JN_CPM_I2SCDR1 CPM_I2SCDR1 | ||
280 | #define JI_CPM_I2SCDR1 | ||
281 | |||
282 | #define REG_CPM_LPCDR jz_reg(CPM_LPCDR) | ||
283 | #define JA_CPM_LPCDR (0xb0000000 + 0x64) | ||
284 | #define JT_CPM_LPCDR JIO_32_RW | ||
285 | #define JN_CPM_LPCDR CPM_LPCDR | ||
286 | #define JI_CPM_LPCDR | ||
287 | #define BP_CPM_LPCDR_CLKDIV 0 | ||
288 | #define BM_CPM_LPCDR_CLKDIV 0xff | ||
289 | #define BF_CPM_LPCDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
290 | #define BFM_CPM_LPCDR_CLKDIV(v) BM_CPM_LPCDR_CLKDIV | ||
291 | #define BF_CPM_LPCDR_CLKDIV_V(e) BF_CPM_LPCDR_CLKDIV(BV_CPM_LPCDR_CLKDIV__##e) | ||
292 | #define BFM_CPM_LPCDR_CLKDIV_V(v) BM_CPM_LPCDR_CLKDIV | ||
293 | #define BP_CPM_LPCDR_CLKSRC 31 | ||
294 | #define BM_CPM_LPCDR_CLKSRC 0x80000000 | ||
295 | #define BV_CPM_LPCDR_CLKSRC__SCLK_A 0x0 | ||
296 | #define BV_CPM_LPCDR_CLKSRC__MPLL 0x1 | ||
297 | #define BF_CPM_LPCDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
298 | #define BFM_CPM_LPCDR_CLKSRC(v) BM_CPM_LPCDR_CLKSRC | ||
299 | #define BF_CPM_LPCDR_CLKSRC_V(e) BF_CPM_LPCDR_CLKSRC(BV_CPM_LPCDR_CLKSRC__##e) | ||
300 | #define BFM_CPM_LPCDR_CLKSRC_V(v) BM_CPM_LPCDR_CLKSRC | ||
301 | #define BP_CPM_LPCDR_CE 28 | ||
302 | #define BM_CPM_LPCDR_CE 0x10000000 | ||
303 | #define BF_CPM_LPCDR_CE(v) (((v) & 0x1) << 28) | ||
304 | #define BFM_CPM_LPCDR_CE(v) BM_CPM_LPCDR_CE | ||
305 | #define BF_CPM_LPCDR_CE_V(e) BF_CPM_LPCDR_CE(BV_CPM_LPCDR_CE__##e) | ||
306 | #define BFM_CPM_LPCDR_CE_V(v) BM_CPM_LPCDR_CE | ||
307 | #define BP_CPM_LPCDR_BUSY 27 | ||
308 | #define BM_CPM_LPCDR_BUSY 0x8000000 | ||
309 | #define BF_CPM_LPCDR_BUSY(v) (((v) & 0x1) << 27) | ||
310 | #define BFM_CPM_LPCDR_BUSY(v) BM_CPM_LPCDR_BUSY | ||
311 | #define BF_CPM_LPCDR_BUSY_V(e) BF_CPM_LPCDR_BUSY(BV_CPM_LPCDR_BUSY__##e) | ||
312 | #define BFM_CPM_LPCDR_BUSY_V(v) BM_CPM_LPCDR_BUSY | ||
313 | #define BP_CPM_LPCDR_STOP 26 | ||
314 | #define BM_CPM_LPCDR_STOP 0x4000000 | ||
315 | #define BF_CPM_LPCDR_STOP(v) (((v) & 0x1) << 26) | ||
316 | #define BFM_CPM_LPCDR_STOP(v) BM_CPM_LPCDR_STOP | ||
317 | #define BF_CPM_LPCDR_STOP_V(e) BF_CPM_LPCDR_STOP(BV_CPM_LPCDR_STOP__##e) | ||
318 | #define BFM_CPM_LPCDR_STOP_V(v) BM_CPM_LPCDR_STOP | ||
319 | |||
320 | #define REG_CPM_MSC0CDR jz_reg(CPM_MSC0CDR) | ||
321 | #define JA_CPM_MSC0CDR (0xb0000000 + 0x68) | ||
322 | #define JT_CPM_MSC0CDR JIO_32_RW | ||
323 | #define JN_CPM_MSC0CDR CPM_MSC0CDR | ||
324 | #define JI_CPM_MSC0CDR | ||
325 | #define BP_CPM_MSC0CDR_CLKDIV 0 | ||
326 | #define BM_CPM_MSC0CDR_CLKDIV 0xff | ||
327 | #define BF_CPM_MSC0CDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
328 | #define BFM_CPM_MSC0CDR_CLKDIV(v) BM_CPM_MSC0CDR_CLKDIV | ||
329 | #define BF_CPM_MSC0CDR_CLKDIV_V(e) BF_CPM_MSC0CDR_CLKDIV(BV_CPM_MSC0CDR_CLKDIV__##e) | ||
330 | #define BFM_CPM_MSC0CDR_CLKDIV_V(v) BM_CPM_MSC0CDR_CLKDIV | ||
331 | #define BP_CPM_MSC0CDR_CLKSRC 31 | ||
332 | #define BM_CPM_MSC0CDR_CLKSRC 0x80000000 | ||
333 | #define BV_CPM_MSC0CDR_CLKSRC__SCLK_A 0x0 | ||
334 | #define BV_CPM_MSC0CDR_CLKSRC__MPLL 0x1 | ||
335 | #define BF_CPM_MSC0CDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
336 | #define BFM_CPM_MSC0CDR_CLKSRC(v) BM_CPM_MSC0CDR_CLKSRC | ||
337 | #define BF_CPM_MSC0CDR_CLKSRC_V(e) BF_CPM_MSC0CDR_CLKSRC(BV_CPM_MSC0CDR_CLKSRC__##e) | ||
338 | #define BFM_CPM_MSC0CDR_CLKSRC_V(v) BM_CPM_MSC0CDR_CLKSRC | ||
339 | #define BP_CPM_MSC0CDR_CE 29 | ||
340 | #define BM_CPM_MSC0CDR_CE 0x20000000 | ||
341 | #define BF_CPM_MSC0CDR_CE(v) (((v) & 0x1) << 29) | ||
342 | #define BFM_CPM_MSC0CDR_CE(v) BM_CPM_MSC0CDR_CE | ||
343 | #define BF_CPM_MSC0CDR_CE_V(e) BF_CPM_MSC0CDR_CE(BV_CPM_MSC0CDR_CE__##e) | ||
344 | #define BFM_CPM_MSC0CDR_CE_V(v) BM_CPM_MSC0CDR_CE | ||
345 | #define BP_CPM_MSC0CDR_BUSY 28 | ||
346 | #define BM_CPM_MSC0CDR_BUSY 0x10000000 | ||
347 | #define BF_CPM_MSC0CDR_BUSY(v) (((v) & 0x1) << 28) | ||
348 | #define BFM_CPM_MSC0CDR_BUSY(v) BM_CPM_MSC0CDR_BUSY | ||
349 | #define BF_CPM_MSC0CDR_BUSY_V(e) BF_CPM_MSC0CDR_BUSY(BV_CPM_MSC0CDR_BUSY__##e) | ||
350 | #define BFM_CPM_MSC0CDR_BUSY_V(v) BM_CPM_MSC0CDR_BUSY | ||
351 | #define BP_CPM_MSC0CDR_STOP 27 | ||
352 | #define BM_CPM_MSC0CDR_STOP 0x8000000 | ||
353 | #define BF_CPM_MSC0CDR_STOP(v) (((v) & 0x1) << 27) | ||
354 | #define BFM_CPM_MSC0CDR_STOP(v) BM_CPM_MSC0CDR_STOP | ||
355 | #define BF_CPM_MSC0CDR_STOP_V(e) BF_CPM_MSC0CDR_STOP(BV_CPM_MSC0CDR_STOP__##e) | ||
356 | #define BFM_CPM_MSC0CDR_STOP_V(v) BM_CPM_MSC0CDR_STOP | ||
357 | #define BP_CPM_MSC0CDR_S_CLK0_SEL 15 | ||
358 | #define BM_CPM_MSC0CDR_S_CLK0_SEL 0x8000 | ||
359 | #define BV_CPM_MSC0CDR_S_CLK0_SEL__90DEG 0x0 | ||
360 | #define BV_CPM_MSC0CDR_S_CLK0_SEL__180DEG 0x1 | ||
361 | #define BF_CPM_MSC0CDR_S_CLK0_SEL(v) (((v) & 0x1) << 15) | ||
362 | #define BFM_CPM_MSC0CDR_S_CLK0_SEL(v) BM_CPM_MSC0CDR_S_CLK0_SEL | ||
363 | #define BF_CPM_MSC0CDR_S_CLK0_SEL_V(e) BF_CPM_MSC0CDR_S_CLK0_SEL(BV_CPM_MSC0CDR_S_CLK0_SEL__##e) | ||
364 | #define BFM_CPM_MSC0CDR_S_CLK0_SEL_V(v) BM_CPM_MSC0CDR_S_CLK0_SEL | ||
365 | |||
366 | #define REG_CPM_MSC1CDR jz_reg(CPM_MSC1CDR) | ||
367 | #define JA_CPM_MSC1CDR (0xb0000000 + 0xa4) | ||
368 | #define JT_CPM_MSC1CDR JIO_32_RW | ||
369 | #define JN_CPM_MSC1CDR CPM_MSC1CDR | ||
370 | #define JI_CPM_MSC1CDR | ||
371 | #define BP_CPM_MSC1CDR_CLKDIV 0 | ||
372 | #define BM_CPM_MSC1CDR_CLKDIV 0xff | ||
373 | #define BF_CPM_MSC1CDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
374 | #define BFM_CPM_MSC1CDR_CLKDIV(v) BM_CPM_MSC1CDR_CLKDIV | ||
375 | #define BF_CPM_MSC1CDR_CLKDIV_V(e) BF_CPM_MSC1CDR_CLKDIV(BV_CPM_MSC1CDR_CLKDIV__##e) | ||
376 | #define BFM_CPM_MSC1CDR_CLKDIV_V(v) BM_CPM_MSC1CDR_CLKDIV | ||
377 | #define BP_CPM_MSC1CDR_CE 29 | ||
378 | #define BM_CPM_MSC1CDR_CE 0x20000000 | ||
379 | #define BF_CPM_MSC1CDR_CE(v) (((v) & 0x1) << 29) | ||
380 | #define BFM_CPM_MSC1CDR_CE(v) BM_CPM_MSC1CDR_CE | ||
381 | #define BF_CPM_MSC1CDR_CE_V(e) BF_CPM_MSC1CDR_CE(BV_CPM_MSC1CDR_CE__##e) | ||
382 | #define BFM_CPM_MSC1CDR_CE_V(v) BM_CPM_MSC1CDR_CE | ||
383 | #define BP_CPM_MSC1CDR_BUSY 28 | ||
384 | #define BM_CPM_MSC1CDR_BUSY 0x10000000 | ||
385 | #define BF_CPM_MSC1CDR_BUSY(v) (((v) & 0x1) << 28) | ||
386 | #define BFM_CPM_MSC1CDR_BUSY(v) BM_CPM_MSC1CDR_BUSY | ||
387 | #define BF_CPM_MSC1CDR_BUSY_V(e) BF_CPM_MSC1CDR_BUSY(BV_CPM_MSC1CDR_BUSY__##e) | ||
388 | #define BFM_CPM_MSC1CDR_BUSY_V(v) BM_CPM_MSC1CDR_BUSY | ||
389 | #define BP_CPM_MSC1CDR_STOP 27 | ||
390 | #define BM_CPM_MSC1CDR_STOP 0x8000000 | ||
391 | #define BF_CPM_MSC1CDR_STOP(v) (((v) & 0x1) << 27) | ||
392 | #define BFM_CPM_MSC1CDR_STOP(v) BM_CPM_MSC1CDR_STOP | ||
393 | #define BF_CPM_MSC1CDR_STOP_V(e) BF_CPM_MSC1CDR_STOP(BV_CPM_MSC1CDR_STOP__##e) | ||
394 | #define BFM_CPM_MSC1CDR_STOP_V(v) BM_CPM_MSC1CDR_STOP | ||
395 | #define BP_CPM_MSC1CDR_S_CLK1_SEL 15 | ||
396 | #define BM_CPM_MSC1CDR_S_CLK1_SEL 0x8000 | ||
397 | #define BV_CPM_MSC1CDR_S_CLK1_SEL__90DEG 0x0 | ||
398 | #define BV_CPM_MSC1CDR_S_CLK1_SEL__180DEG 0x1 | ||
399 | #define BF_CPM_MSC1CDR_S_CLK1_SEL(v) (((v) & 0x1) << 15) | ||
400 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL(v) BM_CPM_MSC1CDR_S_CLK1_SEL | ||
401 | #define BF_CPM_MSC1CDR_S_CLK1_SEL_V(e) BF_CPM_MSC1CDR_S_CLK1_SEL(BV_CPM_MSC1CDR_S_CLK1_SEL__##e) | ||
402 | #define BFM_CPM_MSC1CDR_S_CLK1_SEL_V(v) BM_CPM_MSC1CDR_S_CLK1_SEL | ||
403 | |||
404 | #define REG_CPM_SSICDR jz_reg(CPM_SSICDR) | ||
405 | #define JA_CPM_SSICDR (0xb0000000 + 0x74) | ||
406 | #define JT_CPM_SSICDR JIO_32_RW | ||
407 | #define JN_CPM_SSICDR CPM_SSICDR | ||
408 | #define JI_CPM_SSICDR | ||
409 | #define BP_CPM_SSICDR_CLKDIV 0 | ||
410 | #define BM_CPM_SSICDR_CLKDIV 0xff | ||
411 | #define BF_CPM_SSICDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
412 | #define BFM_CPM_SSICDR_CLKDIV(v) BM_CPM_SSICDR_CLKDIV | ||
413 | #define BF_CPM_SSICDR_CLKDIV_V(e) BF_CPM_SSICDR_CLKDIV(BV_CPM_SSICDR_CLKDIV__##e) | ||
414 | #define BFM_CPM_SSICDR_CLKDIV_V(v) BM_CPM_SSICDR_CLKDIV | ||
415 | #define BP_CPM_SSICDR_SFC_CS 31 | ||
416 | #define BM_CPM_SSICDR_SFC_CS 0x80000000 | ||
417 | #define BV_CPM_SSICDR_SFC_CS__SCLK_A 0x0 | ||
418 | #define BV_CPM_SSICDR_SFC_CS__MPLL 0x1 | ||
419 | #define BF_CPM_SSICDR_SFC_CS(v) (((v) & 0x1) << 31) | ||
420 | #define BFM_CPM_SSICDR_SFC_CS(v) BM_CPM_SSICDR_SFC_CS | ||
421 | #define BF_CPM_SSICDR_SFC_CS_V(e) BF_CPM_SSICDR_SFC_CS(BV_CPM_SSICDR_SFC_CS__##e) | ||
422 | #define BFM_CPM_SSICDR_SFC_CS_V(v) BM_CPM_SSICDR_SFC_CS | ||
423 | #define BP_CPM_SSICDR_SSI_CS 30 | ||
424 | #define BM_CPM_SSICDR_SSI_CS 0x40000000 | ||
425 | #define BV_CPM_SSICDR_SSI_CS__EXCLK 0x0 | ||
426 | #define BV_CPM_SSICDR_SSI_CS__HALF_SFC 0x1 | ||
427 | #define BF_CPM_SSICDR_SSI_CS(v) (((v) & 0x1) << 30) | ||
428 | #define BFM_CPM_SSICDR_SSI_CS(v) BM_CPM_SSICDR_SSI_CS | ||
429 | #define BF_CPM_SSICDR_SSI_CS_V(e) BF_CPM_SSICDR_SSI_CS(BV_CPM_SSICDR_SSI_CS__##e) | ||
430 | #define BFM_CPM_SSICDR_SSI_CS_V(v) BM_CPM_SSICDR_SSI_CS | ||
431 | #define BP_CPM_SSICDR_CE 29 | ||
432 | #define BM_CPM_SSICDR_CE 0x20000000 | ||
433 | #define BF_CPM_SSICDR_CE(v) (((v) & 0x1) << 29) | ||
434 | #define BFM_CPM_SSICDR_CE(v) BM_CPM_SSICDR_CE | ||
435 | #define BF_CPM_SSICDR_CE_V(e) BF_CPM_SSICDR_CE(BV_CPM_SSICDR_CE__##e) | ||
436 | #define BFM_CPM_SSICDR_CE_V(v) BM_CPM_SSICDR_CE | ||
437 | #define BP_CPM_SSICDR_BUSY 28 | ||
438 | #define BM_CPM_SSICDR_BUSY 0x10000000 | ||
439 | #define BF_CPM_SSICDR_BUSY(v) (((v) & 0x1) << 28) | ||
440 | #define BFM_CPM_SSICDR_BUSY(v) BM_CPM_SSICDR_BUSY | ||
441 | #define BF_CPM_SSICDR_BUSY_V(e) BF_CPM_SSICDR_BUSY(BV_CPM_SSICDR_BUSY__##e) | ||
442 | #define BFM_CPM_SSICDR_BUSY_V(v) BM_CPM_SSICDR_BUSY | ||
443 | #define BP_CPM_SSICDR_STOP 27 | ||
444 | #define BM_CPM_SSICDR_STOP 0x8000000 | ||
445 | #define BF_CPM_SSICDR_STOP(v) (((v) & 0x1) << 27) | ||
446 | #define BFM_CPM_SSICDR_STOP(v) BM_CPM_SSICDR_STOP | ||
447 | #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) | ||
448 | #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP | ||
449 | |||
450 | #define REG_CPM_DRCG jz_reg(CPM_DRCG) | ||
451 | #define JA_CPM_DRCG (0xb0000000 + 0xd0) | ||
452 | #define JT_CPM_DRCG JIO_32_RW | ||
453 | #define JN_CPM_DRCG CPM_DRCG | ||
454 | #define JI_CPM_DRCG | ||
455 | |||
456 | #define REG_CPM_APCR jz_reg(CPM_APCR) | ||
457 | #define JA_CPM_APCR (0xb0000000 + 0x10) | ||
458 | #define JT_CPM_APCR JIO_32_RW | ||
459 | #define JN_CPM_APCR CPM_APCR | ||
460 | #define JI_CPM_APCR | ||
461 | #define BP_CPM_APCR_PLLM 24 | ||
462 | #define BM_CPM_APCR_PLLM 0x7f000000 | ||
463 | #define BF_CPM_APCR_PLLM(v) (((v) & 0x7f) << 24) | ||
464 | #define BFM_CPM_APCR_PLLM(v) BM_CPM_APCR_PLLM | ||
465 | #define BF_CPM_APCR_PLLM_V(e) BF_CPM_APCR_PLLM(BV_CPM_APCR_PLLM__##e) | ||
466 | #define BFM_CPM_APCR_PLLM_V(v) BM_CPM_APCR_PLLM | ||
467 | #define BP_CPM_APCR_PLLN 18 | ||
468 | #define BM_CPM_APCR_PLLN 0x7c0000 | ||
469 | #define BF_CPM_APCR_PLLN(v) (((v) & 0x1f) << 18) | ||
470 | #define BFM_CPM_APCR_PLLN(v) BM_CPM_APCR_PLLN | ||
471 | #define BF_CPM_APCR_PLLN_V(e) BF_CPM_APCR_PLLN(BV_CPM_APCR_PLLN__##e) | ||
472 | #define BFM_CPM_APCR_PLLN_V(v) BM_CPM_APCR_PLLN | ||
473 | #define BP_CPM_APCR_PLLOD 16 | ||
474 | #define BM_CPM_APCR_PLLOD 0x30000 | ||
475 | #define BF_CPM_APCR_PLLOD(v) (((v) & 0x3) << 16) | ||
476 | #define BFM_CPM_APCR_PLLOD(v) BM_CPM_APCR_PLLOD | ||
477 | #define BF_CPM_APCR_PLLOD_V(e) BF_CPM_APCR_PLLOD(BV_CPM_APCR_PLLOD__##e) | ||
478 | #define BFM_CPM_APCR_PLLOD_V(v) BM_CPM_APCR_PLLOD | ||
479 | #define BP_CPM_APCR_PLLST 0 | ||
480 | #define BM_CPM_APCR_PLLST 0xff | ||
481 | #define BF_CPM_APCR_PLLST(v) (((v) & 0xff) << 0) | ||
482 | #define BFM_CPM_APCR_PLLST(v) BM_CPM_APCR_PLLST | ||
483 | #define BF_CPM_APCR_PLLST_V(e) BF_CPM_APCR_PLLST(BV_CPM_APCR_PLLST__##e) | ||
484 | #define BFM_CPM_APCR_PLLST_V(v) BM_CPM_APCR_PLLST | ||
485 | #define BP_CPM_APCR_BS 31 | ||
486 | #define BM_CPM_APCR_BS 0x80000000 | ||
487 | #define BF_CPM_APCR_BS(v) (((v) & 0x1) << 31) | ||
488 | #define BFM_CPM_APCR_BS(v) BM_CPM_APCR_BS | ||
489 | #define BF_CPM_APCR_BS_V(e) BF_CPM_APCR_BS(BV_CPM_APCR_BS__##e) | ||
490 | #define BFM_CPM_APCR_BS_V(v) BM_CPM_APCR_BS | ||
491 | #define BP_CPM_APCR_LOCK 15 | ||
492 | #define BM_CPM_APCR_LOCK 0x8000 | ||
493 | #define BF_CPM_APCR_LOCK(v) (((v) & 0x1) << 15) | ||
494 | #define BFM_CPM_APCR_LOCK(v) BM_CPM_APCR_LOCK | ||
495 | #define BF_CPM_APCR_LOCK_V(e) BF_CPM_APCR_LOCK(BV_CPM_APCR_LOCK__##e) | ||
496 | #define BFM_CPM_APCR_LOCK_V(v) BM_CPM_APCR_LOCK | ||
497 | #define BP_CPM_APCR_ON 10 | ||
498 | #define BM_CPM_APCR_ON 0x400 | ||
499 | #define BF_CPM_APCR_ON(v) (((v) & 0x1) << 10) | ||
500 | #define BFM_CPM_APCR_ON(v) BM_CPM_APCR_ON | ||
501 | #define BF_CPM_APCR_ON_V(e) BF_CPM_APCR_ON(BV_CPM_APCR_ON__##e) | ||
502 | #define BFM_CPM_APCR_ON_V(v) BM_CPM_APCR_ON | ||
503 | #define BP_CPM_APCR_BYPASS 9 | ||
504 | #define BM_CPM_APCR_BYPASS 0x200 | ||
505 | #define BF_CPM_APCR_BYPASS(v) (((v) & 0x1) << 9) | ||
506 | #define BFM_CPM_APCR_BYPASS(v) BM_CPM_APCR_BYPASS | ||
507 | #define BF_CPM_APCR_BYPASS_V(e) BF_CPM_APCR_BYPASS(BV_CPM_APCR_BYPASS__##e) | ||
508 | #define BFM_CPM_APCR_BYPASS_V(v) BM_CPM_APCR_BYPASS | ||
509 | #define BP_CPM_APCR_ENABLE 8 | ||
510 | #define BM_CPM_APCR_ENABLE 0x100 | ||
511 | #define BF_CPM_APCR_ENABLE(v) (((v) & 0x1) << 8) | ||
512 | #define BFM_CPM_APCR_ENABLE(v) BM_CPM_APCR_ENABLE | ||
513 | #define BF_CPM_APCR_ENABLE_V(e) BF_CPM_APCR_ENABLE(BV_CPM_APCR_ENABLE__##e) | ||
514 | #define BFM_CPM_APCR_ENABLE_V(v) BM_CPM_APCR_ENABLE | ||
515 | |||
516 | #define REG_CPM_MPCR jz_reg(CPM_MPCR) | ||
517 | #define JA_CPM_MPCR (0xb0000000 + 0x14) | ||
518 | #define JT_CPM_MPCR JIO_32_RW | ||
519 | #define JN_CPM_MPCR CPM_MPCR | ||
520 | #define JI_CPM_MPCR | ||
521 | #define BP_CPM_MPCR_PLLM 24 | ||
522 | #define BM_CPM_MPCR_PLLM 0x7f000000 | ||
523 | #define BF_CPM_MPCR_PLLM(v) (((v) & 0x7f) << 24) | ||
524 | #define BFM_CPM_MPCR_PLLM(v) BM_CPM_MPCR_PLLM | ||
525 | #define BF_CPM_MPCR_PLLM_V(e) BF_CPM_MPCR_PLLM(BV_CPM_MPCR_PLLM__##e) | ||
526 | #define BFM_CPM_MPCR_PLLM_V(v) BM_CPM_MPCR_PLLM | ||
527 | #define BP_CPM_MPCR_PLLN 18 | ||
528 | #define BM_CPM_MPCR_PLLN 0x7c0000 | ||
529 | #define BF_CPM_MPCR_PLLN(v) (((v) & 0x1f) << 18) | ||
530 | #define BFM_CPM_MPCR_PLLN(v) BM_CPM_MPCR_PLLN | ||
531 | #define BF_CPM_MPCR_PLLN_V(e) BF_CPM_MPCR_PLLN(BV_CPM_MPCR_PLLN__##e) | ||
532 | #define BFM_CPM_MPCR_PLLN_V(v) BM_CPM_MPCR_PLLN | ||
533 | #define BP_CPM_MPCR_PLLOD 16 | ||
534 | #define BM_CPM_MPCR_PLLOD 0x30000 | ||
535 | #define BF_CPM_MPCR_PLLOD(v) (((v) & 0x3) << 16) | ||
536 | #define BFM_CPM_MPCR_PLLOD(v) BM_CPM_MPCR_PLLOD | ||
537 | #define BF_CPM_MPCR_PLLOD_V(e) BF_CPM_MPCR_PLLOD(BV_CPM_MPCR_PLLOD__##e) | ||
538 | #define BFM_CPM_MPCR_PLLOD_V(v) BM_CPM_MPCR_PLLOD | ||
539 | #define BP_CPM_MPCR_BS 31 | ||
540 | #define BM_CPM_MPCR_BS 0x80000000 | ||
541 | #define BF_CPM_MPCR_BS(v) (((v) & 0x1) << 31) | ||
542 | #define BFM_CPM_MPCR_BS(v) BM_CPM_MPCR_BS | ||
543 | #define BF_CPM_MPCR_BS_V(e) BF_CPM_MPCR_BS(BV_CPM_MPCR_BS__##e) | ||
544 | #define BFM_CPM_MPCR_BS_V(v) BM_CPM_MPCR_BS | ||
545 | #define BP_CPM_MPCR_ENABLE 7 | ||
546 | #define BM_CPM_MPCR_ENABLE 0x80 | ||
547 | #define BF_CPM_MPCR_ENABLE(v) (((v) & 0x1) << 7) | ||
548 | #define BFM_CPM_MPCR_ENABLE(v) BM_CPM_MPCR_ENABLE | ||
549 | #define BF_CPM_MPCR_ENABLE_V(e) BF_CPM_MPCR_ENABLE(BV_CPM_MPCR_ENABLE__##e) | ||
550 | #define BFM_CPM_MPCR_ENABLE_V(v) BM_CPM_MPCR_ENABLE | ||
551 | #define BP_CPM_MPCR_BYPASS 6 | ||
552 | #define BM_CPM_MPCR_BYPASS 0x40 | ||
553 | #define BF_CPM_MPCR_BYPASS(v) (((v) & 0x1) << 6) | ||
554 | #define BFM_CPM_MPCR_BYPASS(v) BM_CPM_MPCR_BYPASS | ||
555 | #define BF_CPM_MPCR_BYPASS_V(e) BF_CPM_MPCR_BYPASS(BV_CPM_MPCR_BYPASS__##e) | ||
556 | #define BFM_CPM_MPCR_BYPASS_V(v) BM_CPM_MPCR_BYPASS | ||
557 | #define BP_CPM_MPCR_LOCK 1 | ||
558 | #define BM_CPM_MPCR_LOCK 0x2 | ||
559 | #define BF_CPM_MPCR_LOCK(v) (((v) & 0x1) << 1) | ||
560 | #define BFM_CPM_MPCR_LOCK(v) BM_CPM_MPCR_LOCK | ||
561 | #define BF_CPM_MPCR_LOCK_V(e) BF_CPM_MPCR_LOCK(BV_CPM_MPCR_LOCK__##e) | ||
562 | #define BFM_CPM_MPCR_LOCK_V(v) BM_CPM_MPCR_LOCK | ||
563 | #define BP_CPM_MPCR_ON 0 | ||
564 | #define BM_CPM_MPCR_ON 0x1 | ||
565 | #define BF_CPM_MPCR_ON(v) (((v) & 0x1) << 0) | ||
566 | #define BFM_CPM_MPCR_ON(v) BM_CPM_MPCR_ON | ||
567 | #define BF_CPM_MPCR_ON_V(e) BF_CPM_MPCR_ON(BV_CPM_MPCR_ON__##e) | ||
568 | #define BFM_CPM_MPCR_ON_V(v) BM_CPM_MPCR_ON | ||
569 | |||
570 | #define REG_CPM_LCR jz_reg(CPM_LCR) | ||
571 | #define JA_CPM_LCR (0xb0000000 + 0x4) | ||
572 | #define JT_CPM_LCR JIO_32_RW | ||
573 | #define JN_CPM_LCR CPM_LCR | ||
574 | #define JI_CPM_LCR | ||
575 | #define BP_CPM_LCR_PST 8 | ||
576 | #define BM_CPM_LCR_PST 0xfff00 | ||
577 | #define BF_CPM_LCR_PST(v) (((v) & 0xfff) << 8) | ||
578 | #define BFM_CPM_LCR_PST(v) BM_CPM_LCR_PST | ||
579 | #define BF_CPM_LCR_PST_V(e) BF_CPM_LCR_PST(BV_CPM_LCR_PST__##e) | ||
580 | #define BFM_CPM_LCR_PST_V(v) BM_CPM_LCR_PST | ||
581 | #define BP_CPM_LCR_LPM 0 | ||
582 | #define BM_CPM_LCR_LPM 0x3 | ||
583 | #define BV_CPM_LCR_LPM__IDLE 0x0 | ||
584 | #define BV_CPM_LCR_LPM__SLEEP 0x1 | ||
585 | #define BF_CPM_LCR_LPM(v) (((v) & 0x3) << 0) | ||
586 | #define BFM_CPM_LCR_LPM(v) BM_CPM_LCR_LPM | ||
587 | #define BF_CPM_LCR_LPM_V(e) BF_CPM_LCR_LPM(BV_CPM_LCR_LPM__##e) | ||
588 | #define BFM_CPM_LCR_LPM_V(v) BM_CPM_LCR_LPM | ||
589 | |||
590 | #define REG_CPM_PSWC0ST jz_reg(CPM_PSWC0ST) | ||
591 | #define JA_CPM_PSWC0ST (0xb0000000 + 0x90) | ||
592 | #define JT_CPM_PSWC0ST JIO_32_RW | ||
593 | #define JN_CPM_PSWC0ST CPM_PSWC0ST | ||
594 | #define JI_CPM_PSWC0ST | ||
595 | |||
596 | #define REG_CPM_PSWC1ST jz_reg(CPM_PSWC1ST) | ||
597 | #define JA_CPM_PSWC1ST (0xb0000000 + 0x94) | ||
598 | #define JT_CPM_PSWC1ST JIO_32_RW | ||
599 | #define JN_CPM_PSWC1ST CPM_PSWC1ST | ||
600 | #define JI_CPM_PSWC1ST | ||
601 | |||
602 | #define REG_CPM_PSWC2ST jz_reg(CPM_PSWC2ST) | ||
603 | #define JA_CPM_PSWC2ST (0xb0000000 + 0x98) | ||
604 | #define JT_CPM_PSWC2ST JIO_32_RW | ||
605 | #define JN_CPM_PSWC2ST CPM_PSWC2ST | ||
606 | #define JI_CPM_PSWC2ST | ||
607 | |||
608 | #define REG_CPM_PSWC3ST jz_reg(CPM_PSWC3ST) | ||
609 | #define JA_CPM_PSWC3ST (0xb0000000 + 0x9c) | ||
610 | #define JT_CPM_PSWC3ST JIO_32_RW | ||
611 | #define JN_CPM_PSWC3ST CPM_PSWC3ST | ||
612 | #define JI_CPM_PSWC3ST | ||
613 | |||
614 | #define REG_CPM_CLKGR jz_reg(CPM_CLKGR) | ||
615 | #define JA_CPM_CLKGR (0xb0000000 + 0x20) | ||
616 | #define JT_CPM_CLKGR JIO_32_RW | ||
617 | #define JN_CPM_CLKGR CPM_CLKGR | ||
618 | #define JI_CPM_CLKGR | ||
619 | #define BP_CPM_CLKGR_DDR 31 | ||
620 | #define BM_CPM_CLKGR_DDR 0x80000000 | ||
621 | #define BF_CPM_CLKGR_DDR(v) (((v) & 0x1) << 31) | ||
622 | #define BFM_CPM_CLKGR_DDR(v) BM_CPM_CLKGR_DDR | ||
623 | #define BF_CPM_CLKGR_DDR_V(e) BF_CPM_CLKGR_DDR(BV_CPM_CLKGR_DDR__##e) | ||
624 | #define BFM_CPM_CLKGR_DDR_V(v) BM_CPM_CLKGR_DDR | ||
625 | #define BP_CPM_CLKGR_CPU_BIT 30 | ||
626 | #define BM_CPM_CLKGR_CPU_BIT 0x40000000 | ||
627 | #define BF_CPM_CLKGR_CPU_BIT(v) (((v) & 0x1) << 30) | ||
628 | #define BFM_CPM_CLKGR_CPU_BIT(v) BM_CPM_CLKGR_CPU_BIT | ||
629 | #define BF_CPM_CLKGR_CPU_BIT_V(e) BF_CPM_CLKGR_CPU_BIT(BV_CPM_CLKGR_CPU_BIT__##e) | ||
630 | #define BFM_CPM_CLKGR_CPU_BIT_V(v) BM_CPM_CLKGR_CPU_BIT | ||
631 | #define BP_CPM_CLKGR_AHB0 29 | ||
632 | #define BM_CPM_CLKGR_AHB0 0x20000000 | ||
633 | #define BF_CPM_CLKGR_AHB0(v) (((v) & 0x1) << 29) | ||
634 | #define BFM_CPM_CLKGR_AHB0(v) BM_CPM_CLKGR_AHB0 | ||
635 | #define BF_CPM_CLKGR_AHB0_V(e) BF_CPM_CLKGR_AHB0(BV_CPM_CLKGR_AHB0__##e) | ||
636 | #define BFM_CPM_CLKGR_AHB0_V(v) BM_CPM_CLKGR_AHB0 | ||
637 | #define BP_CPM_CLKGR_APB0 28 | ||
638 | #define BM_CPM_CLKGR_APB0 0x10000000 | ||
639 | #define BF_CPM_CLKGR_APB0(v) (((v) & 0x1) << 28) | ||
640 | #define BFM_CPM_CLKGR_APB0(v) BM_CPM_CLKGR_APB0 | ||
641 | #define BF_CPM_CLKGR_APB0_V(e) BF_CPM_CLKGR_APB0(BV_CPM_CLKGR_APB0__##e) | ||
642 | #define BFM_CPM_CLKGR_APB0_V(v) BM_CPM_CLKGR_APB0 | ||
643 | #define BP_CPM_CLKGR_RTC 27 | ||
644 | #define BM_CPM_CLKGR_RTC 0x8000000 | ||
645 | #define BF_CPM_CLKGR_RTC(v) (((v) & 0x1) << 27) | ||
646 | #define BFM_CPM_CLKGR_RTC(v) BM_CPM_CLKGR_RTC | ||
647 | #define BF_CPM_CLKGR_RTC_V(e) BF_CPM_CLKGR_RTC(BV_CPM_CLKGR_RTC__##e) | ||
648 | #define BFM_CPM_CLKGR_RTC_V(v) BM_CPM_CLKGR_RTC | ||
649 | #define BP_CPM_CLKGR_PCM 26 | ||
650 | #define BM_CPM_CLKGR_PCM 0x4000000 | ||
651 | #define BF_CPM_CLKGR_PCM(v) (((v) & 0x1) << 26) | ||
652 | #define BFM_CPM_CLKGR_PCM(v) BM_CPM_CLKGR_PCM | ||
653 | #define BF_CPM_CLKGR_PCM_V(e) BF_CPM_CLKGR_PCM(BV_CPM_CLKGR_PCM__##e) | ||
654 | #define BFM_CPM_CLKGR_PCM_V(v) BM_CPM_CLKGR_PCM | ||
655 | #define BP_CPM_CLKGR_MAC 25 | ||
656 | #define BM_CPM_CLKGR_MAC 0x2000000 | ||
657 | #define BF_CPM_CLKGR_MAC(v) (((v) & 0x1) << 25) | ||
658 | #define BFM_CPM_CLKGR_MAC(v) BM_CPM_CLKGR_MAC | ||
659 | #define BF_CPM_CLKGR_MAC_V(e) BF_CPM_CLKGR_MAC(BV_CPM_CLKGR_MAC__##e) | ||
660 | #define BFM_CPM_CLKGR_MAC_V(v) BM_CPM_CLKGR_MAC | ||
661 | #define BP_CPM_CLKGR_AES 24 | ||
662 | #define BM_CPM_CLKGR_AES 0x1000000 | ||
663 | #define BF_CPM_CLKGR_AES(v) (((v) & 0x1) << 24) | ||
664 | #define BFM_CPM_CLKGR_AES(v) BM_CPM_CLKGR_AES | ||
665 | #define BF_CPM_CLKGR_AES_V(e) BF_CPM_CLKGR_AES(BV_CPM_CLKGR_AES__##e) | ||
666 | #define BFM_CPM_CLKGR_AES_V(v) BM_CPM_CLKGR_AES | ||
667 | #define BP_CPM_CLKGR_LCD 23 | ||
668 | #define BM_CPM_CLKGR_LCD 0x800000 | ||
669 | #define BF_CPM_CLKGR_LCD(v) (((v) & 0x1) << 23) | ||
670 | #define BFM_CPM_CLKGR_LCD(v) BM_CPM_CLKGR_LCD | ||
671 | #define BF_CPM_CLKGR_LCD_V(e) BF_CPM_CLKGR_LCD(BV_CPM_CLKGR_LCD__##e) | ||
672 | #define BFM_CPM_CLKGR_LCD_V(v) BM_CPM_CLKGR_LCD | ||
673 | #define BP_CPM_CLKGR_CIM 22 | ||
674 | #define BM_CPM_CLKGR_CIM 0x400000 | ||
675 | #define BF_CPM_CLKGR_CIM(v) (((v) & 0x1) << 22) | ||
676 | #define BFM_CPM_CLKGR_CIM(v) BM_CPM_CLKGR_CIM | ||
677 | #define BF_CPM_CLKGR_CIM_V(e) BF_CPM_CLKGR_CIM(BV_CPM_CLKGR_CIM__##e) | ||
678 | #define BFM_CPM_CLKGR_CIM_V(v) BM_CPM_CLKGR_CIM | ||
679 | #define BP_CPM_CLKGR_PDMA 21 | ||
680 | #define BM_CPM_CLKGR_PDMA 0x200000 | ||
681 | #define BF_CPM_CLKGR_PDMA(v) (((v) & 0x1) << 21) | ||
682 | #define BFM_CPM_CLKGR_PDMA(v) BM_CPM_CLKGR_PDMA | ||
683 | #define BF_CPM_CLKGR_PDMA_V(e) BF_CPM_CLKGR_PDMA(BV_CPM_CLKGR_PDMA__##e) | ||
684 | #define BFM_CPM_CLKGR_PDMA_V(v) BM_CPM_CLKGR_PDMA | ||
685 | #define BP_CPM_CLKGR_OST 20 | ||
686 | #define BM_CPM_CLKGR_OST 0x100000 | ||
687 | #define BF_CPM_CLKGR_OST(v) (((v) & 0x1) << 20) | ||
688 | #define BFM_CPM_CLKGR_OST(v) BM_CPM_CLKGR_OST | ||
689 | #define BF_CPM_CLKGR_OST_V(e) BF_CPM_CLKGR_OST(BV_CPM_CLKGR_OST__##e) | ||
690 | #define BFM_CPM_CLKGR_OST_V(v) BM_CPM_CLKGR_OST | ||
691 | #define BP_CPM_CLKGR_SSI 19 | ||
692 | #define BM_CPM_CLKGR_SSI 0x80000 | ||
693 | #define BF_CPM_CLKGR_SSI(v) (((v) & 0x1) << 19) | ||
694 | #define BFM_CPM_CLKGR_SSI(v) BM_CPM_CLKGR_SSI | ||
695 | #define BF_CPM_CLKGR_SSI_V(e) BF_CPM_CLKGR_SSI(BV_CPM_CLKGR_SSI__##e) | ||
696 | #define BFM_CPM_CLKGR_SSI_V(v) BM_CPM_CLKGR_SSI | ||
697 | #define BP_CPM_CLKGR_TCU 18 | ||
698 | #define BM_CPM_CLKGR_TCU 0x40000 | ||
699 | #define BF_CPM_CLKGR_TCU(v) (((v) & 0x1) << 18) | ||
700 | #define BFM_CPM_CLKGR_TCU(v) BM_CPM_CLKGR_TCU | ||
701 | #define BF_CPM_CLKGR_TCU_V(e) BF_CPM_CLKGR_TCU(BV_CPM_CLKGR_TCU__##e) | ||
702 | #define BFM_CPM_CLKGR_TCU_V(v) BM_CPM_CLKGR_TCU | ||
703 | #define BP_CPM_CLKGR_DMIC 17 | ||
704 | #define BM_CPM_CLKGR_DMIC 0x20000 | ||
705 | #define BF_CPM_CLKGR_DMIC(v) (((v) & 0x1) << 17) | ||
706 | #define BFM_CPM_CLKGR_DMIC(v) BM_CPM_CLKGR_DMIC | ||
707 | #define BF_CPM_CLKGR_DMIC_V(e) BF_CPM_CLKGR_DMIC(BV_CPM_CLKGR_DMIC__##e) | ||
708 | #define BFM_CPM_CLKGR_DMIC_V(v) BM_CPM_CLKGR_DMIC | ||
709 | #define BP_CPM_CLKGR_UART2 16 | ||
710 | #define BM_CPM_CLKGR_UART2 0x10000 | ||
711 | #define BF_CPM_CLKGR_UART2(v) (((v) & 0x1) << 16) | ||
712 | #define BFM_CPM_CLKGR_UART2(v) BM_CPM_CLKGR_UART2 | ||
713 | #define BF_CPM_CLKGR_UART2_V(e) BF_CPM_CLKGR_UART2(BV_CPM_CLKGR_UART2__##e) | ||
714 | #define BFM_CPM_CLKGR_UART2_V(v) BM_CPM_CLKGR_UART2 | ||
715 | #define BP_CPM_CLKGR_UART1 15 | ||
716 | #define BM_CPM_CLKGR_UART1 0x8000 | ||
717 | #define BF_CPM_CLKGR_UART1(v) (((v) & 0x1) << 15) | ||
718 | #define BFM_CPM_CLKGR_UART1(v) BM_CPM_CLKGR_UART1 | ||
719 | #define BF_CPM_CLKGR_UART1_V(e) BF_CPM_CLKGR_UART1(BV_CPM_CLKGR_UART1__##e) | ||
720 | #define BFM_CPM_CLKGR_UART1_V(v) BM_CPM_CLKGR_UART1 | ||
721 | #define BP_CPM_CLKGR_UART0 14 | ||
722 | #define BM_CPM_CLKGR_UART0 0x4000 | ||
723 | #define BF_CPM_CLKGR_UART0(v) (((v) & 0x1) << 14) | ||
724 | #define BFM_CPM_CLKGR_UART0(v) BM_CPM_CLKGR_UART0 | ||
725 | #define BF_CPM_CLKGR_UART0_V(e) BF_CPM_CLKGR_UART0(BV_CPM_CLKGR_UART0__##e) | ||
726 | #define BFM_CPM_CLKGR_UART0_V(v) BM_CPM_CLKGR_UART0 | ||
727 | #define BP_CPM_CLKGR_JPEG 12 | ||
728 | #define BM_CPM_CLKGR_JPEG 0x1000 | ||
729 | #define BF_CPM_CLKGR_JPEG(v) (((v) & 0x1) << 12) | ||
730 | #define BFM_CPM_CLKGR_JPEG(v) BM_CPM_CLKGR_JPEG | ||
731 | #define BF_CPM_CLKGR_JPEG_V(e) BF_CPM_CLKGR_JPEG(BV_CPM_CLKGR_JPEG__##e) | ||
732 | #define BFM_CPM_CLKGR_JPEG_V(v) BM_CPM_CLKGR_JPEG | ||
733 | #define BP_CPM_CLKGR_AIC 11 | ||
734 | #define BM_CPM_CLKGR_AIC 0x800 | ||
735 | #define BF_CPM_CLKGR_AIC(v) (((v) & 0x1) << 11) | ||
736 | #define BFM_CPM_CLKGR_AIC(v) BM_CPM_CLKGR_AIC | ||
737 | #define BF_CPM_CLKGR_AIC_V(e) BF_CPM_CLKGR_AIC(BV_CPM_CLKGR_AIC__##e) | ||
738 | #define BFM_CPM_CLKGR_AIC_V(v) BM_CPM_CLKGR_AIC | ||
739 | #define BP_CPM_CLKGR_I2C2 9 | ||
740 | #define BM_CPM_CLKGR_I2C2 0x200 | ||
741 | #define BF_CPM_CLKGR_I2C2(v) (((v) & 0x1) << 9) | ||
742 | #define BFM_CPM_CLKGR_I2C2(v) BM_CPM_CLKGR_I2C2 | ||
743 | #define BF_CPM_CLKGR_I2C2_V(e) BF_CPM_CLKGR_I2C2(BV_CPM_CLKGR_I2C2__##e) | ||
744 | #define BFM_CPM_CLKGR_I2C2_V(v) BM_CPM_CLKGR_I2C2 | ||
745 | #define BP_CPM_CLKGR_I2C1 8 | ||
746 | #define BM_CPM_CLKGR_I2C1 0x100 | ||
747 | #define BF_CPM_CLKGR_I2C1(v) (((v) & 0x1) << 8) | ||
748 | #define BFM_CPM_CLKGR_I2C1(v) BM_CPM_CLKGR_I2C1 | ||
749 | #define BF_CPM_CLKGR_I2C1_V(e) BF_CPM_CLKGR_I2C1(BV_CPM_CLKGR_I2C1__##e) | ||
750 | #define BFM_CPM_CLKGR_I2C1_V(v) BM_CPM_CLKGR_I2C1 | ||
751 | #define BP_CPM_CLKGR_I2C0 7 | ||
752 | #define BM_CPM_CLKGR_I2C0 0x80 | ||
753 | #define BF_CPM_CLKGR_I2C0(v) (((v) & 0x1) << 7) | ||
754 | #define BFM_CPM_CLKGR_I2C0(v) BM_CPM_CLKGR_I2C0 | ||
755 | #define BF_CPM_CLKGR_I2C0_V(e) BF_CPM_CLKGR_I2C0(BV_CPM_CLKGR_I2C0__##e) | ||
756 | #define BFM_CPM_CLKGR_I2C0_V(v) BM_CPM_CLKGR_I2C0 | ||
757 | #define BP_CPM_CLKGR_SCC 6 | ||
758 | #define BM_CPM_CLKGR_SCC 0x40 | ||
759 | #define BF_CPM_CLKGR_SCC(v) (((v) & 0x1) << 6) | ||
760 | #define BFM_CPM_CLKGR_SCC(v) BM_CPM_CLKGR_SCC | ||
761 | #define BF_CPM_CLKGR_SCC_V(e) BF_CPM_CLKGR_SCC(BV_CPM_CLKGR_SCC__##e) | ||
762 | #define BFM_CPM_CLKGR_SCC_V(v) BM_CPM_CLKGR_SCC | ||
763 | #define BP_CPM_CLKGR_MSC1 5 | ||
764 | #define BM_CPM_CLKGR_MSC1 0x20 | ||
765 | #define BF_CPM_CLKGR_MSC1(v) (((v) & 0x1) << 5) | ||
766 | #define BFM_CPM_CLKGR_MSC1(v) BM_CPM_CLKGR_MSC1 | ||
767 | #define BF_CPM_CLKGR_MSC1_V(e) BF_CPM_CLKGR_MSC1(BV_CPM_CLKGR_MSC1__##e) | ||
768 | #define BFM_CPM_CLKGR_MSC1_V(v) BM_CPM_CLKGR_MSC1 | ||
769 | #define BP_CPM_CLKGR_MSC0 4 | ||
770 | #define BM_CPM_CLKGR_MSC0 0x10 | ||
771 | #define BF_CPM_CLKGR_MSC0(v) (((v) & 0x1) << 4) | ||
772 | #define BFM_CPM_CLKGR_MSC0(v) BM_CPM_CLKGR_MSC0 | ||
773 | #define BF_CPM_CLKGR_MSC0_V(e) BF_CPM_CLKGR_MSC0(BV_CPM_CLKGR_MSC0__##e) | ||
774 | #define BFM_CPM_CLKGR_MSC0_V(v) BM_CPM_CLKGR_MSC0 | ||
775 | #define BP_CPM_CLKGR_OTG 3 | ||
776 | #define BM_CPM_CLKGR_OTG 0x8 | ||
777 | #define BF_CPM_CLKGR_OTG(v) (((v) & 0x1) << 3) | ||
778 | #define BFM_CPM_CLKGR_OTG(v) BM_CPM_CLKGR_OTG | ||
779 | #define BF_CPM_CLKGR_OTG_V(e) BF_CPM_CLKGR_OTG(BV_CPM_CLKGR_OTG__##e) | ||
780 | #define BFM_CPM_CLKGR_OTG_V(v) BM_CPM_CLKGR_OTG | ||
781 | #define BP_CPM_CLKGR_SFC 2 | ||
782 | #define BM_CPM_CLKGR_SFC 0x4 | ||
783 | #define BF_CPM_CLKGR_SFC(v) (((v) & 0x1) << 2) | ||
784 | #define BFM_CPM_CLKGR_SFC(v) BM_CPM_CLKGR_SFC | ||
785 | #define BF_CPM_CLKGR_SFC_V(e) BF_CPM_CLKGR_SFC(BV_CPM_CLKGR_SFC__##e) | ||
786 | #define BFM_CPM_CLKGR_SFC_V(v) BM_CPM_CLKGR_SFC | ||
787 | #define BP_CPM_CLKGR_EFUSE 1 | ||
788 | #define BM_CPM_CLKGR_EFUSE 0x2 | ||
789 | #define BF_CPM_CLKGR_EFUSE(v) (((v) & 0x1) << 1) | ||
790 | #define BFM_CPM_CLKGR_EFUSE(v) BM_CPM_CLKGR_EFUSE | ||
791 | #define BF_CPM_CLKGR_EFUSE_V(e) BF_CPM_CLKGR_EFUSE(BV_CPM_CLKGR_EFUSE__##e) | ||
792 | #define BFM_CPM_CLKGR_EFUSE_V(v) BM_CPM_CLKGR_EFUSE | ||
793 | |||
794 | #define REG_CPM_OPCR jz_reg(CPM_OPCR) | ||
795 | #define JA_CPM_OPCR (0xb0000000 + 0x24) | ||
796 | #define JT_CPM_OPCR JIO_32_RW | ||
797 | #define JN_CPM_OPCR CPM_OPCR | ||
798 | #define JI_CPM_OPCR | ||
799 | #define BP_CPM_OPCR_O1ST 8 | ||
800 | #define BM_CPM_OPCR_O1ST 0xfff00 | ||
801 | #define BF_CPM_OPCR_O1ST(v) (((v) & 0xfff) << 8) | ||
802 | #define BFM_CPM_OPCR_O1ST(v) BM_CPM_OPCR_O1ST | ||
803 | #define BF_CPM_OPCR_O1ST_V(e) BF_CPM_OPCR_O1ST(BV_CPM_OPCR_O1ST__##e) | ||
804 | #define BFM_CPM_OPCR_O1ST_V(v) BM_CPM_OPCR_O1ST | ||
805 | #define BP_CPM_OPCR_IDLE_DIS 31 | ||
806 | #define BM_CPM_OPCR_IDLE_DIS 0x80000000 | ||
807 | #define BF_CPM_OPCR_IDLE_DIS(v) (((v) & 0x1) << 31) | ||
808 | #define BFM_CPM_OPCR_IDLE_DIS(v) BM_CPM_OPCR_IDLE_DIS | ||
809 | #define BF_CPM_OPCR_IDLE_DIS_V(e) BF_CPM_OPCR_IDLE_DIS(BV_CPM_OPCR_IDLE_DIS__##e) | ||
810 | #define BFM_CPM_OPCR_IDLE_DIS_V(v) BM_CPM_OPCR_IDLE_DIS | ||
811 | #define BP_CPM_OPCR_MASK_INT 30 | ||
812 | #define BM_CPM_OPCR_MASK_INT 0x40000000 | ||
813 | #define BF_CPM_OPCR_MASK_INT(v) (((v) & 0x1) << 30) | ||
814 | #define BFM_CPM_OPCR_MASK_INT(v) BM_CPM_OPCR_MASK_INT | ||
815 | #define BF_CPM_OPCR_MASK_INT_V(e) BF_CPM_OPCR_MASK_INT(BV_CPM_OPCR_MASK_INT__##e) | ||
816 | #define BFM_CPM_OPCR_MASK_INT_V(v) BM_CPM_OPCR_MASK_INT | ||
817 | #define BP_CPM_OPCR_MASK_VPU 29 | ||
818 | #define BM_CPM_OPCR_MASK_VPU 0x20000000 | ||
819 | #define BF_CPM_OPCR_MASK_VPU(v) (((v) & 0x1) << 29) | ||
820 | #define BFM_CPM_OPCR_MASK_VPU(v) BM_CPM_OPCR_MASK_VPU | ||
821 | #define BF_CPM_OPCR_MASK_VPU_V(e) BF_CPM_OPCR_MASK_VPU(BV_CPM_OPCR_MASK_VPU__##e) | ||
822 | #define BFM_CPM_OPCR_MASK_VPU_V(v) BM_CPM_OPCR_MASK_VPU | ||
823 | #define BP_CPM_OPCR_GATE_SCLK_A_BUS 28 | ||
824 | #define BM_CPM_OPCR_GATE_SCLK_A_BUS 0x10000000 | ||
825 | #define BF_CPM_OPCR_GATE_SCLK_A_BUS(v) (((v) & 0x1) << 28) | ||
826 | #define BFM_CPM_OPCR_GATE_SCLK_A_BUS(v) BM_CPM_OPCR_GATE_SCLK_A_BUS | ||
827 | #define BF_CPM_OPCR_GATE_SCLK_A_BUS_V(e) BF_CPM_OPCR_GATE_SCLK_A_BUS(BV_CPM_OPCR_GATE_SCLK_A_BUS__##e) | ||
828 | #define BFM_CPM_OPCR_GATE_SCLK_A_BUS_V(v) BM_CPM_OPCR_GATE_SCLK_A_BUS | ||
829 | #define BP_CPM_OPCR_L2C_PD 25 | ||
830 | #define BM_CPM_OPCR_L2C_PD 0x2000000 | ||
831 | #define BF_CPM_OPCR_L2C_PD(v) (((v) & 0x1) << 25) | ||
832 | #define BFM_CPM_OPCR_L2C_PD(v) BM_CPM_OPCR_L2C_PD | ||
833 | #define BF_CPM_OPCR_L2C_PD_V(e) BF_CPM_OPCR_L2C_PD(BV_CPM_OPCR_L2C_PD__##e) | ||
834 | #define BFM_CPM_OPCR_L2C_PD_V(v) BM_CPM_OPCR_L2C_PD | ||
835 | #define BP_CPM_OPCR_REQ_MODE 24 | ||
836 | #define BM_CPM_OPCR_REQ_MODE 0x1000000 | ||
837 | #define BF_CPM_OPCR_REQ_MODE(v) (((v) & 0x1) << 24) | ||
838 | #define BFM_CPM_OPCR_REQ_MODE(v) BM_CPM_OPCR_REQ_MODE | ||
839 | #define BF_CPM_OPCR_REQ_MODE_V(e) BF_CPM_OPCR_REQ_MODE(BV_CPM_OPCR_REQ_MODE__##e) | ||
840 | #define BFM_CPM_OPCR_REQ_MODE_V(v) BM_CPM_OPCR_REQ_MODE | ||
841 | #define BP_CPM_OPCR_GATE_USBPHY_CLK 23 | ||
842 | #define BM_CPM_OPCR_GATE_USBPHY_CLK 0x800000 | ||
843 | #define BF_CPM_OPCR_GATE_USBPHY_CLK(v) (((v) & 0x1) << 23) | ||
844 | #define BFM_CPM_OPCR_GATE_USBPHY_CLK(v) BM_CPM_OPCR_GATE_USBPHY_CLK | ||
845 | #define BF_CPM_OPCR_GATE_USBPHY_CLK_V(e) BF_CPM_OPCR_GATE_USBPHY_CLK(BV_CPM_OPCR_GATE_USBPHY_CLK__##e) | ||
846 | #define BFM_CPM_OPCR_GATE_USBPHY_CLK_V(v) BM_CPM_OPCR_GATE_USBPHY_CLK | ||
847 | #define BP_CPM_OPCR_DIS_STOP_MUX 22 | ||
848 | #define BM_CPM_OPCR_DIS_STOP_MUX 0x400000 | ||
849 | #define BF_CPM_OPCR_DIS_STOP_MUX(v) (((v) & 0x1) << 22) | ||
850 | #define BFM_CPM_OPCR_DIS_STOP_MUX(v) BM_CPM_OPCR_DIS_STOP_MUX | ||
851 | #define BF_CPM_OPCR_DIS_STOP_MUX_V(e) BF_CPM_OPCR_DIS_STOP_MUX(BV_CPM_OPCR_DIS_STOP_MUX__##e) | ||
852 | #define BFM_CPM_OPCR_DIS_STOP_MUX_V(v) BM_CPM_OPCR_DIS_STOP_MUX | ||
853 | #define BP_CPM_OPCR_SPENDN0 7 | ||
854 | #define BM_CPM_OPCR_SPENDN0 0x80 | ||
855 | #define BF_CPM_OPCR_SPENDN0(v) (((v) & 0x1) << 7) | ||
856 | #define BFM_CPM_OPCR_SPENDN0(v) BM_CPM_OPCR_SPENDN0 | ||
857 | #define BF_CPM_OPCR_SPENDN0_V(e) BF_CPM_OPCR_SPENDN0(BV_CPM_OPCR_SPENDN0__##e) | ||
858 | #define BFM_CPM_OPCR_SPENDN0_V(v) BM_CPM_OPCR_SPENDN0 | ||
859 | #define BP_CPM_OPCR_SPENDN1 6 | ||
860 | #define BM_CPM_OPCR_SPENDN1 0x40 | ||
861 | #define BF_CPM_OPCR_SPENDN1(v) (((v) & 0x1) << 6) | ||
862 | #define BFM_CPM_OPCR_SPENDN1(v) BM_CPM_OPCR_SPENDN1 | ||
863 | #define BF_CPM_OPCR_SPENDN1_V(e) BF_CPM_OPCR_SPENDN1(BV_CPM_OPCR_SPENDN1__##e) | ||
864 | #define BFM_CPM_OPCR_SPENDN1_V(v) BM_CPM_OPCR_SPENDN1 | ||
865 | #define BP_CPM_OPCR_CPU_MODE 5 | ||
866 | #define BM_CPM_OPCR_CPU_MODE 0x20 | ||
867 | #define BF_CPM_OPCR_CPU_MODE(v) (((v) & 0x1) << 5) | ||
868 | #define BFM_CPM_OPCR_CPU_MODE(v) BM_CPM_OPCR_CPU_MODE | ||
869 | #define BF_CPM_OPCR_CPU_MODE_V(e) BF_CPM_OPCR_CPU_MODE(BV_CPM_OPCR_CPU_MODE__##e) | ||
870 | #define BFM_CPM_OPCR_CPU_MODE_V(v) BM_CPM_OPCR_CPU_MODE | ||
871 | #define BP_CPM_OPCR_O1SE 4 | ||
872 | #define BM_CPM_OPCR_O1SE 0x10 | ||
873 | #define BF_CPM_OPCR_O1SE(v) (((v) & 0x1) << 4) | ||
874 | #define BFM_CPM_OPCR_O1SE(v) BM_CPM_OPCR_O1SE | ||
875 | #define BF_CPM_OPCR_O1SE_V(e) BF_CPM_OPCR_O1SE(BV_CPM_OPCR_O1SE__##e) | ||
876 | #define BFM_CPM_OPCR_O1SE_V(v) BM_CPM_OPCR_O1SE | ||
877 | #define BP_CPM_OPCR_PD 3 | ||
878 | #define BM_CPM_OPCR_PD 0x8 | ||
879 | #define BF_CPM_OPCR_PD(v) (((v) & 0x1) << 3) | ||
880 | #define BFM_CPM_OPCR_PD(v) BM_CPM_OPCR_PD | ||
881 | #define BF_CPM_OPCR_PD_V(e) BF_CPM_OPCR_PD(BV_CPM_OPCR_PD__##e) | ||
882 | #define BFM_CPM_OPCR_PD_V(v) BM_CPM_OPCR_PD | ||
883 | #define BP_CPM_OPCR_ERCS 2 | ||
884 | #define BM_CPM_OPCR_ERCS 0x4 | ||
885 | #define BF_CPM_OPCR_ERCS(v) (((v) & 0x1) << 2) | ||
886 | #define BFM_CPM_OPCR_ERCS(v) BM_CPM_OPCR_ERCS | ||
887 | #define BF_CPM_OPCR_ERCS_V(e) BF_CPM_OPCR_ERCS(BV_CPM_OPCR_ERCS__##e) | ||
888 | #define BFM_CPM_OPCR_ERCS_V(v) BM_CPM_OPCR_ERCS | ||
889 | #define BP_CPM_OPCR_BUS_MODE 1 | ||
890 | #define BM_CPM_OPCR_BUS_MODE 0x2 | ||
891 | #define BF_CPM_OPCR_BUS_MODE(v) (((v) & 0x1) << 1) | ||
892 | #define BFM_CPM_OPCR_BUS_MODE(v) BM_CPM_OPCR_BUS_MODE | ||
893 | #define BF_CPM_OPCR_BUS_MODE_V(e) BF_CPM_OPCR_BUS_MODE(BV_CPM_OPCR_BUS_MODE__##e) | ||
894 | #define BFM_CPM_OPCR_BUS_MODE_V(v) BM_CPM_OPCR_BUS_MODE | ||
895 | |||
896 | #endif /* __HEADERGEN_CPM_H__*/ | ||