diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/ddrphy.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/ddrphy.h | 155 |
1 files changed, 155 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h b/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h new file mode 100644 index 0000000000..2ac0563090 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrphy.h | |||
@@ -0,0 +1,155 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DDRPHY_H__ | ||
25 | #define __HEADERGEN_DDRPHY_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DDRPHY_PIR jz_reg(DDRPHY_PIR) | ||
30 | #define JA_DDRPHY_PIR (0xb3011000 + 0x4) | ||
31 | #define JT_DDRPHY_PIR JIO_32_RW | ||
32 | #define JN_DDRPHY_PIR DDRPHY_PIR | ||
33 | #define JI_DDRPHY_PIR | ||
34 | |||
35 | #define REG_DDRPHY_PGCR jz_reg(DDRPHY_PGCR) | ||
36 | #define JA_DDRPHY_PGCR (0xb3011000 + 0x8) | ||
37 | #define JT_DDRPHY_PGCR JIO_32_RW | ||
38 | #define JN_DDRPHY_PGCR DDRPHY_PGCR | ||
39 | #define JI_DDRPHY_PGCR | ||
40 | |||
41 | #define REG_DDRPHY_PGSR jz_reg(DDRPHY_PGSR) | ||
42 | #define JA_DDRPHY_PGSR (0xb3011000 + 0xc) | ||
43 | #define JT_DDRPHY_PGSR JIO_32_RW | ||
44 | #define JN_DDRPHY_PGSR DDRPHY_PGSR | ||
45 | #define JI_DDRPHY_PGSR | ||
46 | |||
47 | #define REG_DDRPHY_DLLGCR jz_reg(DDRPHY_DLLGCR) | ||
48 | #define JA_DDRPHY_DLLGCR (0xb3011000 + 0x10) | ||
49 | #define JT_DDRPHY_DLLGCR JIO_32_RW | ||
50 | #define JN_DDRPHY_DLLGCR DDRPHY_DLLGCR | ||
51 | #define JI_DDRPHY_DLLGCR | ||
52 | |||
53 | #define REG_DDRPHY_ACDLLCR jz_reg(DDRPHY_ACDLLCR) | ||
54 | #define JA_DDRPHY_ACDLLCR (0xb3011000 + 0x14) | ||
55 | #define JT_DDRPHY_ACDLLCR JIO_32_RW | ||
56 | #define JN_DDRPHY_ACDLLCR DDRPHY_ACDLLCR | ||
57 | #define JI_DDRPHY_ACDLLCR | ||
58 | |||
59 | #define REG_DDRPHY_PTR0 jz_reg(DDRPHY_PTR0) | ||
60 | #define JA_DDRPHY_PTR0 (0xb3011000 + 0x18) | ||
61 | #define JT_DDRPHY_PTR0 JIO_32_RW | ||
62 | #define JN_DDRPHY_PTR0 DDRPHY_PTR0 | ||
63 | #define JI_DDRPHY_PTR0 | ||
64 | |||
65 | #define REG_DDRPHY_PTR1 jz_reg(DDRPHY_PTR1) | ||
66 | #define JA_DDRPHY_PTR1 (0xb3011000 + 0x1c) | ||
67 | #define JT_DDRPHY_PTR1 JIO_32_RW | ||
68 | #define JN_DDRPHY_PTR1 DDRPHY_PTR1 | ||
69 | #define JI_DDRPHY_PTR1 | ||
70 | |||
71 | #define REG_DDRPHY_PTR2 jz_reg(DDRPHY_PTR2) | ||
72 | #define JA_DDRPHY_PTR2 (0xb3011000 + 0x20) | ||
73 | #define JT_DDRPHY_PTR2 JIO_32_RW | ||
74 | #define JN_DDRPHY_PTR2 DDRPHY_PTR2 | ||
75 | #define JI_DDRPHY_PTR2 | ||
76 | |||
77 | #define REG_DDRPHY_ACIOCR jz_reg(DDRPHY_ACIOCR) | ||
78 | #define JA_DDRPHY_ACIOCR (0xb3011000 + 0x24) | ||
79 | #define JT_DDRPHY_ACIOCR JIO_32_RW | ||
80 | #define JN_DDRPHY_ACIOCR DDRPHY_ACIOCR | ||
81 | #define JI_DDRPHY_ACIOCR | ||
82 | |||
83 | #define REG_DDRPHY_DXCCR jz_reg(DDRPHY_DXCCR) | ||
84 | #define JA_DDRPHY_DXCCR (0xb3011000 + 0x28) | ||
85 | #define JT_DDRPHY_DXCCR JIO_32_RW | ||
86 | #define JN_DDRPHY_DXCCR DDRPHY_DXCCR | ||
87 | #define JI_DDRPHY_DXCCR | ||
88 | |||
89 | #define REG_DDRPHY_DSGCR jz_reg(DDRPHY_DSGCR) | ||
90 | #define JA_DDRPHY_DSGCR (0xb3011000 + 0x2c) | ||
91 | #define JT_DDRPHY_DSGCR JIO_32_RW | ||
92 | #define JN_DDRPHY_DSGCR DDRPHY_DSGCR | ||
93 | #define JI_DDRPHY_DSGCR | ||
94 | |||
95 | #define REG_DDRPHY_DCR jz_reg(DDRPHY_DCR) | ||
96 | #define JA_DDRPHY_DCR (0xb3011000 + 0x30) | ||
97 | #define JT_DDRPHY_DCR JIO_32_RW | ||
98 | #define JN_DDRPHY_DCR DDRPHY_DCR | ||
99 | #define JI_DDRPHY_DCR | ||
100 | |||
101 | #define REG_DDRPHY_DTPR0 jz_reg(DDRPHY_DTPR0) | ||
102 | #define JA_DDRPHY_DTPR0 (0xb3011000 + 0x34) | ||
103 | #define JT_DDRPHY_DTPR0 JIO_32_RW | ||
104 | #define JN_DDRPHY_DTPR0 DDRPHY_DTPR0 | ||
105 | #define JI_DDRPHY_DTPR0 | ||
106 | |||
107 | #define REG_DDRPHY_DTPR1 jz_reg(DDRPHY_DTPR1) | ||
108 | #define JA_DDRPHY_DTPR1 (0xb3011000 + 0x38) | ||
109 | #define JT_DDRPHY_DTPR1 JIO_32_RW | ||
110 | #define JN_DDRPHY_DTPR1 DDRPHY_DTPR1 | ||
111 | #define JI_DDRPHY_DTPR1 | ||
112 | |||
113 | #define REG_DDRPHY_DTPR2 jz_reg(DDRPHY_DTPR2) | ||
114 | #define JA_DDRPHY_DTPR2 (0xb3011000 + 0x3c) | ||
115 | #define JT_DDRPHY_DTPR2 JIO_32_RW | ||
116 | #define JN_DDRPHY_DTPR2 DDRPHY_DTPR2 | ||
117 | #define JI_DDRPHY_DTPR2 | ||
118 | |||
119 | #define REG_DDRPHY_MR0 jz_reg(DDRPHY_MR0) | ||
120 | #define JA_DDRPHY_MR0 (0xb3011000 + 0x40) | ||
121 | #define JT_DDRPHY_MR0 JIO_32_RW | ||
122 | #define JN_DDRPHY_MR0 DDRPHY_MR0 | ||
123 | #define JI_DDRPHY_MR0 | ||
124 | |||
125 | #define REG_DDRPHY_MR1 jz_reg(DDRPHY_MR1) | ||
126 | #define JA_DDRPHY_MR1 (0xb3011000 + 0x44) | ||
127 | #define JT_DDRPHY_MR1 JIO_32_RW | ||
128 | #define JN_DDRPHY_MR1 DDRPHY_MR1 | ||
129 | #define JI_DDRPHY_MR1 | ||
130 | |||
131 | #define REG_DDRPHY_MR2 jz_reg(DDRPHY_MR2) | ||
132 | #define JA_DDRPHY_MR2 (0xb3011000 + 0x48) | ||
133 | #define JT_DDRPHY_MR2 JIO_32_RW | ||
134 | #define JN_DDRPHY_MR2 DDRPHY_MR2 | ||
135 | #define JI_DDRPHY_MR2 | ||
136 | |||
137 | #define REG_DDRPHY_MR3 jz_reg(DDRPHY_MR3) | ||
138 | #define JA_DDRPHY_MR3 (0xb3011000 + 0x4c) | ||
139 | #define JT_DDRPHY_MR3 JIO_32_RW | ||
140 | #define JN_DDRPHY_MR3 DDRPHY_MR3 | ||
141 | #define JI_DDRPHY_MR3 | ||
142 | |||
143 | #define REG_DDRPHY_DTAR jz_reg(DDRPHY_DTAR) | ||
144 | #define JA_DDRPHY_DTAR (0xb3011000 + 0x54) | ||
145 | #define JT_DDRPHY_DTAR JIO_32_RW | ||
146 | #define JN_DDRPHY_DTAR DDRPHY_DTAR | ||
147 | #define JI_DDRPHY_DTAR | ||
148 | |||
149 | #define REG_DDRPHY_DXGCR(_n1) jz_reg(DDRPHY_DXGCR(_n1)) | ||
150 | #define JA_DDRPHY_DXGCR(_n1) (0xb3011000 + 0x1c0 + (_n1) * 0x40) | ||
151 | #define JT_DDRPHY_DXGCR(_n1) JIO_32_RW | ||
152 | #define JN_DDRPHY_DXGCR(_n1) DDRPHY_DXGCR | ||
153 | #define JI_DDRPHY_DXGCR(_n1) (_n1) | ||
154 | |||
155 | #endif /* __HEADERGEN_DDRPHY_H__*/ | ||