diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/rtc.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/rtc.h | 221 |
1 files changed, 221 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/rtc.h b/firmware/target/mips/ingenic_x1000/x1000/rtc.h new file mode 100644 index 0000000000..38f82e7d0d --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/rtc.h | |||
@@ -0,0 +1,221 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_RTC_H__ | ||
25 | #define __HEADERGEN_RTC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_RTC_CR jz_reg(RTC_CR) | ||
30 | #define JA_RTC_CR (0xb0003000 + 0x0) | ||
31 | #define JT_RTC_CR JIO_32_RW | ||
32 | #define JN_RTC_CR RTC_CR | ||
33 | #define JI_RTC_CR | ||
34 | #define BP_RTC_CR_WRDY 7 | ||
35 | #define BM_RTC_CR_WRDY 0x80 | ||
36 | #define BF_RTC_CR_WRDY(v) (((v) & 0x1) << 7) | ||
37 | #define BFM_RTC_CR_WRDY(v) BM_RTC_CR_WRDY | ||
38 | #define BF_RTC_CR_WRDY_V(e) BF_RTC_CR_WRDY(BV_RTC_CR_WRDY__##e) | ||
39 | #define BFM_RTC_CR_WRDY_V(v) BM_RTC_CR_WRDY | ||
40 | #define BP_RTC_CR_1HZ 6 | ||
41 | #define BM_RTC_CR_1HZ 0x40 | ||
42 | #define BF_RTC_CR_1HZ(v) (((v) & 0x1) << 6) | ||
43 | #define BFM_RTC_CR_1HZ(v) BM_RTC_CR_1HZ | ||
44 | #define BF_RTC_CR_1HZ_V(e) BF_RTC_CR_1HZ(BV_RTC_CR_1HZ__##e) | ||
45 | #define BFM_RTC_CR_1HZ_V(v) BM_RTC_CR_1HZ | ||
46 | #define BP_RTC_CR_1HZIE 5 | ||
47 | #define BM_RTC_CR_1HZIE 0x20 | ||
48 | #define BF_RTC_CR_1HZIE(v) (((v) & 0x1) << 5) | ||
49 | #define BFM_RTC_CR_1HZIE(v) BM_RTC_CR_1HZIE | ||
50 | #define BF_RTC_CR_1HZIE_V(e) BF_RTC_CR_1HZIE(BV_RTC_CR_1HZIE__##e) | ||
51 | #define BFM_RTC_CR_1HZIE_V(v) BM_RTC_CR_1HZIE | ||
52 | #define BP_RTC_CR_AF 4 | ||
53 | #define BM_RTC_CR_AF 0x10 | ||
54 | #define BF_RTC_CR_AF(v) (((v) & 0x1) << 4) | ||
55 | #define BFM_RTC_CR_AF(v) BM_RTC_CR_AF | ||
56 | #define BF_RTC_CR_AF_V(e) BF_RTC_CR_AF(BV_RTC_CR_AF__##e) | ||
57 | #define BFM_RTC_CR_AF_V(v) BM_RTC_CR_AF | ||
58 | #define BP_RTC_CR_AIE 3 | ||
59 | #define BM_RTC_CR_AIE 0x8 | ||
60 | #define BF_RTC_CR_AIE(v) (((v) & 0x1) << 3) | ||
61 | #define BFM_RTC_CR_AIE(v) BM_RTC_CR_AIE | ||
62 | #define BF_RTC_CR_AIE_V(e) BF_RTC_CR_AIE(BV_RTC_CR_AIE__##e) | ||
63 | #define BFM_RTC_CR_AIE_V(v) BM_RTC_CR_AIE | ||
64 | #define BP_RTC_CR_AE 2 | ||
65 | #define BM_RTC_CR_AE 0x4 | ||
66 | #define BF_RTC_CR_AE(v) (((v) & 0x1) << 2) | ||
67 | #define BFM_RTC_CR_AE(v) BM_RTC_CR_AE | ||
68 | #define BF_RTC_CR_AE_V(e) BF_RTC_CR_AE(BV_RTC_CR_AE__##e) | ||
69 | #define BFM_RTC_CR_AE_V(v) BM_RTC_CR_AE | ||
70 | #define BP_RTC_CR_SELEXC 1 | ||
71 | #define BM_RTC_CR_SELEXC 0x2 | ||
72 | #define BF_RTC_CR_SELEXC(v) (((v) & 0x1) << 1) | ||
73 | #define BFM_RTC_CR_SELEXC(v) BM_RTC_CR_SELEXC | ||
74 | #define BF_RTC_CR_SELEXC_V(e) BF_RTC_CR_SELEXC(BV_RTC_CR_SELEXC__##e) | ||
75 | #define BFM_RTC_CR_SELEXC_V(v) BM_RTC_CR_SELEXC | ||
76 | #define BP_RTC_CR_ENABLE 0 | ||
77 | #define BM_RTC_CR_ENABLE 0x1 | ||
78 | #define BF_RTC_CR_ENABLE(v) (((v) & 0x1) << 0) | ||
79 | #define BFM_RTC_CR_ENABLE(v) BM_RTC_CR_ENABLE | ||
80 | #define BF_RTC_CR_ENABLE_V(e) BF_RTC_CR_ENABLE(BV_RTC_CR_ENABLE__##e) | ||
81 | #define BFM_RTC_CR_ENABLE_V(v) BM_RTC_CR_ENABLE | ||
82 | |||
83 | #define REG_RTC_SR jz_reg(RTC_SR) | ||
84 | #define JA_RTC_SR (0xb0003000 + 0x4) | ||
85 | #define JT_RTC_SR JIO_32_RW | ||
86 | #define JN_RTC_SR RTC_SR | ||
87 | #define JI_RTC_SR | ||
88 | |||
89 | #define REG_RTC_SAR jz_reg(RTC_SAR) | ||
90 | #define JA_RTC_SAR (0xb0003000 + 0x8) | ||
91 | #define JT_RTC_SAR JIO_32_RW | ||
92 | #define JN_RTC_SAR RTC_SAR | ||
93 | #define JI_RTC_SAR | ||
94 | |||
95 | #define REG_RTC_GR jz_reg(RTC_GR) | ||
96 | #define JA_RTC_GR (0xb0003000 + 0xc) | ||
97 | #define JT_RTC_GR JIO_32_RW | ||
98 | #define JN_RTC_GR RTC_GR | ||
99 | #define JI_RTC_GR | ||
100 | #define BP_RTC_GR_ADJC 16 | ||
101 | #define BM_RTC_GR_ADJC 0x3ff0000 | ||
102 | #define BF_RTC_GR_ADJC(v) (((v) & 0x3ff) << 16) | ||
103 | #define BFM_RTC_GR_ADJC(v) BM_RTC_GR_ADJC | ||
104 | #define BF_RTC_GR_ADJC_V(e) BF_RTC_GR_ADJC(BV_RTC_GR_ADJC__##e) | ||
105 | #define BFM_RTC_GR_ADJC_V(v) BM_RTC_GR_ADJC | ||
106 | #define BP_RTC_GR_NC1HZ 0 | ||
107 | #define BM_RTC_GR_NC1HZ 0xffff | ||
108 | #define BF_RTC_GR_NC1HZ(v) (((v) & 0xffff) << 0) | ||
109 | #define BFM_RTC_GR_NC1HZ(v) BM_RTC_GR_NC1HZ | ||
110 | #define BF_RTC_GR_NC1HZ_V(e) BF_RTC_GR_NC1HZ(BV_RTC_GR_NC1HZ__##e) | ||
111 | #define BFM_RTC_GR_NC1HZ_V(v) BM_RTC_GR_NC1HZ | ||
112 | #define BP_RTC_GR_LOCK 31 | ||
113 | #define BM_RTC_GR_LOCK 0x80000000 | ||
114 | #define BF_RTC_GR_LOCK(v) (((v) & 0x1) << 31) | ||
115 | #define BFM_RTC_GR_LOCK(v) BM_RTC_GR_LOCK | ||
116 | #define BF_RTC_GR_LOCK_V(e) BF_RTC_GR_LOCK(BV_RTC_GR_LOCK__##e) | ||
117 | #define BFM_RTC_GR_LOCK_V(v) BM_RTC_GR_LOCK | ||
118 | |||
119 | #define REG_RTC_HCR jz_reg(RTC_HCR) | ||
120 | #define JA_RTC_HCR (0xb0003000 + 0x20) | ||
121 | #define JT_RTC_HCR JIO_32_RW | ||
122 | #define JN_RTC_HCR RTC_HCR | ||
123 | #define JI_RTC_HCR | ||
124 | |||
125 | #define REG_RTC_HWFCR jz_reg(RTC_HWFCR) | ||
126 | #define JA_RTC_HWFCR (0xb0003000 + 0x24) | ||
127 | #define JT_RTC_HWFCR JIO_32_RW | ||
128 | #define JN_RTC_HWFCR RTC_HWFCR | ||
129 | #define JI_RTC_HWFCR | ||
130 | |||
131 | #define REG_RTC_HRCR jz_reg(RTC_HRCR) | ||
132 | #define JA_RTC_HRCR (0xb0003000 + 0x28) | ||
133 | #define JT_RTC_HRCR JIO_32_RW | ||
134 | #define JN_RTC_HRCR RTC_HRCR | ||
135 | #define JI_RTC_HRCR | ||
136 | |||
137 | #define REG_RTC_HWCR jz_reg(RTC_HWCR) | ||
138 | #define JA_RTC_HWCR (0xb0003000 + 0x2c) | ||
139 | #define JT_RTC_HWCR JIO_32_RW | ||
140 | #define JN_RTC_HWCR RTC_HWCR | ||
141 | #define JI_RTC_HWCR | ||
142 | #define BP_RTC_HWCR_EPDET 3 | ||
143 | #define BM_RTC_HWCR_EPDET 0xfffffff8 | ||
144 | #define BF_RTC_HWCR_EPDET(v) (((v) & 0x1fffffff) << 3) | ||
145 | #define BFM_RTC_HWCR_EPDET(v) BM_RTC_HWCR_EPDET | ||
146 | #define BF_RTC_HWCR_EPDET_V(e) BF_RTC_HWCR_EPDET(BV_RTC_HWCR_EPDET__##e) | ||
147 | #define BFM_RTC_HWCR_EPDET_V(v) BM_RTC_HWCR_EPDET | ||
148 | #define BP_RTC_HWCR_EALM 1 | ||
149 | #define BM_RTC_HWCR_EALM 0x2 | ||
150 | #define BF_RTC_HWCR_EALM(v) (((v) & 0x1) << 1) | ||
151 | #define BFM_RTC_HWCR_EALM(v) BM_RTC_HWCR_EALM | ||
152 | #define BF_RTC_HWCR_EALM_V(e) BF_RTC_HWCR_EALM(BV_RTC_HWCR_EALM__##e) | ||
153 | #define BFM_RTC_HWCR_EALM_V(v) BM_RTC_HWCR_EALM | ||
154 | |||
155 | #define REG_RTC_HWRSR jz_reg(RTC_HWRSR) | ||
156 | #define JA_RTC_HWRSR (0xb0003000 + 0x30) | ||
157 | #define JT_RTC_HWRSR JIO_32_RW | ||
158 | #define JN_RTC_HWRSR RTC_HWRSR | ||
159 | #define JI_RTC_HWRSR | ||
160 | #define BP_RTC_HWRSR_APD 8 | ||
161 | #define BM_RTC_HWRSR_APD 0x100 | ||
162 | #define BF_RTC_HWRSR_APD(v) (((v) & 0x1) << 8) | ||
163 | #define BFM_RTC_HWRSR_APD(v) BM_RTC_HWRSR_APD | ||
164 | #define BF_RTC_HWRSR_APD_V(e) BF_RTC_HWRSR_APD(BV_RTC_HWRSR_APD__##e) | ||
165 | #define BFM_RTC_HWRSR_APD_V(v) BM_RTC_HWRSR_APD | ||
166 | #define BP_RTC_HWRSR_HR 5 | ||
167 | #define BM_RTC_HWRSR_HR 0x20 | ||
168 | #define BF_RTC_HWRSR_HR(v) (((v) & 0x1) << 5) | ||
169 | #define BFM_RTC_HWRSR_HR(v) BM_RTC_HWRSR_HR | ||
170 | #define BF_RTC_HWRSR_HR_V(e) BF_RTC_HWRSR_HR(BV_RTC_HWRSR_HR__##e) | ||
171 | #define BFM_RTC_HWRSR_HR_V(v) BM_RTC_HWRSR_HR | ||
172 | #define BP_RTC_HWRSR_PPR 4 | ||
173 | #define BM_RTC_HWRSR_PPR 0x10 | ||
174 | #define BF_RTC_HWRSR_PPR(v) (((v) & 0x1) << 4) | ||
175 | #define BFM_RTC_HWRSR_PPR(v) BM_RTC_HWRSR_PPR | ||
176 | #define BF_RTC_HWRSR_PPR_V(e) BF_RTC_HWRSR_PPR(BV_RTC_HWRSR_PPR__##e) | ||
177 | #define BFM_RTC_HWRSR_PPR_V(v) BM_RTC_HWRSR_PPR | ||
178 | #define BP_RTC_HWRSR_PIN 1 | ||
179 | #define BM_RTC_HWRSR_PIN 0x2 | ||
180 | #define BF_RTC_HWRSR_PIN(v) (((v) & 0x1) << 1) | ||
181 | #define BFM_RTC_HWRSR_PIN(v) BM_RTC_HWRSR_PIN | ||
182 | #define BF_RTC_HWRSR_PIN_V(e) BF_RTC_HWRSR_PIN(BV_RTC_HWRSR_PIN__##e) | ||
183 | #define BFM_RTC_HWRSR_PIN_V(v) BM_RTC_HWRSR_PIN | ||
184 | #define BP_RTC_HWRSR_ALM 0 | ||
185 | #define BM_RTC_HWRSR_ALM 0x1 | ||
186 | #define BF_RTC_HWRSR_ALM(v) (((v) & 0x1) << 0) | ||
187 | #define BFM_RTC_HWRSR_ALM(v) BM_RTC_HWRSR_ALM | ||
188 | #define BF_RTC_HWRSR_ALM_V(e) BF_RTC_HWRSR_ALM(BV_RTC_HWRSR_ALM__##e) | ||
189 | #define BFM_RTC_HWRSR_ALM_V(v) BM_RTC_HWRSR_ALM | ||
190 | |||
191 | #define REG_RTC_HSPR jz_reg(RTC_HSPR) | ||
192 | #define JA_RTC_HSPR (0xb0003000 + 0x34) | ||
193 | #define JT_RTC_HSPR JIO_32_RW | ||
194 | #define JN_RTC_HSPR RTC_HSPR | ||
195 | #define JI_RTC_HSPR | ||
196 | |||
197 | #define REG_RTC_WENR jz_reg(RTC_WENR) | ||
198 | #define JA_RTC_WENR (0xb0003000 + 0x3c) | ||
199 | #define JT_RTC_WENR JIO_32_RW | ||
200 | #define JN_RTC_WENR RTC_WENR | ||
201 | #define JI_RTC_WENR | ||
202 | #define BP_RTC_WENR_WEN 31 | ||
203 | #define BM_RTC_WENR_WEN 0x80000000 | ||
204 | #define BF_RTC_WENR_WEN(v) (((v) & 0x1) << 31) | ||
205 | #define BFM_RTC_WENR_WEN(v) BM_RTC_WENR_WEN | ||
206 | #define BF_RTC_WENR_WEN_V(e) BF_RTC_WENR_WEN(BV_RTC_WENR_WEN__##e) | ||
207 | #define BFM_RTC_WENR_WEN_V(v) BM_RTC_WENR_WEN | ||
208 | #define BP_RTC_WENR_WENPAT 0 | ||
209 | #define BM_RTC_WENR_WENPAT 0xffff | ||
210 | #define BF_RTC_WENR_WENPAT(v) (((v) & 0xffff) << 0) | ||
211 | #define BFM_RTC_WENR_WENPAT(v) BM_RTC_WENR_WENPAT | ||
212 | #define BF_RTC_WENR_WENPAT_V(e) BF_RTC_WENR_WENPAT(BV_RTC_WENR_WENPAT__##e) | ||
213 | #define BFM_RTC_WENR_WENPAT_V(v) BM_RTC_WENR_WENPAT | ||
214 | |||
215 | #define REG_RTC_WKUPPINCR jz_reg(RTC_WKUPPINCR) | ||
216 | #define JA_RTC_WKUPPINCR (0xb0003000 + 0x48) | ||
217 | #define JT_RTC_WKUPPINCR JIO_32_RW | ||
218 | #define JN_RTC_WKUPPINCR RTC_WKUPPINCR | ||
219 | #define JI_RTC_WKUPPINCR | ||
220 | |||
221 | #endif /* __HEADERGEN_RTC_H__*/ | ||