diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/dma_chn.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/dma_chn.h | 253 |
1 files changed, 253 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h b/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h new file mode 100644 index 0000000000..56eb2a8cc1 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/dma_chn.h | |||
@@ -0,0 +1,253 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DMA_CHN_H__ | ||
25 | #define __HEADERGEN_DMA_CHN_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DMA_CHN_SA(_n1) jz_reg(DMA_CHN_SA(_n1)) | ||
30 | #define JA_DMA_CHN_SA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x0) | ||
31 | #define JT_DMA_CHN_SA(_n1) JIO_32_RW | ||
32 | #define JN_DMA_CHN_SA(_n1) DMA_CHN_SA | ||
33 | #define JI_DMA_CHN_SA(_n1) (_n1) | ||
34 | |||
35 | #define REG_DMA_CHN_TA(_n1) jz_reg(DMA_CHN_TA(_n1)) | ||
36 | #define JA_DMA_CHN_TA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x4) | ||
37 | #define JT_DMA_CHN_TA(_n1) JIO_32_RW | ||
38 | #define JN_DMA_CHN_TA(_n1) DMA_CHN_TA | ||
39 | #define JI_DMA_CHN_TA(_n1) (_n1) | ||
40 | |||
41 | #define REG_DMA_CHN_TC(_n1) jz_reg(DMA_CHN_TC(_n1)) | ||
42 | #define JA_DMA_CHN_TC(_n1) (0xb3420000 + (_n1) * 0x20 + 0x8) | ||
43 | #define JT_DMA_CHN_TC(_n1) JIO_32_RW | ||
44 | #define JN_DMA_CHN_TC(_n1) DMA_CHN_TC | ||
45 | #define JI_DMA_CHN_TC(_n1) (_n1) | ||
46 | #define BP_DMA_CHN_TC_DOA 24 | ||
47 | #define BM_DMA_CHN_TC_DOA 0xff000000 | ||
48 | #define BF_DMA_CHN_TC_DOA(v) (((v) & 0xff) << 24) | ||
49 | #define BFM_DMA_CHN_TC_DOA(v) BM_DMA_CHN_TC_DOA | ||
50 | #define BF_DMA_CHN_TC_DOA_V(e) BF_DMA_CHN_TC_DOA(BV_DMA_CHN_TC_DOA__##e) | ||
51 | #define BFM_DMA_CHN_TC_DOA_V(v) BM_DMA_CHN_TC_DOA | ||
52 | #define BP_DMA_CHN_TC_CNT 0 | ||
53 | #define BM_DMA_CHN_TC_CNT 0xffffff | ||
54 | #define BF_DMA_CHN_TC_CNT(v) (((v) & 0xffffff) << 0) | ||
55 | #define BFM_DMA_CHN_TC_CNT(v) BM_DMA_CHN_TC_CNT | ||
56 | #define BF_DMA_CHN_TC_CNT_V(e) BF_DMA_CHN_TC_CNT(BV_DMA_CHN_TC_CNT__##e) | ||
57 | #define BFM_DMA_CHN_TC_CNT_V(v) BM_DMA_CHN_TC_CNT | ||
58 | |||
59 | #define REG_DMA_CHN_RT(_n1) jz_reg(DMA_CHN_RT(_n1)) | ||
60 | #define JA_DMA_CHN_RT(_n1) (0xb3420000 + (_n1) * 0x20 + 0xc) | ||
61 | #define JT_DMA_CHN_RT(_n1) JIO_32_RW | ||
62 | #define JN_DMA_CHN_RT(_n1) DMA_CHN_RT | ||
63 | #define JI_DMA_CHN_RT(_n1) (_n1) | ||
64 | #define BP_DMA_CHN_RT_TYPE 0 | ||
65 | #define BM_DMA_CHN_RT_TYPE 0x3f | ||
66 | #define BV_DMA_CHN_RT_TYPE__DMIC_RX 0x5 | ||
67 | #define BV_DMA_CHN_RT_TYPE__I2S_TX 0x6 | ||
68 | #define BV_DMA_CHN_RT_TYPE__I2S_RX 0x7 | ||
69 | #define BV_DMA_CHN_RT_TYPE__AUTO 0x8 | ||
70 | #define BV_DMA_CHN_RT_TYPE__UART2_TX 0x10 | ||
71 | #define BV_DMA_CHN_RT_TYPE__UART2_RX 0x11 | ||
72 | #define BV_DMA_CHN_RT_TYPE__UART1_TX 0x12 | ||
73 | #define BV_DMA_CHN_RT_TYPE__UART1_RX 0x13 | ||
74 | #define BV_DMA_CHN_RT_TYPE__UART0_TX 0x14 | ||
75 | #define BV_DMA_CHN_RT_TYPE__UART0_RX 0x15 | ||
76 | #define BV_DMA_CHN_RT_TYPE__SSI_TX 0x16 | ||
77 | #define BV_DMA_CHN_RT_TYPE__SSI_RX 0x17 | ||
78 | #define BV_DMA_CHN_RT_TYPE__MSC0_TX 0x1a | ||
79 | #define BV_DMA_CHN_RT_TYPE__MSC0_RX 0x1b | ||
80 | #define BV_DMA_CHN_RT_TYPE__MSC1_TX 0x1c | ||
81 | #define BV_DMA_CHN_RT_TYPE__MSC1_RX 0x1d | ||
82 | #define BV_DMA_CHN_RT_TYPE__PCM_TX 0x20 | ||
83 | #define BV_DMA_CHN_RT_TYPE__PCM_RX 0x21 | ||
84 | #define BV_DMA_CHN_RT_TYPE__I2C0_TX 0x24 | ||
85 | #define BV_DMA_CHN_RT_TYPE__I2C0_RX 0x25 | ||
86 | #define BV_DMA_CHN_RT_TYPE__I2C1_TX 0x26 | ||
87 | #define BV_DMA_CHN_RT_TYPE__I2C1_RX 0x27 | ||
88 | #define BV_DMA_CHN_RT_TYPE__I2C2_TX 0x28 | ||
89 | #define BV_DMA_CHN_RT_TYPE__I2C2_RX 0x29 | ||
90 | #define BF_DMA_CHN_RT_TYPE(v) (((v) & 0x3f) << 0) | ||
91 | #define BFM_DMA_CHN_RT_TYPE(v) BM_DMA_CHN_RT_TYPE | ||
92 | #define BF_DMA_CHN_RT_TYPE_V(e) BF_DMA_CHN_RT_TYPE(BV_DMA_CHN_RT_TYPE__##e) | ||
93 | #define BFM_DMA_CHN_RT_TYPE_V(v) BM_DMA_CHN_RT_TYPE | ||
94 | |||
95 | #define REG_DMA_CHN_CS(_n1) jz_reg(DMA_CHN_CS(_n1)) | ||
96 | #define JA_DMA_CHN_CS(_n1) (0xb3420000 + (_n1) * 0x20 + 0x10) | ||
97 | #define JT_DMA_CHN_CS(_n1) JIO_32_RW | ||
98 | #define JN_DMA_CHN_CS(_n1) DMA_CHN_CS | ||
99 | #define JI_DMA_CHN_CS(_n1) (_n1) | ||
100 | #define BP_DMA_CHN_CS_CDOA 8 | ||
101 | #define BM_DMA_CHN_CS_CDOA 0xff00 | ||
102 | #define BF_DMA_CHN_CS_CDOA(v) (((v) & 0xff) << 8) | ||
103 | #define BFM_DMA_CHN_CS_CDOA(v) BM_DMA_CHN_CS_CDOA | ||
104 | #define BF_DMA_CHN_CS_CDOA_V(e) BF_DMA_CHN_CS_CDOA(BV_DMA_CHN_CS_CDOA__##e) | ||
105 | #define BFM_DMA_CHN_CS_CDOA_V(v) BM_DMA_CHN_CS_CDOA | ||
106 | #define BP_DMA_CHN_CS_NDES 31 | ||
107 | #define BM_DMA_CHN_CS_NDES 0x80000000 | ||
108 | #define BF_DMA_CHN_CS_NDES(v) (((v) & 0x1) << 31) | ||
109 | #define BFM_DMA_CHN_CS_NDES(v) BM_DMA_CHN_CS_NDES | ||
110 | #define BF_DMA_CHN_CS_NDES_V(e) BF_DMA_CHN_CS_NDES(BV_DMA_CHN_CS_NDES__##e) | ||
111 | #define BFM_DMA_CHN_CS_NDES_V(v) BM_DMA_CHN_CS_NDES | ||
112 | #define BP_DMA_CHN_CS_DES8 30 | ||
113 | #define BM_DMA_CHN_CS_DES8 0x40000000 | ||
114 | #define BF_DMA_CHN_CS_DES8(v) (((v) & 0x1) << 30) | ||
115 | #define BFM_DMA_CHN_CS_DES8(v) BM_DMA_CHN_CS_DES8 | ||
116 | #define BF_DMA_CHN_CS_DES8_V(e) BF_DMA_CHN_CS_DES8(BV_DMA_CHN_CS_DES8__##e) | ||
117 | #define BFM_DMA_CHN_CS_DES8_V(v) BM_DMA_CHN_CS_DES8 | ||
118 | #define BP_DMA_CHN_CS_AR 4 | ||
119 | #define BM_DMA_CHN_CS_AR 0x10 | ||
120 | #define BF_DMA_CHN_CS_AR(v) (((v) & 0x1) << 4) | ||
121 | #define BFM_DMA_CHN_CS_AR(v) BM_DMA_CHN_CS_AR | ||
122 | #define BF_DMA_CHN_CS_AR_V(e) BF_DMA_CHN_CS_AR(BV_DMA_CHN_CS_AR__##e) | ||
123 | #define BFM_DMA_CHN_CS_AR_V(v) BM_DMA_CHN_CS_AR | ||
124 | #define BP_DMA_CHN_CS_TT 3 | ||
125 | #define BM_DMA_CHN_CS_TT 0x8 | ||
126 | #define BF_DMA_CHN_CS_TT(v) (((v) & 0x1) << 3) | ||
127 | #define BFM_DMA_CHN_CS_TT(v) BM_DMA_CHN_CS_TT | ||
128 | #define BF_DMA_CHN_CS_TT_V(e) BF_DMA_CHN_CS_TT(BV_DMA_CHN_CS_TT__##e) | ||
129 | #define BFM_DMA_CHN_CS_TT_V(v) BM_DMA_CHN_CS_TT | ||
130 | #define BP_DMA_CHN_CS_HLT 2 | ||
131 | #define BM_DMA_CHN_CS_HLT 0x4 | ||
132 | #define BF_DMA_CHN_CS_HLT(v) (((v) & 0x1) << 2) | ||
133 | #define BFM_DMA_CHN_CS_HLT(v) BM_DMA_CHN_CS_HLT | ||
134 | #define BF_DMA_CHN_CS_HLT_V(e) BF_DMA_CHN_CS_HLT(BV_DMA_CHN_CS_HLT__##e) | ||
135 | #define BFM_DMA_CHN_CS_HLT_V(v) BM_DMA_CHN_CS_HLT | ||
136 | #define BP_DMA_CHN_CS_CTE 0 | ||
137 | #define BM_DMA_CHN_CS_CTE 0x1 | ||
138 | #define BF_DMA_CHN_CS_CTE(v) (((v) & 0x1) << 0) | ||
139 | #define BFM_DMA_CHN_CS_CTE(v) BM_DMA_CHN_CS_CTE | ||
140 | #define BF_DMA_CHN_CS_CTE_V(e) BF_DMA_CHN_CS_CTE(BV_DMA_CHN_CS_CTE__##e) | ||
141 | #define BFM_DMA_CHN_CS_CTE_V(v) BM_DMA_CHN_CS_CTE | ||
142 | |||
143 | #define REG_DMA_CHN_CM(_n1) jz_reg(DMA_CHN_CM(_n1)) | ||
144 | #define JA_DMA_CHN_CM(_n1) (0xb3420000 + (_n1) * 0x20 + 0x14) | ||
145 | #define JT_DMA_CHN_CM(_n1) JIO_32_RW | ||
146 | #define JN_DMA_CHN_CM(_n1) DMA_CHN_CM | ||
147 | #define JI_DMA_CHN_CM(_n1) (_n1) | ||
148 | #define BP_DMA_CHN_CM_RDIL 16 | ||
149 | #define BM_DMA_CHN_CM_RDIL 0xf0000 | ||
150 | #define BF_DMA_CHN_CM_RDIL(v) (((v) & 0xf) << 16) | ||
151 | #define BFM_DMA_CHN_CM_RDIL(v) BM_DMA_CHN_CM_RDIL | ||
152 | #define BF_DMA_CHN_CM_RDIL_V(e) BF_DMA_CHN_CM_RDIL(BV_DMA_CHN_CM_RDIL__##e) | ||
153 | #define BFM_DMA_CHN_CM_RDIL_V(v) BM_DMA_CHN_CM_RDIL | ||
154 | #define BP_DMA_CHN_CM_SP 14 | ||
155 | #define BM_DMA_CHN_CM_SP 0xc000 | ||
156 | #define BV_DMA_CHN_CM_SP__32BIT 0x0 | ||
157 | #define BV_DMA_CHN_CM_SP__8BIT 0x1 | ||
158 | #define BV_DMA_CHN_CM_SP__16BIT 0x2 | ||
159 | #define BF_DMA_CHN_CM_SP(v) (((v) & 0x3) << 14) | ||
160 | #define BFM_DMA_CHN_CM_SP(v) BM_DMA_CHN_CM_SP | ||
161 | #define BF_DMA_CHN_CM_SP_V(e) BF_DMA_CHN_CM_SP(BV_DMA_CHN_CM_SP__##e) | ||
162 | #define BFM_DMA_CHN_CM_SP_V(v) BM_DMA_CHN_CM_SP | ||
163 | #define BP_DMA_CHN_CM_DP 12 | ||
164 | #define BM_DMA_CHN_CM_DP 0x3000 | ||
165 | #define BV_DMA_CHN_CM_DP__32BIT 0x0 | ||
166 | #define BV_DMA_CHN_CM_DP__8BIT 0x1 | ||
167 | #define BV_DMA_CHN_CM_DP__16BIT 0x2 | ||
168 | #define BF_DMA_CHN_CM_DP(v) (((v) & 0x3) << 12) | ||
169 | #define BFM_DMA_CHN_CM_DP(v) BM_DMA_CHN_CM_DP | ||
170 | #define BF_DMA_CHN_CM_DP_V(e) BF_DMA_CHN_CM_DP(BV_DMA_CHN_CM_DP__##e) | ||
171 | #define BFM_DMA_CHN_CM_DP_V(v) BM_DMA_CHN_CM_DP | ||
172 | #define BP_DMA_CHN_CM_TSZ 8 | ||
173 | #define BM_DMA_CHN_CM_TSZ 0x700 | ||
174 | #define BV_DMA_CHN_CM_TSZ__32BIT 0x0 | ||
175 | #define BV_DMA_CHN_CM_TSZ__8BIT 0x1 | ||
176 | #define BV_DMA_CHN_CM_TSZ__16BIT 0x2 | ||
177 | #define BV_DMA_CHN_CM_TSZ__16BYTE 0x3 | ||
178 | #define BV_DMA_CHN_CM_TSZ__32BYTE 0x4 | ||
179 | #define BV_DMA_CHN_CM_TSZ__64BYTE 0x5 | ||
180 | #define BV_DMA_CHN_CM_TSZ__128BYTE 0x6 | ||
181 | #define BV_DMA_CHN_CM_TSZ__AUTO 0x7 | ||
182 | #define BF_DMA_CHN_CM_TSZ(v) (((v) & 0x7) << 8) | ||
183 | #define BFM_DMA_CHN_CM_TSZ(v) BM_DMA_CHN_CM_TSZ | ||
184 | #define BF_DMA_CHN_CM_TSZ_V(e) BF_DMA_CHN_CM_TSZ(BV_DMA_CHN_CM_TSZ__##e) | ||
185 | #define BFM_DMA_CHN_CM_TSZ_V(v) BM_DMA_CHN_CM_TSZ | ||
186 | #define BP_DMA_CHN_CM_SAI 23 | ||
187 | #define BM_DMA_CHN_CM_SAI 0x800000 | ||
188 | #define BF_DMA_CHN_CM_SAI(v) (((v) & 0x1) << 23) | ||
189 | #define BFM_DMA_CHN_CM_SAI(v) BM_DMA_CHN_CM_SAI | ||
190 | #define BF_DMA_CHN_CM_SAI_V(e) BF_DMA_CHN_CM_SAI(BV_DMA_CHN_CM_SAI__##e) | ||
191 | #define BFM_DMA_CHN_CM_SAI_V(v) BM_DMA_CHN_CM_SAI | ||
192 | #define BP_DMA_CHN_CM_DAI 22 | ||
193 | #define BM_DMA_CHN_CM_DAI 0x400000 | ||
194 | #define BF_DMA_CHN_CM_DAI(v) (((v) & 0x1) << 22) | ||
195 | #define BFM_DMA_CHN_CM_DAI(v) BM_DMA_CHN_CM_DAI | ||
196 | #define BF_DMA_CHN_CM_DAI_V(e) BF_DMA_CHN_CM_DAI(BV_DMA_CHN_CM_DAI__##e) | ||
197 | #define BFM_DMA_CHN_CM_DAI_V(v) BM_DMA_CHN_CM_DAI | ||
198 | #define BP_DMA_CHN_CM_STDE 2 | ||
199 | #define BM_DMA_CHN_CM_STDE 0x4 | ||
200 | #define BF_DMA_CHN_CM_STDE(v) (((v) & 0x1) << 2) | ||
201 | #define BFM_DMA_CHN_CM_STDE(v) BM_DMA_CHN_CM_STDE | ||
202 | #define BF_DMA_CHN_CM_STDE_V(e) BF_DMA_CHN_CM_STDE(BV_DMA_CHN_CM_STDE__##e) | ||
203 | #define BFM_DMA_CHN_CM_STDE_V(v) BM_DMA_CHN_CM_STDE | ||
204 | #define BP_DMA_CHN_CM_TIE 1 | ||
205 | #define BM_DMA_CHN_CM_TIE 0x2 | ||
206 | #define BF_DMA_CHN_CM_TIE(v) (((v) & 0x1) << 1) | ||
207 | #define BFM_DMA_CHN_CM_TIE(v) BM_DMA_CHN_CM_TIE | ||
208 | #define BF_DMA_CHN_CM_TIE_V(e) BF_DMA_CHN_CM_TIE(BV_DMA_CHN_CM_TIE__##e) | ||
209 | #define BFM_DMA_CHN_CM_TIE_V(v) BM_DMA_CHN_CM_TIE | ||
210 | #define BP_DMA_CHN_CM_LINK 0 | ||
211 | #define BM_DMA_CHN_CM_LINK 0x1 | ||
212 | #define BF_DMA_CHN_CM_LINK(v) (((v) & 0x1) << 0) | ||
213 | #define BFM_DMA_CHN_CM_LINK(v) BM_DMA_CHN_CM_LINK | ||
214 | #define BF_DMA_CHN_CM_LINK_V(e) BF_DMA_CHN_CM_LINK(BV_DMA_CHN_CM_LINK__##e) | ||
215 | #define BFM_DMA_CHN_CM_LINK_V(v) BM_DMA_CHN_CM_LINK | ||
216 | |||
217 | #define REG_DMA_CHN_DA(_n1) jz_reg(DMA_CHN_DA(_n1)) | ||
218 | #define JA_DMA_CHN_DA(_n1) (0xb3420000 + (_n1) * 0x20 + 0x18) | ||
219 | #define JT_DMA_CHN_DA(_n1) JIO_32_RW | ||
220 | #define JN_DMA_CHN_DA(_n1) DMA_CHN_DA | ||
221 | #define JI_DMA_CHN_DA(_n1) (_n1) | ||
222 | #define BP_DMA_CHN_DA_DBA 12 | ||
223 | #define BM_DMA_CHN_DA_DBA 0xfffff000 | ||
224 | #define BF_DMA_CHN_DA_DBA(v) (((v) & 0xfffff) << 12) | ||
225 | #define BFM_DMA_CHN_DA_DBA(v) BM_DMA_CHN_DA_DBA | ||
226 | #define BF_DMA_CHN_DA_DBA_V(e) BF_DMA_CHN_DA_DBA(BV_DMA_CHN_DA_DBA__##e) | ||
227 | #define BFM_DMA_CHN_DA_DBA_V(v) BM_DMA_CHN_DA_DBA | ||
228 | #define BP_DMA_CHN_DA_DOA 4 | ||
229 | #define BM_DMA_CHN_DA_DOA 0xff0 | ||
230 | #define BF_DMA_CHN_DA_DOA(v) (((v) & 0xff) << 4) | ||
231 | #define BFM_DMA_CHN_DA_DOA(v) BM_DMA_CHN_DA_DOA | ||
232 | #define BF_DMA_CHN_DA_DOA_V(e) BF_DMA_CHN_DA_DOA(BV_DMA_CHN_DA_DOA__##e) | ||
233 | #define BFM_DMA_CHN_DA_DOA_V(v) BM_DMA_CHN_DA_DOA | ||
234 | |||
235 | #define REG_DMA_CHN_SD(_n1) jz_reg(DMA_CHN_SD(_n1)) | ||
236 | #define JA_DMA_CHN_SD(_n1) (0xb3420000 + (_n1) * 0x20 + 0x1c) | ||
237 | #define JT_DMA_CHN_SD(_n1) JIO_32_RW | ||
238 | #define JN_DMA_CHN_SD(_n1) DMA_CHN_SD | ||
239 | #define JI_DMA_CHN_SD(_n1) (_n1) | ||
240 | #define BP_DMA_CHN_SD_TSD 16 | ||
241 | #define BM_DMA_CHN_SD_TSD 0xffff0000 | ||
242 | #define BF_DMA_CHN_SD_TSD(v) (((v) & 0xffff) << 16) | ||
243 | #define BFM_DMA_CHN_SD_TSD(v) BM_DMA_CHN_SD_TSD | ||
244 | #define BF_DMA_CHN_SD_TSD_V(e) BF_DMA_CHN_SD_TSD(BV_DMA_CHN_SD_TSD__##e) | ||
245 | #define BFM_DMA_CHN_SD_TSD_V(v) BM_DMA_CHN_SD_TSD | ||
246 | #define BP_DMA_CHN_SD_SSD 0 | ||
247 | #define BM_DMA_CHN_SD_SSD 0xffff | ||
248 | #define BF_DMA_CHN_SD_SSD(v) (((v) & 0xffff) << 0) | ||
249 | #define BFM_DMA_CHN_SD_SSD(v) BM_DMA_CHN_SD_SSD | ||
250 | #define BF_DMA_CHN_SD_SSD_V(e) BF_DMA_CHN_SD_SSD(BV_DMA_CHN_SD_SSD__##e) | ||
251 | #define BFM_DMA_CHN_SD_SSD_V(v) BM_DMA_CHN_SD_SSD | ||
252 | |||
253 | #endif /* __HEADERGEN_DMA_CHN_H__*/ | ||