diff options
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/tcu.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/tcu.h | 192 |
1 files changed, 192 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/tcu.h b/firmware/target/mips/ingenic_x1000/x1000/tcu.h new file mode 100644 index 0000000000..9f00692660 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/tcu.h | |||
@@ -0,0 +1,192 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_TCU_H__ | ||
25 | #define __HEADERGEN_TCU_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_TCU_STATUS jz_reg(TCU_STATUS) | ||
30 | #define JA_TCU_STATUS (0xb0002000 + 0xf0) | ||
31 | #define JT_TCU_STATUS JIO_32_RW | ||
32 | #define JN_TCU_STATUS TCU_STATUS | ||
33 | #define JI_TCU_STATUS | ||
34 | #define REG_TCU_STATUS_SET jz_reg(TCU_STATUS_SET) | ||
35 | #define JA_TCU_STATUS_SET (JA_TCU_STATUS + 0x4) | ||
36 | #define JT_TCU_STATUS_SET JIO_32_WO | ||
37 | #define JN_TCU_STATUS_SET TCU_STATUS | ||
38 | #define JI_TCU_STATUS_SET | ||
39 | #define REG_TCU_STATUS_CLR jz_reg(TCU_STATUS_CLR) | ||
40 | #define JA_TCU_STATUS_CLR (JA_TCU_STATUS + 0x8) | ||
41 | #define JT_TCU_STATUS_CLR JIO_32_WO | ||
42 | #define JN_TCU_STATUS_CLR TCU_STATUS | ||
43 | #define JI_TCU_STATUS_CLR | ||
44 | |||
45 | #define REG_TCU_STOP jz_reg(TCU_STOP) | ||
46 | #define JA_TCU_STOP (0xb0002000 + 0x1c) | ||
47 | #define JT_TCU_STOP JIO_32_RW | ||
48 | #define JN_TCU_STOP TCU_STOP | ||
49 | #define JI_TCU_STOP | ||
50 | #define REG_TCU_STOP_SET jz_reg(TCU_STOP_SET) | ||
51 | #define JA_TCU_STOP_SET (JA_TCU_STOP + 0x10) | ||
52 | #define JT_TCU_STOP_SET JIO_32_WO | ||
53 | #define JN_TCU_STOP_SET TCU_STOP | ||
54 | #define JI_TCU_STOP_SET | ||
55 | #define REG_TCU_STOP_CLR jz_reg(TCU_STOP_CLR) | ||
56 | #define JA_TCU_STOP_CLR (JA_TCU_STOP + 0x20) | ||
57 | #define JT_TCU_STOP_CLR JIO_32_WO | ||
58 | #define JN_TCU_STOP_CLR TCU_STOP | ||
59 | #define JI_TCU_STOP_CLR | ||
60 | |||
61 | #define REG_TCU_ENABLE jz_reg(TCU_ENABLE) | ||
62 | #define JA_TCU_ENABLE (0xb0002000 + 0x10) | ||
63 | #define JT_TCU_ENABLE JIO_32_RW | ||
64 | #define JN_TCU_ENABLE TCU_ENABLE | ||
65 | #define JI_TCU_ENABLE | ||
66 | #define REG_TCU_ENABLE_SET jz_reg(TCU_ENABLE_SET) | ||
67 | #define JA_TCU_ENABLE_SET (JA_TCU_ENABLE + 0x4) | ||
68 | #define JT_TCU_ENABLE_SET JIO_32_WO | ||
69 | #define JN_TCU_ENABLE_SET TCU_ENABLE | ||
70 | #define JI_TCU_ENABLE_SET | ||
71 | #define REG_TCU_ENABLE_CLR jz_reg(TCU_ENABLE_CLR) | ||
72 | #define JA_TCU_ENABLE_CLR (JA_TCU_ENABLE + 0x8) | ||
73 | #define JT_TCU_ENABLE_CLR JIO_32_WO | ||
74 | #define JN_TCU_ENABLE_CLR TCU_ENABLE | ||
75 | #define JI_TCU_ENABLE_CLR | ||
76 | |||
77 | #define REG_TCU_FLAG jz_reg(TCU_FLAG) | ||
78 | #define JA_TCU_FLAG (0xb0002000 + 0x20) | ||
79 | #define JT_TCU_FLAG JIO_32_RW | ||
80 | #define JN_TCU_FLAG TCU_FLAG | ||
81 | #define JI_TCU_FLAG | ||
82 | #define REG_TCU_FLAG_SET jz_reg(TCU_FLAG_SET) | ||
83 | #define JA_TCU_FLAG_SET (JA_TCU_FLAG + 0x4) | ||
84 | #define JT_TCU_FLAG_SET JIO_32_WO | ||
85 | #define JN_TCU_FLAG_SET TCU_FLAG | ||
86 | #define JI_TCU_FLAG_SET | ||
87 | #define REG_TCU_FLAG_CLR jz_reg(TCU_FLAG_CLR) | ||
88 | #define JA_TCU_FLAG_CLR (JA_TCU_FLAG + 0x8) | ||
89 | #define JT_TCU_FLAG_CLR JIO_32_WO | ||
90 | #define JN_TCU_FLAG_CLR TCU_FLAG | ||
91 | #define JI_TCU_FLAG_CLR | ||
92 | |||
93 | #define REG_TCU_MASK jz_reg(TCU_MASK) | ||
94 | #define JA_TCU_MASK (0xb0002000 + 0x30) | ||
95 | #define JT_TCU_MASK JIO_32_RW | ||
96 | #define JN_TCU_MASK TCU_MASK | ||
97 | #define JI_TCU_MASK | ||
98 | #define REG_TCU_MASK_SET jz_reg(TCU_MASK_SET) | ||
99 | #define JA_TCU_MASK_SET (JA_TCU_MASK + 0x4) | ||
100 | #define JT_TCU_MASK_SET JIO_32_WO | ||
101 | #define JN_TCU_MASK_SET TCU_MASK | ||
102 | #define JI_TCU_MASK_SET | ||
103 | #define REG_TCU_MASK_CLR jz_reg(TCU_MASK_CLR) | ||
104 | #define JA_TCU_MASK_CLR (JA_TCU_MASK + 0x8) | ||
105 | #define JT_TCU_MASK_CLR JIO_32_WO | ||
106 | #define JN_TCU_MASK_CLR TCU_MASK | ||
107 | #define JI_TCU_MASK_CLR | ||
108 | |||
109 | #define REG_TCU_CMP_FULL(_n1) jz_reg(TCU_CMP_FULL(_n1)) | ||
110 | #define JA_TCU_CMP_FULL(_n1) (0xb0002000 + 0x40 + (_n1) * 0x10) | ||
111 | #define JT_TCU_CMP_FULL(_n1) JIO_32_RW | ||
112 | #define JN_TCU_CMP_FULL(_n1) TCU_CMP_FULL | ||
113 | #define JI_TCU_CMP_FULL(_n1) (_n1) | ||
114 | |||
115 | #define REG_TCU_CMP_HALF(_n1) jz_reg(TCU_CMP_HALF(_n1)) | ||
116 | #define JA_TCU_CMP_HALF(_n1) (0xb0002000 + 0x44 + (_n1) * 0x10) | ||
117 | #define JT_TCU_CMP_HALF(_n1) JIO_32_RW | ||
118 | #define JN_TCU_CMP_HALF(_n1) TCU_CMP_HALF | ||
119 | #define JI_TCU_CMP_HALF(_n1) (_n1) | ||
120 | |||
121 | #define REG_TCU_COUNT(_n1) jz_reg(TCU_COUNT(_n1)) | ||
122 | #define JA_TCU_COUNT(_n1) (0xb0002000 + 0x48 + (_n1) * 0x10) | ||
123 | #define JT_TCU_COUNT(_n1) JIO_32_RW | ||
124 | #define JN_TCU_COUNT(_n1) TCU_COUNT | ||
125 | #define JI_TCU_COUNT(_n1) (_n1) | ||
126 | |||
127 | #define REG_TCU_CTRL(_n1) jz_reg(TCU_CTRL(_n1)) | ||
128 | #define JA_TCU_CTRL(_n1) (0xb0002000 + 0x4c + (_n1) * 0x10) | ||
129 | #define JT_TCU_CTRL(_n1) JIO_32_RW | ||
130 | #define JN_TCU_CTRL(_n1) TCU_CTRL | ||
131 | #define JI_TCU_CTRL(_n1) (_n1) | ||
132 | #define BP_TCU_CTRL_PRESCALE 3 | ||
133 | #define BM_TCU_CTRL_PRESCALE 0x38 | ||
134 | #define BV_TCU_CTRL_PRESCALE__BY_1 0x0 | ||
135 | #define BV_TCU_CTRL_PRESCALE__BY_4 0x1 | ||
136 | #define BV_TCU_CTRL_PRESCALE__BY_16 0x2 | ||
137 | #define BV_TCU_CTRL_PRESCALE__BY_64 0x3 | ||
138 | #define BV_TCU_CTRL_PRESCALE__BY_256 0x4 | ||
139 | #define BV_TCU_CTRL_PRESCALE__BY_1024 0x5 | ||
140 | #define BF_TCU_CTRL_PRESCALE(v) (((v) & 0x7) << 3) | ||
141 | #define BFM_TCU_CTRL_PRESCALE(v) BM_TCU_CTRL_PRESCALE | ||
142 | #define BF_TCU_CTRL_PRESCALE_V(e) BF_TCU_CTRL_PRESCALE(BV_TCU_CTRL_PRESCALE__##e) | ||
143 | #define BFM_TCU_CTRL_PRESCALE_V(v) BM_TCU_CTRL_PRESCALE | ||
144 | #define BP_TCU_CTRL_SOURCE 0 | ||
145 | #define BM_TCU_CTRL_SOURCE 0x7 | ||
146 | #define BV_TCU_CTRL_SOURCE__EXT 0x4 | ||
147 | #define BV_TCU_CTRL_SOURCE__RTC 0x2 | ||
148 | #define BV_TCU_CTRL_SOURCE__PCLK 0x1 | ||
149 | #define BF_TCU_CTRL_SOURCE(v) (((v) & 0x7) << 0) | ||
150 | #define BFM_TCU_CTRL_SOURCE(v) BM_TCU_CTRL_SOURCE | ||
151 | #define BF_TCU_CTRL_SOURCE_V(e) BF_TCU_CTRL_SOURCE(BV_TCU_CTRL_SOURCE__##e) | ||
152 | #define BFM_TCU_CTRL_SOURCE_V(v) BM_TCU_CTRL_SOURCE | ||
153 | #define BP_TCU_CTRL_BYPASS 11 | ||
154 | #define BM_TCU_CTRL_BYPASS 0x800 | ||
155 | #define BF_TCU_CTRL_BYPASS(v) (((v) & 0x1) << 11) | ||
156 | #define BFM_TCU_CTRL_BYPASS(v) BM_TCU_CTRL_BYPASS | ||
157 | #define BF_TCU_CTRL_BYPASS_V(e) BF_TCU_CTRL_BYPASS(BV_TCU_CTRL_BYPASS__##e) | ||
158 | #define BFM_TCU_CTRL_BYPASS_V(v) BM_TCU_CTRL_BYPASS | ||
159 | #define BP_TCU_CTRL_CLRZ 10 | ||
160 | #define BM_TCU_CTRL_CLRZ 0x400 | ||
161 | #define BF_TCU_CTRL_CLRZ(v) (((v) & 0x1) << 10) | ||
162 | #define BFM_TCU_CTRL_CLRZ(v) BM_TCU_CTRL_CLRZ | ||
163 | #define BF_TCU_CTRL_CLRZ_V(e) BF_TCU_CTRL_CLRZ(BV_TCU_CTRL_CLRZ__##e) | ||
164 | #define BFM_TCU_CTRL_CLRZ_V(v) BM_TCU_CTRL_CLRZ | ||
165 | #define BP_TCU_CTRL_SHUTDOWN 9 | ||
166 | #define BM_TCU_CTRL_SHUTDOWN 0x200 | ||
167 | #define BV_TCU_CTRL_SHUTDOWN__GRACEFUL 0x0 | ||
168 | #define BV_TCU_CTRL_SHUTDOWN__ABRUPT 0x1 | ||
169 | #define BF_TCU_CTRL_SHUTDOWN(v) (((v) & 0x1) << 9) | ||
170 | #define BFM_TCU_CTRL_SHUTDOWN(v) BM_TCU_CTRL_SHUTDOWN | ||
171 | #define BF_TCU_CTRL_SHUTDOWN_V(e) BF_TCU_CTRL_SHUTDOWN(BV_TCU_CTRL_SHUTDOWN__##e) | ||
172 | #define BFM_TCU_CTRL_SHUTDOWN_V(v) BM_TCU_CTRL_SHUTDOWN | ||
173 | #define BP_TCU_CTRL_INIT_LVL 8 | ||
174 | #define BM_TCU_CTRL_INIT_LVL 0x100 | ||
175 | #define BF_TCU_CTRL_INIT_LVL(v) (((v) & 0x1) << 8) | ||
176 | #define BFM_TCU_CTRL_INIT_LVL(v) BM_TCU_CTRL_INIT_LVL | ||
177 | #define BF_TCU_CTRL_INIT_LVL_V(e) BF_TCU_CTRL_INIT_LVL(BV_TCU_CTRL_INIT_LVL__##e) | ||
178 | #define BFM_TCU_CTRL_INIT_LVL_V(v) BM_TCU_CTRL_INIT_LVL | ||
179 | #define BP_TCU_CTRL_PWM_EN 7 | ||
180 | #define BM_TCU_CTRL_PWM_EN 0x80 | ||
181 | #define BF_TCU_CTRL_PWM_EN(v) (((v) & 0x1) << 7) | ||
182 | #define BFM_TCU_CTRL_PWM_EN(v) BM_TCU_CTRL_PWM_EN | ||
183 | #define BF_TCU_CTRL_PWM_EN_V(e) BF_TCU_CTRL_PWM_EN(BV_TCU_CTRL_PWM_EN__##e) | ||
184 | #define BFM_TCU_CTRL_PWM_EN_V(v) BM_TCU_CTRL_PWM_EN | ||
185 | #define BP_TCU_CTRL_PWM_IN_EN 6 | ||
186 | #define BM_TCU_CTRL_PWM_IN_EN 0x40 | ||
187 | #define BF_TCU_CTRL_PWM_IN_EN(v) (((v) & 0x1) << 6) | ||
188 | #define BFM_TCU_CTRL_PWM_IN_EN(v) BM_TCU_CTRL_PWM_IN_EN | ||
189 | #define BF_TCU_CTRL_PWM_IN_EN_V(e) BF_TCU_CTRL_PWM_IN_EN(BV_TCU_CTRL_PWM_IN_EN__##e) | ||
190 | #define BFM_TCU_CTRL_PWM_IN_EN_V(v) BM_TCU_CTRL_PWM_IN_EN | ||
191 | |||
192 | #endif /* __HEADERGEN_TCU_H__*/ | ||