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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
| commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
| tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3700 | |
| parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
| download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip | |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700')
31 files changed, 13042 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h new file mode 100644 index 0000000000..fe654841af --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-apbh.h | |||
| @@ -0,0 +1,301 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__APBH__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__APBH__H__ | ||
| 25 | |||
| 26 | #define REGS_APBH_BASE (0x80004000) | ||
| 27 | |||
| 28 | #define REGS_APBH_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_APBH_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_APBH_CTRL0 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_APBH_CTRL0_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_APBH_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_APBH_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_APBH_CTRL0_SFTRST 31 | ||
| 40 | #define BM_APBH_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_APBH_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_APBH_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_APBH_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 | ||
| 46 | #define BM_APBH_CTRL0_RESET_CHANNEL 0xff0000 | ||
| 47 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP1 0x1 | ||
| 48 | #define BV_APBH_CTRL0_RESET_CHANNEL__SSP2 0x2 | ||
| 49 | #define BV_APBH_CTRL0_RESET_CHANNEL__LCDIF 0x4 | ||
| 50 | #define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 | ||
| 51 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 | ||
| 52 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 | ||
| 53 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x40 | ||
| 54 | #define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x80 | ||
| 55 | #define BF_APBH_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
| 56 | #define BF_APBH_CTRL0_RESET_CHANNEL_V(v) ((BV_APBH_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
| 57 | #define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 | ||
| 58 | #define BM_APBH_CTRL0_CLKGATE_CHANNEL 0xff00 | ||
| 59 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x1 | ||
| 60 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x2 | ||
| 61 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x4 | ||
| 62 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 | ||
| 63 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 | ||
| 64 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 | ||
| 65 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x40 | ||
| 66 | #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x80 | ||
| 67 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) << 8) & 0xff00) | ||
| 68 | #define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(v) ((BV_APBH_CTRL0_CLKGATE_CHANNEL__##v << 8) & 0xff00) | ||
| 69 | #define BP_APBH_CTRL0_FREEZE_CHANNEL 0 | ||
| 70 | #define BM_APBH_CTRL0_FREEZE_CHANNEL 0xff | ||
| 71 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1 0x1 | ||
| 72 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2 0x2 | ||
| 73 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__LCDIF 0x4 | ||
| 74 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 | ||
| 75 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 | ||
| 76 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 | ||
| 77 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x30 | ||
| 78 | #define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x40 | ||
| 79 | #define BF_APBH_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
| 80 | #define BF_APBH_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBH_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
| 81 | |||
| 82 | /** | ||
| 83 | * Register: HW_APBH_CTRL1 | ||
| 84 | * Address: 0x10 | ||
| 85 | * SCT: yes | ||
| 86 | */ | ||
| 87 | #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x0)) | ||
| 88 | #define HW_APBH_CTRL1_SET (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x4)) | ||
| 89 | #define HW_APBH_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0x8)) | ||
| 90 | #define HW_APBH_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBH_BASE + 0x10 + 0xc)) | ||
| 91 | #define BP_APBH_CTRL1_CH_AHB_ERROR_IRQ 16 | ||
| 92 | #define BM_APBH_CTRL1_CH_AHB_ERROR_IRQ 0xff0000 | ||
| 93 | #define BF_APBH_CTRL1_CH_AHB_ERROR_IRQ(v) (((v) << 16) & 0xff0000) | ||
| 94 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 8 | ||
| 95 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff00 | ||
| 96 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00) | ||
| 97 | #define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
| 98 | #define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
| 99 | #define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
| 100 | |||
| 101 | /** | ||
| 102 | * Register: HW_APBH_DEVSEL | ||
| 103 | * Address: 0x20 | ||
| 104 | * SCT: no | ||
| 105 | */ | ||
| 106 | #define HW_APBH_DEVSEL (*(volatile unsigned long *)(REGS_APBH_BASE + 0x20)) | ||
| 107 | #define BP_APBH_DEVSEL_CH7 28 | ||
| 108 | #define BM_APBH_DEVSEL_CH7 0xf0000000 | ||
| 109 | #define BF_APBH_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
| 110 | #define BP_APBH_DEVSEL_CH6 24 | ||
| 111 | #define BM_APBH_DEVSEL_CH6 0xf000000 | ||
| 112 | #define BF_APBH_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
| 113 | #define BP_APBH_DEVSEL_CH5 20 | ||
| 114 | #define BM_APBH_DEVSEL_CH5 0xf00000 | ||
| 115 | #define BF_APBH_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
| 116 | #define BP_APBH_DEVSEL_CH4 16 | ||
| 117 | #define BM_APBH_DEVSEL_CH4 0xf0000 | ||
| 118 | #define BF_APBH_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
| 119 | #define BP_APBH_DEVSEL_CH3 12 | ||
| 120 | #define BM_APBH_DEVSEL_CH3 0xf000 | ||
| 121 | #define BF_APBH_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
| 122 | #define BP_APBH_DEVSEL_CH2 8 | ||
| 123 | #define BM_APBH_DEVSEL_CH2 0xf00 | ||
| 124 | #define BF_APBH_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
| 125 | #define BP_APBH_DEVSEL_CH1 4 | ||
| 126 | #define BM_APBH_DEVSEL_CH1 0xf0 | ||
| 127 | #define BF_APBH_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
| 128 | #define BP_APBH_DEVSEL_CH0 0 | ||
| 129 | #define BM_APBH_DEVSEL_CH0 0xf | ||
| 130 | #define BF_APBH_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
| 131 | |||
| 132 | /** | ||
| 133 | * Register: HW_APBH_CHn_CURCMDAR | ||
| 134 | * Address: 0x40+n*0x70 | ||
| 135 | * SCT: no | ||
| 136 | */ | ||
| 137 | #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x40+(n)*0x70)) | ||
| 138 | #define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 | ||
| 139 | #define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
| 140 | #define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 141 | |||
| 142 | /** | ||
| 143 | * Register: HW_APBH_CHn_NXTCMDAR | ||
| 144 | * Address: 0x50+n*0x70 | ||
| 145 | * SCT: no | ||
| 146 | */ | ||
| 147 | #define HW_APBH_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x50+(n)*0x70)) | ||
| 148 | #define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 | ||
| 149 | #define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
| 150 | #define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 151 | |||
| 152 | /** | ||
| 153 | * Register: HW_APBH_CHn_CMD | ||
| 154 | * Address: 0x60+n*0x70 | ||
| 155 | * SCT: no | ||
| 156 | */ | ||
| 157 | #define HW_APBH_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x60+(n)*0x70)) | ||
| 158 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 | ||
| 159 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xffff0000 | ||
| 160 | #define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 161 | #define BP_APBH_CHn_CMD_CMDWORDS 12 | ||
| 162 | #define BM_APBH_CHn_CMD_CMDWORDS 0xf000 | ||
| 163 | #define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
| 164 | #define BP_APBH_CHn_CMD_HALTONTERMINATE 8 | ||
| 165 | #define BM_APBH_CHn_CMD_HALTONTERMINATE 0x100 | ||
| 166 | #define BF_APBH_CHn_CMD_HALTONTERMINATE(v) (((v) << 8) & 0x100) | ||
| 167 | #define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 | ||
| 168 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x80 | ||
| 169 | #define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
| 170 | #define BP_APBH_CHn_CMD_SEMAPHORE 6 | ||
| 171 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x40 | ||
| 172 | #define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
| 173 | #define BP_APBH_CHn_CMD_NANDWAIT4READY 5 | ||
| 174 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x20 | ||
| 175 | #define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) << 5) & 0x20) | ||
| 176 | #define BP_APBH_CHn_CMD_NANDLOCK 4 | ||
| 177 | #define BM_APBH_CHn_CMD_NANDLOCK 0x10 | ||
| 178 | #define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) << 4) & 0x10) | ||
| 179 | #define BP_APBH_CHn_CMD_IRQONCMPLT 3 | ||
| 180 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x8 | ||
| 181 | #define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
| 182 | #define BP_APBH_CHn_CMD_CHAIN 2 | ||
| 183 | #define BM_APBH_CHn_CMD_CHAIN 0x4 | ||
| 184 | #define BF_APBH_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
| 185 | #define BP_APBH_CHn_CMD_COMMAND 0 | ||
| 186 | #define BM_APBH_CHn_CMD_COMMAND 0x3 | ||
| 187 | #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
| 188 | #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
| 189 | #define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
| 190 | #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 | ||
| 191 | #define BF_APBH_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
| 192 | #define BF_APBH_CHn_CMD_COMMAND_V(v) ((BV_APBH_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
| 193 | |||
| 194 | /** | ||
| 195 | * Register: HW_APBH_CHn_BAR | ||
| 196 | * Address: 0x70+n*0x70 | ||
| 197 | * SCT: no | ||
| 198 | */ | ||
| 199 | #define HW_APBH_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x70+(n)*0x70)) | ||
| 200 | #define BP_APBH_CHn_BAR_ADDRESS 0 | ||
| 201 | #define BM_APBH_CHn_BAR_ADDRESS 0xffffffff | ||
| 202 | #define BF_APBH_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
| 203 | |||
| 204 | /** | ||
| 205 | * Register: HW_APBH_CHn_SEMA | ||
| 206 | * Address: 0x80+n*0x70 | ||
| 207 | * SCT: no | ||
| 208 | */ | ||
| 209 | #define HW_APBH_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x80+(n)*0x70)) | ||
| 210 | #define BP_APBH_CHn_SEMA_PHORE 16 | ||
| 211 | #define BM_APBH_CHn_SEMA_PHORE 0xff0000 | ||
| 212 | #define BF_APBH_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
| 213 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 | ||
| 214 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0xff | ||
| 215 | #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
| 216 | |||
| 217 | /** | ||
| 218 | * Register: HW_APBH_CHn_DEBUG1 | ||
| 219 | * Address: 0x90+n*0x70 | ||
| 220 | * SCT: no | ||
| 221 | */ | ||
| 222 | #define HW_APBH_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0x90+(n)*0x70)) | ||
| 223 | #define BP_APBH_CHn_DEBUG1_REQ 31 | ||
| 224 | #define BM_APBH_CHn_DEBUG1_REQ 0x80000000 | ||
| 225 | #define BF_APBH_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
| 226 | #define BP_APBH_CHn_DEBUG1_BURST 30 | ||
| 227 | #define BM_APBH_CHn_DEBUG1_BURST 0x40000000 | ||
| 228 | #define BF_APBH_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
| 229 | #define BP_APBH_CHn_DEBUG1_KICK 29 | ||
| 230 | #define BM_APBH_CHn_DEBUG1_KICK 0x20000000 | ||
| 231 | #define BF_APBH_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
| 232 | #define BP_APBH_CHn_DEBUG1_END 28 | ||
| 233 | #define BM_APBH_CHn_DEBUG1_END 0x10000000 | ||
| 234 | #define BF_APBH_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
| 235 | #define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
| 236 | #define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
| 237 | #define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
| 238 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
| 239 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
| 240 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
| 241 | #define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
| 242 | #define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
| 243 | #define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
| 244 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
| 245 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
| 246 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
| 247 | #define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
| 248 | #define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
| 249 | #define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
| 250 | #define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 | ||
| 251 | #define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x1f | ||
| 252 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
| 253 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
| 254 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
| 255 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
| 256 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
| 257 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
| 258 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
| 259 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
| 260 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
| 261 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
| 262 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
| 263 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
| 264 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
| 265 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
| 266 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
| 267 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
| 268 | #define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
| 269 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
| 270 | #define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBH_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
| 271 | |||
| 272 | /** | ||
| 273 | * Register: HW_APBH_CHn_DEBUG2 | ||
| 274 | * Address: 0xa0+n*0x70 | ||
| 275 | * SCT: no | ||
| 276 | */ | ||
| 277 | #define HW_APBH_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBH_BASE + 0xa0+(n)*0x70)) | ||
| 278 | #define BP_APBH_CHn_DEBUG2_APB_BYTES 16 | ||
| 279 | #define BM_APBH_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
| 280 | #define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
| 281 | #define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 | ||
| 282 | #define BM_APBH_CHn_DEBUG2_AHB_BYTES 0xffff | ||
| 283 | #define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
| 284 | |||
| 285 | /** | ||
| 286 | * Register: HW_APBH_VERSION | ||
| 287 | * Address: 0x3f0 | ||
| 288 | * SCT: no | ||
| 289 | */ | ||
| 290 | #define HW_APBH_VERSION (*(volatile unsigned long *)(REGS_APBH_BASE + 0x3f0)) | ||
| 291 | #define BP_APBH_VERSION_MAJOR 24 | ||
| 292 | #define BM_APBH_VERSION_MAJOR 0xff000000 | ||
| 293 | #define BF_APBH_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 294 | #define BP_APBH_VERSION_MINOR 16 | ||
| 295 | #define BM_APBH_VERSION_MINOR 0xff0000 | ||
| 296 | #define BF_APBH_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 297 | #define BP_APBH_VERSION_STEP 0 | ||
| 298 | #define BM_APBH_VERSION_STEP 0xffff | ||
| 299 | #define BF_APBH_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 300 | |||
| 301 | #endif /* __HEADERGEN__STMP3700__APBH__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h new file mode 100644 index 0000000000..5f93e5de3c --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-apbx.h | |||
| @@ -0,0 +1,294 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__APBX__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__APBX__H__ | ||
| 25 | |||
| 26 | #define REGS_APBX_BASE (0x80024000) | ||
| 27 | |||
| 28 | #define REGS_APBX_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_APBX_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_APBX_CTRL0 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_APBX_CTRL0_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_APBX_CTRL0_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_APBX_CTRL0_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_APBX_CTRL0_SFTRST 31 | ||
| 40 | #define BM_APBX_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_APBX_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_APBX_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_APBX_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_APBX_CTRL0_RESET_CHANNEL 16 | ||
| 46 | #define BM_APBX_CTRL0_RESET_CHANNEL 0xff0000 | ||
| 47 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOIN 0x1 | ||
| 48 | #define BV_APBX_CTRL0_RESET_CHANNEL__AUDIOOUT 0x2 | ||
| 49 | #define BV_APBX_CTRL0_RESET_CHANNEL__SPDIF_TX 0x4 | ||
| 50 | #define BV_APBX_CTRL0_RESET_CHANNEL__SAIF2 0x4 | ||
| 51 | #define BV_APBX_CTRL0_RESET_CHANNEL__I2C 0x8 | ||
| 52 | #define BV_APBX_CTRL0_RESET_CHANNEL__SAIF1 0x10 | ||
| 53 | #define BV_APBX_CTRL0_RESET_CHANNEL__DRI 0x20 | ||
| 54 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_RX 0x40 | ||
| 55 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_RX 0x40 | ||
| 56 | #define BV_APBX_CTRL0_RESET_CHANNEL__UART_TX 0x80 | ||
| 57 | #define BV_APBX_CTRL0_RESET_CHANNEL__IRDA_TX 0x80 | ||
| 58 | #define BF_APBX_CTRL0_RESET_CHANNEL(v) (((v) << 16) & 0xff0000) | ||
| 59 | #define BF_APBX_CTRL0_RESET_CHANNEL_V(v) ((BV_APBX_CTRL0_RESET_CHANNEL__##v << 16) & 0xff0000) | ||
| 60 | #define BP_APBX_CTRL0_FREEZE_CHANNEL 0 | ||
| 61 | #define BM_APBX_CTRL0_FREEZE_CHANNEL 0xff | ||
| 62 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOIN 0x1 | ||
| 63 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__AUDIOOUT 0x2 | ||
| 64 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SPDIF_TX 0x4 | ||
| 65 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF2 0x4 | ||
| 66 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__I2C 0x8 | ||
| 67 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__SAIF1 0x10 | ||
| 68 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__DRI 0x20 | ||
| 69 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_RX 0x40 | ||
| 70 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_RX 0x40 | ||
| 71 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__UART_TX 0x80 | ||
| 72 | #define BV_APBX_CTRL0_FREEZE_CHANNEL__IRDA_TX 0x80 | ||
| 73 | #define BF_APBX_CTRL0_FREEZE_CHANNEL(v) (((v) << 0) & 0xff) | ||
| 74 | #define BF_APBX_CTRL0_FREEZE_CHANNEL_V(v) ((BV_APBX_CTRL0_FREEZE_CHANNEL__##v << 0) & 0xff) | ||
| 75 | |||
| 76 | /** | ||
| 77 | * Register: HW_APBX_CTRL1 | ||
| 78 | * Address: 0x10 | ||
| 79 | * SCT: yes | ||
| 80 | */ | ||
| 81 | #define HW_APBX_CTRL1 (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x0)) | ||
| 82 | #define HW_APBX_CTRL1_SET (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x4)) | ||
| 83 | #define HW_APBX_CTRL1_CLR (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0x8)) | ||
| 84 | #define HW_APBX_CTRL1_TOG (*(volatile unsigned long *)(REGS_APBX_BASE + 0x10 + 0xc)) | ||
| 85 | #define BP_APBX_CTRL1_CH_AHB_ERROR_IRQ 16 | ||
| 86 | #define BM_APBX_CTRL1_CH_AHB_ERROR_IRQ 0xff0000 | ||
| 87 | #define BF_APBX_CTRL1_CH_AHB_ERROR_IRQ(v) (((v) << 16) & 0xff0000) | ||
| 88 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 8 | ||
| 89 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff00 | ||
| 90 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) << 8) & 0xff00) | ||
| 91 | #define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ 0 | ||
| 92 | #define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ 0xff | ||
| 93 | #define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) << 0) & 0xff) | ||
| 94 | |||
| 95 | /** | ||
| 96 | * Register: HW_APBX_DEVSEL | ||
| 97 | * Address: 0x20 | ||
| 98 | * SCT: no | ||
| 99 | */ | ||
| 100 | #define HW_APBX_DEVSEL (*(volatile unsigned long *)(REGS_APBX_BASE + 0x20)) | ||
| 101 | #define BP_APBX_DEVSEL_CH7 28 | ||
| 102 | #define BM_APBX_DEVSEL_CH7 0xf0000000 | ||
| 103 | #define BV_APBX_DEVSEL_CH7__USE_UART 0x0 | ||
| 104 | #define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 | ||
| 105 | #define BF_APBX_DEVSEL_CH7(v) (((v) << 28) & 0xf0000000) | ||
| 106 | #define BF_APBX_DEVSEL_CH7_V(v) ((BV_APBX_DEVSEL_CH7__##v << 28) & 0xf0000000) | ||
| 107 | #define BP_APBX_DEVSEL_CH6 24 | ||
| 108 | #define BM_APBX_DEVSEL_CH6 0xf000000 | ||
| 109 | #define BV_APBX_DEVSEL_CH6__USE_UART 0x0 | ||
| 110 | #define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 | ||
| 111 | #define BF_APBX_DEVSEL_CH6(v) (((v) << 24) & 0xf000000) | ||
| 112 | #define BF_APBX_DEVSEL_CH6_V(v) ((BV_APBX_DEVSEL_CH6__##v << 24) & 0xf000000) | ||
| 113 | #define BP_APBX_DEVSEL_CH5 20 | ||
| 114 | #define BM_APBX_DEVSEL_CH5 0xf00000 | ||
| 115 | #define BF_APBX_DEVSEL_CH5(v) (((v) << 20) & 0xf00000) | ||
| 116 | #define BP_APBX_DEVSEL_CH4 16 | ||
| 117 | #define BM_APBX_DEVSEL_CH4 0xf0000 | ||
| 118 | #define BF_APBX_DEVSEL_CH4(v) (((v) << 16) & 0xf0000) | ||
| 119 | #define BP_APBX_DEVSEL_CH3 12 | ||
| 120 | #define BM_APBX_DEVSEL_CH3 0xf000 | ||
| 121 | #define BF_APBX_DEVSEL_CH3(v) (((v) << 12) & 0xf000) | ||
| 122 | #define BP_APBX_DEVSEL_CH2 8 | ||
| 123 | #define BM_APBX_DEVSEL_CH2 0xf00 | ||
| 124 | #define BV_APBX_DEVSEL_CH2__USE_SPDIF 0x0 | ||
| 125 | #define BV_APBX_DEVSEL_CH2__USE_SAIF2 0x1 | ||
| 126 | #define BF_APBX_DEVSEL_CH2(v) (((v) << 8) & 0xf00) | ||
| 127 | #define BF_APBX_DEVSEL_CH2_V(v) ((BV_APBX_DEVSEL_CH2__##v << 8) & 0xf00) | ||
| 128 | #define BP_APBX_DEVSEL_CH1 4 | ||
| 129 | #define BM_APBX_DEVSEL_CH1 0xf0 | ||
| 130 | #define BF_APBX_DEVSEL_CH1(v) (((v) << 4) & 0xf0) | ||
| 131 | #define BP_APBX_DEVSEL_CH0 0 | ||
| 132 | #define BM_APBX_DEVSEL_CH0 0xf | ||
| 133 | #define BF_APBX_DEVSEL_CH0(v) (((v) << 0) & 0xf) | ||
| 134 | |||
| 135 | /** | ||
| 136 | * Register: HW_APBX_CHn_CURCMDAR | ||
| 137 | * Address: 0x40+n*0x70 | ||
| 138 | * SCT: no | ||
| 139 | */ | ||
| 140 | #define HW_APBX_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x40+(n)*0x70)) | ||
| 141 | #define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 | ||
| 142 | #define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xffffffff | ||
| 143 | #define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 144 | |||
| 145 | /** | ||
| 146 | * Register: HW_APBX_CHn_NXTCMDAR | ||
| 147 | * Address: 0x50+n*0x70 | ||
| 148 | * SCT: no | ||
| 149 | */ | ||
| 150 | #define HW_APBX_CHn_NXTCMDAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x50+(n)*0x70)) | ||
| 151 | #define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 | ||
| 152 | #define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xffffffff | ||
| 153 | #define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 154 | |||
| 155 | /** | ||
| 156 | * Register: HW_APBX_CHn_CMD | ||
| 157 | * Address: 0x60+n*0x70 | ||
| 158 | * SCT: no | ||
| 159 | */ | ||
| 160 | #define HW_APBX_CHn_CMD(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x60+(n)*0x70)) | ||
| 161 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 | ||
| 162 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xffff0000 | ||
| 163 | #define BF_APBX_CHn_CMD_XFER_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 164 | #define BP_APBX_CHn_CMD_CMDWORDS 12 | ||
| 165 | #define BM_APBX_CHn_CMD_CMDWORDS 0xf000 | ||
| 166 | #define BF_APBX_CHn_CMD_CMDWORDS(v) (((v) << 12) & 0xf000) | ||
| 167 | #define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 | ||
| 168 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x80 | ||
| 169 | #define BF_APBX_CHn_CMD_WAIT4ENDCMD(v) (((v) << 7) & 0x80) | ||
| 170 | #define BP_APBX_CHn_CMD_SEMAPHORE 6 | ||
| 171 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x40 | ||
| 172 | #define BF_APBX_CHn_CMD_SEMAPHORE(v) (((v) << 6) & 0x40) | ||
| 173 | #define BP_APBX_CHn_CMD_IRQONCMPLT 3 | ||
| 174 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x8 | ||
| 175 | #define BF_APBX_CHn_CMD_IRQONCMPLT(v) (((v) << 3) & 0x8) | ||
| 176 | #define BP_APBX_CHn_CMD_CHAIN 2 | ||
| 177 | #define BM_APBX_CHn_CMD_CHAIN 0x4 | ||
| 178 | #define BF_APBX_CHn_CMD_CHAIN(v) (((v) << 2) & 0x4) | ||
| 179 | #define BP_APBX_CHn_CMD_COMMAND 0 | ||
| 180 | #define BM_APBX_CHn_CMD_COMMAND 0x3 | ||
| 181 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 | ||
| 182 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 | ||
| 183 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 | ||
| 184 | #define BF_APBX_CHn_CMD_COMMAND(v) (((v) << 0) & 0x3) | ||
| 185 | #define BF_APBX_CHn_CMD_COMMAND_V(v) ((BV_APBX_CHn_CMD_COMMAND__##v << 0) & 0x3) | ||
| 186 | |||
| 187 | /** | ||
| 188 | * Register: HW_APBX_CHn_BAR | ||
| 189 | * Address: 0x70+n*0x70 | ||
| 190 | * SCT: no | ||
| 191 | */ | ||
| 192 | #define HW_APBX_CHn_BAR(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x70+(n)*0x70)) | ||
| 193 | #define BP_APBX_CHn_BAR_ADDRESS 0 | ||
| 194 | #define BM_APBX_CHn_BAR_ADDRESS 0xffffffff | ||
| 195 | #define BF_APBX_CHn_BAR_ADDRESS(v) (((v) << 0) & 0xffffffff) | ||
| 196 | |||
| 197 | /** | ||
| 198 | * Register: HW_APBX_CHn_SEMA | ||
| 199 | * Address: 0x80+n*0x70 | ||
| 200 | * SCT: no | ||
| 201 | */ | ||
| 202 | #define HW_APBX_CHn_SEMA(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x80+(n)*0x70)) | ||
| 203 | #define BP_APBX_CHn_SEMA_PHORE 16 | ||
| 204 | #define BM_APBX_CHn_SEMA_PHORE 0xff0000 | ||
| 205 | #define BF_APBX_CHn_SEMA_PHORE(v) (((v) << 16) & 0xff0000) | ||
| 206 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 | ||
| 207 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0xff | ||
| 208 | #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) (((v) << 0) & 0xff) | ||
| 209 | |||
| 210 | /** | ||
| 211 | * Register: HW_APBX_CHn_DEBUG1 | ||
| 212 | * Address: 0x90+n*0x70 | ||
| 213 | * SCT: no | ||
| 214 | */ | ||
| 215 | #define HW_APBX_CHn_DEBUG1(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0x90+(n)*0x70)) | ||
| 216 | #define BP_APBX_CHn_DEBUG1_REQ 31 | ||
| 217 | #define BM_APBX_CHn_DEBUG1_REQ 0x80000000 | ||
| 218 | #define BF_APBX_CHn_DEBUG1_REQ(v) (((v) << 31) & 0x80000000) | ||
| 219 | #define BP_APBX_CHn_DEBUG1_BURST 30 | ||
| 220 | #define BM_APBX_CHn_DEBUG1_BURST 0x40000000 | ||
| 221 | #define BF_APBX_CHn_DEBUG1_BURST(v) (((v) << 30) & 0x40000000) | ||
| 222 | #define BP_APBX_CHn_DEBUG1_KICK 29 | ||
| 223 | #define BM_APBX_CHn_DEBUG1_KICK 0x20000000 | ||
| 224 | #define BF_APBX_CHn_DEBUG1_KICK(v) (((v) << 29) & 0x20000000) | ||
| 225 | #define BP_APBX_CHn_DEBUG1_END 28 | ||
| 226 | #define BM_APBX_CHn_DEBUG1_END 0x10000000 | ||
| 227 | #define BF_APBX_CHn_DEBUG1_END(v) (((v) << 28) & 0x10000000) | ||
| 228 | #define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 24 | ||
| 229 | #define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 | ||
| 230 | #define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) << 24) & 0x1000000) | ||
| 231 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 23 | ||
| 232 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 | ||
| 233 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) << 23) & 0x800000) | ||
| 234 | #define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL 22 | ||
| 235 | #define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x400000 | ||
| 236 | #define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) << 22) & 0x400000) | ||
| 237 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 21 | ||
| 238 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 | ||
| 239 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) << 21) & 0x200000) | ||
| 240 | #define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL 20 | ||
| 241 | #define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x100000 | ||
| 242 | #define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) << 20) & 0x100000) | ||
| 243 | #define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 | ||
| 244 | #define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x1f | ||
| 245 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 | ||
| 246 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 | ||
| 247 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 | ||
| 248 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 | ||
| 249 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 | ||
| 250 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 | ||
| 251 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 | ||
| 252 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 | ||
| 253 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 | ||
| 254 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 | ||
| 255 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0xc | ||
| 256 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd | ||
| 257 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe | ||
| 258 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf | ||
| 259 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 | ||
| 260 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c | ||
| 261 | #define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e | ||
| 262 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) (((v) << 0) & 0x1f) | ||
| 263 | #define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(v) ((BV_APBX_CHn_DEBUG1_STATEMACHINE__##v << 0) & 0x1f) | ||
| 264 | |||
| 265 | /** | ||
| 266 | * Register: HW_APBX_CHn_DEBUG2 | ||
| 267 | * Address: 0xa0+n*0x70 | ||
| 268 | * SCT: no | ||
| 269 | */ | ||
| 270 | #define HW_APBX_CHn_DEBUG2(n) (*(volatile unsigned long *)(REGS_APBX_BASE + 0xa0+(n)*0x70)) | ||
| 271 | #define BP_APBX_CHn_DEBUG2_APB_BYTES 16 | ||
| 272 | #define BM_APBX_CHn_DEBUG2_APB_BYTES 0xffff0000 | ||
| 273 | #define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) << 16) & 0xffff0000) | ||
| 274 | #define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 | ||
| 275 | #define BM_APBX_CHn_DEBUG2_AHB_BYTES 0xffff | ||
| 276 | #define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) << 0) & 0xffff) | ||
| 277 | |||
| 278 | /** | ||
| 279 | * Register: HW_APBX_VERSION | ||
| 280 | * Address: 0x3f0 | ||
| 281 | * SCT: no | ||
| 282 | */ | ||
| 283 | #define HW_APBX_VERSION (*(volatile unsigned long *)(REGS_APBX_BASE + 0x3f0)) | ||
| 284 | #define BP_APBX_VERSION_MAJOR 24 | ||
| 285 | #define BM_APBX_VERSION_MAJOR 0xff000000 | ||
| 286 | #define BF_APBX_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 287 | #define BP_APBX_VERSION_MINOR 16 | ||
| 288 | #define BM_APBX_VERSION_MINOR 0xff0000 | ||
| 289 | #define BF_APBX_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 290 | #define BP_APBX_VERSION_STEP 0 | ||
| 291 | #define BM_APBX_VERSION_STEP 0xffff | ||
| 292 | #define BF_APBX_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 293 | |||
| 294 | #endif /* __HEADERGEN__STMP3700__APBX__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h new file mode 100644 index 0000000000..8bb4cb3e71 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-audioin.h | |||
| @@ -0,0 +1,284 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.4.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__AUDIOIN__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__AUDIOIN__H__ | ||
| 25 | |||
| 26 | #define REGS_AUDIOIN_BASE (0x8004c000) | ||
| 27 | |||
| 28 | #define REGS_AUDIOIN_VERSION "3.4.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_AUDIOIN_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_AUDIOIN_CTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_AUDIOIN_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_AUDIOIN_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_AUDIOIN_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_AUDIOIN_CTRL_SFTRST 31 | ||
| 40 | #define BM_AUDIOIN_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_AUDIOIN_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_AUDIOIN_CTRL_CLKGATE 30 | ||
| 43 | #define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_AUDIOIN_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 | ||
| 46 | #define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
| 47 | #define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 48 | #define BP_AUDIOIN_CTRL_LR_SWAP 10 | ||
| 49 | #define BM_AUDIOIN_CTRL_LR_SWAP 0x400 | ||
| 50 | #define BF_AUDIOIN_CTRL_LR_SWAP(v) (((v) << 10) & 0x400) | ||
| 51 | #define BP_AUDIOIN_CTRL_EDGE_SYNC 9 | ||
| 52 | #define BM_AUDIOIN_CTRL_EDGE_SYNC 0x200 | ||
| 53 | #define BF_AUDIOIN_CTRL_EDGE_SYNC(v) (((v) << 9) & 0x200) | ||
| 54 | #define BP_AUDIOIN_CTRL_INVERT_1BIT 8 | ||
| 55 | #define BM_AUDIOIN_CTRL_INVERT_1BIT 0x100 | ||
| 56 | #define BF_AUDIOIN_CTRL_INVERT_1BIT(v) (((v) << 8) & 0x100) | ||
| 57 | #define BP_AUDIOIN_CTRL_OFFSET_ENABLE 7 | ||
| 58 | #define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x80 | ||
| 59 | #define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v) (((v) << 7) & 0x80) | ||
| 60 | #define BP_AUDIOIN_CTRL_HPF_ENABLE 6 | ||
| 61 | #define BM_AUDIOIN_CTRL_HPF_ENABLE 0x40 | ||
| 62 | #define BF_AUDIOIN_CTRL_HPF_ENABLE(v) (((v) << 6) & 0x40) | ||
| 63 | #define BP_AUDIOIN_CTRL_WORD_LENGTH 5 | ||
| 64 | #define BM_AUDIOIN_CTRL_WORD_LENGTH 0x20 | ||
| 65 | #define BF_AUDIOIN_CTRL_WORD_LENGTH(v) (((v) << 5) & 0x20) | ||
| 66 | #define BP_AUDIOIN_CTRL_LOOPBACK 4 | ||
| 67 | #define BM_AUDIOIN_CTRL_LOOPBACK 0x10 | ||
| 68 | #define BF_AUDIOIN_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
| 69 | #define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
| 70 | #define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
| 71 | #define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 72 | #define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
| 73 | #define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
| 74 | #define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
| 75 | #define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
| 76 | #define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
| 77 | #define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 78 | #define BP_AUDIOIN_CTRL_RUN 0 | ||
| 79 | #define BM_AUDIOIN_CTRL_RUN 0x1 | ||
| 80 | #define BF_AUDIOIN_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 81 | |||
| 82 | /** | ||
| 83 | * Register: HW_AUDIOIN_STAT | ||
| 84 | * Address: 0x10 | ||
| 85 | * SCT: no | ||
| 86 | */ | ||
| 87 | #define HW_AUDIOIN_STAT (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x10)) | ||
| 88 | #define BP_AUDIOIN_STAT_ADC_PRESENT 31 | ||
| 89 | #define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 | ||
| 90 | #define BF_AUDIOIN_STAT_ADC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 91 | |||
| 92 | /** | ||
| 93 | * Register: HW_AUDIOIN_ADCSRR | ||
| 94 | * Address: 0x20 | ||
| 95 | * SCT: yes | ||
| 96 | */ | ||
| 97 | #define HW_AUDIOIN_ADCSRR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x0)) | ||
| 98 | #define HW_AUDIOIN_ADCSRR_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x4)) | ||
| 99 | #define HW_AUDIOIN_ADCSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0x8)) | ||
| 100 | #define HW_AUDIOIN_ADCSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x20 + 0xc)) | ||
| 101 | #define BP_AUDIOIN_ADCSRR_OSR 31 | ||
| 102 | #define BM_AUDIOIN_ADCSRR_OSR 0x80000000 | ||
| 103 | #define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 | ||
| 104 | #define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 | ||
| 105 | #define BF_AUDIOIN_ADCSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
| 106 | #define BF_AUDIOIN_ADCSRR_OSR_V(v) ((BV_AUDIOIN_ADCSRR_OSR__##v << 31) & 0x80000000) | ||
| 107 | #define BP_AUDIOIN_ADCSRR_BASEMULT 28 | ||
| 108 | #define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 | ||
| 109 | #define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 | ||
| 110 | #define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
| 111 | #define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 | ||
| 112 | #define BF_AUDIOIN_ADCSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
| 113 | #define BF_AUDIOIN_ADCSRR_BASEMULT_V(v) ((BV_AUDIOIN_ADCSRR_BASEMULT__##v << 28) & 0x70000000) | ||
| 114 | #define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 | ||
| 115 | #define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x7000000 | ||
| 116 | #define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
| 117 | #define BP_AUDIOIN_ADCSRR_SRC_INT 16 | ||
| 118 | #define BM_AUDIOIN_ADCSRR_SRC_INT 0x1f0000 | ||
| 119 | #define BF_AUDIOIN_ADCSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
| 120 | #define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 | ||
| 121 | #define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x1fff | ||
| 122 | #define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
| 123 | |||
| 124 | /** | ||
| 125 | * Register: HW_AUDIOIN_ADCVOLUME | ||
| 126 | * Address: 0x30 | ||
| 127 | * SCT: yes | ||
| 128 | */ | ||
| 129 | #define HW_AUDIOIN_ADCVOLUME (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x0)) | ||
| 130 | #define HW_AUDIOIN_ADCVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x4)) | ||
| 131 | #define HW_AUDIOIN_ADCVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0x8)) | ||
| 132 | #define HW_AUDIOIN_ADCVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x30 + 0xc)) | ||
| 133 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 28 | ||
| 134 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
| 135 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
| 136 | #define BP_AUDIOIN_ADCVOLUME_EN_ZCD 25 | ||
| 137 | #define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x2000000 | ||
| 138 | #define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
| 139 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 | ||
| 140 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0xff0000 | ||
| 141 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
| 142 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
| 143 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
| 144 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
| 145 | #define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 | ||
| 146 | #define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0xff | ||
| 147 | #define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_AUDIOIN_ADCDEBUG | ||
| 151 | * Address: 0x40 | ||
| 152 | * SCT: yes | ||
| 153 | */ | ||
| 154 | #define HW_AUDIOIN_ADCDEBUG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x0)) | ||
| 155 | #define HW_AUDIOIN_ADCDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x4)) | ||
| 156 | #define HW_AUDIOIN_ADCDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0x8)) | ||
| 157 | #define HW_AUDIOIN_ADCDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x40 + 0xc)) | ||
| 158 | #define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 31 | ||
| 159 | #define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 | ||
| 160 | #define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v) (((v) << 31) & 0x80000000) | ||
| 161 | #define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 3 | ||
| 162 | #define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x8 | ||
| 163 | #define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) << 3) & 0x8) | ||
| 164 | #define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 2 | ||
| 165 | #define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x4 | ||
| 166 | #define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
| 167 | #define BP_AUDIOIN_ADCDEBUG_DMA_PREQ 1 | ||
| 168 | #define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x2 | ||
| 169 | #define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
| 170 | #define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS 0 | ||
| 171 | #define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x1 | ||
| 172 | #define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
| 173 | |||
| 174 | /** | ||
| 175 | * Register: HW_AUDIOIN_ADCVOL | ||
| 176 | * Address: 0x50 | ||
| 177 | * SCT: yes | ||
| 178 | */ | ||
| 179 | #define HW_AUDIOIN_ADCVOL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x0)) | ||
| 180 | #define HW_AUDIOIN_ADCVOL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x4)) | ||
| 181 | #define HW_AUDIOIN_ADCVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0x8)) | ||
| 182 | #define HW_AUDIOIN_ADCVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x50 + 0xc)) | ||
| 183 | #define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 28 | ||
| 184 | #define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000 | ||
| 185 | #define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
| 186 | #define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD 25 | ||
| 187 | #define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x2000000 | ||
| 188 | #define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v) (((v) << 25) & 0x2000000) | ||
| 189 | #define BP_AUDIOIN_ADCVOL_MUTE 24 | ||
| 190 | #define BM_AUDIOIN_ADCVOL_MUTE 0x1000000 | ||
| 191 | #define BF_AUDIOIN_ADCVOL_MUTE(v) (((v) << 24) & 0x1000000) | ||
| 192 | #define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 | ||
| 193 | #define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x3000 | ||
| 194 | #define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) (((v) << 12) & 0x3000) | ||
| 195 | #define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 | ||
| 196 | #define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0xf00 | ||
| 197 | #define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) (((v) << 8) & 0xf00) | ||
| 198 | #define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 | ||
| 199 | #define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x30 | ||
| 200 | #define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) (((v) << 4) & 0x30) | ||
| 201 | #define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 | ||
| 202 | #define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0xf | ||
| 203 | #define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) (((v) << 0) & 0xf) | ||
| 204 | |||
| 205 | /** | ||
| 206 | * Register: HW_AUDIOIN_MICLINE | ||
| 207 | * Address: 0x60 | ||
| 208 | * SCT: yes | ||
| 209 | */ | ||
| 210 | #define HW_AUDIOIN_MICLINE (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x0)) | ||
| 211 | #define HW_AUDIOIN_MICLINE_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x4)) | ||
| 212 | #define HW_AUDIOIN_MICLINE_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0x8)) | ||
| 213 | #define HW_AUDIOIN_MICLINE_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x60 + 0xc)) | ||
| 214 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE1 29 | ||
| 215 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 | ||
| 216 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v) (((v) << 29) & 0x20000000) | ||
| 217 | #define BP_AUDIOIN_MICLINE_DIVIDE_LINE2 28 | ||
| 218 | #define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 | ||
| 219 | #define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v) (((v) << 28) & 0x10000000) | ||
| 220 | #define BP_AUDIOIN_MICLINE_MIC_SELECT 24 | ||
| 221 | #define BM_AUDIOIN_MICLINE_MIC_SELECT 0x1000000 | ||
| 222 | #define BF_AUDIOIN_MICLINE_MIC_SELECT(v) (((v) << 24) & 0x1000000) | ||
| 223 | #define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 | ||
| 224 | #define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x300000 | ||
| 225 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off 0x0 | ||
| 226 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm 0x1 | ||
| 227 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm 0x2 | ||
| 228 | #define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm 0x3 | ||
| 229 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) (((v) << 20) & 0x300000) | ||
| 230 | #define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(v) ((BV_AUDIOIN_MICLINE_MIC_RESISTOR__##v << 20) & 0x300000) | ||
| 231 | #define BP_AUDIOIN_MICLINE_MIC_BIAS 16 | ||
| 232 | #define BM_AUDIOIN_MICLINE_MIC_BIAS 0x70000 | ||
| 233 | #define BF_AUDIOIN_MICLINE_MIC_BIAS(v) (((v) << 16) & 0x70000) | ||
| 234 | #define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4 | ||
| 235 | #define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x30 | ||
| 236 | #define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) (((v) << 4) & 0x30) | ||
| 237 | #define BP_AUDIOIN_MICLINE_MIC_GAIN 0 | ||
| 238 | #define BM_AUDIOIN_MICLINE_MIC_GAIN 0x3 | ||
| 239 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB 0x0 | ||
| 240 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB 0x1 | ||
| 241 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB 0x2 | ||
| 242 | #define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB 0x3 | ||
| 243 | #define BF_AUDIOIN_MICLINE_MIC_GAIN(v) (((v) << 0) & 0x3) | ||
| 244 | #define BF_AUDIOIN_MICLINE_MIC_GAIN_V(v) ((BV_AUDIOIN_MICLINE_MIC_GAIN__##v << 0) & 0x3) | ||
| 245 | |||
| 246 | /** | ||
| 247 | * Register: HW_AUDIOIN_ANACLKCTRL | ||
| 248 | * Address: 0x70 | ||
| 249 | * SCT: yes | ||
| 250 | */ | ||
| 251 | #define HW_AUDIOIN_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x0)) | ||
| 252 | #define HW_AUDIOIN_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x4)) | ||
| 253 | #define HW_AUDIOIN_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0x8)) | ||
| 254 | #define HW_AUDIOIN_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x70 + 0xc)) | ||
| 255 | #define BP_AUDIOIN_ANACLKCTRL_CLKGATE 31 | ||
| 256 | #define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 | ||
| 257 | #define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 258 | #define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF 6 | ||
| 259 | #define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x40 | ||
| 260 | #define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v) (((v) << 6) & 0x40) | ||
| 261 | #define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER 5 | ||
| 262 | #define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x20 | ||
| 263 | #define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v) (((v) << 5) & 0x20) | ||
| 264 | #define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 4 | ||
| 265 | #define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x10 | ||
| 266 | #define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v) (((v) << 4) & 0x10) | ||
| 267 | #define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 | ||
| 268 | #define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x7 | ||
| 269 | #define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) (((v) << 0) & 0x7) | ||
| 270 | |||
| 271 | /** | ||
| 272 | * Register: HW_AUDIOIN_DATA | ||
| 273 | * Address: 0x80 | ||
| 274 | * SCT: no | ||
| 275 | */ | ||
| 276 | #define HW_AUDIOIN_DATA (*(volatile unsigned long *)(REGS_AUDIOIN_BASE + 0x80)) | ||
| 277 | #define BP_AUDIOIN_DATA_HIGH 16 | ||
| 278 | #define BM_AUDIOIN_DATA_HIGH 0xffff0000 | ||
| 279 | #define BF_AUDIOIN_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
| 280 | #define BP_AUDIOIN_DATA_LOW 0 | ||
| 281 | #define BM_AUDIOIN_DATA_LOW 0xffff | ||
| 282 | #define BF_AUDIOIN_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
| 283 | |||
| 284 | #endif /* __HEADERGEN__STMP3700__AUDIOIN__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h b/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h new file mode 100644 index 0000000000..c45ea1e0d0 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-audioout.h | |||
| @@ -0,0 +1,511 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__AUDIOOUT__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__AUDIOOUT__H__ | ||
| 25 | |||
| 26 | #define REGS_AUDIOOUT_BASE (0x80048000) | ||
| 27 | |||
| 28 | #define REGS_AUDIOOUT_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_AUDIOOUT_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_AUDIOOUT_CTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_AUDIOOUT_CTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_AUDIOOUT_CTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_AUDIOOUT_CTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_AUDIOOUT_CTRL_SFTRST 31 | ||
| 40 | #define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_AUDIOOUT_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_AUDIOOUT_CTRL_CLKGATE 30 | ||
| 43 | #define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_AUDIOOUT_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 | ||
| 46 | #define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
| 47 | #define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 48 | #define BP_AUDIOOUT_CTRL_LR_SWAP 14 | ||
| 49 | #define BM_AUDIOOUT_CTRL_LR_SWAP 0x4000 | ||
| 50 | #define BF_AUDIOOUT_CTRL_LR_SWAP(v) (((v) << 14) & 0x4000) | ||
| 51 | #define BP_AUDIOOUT_CTRL_EDGE_SYNC 13 | ||
| 52 | #define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x2000 | ||
| 53 | #define BF_AUDIOOUT_CTRL_EDGE_SYNC(v) (((v) << 13) & 0x2000) | ||
| 54 | #define BP_AUDIOOUT_CTRL_INVERT_1BIT 12 | ||
| 55 | #define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x1000 | ||
| 56 | #define BF_AUDIOOUT_CTRL_INVERT_1BIT(v) (((v) << 12) & 0x1000) | ||
| 57 | #define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 | ||
| 58 | #define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x300 | ||
| 59 | #define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) (((v) << 8) & 0x300) | ||
| 60 | #define BP_AUDIOOUT_CTRL_WORD_LENGTH 6 | ||
| 61 | #define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x40 | ||
| 62 | #define BF_AUDIOOUT_CTRL_WORD_LENGTH(v) (((v) << 6) & 0x40) | ||
| 63 | #define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 5 | ||
| 64 | #define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x20 | ||
| 65 | #define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v) (((v) << 5) & 0x20) | ||
| 66 | #define BP_AUDIOOUT_CTRL_LOOPBACK 4 | ||
| 67 | #define BM_AUDIOOUT_CTRL_LOOPBACK 0x10 | ||
| 68 | #define BF_AUDIOOUT_CTRL_LOOPBACK(v) (((v) << 4) & 0x10) | ||
| 69 | #define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
| 70 | #define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
| 71 | #define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 72 | #define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
| 73 | #define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
| 74 | #define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
| 75 | #define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
| 76 | #define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
| 77 | #define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 78 | #define BP_AUDIOOUT_CTRL_RUN 0 | ||
| 79 | #define BM_AUDIOOUT_CTRL_RUN 0x1 | ||
| 80 | #define BF_AUDIOOUT_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 81 | |||
| 82 | /** | ||
| 83 | * Register: HW_AUDIOOUT_STAT | ||
| 84 | * Address: 0x10 | ||
| 85 | * SCT: no | ||
| 86 | */ | ||
| 87 | #define HW_AUDIOOUT_STAT (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x10)) | ||
| 88 | #define BP_AUDIOOUT_STAT_DAC_PRESENT 31 | ||
| 89 | #define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 | ||
| 90 | #define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 91 | |||
| 92 | /** | ||
| 93 | * Register: HW_AUDIOOUT_DACSRR | ||
| 94 | * Address: 0x20 | ||
| 95 | * SCT: yes | ||
| 96 | */ | ||
| 97 | #define HW_AUDIOOUT_DACSRR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x0)) | ||
| 98 | #define HW_AUDIOOUT_DACSRR_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x4)) | ||
| 99 | #define HW_AUDIOOUT_DACSRR_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0x8)) | ||
| 100 | #define HW_AUDIOOUT_DACSRR_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x20 + 0xc)) | ||
| 101 | #define BP_AUDIOOUT_DACSRR_OSR 31 | ||
| 102 | #define BM_AUDIOOUT_DACSRR_OSR 0x80000000 | ||
| 103 | #define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 | ||
| 104 | #define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 | ||
| 105 | #define BF_AUDIOOUT_DACSRR_OSR(v) (((v) << 31) & 0x80000000) | ||
| 106 | #define BF_AUDIOOUT_DACSRR_OSR_V(v) ((BV_AUDIOOUT_DACSRR_OSR__##v << 31) & 0x80000000) | ||
| 107 | #define BP_AUDIOOUT_DACSRR_BASEMULT 28 | ||
| 108 | #define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 | ||
| 109 | #define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 | ||
| 110 | #define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 | ||
| 111 | #define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 | ||
| 112 | #define BF_AUDIOOUT_DACSRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
| 113 | #define BF_AUDIOOUT_DACSRR_BASEMULT_V(v) ((BV_AUDIOOUT_DACSRR_BASEMULT__##v << 28) & 0x70000000) | ||
| 114 | #define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 | ||
| 115 | #define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x7000000 | ||
| 116 | #define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) (((v) << 24) & 0x7000000) | ||
| 117 | #define BP_AUDIOOUT_DACSRR_SRC_INT 16 | ||
| 118 | #define BM_AUDIOOUT_DACSRR_SRC_INT 0x1f0000 | ||
| 119 | #define BF_AUDIOOUT_DACSRR_SRC_INT(v) (((v) << 16) & 0x1f0000) | ||
| 120 | #define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 | ||
| 121 | #define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x1fff | ||
| 122 | #define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) (((v) << 0) & 0x1fff) | ||
| 123 | |||
| 124 | /** | ||
| 125 | * Register: HW_AUDIOOUT_DACVOLUME | ||
| 126 | * Address: 0x30 | ||
| 127 | * SCT: yes | ||
| 128 | */ | ||
| 129 | #define HW_AUDIOOUT_DACVOLUME (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x0)) | ||
| 130 | #define HW_AUDIOOUT_DACVOLUME_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x4)) | ||
| 131 | #define HW_AUDIOOUT_DACVOLUME_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0x8)) | ||
| 132 | #define HW_AUDIOOUT_DACVOLUME_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x30 + 0xc)) | ||
| 133 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 28 | ||
| 134 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 | ||
| 135 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v) (((v) << 28) & 0x10000000) | ||
| 136 | #define BP_AUDIOOUT_DACVOLUME_EN_ZCD 25 | ||
| 137 | #define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x2000000 | ||
| 138 | #define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v) (((v) << 25) & 0x2000000) | ||
| 139 | #define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT 24 | ||
| 140 | #define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x1000000 | ||
| 141 | #define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v) (((v) << 24) & 0x1000000) | ||
| 142 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 | ||
| 143 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0xff0000 | ||
| 144 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) (((v) << 16) & 0xff0000) | ||
| 145 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 12 | ||
| 146 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x1000 | ||
| 147 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) << 12) & 0x1000) | ||
| 148 | #define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT 8 | ||
| 149 | #define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x100 | ||
| 150 | #define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v) (((v) << 8) & 0x100) | ||
| 151 | #define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 | ||
| 152 | #define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0xff | ||
| 153 | #define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) (((v) << 0) & 0xff) | ||
| 154 | |||
| 155 | /** | ||
| 156 | * Register: HW_AUDIOOUT_DACDEBUG | ||
| 157 | * Address: 0x40 | ||
| 158 | * SCT: yes | ||
| 159 | */ | ||
| 160 | #define HW_AUDIOOUT_DACDEBUG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x0)) | ||
| 161 | #define HW_AUDIOOUT_DACDEBUG_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x4)) | ||
| 162 | #define HW_AUDIOOUT_DACDEBUG_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0x8)) | ||
| 163 | #define HW_AUDIOOUT_DACDEBUG_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x40 + 0xc)) | ||
| 164 | #define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 31 | ||
| 165 | #define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 | ||
| 166 | #define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v) (((v) << 31) & 0x80000000) | ||
| 167 | #define BP_AUDIOOUT_DACDEBUG_RAM_SS 8 | ||
| 168 | #define BM_AUDIOOUT_DACDEBUG_RAM_SS 0xf00 | ||
| 169 | #define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) (((v) << 8) & 0xf00) | ||
| 170 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 5 | ||
| 171 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x20 | ||
| 172 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v) (((v) << 5) & 0x20) | ||
| 173 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 4 | ||
| 174 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x10 | ||
| 175 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v) (((v) << 4) & 0x10) | ||
| 176 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 3 | ||
| 177 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x8 | ||
| 178 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v) (((v) << 3) & 0x8) | ||
| 179 | #define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 2 | ||
| 180 | #define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x4 | ||
| 181 | #define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v) (((v) << 2) & 0x4) | ||
| 182 | #define BP_AUDIOOUT_DACDEBUG_DMA_PREQ 1 | ||
| 183 | #define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x2 | ||
| 184 | #define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
| 185 | #define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS 0 | ||
| 186 | #define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x1 | ||
| 187 | #define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
| 188 | |||
| 189 | /** | ||
| 190 | * Register: HW_AUDIOOUT_HPVOL | ||
| 191 | * Address: 0x50 | ||
| 192 | * SCT: yes | ||
| 193 | */ | ||
| 194 | #define HW_AUDIOOUT_HPVOL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x0)) | ||
| 195 | #define HW_AUDIOOUT_HPVOL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x4)) | ||
| 196 | #define HW_AUDIOOUT_HPVOL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0x8)) | ||
| 197 | #define HW_AUDIOOUT_HPVOL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x50 + 0xc)) | ||
| 198 | #define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 28 | ||
| 199 | #define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000 | ||
| 200 | #define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
| 201 | #define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD 25 | ||
| 202 | #define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x2000000 | ||
| 203 | #define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v) (((v) << 25) & 0x2000000) | ||
| 204 | #define BP_AUDIOOUT_HPVOL_MUTE 24 | ||
| 205 | #define BM_AUDIOOUT_HPVOL_MUTE 0x1000000 | ||
| 206 | #define BF_AUDIOOUT_HPVOL_MUTE(v) (((v) << 24) & 0x1000000) | ||
| 207 | #define BP_AUDIOOUT_HPVOL_SELECT 16 | ||
| 208 | #define BM_AUDIOOUT_HPVOL_SELECT 0x10000 | ||
| 209 | #define BF_AUDIOOUT_HPVOL_SELECT(v) (((v) << 16) & 0x10000) | ||
| 210 | #define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 | ||
| 211 | #define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x7f00 | ||
| 212 | #define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) (((v) << 8) & 0x7f00) | ||
| 213 | #define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 | ||
| 214 | #define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x7f | ||
| 215 | #define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) (((v) << 0) & 0x7f) | ||
| 216 | |||
| 217 | /** | ||
| 218 | * Register: HW_AUDIOOUT_RESERVED | ||
| 219 | * Address: 0x60 | ||
| 220 | * SCT: no | ||
| 221 | */ | ||
| 222 | #define HW_AUDIOOUT_RESERVED (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x60)) | ||
| 223 | |||
| 224 | /** | ||
| 225 | * Register: HW_AUDIOOUT_PWRDN | ||
| 226 | * Address: 0x70 | ||
| 227 | * SCT: yes | ||
| 228 | */ | ||
| 229 | #define HW_AUDIOOUT_PWRDN (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x0)) | ||
| 230 | #define HW_AUDIOOUT_PWRDN_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x4)) | ||
| 231 | #define HW_AUDIOOUT_PWRDN_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0x8)) | ||
| 232 | #define HW_AUDIOOUT_PWRDN_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x70 + 0xc)) | ||
| 233 | #define BP_AUDIOOUT_PWRDN_LINEOUT 24 | ||
| 234 | #define BM_AUDIOOUT_PWRDN_LINEOUT 0x1000000 | ||
| 235 | #define BF_AUDIOOUT_PWRDN_LINEOUT(v) (((v) << 24) & 0x1000000) | ||
| 236 | #define BP_AUDIOOUT_PWRDN_SELFBIAS 20 | ||
| 237 | #define BM_AUDIOOUT_PWRDN_SELFBIAS 0x100000 | ||
| 238 | #define BF_AUDIOOUT_PWRDN_SELFBIAS(v) (((v) << 20) & 0x100000) | ||
| 239 | #define BP_AUDIOOUT_PWRDN_RIGHT_ADC 16 | ||
| 240 | #define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x10000 | ||
| 241 | #define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v) (((v) << 16) & 0x10000) | ||
| 242 | #define BP_AUDIOOUT_PWRDN_DAC 12 | ||
| 243 | #define BM_AUDIOOUT_PWRDN_DAC 0x1000 | ||
| 244 | #define BF_AUDIOOUT_PWRDN_DAC(v) (((v) << 12) & 0x1000) | ||
| 245 | #define BP_AUDIOOUT_PWRDN_ADC 8 | ||
| 246 | #define BM_AUDIOOUT_PWRDN_ADC 0x100 | ||
| 247 | #define BF_AUDIOOUT_PWRDN_ADC(v) (((v) << 8) & 0x100) | ||
| 248 | #define BP_AUDIOOUT_PWRDN_CAPLESS 4 | ||
| 249 | #define BM_AUDIOOUT_PWRDN_CAPLESS 0x10 | ||
| 250 | #define BF_AUDIOOUT_PWRDN_CAPLESS(v) (((v) << 4) & 0x10) | ||
| 251 | #define BP_AUDIOOUT_PWRDN_HEADPHONE 0 | ||
| 252 | #define BM_AUDIOOUT_PWRDN_HEADPHONE 0x1 | ||
| 253 | #define BF_AUDIOOUT_PWRDN_HEADPHONE(v) (((v) << 0) & 0x1) | ||
| 254 | |||
| 255 | /** | ||
| 256 | * Register: HW_AUDIOOUT_REFCTRL | ||
| 257 | * Address: 0x80 | ||
| 258 | * SCT: yes | ||
| 259 | */ | ||
| 260 | #define HW_AUDIOOUT_REFCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x0)) | ||
| 261 | #define HW_AUDIOOUT_REFCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x4)) | ||
| 262 | #define HW_AUDIOOUT_REFCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0x8)) | ||
| 263 | #define HW_AUDIOOUT_REFCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x80 + 0xc)) | ||
| 264 | #define BP_AUDIOOUT_REFCTRL_FASTSETTLING 26 | ||
| 265 | #define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x4000000 | ||
| 266 | #define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v) (((v) << 26) & 0x4000000) | ||
| 267 | #define BP_AUDIOOUT_REFCTRL_RAISE_REF 25 | ||
| 268 | #define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x2000000 | ||
| 269 | #define BF_AUDIOOUT_REFCTRL_RAISE_REF(v) (((v) << 25) & 0x2000000) | ||
| 270 | #define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 24 | ||
| 271 | #define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x1000000 | ||
| 272 | #define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v) (((v) << 24) & 0x1000000) | ||
| 273 | #define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 | ||
| 274 | #define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x700000 | ||
| 275 | #define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) (((v) << 20) & 0x700000) | ||
| 276 | #define BP_AUDIOOUT_REFCTRL_LOW_PWR 19 | ||
| 277 | #define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x80000 | ||
| 278 | #define BF_AUDIOOUT_REFCTRL_LOW_PWR(v) (((v) << 19) & 0x80000) | ||
| 279 | #define BP_AUDIOOUT_REFCTRL_LW_REF 18 | ||
| 280 | #define BM_AUDIOOUT_REFCTRL_LW_REF 0x40000 | ||
| 281 | #define BF_AUDIOOUT_REFCTRL_LW_REF(v) (((v) << 18) & 0x40000) | ||
| 282 | #define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 | ||
| 283 | #define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x30000 | ||
| 284 | #define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) (((v) << 16) & 0x30000) | ||
| 285 | #define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 14 | ||
| 286 | #define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x4000 | ||
| 287 | #define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v) (((v) << 14) & 0x4000) | ||
| 288 | #define BP_AUDIOOUT_REFCTRL_ADJ_ADC 13 | ||
| 289 | #define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x2000 | ||
| 290 | #define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v) (((v) << 13) & 0x2000) | ||
| 291 | #define BP_AUDIOOUT_REFCTRL_ADJ_VAG 12 | ||
| 292 | #define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x1000 | ||
| 293 | #define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v) (((v) << 12) & 0x1000) | ||
| 294 | #define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 | ||
| 295 | #define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0xf00 | ||
| 296 | #define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) (((v) << 8) & 0xf00) | ||
| 297 | #define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 | ||
| 298 | #define BM_AUDIOOUT_REFCTRL_VAG_VAL 0xf0 | ||
| 299 | #define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) (((v) << 4) & 0xf0) | ||
| 300 | #define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 | ||
| 301 | #define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x7 | ||
| 302 | #define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) (((v) << 0) & 0x7) | ||
| 303 | |||
| 304 | /** | ||
| 305 | * Register: HW_AUDIOOUT_ANACTRL | ||
| 306 | * Address: 0x90 | ||
| 307 | * SCT: yes | ||
| 308 | */ | ||
| 309 | #define HW_AUDIOOUT_ANACTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x0)) | ||
| 310 | #define HW_AUDIOOUT_ANACTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x4)) | ||
| 311 | #define HW_AUDIOOUT_ANACTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0x8)) | ||
| 312 | #define HW_AUDIOOUT_ANACTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x90 + 0xc)) | ||
| 313 | #define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS 28 | ||
| 314 | #define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 | ||
| 315 | #define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v) (((v) << 28) & 0x10000000) | ||
| 316 | #define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS 24 | ||
| 317 | #define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x1000000 | ||
| 318 | #define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v) (((v) << 24) & 0x1000000) | ||
| 319 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 | ||
| 320 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x300000 | ||
| 321 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) (((v) << 20) & 0x300000) | ||
| 322 | #define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 | ||
| 323 | #define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x60000 | ||
| 324 | #define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) (((v) << 17) & 0x60000) | ||
| 325 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 | ||
| 326 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x7000 | ||
| 327 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) (((v) << 12) & 0x7000) | ||
| 328 | #define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 | ||
| 329 | #define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x700 | ||
| 330 | #define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) (((v) << 8) & 0x700) | ||
| 331 | #define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND 5 | ||
| 332 | #define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x20 | ||
| 333 | #define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v) (((v) << 5) & 0x20) | ||
| 334 | #define BP_AUDIOOUT_ANACTRL_HP_CLASSAB 4 | ||
| 335 | #define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x10 | ||
| 336 | #define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v) (((v) << 4) & 0x10) | ||
| 337 | |||
| 338 | /** | ||
| 339 | * Register: HW_AUDIOOUT_TEST | ||
| 340 | * Address: 0xa0 | ||
| 341 | * SCT: yes | ||
| 342 | */ | ||
| 343 | #define HW_AUDIOOUT_TEST (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x0)) | ||
| 344 | #define HW_AUDIOOUT_TEST_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x4)) | ||
| 345 | #define HW_AUDIOOUT_TEST_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0x8)) | ||
| 346 | #define HW_AUDIOOUT_TEST_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xa0 + 0xc)) | ||
| 347 | #define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 | ||
| 348 | #define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 | ||
| 349 | #define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) (((v) << 28) & 0x70000000) | ||
| 350 | #define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP 26 | ||
| 351 | #define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x4000000 | ||
| 352 | #define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v) (((v) << 26) & 0x4000000) | ||
| 353 | #define BP_AUDIOOUT_TEST_TM_LINEOUT 25 | ||
| 354 | #define BM_AUDIOOUT_TEST_TM_LINEOUT 0x2000000 | ||
| 355 | #define BF_AUDIOOUT_TEST_TM_LINEOUT(v) (((v) << 25) & 0x2000000) | ||
| 356 | #define BP_AUDIOOUT_TEST_TM_HPCOMMON 24 | ||
| 357 | #define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x1000000 | ||
| 358 | #define BF_AUDIOOUT_TEST_TM_HPCOMMON(v) (((v) << 24) & 0x1000000) | ||
| 359 | #define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 | ||
| 360 | #define BM_AUDIOOUT_TEST_HP_I1_ADJ 0xc00000 | ||
| 361 | #define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) (((v) << 22) & 0xc00000) | ||
| 362 | #define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 | ||
| 363 | #define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x300000 | ||
| 364 | #define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) (((v) << 20) & 0x300000) | ||
| 365 | #define BP_AUDIOOUT_TEST_VAG_CLASSA 13 | ||
| 366 | #define BM_AUDIOOUT_TEST_VAG_CLASSA 0x2000 | ||
| 367 | #define BF_AUDIOOUT_TEST_VAG_CLASSA(v) (((v) << 13) & 0x2000) | ||
| 368 | #define BP_AUDIOOUT_TEST_VAG_DOUBLE_I 12 | ||
| 369 | #define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x1000 | ||
| 370 | #define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v) (((v) << 12) & 0x1000) | ||
| 371 | #define BP_AUDIOOUT_TEST_DAC_CLASSA 2 | ||
| 372 | #define BM_AUDIOOUT_TEST_DAC_CLASSA 0x4 | ||
| 373 | #define BF_AUDIOOUT_TEST_DAC_CLASSA(v) (((v) << 2) & 0x4) | ||
| 374 | #define BP_AUDIOOUT_TEST_DAC_DOUBLE_I 1 | ||
| 375 | #define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x2 | ||
| 376 | #define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v) (((v) << 1) & 0x2) | ||
| 377 | #define BP_AUDIOOUT_TEST_DAC_DIS_RTZ 0 | ||
| 378 | #define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x1 | ||
| 379 | #define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v) (((v) << 0) & 0x1) | ||
| 380 | |||
| 381 | /** | ||
| 382 | * Register: HW_AUDIOOUT_BISTCTRL | ||
| 383 | * Address: 0xb0 | ||
| 384 | * SCT: yes | ||
| 385 | */ | ||
| 386 | #define HW_AUDIOOUT_BISTCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x0)) | ||
| 387 | #define HW_AUDIOOUT_BISTCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x4)) | ||
| 388 | #define HW_AUDIOOUT_BISTCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0x8)) | ||
| 389 | #define HW_AUDIOOUT_BISTCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xb0 + 0xc)) | ||
| 390 | #define BP_AUDIOOUT_BISTCTRL_FAIL 3 | ||
| 391 | #define BM_AUDIOOUT_BISTCTRL_FAIL 0x8 | ||
| 392 | #define BF_AUDIOOUT_BISTCTRL_FAIL(v) (((v) << 3) & 0x8) | ||
| 393 | #define BP_AUDIOOUT_BISTCTRL_PASS 2 | ||
| 394 | #define BM_AUDIOOUT_BISTCTRL_PASS 0x4 | ||
| 395 | #define BF_AUDIOOUT_BISTCTRL_PASS(v) (((v) << 2) & 0x4) | ||
| 396 | #define BP_AUDIOOUT_BISTCTRL_DONE 1 | ||
| 397 | #define BM_AUDIOOUT_BISTCTRL_DONE 0x2 | ||
| 398 | #define BF_AUDIOOUT_BISTCTRL_DONE(v) (((v) << 1) & 0x2) | ||
| 399 | #define BP_AUDIOOUT_BISTCTRL_START 0 | ||
| 400 | #define BM_AUDIOOUT_BISTCTRL_START 0x1 | ||
| 401 | #define BF_AUDIOOUT_BISTCTRL_START(v) (((v) << 0) & 0x1) | ||
| 402 | |||
| 403 | /** | ||
| 404 | * Register: HW_AUDIOOUT_BISTSTAT0 | ||
| 405 | * Address: 0xc0 | ||
| 406 | * SCT: no | ||
| 407 | */ | ||
| 408 | #define HW_AUDIOOUT_BISTSTAT0 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xc0)) | ||
| 409 | #define BP_AUDIOOUT_BISTSTAT0_DATA 0 | ||
| 410 | #define BM_AUDIOOUT_BISTSTAT0_DATA 0xffffff | ||
| 411 | #define BF_AUDIOOUT_BISTSTAT0_DATA(v) (((v) << 0) & 0xffffff) | ||
| 412 | |||
| 413 | /** | ||
| 414 | * Register: HW_AUDIOOUT_BISTSTAT1 | ||
| 415 | * Address: 0xd0 | ||
| 416 | * SCT: no | ||
| 417 | */ | ||
| 418 | #define HW_AUDIOOUT_BISTSTAT1 (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xd0)) | ||
| 419 | #define BP_AUDIOOUT_BISTSTAT1_STATE 24 | ||
| 420 | #define BM_AUDIOOUT_BISTSTAT1_STATE 0x1f000000 | ||
| 421 | #define BF_AUDIOOUT_BISTSTAT1_STATE(v) (((v) << 24) & 0x1f000000) | ||
| 422 | #define BP_AUDIOOUT_BISTSTAT1_ADDR 0 | ||
| 423 | #define BM_AUDIOOUT_BISTSTAT1_ADDR 0xff | ||
| 424 | #define BF_AUDIOOUT_BISTSTAT1_ADDR(v) (((v) << 0) & 0xff) | ||
| 425 | |||
| 426 | /** | ||
| 427 | * Register: HW_AUDIOOUT_ANACLKCTRL | ||
| 428 | * Address: 0xe0 | ||
| 429 | * SCT: yes | ||
| 430 | */ | ||
| 431 | #define HW_AUDIOOUT_ANACLKCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x0)) | ||
| 432 | #define HW_AUDIOOUT_ANACLKCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x4)) | ||
| 433 | #define HW_AUDIOOUT_ANACLKCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0x8)) | ||
| 434 | #define HW_AUDIOOUT_ANACLKCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xe0 + 0xc)) | ||
| 435 | #define BP_AUDIOOUT_ANACLKCTRL_CLKGATE 31 | ||
| 436 | #define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 | ||
| 437 | #define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 438 | #define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 4 | ||
| 439 | #define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x10 | ||
| 440 | #define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) << 4) & 0x10) | ||
| 441 | #define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 | ||
| 442 | #define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x7 | ||
| 443 | #define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) (((v) << 0) & 0x7) | ||
| 444 | |||
| 445 | /** | ||
| 446 | * Register: HW_AUDIOOUT_DATA | ||
| 447 | * Address: 0xf0 | ||
| 448 | * SCT: yes | ||
| 449 | */ | ||
| 450 | #define HW_AUDIOOUT_DATA (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x0)) | ||
| 451 | #define HW_AUDIOOUT_DATA_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x4)) | ||
| 452 | #define HW_AUDIOOUT_DATA_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0x8)) | ||
| 453 | #define HW_AUDIOOUT_DATA_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0xf0 + 0xc)) | ||
| 454 | #define BP_AUDIOOUT_DATA_HIGH 16 | ||
| 455 | #define BM_AUDIOOUT_DATA_HIGH 0xffff0000 | ||
| 456 | #define BF_AUDIOOUT_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
| 457 | #define BP_AUDIOOUT_DATA_LOW 0 | ||
| 458 | #define BM_AUDIOOUT_DATA_LOW 0xffff | ||
| 459 | #define BF_AUDIOOUT_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
| 460 | |||
| 461 | /** | ||
| 462 | * Register: HW_AUDIOOUT_LINEOUTCTRL | ||
| 463 | * Address: 0x100 | ||
| 464 | * SCT: yes | ||
| 465 | */ | ||
| 466 | #define HW_AUDIOOUT_LINEOUTCTRL (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x0)) | ||
| 467 | #define HW_AUDIOOUT_LINEOUTCTRL_SET (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x4)) | ||
| 468 | #define HW_AUDIOOUT_LINEOUTCTRL_CLR (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0x8)) | ||
| 469 | #define HW_AUDIOOUT_LINEOUTCTRL_TOG (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x100 + 0xc)) | ||
| 470 | #define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING 28 | ||
| 471 | #define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING 0x10000000 | ||
| 472 | #define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_UPDATE_PENDING(v) (((v) << 28) & 0x10000000) | ||
| 473 | #define BP_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD 25 | ||
| 474 | #define BM_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD 0x2000000 | ||
| 475 | #define BF_AUDIOOUT_LINEOUTCTRL_EN_LINEOUT_ZCD(v) (((v) << 25) & 0x2000000) | ||
| 476 | #define BP_AUDIOOUT_LINEOUTCTRL_MUTE 24 | ||
| 477 | #define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x1000000 | ||
| 478 | #define BF_AUDIOOUT_LINEOUTCTRL_MUTE(v) (((v) << 24) & 0x1000000) | ||
| 479 | #define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20 | ||
| 480 | #define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0xf00000 | ||
| 481 | #define BF_AUDIOOUT_LINEOUTCTRL_VAG_CTRL(v) (((v) << 20) & 0xf00000) | ||
| 482 | #define BP_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT 16 | ||
| 483 | #define BM_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT 0xf0000 | ||
| 484 | #define BF_AUDIOOUT_LINEOUTCTRL_OUT_CURRENT(v) (((v) << 16) & 0xf0000) | ||
| 485 | #define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 13 | ||
| 486 | #define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0xe000 | ||
| 487 | #define BF_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP(v) (((v) << 13) & 0xe000) | ||
| 488 | #define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT 8 | ||
| 489 | #define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT 0x1f00 | ||
| 490 | #define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_LEFT(v) (((v) << 8) & 0x1f00) | ||
| 491 | #define BP_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT 0 | ||
| 492 | #define BM_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT 0x1f | ||
| 493 | #define BF_AUDIOOUT_LINEOUTCTRL_VOLUME_RIGHT(v) (((v) << 0) & 0x1f) | ||
| 494 | |||
| 495 | /** | ||
| 496 | * Register: HW_AUDIOOUT_VERSION | ||
| 497 | * Address: 0x200 | ||
| 498 | * SCT: no | ||
| 499 | */ | ||
| 500 | #define HW_AUDIOOUT_VERSION (*(volatile unsigned long *)(REGS_AUDIOOUT_BASE + 0x200)) | ||
| 501 | #define BP_AUDIOOUT_VERSION_MAJOR 24 | ||
| 502 | #define BM_AUDIOOUT_VERSION_MAJOR 0xff000000 | ||
| 503 | #define BF_AUDIOOUT_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 504 | #define BP_AUDIOOUT_VERSION_MINOR 16 | ||
| 505 | #define BM_AUDIOOUT_VERSION_MINOR 0xff0000 | ||
| 506 | #define BF_AUDIOOUT_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 507 | #define BP_AUDIOOUT_VERSION_STEP 0 | ||
| 508 | #define BM_AUDIOOUT_VERSION_STEP 0xffff | ||
| 509 | #define BF_AUDIOOUT_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 510 | |||
| 511 | #endif /* __HEADERGEN__STMP3700__AUDIOOUT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h new file mode 100644 index 0000000000..0449161d11 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-clkctrl.h | |||
| @@ -0,0 +1,459 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__CLKCTRL__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__CLKCTRL__H__ | ||
| 25 | |||
| 26 | #define REGS_CLKCTRL_BASE (0x80040000) | ||
| 27 | |||
| 28 | #define REGS_CLKCTRL_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_CLKCTRL_PLLCTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_CLKCTRL_PLLCTRL0 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_CLKCTRL_PLLCTRL0_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_CLKCTRL_PLLCTRL0_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_CLKCTRL_PLLCTRL0_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 | ||
| 40 | #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 | ||
| 41 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 | ||
| 42 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 | ||
| 43 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 | ||
| 44 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 | ||
| 45 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) (((v) << 28) & 0x30000000) | ||
| 46 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_LFR_SEL__##v << 28) & 0x30000000) | ||
| 47 | #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 | ||
| 48 | #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x3000000 | ||
| 49 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 | ||
| 50 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 | ||
| 51 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 | ||
| 52 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 | ||
| 53 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) (((v) << 24) & 0x3000000) | ||
| 54 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_CP_SEL__##v << 24) & 0x3000000) | ||
| 55 | #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 | ||
| 56 | #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x300000 | ||
| 57 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 | ||
| 58 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 | ||
| 59 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 | ||
| 60 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 | ||
| 61 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) (((v) << 20) & 0x300000) | ||
| 62 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(v) ((BV_CLKCTRL_PLLCTRL0_DIV_SEL__##v << 20) & 0x300000) | ||
| 63 | #define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 | ||
| 64 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 | ||
| 65 | #define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) << 18) & 0x40000) | ||
| 66 | #define BP_CLKCTRL_PLLCTRL0_POWER 16 | ||
| 67 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 | ||
| 68 | #define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) << 16) & 0x10000) | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Register: HW_CLKCTRL_PLLCTRL1 | ||
| 72 | * Address: 0x10 | ||
| 73 | * SCT: no | ||
| 74 | */ | ||
| 75 | #define HW_CLKCTRL_PLLCTRL1 (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x10)) | ||
| 76 | #define BP_CLKCTRL_PLLCTRL1_LOCK 31 | ||
| 77 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
| 78 | #define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) << 31) & 0x80000000) | ||
| 79 | #define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 | ||
| 80 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
| 81 | #define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) << 30) & 0x40000000) | ||
| 82 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
| 83 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff | ||
| 84 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) << 0) & 0xffff) | ||
| 85 | |||
| 86 | /** | ||
| 87 | * Register: HW_CLKCTRL_CPU | ||
| 88 | * Address: 0x20 | ||
| 89 | * SCT: yes | ||
| 90 | */ | ||
| 91 | #define HW_CLKCTRL_CPU (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x0)) | ||
| 92 | #define HW_CLKCTRL_CPU_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x4)) | ||
| 93 | #define HW_CLKCTRL_CPU_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0x8)) | ||
| 94 | #define HW_CLKCTRL_CPU_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x20 + 0xc)) | ||
| 95 | #define BP_CLKCTRL_CPU_BUSY_REF_XTAL 29 | ||
| 96 | #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 | ||
| 97 | #define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
| 98 | #define BP_CLKCTRL_CPU_BUSY_REF_CPU 28 | ||
| 99 | #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 | ||
| 100 | #define BF_CLKCTRL_CPU_BUSY_REF_CPU(v) (((v) << 28) & 0x10000000) | ||
| 101 | #define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 26 | ||
| 102 | #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x4000000 | ||
| 103 | #define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) (((v) << 26) & 0x4000000) | ||
| 104 | #define BP_CLKCTRL_CPU_DIV_XTAL 16 | ||
| 105 | #define BM_CLKCTRL_CPU_DIV_XTAL 0x3ff0000 | ||
| 106 | #define BF_CLKCTRL_CPU_DIV_XTAL(v) (((v) << 16) & 0x3ff0000) | ||
| 107 | #define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 | ||
| 108 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 | ||
| 109 | #define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) << 12) & 0x1000) | ||
| 110 | #define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN 10 | ||
| 111 | #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x400 | ||
| 112 | #define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) (((v) << 10) & 0x400) | ||
| 113 | #define BP_CLKCTRL_CPU_DIV_CPU 0 | ||
| 114 | #define BM_CLKCTRL_CPU_DIV_CPU 0x3ff | ||
| 115 | #define BF_CLKCTRL_CPU_DIV_CPU(v) (((v) << 0) & 0x3ff) | ||
| 116 | |||
| 117 | /** | ||
| 118 | * Register: HW_CLKCTRL_HBUS | ||
| 119 | * Address: 0x30 | ||
| 120 | * SCT: yes | ||
| 121 | */ | ||
| 122 | #define HW_CLKCTRL_HBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x0)) | ||
| 123 | #define HW_CLKCTRL_HBUS_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x4)) | ||
| 124 | #define HW_CLKCTRL_HBUS_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0x8)) | ||
| 125 | #define HW_CLKCTRL_HBUS_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x30 + 0xc)) | ||
| 126 | #define BP_CLKCTRL_HBUS_BUSY 29 | ||
| 127 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
| 128 | #define BF_CLKCTRL_HBUS_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 129 | #define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 26 | ||
| 130 | #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x4000000 | ||
| 131 | #define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) (((v) << 26) & 0x4000000) | ||
| 132 | #define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 25 | ||
| 133 | #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x2000000 | ||
| 134 | #define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) (((v) << 25) & 0x2000000) | ||
| 135 | #define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 24 | ||
| 136 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x1000000 | ||
| 137 | #define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) (((v) << 24) & 0x1000000) | ||
| 138 | #define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 23 | ||
| 139 | #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x800000 | ||
| 140 | #define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) (((v) << 23) & 0x800000) | ||
| 141 | #define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 22 | ||
| 142 | #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x400000 | ||
| 143 | #define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) (((v) << 22) & 0x400000) | ||
| 144 | #define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 21 | ||
| 145 | #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x200000 | ||
| 146 | #define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) (((v) << 21) & 0x200000) | ||
| 147 | #define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 | ||
| 148 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 | ||
| 149 | #define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) << 20) & 0x100000) | ||
| 150 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
| 151 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x70000 | ||
| 152 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
| 153 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
| 154 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
| 155 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
| 156 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 | ||
| 157 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 | ||
| 158 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) << 16) & 0x70000) | ||
| 159 | #define BF_CLKCTRL_HBUS_SLOW_DIV_V(v) ((BV_CLKCTRL_HBUS_SLOW_DIV__##v << 16) & 0x70000) | ||
| 160 | #define BP_CLKCTRL_HBUS_DIV_FRAC_EN 5 | ||
| 161 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x20 | ||
| 162 | #define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v) (((v) << 5) & 0x20) | ||
| 163 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
| 164 | #define BM_CLKCTRL_HBUS_DIV 0x1f | ||
| 165 | #define BF_CLKCTRL_HBUS_DIV(v) (((v) << 0) & 0x1f) | ||
| 166 | |||
| 167 | /** | ||
| 168 | * Register: HW_CLKCTRL_XBUS | ||
| 169 | * Address: 0x40 | ||
| 170 | * SCT: no | ||
| 171 | */ | ||
| 172 | #define HW_CLKCTRL_XBUS (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x40)) | ||
| 173 | #define BP_CLKCTRL_XBUS_BUSY 31 | ||
| 174 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
| 175 | #define BF_CLKCTRL_XBUS_BUSY(v) (((v) << 31) & 0x80000000) | ||
| 176 | #define BP_CLKCTRL_XBUS_DIV_FRAC_EN 10 | ||
| 177 | #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x400 | ||
| 178 | #define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
| 179 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
| 180 | #define BM_CLKCTRL_XBUS_DIV 0x3ff | ||
| 181 | #define BF_CLKCTRL_XBUS_DIV(v) (((v) << 0) & 0x3ff) | ||
| 182 | |||
| 183 | /** | ||
| 184 | * Register: HW_CLKCTRL_XTAL | ||
| 185 | * Address: 0x50 | ||
| 186 | * SCT: yes | ||
| 187 | */ | ||
| 188 | #define HW_CLKCTRL_XTAL (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x0)) | ||
| 189 | #define HW_CLKCTRL_XTAL_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x4)) | ||
| 190 | #define HW_CLKCTRL_XTAL_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0x8)) | ||
| 191 | #define HW_CLKCTRL_XTAL_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x50 + 0xc)) | ||
| 192 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
| 193 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
| 194 | #define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) << 31) & 0x80000000) | ||
| 195 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
| 196 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
| 197 | #define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) << 30) & 0x40000000) | ||
| 198 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
| 199 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
| 200 | #define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) << 29) & 0x20000000) | ||
| 201 | #define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 | ||
| 202 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
| 203 | #define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) << 28) & 0x10000000) | ||
| 204 | #define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 | ||
| 205 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 | ||
| 206 | #define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) << 27) & 0x8000000) | ||
| 207 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
| 208 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 | ||
| 209 | #define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) << 26) & 0x4000000) | ||
| 210 | #define BP_CLKCTRL_XTAL_DIV_UART 0 | ||
| 211 | #define BM_CLKCTRL_XTAL_DIV_UART 0x3 | ||
| 212 | #define BF_CLKCTRL_XTAL_DIV_UART(v) (((v) << 0) & 0x3) | ||
| 213 | |||
| 214 | /** | ||
| 215 | * Register: HW_CLKCTRL_PIX | ||
| 216 | * Address: 0x60 | ||
| 217 | * SCT: no | ||
| 218 | */ | ||
| 219 | #define HW_CLKCTRL_PIX (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x60)) | ||
| 220 | #define BP_CLKCTRL_PIX_CLKGATE 31 | ||
| 221 | #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 | ||
| 222 | #define BF_CLKCTRL_PIX_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 223 | #define BP_CLKCTRL_PIX_BUSY 29 | ||
| 224 | #define BM_CLKCTRL_PIX_BUSY 0x20000000 | ||
| 225 | #define BF_CLKCTRL_PIX_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 226 | #define BP_CLKCTRL_PIX_DIV_FRAC_EN 15 | ||
| 227 | #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x8000 | ||
| 228 | #define BF_CLKCTRL_PIX_DIV_FRAC_EN(v) (((v) << 15) & 0x8000) | ||
| 229 | #define BP_CLKCTRL_PIX_DIV 0 | ||
| 230 | #define BM_CLKCTRL_PIX_DIV 0x7fff | ||
| 231 | #define BF_CLKCTRL_PIX_DIV(v) (((v) << 0) & 0x7fff) | ||
| 232 | |||
| 233 | /** | ||
| 234 | * Register: HW_CLKCTRL_SSP | ||
| 235 | * Address: 0x70 | ||
| 236 | * SCT: no | ||
| 237 | */ | ||
| 238 | #define HW_CLKCTRL_SSP (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x70)) | ||
| 239 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
| 240 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
| 241 | #define BF_CLKCTRL_SSP_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 242 | #define BP_CLKCTRL_SSP_BUSY 29 | ||
| 243 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
| 244 | #define BF_CLKCTRL_SSP_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 245 | #define BP_CLKCTRL_SSP_DIV_FRAC_EN 9 | ||
| 246 | #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x200 | ||
| 247 | #define BF_CLKCTRL_SSP_DIV_FRAC_EN(v) (((v) << 9) & 0x200) | ||
| 248 | #define BP_CLKCTRL_SSP_DIV 0 | ||
| 249 | #define BM_CLKCTRL_SSP_DIV 0x1ff | ||
| 250 | #define BF_CLKCTRL_SSP_DIV(v) (((v) << 0) & 0x1ff) | ||
| 251 | |||
| 252 | /** | ||
| 253 | * Register: HW_CLKCTRL_GPMI | ||
| 254 | * Address: 0x80 | ||
| 255 | * SCT: no | ||
| 256 | */ | ||
| 257 | #define HW_CLKCTRL_GPMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x80)) | ||
| 258 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
| 259 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
| 260 | #define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 261 | #define BP_CLKCTRL_GPMI_BUSY 29 | ||
| 262 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
| 263 | #define BF_CLKCTRL_GPMI_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 264 | #define BP_CLKCTRL_GPMI_DIV_FRAC_EN 10 | ||
| 265 | #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x400 | ||
| 266 | #define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v) (((v) << 10) & 0x400) | ||
| 267 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
| 268 | #define BM_CLKCTRL_GPMI_DIV 0x3ff | ||
| 269 | #define BF_CLKCTRL_GPMI_DIV(v) (((v) << 0) & 0x3ff) | ||
| 270 | |||
| 271 | /** | ||
| 272 | * Register: HW_CLKCTRL_SPDIF | ||
| 273 | * Address: 0x90 | ||
| 274 | * SCT: no | ||
| 275 | */ | ||
| 276 | #define HW_CLKCTRL_SPDIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x90)) | ||
| 277 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
| 278 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
| 279 | #define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 280 | |||
| 281 | /** | ||
| 282 | * Register: HW_CLKCTRL_EMI | ||
| 283 | * Address: 0xa0 | ||
| 284 | * SCT: no | ||
| 285 | */ | ||
| 286 | #define HW_CLKCTRL_EMI (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xa0)) | ||
| 287 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
| 288 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
| 289 | #define BF_CLKCTRL_EMI_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 290 | #define BP_CLKCTRL_EMI_BUSY_REF_XTAL 29 | ||
| 291 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 | ||
| 292 | #define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v) (((v) << 29) & 0x20000000) | ||
| 293 | #define BP_CLKCTRL_EMI_BUSY_REF_EMI 28 | ||
| 294 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 | ||
| 295 | #define BF_CLKCTRL_EMI_BUSY_REF_EMI(v) (((v) << 28) & 0x10000000) | ||
| 296 | #define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC 17 | ||
| 297 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x20000 | ||
| 298 | #define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) (((v) << 17) & 0x20000) | ||
| 299 | #define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE 16 | ||
| 300 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x10000 | ||
| 301 | #define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 302 | #define BP_CLKCTRL_EMI_DIV_XTAL 8 | ||
| 303 | #define BM_CLKCTRL_EMI_DIV_XTAL 0xf00 | ||
| 304 | #define BF_CLKCTRL_EMI_DIV_XTAL(v) (((v) << 8) & 0xf00) | ||
| 305 | #define BP_CLKCTRL_EMI_DIV_EMI 0 | ||
| 306 | #define BM_CLKCTRL_EMI_DIV_EMI 0x3f | ||
| 307 | #define BF_CLKCTRL_EMI_DIV_EMI(v) (((v) << 0) & 0x3f) | ||
| 308 | |||
| 309 | /** | ||
| 310 | * Register: HW_CLKCTRL_IR | ||
| 311 | * Address: 0xb0 | ||
| 312 | * SCT: no | ||
| 313 | */ | ||
| 314 | #define HW_CLKCTRL_IR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xb0)) | ||
| 315 | #define BP_CLKCTRL_IR_CLKGATE 31 | ||
| 316 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
| 317 | #define BF_CLKCTRL_IR_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 318 | #define BP_CLKCTRL_IR_AUTO_DIV 29 | ||
| 319 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
| 320 | #define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) << 29) & 0x20000000) | ||
| 321 | #define BP_CLKCTRL_IR_IR_BUSY 28 | ||
| 322 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
| 323 | #define BF_CLKCTRL_IR_IR_BUSY(v) (((v) << 28) & 0x10000000) | ||
| 324 | #define BP_CLKCTRL_IR_IROV_BUSY 27 | ||
| 325 | #define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 | ||
| 326 | #define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) << 27) & 0x8000000) | ||
| 327 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
| 328 | #define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 | ||
| 329 | #define BF_CLKCTRL_IR_IROV_DIV(v) (((v) << 16) & 0x1ff0000) | ||
| 330 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
| 331 | #define BM_CLKCTRL_IR_IR_DIV 0x3ff | ||
| 332 | #define BF_CLKCTRL_IR_IR_DIV(v) (((v) << 0) & 0x3ff) | ||
| 333 | |||
| 334 | /** | ||
| 335 | * Register: HW_CLKCTRL_SAIF | ||
| 336 | * Address: 0xc0 | ||
| 337 | * SCT: no | ||
| 338 | */ | ||
| 339 | #define HW_CLKCTRL_SAIF (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xc0)) | ||
| 340 | #define BP_CLKCTRL_SAIF_CLKGATE 31 | ||
| 341 | #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 | ||
| 342 | #define BF_CLKCTRL_SAIF_CLKGATE(v) (((v) << 31) & 0x80000000) | ||
| 343 | #define BP_CLKCTRL_SAIF_BUSY 29 | ||
| 344 | #define BM_CLKCTRL_SAIF_BUSY 0x20000000 | ||
| 345 | #define BF_CLKCTRL_SAIF_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 346 | #define BP_CLKCTRL_SAIF_DIV_FRAC_EN 16 | ||
| 347 | #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x10000 | ||
| 348 | #define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v) (((v) << 16) & 0x10000) | ||
| 349 | #define BP_CLKCTRL_SAIF_DIV 0 | ||
| 350 | #define BM_CLKCTRL_SAIF_DIV 0xffff | ||
| 351 | #define BF_CLKCTRL_SAIF_DIV(v) (((v) << 0) & 0xffff) | ||
| 352 | |||
| 353 | /** | ||
| 354 | * Register: HW_CLKCTRL_FRAC | ||
| 355 | * Address: 0xd0 | ||
| 356 | * SCT: yes | ||
| 357 | */ | ||
| 358 | #define HW_CLKCTRL_FRAC (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x0)) | ||
| 359 | #define HW_CLKCTRL_FRAC_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x4)) | ||
| 360 | #define HW_CLKCTRL_FRAC_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0x8)) | ||
| 361 | #define HW_CLKCTRL_FRAC_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xd0 + 0xc)) | ||
| 362 | #define BP_CLKCTRL_FRAC_CLKGATEIO 31 | ||
| 363 | #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 | ||
| 364 | #define BF_CLKCTRL_FRAC_CLKGATEIO(v) (((v) << 31) & 0x80000000) | ||
| 365 | #define BP_CLKCTRL_FRAC_IO_STABLE 30 | ||
| 366 | #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 | ||
| 367 | #define BF_CLKCTRL_FRAC_IO_STABLE(v) (((v) << 30) & 0x40000000) | ||
| 368 | #define BP_CLKCTRL_FRAC_IOFRAC 24 | ||
| 369 | #define BM_CLKCTRL_FRAC_IOFRAC 0x3f000000 | ||
| 370 | #define BF_CLKCTRL_FRAC_IOFRAC(v) (((v) << 24) & 0x3f000000) | ||
| 371 | #define BP_CLKCTRL_FRAC_CLKGATEPIX 23 | ||
| 372 | #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x800000 | ||
| 373 | #define BF_CLKCTRL_FRAC_CLKGATEPIX(v) (((v) << 23) & 0x800000) | ||
| 374 | #define BP_CLKCTRL_FRAC_PIX_STABLE 22 | ||
| 375 | #define BM_CLKCTRL_FRAC_PIX_STABLE 0x400000 | ||
| 376 | #define BF_CLKCTRL_FRAC_PIX_STABLE(v) (((v) << 22) & 0x400000) | ||
| 377 | #define BP_CLKCTRL_FRAC_PIXFRAC 16 | ||
| 378 | #define BM_CLKCTRL_FRAC_PIXFRAC 0x3f0000 | ||
| 379 | #define BF_CLKCTRL_FRAC_PIXFRAC(v) (((v) << 16) & 0x3f0000) | ||
| 380 | #define BP_CLKCTRL_FRAC_CLKGATEEMI 15 | ||
| 381 | #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x8000 | ||
| 382 | #define BF_CLKCTRL_FRAC_CLKGATEEMI(v) (((v) << 15) & 0x8000) | ||
| 383 | #define BP_CLKCTRL_FRAC_EMI_STABLE 14 | ||
| 384 | #define BM_CLKCTRL_FRAC_EMI_STABLE 0x4000 | ||
| 385 | #define BF_CLKCTRL_FRAC_EMI_STABLE(v) (((v) << 14) & 0x4000) | ||
| 386 | #define BP_CLKCTRL_FRAC_EMIFRAC 8 | ||
| 387 | #define BM_CLKCTRL_FRAC_EMIFRAC 0x3f00 | ||
| 388 | #define BF_CLKCTRL_FRAC_EMIFRAC(v) (((v) << 8) & 0x3f00) | ||
| 389 | #define BP_CLKCTRL_FRAC_CLKGATECPU 7 | ||
| 390 | #define BM_CLKCTRL_FRAC_CLKGATECPU 0x80 | ||
| 391 | #define BF_CLKCTRL_FRAC_CLKGATECPU(v) (((v) << 7) & 0x80) | ||
| 392 | #define BP_CLKCTRL_FRAC_CPU_STABLE 6 | ||
| 393 | #define BM_CLKCTRL_FRAC_CPU_STABLE 0x40 | ||
| 394 | #define BF_CLKCTRL_FRAC_CPU_STABLE(v) (((v) << 6) & 0x40) | ||
| 395 | #define BP_CLKCTRL_FRAC_CPUFRAC 0 | ||
| 396 | #define BM_CLKCTRL_FRAC_CPUFRAC 0x3f | ||
| 397 | #define BF_CLKCTRL_FRAC_CPUFRAC(v) (((v) << 0) & 0x3f) | ||
| 398 | |||
| 399 | /** | ||
| 400 | * Register: HW_CLKCTRL_CLKSEQ | ||
| 401 | * Address: 0xe0 | ||
| 402 | * SCT: yes | ||
| 403 | */ | ||
| 404 | #define HW_CLKCTRL_CLKSEQ (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x0)) | ||
| 405 | #define HW_CLKCTRL_CLKSEQ_SET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x4)) | ||
| 406 | #define HW_CLKCTRL_CLKSEQ_CLR (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0x8)) | ||
| 407 | #define HW_CLKCTRL_CLKSEQ_TOG (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xe0 + 0xc)) | ||
| 408 | #define BP_CLKCTRL_CLKSEQ_BYPASS_CPU 7 | ||
| 409 | #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x80 | ||
| 410 | #define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v) (((v) << 7) & 0x80) | ||
| 411 | #define BP_CLKCTRL_CLKSEQ_BYPASS_EMI 6 | ||
| 412 | #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x40 | ||
| 413 | #define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v) (((v) << 6) & 0x40) | ||
| 414 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SSP 5 | ||
| 415 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x20 | ||
| 416 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v) (((v) << 5) & 0x20) | ||
| 417 | #define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI 4 | ||
| 418 | #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x10 | ||
| 419 | #define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) (((v) << 4) & 0x10) | ||
| 420 | #define BP_CLKCTRL_CLKSEQ_BYPASS_IR 3 | ||
| 421 | #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x8 | ||
| 422 | #define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v) (((v) << 3) & 0x8) | ||
| 423 | #define BP_CLKCTRL_CLKSEQ_BYPASS_PIX 1 | ||
| 424 | #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x2 | ||
| 425 | #define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v) (((v) << 1) & 0x2) | ||
| 426 | #define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF 0 | ||
| 427 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x1 | ||
| 428 | #define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) (((v) << 0) & 0x1) | ||
| 429 | |||
| 430 | /** | ||
| 431 | * Register: HW_CLKCTRL_RESET | ||
| 432 | * Address: 0xf0 | ||
| 433 | * SCT: no | ||
| 434 | */ | ||
| 435 | #define HW_CLKCTRL_RESET (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0xf0)) | ||
| 436 | #define BP_CLKCTRL_RESET_CHIP 1 | ||
| 437 | #define BM_CLKCTRL_RESET_CHIP 0x2 | ||
| 438 | #define BF_CLKCTRL_RESET_CHIP(v) (((v) << 1) & 0x2) | ||
| 439 | #define BP_CLKCTRL_RESET_DIG 0 | ||
| 440 | #define BM_CLKCTRL_RESET_DIG 0x1 | ||
| 441 | #define BF_CLKCTRL_RESET_DIG(v) (((v) << 0) & 0x1) | ||
| 442 | |||
| 443 | /** | ||
| 444 | * Register: HW_CLKCTRL_VERSION | ||
| 445 | * Address: 0x100 | ||
| 446 | * SCT: no | ||
| 447 | */ | ||
| 448 | #define HW_CLKCTRL_VERSION (*(volatile unsigned long *)(REGS_CLKCTRL_BASE + 0x100)) | ||
| 449 | #define BP_CLKCTRL_VERSION_MAJOR 24 | ||
| 450 | #define BM_CLKCTRL_VERSION_MAJOR 0xff000000 | ||
| 451 | #define BF_CLKCTRL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 452 | #define BP_CLKCTRL_VERSION_MINOR 16 | ||
| 453 | #define BM_CLKCTRL_VERSION_MINOR 0xff0000 | ||
| 454 | #define BF_CLKCTRL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 455 | #define BP_CLKCTRL_VERSION_STEP 0 | ||
| 456 | #define BM_CLKCTRL_VERSION_STEP 0xffff | ||
| 457 | #define BF_CLKCTRL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 458 | |||
| 459 | #endif /* __HEADERGEN__STMP3700__CLKCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h new file mode 100644 index 0000000000..f0b6273439 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dcp.h | |||
| @@ -0,0 +1,707 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__DCP__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__DCP__H__ | ||
| 25 | |||
| 26 | #define REGS_DCP_BASE (0x80028000) | ||
| 27 | |||
| 28 | #define REGS_DCP_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_DCP_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_DCP_CTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_DCP_CTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_DCP_CTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_DCP_CTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_DCP_CTRL_SFTRST 31 | ||
| 40 | #define BM_DCP_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_DCP_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_DCP_CTRL_CLKGATE 30 | ||
| 43 | #define BM_DCP_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_DCP_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_DCP_CTRL_PRESENT_CRYPTO 29 | ||
| 46 | #define BM_DCP_CTRL_PRESENT_CRYPTO 0x20000000 | ||
| 47 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1 | ||
| 48 | #define BV_DCP_CTRL_PRESENT_CRYPTO__Absent 0x0 | ||
| 49 | #define BF_DCP_CTRL_PRESENT_CRYPTO(v) (((v) << 29) & 0x20000000) | ||
| 50 | #define BF_DCP_CTRL_PRESENT_CRYPTO_V(v) ((BV_DCP_CTRL_PRESENT_CRYPTO__##v << 29) & 0x20000000) | ||
| 51 | #define BP_DCP_CTRL_PRESENT_CSC 28 | ||
| 52 | #define BM_DCP_CTRL_PRESENT_CSC 0x10000000 | ||
| 53 | #define BV_DCP_CTRL_PRESENT_CSC__Present 0x1 | ||
| 54 | #define BV_DCP_CTRL_PRESENT_CSC__Absent 0x0 | ||
| 55 | #define BF_DCP_CTRL_PRESENT_CSC(v) (((v) << 28) & 0x10000000) | ||
| 56 | #define BF_DCP_CTRL_PRESENT_CSC_V(v) ((BV_DCP_CTRL_PRESENT_CSC__##v << 28) & 0x10000000) | ||
| 57 | #define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES 23 | ||
| 58 | #define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x800000 | ||
| 59 | #define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v) (((v) << 23) & 0x800000) | ||
| 60 | #define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING 22 | ||
| 61 | #define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x400000 | ||
| 62 | #define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v) (((v) << 22) & 0x400000) | ||
| 63 | #define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 21 | ||
| 64 | #define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 0x200000 | ||
| 65 | #define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v) (((v) << 21) & 0x200000) | ||
| 66 | #define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE 8 | ||
| 67 | #define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE 0x100 | ||
| 68 | #define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v) (((v) << 8) & 0x100) | ||
| 69 | #define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 | ||
| 70 | #define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0xff | ||
| 71 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x1 | ||
| 72 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x2 | ||
| 73 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x4 | ||
| 74 | #define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x8 | ||
| 75 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) (((v) << 0) & 0xff) | ||
| 76 | #define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v) ((BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##v << 0) & 0xff) | ||
| 77 | |||
| 78 | /** | ||
| 79 | * Register: HW_DCP_STAT | ||
| 80 | * Address: 0x10 | ||
| 81 | * SCT: yes | ||
| 82 | */ | ||
| 83 | #define HW_DCP_STAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x0)) | ||
| 84 | #define HW_DCP_STAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x4)) | ||
| 85 | #define HW_DCP_STAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0x8)) | ||
| 86 | #define HW_DCP_STAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x10 + 0xc)) | ||
| 87 | #define BP_DCP_STAT_OTP_KEY_READY 28 | ||
| 88 | #define BM_DCP_STAT_OTP_KEY_READY 0x10000000 | ||
| 89 | #define BF_DCP_STAT_OTP_KEY_READY(v) (((v) << 28) & 0x10000000) | ||
| 90 | #define BP_DCP_STAT_CUR_CHANNEL 24 | ||
| 91 | #define BM_DCP_STAT_CUR_CHANNEL 0xf000000 | ||
| 92 | #define BV_DCP_STAT_CUR_CHANNEL__None 0x0 | ||
| 93 | #define BV_DCP_STAT_CUR_CHANNEL__CH0 0x1 | ||
| 94 | #define BV_DCP_STAT_CUR_CHANNEL__CH1 0x2 | ||
| 95 | #define BV_DCP_STAT_CUR_CHANNEL__CH2 0x3 | ||
| 96 | #define BV_DCP_STAT_CUR_CHANNEL__CH3 0x4 | ||
| 97 | #define BV_DCP_STAT_CUR_CHANNEL__CSC 0x8 | ||
| 98 | #define BF_DCP_STAT_CUR_CHANNEL(v) (((v) << 24) & 0xf000000) | ||
| 99 | #define BF_DCP_STAT_CUR_CHANNEL_V(v) ((BV_DCP_STAT_CUR_CHANNEL__##v << 24) & 0xf000000) | ||
| 100 | #define BP_DCP_STAT_READY_CHANNELS 16 | ||
| 101 | #define BM_DCP_STAT_READY_CHANNELS 0xff0000 | ||
| 102 | #define BV_DCP_STAT_READY_CHANNELS__CH0 0x1 | ||
| 103 | #define BV_DCP_STAT_READY_CHANNELS__CH1 0x2 | ||
| 104 | #define BV_DCP_STAT_READY_CHANNELS__CH2 0x4 | ||
| 105 | #define BV_DCP_STAT_READY_CHANNELS__CH3 0x8 | ||
| 106 | #define BF_DCP_STAT_READY_CHANNELS(v) (((v) << 16) & 0xff0000) | ||
| 107 | #define BF_DCP_STAT_READY_CHANNELS_V(v) ((BV_DCP_STAT_READY_CHANNELS__##v << 16) & 0xff0000) | ||
| 108 | #define BP_DCP_STAT_CSCIRQ 8 | ||
| 109 | #define BM_DCP_STAT_CSCIRQ 0x100 | ||
| 110 | #define BF_DCP_STAT_CSCIRQ(v) (((v) << 8) & 0x100) | ||
| 111 | #define BP_DCP_STAT_IRQ 0 | ||
| 112 | #define BM_DCP_STAT_IRQ 0xf | ||
| 113 | #define BF_DCP_STAT_IRQ(v) (((v) << 0) & 0xf) | ||
| 114 | |||
| 115 | /** | ||
| 116 | * Register: HW_DCP_CHANNELCTRL | ||
| 117 | * Address: 0x20 | ||
| 118 | * SCT: yes | ||
| 119 | */ | ||
| 120 | #define HW_DCP_CHANNELCTRL (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x0)) | ||
| 121 | #define HW_DCP_CHANNELCTRL_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x4)) | ||
| 122 | #define HW_DCP_CHANNELCTRL_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0x8)) | ||
| 123 | #define HW_DCP_CHANNELCTRL_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x20 + 0xc)) | ||
| 124 | #define BP_DCP_CHANNELCTRL_CSC_PRIORITY 17 | ||
| 125 | #define BM_DCP_CHANNELCTRL_CSC_PRIORITY 0x60000 | ||
| 126 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH 0x3 | ||
| 127 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED 0x2 | ||
| 128 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW 0x1 | ||
| 129 | #define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0 | ||
| 130 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v) (((v) << 17) & 0x60000) | ||
| 131 | #define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(v) ((BV_DCP_CHANNELCTRL_CSC_PRIORITY__##v << 17) & 0x60000) | ||
| 132 | #define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED 16 | ||
| 133 | #define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED 0x10000 | ||
| 134 | #define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v) (((v) << 16) & 0x10000) | ||
| 135 | #define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 8 | ||
| 136 | #define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 0xff00 | ||
| 137 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x1 | ||
| 138 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x2 | ||
| 139 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x4 | ||
| 140 | #define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x8 | ||
| 141 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) (((v) << 8) & 0xff00) | ||
| 142 | #define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##v << 8) & 0xff00) | ||
| 143 | #define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 | ||
| 144 | #define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0xff | ||
| 145 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x1 | ||
| 146 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x2 | ||
| 147 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x4 | ||
| 148 | #define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x8 | ||
| 149 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) (((v) << 0) & 0xff) | ||
| 150 | #define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v) ((BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##v << 0) & 0xff) | ||
| 151 | |||
| 152 | /** | ||
| 153 | * Register: HW_DCP_CAPABILITY0 | ||
| 154 | * Address: 0x30 | ||
| 155 | * SCT: no | ||
| 156 | */ | ||
| 157 | #define HW_DCP_CAPABILITY0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x30)) | ||
| 158 | #define BP_DCP_CAPABILITY0_NUM_CHANNELS 8 | ||
| 159 | #define BM_DCP_CAPABILITY0_NUM_CHANNELS 0xf00 | ||
| 160 | #define BF_DCP_CAPABILITY0_NUM_CHANNELS(v) (((v) << 8) & 0xf00) | ||
| 161 | #define BP_DCP_CAPABILITY0_NUM_KEYS 0 | ||
| 162 | #define BM_DCP_CAPABILITY0_NUM_KEYS 0xff | ||
| 163 | #define BF_DCP_CAPABILITY0_NUM_KEYS(v) (((v) << 0) & 0xff) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_DCP_CAPABILITY1 | ||
| 167 | * Address: 0x40 | ||
| 168 | * SCT: no | ||
| 169 | */ | ||
| 170 | #define HW_DCP_CAPABILITY1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x40)) | ||
| 171 | #define BP_DCP_CAPABILITY1_HASH_ALGORITHMS 16 | ||
| 172 | #define BM_DCP_CAPABILITY1_HASH_ALGORITHMS 0xffff0000 | ||
| 173 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1 0x1 | ||
| 174 | #define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x2 | ||
| 175 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) (((v) << 16) & 0xffff0000) | ||
| 176 | #define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##v << 16) & 0xffff0000) | ||
| 177 | #define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0 | ||
| 178 | #define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0xffff | ||
| 179 | #define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x1 | ||
| 180 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) (((v) << 0) & 0xffff) | ||
| 181 | #define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v) ((BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##v << 0) & 0xffff) | ||
| 182 | |||
| 183 | /** | ||
| 184 | * Register: HW_DCP_CONTEXT | ||
| 185 | * Address: 0x50 | ||
| 186 | * SCT: no | ||
| 187 | */ | ||
| 188 | #define HW_DCP_CONTEXT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x50)) | ||
| 189 | #define BP_DCP_CONTEXT_ADDR 0 | ||
| 190 | #define BM_DCP_CONTEXT_ADDR 0xffffffff | ||
| 191 | #define BF_DCP_CONTEXT_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 192 | |||
| 193 | /** | ||
| 194 | * Register: HW_DCP_KEY | ||
| 195 | * Address: 0x60 | ||
| 196 | * SCT: no | ||
| 197 | */ | ||
| 198 | #define HW_DCP_KEY (*(volatile unsigned long *)(REGS_DCP_BASE + 0x60)) | ||
| 199 | #define BP_DCP_KEY_INDEX 4 | ||
| 200 | #define BM_DCP_KEY_INDEX 0x30 | ||
| 201 | #define BF_DCP_KEY_INDEX(v) (((v) << 4) & 0x30) | ||
| 202 | #define BP_DCP_KEY_SUBWORD 0 | ||
| 203 | #define BM_DCP_KEY_SUBWORD 0x3 | ||
| 204 | #define BF_DCP_KEY_SUBWORD(v) (((v) << 0) & 0x3) | ||
| 205 | |||
| 206 | /** | ||
| 207 | * Register: HW_DCP_KEYDATA | ||
| 208 | * Address: 0x70 | ||
| 209 | * SCT: no | ||
| 210 | */ | ||
| 211 | #define HW_DCP_KEYDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x70)) | ||
| 212 | #define BP_DCP_KEYDATA_DATA 0 | ||
| 213 | #define BM_DCP_KEYDATA_DATA 0xffffffff | ||
| 214 | #define BF_DCP_KEYDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 215 | |||
| 216 | /** | ||
| 217 | * Register: HW_DCP_PACKET0 | ||
| 218 | * Address: 0x80 | ||
| 219 | * SCT: no | ||
| 220 | */ | ||
| 221 | #define HW_DCP_PACKET0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x80)) | ||
| 222 | #define BP_DCP_PACKET0_ADDR 0 | ||
| 223 | #define BM_DCP_PACKET0_ADDR 0xffffffff | ||
| 224 | #define BF_DCP_PACKET0_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 225 | |||
| 226 | /** | ||
| 227 | * Register: HW_DCP_PACKET1 | ||
| 228 | * Address: 0x90 | ||
| 229 | * SCT: no | ||
| 230 | */ | ||
| 231 | #define HW_DCP_PACKET1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x90)) | ||
| 232 | #define BP_DCP_PACKET1_TAG 24 | ||
| 233 | #define BM_DCP_PACKET1_TAG 0xff000000 | ||
| 234 | #define BF_DCP_PACKET1_TAG(v) (((v) << 24) & 0xff000000) | ||
| 235 | #define BP_DCP_PACKET1_OUTPUT_WORDSWAP 23 | ||
| 236 | #define BM_DCP_PACKET1_OUTPUT_WORDSWAP 0x800000 | ||
| 237 | #define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v) (((v) << 23) & 0x800000) | ||
| 238 | #define BP_DCP_PACKET1_OUTPUT_BYTESWAP 22 | ||
| 239 | #define BM_DCP_PACKET1_OUTPUT_BYTESWAP 0x400000 | ||
| 240 | #define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v) (((v) << 22) & 0x400000) | ||
| 241 | #define BP_DCP_PACKET1_INPUT_WORDSWAP 21 | ||
| 242 | #define BM_DCP_PACKET1_INPUT_WORDSWAP 0x200000 | ||
| 243 | #define BF_DCP_PACKET1_INPUT_WORDSWAP(v) (((v) << 21) & 0x200000) | ||
| 244 | #define BP_DCP_PACKET1_INPUT_BYTESWAP 20 | ||
| 245 | #define BM_DCP_PACKET1_INPUT_BYTESWAP 0x100000 | ||
| 246 | #define BF_DCP_PACKET1_INPUT_BYTESWAP(v) (((v) << 20) & 0x100000) | ||
| 247 | #define BP_DCP_PACKET1_KEY_WORDSWAP 19 | ||
| 248 | #define BM_DCP_PACKET1_KEY_WORDSWAP 0x80000 | ||
| 249 | #define BF_DCP_PACKET1_KEY_WORDSWAP(v) (((v) << 19) & 0x80000) | ||
| 250 | #define BP_DCP_PACKET1_KEY_BYTESWAP 18 | ||
| 251 | #define BM_DCP_PACKET1_KEY_BYTESWAP 0x40000 | ||
| 252 | #define BF_DCP_PACKET1_KEY_BYTESWAP(v) (((v) << 18) & 0x40000) | ||
| 253 | #define BP_DCP_PACKET1_TEST_SEMA_IRQ 17 | ||
| 254 | #define BM_DCP_PACKET1_TEST_SEMA_IRQ 0x20000 | ||
| 255 | #define BF_DCP_PACKET1_TEST_SEMA_IRQ(v) (((v) << 17) & 0x20000) | ||
| 256 | #define BP_DCP_PACKET1_CONSTANT_FILL 16 | ||
| 257 | #define BM_DCP_PACKET1_CONSTANT_FILL 0x10000 | ||
| 258 | #define BF_DCP_PACKET1_CONSTANT_FILL(v) (((v) << 16) & 0x10000) | ||
| 259 | #define BP_DCP_PACKET1_HASH_OUTPUT 15 | ||
| 260 | #define BM_DCP_PACKET1_HASH_OUTPUT 0x8000 | ||
| 261 | #define BV_DCP_PACKET1_HASH_OUTPUT__INPUT 0x0 | ||
| 262 | #define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x1 | ||
| 263 | #define BF_DCP_PACKET1_HASH_OUTPUT(v) (((v) << 15) & 0x8000) | ||
| 264 | #define BF_DCP_PACKET1_HASH_OUTPUT_V(v) ((BV_DCP_PACKET1_HASH_OUTPUT__##v << 15) & 0x8000) | ||
| 265 | #define BP_DCP_PACKET1_CHECK_HASH 14 | ||
| 266 | #define BM_DCP_PACKET1_CHECK_HASH 0x4000 | ||
| 267 | #define BF_DCP_PACKET1_CHECK_HASH(v) (((v) << 14) & 0x4000) | ||
| 268 | #define BP_DCP_PACKET1_HASH_TERM 13 | ||
| 269 | #define BM_DCP_PACKET1_HASH_TERM 0x2000 | ||
| 270 | #define BF_DCP_PACKET1_HASH_TERM(v) (((v) << 13) & 0x2000) | ||
| 271 | #define BP_DCP_PACKET1_HASH_INIT 12 | ||
| 272 | #define BM_DCP_PACKET1_HASH_INIT 0x1000 | ||
| 273 | #define BF_DCP_PACKET1_HASH_INIT(v) (((v) << 12) & 0x1000) | ||
| 274 | #define BP_DCP_PACKET1_PAYLOAD_KEY 11 | ||
| 275 | #define BM_DCP_PACKET1_PAYLOAD_KEY 0x800 | ||
| 276 | #define BF_DCP_PACKET1_PAYLOAD_KEY(v) (((v) << 11) & 0x800) | ||
| 277 | #define BP_DCP_PACKET1_OTP_KEY 10 | ||
| 278 | #define BM_DCP_PACKET1_OTP_KEY 0x400 | ||
| 279 | #define BF_DCP_PACKET1_OTP_KEY(v) (((v) << 10) & 0x400) | ||
| 280 | #define BP_DCP_PACKET1_CIPHER_INIT 9 | ||
| 281 | #define BM_DCP_PACKET1_CIPHER_INIT 0x200 | ||
| 282 | #define BF_DCP_PACKET1_CIPHER_INIT(v) (((v) << 9) & 0x200) | ||
| 283 | #define BP_DCP_PACKET1_CIPHER_ENCRYPT 8 | ||
| 284 | #define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x100 | ||
| 285 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x1 | ||
| 286 | #define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x0 | ||
| 287 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT(v) (((v) << 8) & 0x100) | ||
| 288 | #define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(v) ((BV_DCP_PACKET1_CIPHER_ENCRYPT__##v << 8) & 0x100) | ||
| 289 | #define BP_DCP_PACKET1_ENABLE_BLIT 7 | ||
| 290 | #define BM_DCP_PACKET1_ENABLE_BLIT 0x80 | ||
| 291 | #define BF_DCP_PACKET1_ENABLE_BLIT(v) (((v) << 7) & 0x80) | ||
| 292 | #define BP_DCP_PACKET1_ENABLE_HASH 6 | ||
| 293 | #define BM_DCP_PACKET1_ENABLE_HASH 0x40 | ||
| 294 | #define BF_DCP_PACKET1_ENABLE_HASH(v) (((v) << 6) & 0x40) | ||
| 295 | #define BP_DCP_PACKET1_ENABLE_CIPHER 5 | ||
| 296 | #define BM_DCP_PACKET1_ENABLE_CIPHER 0x20 | ||
| 297 | #define BF_DCP_PACKET1_ENABLE_CIPHER(v) (((v) << 5) & 0x20) | ||
| 298 | #define BP_DCP_PACKET1_ENABLE_MEMCOPY 4 | ||
| 299 | #define BM_DCP_PACKET1_ENABLE_MEMCOPY 0x10 | ||
| 300 | #define BF_DCP_PACKET1_ENABLE_MEMCOPY(v) (((v) << 4) & 0x10) | ||
| 301 | #define BP_DCP_PACKET1_CHAIN_CONTIGUOUS 3 | ||
| 302 | #define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x8 | ||
| 303 | #define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v) (((v) << 3) & 0x8) | ||
| 304 | #define BP_DCP_PACKET1_CHAIN 2 | ||
| 305 | #define BM_DCP_PACKET1_CHAIN 0x4 | ||
| 306 | #define BF_DCP_PACKET1_CHAIN(v) (((v) << 2) & 0x4) | ||
| 307 | #define BP_DCP_PACKET1_DECR_SEMAPHORE 1 | ||
| 308 | #define BM_DCP_PACKET1_DECR_SEMAPHORE 0x2 | ||
| 309 | #define BF_DCP_PACKET1_DECR_SEMAPHORE(v) (((v) << 1) & 0x2) | ||
| 310 | #define BP_DCP_PACKET1_INTERRUPT 0 | ||
| 311 | #define BM_DCP_PACKET1_INTERRUPT 0x1 | ||
| 312 | #define BF_DCP_PACKET1_INTERRUPT(v) (((v) << 0) & 0x1) | ||
| 313 | |||
| 314 | /** | ||
| 315 | * Register: HW_DCP_PACKET2 | ||
| 316 | * Address: 0xa0 | ||
| 317 | * SCT: no | ||
| 318 | */ | ||
| 319 | #define HW_DCP_PACKET2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xa0)) | ||
| 320 | #define BP_DCP_PACKET2_CIPHER_CFG 24 | ||
| 321 | #define BM_DCP_PACKET2_CIPHER_CFG 0xff000000 | ||
| 322 | #define BF_DCP_PACKET2_CIPHER_CFG(v) (((v) << 24) & 0xff000000) | ||
| 323 | #define BP_DCP_PACKET2_HASH_SELECT 16 | ||
| 324 | #define BM_DCP_PACKET2_HASH_SELECT 0xf0000 | ||
| 325 | #define BV_DCP_PACKET2_HASH_SELECT__SHA1 0x0 | ||
| 326 | #define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x1 | ||
| 327 | #define BF_DCP_PACKET2_HASH_SELECT(v) (((v) << 16) & 0xf0000) | ||
| 328 | #define BF_DCP_PACKET2_HASH_SELECT_V(v) ((BV_DCP_PACKET2_HASH_SELECT__##v << 16) & 0xf0000) | ||
| 329 | #define BP_DCP_PACKET2_KEY_SELECT 8 | ||
| 330 | #define BM_DCP_PACKET2_KEY_SELECT 0xff00 | ||
| 331 | #define BF_DCP_PACKET2_KEY_SELECT(v) (((v) << 8) & 0xff00) | ||
| 332 | #define BP_DCP_PACKET2_CIPHER_MODE 4 | ||
| 333 | #define BM_DCP_PACKET2_CIPHER_MODE 0xf0 | ||
| 334 | #define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x0 | ||
| 335 | #define BV_DCP_PACKET2_CIPHER_MODE__CCB 0x1 | ||
| 336 | #define BF_DCP_PACKET2_CIPHER_MODE(v) (((v) << 4) & 0xf0) | ||
| 337 | #define BF_DCP_PACKET2_CIPHER_MODE_V(v) ((BV_DCP_PACKET2_CIPHER_MODE__##v << 4) & 0xf0) | ||
| 338 | #define BP_DCP_PACKET2_CIPHER_SELECT 0 | ||
| 339 | #define BM_DCP_PACKET2_CIPHER_SELECT 0xf | ||
| 340 | #define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x0 | ||
| 341 | #define BF_DCP_PACKET2_CIPHER_SELECT(v) (((v) << 0) & 0xf) | ||
| 342 | #define BF_DCP_PACKET2_CIPHER_SELECT_V(v) ((BV_DCP_PACKET2_CIPHER_SELECT__##v << 0) & 0xf) | ||
| 343 | |||
| 344 | /** | ||
| 345 | * Register: HW_DCP_PACKET3 | ||
| 346 | * Address: 0xb0 | ||
| 347 | * SCT: no | ||
| 348 | */ | ||
| 349 | #define HW_DCP_PACKET3 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xb0)) | ||
| 350 | #define BP_DCP_PACKET3_ADDR 0 | ||
| 351 | #define BM_DCP_PACKET3_ADDR 0xffffffff | ||
| 352 | #define BF_DCP_PACKET3_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 353 | |||
| 354 | /** | ||
| 355 | * Register: HW_DCP_PACKET4 | ||
| 356 | * Address: 0xc0 | ||
| 357 | * SCT: no | ||
| 358 | */ | ||
| 359 | #define HW_DCP_PACKET4 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xc0)) | ||
| 360 | #define BP_DCP_PACKET4_ADDR 0 | ||
| 361 | #define BM_DCP_PACKET4_ADDR 0xffffffff | ||
| 362 | #define BF_DCP_PACKET4_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 363 | |||
| 364 | /** | ||
| 365 | * Register: HW_DCP_PACKET5 | ||
| 366 | * Address: 0xd0 | ||
| 367 | * SCT: no | ||
| 368 | */ | ||
| 369 | #define HW_DCP_PACKET5 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xd0)) | ||
| 370 | #define BP_DCP_PACKET5_COUNT 0 | ||
| 371 | #define BM_DCP_PACKET5_COUNT 0xffffffff | ||
| 372 | #define BF_DCP_PACKET5_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 373 | |||
| 374 | /** | ||
| 375 | * Register: HW_DCP_PACKET6 | ||
| 376 | * Address: 0xe0 | ||
| 377 | * SCT: no | ||
| 378 | */ | ||
| 379 | #define HW_DCP_PACKET6 (*(volatile unsigned long *)(REGS_DCP_BASE + 0xe0)) | ||
| 380 | #define BP_DCP_PACKET6_ADDR 0 | ||
| 381 | #define BM_DCP_PACKET6_ADDR 0xffffffff | ||
| 382 | #define BF_DCP_PACKET6_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 383 | |||
| 384 | /** | ||
| 385 | * Register: HW_DCP_CHnCMDPTR | ||
| 386 | * Address: 0x100+n*0x40 | ||
| 387 | * SCT: no | ||
| 388 | */ | ||
| 389 | #define HW_DCP_CHnCMDPTR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x100+(n)*0x40)) | ||
| 390 | #define BP_DCP_CHnCMDPTR_ADDR 0 | ||
| 391 | #define BM_DCP_CHnCMDPTR_ADDR 0xffffffff | ||
| 392 | #define BF_DCP_CHnCMDPTR_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 393 | |||
| 394 | /** | ||
| 395 | * Register: HW_DCP_CHnSEMA | ||
| 396 | * Address: 0x110+n*0x40 | ||
| 397 | * SCT: no | ||
| 398 | */ | ||
| 399 | #define HW_DCP_CHnSEMA(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x110+(n)*0x40)) | ||
| 400 | #define BP_DCP_CHnSEMA_VALUE 16 | ||
| 401 | #define BM_DCP_CHnSEMA_VALUE 0xff0000 | ||
| 402 | #define BF_DCP_CHnSEMA_VALUE(v) (((v) << 16) & 0xff0000) | ||
| 403 | #define BP_DCP_CHnSEMA_INCREMENT 0 | ||
| 404 | #define BM_DCP_CHnSEMA_INCREMENT 0xff | ||
| 405 | #define BF_DCP_CHnSEMA_INCREMENT(v) (((v) << 0) & 0xff) | ||
| 406 | |||
| 407 | /** | ||
| 408 | * Register: HW_DCP_CHnSTAT | ||
| 409 | * Address: 0x120+n*0x40 | ||
| 410 | * SCT: yes | ||
| 411 | */ | ||
| 412 | #define HW_DCP_CHnSTAT(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x0)) | ||
| 413 | #define HW_DCP_CHnSTAT_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x4)) | ||
| 414 | #define HW_DCP_CHnSTAT_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0x8)) | ||
| 415 | #define HW_DCP_CHnSTAT_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x120+(n)*0x40 + 0xc)) | ||
| 416 | #define BP_DCP_CHnSTAT_TAG 24 | ||
| 417 | #define BM_DCP_CHnSTAT_TAG 0xff000000 | ||
| 418 | #define BF_DCP_CHnSTAT_TAG(v) (((v) << 24) & 0xff000000) | ||
| 419 | #define BP_DCP_CHnSTAT_ERROR_CODE 16 | ||
| 420 | #define BM_DCP_CHnSTAT_ERROR_CODE 0xff0000 | ||
| 421 | #define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x1 | ||
| 422 | #define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN 0x2 | ||
| 423 | #define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR 0x3 | ||
| 424 | #define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR 0x4 | ||
| 425 | #define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE 0x5 | ||
| 426 | #define BF_DCP_CHnSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
| 427 | #define BF_DCP_CHnSTAT_ERROR_CODE_V(v) ((BV_DCP_CHnSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
| 428 | #define BP_DCP_CHnSTAT_ERROR_DST 5 | ||
| 429 | #define BM_DCP_CHnSTAT_ERROR_DST 0x20 | ||
| 430 | #define BF_DCP_CHnSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
| 431 | #define BP_DCP_CHnSTAT_ERROR_SRC 4 | ||
| 432 | #define BM_DCP_CHnSTAT_ERROR_SRC 0x10 | ||
| 433 | #define BF_DCP_CHnSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
| 434 | #define BP_DCP_CHnSTAT_ERROR_PACKET 3 | ||
| 435 | #define BM_DCP_CHnSTAT_ERROR_PACKET 0x8 | ||
| 436 | #define BF_DCP_CHnSTAT_ERROR_PACKET(v) (((v) << 3) & 0x8) | ||
| 437 | #define BP_DCP_CHnSTAT_ERROR_SETUP 2 | ||
| 438 | #define BM_DCP_CHnSTAT_ERROR_SETUP 0x4 | ||
| 439 | #define BF_DCP_CHnSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
| 440 | #define BP_DCP_CHnSTAT_HASH_MISMATCH 1 | ||
| 441 | #define BM_DCP_CHnSTAT_HASH_MISMATCH 0x2 | ||
| 442 | #define BF_DCP_CHnSTAT_HASH_MISMATCH(v) (((v) << 1) & 0x2) | ||
| 443 | |||
| 444 | /** | ||
| 445 | * Register: HW_DCP_CHnOPTS | ||
| 446 | * Address: 0x130+n*0x40 | ||
| 447 | * SCT: yes | ||
| 448 | */ | ||
| 449 | #define HW_DCP_CHnOPTS(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x0)) | ||
| 450 | #define HW_DCP_CHnOPTS_SET(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x4)) | ||
| 451 | #define HW_DCP_CHnOPTS_CLR(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0x8)) | ||
| 452 | #define HW_DCP_CHnOPTS_TOG(n) (*(volatile unsigned long *)(REGS_DCP_BASE + 0x130+(n)*0x40 + 0xc)) | ||
| 453 | #define BP_DCP_CHnOPTS_RECOVERY_TIMER 0 | ||
| 454 | #define BM_DCP_CHnOPTS_RECOVERY_TIMER 0xffff | ||
| 455 | #define BF_DCP_CHnOPTS_RECOVERY_TIMER(v) (((v) << 0) & 0xffff) | ||
| 456 | |||
| 457 | /** | ||
| 458 | * Register: HW_DCP_CSCCTRL0 | ||
| 459 | * Address: 0x300 | ||
| 460 | * SCT: yes | ||
| 461 | */ | ||
| 462 | #define HW_DCP_CSCCTRL0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x0)) | ||
| 463 | #define HW_DCP_CSCCTRL0_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x4)) | ||
| 464 | #define HW_DCP_CSCCTRL0_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0x8)) | ||
| 465 | #define HW_DCP_CSCCTRL0_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x300 + 0xc)) | ||
| 466 | #define BP_DCP_CSCCTRL0_UPSAMPLE 14 | ||
| 467 | #define BM_DCP_CSCCTRL0_UPSAMPLE 0x4000 | ||
| 468 | #define BF_DCP_CSCCTRL0_UPSAMPLE(v) (((v) << 14) & 0x4000) | ||
| 469 | #define BP_DCP_CSCCTRL0_SCALE 13 | ||
| 470 | #define BM_DCP_CSCCTRL0_SCALE 0x2000 | ||
| 471 | #define BF_DCP_CSCCTRL0_SCALE(v) (((v) << 13) & 0x2000) | ||
| 472 | #define BP_DCP_CSCCTRL0_ROTATE 12 | ||
| 473 | #define BM_DCP_CSCCTRL0_ROTATE 0x1000 | ||
| 474 | #define BF_DCP_CSCCTRL0_ROTATE(v) (((v) << 12) & 0x1000) | ||
| 475 | #define BP_DCP_CSCCTRL0_SUBSAMPLE 11 | ||
| 476 | #define BM_DCP_CSCCTRL0_SUBSAMPLE 0x800 | ||
| 477 | #define BF_DCP_CSCCTRL0_SUBSAMPLE(v) (((v) << 11) & 0x800) | ||
| 478 | #define BP_DCP_CSCCTRL0_DELTA 10 | ||
| 479 | #define BM_DCP_CSCCTRL0_DELTA 0x400 | ||
| 480 | #define BF_DCP_CSCCTRL0_DELTA(v) (((v) << 10) & 0x400) | ||
| 481 | #define BP_DCP_CSCCTRL0_RGB_FORMAT 8 | ||
| 482 | #define BM_DCP_CSCCTRL0_RGB_FORMAT 0x300 | ||
| 483 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0 | ||
| 484 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24 0x2 | ||
| 485 | #define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I 0x3 | ||
| 486 | #define BF_DCP_CSCCTRL0_RGB_FORMAT(v) (((v) << 8) & 0x300) | ||
| 487 | #define BF_DCP_CSCCTRL0_RGB_FORMAT_V(v) ((BV_DCP_CSCCTRL0_RGB_FORMAT__##v << 8) & 0x300) | ||
| 488 | #define BP_DCP_CSCCTRL0_YUV_FORMAT 4 | ||
| 489 | #define BM_DCP_CSCCTRL0_YUV_FORMAT 0xf0 | ||
| 490 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0 | ||
| 491 | #define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2 | ||
| 492 | #define BF_DCP_CSCCTRL0_YUV_FORMAT(v) (((v) << 4) & 0xf0) | ||
| 493 | #define BF_DCP_CSCCTRL0_YUV_FORMAT_V(v) ((BV_DCP_CSCCTRL0_YUV_FORMAT__##v << 4) & 0xf0) | ||
| 494 | #define BP_DCP_CSCCTRL0_ENABLE 0 | ||
| 495 | #define BM_DCP_CSCCTRL0_ENABLE 0x1 | ||
| 496 | #define BF_DCP_CSCCTRL0_ENABLE(v) (((v) << 0) & 0x1) | ||
| 497 | |||
| 498 | /** | ||
| 499 | * Register: HW_DCP_CSCSTAT | ||
| 500 | * Address: 0x310 | ||
| 501 | * SCT: yes | ||
| 502 | */ | ||
| 503 | #define HW_DCP_CSCSTAT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x0)) | ||
| 504 | #define HW_DCP_CSCSTAT_SET (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x4)) | ||
| 505 | #define HW_DCP_CSCSTAT_CLR (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0x8)) | ||
| 506 | #define HW_DCP_CSCSTAT_TOG (*(volatile unsigned long *)(REGS_DCP_BASE + 0x310 + 0xc)) | ||
| 507 | #define BP_DCP_CSCSTAT_ERROR_CODE 16 | ||
| 508 | #define BM_DCP_CSCSTAT_ERROR_CODE 0xff0000 | ||
| 509 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1 | ||
| 510 | #define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2 | ||
| 511 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3 | ||
| 512 | #define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4 | ||
| 513 | #define BF_DCP_CSCSTAT_ERROR_CODE(v) (((v) << 16) & 0xff0000) | ||
| 514 | #define BF_DCP_CSCSTAT_ERROR_CODE_V(v) ((BV_DCP_CSCSTAT_ERROR_CODE__##v << 16) & 0xff0000) | ||
| 515 | #define BP_DCP_CSCSTAT_ERROR_DST 5 | ||
| 516 | #define BM_DCP_CSCSTAT_ERROR_DST 0x20 | ||
| 517 | #define BF_DCP_CSCSTAT_ERROR_DST(v) (((v) << 5) & 0x20) | ||
| 518 | #define BP_DCP_CSCSTAT_ERROR_SRC 4 | ||
| 519 | #define BM_DCP_CSCSTAT_ERROR_SRC 0x10 | ||
| 520 | #define BF_DCP_CSCSTAT_ERROR_SRC(v) (((v) << 4) & 0x10) | ||
| 521 | #define BP_DCP_CSCSTAT_ERROR_SETUP 2 | ||
| 522 | #define BM_DCP_CSCSTAT_ERROR_SETUP 0x4 | ||
| 523 | #define BF_DCP_CSCSTAT_ERROR_SETUP(v) (((v) << 2) & 0x4) | ||
| 524 | #define BP_DCP_CSCSTAT_COMPLETE 0 | ||
| 525 | #define BM_DCP_CSCSTAT_COMPLETE 0x1 | ||
| 526 | #define BF_DCP_CSCSTAT_COMPLETE(v) (((v) << 0) & 0x1) | ||
| 527 | |||
| 528 | /** | ||
| 529 | * Register: HW_DCP_CSCOUTBUFPARAM | ||
| 530 | * Address: 0x320 | ||
| 531 | * SCT: no | ||
| 532 | */ | ||
| 533 | #define HW_DCP_CSCOUTBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x320)) | ||
| 534 | #define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE 12 | ||
| 535 | #define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE 0xfff000 | ||
| 536 | #define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) << 12) & 0xfff000) | ||
| 537 | #define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE 0 | ||
| 538 | #define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE 0xfff | ||
| 539 | #define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
| 540 | |||
| 541 | /** | ||
| 542 | * Register: HW_DCP_CSCINBUFPARAM | ||
| 543 | * Address: 0x330 | ||
| 544 | * SCT: no | ||
| 545 | */ | ||
| 546 | #define HW_DCP_CSCINBUFPARAM (*(volatile unsigned long *)(REGS_DCP_BASE + 0x330)) | ||
| 547 | #define BP_DCP_CSCINBUFPARAM_LINE_SIZE 0 | ||
| 548 | #define BM_DCP_CSCINBUFPARAM_LINE_SIZE 0xfff | ||
| 549 | #define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v) (((v) << 0) & 0xfff) | ||
| 550 | |||
| 551 | /** | ||
| 552 | * Register: HW_DCP_CSCRGB | ||
| 553 | * Address: 0x340 | ||
| 554 | * SCT: no | ||
| 555 | */ | ||
| 556 | #define HW_DCP_CSCRGB (*(volatile unsigned long *)(REGS_DCP_BASE + 0x340)) | ||
| 557 | #define BP_DCP_CSCRGB_ADDR 0 | ||
| 558 | #define BM_DCP_CSCRGB_ADDR 0xffffffff | ||
| 559 | #define BF_DCP_CSCRGB_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 560 | |||
| 561 | /** | ||
| 562 | * Register: HW_DCP_CSCLUMA | ||
| 563 | * Address: 0x350 | ||
| 564 | * SCT: no | ||
| 565 | */ | ||
| 566 | #define HW_DCP_CSCLUMA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x350)) | ||
| 567 | #define BP_DCP_CSCLUMA_ADDR 0 | ||
| 568 | #define BM_DCP_CSCLUMA_ADDR 0xffffffff | ||
| 569 | #define BF_DCP_CSCLUMA_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 570 | |||
| 571 | /** | ||
| 572 | * Register: HW_DCP_CSCCHROMAU | ||
| 573 | * Address: 0x360 | ||
| 574 | * SCT: no | ||
| 575 | */ | ||
| 576 | #define HW_DCP_CSCCHROMAU (*(volatile unsigned long *)(REGS_DCP_BASE + 0x360)) | ||
| 577 | #define BP_DCP_CSCCHROMAU_ADDR 0 | ||
| 578 | #define BM_DCP_CSCCHROMAU_ADDR 0xffffffff | ||
| 579 | #define BF_DCP_CSCCHROMAU_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 580 | |||
| 581 | /** | ||
| 582 | * Register: HW_DCP_CSCCHROMAV | ||
| 583 | * Address: 0x370 | ||
| 584 | * SCT: no | ||
| 585 | */ | ||
| 586 | #define HW_DCP_CSCCHROMAV (*(volatile unsigned long *)(REGS_DCP_BASE + 0x370)) | ||
| 587 | #define BP_DCP_CSCCHROMAV_ADDR 0 | ||
| 588 | #define BM_DCP_CSCCHROMAV_ADDR 0xffffffff | ||
| 589 | #define BF_DCP_CSCCHROMAV_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 590 | |||
| 591 | /** | ||
| 592 | * Register: HW_DCP_CSCCOEFF0 | ||
| 593 | * Address: 0x380 | ||
| 594 | * SCT: no | ||
| 595 | */ | ||
| 596 | #define HW_DCP_CSCCOEFF0 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x380)) | ||
| 597 | #define BP_DCP_CSCCOEFF0_C0 16 | ||
| 598 | #define BM_DCP_CSCCOEFF0_C0 0x3ff0000 | ||
| 599 | #define BF_DCP_CSCCOEFF0_C0(v) (((v) << 16) & 0x3ff0000) | ||
| 600 | #define BP_DCP_CSCCOEFF0_UV_OFFSET 8 | ||
| 601 | #define BM_DCP_CSCCOEFF0_UV_OFFSET 0xff00 | ||
| 602 | #define BF_DCP_CSCCOEFF0_UV_OFFSET(v) (((v) << 8) & 0xff00) | ||
| 603 | #define BP_DCP_CSCCOEFF0_Y_OFFSET 0 | ||
| 604 | #define BM_DCP_CSCCOEFF0_Y_OFFSET 0xff | ||
| 605 | #define BF_DCP_CSCCOEFF0_Y_OFFSET(v) (((v) << 0) & 0xff) | ||
| 606 | |||
| 607 | /** | ||
| 608 | * Register: HW_DCP_CSCCOEFF1 | ||
| 609 | * Address: 0x390 | ||
| 610 | * SCT: no | ||
| 611 | */ | ||
| 612 | #define HW_DCP_CSCCOEFF1 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x390)) | ||
| 613 | #define BP_DCP_CSCCOEFF1_C1 16 | ||
| 614 | #define BM_DCP_CSCCOEFF1_C1 0x3ff0000 | ||
| 615 | #define BF_DCP_CSCCOEFF1_C1(v) (((v) << 16) & 0x3ff0000) | ||
| 616 | #define BP_DCP_CSCCOEFF1_C4 0 | ||
| 617 | #define BM_DCP_CSCCOEFF1_C4 0x3ff | ||
| 618 | #define BF_DCP_CSCCOEFF1_C4(v) (((v) << 0) & 0x3ff) | ||
| 619 | |||
| 620 | /** | ||
| 621 | * Register: HW_DCP_CSCCOEFF2 | ||
| 622 | * Address: 0x3a0 | ||
| 623 | * SCT: no | ||
| 624 | */ | ||
| 625 | #define HW_DCP_CSCCOEFF2 (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3a0)) | ||
| 626 | #define BP_DCP_CSCCOEFF2_C2 16 | ||
| 627 | #define BM_DCP_CSCCOEFF2_C2 0x3ff0000 | ||
| 628 | #define BF_DCP_CSCCOEFF2_C2(v) (((v) << 16) & 0x3ff0000) | ||
| 629 | #define BP_DCP_CSCCOEFF2_C3 0 | ||
| 630 | #define BM_DCP_CSCCOEFF2_C3 0x3ff | ||
| 631 | #define BF_DCP_CSCCOEFF2_C3(v) (((v) << 0) & 0x3ff) | ||
| 632 | |||
| 633 | /** | ||
| 634 | * Register: HW_DCP_CSCXSCALE | ||
| 635 | * Address: 0x3e0 | ||
| 636 | * SCT: no | ||
| 637 | */ | ||
| 638 | #define HW_DCP_CSCXSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3e0)) | ||
| 639 | #define BP_DCP_CSCXSCALE_INT 24 | ||
| 640 | #define BM_DCP_CSCXSCALE_INT 0x3000000 | ||
| 641 | #define BF_DCP_CSCXSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
| 642 | #define BP_DCP_CSCXSCALE_FRAC 12 | ||
| 643 | #define BM_DCP_CSCXSCALE_FRAC 0xfff000 | ||
| 644 | #define BF_DCP_CSCXSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
| 645 | #define BP_DCP_CSCXSCALE_WIDTH 0 | ||
| 646 | #define BM_DCP_CSCXSCALE_WIDTH 0xfff | ||
| 647 | #define BF_DCP_CSCXSCALE_WIDTH(v) (((v) << 0) & 0xfff) | ||
| 648 | |||
| 649 | /** | ||
| 650 | * Register: HW_DCP_CSCYSCALE | ||
| 651 | * Address: 0x3f0 | ||
| 652 | * SCT: no | ||
| 653 | */ | ||
| 654 | #define HW_DCP_CSCYSCALE (*(volatile unsigned long *)(REGS_DCP_BASE + 0x3f0)) | ||
| 655 | #define BP_DCP_CSCYSCALE_INT 24 | ||
| 656 | #define BM_DCP_CSCYSCALE_INT 0x3000000 | ||
| 657 | #define BF_DCP_CSCYSCALE_INT(v) (((v) << 24) & 0x3000000) | ||
| 658 | #define BP_DCP_CSCYSCALE_FRAC 12 | ||
| 659 | #define BM_DCP_CSCYSCALE_FRAC 0xfff000 | ||
| 660 | #define BF_DCP_CSCYSCALE_FRAC(v) (((v) << 12) & 0xfff000) | ||
| 661 | #define BP_DCP_CSCYSCALE_HEIGHT 0 | ||
| 662 | #define BM_DCP_CSCYSCALE_HEIGHT 0xfff | ||
| 663 | #define BF_DCP_CSCYSCALE_HEIGHT(v) (((v) << 0) & 0xfff) | ||
| 664 | |||
| 665 | /** | ||
| 666 | * Register: HW_DCP_DBGSELECT | ||
| 667 | * Address: 0x400 | ||
| 668 | * SCT: no | ||
| 669 | */ | ||
| 670 | #define HW_DCP_DBGSELECT (*(volatile unsigned long *)(REGS_DCP_BASE + 0x400)) | ||
| 671 | #define BP_DCP_DBGSELECT_INDEX 0 | ||
| 672 | #define BM_DCP_DBGSELECT_INDEX 0xff | ||
| 673 | #define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1 | ||
| 674 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10 | ||
| 675 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11 | ||
| 676 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12 | ||
| 677 | #define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13 | ||
| 678 | #define BF_DCP_DBGSELECT_INDEX(v) (((v) << 0) & 0xff) | ||
| 679 | #define BF_DCP_DBGSELECT_INDEX_V(v) ((BV_DCP_DBGSELECT_INDEX__##v << 0) & 0xff) | ||
| 680 | |||
| 681 | /** | ||
| 682 | * Register: HW_DCP_DBGDATA | ||
| 683 | * Address: 0x410 | ||
| 684 | * SCT: no | ||
| 685 | */ | ||
| 686 | #define HW_DCP_DBGDATA (*(volatile unsigned long *)(REGS_DCP_BASE + 0x410)) | ||
| 687 | #define BP_DCP_DBGDATA_DATA 0 | ||
| 688 | #define BM_DCP_DBGDATA_DATA 0xffffffff | ||
| 689 | #define BF_DCP_DBGDATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 690 | |||
| 691 | /** | ||
| 692 | * Register: HW_DCP_VERSION | ||
| 693 | * Address: 0x420 | ||
| 694 | * SCT: no | ||
| 695 | */ | ||
| 696 | #define HW_DCP_VERSION (*(volatile unsigned long *)(REGS_DCP_BASE + 0x420)) | ||
| 697 | #define BP_DCP_VERSION_MAJOR 24 | ||
| 698 | #define BM_DCP_VERSION_MAJOR 0xff000000 | ||
| 699 | #define BF_DCP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 700 | #define BP_DCP_VERSION_MINOR 16 | ||
| 701 | #define BM_DCP_VERSION_MINOR 0xff0000 | ||
| 702 | #define BF_DCP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 703 | #define BP_DCP_VERSION_STEP 0 | ||
| 704 | #define BM_DCP_VERSION_STEP 0xffff | ||
| 705 | #define BF_DCP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 706 | |||
| 707 | #endif /* __HEADERGEN__STMP3700__DCP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h new file mode 100644 index 0000000000..69d4e7128f --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-digctl.h | |||
| @@ -0,0 +1,759 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__DIGCTL__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__DIGCTL__H__ | ||
| 25 | |||
| 26 | #define REGS_DIGCTL_BASE (0x8001c000) | ||
| 27 | |||
| 28 | #define REGS_DIGCTL_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_DIGCTL_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_DIGCTL_CTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_DIGCTL_CTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_DIGCTL_CTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_DIGCTL_CTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_DIGCTL_CTRL_TRAP_IRQ 29 | ||
| 40 | #define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 | ||
| 41 | #define BF_DIGCTL_CTRL_TRAP_IRQ(v) (((v) << 29) & 0x20000000) | ||
| 42 | #define BP_DIGCTL_CTRL_DCP_BIST_CLKEN 23 | ||
| 43 | #define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x800000 | ||
| 44 | #define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v) (((v) << 23) & 0x800000) | ||
| 45 | #define BP_DIGCTL_CTRL_DCP_BIST_START 22 | ||
| 46 | #define BM_DIGCTL_CTRL_DCP_BIST_START 0x400000 | ||
| 47 | #define BF_DIGCTL_CTRL_DCP_BIST_START(v) (((v) << 22) & 0x400000) | ||
| 48 | #define BP_DIGCTL_CTRL_ARM_BIST_CLKEN 21 | ||
| 49 | #define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x200000 | ||
| 50 | #define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v) (((v) << 21) & 0x200000) | ||
| 51 | #define BP_DIGCTL_CTRL_USB_TESTMODE 20 | ||
| 52 | #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 | ||
| 53 | #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) << 20) & 0x100000) | ||
| 54 | #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 | ||
| 55 | #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 | ||
| 56 | #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) << 19) & 0x80000) | ||
| 57 | #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 | ||
| 58 | #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 | ||
| 59 | #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) << 18) & 0x40000) | ||
| 60 | #define BP_DIGCTL_CTRL_ARM_BIST_START 17 | ||
| 61 | #define BM_DIGCTL_CTRL_ARM_BIST_START 0x20000 | ||
| 62 | #define BF_DIGCTL_CTRL_ARM_BIST_START(v) (((v) << 17) & 0x20000) | ||
| 63 | #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 | ||
| 64 | #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 | ||
| 65 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 | ||
| 66 | #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 | ||
| 67 | #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) << 16) & 0x10000) | ||
| 68 | #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_UART_LOOPBACK__##v << 16) & 0x10000) | ||
| 69 | #define BP_DIGCTL_CTRL_SAIF_LOOPBACK 15 | ||
| 70 | #define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x8000 | ||
| 71 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 | ||
| 72 | #define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 | ||
| 73 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v) (((v) << 15) & 0x8000) | ||
| 74 | #define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(v) ((BV_DIGCTL_CTRL_SAIF_LOOPBACK__##v << 15) & 0x8000) | ||
| 75 | #define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 | ||
| 76 | #define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x6000 | ||
| 77 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 | ||
| 78 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 | ||
| 79 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 | ||
| 80 | #define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 | ||
| 81 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) (((v) << 13) & 0x6000) | ||
| 82 | #define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##v << 13) & 0x6000) | ||
| 83 | #define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL 12 | ||
| 84 | #define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x1000 | ||
| 85 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 | ||
| 86 | #define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 | ||
| 87 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) (((v) << 12) & 0x1000) | ||
| 88 | #define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v) ((BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##v << 12) & 0x1000) | ||
| 89 | #define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 11 | ||
| 90 | #define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x800 | ||
| 91 | #define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) (((v) << 11) & 0x800) | ||
| 92 | #define BP_DIGCTL_CTRL_USE_SERIAL_JTAG 6 | ||
| 93 | #define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x40 | ||
| 94 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 | ||
| 95 | #define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 | ||
| 96 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v) (((v) << 6) & 0x40) | ||
| 97 | #define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v) ((BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##v << 6) & 0x40) | ||
| 98 | #define BP_DIGCTL_CTRL_TRAP_IN_RANGE 5 | ||
| 99 | #define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x20 | ||
| 100 | #define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v) (((v) << 5) & 0x20) | ||
| 101 | #define BP_DIGCTL_CTRL_TRAP_ENABLE 4 | ||
| 102 | #define BM_DIGCTL_CTRL_TRAP_ENABLE 0x10 | ||
| 103 | #define BF_DIGCTL_CTRL_TRAP_ENABLE(v) (((v) << 4) & 0x10) | ||
| 104 | #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 | ||
| 105 | #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 | ||
| 106 | #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) << 3) & 0x8) | ||
| 107 | #define BP_DIGCTL_CTRL_USB_CLKGATE 2 | ||
| 108 | #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 | ||
| 109 | #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 | ||
| 110 | #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 | ||
| 111 | #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) << 2) & 0x4) | ||
| 112 | #define BF_DIGCTL_CTRL_USB_CLKGATE_V(v) ((BV_DIGCTL_CTRL_USB_CLKGATE__##v << 2) & 0x4) | ||
| 113 | #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 | ||
| 114 | #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 | ||
| 115 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 | ||
| 116 | #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 | ||
| 117 | #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) << 1) & 0x2) | ||
| 118 | #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(v) ((BV_DIGCTL_CTRL_JTAG_SHIELD__##v << 1) & 0x2) | ||
| 119 | #define BP_DIGCTL_CTRL_LATCH_ENTROPY 0 | ||
| 120 | #define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x1 | ||
| 121 | #define BF_DIGCTL_CTRL_LATCH_ENTROPY(v) (((v) << 0) & 0x1) | ||
| 122 | |||
| 123 | /** | ||
| 124 | * Register: HW_DIGCTL_STATUS | ||
| 125 | * Address: 0x10 | ||
| 126 | * SCT: no | ||
| 127 | */ | ||
| 128 | #define HW_DIGCTL_STATUS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x10)) | ||
| 129 | #define BP_DIGCTL_STATUS_USB_HS_PRESENT 31 | ||
| 130 | #define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 | ||
| 131 | #define BF_DIGCTL_STATUS_USB_HS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 132 | #define BP_DIGCTL_STATUS_USB_OTG_PRESENT 30 | ||
| 133 | #define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 | ||
| 134 | #define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 135 | #define BP_DIGCTL_STATUS_USB_HOST_PRESENT 29 | ||
| 136 | #define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 | ||
| 137 | #define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 138 | #define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT 28 | ||
| 139 | #define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 | ||
| 140 | #define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 141 | #define BP_DIGCTL_STATUS_DCP_BIST_FAIL 10 | ||
| 142 | #define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x400 | ||
| 143 | #define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v) (((v) << 10) & 0x400) | ||
| 144 | #define BP_DIGCTL_STATUS_DCP_BIST_PASS 9 | ||
| 145 | #define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x200 | ||
| 146 | #define BF_DIGCTL_STATUS_DCP_BIST_PASS(v) (((v) << 9) & 0x200) | ||
| 147 | #define BP_DIGCTL_STATUS_DCP_BIST_DONE 8 | ||
| 148 | #define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x100 | ||
| 149 | #define BF_DIGCTL_STATUS_DCP_BIST_DONE(v) (((v) << 8) & 0x100) | ||
| 150 | #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 | ||
| 151 | #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 | ||
| 152 | #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) << 4) & 0x10) | ||
| 153 | #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 | ||
| 154 | #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0xe | ||
| 155 | #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) << 1) & 0xe) | ||
| 156 | #define BP_DIGCTL_STATUS_WRITTEN 0 | ||
| 157 | #define BM_DIGCTL_STATUS_WRITTEN 0x1 | ||
| 158 | #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) << 0) & 0x1) | ||
| 159 | |||
| 160 | /** | ||
| 161 | * Register: HW_DIGCTL_HCLKCOUNT | ||
| 162 | * Address: 0x20 | ||
| 163 | * SCT: no | ||
| 164 | */ | ||
| 165 | #define HW_DIGCTL_HCLKCOUNT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x20)) | ||
| 166 | #define BP_DIGCTL_HCLKCOUNT_COUNT 0 | ||
| 167 | #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff | ||
| 168 | #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 169 | |||
| 170 | /** | ||
| 171 | * Register: HW_DIGCTL_RAMCTRL | ||
| 172 | * Address: 0x30 | ||
| 173 | * SCT: yes | ||
| 174 | */ | ||
| 175 | #define HW_DIGCTL_RAMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x0)) | ||
| 176 | #define HW_DIGCTL_RAMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x4)) | ||
| 177 | #define HW_DIGCTL_RAMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0x8)) | ||
| 178 | #define HW_DIGCTL_RAMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x30 + 0xc)) | ||
| 179 | #define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 | ||
| 180 | #define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0xf00 | ||
| 181 | #define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) (((v) << 8) & 0xf00) | ||
| 182 | #define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0 | ||
| 183 | #define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x1 | ||
| 184 | #define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) (((v) << 0) & 0x1) | ||
| 185 | |||
| 186 | /** | ||
| 187 | * Register: HW_DIGCTL_RAMREPAIR | ||
| 188 | * Address: 0x40 | ||
| 189 | * SCT: yes | ||
| 190 | */ | ||
| 191 | #define HW_DIGCTL_RAMREPAIR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x0)) | ||
| 192 | #define HW_DIGCTL_RAMREPAIR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x4)) | ||
| 193 | #define HW_DIGCTL_RAMREPAIR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0x8)) | ||
| 194 | #define HW_DIGCTL_RAMREPAIR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x40 + 0xc)) | ||
| 195 | #define BP_DIGCTL_RAMREPAIR_ADDR 0 | ||
| 196 | #define BM_DIGCTL_RAMREPAIR_ADDR 0xffff | ||
| 197 | #define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) << 0) & 0xffff) | ||
| 198 | |||
| 199 | /** | ||
| 200 | * Register: HW_DIGCTL_ROMCTRL | ||
| 201 | * Address: 0x50 | ||
| 202 | * SCT: yes | ||
| 203 | */ | ||
| 204 | #define HW_DIGCTL_ROMCTRL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x0)) | ||
| 205 | #define HW_DIGCTL_ROMCTRL_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x4)) | ||
| 206 | #define HW_DIGCTL_ROMCTRL_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0x8)) | ||
| 207 | #define HW_DIGCTL_ROMCTRL_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x50 + 0xc)) | ||
| 208 | #define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 | ||
| 209 | #define BM_DIGCTL_ROMCTRL_RD_MARGIN 0xf | ||
| 210 | #define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) (((v) << 0) & 0xf) | ||
| 211 | |||
| 212 | /** | ||
| 213 | * Register: HW_DIGCTL_WRITEONCE | ||
| 214 | * Address: 0x60 | ||
| 215 | * SCT: no | ||
| 216 | */ | ||
| 217 | #define HW_DIGCTL_WRITEONCE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x60)) | ||
| 218 | #define BP_DIGCTL_WRITEONCE_BITS 0 | ||
| 219 | #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff | ||
| 220 | #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 221 | |||
| 222 | /** | ||
| 223 | * Register: HW_DIGCTL_ENTROPY | ||
| 224 | * Address: 0x90 | ||
| 225 | * SCT: no | ||
| 226 | */ | ||
| 227 | #define HW_DIGCTL_ENTROPY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x90)) | ||
| 228 | #define BP_DIGCTL_ENTROPY_VALUE 0 | ||
| 229 | #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff | ||
| 230 | #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 231 | |||
| 232 | /** | ||
| 233 | * Register: HW_DIGCTL_ENTROPY_LATCHED | ||
| 234 | * Address: 0xa0 | ||
| 235 | * SCT: no | ||
| 236 | */ | ||
| 237 | #define HW_DIGCTL_ENTROPY_LATCHED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xa0)) | ||
| 238 | #define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 | ||
| 239 | #define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xffffffff | ||
| 240 | #define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 241 | |||
| 242 | /** | ||
| 243 | * Register: HW_DIGCTL_SJTAGDBG | ||
| 244 | * Address: 0xb0 | ||
| 245 | * SCT: yes | ||
| 246 | */ | ||
| 247 | #define HW_DIGCTL_SJTAGDBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x0)) | ||
| 248 | #define HW_DIGCTL_SJTAGDBG_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x4)) | ||
| 249 | #define HW_DIGCTL_SJTAGDBG_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0x8)) | ||
| 250 | #define HW_DIGCTL_SJTAGDBG_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xb0 + 0xc)) | ||
| 251 | #define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 | ||
| 252 | #define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x7ff0000 | ||
| 253 | #define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) (((v) << 16) & 0x7ff0000) | ||
| 254 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDO 10 | ||
| 255 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x400 | ||
| 256 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v) (((v) << 10) & 0x400) | ||
| 257 | #define BP_DIGCTL_SJTAGDBG_SJTAG_TDI 9 | ||
| 258 | #define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x200 | ||
| 259 | #define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v) (((v) << 9) & 0x200) | ||
| 260 | #define BP_DIGCTL_SJTAGDBG_SJTAG_MODE 8 | ||
| 261 | #define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x100 | ||
| 262 | #define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v) (((v) << 8) & 0x100) | ||
| 263 | #define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 | ||
| 264 | #define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0xf0 | ||
| 265 | #define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) (((v) << 4) & 0xf0) | ||
| 266 | #define BP_DIGCTL_SJTAGDBG_ACTIVE 3 | ||
| 267 | #define BM_DIGCTL_SJTAGDBG_ACTIVE 0x8 | ||
| 268 | #define BF_DIGCTL_SJTAGDBG_ACTIVE(v) (((v) << 3) & 0x8) | ||
| 269 | #define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 2 | ||
| 270 | #define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x4 | ||
| 271 | #define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) (((v) << 2) & 0x4) | ||
| 272 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 1 | ||
| 273 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x2 | ||
| 274 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) (((v) << 1) & 0x2) | ||
| 275 | #define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0 | ||
| 276 | #define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x1 | ||
| 277 | #define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) (((v) << 0) & 0x1) | ||
| 278 | |||
| 279 | /** | ||
| 280 | * Register: HW_DIGCTL_MICROSECONDS | ||
| 281 | * Address: 0xc0 | ||
| 282 | * SCT: yes | ||
| 283 | */ | ||
| 284 | #define HW_DIGCTL_MICROSECONDS (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x0)) | ||
| 285 | #define HW_DIGCTL_MICROSECONDS_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x4)) | ||
| 286 | #define HW_DIGCTL_MICROSECONDS_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0x8)) | ||
| 287 | #define HW_DIGCTL_MICROSECONDS_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xc0 + 0xc)) | ||
| 288 | #define BP_DIGCTL_MICROSECONDS_VALUE 0 | ||
| 289 | #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff | ||
| 290 | #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 291 | |||
| 292 | /** | ||
| 293 | * Register: HW_DIGCTL_DBGRD | ||
| 294 | * Address: 0xd0 | ||
| 295 | * SCT: no | ||
| 296 | */ | ||
| 297 | #define HW_DIGCTL_DBGRD (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xd0)) | ||
| 298 | #define BP_DIGCTL_DBGRD_COMPLEMENT 0 | ||
| 299 | #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff | ||
| 300 | #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) << 0) & 0xffffffff) | ||
| 301 | |||
| 302 | /** | ||
| 303 | * Register: HW_DIGCTL_DBG | ||
| 304 | * Address: 0xe0 | ||
| 305 | * SCT: no | ||
| 306 | */ | ||
| 307 | #define HW_DIGCTL_DBG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xe0)) | ||
| 308 | #define BP_DIGCTL_DBG_VALUE 0 | ||
| 309 | #define BM_DIGCTL_DBG_VALUE 0xffffffff | ||
| 310 | #define BF_DIGCTL_DBG_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 311 | |||
| 312 | /** | ||
| 313 | * Register: HW_DIGCTL_OCRAM_BIST_CSR | ||
| 314 | * Address: 0xf0 | ||
| 315 | * SCT: yes | ||
| 316 | */ | ||
| 317 | #define HW_DIGCTL_OCRAM_BIST_CSR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x0)) | ||
| 318 | #define HW_DIGCTL_OCRAM_BIST_CSR_SET (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x4)) | ||
| 319 | #define HW_DIGCTL_OCRAM_BIST_CSR_CLR (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0x8)) | ||
| 320 | #define HW_DIGCTL_OCRAM_BIST_CSR_TOG (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0xf0 + 0xc)) | ||
| 321 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 9 | ||
| 322 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x200 | ||
| 323 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) (((v) << 9) & 0x200) | ||
| 324 | #define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 8 | ||
| 325 | #define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x100 | ||
| 326 | #define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) (((v) << 8) & 0x100) | ||
| 327 | #define BP_DIGCTL_OCRAM_BIST_CSR_FAIL 3 | ||
| 328 | #define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x8 | ||
| 329 | #define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v) (((v) << 3) & 0x8) | ||
| 330 | #define BP_DIGCTL_OCRAM_BIST_CSR_PASS 2 | ||
| 331 | #define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x4 | ||
| 332 | #define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v) (((v) << 2) & 0x4) | ||
| 333 | #define BP_DIGCTL_OCRAM_BIST_CSR_DONE 1 | ||
| 334 | #define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x2 | ||
| 335 | #define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v) (((v) << 1) & 0x2) | ||
| 336 | #define BP_DIGCTL_OCRAM_BIST_CSR_START 0 | ||
| 337 | #define BM_DIGCTL_OCRAM_BIST_CSR_START 0x1 | ||
| 338 | #define BF_DIGCTL_OCRAM_BIST_CSR_START(v) (((v) << 0) & 0x1) | ||
| 339 | |||
| 340 | /** | ||
| 341 | * Register: HW_DIGCTL_OCRAM_STATUS0 | ||
| 342 | * Address: 0x110 | ||
| 343 | * SCT: no | ||
| 344 | */ | ||
| 345 | #define HW_DIGCTL_OCRAM_STATUS0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x110)) | ||
| 346 | #define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 | ||
| 347 | #define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xffffffff | ||
| 348 | #define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (((v) << 0) & 0xffffffff) | ||
| 349 | |||
| 350 | /** | ||
| 351 | * Register: HW_DIGCTL_OCRAM_STATUS1 | ||
| 352 | * Address: 0x120 | ||
| 353 | * SCT: no | ||
| 354 | */ | ||
| 355 | #define HW_DIGCTL_OCRAM_STATUS1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x120)) | ||
| 356 | #define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 | ||
| 357 | #define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xffffffff | ||
| 358 | #define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (((v) << 0) & 0xffffffff) | ||
| 359 | |||
| 360 | /** | ||
| 361 | * Register: HW_DIGCTL_OCRAM_STATUS2 | ||
| 362 | * Address: 0x130 | ||
| 363 | * SCT: no | ||
| 364 | */ | ||
| 365 | #define HW_DIGCTL_OCRAM_STATUS2 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x130)) | ||
| 366 | #define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 | ||
| 367 | #define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xffffffff | ||
| 368 | #define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (((v) << 0) & 0xffffffff) | ||
| 369 | |||
| 370 | /** | ||
| 371 | * Register: HW_DIGCTL_OCRAM_STATUS3 | ||
| 372 | * Address: 0x140 | ||
| 373 | * SCT: no | ||
| 374 | */ | ||
| 375 | #define HW_DIGCTL_OCRAM_STATUS3 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x140)) | ||
| 376 | #define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 | ||
| 377 | #define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xffffffff | ||
| 378 | #define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (((v) << 0) & 0xffffffff) | ||
| 379 | |||
| 380 | /** | ||
| 381 | * Register: HW_DIGCTL_OCRAM_STATUS4 | ||
| 382 | * Address: 0x150 | ||
| 383 | * SCT: no | ||
| 384 | */ | ||
| 385 | #define HW_DIGCTL_OCRAM_STATUS4 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x150)) | ||
| 386 | #define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 | ||
| 387 | #define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xffffffff | ||
| 388 | #define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (((v) << 0) & 0xffffffff) | ||
| 389 | |||
| 390 | /** | ||
| 391 | * Register: HW_DIGCTL_OCRAM_STATUS5 | ||
| 392 | * Address: 0x160 | ||
| 393 | * SCT: no | ||
| 394 | */ | ||
| 395 | #define HW_DIGCTL_OCRAM_STATUS5 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x160)) | ||
| 396 | #define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 | ||
| 397 | #define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xffffffff | ||
| 398 | #define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (((v) << 0) & 0xffffffff) | ||
| 399 | |||
| 400 | /** | ||
| 401 | * Register: HW_DIGCTL_OCRAM_STATUS6 | ||
| 402 | * Address: 0x170 | ||
| 403 | * SCT: no | ||
| 404 | */ | ||
| 405 | #define HW_DIGCTL_OCRAM_STATUS6 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x170)) | ||
| 406 | #define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 | ||
| 407 | #define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xffffffff | ||
| 408 | #define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (((v) << 0) & 0xffffffff) | ||
| 409 | |||
| 410 | /** | ||
| 411 | * Register: HW_DIGCTL_OCRAM_STATUS7 | ||
| 412 | * Address: 0x180 | ||
| 413 | * SCT: no | ||
| 414 | */ | ||
| 415 | #define HW_DIGCTL_OCRAM_STATUS7 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x180)) | ||
| 416 | #define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 | ||
| 417 | #define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xffffffff | ||
| 418 | #define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (((v) << 0) & 0xffffffff) | ||
| 419 | |||
| 420 | /** | ||
| 421 | * Register: HW_DIGCTL_OCRAM_STATUS8 | ||
| 422 | * Address: 0x190 | ||
| 423 | * SCT: no | ||
| 424 | */ | ||
| 425 | #define HW_DIGCTL_OCRAM_STATUS8 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x190)) | ||
| 426 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 | ||
| 427 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0xffff0000 | ||
| 428 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) (((v) << 16) & 0xffff0000) | ||
| 429 | #define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 | ||
| 430 | #define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0xffff | ||
| 431 | #define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) (((v) << 0) & 0xffff) | ||
| 432 | |||
| 433 | /** | ||
| 434 | * Register: HW_DIGCTL_OCRAM_STATUS9 | ||
| 435 | * Address: 0x1a0 | ||
| 436 | * SCT: no | ||
| 437 | */ | ||
| 438 | #define HW_DIGCTL_OCRAM_STATUS9 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1a0)) | ||
| 439 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 | ||
| 440 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0xffff0000 | ||
| 441 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) (((v) << 16) & 0xffff0000) | ||
| 442 | #define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 | ||
| 443 | #define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0xffff | ||
| 444 | #define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) (((v) << 0) & 0xffff) | ||
| 445 | |||
| 446 | /** | ||
| 447 | * Register: HW_DIGCTL_OCRAM_STATUS10 | ||
| 448 | * Address: 0x1b0 | ||
| 449 | * SCT: no | ||
| 450 | */ | ||
| 451 | #define HW_DIGCTL_OCRAM_STATUS10 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1b0)) | ||
| 452 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 | ||
| 453 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0xffff0000 | ||
| 454 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) (((v) << 16) & 0xffff0000) | ||
| 455 | #define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 | ||
| 456 | #define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0xffff | ||
| 457 | #define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) (((v) << 0) & 0xffff) | ||
| 458 | |||
| 459 | /** | ||
| 460 | * Register: HW_DIGCTL_OCRAM_STATUS11 | ||
| 461 | * Address: 0x1c0 | ||
| 462 | * SCT: no | ||
| 463 | */ | ||
| 464 | #define HW_DIGCTL_OCRAM_STATUS11 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1c0)) | ||
| 465 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 | ||
| 466 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0xffff0000 | ||
| 467 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) (((v) << 16) & 0xffff0000) | ||
| 468 | #define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 | ||
| 469 | #define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0xffff | ||
| 470 | #define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) (((v) << 0) & 0xffff) | ||
| 471 | |||
| 472 | /** | ||
| 473 | * Register: HW_DIGCTL_OCRAM_STATUS12 | ||
| 474 | * Address: 0x1d0 | ||
| 475 | * SCT: no | ||
| 476 | */ | ||
| 477 | #define HW_DIGCTL_OCRAM_STATUS12 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1d0)) | ||
| 478 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 | ||
| 479 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x1f000000 | ||
| 480 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) << 24) & 0x1f000000) | ||
| 481 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 | ||
| 482 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x1f0000 | ||
| 483 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) << 16) & 0x1f0000) | ||
| 484 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 | ||
| 485 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x1f00 | ||
| 486 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) << 8) & 0x1f00) | ||
| 487 | #define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 | ||
| 488 | #define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x1f | ||
| 489 | #define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) << 0) & 0x1f) | ||
| 490 | |||
| 491 | /** | ||
| 492 | * Register: HW_DIGCTL_OCRAM_STATUS13 | ||
| 493 | * Address: 0x1e0 | ||
| 494 | * SCT: no | ||
| 495 | */ | ||
| 496 | #define HW_DIGCTL_OCRAM_STATUS13 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x1e0)) | ||
| 497 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 | ||
| 498 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x1f000000 | ||
| 499 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) << 24) & 0x1f000000) | ||
| 500 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 | ||
| 501 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x1f0000 | ||
| 502 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) << 16) & 0x1f0000) | ||
| 503 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 | ||
| 504 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x1f00 | ||
| 505 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) << 8) & 0x1f00) | ||
| 506 | #define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 | ||
| 507 | #define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x1f | ||
| 508 | #define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) << 0) & 0x1f) | ||
| 509 | |||
| 510 | /** | ||
| 511 | * Register: HW_DIGCTL_SCRATCH0 | ||
| 512 | * Address: 0x290 | ||
| 513 | * SCT: no | ||
| 514 | */ | ||
| 515 | #define HW_DIGCTL_SCRATCH0 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x290)) | ||
| 516 | #define BP_DIGCTL_SCRATCH0_PTR 0 | ||
| 517 | #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff | ||
| 518 | #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) << 0) & 0xffffffff) | ||
| 519 | |||
| 520 | /** | ||
| 521 | * Register: HW_DIGCTL_SCRATCH1 | ||
| 522 | * Address: 0x2a0 | ||
| 523 | * SCT: no | ||
| 524 | */ | ||
| 525 | #define HW_DIGCTL_SCRATCH1 (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2a0)) | ||
| 526 | #define BP_DIGCTL_SCRATCH1_PTR 0 | ||
| 527 | #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff | ||
| 528 | #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) << 0) & 0xffffffff) | ||
| 529 | |||
| 530 | /** | ||
| 531 | * Register: HW_DIGCTL_ARMCACHE | ||
| 532 | * Address: 0x2b0 | ||
| 533 | * SCT: no | ||
| 534 | */ | ||
| 535 | #define HW_DIGCTL_ARMCACHE (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2b0)) | ||
| 536 | #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 | ||
| 537 | #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 | ||
| 538 | #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) << 8) & 0x300) | ||
| 539 | #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 | ||
| 540 | #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 | ||
| 541 | #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) << 4) & 0x30) | ||
| 542 | #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 | ||
| 543 | #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 | ||
| 544 | #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) << 0) & 0x3) | ||
| 545 | |||
| 546 | /** | ||
| 547 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_LOW | ||
| 548 | * Address: 0x2c0 | ||
| 549 | * SCT: no | ||
| 550 | */ | ||
| 551 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2c0)) | ||
| 552 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 | ||
| 553 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xffffffff | ||
| 554 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 555 | |||
| 556 | /** | ||
| 557 | * Register: HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH | ||
| 558 | * Address: 0x2d0 | ||
| 559 | * SCT: no | ||
| 560 | */ | ||
| 561 | #define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x2d0)) | ||
| 562 | #define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 | ||
| 563 | #define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xffffffff | ||
| 564 | #define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (((v) << 0) & 0xffffffff) | ||
| 565 | |||
| 566 | /** | ||
| 567 | * Register: HW_DIGCTL_SGTL | ||
| 568 | * Address: 0x300 | ||
| 569 | * SCT: no | ||
| 570 | */ | ||
| 571 | #define HW_DIGCTL_SGTL (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x300)) | ||
| 572 | #define BP_DIGCTL_SGTL_COPYRIGHT 0 | ||
| 573 | #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff | ||
| 574 | #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) << 0) & 0xffffffff) | ||
| 575 | |||
| 576 | /** | ||
| 577 | * Register: HW_DIGCTL_CHIPID | ||
| 578 | * Address: 0x310 | ||
| 579 | * SCT: no | ||
| 580 | */ | ||
| 581 | #define HW_DIGCTL_CHIPID (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x310)) | ||
| 582 | #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 | ||
| 583 | #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 | ||
| 584 | #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) << 16) & 0xffff0000) | ||
| 585 | #define BP_DIGCTL_CHIPID_REVISION 0 | ||
| 586 | #define BM_DIGCTL_CHIPID_REVISION 0xff | ||
| 587 | #define BF_DIGCTL_CHIPID_REVISION(v) (((v) << 0) & 0xff) | ||
| 588 | |||
| 589 | /** | ||
| 590 | * Register: HW_DIGCTL_AHB_STATS_SELECT | ||
| 591 | * Address: 0x330 | ||
| 592 | * SCT: no | ||
| 593 | */ | ||
| 594 | #define HW_DIGCTL_AHB_STATS_SELECT (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x330)) | ||
| 595 | #define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 | ||
| 596 | #define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0xf000000 | ||
| 597 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 | ||
| 598 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 | ||
| 599 | #define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 | ||
| 600 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) (((v) << 24) & 0xf000000) | ||
| 601 | #define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##v << 24) & 0xf000000) | ||
| 602 | #define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 | ||
| 603 | #define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0xf0000 | ||
| 604 | #define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 | ||
| 605 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) (((v) << 16) & 0xf0000) | ||
| 606 | #define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##v << 16) & 0xf0000) | ||
| 607 | #define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 | ||
| 608 | #define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0xf00 | ||
| 609 | #define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 | ||
| 610 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) (((v) << 8) & 0xf00) | ||
| 611 | #define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##v << 8) & 0xf00) | ||
| 612 | #define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 | ||
| 613 | #define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0xf | ||
| 614 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 | ||
| 615 | #define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 | ||
| 616 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) (((v) << 0) & 0xf) | ||
| 617 | #define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v) ((BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##v << 0) & 0xf) | ||
| 618 | |||
| 619 | /** | ||
| 620 | * Register: HW_DIGCTL_L0_AHB_ACTIVE_CYCLES | ||
| 621 | * Address: 0x340 | ||
| 622 | * SCT: no | ||
| 623 | */ | ||
| 624 | #define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x340)) | ||
| 625 | #define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 | ||
| 626 | #define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
| 627 | #define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 628 | |||
| 629 | /** | ||
| 630 | * Register: HW_DIGCTL_L0_AHB_DATA_STALLED | ||
| 631 | * Address: 0x350 | ||
| 632 | * SCT: no | ||
| 633 | */ | ||
| 634 | #define HW_DIGCTL_L0_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x350)) | ||
| 635 | #define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 | ||
| 636 | #define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xffffffff | ||
| 637 | #define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 638 | |||
| 639 | /** | ||
| 640 | * Register: HW_DIGCTL_L0_AHB_DATA_CYCLES | ||
| 641 | * Address: 0x360 | ||
| 642 | * SCT: no | ||
| 643 | */ | ||
| 644 | #define HW_DIGCTL_L0_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x360)) | ||
| 645 | #define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 | ||
| 646 | #define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
| 647 | #define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 648 | |||
| 649 | /** | ||
| 650 | * Register: HW_DIGCTL_L1_AHB_ACTIVE_CYCLES | ||
| 651 | * Address: 0x370 | ||
| 652 | * SCT: no | ||
| 653 | */ | ||
| 654 | #define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x370)) | ||
| 655 | #define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 | ||
| 656 | #define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
| 657 | #define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 658 | |||
| 659 | /** | ||
| 660 | * Register: HW_DIGCTL_L1_AHB_DATA_STALLED | ||
| 661 | * Address: 0x380 | ||
| 662 | * SCT: no | ||
| 663 | */ | ||
| 664 | #define HW_DIGCTL_L1_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x380)) | ||
| 665 | #define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 | ||
| 666 | #define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xffffffff | ||
| 667 | #define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 668 | |||
| 669 | /** | ||
| 670 | * Register: HW_DIGCTL_L1_AHB_DATA_CYCLES | ||
| 671 | * Address: 0x390 | ||
| 672 | * SCT: no | ||
| 673 | */ | ||
| 674 | #define HW_DIGCTL_L1_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x390)) | ||
| 675 | #define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 | ||
| 676 | #define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
| 677 | #define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 678 | |||
| 679 | /** | ||
| 680 | * Register: HW_DIGCTL_L2_AHB_ACTIVE_CYCLES | ||
| 681 | * Address: 0x3a0 | ||
| 682 | * SCT: no | ||
| 683 | */ | ||
| 684 | #define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3a0)) | ||
| 685 | #define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 | ||
| 686 | #define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
| 687 | #define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 688 | |||
| 689 | /** | ||
| 690 | * Register: HW_DIGCTL_L2_AHB_DATA_STALLED | ||
| 691 | * Address: 0x3b0 | ||
| 692 | * SCT: no | ||
| 693 | */ | ||
| 694 | #define HW_DIGCTL_L2_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3b0)) | ||
| 695 | #define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 | ||
| 696 | #define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xffffffff | ||
| 697 | #define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 698 | |||
| 699 | /** | ||
| 700 | * Register: HW_DIGCTL_L2_AHB_DATA_CYCLES | ||
| 701 | * Address: 0x3c0 | ||
| 702 | * SCT: no | ||
| 703 | */ | ||
| 704 | #define HW_DIGCTL_L2_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3c0)) | ||
| 705 | #define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 | ||
| 706 | #define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
| 707 | #define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 708 | |||
| 709 | /** | ||
| 710 | * Register: HW_DIGCTL_L3_AHB_ACTIVE_CYCLES | ||
| 711 | * Address: 0x3d0 | ||
| 712 | * SCT: no | ||
| 713 | */ | ||
| 714 | #define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3d0)) | ||
| 715 | #define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 | ||
| 716 | #define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xffffffff | ||
| 717 | #define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 718 | |||
| 719 | /** | ||
| 720 | * Register: HW_DIGCTL_L3_AHB_DATA_STALLED | ||
| 721 | * Address: 0x3e0 | ||
| 722 | * SCT: no | ||
| 723 | */ | ||
| 724 | #define HW_DIGCTL_L3_AHB_DATA_STALLED (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3e0)) | ||
| 725 | #define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 | ||
| 726 | #define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xffffffff | ||
| 727 | #define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 728 | |||
| 729 | /** | ||
| 730 | * Register: HW_DIGCTL_L3_AHB_DATA_CYCLES | ||
| 731 | * Address: 0x3f0 | ||
| 732 | * SCT: no | ||
| 733 | */ | ||
| 734 | #define HW_DIGCTL_L3_AHB_DATA_CYCLES (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x3f0)) | ||
| 735 | #define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 | ||
| 736 | #define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xffffffff | ||
| 737 | #define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 738 | |||
| 739 | /** | ||
| 740 | * Register: HW_DIGCTL_MPTEn_LOC | ||
| 741 | * Address: 0x400+n*0x10 | ||
| 742 | * SCT: no | ||
| 743 | */ | ||
| 744 | #define HW_DIGCTL_MPTEn_LOC(n) (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x400+(n)*0x10)) | ||
| 745 | #define BP_DIGCTL_MPTEn_LOC_LOC 0 | ||
| 746 | #define BM_DIGCTL_MPTEn_LOC_LOC 0xfff | ||
| 747 | #define BF_DIGCTL_MPTEn_LOC_LOC(v) (((v) << 0) & 0xfff) | ||
| 748 | |||
| 749 | /** | ||
| 750 | * Register: HW_DIGCTL_EMICLK_DELAY | ||
| 751 | * Address: 0x480 | ||
| 752 | * SCT: no | ||
| 753 | */ | ||
| 754 | #define HW_DIGCTL_EMICLK_DELAY (*(volatile unsigned long *)(REGS_DIGCTL_BASE + 0x480)) | ||
| 755 | #define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 | ||
| 756 | #define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x1f | ||
| 757 | #define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) (((v) << 0) & 0x1f) | ||
| 758 | |||
| 759 | #endif /* __HEADERGEN__STMP3700__DIGCTL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h new file mode 100644 index 0000000000..7ec44c41ee --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dram.h | |||
| @@ -0,0 +1,671 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__DRAM__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__DRAM__H__ | ||
| 25 | |||
| 26 | #define REGS_DRAM_BASE (0x800e0000) | ||
| 27 | |||
| 28 | #define REGS_DRAM_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_DRAM_CTL00 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: no | ||
| 34 | */ | ||
| 35 | #define HW_DRAM_CTL00 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x0)) | ||
| 36 | #define BP_DRAM_CTL00_AHB0_W_PRIORITY 24 | ||
| 37 | #define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x1000000 | ||
| 38 | #define BF_DRAM_CTL00_AHB0_W_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
| 39 | #define BP_DRAM_CTL00_AHB0_R_PRIORITY 16 | ||
| 40 | #define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x10000 | ||
| 41 | #define BF_DRAM_CTL00_AHB0_R_PRIORITY(v) (((v) << 16) & 0x10000) | ||
| 42 | #define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG 8 | ||
| 43 | #define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x100 | ||
| 44 | #define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) << 8) & 0x100) | ||
| 45 | #define BP_DRAM_CTL00_ADDR_CMP_EN 0 | ||
| 46 | #define BM_DRAM_CTL00_ADDR_CMP_EN 0x1 | ||
| 47 | #define BF_DRAM_CTL00_ADDR_CMP_EN(v) (((v) << 0) & 0x1) | ||
| 48 | |||
| 49 | /** | ||
| 50 | * Register: HW_DRAM_CTL01 | ||
| 51 | * Address: 0x4 | ||
| 52 | * SCT: no | ||
| 53 | */ | ||
| 54 | #define HW_DRAM_CTL01 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4)) | ||
| 55 | #define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG 24 | ||
| 56 | #define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x1000000 | ||
| 57 | #define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) << 24) & 0x1000000) | ||
| 58 | #define BP_DRAM_CTL01_AHB1_W_PRIORITY 16 | ||
| 59 | #define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x10000 | ||
| 60 | #define BF_DRAM_CTL01_AHB1_W_PRIORITY(v) (((v) << 16) & 0x10000) | ||
| 61 | #define BP_DRAM_CTL01_AHB1_R_PRIORITY 8 | ||
| 62 | #define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x100 | ||
| 63 | #define BF_DRAM_CTL01_AHB1_R_PRIORITY(v) (((v) << 8) & 0x100) | ||
| 64 | #define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0 | ||
| 65 | #define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x1 | ||
| 66 | #define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) << 0) & 0x1) | ||
| 67 | |||
| 68 | /** | ||
| 69 | * Register: HW_DRAM_CTL02 | ||
| 70 | * Address: 0x8 | ||
| 71 | * SCT: no | ||
| 72 | */ | ||
| 73 | #define HW_DRAM_CTL02 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8)) | ||
| 74 | #define BP_DRAM_CTL02_AHB3_R_PRIORITY 24 | ||
| 75 | #define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x1000000 | ||
| 76 | #define BF_DRAM_CTL02_AHB3_R_PRIORITY(v) (((v) << 24) & 0x1000000) | ||
| 77 | #define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG 16 | ||
| 78 | #define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x10000 | ||
| 79 | #define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) << 16) & 0x10000) | ||
| 80 | #define BP_DRAM_CTL02_AHB2_W_PRIORITY 8 | ||
| 81 | #define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x100 | ||
| 82 | #define BF_DRAM_CTL02_AHB2_W_PRIORITY(v) (((v) << 8) & 0x100) | ||
| 83 | #define BP_DRAM_CTL02_AHB2_R_PRIORITY 0 | ||
| 84 | #define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x1 | ||
| 85 | #define BF_DRAM_CTL02_AHB2_R_PRIORITY(v) (((v) << 0) & 0x1) | ||
| 86 | |||
| 87 | /** | ||
| 88 | * Register: HW_DRAM_CTL03 | ||
| 89 | * Address: 0xc | ||
| 90 | * SCT: no | ||
| 91 | */ | ||
| 92 | #define HW_DRAM_CTL03 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xc)) | ||
| 93 | #define BP_DRAM_CTL03_AUTO_REFRESH_MODE 24 | ||
| 94 | #define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x1000000 | ||
| 95 | #define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v) (((v) << 24) & 0x1000000) | ||
| 96 | #define BP_DRAM_CTL03_AREFRESH 16 | ||
| 97 | #define BM_DRAM_CTL03_AREFRESH 0x10000 | ||
| 98 | #define BF_DRAM_CTL03_AREFRESH(v) (((v) << 16) & 0x10000) | ||
| 99 | #define BP_DRAM_CTL03_AP 8 | ||
| 100 | #define BM_DRAM_CTL03_AP 0x100 | ||
| 101 | #define BF_DRAM_CTL03_AP(v) (((v) << 8) & 0x100) | ||
| 102 | #define BP_DRAM_CTL03_AHB3_W_PRIORITY 0 | ||
| 103 | #define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x1 | ||
| 104 | #define BF_DRAM_CTL03_AHB3_W_PRIORITY(v) (((v) << 0) & 0x1) | ||
| 105 | |||
| 106 | /** | ||
| 107 | * Register: HW_DRAM_CTL04 | ||
| 108 | * Address: 0x10 | ||
| 109 | * SCT: no | ||
| 110 | */ | ||
| 111 | #define HW_DRAM_CTL04 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x10)) | ||
| 112 | #define BP_DRAM_CTL04_DLL_BYPASS_MODE 24 | ||
| 113 | #define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x1000000 | ||
| 114 | #define BF_DRAM_CTL04_DLL_BYPASS_MODE(v) (((v) << 24) & 0x1000000) | ||
| 115 | #define BP_DRAM_CTL04_DLLLOCKREG 16 | ||
| 116 | #define BM_DRAM_CTL04_DLLLOCKREG 0x10000 | ||
| 117 | #define BF_DRAM_CTL04_DLLLOCKREG(v) (((v) << 16) & 0x10000) | ||
| 118 | #define BP_DRAM_CTL04_CONCURRENTAP 8 | ||
| 119 | #define BM_DRAM_CTL04_CONCURRENTAP 0x100 | ||
| 120 | #define BF_DRAM_CTL04_CONCURRENTAP(v) (((v) << 8) & 0x100) | ||
| 121 | #define BP_DRAM_CTL04_BANK_SPLIT_EN 0 | ||
| 122 | #define BM_DRAM_CTL04_BANK_SPLIT_EN 0x1 | ||
| 123 | #define BF_DRAM_CTL04_BANK_SPLIT_EN(v) (((v) << 0) & 0x1) | ||
| 124 | |||
| 125 | /** | ||
| 126 | * Register: HW_DRAM_CTL05 | ||
| 127 | * Address: 0x14 | ||
| 128 | * SCT: no | ||
| 129 | */ | ||
| 130 | #define HW_DRAM_CTL05 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x14)) | ||
| 131 | #define BP_DRAM_CTL05_INTRPTREADA 24 | ||
| 132 | #define BM_DRAM_CTL05_INTRPTREADA 0x1000000 | ||
| 133 | #define BF_DRAM_CTL05_INTRPTREADA(v) (((v) << 24) & 0x1000000) | ||
| 134 | #define BP_DRAM_CTL05_INTRPTAPBURST 16 | ||
| 135 | #define BM_DRAM_CTL05_INTRPTAPBURST 0x10000 | ||
| 136 | #define BF_DRAM_CTL05_INTRPTAPBURST(v) (((v) << 16) & 0x10000) | ||
| 137 | #define BP_DRAM_CTL05_FAST_WRITE 8 | ||
| 138 | #define BM_DRAM_CTL05_FAST_WRITE 0x100 | ||
| 139 | #define BF_DRAM_CTL05_FAST_WRITE(v) (((v) << 8) & 0x100) | ||
| 140 | #define BP_DRAM_CTL05_EN_LOWPOWER_MODE 0 | ||
| 141 | #define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x1 | ||
| 142 | #define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v) (((v) << 0) & 0x1) | ||
| 143 | |||
| 144 | /** | ||
| 145 | * Register: HW_DRAM_CTL06 | ||
| 146 | * Address: 0x18 | ||
| 147 | * SCT: no | ||
| 148 | */ | ||
| 149 | #define HW_DRAM_CTL06 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x18)) | ||
| 150 | #define BP_DRAM_CTL06_POWER_DOWN 24 | ||
| 151 | #define BM_DRAM_CTL06_POWER_DOWN 0x1000000 | ||
| 152 | #define BF_DRAM_CTL06_POWER_DOWN(v) (((v) << 24) & 0x1000000) | ||
| 153 | #define BP_DRAM_CTL06_PLACEMENT_EN 16 | ||
| 154 | #define BM_DRAM_CTL06_PLACEMENT_EN 0x10000 | ||
| 155 | #define BF_DRAM_CTL06_PLACEMENT_EN(v) (((v) << 16) & 0x10000) | ||
| 156 | #define BP_DRAM_CTL06_NO_CMD_INIT 8 | ||
| 157 | #define BM_DRAM_CTL06_NO_CMD_INIT 0x100 | ||
| 158 | #define BF_DRAM_CTL06_NO_CMD_INIT(v) (((v) << 8) & 0x100) | ||
| 159 | #define BP_DRAM_CTL06_INTRPTWRITEA 0 | ||
| 160 | #define BM_DRAM_CTL06_INTRPTWRITEA 0x1 | ||
| 161 | #define BF_DRAM_CTL06_INTRPTWRITEA(v) (((v) << 0) & 0x1) | ||
| 162 | |||
| 163 | /** | ||
| 164 | * Register: HW_DRAM_CTL07 | ||
| 165 | * Address: 0x1c | ||
| 166 | * SCT: no | ||
| 167 | */ | ||
| 168 | #define HW_DRAM_CTL07 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x1c)) | ||
| 169 | #define BP_DRAM_CTL07_RW_SAME_EN 24 | ||
| 170 | #define BM_DRAM_CTL07_RW_SAME_EN 0x1000000 | ||
| 171 | #define BF_DRAM_CTL07_RW_SAME_EN(v) (((v) << 24) & 0x1000000) | ||
| 172 | #define BP_DRAM_CTL07_REG_DIMM_ENABLE 16 | ||
| 173 | #define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x10000 | ||
| 174 | #define BF_DRAM_CTL07_REG_DIMM_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 175 | #define BP_DRAM_CTL07_RD2RD_TURN 8 | ||
| 176 | #define BM_DRAM_CTL07_RD2RD_TURN 0x100 | ||
| 177 | #define BF_DRAM_CTL07_RD2RD_TURN(v) (((v) << 8) & 0x100) | ||
| 178 | #define BP_DRAM_CTL07_PRIORITY_EN 0 | ||
| 179 | #define BM_DRAM_CTL07_PRIORITY_EN 0x1 | ||
| 180 | #define BF_DRAM_CTL07_PRIORITY_EN(v) (((v) << 0) & 0x1) | ||
| 181 | |||
| 182 | /** | ||
| 183 | * Register: HW_DRAM_CTL08 | ||
| 184 | * Address: 0x20 | ||
| 185 | * SCT: no | ||
| 186 | */ | ||
| 187 | #define HW_DRAM_CTL08 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x20)) | ||
| 188 | #define BP_DRAM_CTL08_TRAS_LOCKOUT 24 | ||
| 189 | #define BM_DRAM_CTL08_TRAS_LOCKOUT 0x1000000 | ||
| 190 | #define BF_DRAM_CTL08_TRAS_LOCKOUT(v) (((v) << 24) & 0x1000000) | ||
| 191 | #define BP_DRAM_CTL08_START 16 | ||
| 192 | #define BM_DRAM_CTL08_START 0x10000 | ||
| 193 | #define BF_DRAM_CTL08_START(v) (((v) << 16) & 0x10000) | ||
| 194 | #define BP_DRAM_CTL08_SREFRESH 8 | ||
| 195 | #define BM_DRAM_CTL08_SREFRESH 0x100 | ||
| 196 | #define BF_DRAM_CTL08_SREFRESH(v) (((v) << 8) & 0x100) | ||
| 197 | #define BP_DRAM_CTL08_SDR_MODE 0 | ||
| 198 | #define BM_DRAM_CTL08_SDR_MODE 0x1 | ||
| 199 | #define BF_DRAM_CTL08_SDR_MODE(v) (((v) << 0) & 0x1) | ||
| 200 | |||
| 201 | /** | ||
| 202 | * Register: HW_DRAM_CTL09 | ||
| 203 | * Address: 0x24 | ||
| 204 | * SCT: no | ||
| 205 | */ | ||
| 206 | #define HW_DRAM_CTL09 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x24)) | ||
| 207 | #define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24 | ||
| 208 | #define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x3000000 | ||
| 209 | #define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) (((v) << 24) & 0x3000000) | ||
| 210 | #define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16 | ||
| 211 | #define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x30000 | ||
| 212 | #define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) << 16) & 0x30000) | ||
| 213 | #define BP_DRAM_CTL09_WRITE_MODEREG 8 | ||
| 214 | #define BM_DRAM_CTL09_WRITE_MODEREG 0x100 | ||
| 215 | #define BF_DRAM_CTL09_WRITE_MODEREG(v) (((v) << 8) & 0x100) | ||
| 216 | #define BP_DRAM_CTL09_WRITEINTERP 0 | ||
| 217 | #define BM_DRAM_CTL09_WRITEINTERP 0x1 | ||
| 218 | #define BF_DRAM_CTL09_WRITEINTERP(v) (((v) << 0) & 0x1) | ||
| 219 | |||
| 220 | /** | ||
| 221 | * Register: HW_DRAM_CTL10 | ||
| 222 | * Address: 0x28 | ||
| 223 | * SCT: no | ||
| 224 | */ | ||
| 225 | #define HW_DRAM_CTL10 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x28)) | ||
| 226 | #define BP_DRAM_CTL10_AGE_COUNT 24 | ||
| 227 | #define BM_DRAM_CTL10_AGE_COUNT 0x7000000 | ||
| 228 | #define BF_DRAM_CTL10_AGE_COUNT(v) (((v) << 24) & 0x7000000) | ||
| 229 | #define BP_DRAM_CTL10_ADDR_PINS 16 | ||
| 230 | #define BM_DRAM_CTL10_ADDR_PINS 0x70000 | ||
| 231 | #define BF_DRAM_CTL10_ADDR_PINS(v) (((v) << 16) & 0x70000) | ||
| 232 | #define BP_DRAM_CTL10_TEMRS 8 | ||
| 233 | #define BM_DRAM_CTL10_TEMRS 0x300 | ||
| 234 | #define BF_DRAM_CTL10_TEMRS(v) (((v) << 8) & 0x300) | ||
| 235 | #define BP_DRAM_CTL10_Q_FULLNESS 0 | ||
| 236 | #define BM_DRAM_CTL10_Q_FULLNESS 0x3 | ||
| 237 | #define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) << 0) & 0x3) | ||
| 238 | |||
| 239 | /** | ||
| 240 | * Register: HW_DRAM_CTL11 | ||
| 241 | * Address: 0x2c | ||
| 242 | * SCT: no | ||
| 243 | */ | ||
| 244 | #define HW_DRAM_CTL11 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x2c)) | ||
| 245 | #define BP_DRAM_CTL11_MAX_CS_REG 24 | ||
| 246 | #define BM_DRAM_CTL11_MAX_CS_REG 0x7000000 | ||
| 247 | #define BF_DRAM_CTL11_MAX_CS_REG(v) (((v) << 24) & 0x7000000) | ||
| 248 | #define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16 | ||
| 249 | #define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x70000 | ||
| 250 | #define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) (((v) << 16) & 0x70000) | ||
| 251 | #define BP_DRAM_CTL11_COLUMN_SIZE 8 | ||
| 252 | #define BM_DRAM_CTL11_COLUMN_SIZE 0x700 | ||
| 253 | #define BF_DRAM_CTL11_COLUMN_SIZE(v) (((v) << 8) & 0x700) | ||
| 254 | #define BP_DRAM_CTL11_CASLAT 0 | ||
| 255 | #define BM_DRAM_CTL11_CASLAT 0x7 | ||
| 256 | #define BF_DRAM_CTL11_CASLAT(v) (((v) << 0) & 0x7) | ||
| 257 | |||
| 258 | /** | ||
| 259 | * Register: HW_DRAM_CTL12 | ||
| 260 | * Address: 0x30 | ||
| 261 | * SCT: no | ||
| 262 | */ | ||
| 263 | #define HW_DRAM_CTL12 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x30)) | ||
| 264 | #define BP_DRAM_CTL12_TWR_INT 24 | ||
| 265 | #define BM_DRAM_CTL12_TWR_INT 0x7000000 | ||
| 266 | #define BF_DRAM_CTL12_TWR_INT(v) (((v) << 24) & 0x7000000) | ||
| 267 | #define BP_DRAM_CTL12_TRRD 16 | ||
| 268 | #define BM_DRAM_CTL12_TRRD 0x70000 | ||
| 269 | #define BF_DRAM_CTL12_TRRD(v) (((v) << 16) & 0x70000) | ||
| 270 | #define BP_DRAM_CTL12_TCKE 0 | ||
| 271 | #define BM_DRAM_CTL12_TCKE 0x7 | ||
| 272 | #define BF_DRAM_CTL12_TCKE(v) (((v) << 0) & 0x7) | ||
| 273 | |||
| 274 | /** | ||
| 275 | * Register: HW_DRAM_CTL13 | ||
| 276 | * Address: 0x34 | ||
| 277 | * SCT: no | ||
| 278 | */ | ||
| 279 | #define HW_DRAM_CTL13 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x34)) | ||
| 280 | #define BP_DRAM_CTL13_CASLAT_LIN_GATE 24 | ||
| 281 | #define BM_DRAM_CTL13_CASLAT_LIN_GATE 0xf000000 | ||
| 282 | #define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) (((v) << 24) & 0xf000000) | ||
| 283 | #define BP_DRAM_CTL13_CASLAT_LIN 16 | ||
| 284 | #define BM_DRAM_CTL13_CASLAT_LIN 0xf0000 | ||
| 285 | #define BF_DRAM_CTL13_CASLAT_LIN(v) (((v) << 16) & 0xf0000) | ||
| 286 | #define BP_DRAM_CTL13_APREBIT 8 | ||
| 287 | #define BM_DRAM_CTL13_APREBIT 0xf00 | ||
| 288 | #define BF_DRAM_CTL13_APREBIT(v) (((v) << 8) & 0xf00) | ||
| 289 | #define BP_DRAM_CTL13_TWTR 0 | ||
| 290 | #define BM_DRAM_CTL13_TWTR 0x7 | ||
| 291 | #define BF_DRAM_CTL13_TWTR(v) (((v) << 0) & 0x7) | ||
| 292 | |||
| 293 | /** | ||
| 294 | * Register: HW_DRAM_CTL14 | ||
| 295 | * Address: 0x38 | ||
| 296 | * SCT: no | ||
| 297 | */ | ||
| 298 | #define HW_DRAM_CTL14 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x38)) | ||
| 299 | #define BP_DRAM_CTL14_MAX_COL_REG 24 | ||
| 300 | #define BM_DRAM_CTL14_MAX_COL_REG 0xf000000 | ||
| 301 | #define BF_DRAM_CTL14_MAX_COL_REG(v) (((v) << 24) & 0xf000000) | ||
| 302 | #define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16 | ||
| 303 | #define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0xf0000 | ||
| 304 | #define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) (((v) << 16) & 0xf0000) | ||
| 305 | #define BP_DRAM_CTL14_INITAREF 8 | ||
| 306 | #define BM_DRAM_CTL14_INITAREF 0xf00 | ||
| 307 | #define BF_DRAM_CTL14_INITAREF(v) (((v) << 8) & 0xf00) | ||
| 308 | #define BP_DRAM_CTL14_CS_MAP 0 | ||
| 309 | #define BM_DRAM_CTL14_CS_MAP 0xf | ||
| 310 | #define BF_DRAM_CTL14_CS_MAP(v) (((v) << 0) & 0xf) | ||
| 311 | |||
| 312 | /** | ||
| 313 | * Register: HW_DRAM_CTL15 | ||
| 314 | * Address: 0x3c | ||
| 315 | * SCT: no | ||
| 316 | */ | ||
| 317 | #define HW_DRAM_CTL15 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x3c)) | ||
| 318 | #define BP_DRAM_CTL15_TRP 24 | ||
| 319 | #define BM_DRAM_CTL15_TRP 0xf000000 | ||
| 320 | #define BF_DRAM_CTL15_TRP(v) (((v) << 24) & 0xf000000) | ||
| 321 | #define BP_DRAM_CTL15_TDAL 16 | ||
| 322 | #define BM_DRAM_CTL15_TDAL 0xf0000 | ||
| 323 | #define BF_DRAM_CTL15_TDAL(v) (((v) << 16) & 0xf0000) | ||
| 324 | #define BP_DRAM_CTL15_PORT_BUSY 8 | ||
| 325 | #define BM_DRAM_CTL15_PORT_BUSY 0xf00 | ||
| 326 | #define BF_DRAM_CTL15_PORT_BUSY(v) (((v) << 8) & 0xf00) | ||
| 327 | #define BP_DRAM_CTL15_MAX_ROW_REG 0 | ||
| 328 | #define BM_DRAM_CTL15_MAX_ROW_REG 0xf | ||
| 329 | #define BF_DRAM_CTL15_MAX_ROW_REG(v) (((v) << 0) & 0xf) | ||
| 330 | |||
| 331 | /** | ||
| 332 | * Register: HW_DRAM_CTL16 | ||
| 333 | * Address: 0x40 | ||
| 334 | * SCT: no | ||
| 335 | */ | ||
| 336 | #define HW_DRAM_CTL16 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x40)) | ||
| 337 | #define BP_DRAM_CTL16_TMRD 24 | ||
| 338 | #define BM_DRAM_CTL16_TMRD 0x1f000000 | ||
| 339 | #define BF_DRAM_CTL16_TMRD(v) (((v) << 24) & 0x1f000000) | ||
| 340 | #define BP_DRAM_CTL16_LOWPOWER_CONTROL 16 | ||
| 341 | #define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x1f0000 | ||
| 342 | #define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) (((v) << 16) & 0x1f0000) | ||
| 343 | #define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8 | ||
| 344 | #define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x1f00 | ||
| 345 | #define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) (((v) << 8) & 0x1f00) | ||
| 346 | #define BP_DRAM_CTL16_INT_ACK 0 | ||
| 347 | #define BM_DRAM_CTL16_INT_ACK 0xf | ||
| 348 | #define BF_DRAM_CTL16_INT_ACK(v) (((v) << 0) & 0xf) | ||
| 349 | |||
| 350 | /** | ||
| 351 | * Register: HW_DRAM_CTL17 | ||
| 352 | * Address: 0x44 | ||
| 353 | * SCT: no | ||
| 354 | */ | ||
| 355 | #define HW_DRAM_CTL17 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x44)) | ||
| 356 | #define BP_DRAM_CTL17_DLL_START_POINT 24 | ||
| 357 | #define BM_DRAM_CTL17_DLL_START_POINT 0xff000000 | ||
| 358 | #define BF_DRAM_CTL17_DLL_START_POINT(v) (((v) << 24) & 0xff000000) | ||
| 359 | #define BP_DRAM_CTL17_DLL_LOCK 16 | ||
| 360 | #define BM_DRAM_CTL17_DLL_LOCK 0xff0000 | ||
| 361 | #define BF_DRAM_CTL17_DLL_LOCK(v) (((v) << 16) & 0xff0000) | ||
| 362 | #define BP_DRAM_CTL17_DLL_INCREMENT 8 | ||
| 363 | #define BM_DRAM_CTL17_DLL_INCREMENT 0xff00 | ||
| 364 | #define BF_DRAM_CTL17_DLL_INCREMENT(v) (((v) << 8) & 0xff00) | ||
| 365 | #define BP_DRAM_CTL17_TRC 0 | ||
| 366 | #define BM_DRAM_CTL17_TRC 0x1f | ||
| 367 | #define BF_DRAM_CTL17_TRC(v) (((v) << 0) & 0x1f) | ||
| 368 | |||
| 369 | /** | ||
| 370 | * Register: HW_DRAM_CTL18 | ||
| 371 | * Address: 0x48 | ||
| 372 | * SCT: no | ||
| 373 | */ | ||
| 374 | #define HW_DRAM_CTL18 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x48)) | ||
| 375 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24 | ||
| 376 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7f000000 | ||
| 377 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) (((v) << 24) & 0x7f000000) | ||
| 378 | #define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16 | ||
| 379 | #define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x7f0000 | ||
| 380 | #define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) (((v) << 16) & 0x7f0000) | ||
| 381 | #define BP_DRAM_CTL18_INT_STATUS 8 | ||
| 382 | #define BM_DRAM_CTL18_INT_STATUS 0x1f00 | ||
| 383 | #define BF_DRAM_CTL18_INT_STATUS(v) (((v) << 8) & 0x1f00) | ||
| 384 | #define BP_DRAM_CTL18_INT_MASK 0 | ||
| 385 | #define BM_DRAM_CTL18_INT_MASK 0x1f | ||
| 386 | #define BF_DRAM_CTL18_INT_MASK(v) (((v) << 0) & 0x1f) | ||
| 387 | |||
| 388 | /** | ||
| 389 | * Register: HW_DRAM_CTL19 | ||
| 390 | * Address: 0x4c | ||
| 391 | * SCT: no | ||
| 392 | */ | ||
| 393 | #define HW_DRAM_CTL19 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x4c)) | ||
| 394 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24 | ||
| 395 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xff000000 | ||
| 396 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) (((v) << 24) & 0xff000000) | ||
| 397 | #define BP_DRAM_CTL19_DQS_OUT_SHIFT 16 | ||
| 398 | #define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x7f0000 | ||
| 399 | #define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) (((v) << 16) & 0x7f0000) | ||
| 400 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8 | ||
| 401 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0xff00 | ||
| 402 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) << 8) & 0xff00) | ||
| 403 | #define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0 | ||
| 404 | #define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0xff | ||
| 405 | #define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) << 0) & 0xff) | ||
| 406 | |||
| 407 | /** | ||
| 408 | * Register: HW_DRAM_CTL20 | ||
| 409 | * Address: 0x50 | ||
| 410 | * SCT: no | ||
| 411 | */ | ||
| 412 | #define HW_DRAM_CTL20 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x50)) | ||
| 413 | #define BP_DRAM_CTL20_TRCD_INT 24 | ||
| 414 | #define BM_DRAM_CTL20_TRCD_INT 0xff000000 | ||
| 415 | #define BF_DRAM_CTL20_TRCD_INT(v) (((v) << 24) & 0xff000000) | ||
| 416 | #define BP_DRAM_CTL20_TRAS_MIN 16 | ||
| 417 | #define BM_DRAM_CTL20_TRAS_MIN 0xff0000 | ||
| 418 | #define BF_DRAM_CTL20_TRAS_MIN(v) (((v) << 16) & 0xff0000) | ||
| 419 | #define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8 | ||
| 420 | #define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0xff00 | ||
| 421 | #define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) (((v) << 8) & 0xff00) | ||
| 422 | #define BP_DRAM_CTL20_WR_DQS_SHIFT 0 | ||
| 423 | #define BM_DRAM_CTL20_WR_DQS_SHIFT 0x7f | ||
| 424 | #define BF_DRAM_CTL20_WR_DQS_SHIFT(v) (((v) << 0) & 0x7f) | ||
| 425 | |||
| 426 | /** | ||
| 427 | * Register: HW_DRAM_CTL21 | ||
| 428 | * Address: 0x54 | ||
| 429 | * SCT: no | ||
| 430 | */ | ||
| 431 | #define HW_DRAM_CTL21 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x54)) | ||
| 432 | #define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8 | ||
| 433 | #define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x3ff00 | ||
| 434 | #define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) (((v) << 8) & 0x3ff00) | ||
| 435 | #define BP_DRAM_CTL21_TRFC 0 | ||
| 436 | #define BM_DRAM_CTL21_TRFC 0xff | ||
| 437 | #define BF_DRAM_CTL21_TRFC(v) (((v) << 0) & 0xff) | ||
| 438 | |||
| 439 | /** | ||
| 440 | * Register: HW_DRAM_CTL22 | ||
| 441 | * Address: 0x58 | ||
| 442 | * SCT: no | ||
| 443 | */ | ||
| 444 | #define HW_DRAM_CTL22 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x58)) | ||
| 445 | #define BP_DRAM_CTL22_AHB0_WRCNT 16 | ||
| 446 | #define BM_DRAM_CTL22_AHB0_WRCNT 0x7ff0000 | ||
| 447 | #define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
| 448 | #define BP_DRAM_CTL22_AHB0_RDCNT 0 | ||
| 449 | #define BM_DRAM_CTL22_AHB0_RDCNT 0x7ff | ||
| 450 | #define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) << 0) & 0x7ff) | ||
| 451 | |||
| 452 | /** | ||
| 453 | * Register: HW_DRAM_CTL23 | ||
| 454 | * Address: 0x5c | ||
| 455 | * SCT: no | ||
| 456 | */ | ||
| 457 | #define HW_DRAM_CTL23 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x5c)) | ||
| 458 | #define BP_DRAM_CTL23_AHB1_WRCNT 16 | ||
| 459 | #define BM_DRAM_CTL23_AHB1_WRCNT 0x7ff0000 | ||
| 460 | #define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
| 461 | #define BP_DRAM_CTL23_AHB1_RDCNT 0 | ||
| 462 | #define BM_DRAM_CTL23_AHB1_RDCNT 0x7ff | ||
| 463 | #define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) << 0) & 0x7ff) | ||
| 464 | |||
| 465 | /** | ||
| 466 | * Register: HW_DRAM_CTL24 | ||
| 467 | * Address: 0x60 | ||
| 468 | * SCT: no | ||
| 469 | */ | ||
| 470 | #define HW_DRAM_CTL24 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x60)) | ||
| 471 | #define BP_DRAM_CTL24_AHB2_WRCNT 16 | ||
| 472 | #define BM_DRAM_CTL24_AHB2_WRCNT 0x7ff0000 | ||
| 473 | #define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
| 474 | #define BP_DRAM_CTL24_AHB2_RDCNT 0 | ||
| 475 | #define BM_DRAM_CTL24_AHB2_RDCNT 0x7ff | ||
| 476 | #define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) << 0) & 0x7ff) | ||
| 477 | |||
| 478 | /** | ||
| 479 | * Register: HW_DRAM_CTL25 | ||
| 480 | * Address: 0x64 | ||
| 481 | * SCT: no | ||
| 482 | */ | ||
| 483 | #define HW_DRAM_CTL25 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x64)) | ||
| 484 | #define BP_DRAM_CTL25_AHB3_WRCNT 16 | ||
| 485 | #define BM_DRAM_CTL25_AHB3_WRCNT 0x7ff0000 | ||
| 486 | #define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) << 16) & 0x7ff0000) | ||
| 487 | #define BP_DRAM_CTL25_AHB3_RDCNT 0 | ||
| 488 | #define BM_DRAM_CTL25_AHB3_RDCNT 0x7ff | ||
| 489 | #define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) << 0) & 0x7ff) | ||
| 490 | |||
| 491 | /** | ||
| 492 | * Register: HW_DRAM_CTL26 | ||
| 493 | * Address: 0x68 | ||
| 494 | * SCT: no | ||
| 495 | */ | ||
| 496 | #define HW_DRAM_CTL26 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x68)) | ||
| 497 | #define BP_DRAM_CTL26_TREF 0 | ||
| 498 | #define BM_DRAM_CTL26_TREF 0xfff | ||
| 499 | #define BF_DRAM_CTL26_TREF(v) (((v) << 0) & 0xfff) | ||
| 500 | |||
| 501 | /** | ||
| 502 | * Register: HW_DRAM_CTL27 | ||
| 503 | * Address: 0x6c | ||
| 504 | * SCT: no | ||
| 505 | */ | ||
| 506 | #define HW_DRAM_CTL27 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x6c)) | ||
| 507 | |||
| 508 | /** | ||
| 509 | * Register: HW_DRAM_CTL28 | ||
| 510 | * Address: 0x70 | ||
| 511 | * SCT: no | ||
| 512 | */ | ||
| 513 | #define HW_DRAM_CTL28 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x70)) | ||
| 514 | |||
| 515 | /** | ||
| 516 | * Register: HW_DRAM_CTL29 | ||
| 517 | * Address: 0x74 | ||
| 518 | * SCT: no | ||
| 519 | */ | ||
| 520 | #define HW_DRAM_CTL29 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x74)) | ||
| 521 | #define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 16 | ||
| 522 | #define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 0xffff0000 | ||
| 523 | #define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v) (((v) << 16) & 0xffff0000) | ||
| 524 | #define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0 | ||
| 525 | #define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0xffff | ||
| 526 | #define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v) (((v) << 0) & 0xffff) | ||
| 527 | |||
| 528 | /** | ||
| 529 | * Register: HW_DRAM_CTL30 | ||
| 530 | * Address: 0x78 | ||
| 531 | * SCT: no | ||
| 532 | */ | ||
| 533 | #define HW_DRAM_CTL30 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x78)) | ||
| 534 | #define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 16 | ||
| 535 | #define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 0xffff0000 | ||
| 536 | #define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v) (((v) << 16) & 0xffff0000) | ||
| 537 | #define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0 | ||
| 538 | #define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0xffff | ||
| 539 | #define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v) (((v) << 0) & 0xffff) | ||
| 540 | |||
| 541 | /** | ||
| 542 | * Register: HW_DRAM_CTL31 | ||
| 543 | * Address: 0x7c | ||
| 544 | * SCT: no | ||
| 545 | */ | ||
| 546 | #define HW_DRAM_CTL31 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x7c)) | ||
| 547 | #define BP_DRAM_CTL31_TDLL 16 | ||
| 548 | #define BM_DRAM_CTL31_TDLL 0xffff0000 | ||
| 549 | #define BF_DRAM_CTL31_TDLL(v) (((v) << 16) & 0xffff0000) | ||
| 550 | #define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0 | ||
| 551 | #define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0xffff | ||
| 552 | #define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v) (((v) << 0) & 0xffff) | ||
| 553 | |||
| 554 | /** | ||
| 555 | * Register: HW_DRAM_CTL32 | ||
| 556 | * Address: 0x80 | ||
| 557 | * SCT: no | ||
| 558 | */ | ||
| 559 | #define HW_DRAM_CTL32 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x80)) | ||
| 560 | #define BP_DRAM_CTL32_TXSNR 16 | ||
| 561 | #define BM_DRAM_CTL32_TXSNR 0xffff0000 | ||
| 562 | #define BF_DRAM_CTL32_TXSNR(v) (((v) << 16) & 0xffff0000) | ||
| 563 | #define BP_DRAM_CTL32_TRAS_MAX 0 | ||
| 564 | #define BM_DRAM_CTL32_TRAS_MAX 0xffff | ||
| 565 | #define BF_DRAM_CTL32_TRAS_MAX(v) (((v) << 0) & 0xffff) | ||
| 566 | |||
| 567 | /** | ||
| 568 | * Register: HW_DRAM_CTL33 | ||
| 569 | * Address: 0x84 | ||
| 570 | * SCT: no | ||
| 571 | */ | ||
| 572 | #define HW_DRAM_CTL33 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x84)) | ||
| 573 | #define BP_DRAM_CTL33_VERSION 16 | ||
| 574 | #define BM_DRAM_CTL33_VERSION 0xffff0000 | ||
| 575 | #define BF_DRAM_CTL33_VERSION(v) (((v) << 16) & 0xffff0000) | ||
| 576 | #define BP_DRAM_CTL33_TXSR 0 | ||
| 577 | #define BM_DRAM_CTL33_TXSR 0xffff | ||
| 578 | #define BF_DRAM_CTL33_TXSR(v) (((v) << 0) & 0xffff) | ||
| 579 | |||
| 580 | /** | ||
| 581 | * Register: HW_DRAM_CTL34 | ||
| 582 | * Address: 0x88 | ||
| 583 | * SCT: no | ||
| 584 | */ | ||
| 585 | #define HW_DRAM_CTL34 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x88)) | ||
| 586 | #define BP_DRAM_CTL34_TINIT 0 | ||
| 587 | #define BM_DRAM_CTL34_TINIT 0xffffff | ||
| 588 | #define BF_DRAM_CTL34_TINIT(v) (((v) << 0) & 0xffffff) | ||
| 589 | |||
| 590 | /** | ||
| 591 | * Register: HW_DRAM_CTL35 | ||
| 592 | * Address: 0x8c | ||
| 593 | * SCT: no | ||
| 594 | */ | ||
| 595 | #define HW_DRAM_CTL35 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x8c)) | ||
| 596 | #define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR 0 | ||
| 597 | #define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR 0x7fffffff | ||
| 598 | #define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v) (((v) << 0) & 0x7fffffff) | ||
| 599 | |||
| 600 | /** | ||
| 601 | * Register: HW_DRAM_CTL36 | ||
| 602 | * Address: 0x90 | ||
| 603 | * SCT: no | ||
| 604 | */ | ||
| 605 | #define HW_DRAM_CTL36 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x90)) | ||
| 606 | #define BP_DRAM_CTL36_PWRUP_SREFRESH_EXIT 24 | ||
| 607 | #define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT 0x1000000 | ||
| 608 | #define BF_DRAM_CTL36_PWRUP_SREFRESH_EXIT(v) (((v) << 24) & 0x1000000) | ||
| 609 | #define BP_DRAM_CTL36_ENABLE_QUICK_SREFRESH 16 | ||
| 610 | #define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH 0x10000 | ||
| 611 | #define BF_DRAM_CTL36_ENABLE_QUICK_SREFRESH(v) (((v) << 16) & 0x10000) | ||
| 612 | #define BP_DRAM_CTL36_BUS_SHARE_ENABLE 8 | ||
| 613 | #define BM_DRAM_CTL36_BUS_SHARE_ENABLE 0x100 | ||
| 614 | #define BF_DRAM_CTL36_BUS_SHARE_ENABLE(v) (((v) << 8) & 0x100) | ||
| 615 | #define BP_DRAM_CTL36_ACTIVE_AGING 0 | ||
| 616 | #define BM_DRAM_CTL36_ACTIVE_AGING 0x1 | ||
| 617 | #define BF_DRAM_CTL36_ACTIVE_AGING(v) (((v) << 0) & 0x1) | ||
| 618 | |||
| 619 | /** | ||
| 620 | * Register: HW_DRAM_CTL37 | ||
| 621 | * Address: 0x94 | ||
| 622 | * SCT: no | ||
| 623 | */ | ||
| 624 | #define HW_DRAM_CTL37 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x94)) | ||
| 625 | #define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT 8 | ||
| 626 | #define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT 0x3ff00 | ||
| 627 | #define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v) (((v) << 8) & 0x3ff00) | ||
| 628 | #define BP_DRAM_CTL37_TREF_ENABLE 0 | ||
| 629 | #define BM_DRAM_CTL37_TREF_ENABLE 0x1 | ||
| 630 | #define BF_DRAM_CTL37_TREF_ENABLE(v) (((v) << 0) & 0x1) | ||
| 631 | |||
| 632 | /** | ||
| 633 | * Register: HW_DRAM_CTL38 | ||
| 634 | * Address: 0x98 | ||
| 635 | * SCT: no | ||
| 636 | */ | ||
| 637 | #define HW_DRAM_CTL38 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x98)) | ||
| 638 | #define BP_DRAM_CTL38_EMRS2_DATA_0 16 | ||
| 639 | #define BM_DRAM_CTL38_EMRS2_DATA_0 0x1fff0000 | ||
| 640 | #define BF_DRAM_CTL38_EMRS2_DATA_0(v) (((v) << 16) & 0x1fff0000) | ||
| 641 | #define BP_DRAM_CTL38_EMRS1_DATA 0 | ||
| 642 | #define BM_DRAM_CTL38_EMRS1_DATA 0x1fff | ||
| 643 | #define BF_DRAM_CTL38_EMRS1_DATA(v) (((v) << 0) & 0x1fff) | ||
| 644 | |||
| 645 | /** | ||
| 646 | * Register: HW_DRAM_CTL39 | ||
| 647 | * Address: 0x9c | ||
| 648 | * SCT: no | ||
| 649 | */ | ||
| 650 | #define HW_DRAM_CTL39 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0x9c)) | ||
| 651 | #define BP_DRAM_CTL39_EMRS2_DATA_2 16 | ||
| 652 | #define BM_DRAM_CTL39_EMRS2_DATA_2 0x1fff0000 | ||
| 653 | #define BF_DRAM_CTL39_EMRS2_DATA_2(v) (((v) << 16) & 0x1fff0000) | ||
| 654 | #define BP_DRAM_CTL39_EMRS2_DATA_1 0 | ||
| 655 | #define BM_DRAM_CTL39_EMRS2_DATA_1 0x1fff | ||
| 656 | #define BF_DRAM_CTL39_EMRS2_DATA_1(v) (((v) << 0) & 0x1fff) | ||
| 657 | |||
| 658 | /** | ||
| 659 | * Register: HW_DRAM_CTL40 | ||
| 660 | * Address: 0xa0 | ||
| 661 | * SCT: no | ||
| 662 | */ | ||
| 663 | #define HW_DRAM_CTL40 (*(volatile unsigned long *)(REGS_DRAM_BASE + 0xa0)) | ||
| 664 | #define BP_DRAM_CTL40_TPDEX 16 | ||
| 665 | #define BM_DRAM_CTL40_TPDEX 0xffff0000 | ||
| 666 | #define BF_DRAM_CTL40_TPDEX(v) (((v) << 16) & 0xffff0000) | ||
| 667 | #define BP_DRAM_CTL40_EMRS2_DATA_3 0 | ||
| 668 | #define BM_DRAM_CTL40_EMRS2_DATA_3 0x1fff | ||
| 669 | #define BF_DRAM_CTL40_EMRS2_DATA_3(v) (((v) << 0) & 0x1fff) | ||
| 670 | |||
| 671 | #endif /* __HEADERGEN__STMP3700__DRAM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h b/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h new file mode 100644 index 0000000000..a3ae0f52d1 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-dri.h | |||
| @@ -0,0 +1,274 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__DRI__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__DRI__H__ | ||
| 25 | |||
| 26 | #define REGS_DRI_BASE (0x80074000) | ||
| 27 | |||
| 28 | #define REGS_DRI_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_DRI_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_DRI_CTRL_SFTRST 31 | ||
| 40 | #define BM_DRI_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BV_DRI_CTRL_SFTRST__RUN 0x0 | ||
| 42 | #define BV_DRI_CTRL_SFTRST__RESET 0x1 | ||
| 43 | #define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_DRI_CTRL_CLKGATE 30 | ||
| 46 | #define BM_DRI_CTRL_CLKGATE 0x40000000 | ||
| 47 | #define BV_DRI_CTRL_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_DRI_CTRL_ENABLE_INPUTS 29 | ||
| 52 | #define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 | ||
| 53 | #define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0 | ||
| 54 | #define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1 | ||
| 55 | #define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000) | ||
| 57 | #define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26 | ||
| 58 | #define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000 | ||
| 59 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0 | ||
| 60 | #define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1 | ||
| 61 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000) | ||
| 62 | #define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000) | ||
| 63 | #define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25 | ||
| 64 | #define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000 | ||
| 65 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0 | ||
| 66 | #define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1 | ||
| 67 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000) | ||
| 68 | #define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000) | ||
| 69 | #define BP_DRI_CTRL_DMA_DELAY_COUNT 16 | ||
| 70 | #define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000 | ||
| 71 | #define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 72 | #define BP_DRI_CTRL_REACQUIRE_PHASE 15 | ||
| 73 | #define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000 | ||
| 74 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0 | ||
| 75 | #define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1 | ||
| 76 | #define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000) | ||
| 77 | #define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000) | ||
| 78 | #define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11 | ||
| 79 | #define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800 | ||
| 80 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0 | ||
| 81 | #define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1 | ||
| 82 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800) | ||
| 83 | #define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800) | ||
| 84 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10 | ||
| 85 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400 | ||
| 86 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0 | ||
| 87 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1 | ||
| 88 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
| 89 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
| 90 | #define BP_DRI_CTRL_ATTENTION_IRQ_EN 9 | ||
| 91 | #define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200 | ||
| 92 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0 | ||
| 93 | #define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1 | ||
| 94 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200) | ||
| 95 | #define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200) | ||
| 96 | #define BP_DRI_CTRL_OVERFLOW_IRQ 3 | ||
| 97 | #define BM_DRI_CTRL_OVERFLOW_IRQ 0x8 | ||
| 98 | #define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
| 99 | #define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1 | ||
| 100 | #define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 101 | #define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8) | ||
| 102 | #define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2 | ||
| 103 | #define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4 | ||
| 104 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0 | ||
| 105 | #define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1 | ||
| 106 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
| 107 | #define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4) | ||
| 108 | #define BP_DRI_CTRL_ATTENTION_IRQ 1 | ||
| 109 | #define BM_DRI_CTRL_ATTENTION_IRQ 0x2 | ||
| 110 | #define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0 | ||
| 111 | #define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1 | ||
| 112 | #define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2) | ||
| 113 | #define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2) | ||
| 114 | #define BP_DRI_CTRL_RUN 0 | ||
| 115 | #define BM_DRI_CTRL_RUN 0x1 | ||
| 116 | #define BV_DRI_CTRL_RUN__HALT 0x0 | ||
| 117 | #define BV_DRI_CTRL_RUN__RUN 0x1 | ||
| 118 | #define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 119 | #define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1) | ||
| 120 | |||
| 121 | /** | ||
| 122 | * Register: HW_DRI_TIMING | ||
| 123 | * Address: 0x10 | ||
| 124 | * SCT: no | ||
| 125 | */ | ||
| 126 | #define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10)) | ||
| 127 | #define BP_DRI_TIMING_PILOT_REP_RATE 16 | ||
| 128 | #define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000 | ||
| 129 | #define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000) | ||
| 130 | #define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 | ||
| 131 | #define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff | ||
| 132 | #define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff) | ||
| 133 | |||
| 134 | /** | ||
| 135 | * Register: HW_DRI_STAT | ||
| 136 | * Address: 0x20 | ||
| 137 | * SCT: no | ||
| 138 | */ | ||
| 139 | #define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20)) | ||
| 140 | #define BP_DRI_STAT_DRI_PRESENT 31 | ||
| 141 | #define BM_DRI_STAT_DRI_PRESENT 0x80000000 | ||
| 142 | #define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0 | ||
| 143 | #define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1 | ||
| 144 | #define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 145 | #define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000) | ||
| 146 | #define BP_DRI_STAT_PILOT_PHASE 16 | ||
| 147 | #define BM_DRI_STAT_PILOT_PHASE 0xf0000 | ||
| 148 | #define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000) | ||
| 149 | #define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3 | ||
| 150 | #define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8 | ||
| 151 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 152 | #define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1 | ||
| 153 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
| 154 | #define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8) | ||
| 155 | #define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2 | ||
| 156 | #define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4 | ||
| 157 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 158 | #define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
| 159 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
| 160 | #define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
| 161 | #define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1 | ||
| 162 | #define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2 | ||
| 163 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 164 | #define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1 | ||
| 165 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
| 166 | #define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2) | ||
| 167 | |||
| 168 | /** | ||
| 169 | * Register: HW_DRI_DATA | ||
| 170 | * Address: 0x30 | ||
| 171 | * SCT: no | ||
| 172 | */ | ||
| 173 | #define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30)) | ||
| 174 | #define BP_DRI_DATA_DATA 0 | ||
| 175 | #define BM_DRI_DATA_DATA 0xffffffff | ||
| 176 | #define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 177 | |||
| 178 | /** | ||
| 179 | * Register: HW_DRI_DEBUG0 | ||
| 180 | * Address: 0x40 | ||
| 181 | * SCT: yes | ||
| 182 | */ | ||
| 183 | #define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0)) | ||
| 184 | #define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4)) | ||
| 185 | #define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8)) | ||
| 186 | #define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc)) | ||
| 187 | #define BP_DRI_DEBUG0_DMAREQ 31 | ||
| 188 | #define BM_DRI_DEBUG0_DMAREQ 0x80000000 | ||
| 189 | #define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
| 190 | #define BP_DRI_DEBUG0_DMACMDKICK 30 | ||
| 191 | #define BM_DRI_DEBUG0_DMACMDKICK 0x40000000 | ||
| 192 | #define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000) | ||
| 193 | #define BP_DRI_DEBUG0_DRI_CLK_INPUT 29 | ||
| 194 | #define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000 | ||
| 195 | #define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000) | ||
| 196 | #define BP_DRI_DEBUG0_DRI_DATA_INPUT 28 | ||
| 197 | #define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000 | ||
| 198 | #define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000) | ||
| 199 | #define BP_DRI_DEBUG0_TEST_MODE 27 | ||
| 200 | #define BM_DRI_DEBUG0_TEST_MODE 0x8000000 | ||
| 201 | #define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000) | ||
| 202 | #define BP_DRI_DEBUG0_PILOT_REP_RATE 26 | ||
| 203 | #define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000 | ||
| 204 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0 | ||
| 205 | #define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1 | ||
| 206 | #define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000) | ||
| 207 | #define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000) | ||
| 208 | #define BP_DRI_DEBUG0_SPARE 18 | ||
| 209 | #define BM_DRI_DEBUG0_SPARE 0x3fc0000 | ||
| 210 | #define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000) | ||
| 211 | #define BP_DRI_DEBUG0_FRAME 0 | ||
| 212 | #define BM_DRI_DEBUG0_FRAME 0x3ffff | ||
| 213 | #define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff) | ||
| 214 | |||
| 215 | /** | ||
| 216 | * Register: HW_DRI_DEBUG1 | ||
| 217 | * Address: 0x50 | ||
| 218 | * SCT: yes | ||
| 219 | */ | ||
| 220 | #define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0)) | ||
| 221 | #define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4)) | ||
| 222 | #define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8)) | ||
| 223 | #define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc)) | ||
| 224 | #define BP_DRI_DEBUG1_INVERT_PILOT 31 | ||
| 225 | #define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000 | ||
| 226 | #define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0 | ||
| 227 | #define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1 | ||
| 228 | #define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000) | ||
| 229 | #define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000) | ||
| 230 | #define BP_DRI_DEBUG1_INVERT_ATTENTION 30 | ||
| 231 | #define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000 | ||
| 232 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0 | ||
| 233 | #define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1 | ||
| 234 | #define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000) | ||
| 235 | #define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000) | ||
| 236 | #define BP_DRI_DEBUG1_INVERT_DRI_DATA 29 | ||
| 237 | #define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000 | ||
| 238 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0 | ||
| 239 | #define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1 | ||
| 240 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000) | ||
| 241 | #define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000) | ||
| 242 | #define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28 | ||
| 243 | #define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000 | ||
| 244 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0 | ||
| 245 | #define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1 | ||
| 246 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000) | ||
| 247 | #define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000) | ||
| 248 | #define BP_DRI_DEBUG1_REVERSE_FRAME 27 | ||
| 249 | #define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000 | ||
| 250 | #define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0 | ||
| 251 | #define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1 | ||
| 252 | #define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000) | ||
| 253 | #define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000) | ||
| 254 | #define BP_DRI_DEBUG1_SWIZZLED_FRAME 0 | ||
| 255 | #define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff | ||
| 256 | #define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff) | ||
| 257 | |||
| 258 | /** | ||
| 259 | * Register: HW_DRI_VERSION | ||
| 260 | * Address: 0x60 | ||
| 261 | * SCT: no | ||
| 262 | */ | ||
| 263 | #define HW_DRI_VERSION (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60)) | ||
| 264 | #define BP_DRI_VERSION_MAJOR 24 | ||
| 265 | #define BM_DRI_VERSION_MAJOR 0xff000000 | ||
| 266 | #define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 267 | #define BP_DRI_VERSION_MINOR 16 | ||
| 268 | #define BM_DRI_VERSION_MINOR 0xff0000 | ||
| 269 | #define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 270 | #define BP_DRI_VERSION_STEP 0 | ||
| 271 | #define BM_DRI_VERSION_STEP 0xffff | ||
| 272 | #define BF_DRI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 273 | |||
| 274 | #endif /* __HEADERGEN__STMP3700__DRI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h new file mode 100644 index 0000000000..e84274169e --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ecc8.h | |||
| @@ -0,0 +1,387 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__ECC8__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__ECC8__H__ | ||
| 25 | |||
| 26 | #define REGS_ECC8_BASE (0x80008000) | ||
| 27 | |||
| 28 | #define REGS_ECC8_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_ECC8_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_ECC8_CTRL (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_ECC8_CTRL_SET (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_ECC8_CTRL_CLR (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_ECC8_CTRL_TOG (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_ECC8_CTRL_SFTRST 31 | ||
| 40 | #define BM_ECC8_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BV_ECC8_CTRL_SFTRST__RUN 0x0 | ||
| 42 | #define BV_ECC8_CTRL_SFTRST__RESET 0x1 | ||
| 43 | #define BF_ECC8_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_ECC8_CTRL_SFTRST_V(v) ((BV_ECC8_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_ECC8_CTRL_CLKGATE 30 | ||
| 46 | #define BM_ECC8_CTRL_CLKGATE 0x40000000 | ||
| 47 | #define BV_ECC8_CTRL_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_ECC8_CTRL_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_ECC8_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_ECC8_CTRL_CLKGATE_V(v) ((BV_ECC8_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_ECC8_CTRL_AHBM_SFTRST 29 | ||
| 52 | #define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 | ||
| 53 | #define BV_ECC8_CTRL_AHBM_SFTRST__RUN 0x0 | ||
| 54 | #define BV_ECC8_CTRL_AHBM_SFTRST__RESET 0x1 | ||
| 55 | #define BF_ECC8_CTRL_AHBM_SFTRST(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_ECC8_CTRL_AHBM_SFTRST_V(v) ((BV_ECC8_CTRL_AHBM_SFTRST__##v << 29) & 0x20000000) | ||
| 57 | #define BP_ECC8_CTRL_THROTTLE 24 | ||
| 58 | #define BM_ECC8_CTRL_THROTTLE 0xf000000 | ||
| 59 | #define BF_ECC8_CTRL_THROTTLE(v) (((v) << 24) & 0xf000000) | ||
| 60 | #define BP_ECC8_CTRL_DEBUG_STALL_IRQ_EN 10 | ||
| 61 | #define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN 0x400 | ||
| 62 | #define BF_ECC8_CTRL_DEBUG_STALL_IRQ_EN(v) (((v) << 10) & 0x400) | ||
| 63 | #define BP_ECC8_CTRL_DEBUG_WRITE_IRQ_EN 9 | ||
| 64 | #define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN 0x200 | ||
| 65 | #define BF_ECC8_CTRL_DEBUG_WRITE_IRQ_EN(v) (((v) << 9) & 0x200) | ||
| 66 | #define BP_ECC8_CTRL_COMPLETE_IRQ_EN 8 | ||
| 67 | #define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x100 | ||
| 68 | #define BF_ECC8_CTRL_COMPLETE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
| 69 | #define BP_ECC8_CTRL_BM_ERROR_IRQ 3 | ||
| 70 | #define BM_ECC8_CTRL_BM_ERROR_IRQ 0x8 | ||
| 71 | #define BF_ECC8_CTRL_BM_ERROR_IRQ(v) (((v) << 3) & 0x8) | ||
| 72 | #define BP_ECC8_CTRL_DEBUG_STALL_IRQ 2 | ||
| 73 | #define BM_ECC8_CTRL_DEBUG_STALL_IRQ 0x4 | ||
| 74 | #define BF_ECC8_CTRL_DEBUG_STALL_IRQ(v) (((v) << 2) & 0x4) | ||
| 75 | #define BP_ECC8_CTRL_DEBUG_WRITE_IRQ 1 | ||
| 76 | #define BM_ECC8_CTRL_DEBUG_WRITE_IRQ 0x2 | ||
| 77 | #define BF_ECC8_CTRL_DEBUG_WRITE_IRQ(v) (((v) << 1) & 0x2) | ||
| 78 | #define BP_ECC8_CTRL_COMPLETE_IRQ 0 | ||
| 79 | #define BM_ECC8_CTRL_COMPLETE_IRQ 0x1 | ||
| 80 | #define BF_ECC8_CTRL_COMPLETE_IRQ(v) (((v) << 0) & 0x1) | ||
| 81 | |||
| 82 | /** | ||
| 83 | * Register: HW_ECC8_STATUS0 | ||
| 84 | * Address: 0x10 | ||
| 85 | * SCT: no | ||
| 86 | */ | ||
| 87 | #define HW_ECC8_STATUS0 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x10)) | ||
| 88 | #define BP_ECC8_STATUS0_HANDLE 16 | ||
| 89 | #define BM_ECC8_STATUS0_HANDLE 0xffff0000 | ||
| 90 | #define BF_ECC8_STATUS0_HANDLE(v) (((v) << 16) & 0xffff0000) | ||
| 91 | #define BP_ECC8_STATUS0_RS8ECC_ENC_PRESENT 15 | ||
| 92 | #define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT 0x8000 | ||
| 93 | #define BF_ECC8_STATUS0_RS8ECC_ENC_PRESENT(v) (((v) << 15) & 0x8000) | ||
| 94 | #define BP_ECC8_STATUS0_RS8ECC_DEC_PRESENT 14 | ||
| 95 | #define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT 0x4000 | ||
| 96 | #define BF_ECC8_STATUS0_RS8ECC_DEC_PRESENT(v) (((v) << 14) & 0x4000) | ||
| 97 | #define BP_ECC8_STATUS0_RS4ECC_ENC_PRESENT 13 | ||
| 98 | #define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT 0x2000 | ||
| 99 | #define BF_ECC8_STATUS0_RS4ECC_ENC_PRESENT(v) (((v) << 13) & 0x2000) | ||
| 100 | #define BP_ECC8_STATUS0_RS4ECC_DEC_PRESENT 12 | ||
| 101 | #define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT 0x1000 | ||
| 102 | #define BF_ECC8_STATUS0_RS4ECC_DEC_PRESENT(v) (((v) << 12) & 0x1000) | ||
| 103 | #define BP_ECC8_STATUS0_STATUS_AUX 8 | ||
| 104 | #define BM_ECC8_STATUS0_STATUS_AUX 0xf00 | ||
| 105 | #define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS 0x0 | ||
| 106 | #define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE 0x1 | ||
| 107 | #define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE 0x2 | ||
| 108 | #define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE 0x3 | ||
| 109 | #define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE 0x4 | ||
| 110 | #define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED 0xc | ||
| 111 | #define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE 0xe | ||
| 112 | #define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES 0xf | ||
| 113 | #define BF_ECC8_STATUS0_STATUS_AUX(v) (((v) << 8) & 0xf00) | ||
| 114 | #define BF_ECC8_STATUS0_STATUS_AUX_V(v) ((BV_ECC8_STATUS0_STATUS_AUX__##v << 8) & 0xf00) | ||
| 115 | #define BP_ECC8_STATUS0_ALLONES 4 | ||
| 116 | #define BM_ECC8_STATUS0_ALLONES 0x10 | ||
| 117 | #define BF_ECC8_STATUS0_ALLONES(v) (((v) << 4) & 0x10) | ||
| 118 | #define BP_ECC8_STATUS0_CORRECTED 3 | ||
| 119 | #define BM_ECC8_STATUS0_CORRECTED 0x8 | ||
| 120 | #define BF_ECC8_STATUS0_CORRECTED(v) (((v) << 3) & 0x8) | ||
| 121 | #define BP_ECC8_STATUS0_UNCORRECTABLE 2 | ||
| 122 | #define BM_ECC8_STATUS0_UNCORRECTABLE 0x4 | ||
| 123 | #define BF_ECC8_STATUS0_UNCORRECTABLE(v) (((v) << 2) & 0x4) | ||
| 124 | #define BP_ECC8_STATUS0_COMPLETED_CE 0 | ||
| 125 | #define BM_ECC8_STATUS0_COMPLETED_CE 0x3 | ||
| 126 | #define BF_ECC8_STATUS0_COMPLETED_CE(v) (((v) << 0) & 0x3) | ||
| 127 | |||
| 128 | /** | ||
| 129 | * Register: HW_ECC8_STATUS1 | ||
| 130 | * Address: 0x20 | ||
| 131 | * SCT: no | ||
| 132 | */ | ||
| 133 | #define HW_ECC8_STATUS1 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x20)) | ||
| 134 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD7 28 | ||
| 135 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD7 0xf0000000 | ||
| 136 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS 0x0 | ||
| 137 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE 0x1 | ||
| 138 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE 0x2 | ||
| 139 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE 0x3 | ||
| 140 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE 0x4 | ||
| 141 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE 0x5 | ||
| 142 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE 0x6 | ||
| 143 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE 0x7 | ||
| 144 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE 0x8 | ||
| 145 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED 0xc | ||
| 146 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE 0xe | ||
| 147 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES 0xf | ||
| 148 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v) (((v) << 28) & 0xf0000000) | ||
| 149 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD7_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD7__##v << 28) & 0xf0000000) | ||
| 150 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD6 24 | ||
| 151 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD6 0xf000000 | ||
| 152 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS 0x0 | ||
| 153 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE 0x1 | ||
| 154 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE 0x2 | ||
| 155 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE 0x3 | ||
| 156 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE 0x4 | ||
| 157 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE 0x5 | ||
| 158 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE 0x6 | ||
| 159 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE 0x7 | ||
| 160 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE 0x8 | ||
| 161 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED 0xc | ||
| 162 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE 0xe | ||
| 163 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES 0xf | ||
| 164 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v) (((v) << 24) & 0xf000000) | ||
| 165 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD6_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD6__##v << 24) & 0xf000000) | ||
| 166 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD5 20 | ||
| 167 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD5 0xf00000 | ||
| 168 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS 0x0 | ||
| 169 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE 0x1 | ||
| 170 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE 0x2 | ||
| 171 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE 0x3 | ||
| 172 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE 0x4 | ||
| 173 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE 0x5 | ||
| 174 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE 0x6 | ||
| 175 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE 0x7 | ||
| 176 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE 0x8 | ||
| 177 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED 0xc | ||
| 178 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE 0xe | ||
| 179 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES 0xf | ||
| 180 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v) (((v) << 20) & 0xf00000) | ||
| 181 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD5_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD5__##v << 20) & 0xf00000) | ||
| 182 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD4 16 | ||
| 183 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD4 0xf0000 | ||
| 184 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS 0x0 | ||
| 185 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE 0x1 | ||
| 186 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE 0x2 | ||
| 187 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE 0x3 | ||
| 188 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE 0x4 | ||
| 189 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE 0x5 | ||
| 190 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE 0x6 | ||
| 191 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE 0x7 | ||
| 192 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE 0x8 | ||
| 193 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED 0xc | ||
| 194 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE 0xe | ||
| 195 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES 0xf | ||
| 196 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v) (((v) << 16) & 0xf0000) | ||
| 197 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD4_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD4__##v << 16) & 0xf0000) | ||
| 198 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD3 12 | ||
| 199 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD3 0xf000 | ||
| 200 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS 0x0 | ||
| 201 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE 0x1 | ||
| 202 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE 0x2 | ||
| 203 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE 0x3 | ||
| 204 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE 0x4 | ||
| 205 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE 0x5 | ||
| 206 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE 0x6 | ||
| 207 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE 0x7 | ||
| 208 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE 0x8 | ||
| 209 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED 0xc | ||
| 210 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE 0xe | ||
| 211 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES 0xf | ||
| 212 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v) (((v) << 12) & 0xf000) | ||
| 213 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD3_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD3__##v << 12) & 0xf000) | ||
| 214 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD2 8 | ||
| 215 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD2 0xf00 | ||
| 216 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS 0x0 | ||
| 217 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE 0x1 | ||
| 218 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE 0x2 | ||
| 219 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE 0x3 | ||
| 220 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE 0x4 | ||
| 221 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE 0x5 | ||
| 222 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE 0x6 | ||
| 223 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE 0x7 | ||
| 224 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE 0x8 | ||
| 225 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED 0xc | ||
| 226 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE 0xe | ||
| 227 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES 0xf | ||
| 228 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v) (((v) << 8) & 0xf00) | ||
| 229 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD2_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD2__##v << 8) & 0xf00) | ||
| 230 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD1 4 | ||
| 231 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD1 0xf0 | ||
| 232 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS 0x0 | ||
| 233 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE 0x1 | ||
| 234 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE 0x2 | ||
| 235 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE 0x3 | ||
| 236 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE 0x4 | ||
| 237 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE 0x5 | ||
| 238 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE 0x6 | ||
| 239 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE 0x7 | ||
| 240 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE 0x8 | ||
| 241 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED 0xc | ||
| 242 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE 0xe | ||
| 243 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES 0xf | ||
| 244 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v) (((v) << 4) & 0xf0) | ||
| 245 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD1_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD1__##v << 4) & 0xf0) | ||
| 246 | #define BP_ECC8_STATUS1_STATUS_PAYLOAD0 0 | ||
| 247 | #define BM_ECC8_STATUS1_STATUS_PAYLOAD0 0xf | ||
| 248 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS 0x0 | ||
| 249 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE 0x1 | ||
| 250 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE 0x2 | ||
| 251 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE 0x3 | ||
| 252 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE 0x4 | ||
| 253 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE 0x5 | ||
| 254 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE 0x6 | ||
| 255 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE 0x7 | ||
| 256 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE 0x8 | ||
| 257 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED 0xc | ||
| 258 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE 0xe | ||
| 259 | #define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES 0xf | ||
| 260 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v) (((v) << 0) & 0xf) | ||
| 261 | #define BF_ECC8_STATUS1_STATUS_PAYLOAD0_V(v) ((BV_ECC8_STATUS1_STATUS_PAYLOAD0__##v << 0) & 0xf) | ||
| 262 | |||
| 263 | /** | ||
| 264 | * Register: HW_ECC8_DEBUG0 | ||
| 265 | * Address: 0x30 | ||
| 266 | * SCT: yes | ||
| 267 | */ | ||
| 268 | #define HW_ECC8_DEBUG0 (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x0)) | ||
| 269 | #define HW_ECC8_DEBUG0_SET (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x4)) | ||
| 270 | #define HW_ECC8_DEBUG0_CLR (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0x8)) | ||
| 271 | #define HW_ECC8_DEBUG0_TOG (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x30 + 0xc)) | ||
| 272 | #define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 | ||
| 273 | #define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x1ff0000 | ||
| 274 | #define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 | ||
| 275 | #define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 | ||
| 276 | #define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << 16) & 0x1ff0000) | ||
| 277 | #define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##v << 16) & 0x1ff0000) | ||
| 278 | #define BP_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND 15 | ||
| 279 | #define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND 0x8000 | ||
| 280 | #define BF_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND(v) (((v) << 15) & 0x8000) | ||
| 281 | #define BP_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 14 | ||
| 282 | #define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x4000 | ||
| 283 | #define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 | ||
| 284 | #define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 | ||
| 285 | #define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) (((v) << 14) & 0x4000) | ||
| 286 | #define BF_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##v << 14) & 0x4000) | ||
| 287 | #define BP_ECC8_DEBUG0_KES_DEBUG_MODE4K 13 | ||
| 288 | #define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K 0x2000 | ||
| 289 | #define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 | ||
| 290 | #define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 | ||
| 291 | #define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K(v) (((v) << 13) & 0x2000) | ||
| 292 | #define BF_ECC8_DEBUG0_KES_DEBUG_MODE4K_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__##v << 13) & 0x2000) | ||
| 293 | #define BP_ECC8_DEBUG0_KES_DEBUG_KICK 12 | ||
| 294 | #define BM_ECC8_DEBUG0_KES_DEBUG_KICK 0x1000 | ||
| 295 | #define BF_ECC8_DEBUG0_KES_DEBUG_KICK(v) (((v) << 12) & 0x1000) | ||
| 296 | #define BP_ECC8_DEBUG0_KES_STANDALONE 11 | ||
| 297 | #define BM_ECC8_DEBUG0_KES_STANDALONE 0x800 | ||
| 298 | #define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL 0x0 | ||
| 299 | #define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 | ||
| 300 | #define BF_ECC8_DEBUG0_KES_STANDALONE(v) (((v) << 11) & 0x800) | ||
| 301 | #define BF_ECC8_DEBUG0_KES_STANDALONE_V(v) ((BV_ECC8_DEBUG0_KES_STANDALONE__##v << 11) & 0x800) | ||
| 302 | #define BP_ECC8_DEBUG0_KES_DEBUG_STEP 10 | ||
| 303 | #define BM_ECC8_DEBUG0_KES_DEBUG_STEP 0x400 | ||
| 304 | #define BF_ECC8_DEBUG0_KES_DEBUG_STEP(v) (((v) << 10) & 0x400) | ||
| 305 | #define BP_ECC8_DEBUG0_KES_DEBUG_STALL 9 | ||
| 306 | #define BM_ECC8_DEBUG0_KES_DEBUG_STALL 0x200 | ||
| 307 | #define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 | ||
| 308 | #define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 | ||
| 309 | #define BF_ECC8_DEBUG0_KES_DEBUG_STALL(v) (((v) << 9) & 0x200) | ||
| 310 | #define BF_ECC8_DEBUG0_KES_DEBUG_STALL_V(v) ((BV_ECC8_DEBUG0_KES_DEBUG_STALL__##v << 9) & 0x200) | ||
| 311 | #define BP_ECC8_DEBUG0_BM_KES_TEST_BYPASS 8 | ||
| 312 | #define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS 0x100 | ||
| 313 | #define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 | ||
| 314 | #define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 | ||
| 315 | #define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS(v) (((v) << 8) & 0x100) | ||
| 316 | #define BF_ECC8_DEBUG0_BM_KES_TEST_BYPASS_V(v) ((BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__##v << 8) & 0x100) | ||
| 317 | #define BP_ECC8_DEBUG0_DEBUG_REG_SELECT 0 | ||
| 318 | #define BM_ECC8_DEBUG0_DEBUG_REG_SELECT 0x3f | ||
| 319 | #define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v) (((v) << 0) & 0x3f) | ||
| 320 | |||
| 321 | /** | ||
| 322 | * Register: HW_ECC8_DBGKESREAD | ||
| 323 | * Address: 0x40 | ||
| 324 | * SCT: no | ||
| 325 | */ | ||
| 326 | #define HW_ECC8_DBGKESREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x40)) | ||
| 327 | #define BP_ECC8_DBGKESREAD_VALUES 0 | ||
| 328 | #define BM_ECC8_DBGKESREAD_VALUES 0xffffffff | ||
| 329 | #define BF_ECC8_DBGKESREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
| 330 | |||
| 331 | /** | ||
| 332 | * Register: HW_ECC8_DBGCSFEREAD | ||
| 333 | * Address: 0x50 | ||
| 334 | * SCT: no | ||
| 335 | */ | ||
| 336 | #define HW_ECC8_DBGCSFEREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x50)) | ||
| 337 | #define BP_ECC8_DBGCSFEREAD_VALUES 0 | ||
| 338 | #define BM_ECC8_DBGCSFEREAD_VALUES 0xffffffff | ||
| 339 | #define BF_ECC8_DBGCSFEREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
| 340 | |||
| 341 | /** | ||
| 342 | * Register: HW_ECC8_DBGSYNDGENREAD | ||
| 343 | * Address: 0x60 | ||
| 344 | * SCT: no | ||
| 345 | */ | ||
| 346 | #define HW_ECC8_DBGSYNDGENREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x60)) | ||
| 347 | #define BP_ECC8_DBGSYNDGENREAD_VALUES 0 | ||
| 348 | #define BM_ECC8_DBGSYNDGENREAD_VALUES 0xffffffff | ||
| 349 | #define BF_ECC8_DBGSYNDGENREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
| 350 | |||
| 351 | /** | ||
| 352 | * Register: HW_ECC8_DBGAHBMREAD | ||
| 353 | * Address: 0x70 | ||
| 354 | * SCT: no | ||
| 355 | */ | ||
| 356 | #define HW_ECC8_DBGAHBMREAD (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x70)) | ||
| 357 | #define BP_ECC8_DBGAHBMREAD_VALUES 0 | ||
| 358 | #define BM_ECC8_DBGAHBMREAD_VALUES 0xffffffff | ||
| 359 | #define BF_ECC8_DBGAHBMREAD_VALUES(v) (((v) << 0) & 0xffffffff) | ||
| 360 | |||
| 361 | /** | ||
| 362 | * Register: HW_ECC8_BLOCKNAME | ||
| 363 | * Address: 0x80 | ||
| 364 | * SCT: no | ||
| 365 | */ | ||
| 366 | #define HW_ECC8_BLOCKNAME (*(volatile unsigned long *)(REGS_ECC8_BASE + 0x80)) | ||
| 367 | #define BP_ECC8_BLOCKNAME_NAME 0 | ||
| 368 | #define BM_ECC8_BLOCKNAME_NAME 0xffffffff | ||
| 369 | #define BF_ECC8_BLOCKNAME_NAME(v) (((v) << 0) & 0xffffffff) | ||
| 370 | |||
| 371 | /** | ||
| 372 | * Register: HW_ECC8_VERSION | ||
| 373 | * Address: 0xa0 | ||
| 374 | * SCT: no | ||
| 375 | */ | ||
| 376 | #define HW_ECC8_VERSION (*(volatile unsigned long *)(REGS_ECC8_BASE + 0xa0)) | ||
| 377 | #define BP_ECC8_VERSION_MAJOR 24 | ||
| 378 | #define BM_ECC8_VERSION_MAJOR 0xff000000 | ||
| 379 | #define BF_ECC8_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 380 | #define BP_ECC8_VERSION_MINOR 16 | ||
| 381 | #define BM_ECC8_VERSION_MINOR 0xff0000 | ||
| 382 | #define BF_ECC8_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 383 | #define BP_ECC8_VERSION_STEP 0 | ||
| 384 | #define BM_ECC8_VERSION_STEP 0xffff | ||
| 385 | #define BF_ECC8_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 386 | |||
| 387 | #endif /* __HEADERGEN__STMP3700__ECC8__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h new file mode 100644 index 0000000000..b81fb35313 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-emi.h | |||
| @@ -0,0 +1,196 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__EMI__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__EMI__H__ | ||
| 25 | |||
| 26 | #define REGS_EMI_BASE (0x80020000) | ||
| 27 | |||
| 28 | #define REGS_EMI_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_EMI_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_EMI_CTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_EMI_CTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_EMI_CTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_EMI_CTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_EMI_CTRL_SFTRST 31 | ||
| 40 | #define BM_EMI_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_EMI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_EMI_CTRL_CLKGATE 30 | ||
| 43 | #define BM_EMI_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_EMI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_EMI_CTRL_MEM_WIDTH 6 | ||
| 46 | #define BM_EMI_CTRL_MEM_WIDTH 0x40 | ||
| 47 | #define BF_EMI_CTRL_MEM_WIDTH(v) (((v) << 6) & 0x40) | ||
| 48 | #define BP_EMI_CTRL_WRITE_PROTECT 5 | ||
| 49 | #define BM_EMI_CTRL_WRITE_PROTECT 0x20 | ||
| 50 | #define BF_EMI_CTRL_WRITE_PROTECT(v) (((v) << 5) & 0x20) | ||
| 51 | #define BP_EMI_CTRL_RESET_OUT 4 | ||
| 52 | #define BM_EMI_CTRL_RESET_OUT 0x10 | ||
| 53 | #define BF_EMI_CTRL_RESET_OUT(v) (((v) << 4) & 0x10) | ||
| 54 | #define BP_EMI_CTRL_CE_SELECT 0 | ||
| 55 | #define BM_EMI_CTRL_CE_SELECT 0xf | ||
| 56 | #define BV_EMI_CTRL_CE_SELECT__NONE 0x0 | ||
| 57 | #define BV_EMI_CTRL_CE_SELECT__CE0 0x1 | ||
| 58 | #define BV_EMI_CTRL_CE_SELECT__CE1 0x2 | ||
| 59 | #define BV_EMI_CTRL_CE_SELECT__CE2 0x4 | ||
| 60 | #define BV_EMI_CTRL_CE_SELECT__CE3 0x8 | ||
| 61 | #define BF_EMI_CTRL_CE_SELECT(v) (((v) << 0) & 0xf) | ||
| 62 | #define BF_EMI_CTRL_CE_SELECT_V(v) ((BV_EMI_CTRL_CE_SELECT__##v << 0) & 0xf) | ||
| 63 | |||
| 64 | /** | ||
| 65 | * Register: HW_EMI_STAT | ||
| 66 | * Address: 0x10 | ||
| 67 | * SCT: no | ||
| 68 | */ | ||
| 69 | #define HW_EMI_STAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10)) | ||
| 70 | #define BP_EMI_STAT_DRAM_PRESENT 31 | ||
| 71 | #define BM_EMI_STAT_DRAM_PRESENT 0x80000000 | ||
| 72 | #define BF_EMI_STAT_DRAM_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 73 | #define BP_EMI_STAT_NOR_PRESENT 30 | ||
| 74 | #define BM_EMI_STAT_NOR_PRESENT 0x40000000 | ||
| 75 | #define BF_EMI_STAT_NOR_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 76 | #define BP_EMI_STAT_LARGE_DRAM_ENABLED 29 | ||
| 77 | #define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000 | ||
| 78 | #define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) << 29) & 0x20000000) | ||
| 79 | #define BP_EMI_STAT_DRAM_HALTED 1 | ||
| 80 | #define BM_EMI_STAT_DRAM_HALTED 0x2 | ||
| 81 | #define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0 | ||
| 82 | #define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1 | ||
| 83 | #define BF_EMI_STAT_DRAM_HALTED(v) (((v) << 1) & 0x2) | ||
| 84 | #define BF_EMI_STAT_DRAM_HALTED_V(v) ((BV_EMI_STAT_DRAM_HALTED__##v << 1) & 0x2) | ||
| 85 | #define BP_EMI_STAT_NOR_BUSY 0 | ||
| 86 | #define BM_EMI_STAT_NOR_BUSY 0x1 | ||
| 87 | #define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0 | ||
| 88 | #define BV_EMI_STAT_NOR_BUSY__BUSY 0x1 | ||
| 89 | #define BF_EMI_STAT_NOR_BUSY(v) (((v) << 0) & 0x1) | ||
| 90 | #define BF_EMI_STAT_NOR_BUSY_V(v) ((BV_EMI_STAT_NOR_BUSY__##v << 0) & 0x1) | ||
| 91 | |||
| 92 | /** | ||
| 93 | * Register: HW_EMI_TIME | ||
| 94 | * Address: 0x20 | ||
| 95 | * SCT: yes | ||
| 96 | */ | ||
| 97 | #define HW_EMI_TIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x0)) | ||
| 98 | #define HW_EMI_TIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x4)) | ||
| 99 | #define HW_EMI_TIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0x8)) | ||
| 100 | #define HW_EMI_TIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20 + 0xc)) | ||
| 101 | #define BP_EMI_TIME_THZ 24 | ||
| 102 | #define BM_EMI_TIME_THZ 0xf000000 | ||
| 103 | #define BF_EMI_TIME_THZ(v) (((v) << 24) & 0xf000000) | ||
| 104 | #define BP_EMI_TIME_TDH 16 | ||
| 105 | #define BM_EMI_TIME_TDH 0xf0000 | ||
| 106 | #define BF_EMI_TIME_TDH(v) (((v) << 16) & 0xf0000) | ||
| 107 | #define BP_EMI_TIME_TDS 8 | ||
| 108 | #define BM_EMI_TIME_TDS 0x1f00 | ||
| 109 | #define BF_EMI_TIME_TDS(v) (((v) << 8) & 0x1f00) | ||
| 110 | #define BP_EMI_TIME_TAS 0 | ||
| 111 | #define BM_EMI_TIME_TAS 0xf | ||
| 112 | #define BF_EMI_TIME_TAS(v) (((v) << 0) & 0xf) | ||
| 113 | |||
| 114 | /** | ||
| 115 | * Register: HW_EMI_DDR_TEST_MODE_CSR | ||
| 116 | * Address: 0x30 | ||
| 117 | * SCT: yes | ||
| 118 | */ | ||
| 119 | #define HW_EMI_DDR_TEST_MODE_CSR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x0)) | ||
| 120 | #define HW_EMI_DDR_TEST_MODE_CSR_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x4)) | ||
| 121 | #define HW_EMI_DDR_TEST_MODE_CSR_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0x8)) | ||
| 122 | #define HW_EMI_DDR_TEST_MODE_CSR_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x30 + 0xc)) | ||
| 123 | #define BP_EMI_DDR_TEST_MODE_CSR_DONE 1 | ||
| 124 | #define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x2 | ||
| 125 | #define BF_EMI_DDR_TEST_MODE_CSR_DONE(v) (((v) << 1) & 0x2) | ||
| 126 | #define BP_EMI_DDR_TEST_MODE_CSR_START 0 | ||
| 127 | #define BM_EMI_DDR_TEST_MODE_CSR_START 0x1 | ||
| 128 | #define BF_EMI_DDR_TEST_MODE_CSR_START(v) (((v) << 0) & 0x1) | ||
| 129 | |||
| 130 | /** | ||
| 131 | * Register: HW_EMI_DEBUG | ||
| 132 | * Address: 0x80 | ||
| 133 | * SCT: no | ||
| 134 | */ | ||
| 135 | #define HW_EMI_DEBUG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80)) | ||
| 136 | #define BP_EMI_DEBUG_NOR_STATE 0 | ||
| 137 | #define BM_EMI_DEBUG_NOR_STATE 0xf | ||
| 138 | #define BF_EMI_DEBUG_NOR_STATE(v) (((v) << 0) & 0xf) | ||
| 139 | |||
| 140 | /** | ||
| 141 | * Register: HW_EMI_DDR_TEST_MODE_STATUS0 | ||
| 142 | * Address: 0x90 | ||
| 143 | * SCT: no | ||
| 144 | */ | ||
| 145 | #define HW_EMI_DDR_TEST_MODE_STATUS0 (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90)) | ||
| 146 | #define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0 | ||
| 147 | #define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x1fff | ||
| 148 | #define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) (((v) << 0) & 0x1fff) | ||
| 149 | |||
| 150 | /** | ||
| 151 | * Register: HW_EMI_DDR_TEST_MODE_STATUS1 | ||
| 152 | * Address: 0xa0 | ||
| 153 | * SCT: no | ||
| 154 | */ | ||
| 155 | #define HW_EMI_DDR_TEST_MODE_STATUS1 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0)) | ||
| 156 | #define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0 | ||
| 157 | #define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x1fff | ||
| 158 | #define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) (((v) << 0) & 0x1fff) | ||
| 159 | |||
| 160 | /** | ||
| 161 | * Register: HW_EMI_DDR_TEST_MODE_STATUS2 | ||
| 162 | * Address: 0xb0 | ||
| 163 | * SCT: no | ||
| 164 | */ | ||
| 165 | #define HW_EMI_DDR_TEST_MODE_STATUS2 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0)) | ||
| 166 | #define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0 | ||
| 167 | #define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xffffffff | ||
| 168 | #define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (((v) << 0) & 0xffffffff) | ||
| 169 | |||
| 170 | /** | ||
| 171 | * Register: HW_EMI_DDR_TEST_MODE_STATUS3 | ||
| 172 | * Address: 0xc0 | ||
| 173 | * SCT: no | ||
| 174 | */ | ||
| 175 | #define HW_EMI_DDR_TEST_MODE_STATUS3 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0)) | ||
| 176 | #define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0 | ||
| 177 | #define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xffffffff | ||
| 178 | #define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (((v) << 0) & 0xffffffff) | ||
| 179 | |||
| 180 | /** | ||
| 181 | * Register: HW_EMI_VERSION | ||
| 182 | * Address: 0xf0 | ||
| 183 | * SCT: no | ||
| 184 | */ | ||
| 185 | #define HW_EMI_VERSION (*(volatile unsigned long *)(REGS_EMI_BASE + 0xf0)) | ||
| 186 | #define BP_EMI_VERSION_MAJOR 24 | ||
| 187 | #define BM_EMI_VERSION_MAJOR 0xff000000 | ||
| 188 | #define BF_EMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 189 | #define BP_EMI_VERSION_MINOR 16 | ||
| 190 | #define BM_EMI_VERSION_MINOR 0xff0000 | ||
| 191 | #define BF_EMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 192 | #define BP_EMI_VERSION_STEP 0 | ||
| 193 | #define BM_EMI_VERSION_STEP 0xffff | ||
| 194 | #define BF_EMI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 195 | |||
| 196 | #endif /* __HEADERGEN__STMP3700__EMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h new file mode 100644 index 0000000000..a872606da4 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h | |||
| @@ -0,0 +1,355 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__GPIOMON__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__GPIOMON__H__ | ||
| 25 | |||
| 26 | #define REGS_GPIOMON_BASE (0x8003c300) | ||
| 27 | |||
| 28 | #define REGS_GPIOMON_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_GPIOMON_BANK0_DATAIN | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: no | ||
| 34 | */ | ||
| 35 | #define HW_GPIOMON_BANK0_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x0)) | ||
| 36 | #define BP_GPIOMON_BANK0_DATAIN_DATA 0 | ||
| 37 | #define BM_GPIOMON_BANK0_DATAIN_DATA 0xffffffff | ||
| 38 | #define BF_GPIOMON_BANK0_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 39 | |||
| 40 | /** | ||
| 41 | * Register: HW_GPIOMON_BANK1_DATAIN | ||
| 42 | * Address: 0x10 | ||
| 43 | * SCT: no | ||
| 44 | */ | ||
| 45 | #define HW_GPIOMON_BANK1_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x10)) | ||
| 46 | #define BP_GPIOMON_BANK1_DATAIN_DATA 0 | ||
| 47 | #define BM_GPIOMON_BANK1_DATAIN_DATA 0xffffffff | ||
| 48 | #define BF_GPIOMON_BANK1_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 49 | |||
| 50 | /** | ||
| 51 | * Register: HW_GPIOMON_BANK2_DATAIN | ||
| 52 | * Address: 0x20 | ||
| 53 | * SCT: no | ||
| 54 | */ | ||
| 55 | #define HW_GPIOMON_BANK2_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x20)) | ||
| 56 | #define BP_GPIOMON_BANK2_DATAIN_DATA 0 | ||
| 57 | #define BM_GPIOMON_BANK2_DATAIN_DATA 0xffffffff | ||
| 58 | #define BF_GPIOMON_BANK2_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 59 | |||
| 60 | /** | ||
| 61 | * Register: HW_GPIOMON_BANK3_DATAIN | ||
| 62 | * Address: 0x30 | ||
| 63 | * SCT: no | ||
| 64 | */ | ||
| 65 | #define HW_GPIOMON_BANK3_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x30)) | ||
| 66 | #define BP_GPIOMON_BANK3_DATAIN_DATA 0 | ||
| 67 | #define BM_GPIOMON_BANK3_DATAIN_DATA 0xffffffff | ||
| 68 | #define BF_GPIOMON_BANK3_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Register: HW_GPIOMON_BANK0_DATAOUT | ||
| 72 | * Address: 0x40 | ||
| 73 | * SCT: yes | ||
| 74 | */ | ||
| 75 | #define HW_GPIOMON_BANK0_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x0)) | ||
| 76 | #define HW_GPIOMON_BANK0_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x4)) | ||
| 77 | #define HW_GPIOMON_BANK0_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x8)) | ||
| 78 | #define HW_GPIOMON_BANK0_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0xc)) | ||
| 79 | #define BP_GPIOMON_BANK0_DATAOUT_DATA 0 | ||
| 80 | #define BM_GPIOMON_BANK0_DATAOUT_DATA 0xffffffff | ||
| 81 | #define BF_GPIOMON_BANK0_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 82 | |||
| 83 | /** | ||
| 84 | * Register: HW_GPIOMON_BANK1_DATAOUT | ||
| 85 | * Address: 0x50 | ||
| 86 | * SCT: yes | ||
| 87 | */ | ||
| 88 | #define HW_GPIOMON_BANK1_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x0)) | ||
| 89 | #define HW_GPIOMON_BANK1_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x4)) | ||
| 90 | #define HW_GPIOMON_BANK1_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x8)) | ||
| 91 | #define HW_GPIOMON_BANK1_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0xc)) | ||
| 92 | #define BP_GPIOMON_BANK1_DATAOUT_DATA 0 | ||
| 93 | #define BM_GPIOMON_BANK1_DATAOUT_DATA 0xffffffff | ||
| 94 | #define BF_GPIOMON_BANK1_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 95 | |||
| 96 | /** | ||
| 97 | * Register: HW_GPIOMON_BANK2_DATAOUT | ||
| 98 | * Address: 0x60 | ||
| 99 | * SCT: yes | ||
| 100 | */ | ||
| 101 | #define HW_GPIOMON_BANK2_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x0)) | ||
| 102 | #define HW_GPIOMON_BANK2_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x4)) | ||
| 103 | #define HW_GPIOMON_BANK2_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x8)) | ||
| 104 | #define HW_GPIOMON_BANK2_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0xc)) | ||
| 105 | #define BP_GPIOMON_BANK2_DATAOUT_DATA 0 | ||
| 106 | #define BM_GPIOMON_BANK2_DATAOUT_DATA 0xffffffff | ||
| 107 | #define BF_GPIOMON_BANK2_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Register: HW_GPIOMON_BANK3_DATAOUT | ||
| 111 | * Address: 0x70 | ||
| 112 | * SCT: yes | ||
| 113 | */ | ||
| 114 | #define HW_GPIOMON_BANK3_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x0)) | ||
| 115 | #define HW_GPIOMON_BANK3_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x4)) | ||
| 116 | #define HW_GPIOMON_BANK3_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x8)) | ||
| 117 | #define HW_GPIOMON_BANK3_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0xc)) | ||
| 118 | #define BP_GPIOMON_BANK3_DATAOUT_DATA 0 | ||
| 119 | #define BM_GPIOMON_BANK3_DATAOUT_DATA 0xffffffff | ||
| 120 | #define BF_GPIOMON_BANK3_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_GPIOMON_BANK0_DATAOEN | ||
| 124 | * Address: 0x80 | ||
| 125 | * SCT: yes | ||
| 126 | */ | ||
| 127 | #define HW_GPIOMON_BANK0_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x0)) | ||
| 128 | #define HW_GPIOMON_BANK0_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x4)) | ||
| 129 | #define HW_GPIOMON_BANK0_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x8)) | ||
| 130 | #define HW_GPIOMON_BANK0_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0xc)) | ||
| 131 | #define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0 | ||
| 132 | #define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
| 133 | #define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
| 134 | |||
| 135 | /** | ||
| 136 | * Register: HW_GPIOMON_BANK1_DATAOEN | ||
| 137 | * Address: 0x90 | ||
| 138 | * SCT: yes | ||
| 139 | */ | ||
| 140 | #define HW_GPIOMON_BANK1_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x0)) | ||
| 141 | #define HW_GPIOMON_BANK1_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x4)) | ||
| 142 | #define HW_GPIOMON_BANK1_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x8)) | ||
| 143 | #define HW_GPIOMON_BANK1_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0xc)) | ||
| 144 | #define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0 | ||
| 145 | #define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
| 146 | #define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
| 147 | |||
| 148 | /** | ||
| 149 | * Register: HW_GPIOMON_BANK2_DATAOEN | ||
| 150 | * Address: 0xa0 | ||
| 151 | * SCT: yes | ||
| 152 | */ | ||
| 153 | #define HW_GPIOMON_BANK2_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x0)) | ||
| 154 | #define HW_GPIOMON_BANK2_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x4)) | ||
| 155 | #define HW_GPIOMON_BANK2_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x8)) | ||
| 156 | #define HW_GPIOMON_BANK2_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0xc)) | ||
| 157 | #define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0 | ||
| 158 | #define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
| 159 | #define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
| 160 | |||
| 161 | /** | ||
| 162 | * Register: HW_GPIOMON_BANK3_DATAOEN | ||
| 163 | * Address: 0xb0 | ||
| 164 | * SCT: yes | ||
| 165 | */ | ||
| 166 | #define HW_GPIOMON_BANK3_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x0)) | ||
| 167 | #define HW_GPIOMON_BANK3_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x4)) | ||
| 168 | #define HW_GPIOMON_BANK3_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x8)) | ||
| 169 | #define HW_GPIOMON_BANK3_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0xc)) | ||
| 170 | #define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0 | ||
| 171 | #define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
| 172 | #define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
| 173 | |||
| 174 | /** | ||
| 175 | * Register: HW_GPIOMON_CTRL | ||
| 176 | * Address: 0xc0 | ||
| 177 | * SCT: yes | ||
| 178 | */ | ||
| 179 | #define HW_GPIOMON_CTRL (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x0)) | ||
| 180 | #define HW_GPIOMON_CTRL_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x4)) | ||
| 181 | #define HW_GPIOMON_CTRL_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x8)) | ||
| 182 | #define HW_GPIOMON_CTRL_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0xc)) | ||
| 183 | #define BP_GPIOMON_CTRL_RSRVD 4 | ||
| 184 | #define BM_GPIOMON_CTRL_RSRVD 0xfffffff0 | ||
| 185 | #define BF_GPIOMON_CTRL_RSRVD(v) (((v) << 4) & 0xfffffff0) | ||
| 186 | #define BP_GPIOMON_CTRL_PINMUX_ALT_RESET 3 | ||
| 187 | #define BM_GPIOMON_CTRL_PINMUX_ALT_RESET 0x8 | ||
| 188 | #define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v) (((v) << 3) & 0x8) | ||
| 189 | #define BP_GPIOMON_CTRL_OEN_8MA 2 | ||
| 190 | #define BM_GPIOMON_CTRL_OEN_8MA 0x4 | ||
| 191 | #define BF_GPIOMON_CTRL_OEN_8MA(v) (((v) << 2) & 0x4) | ||
| 192 | #define BP_GPIOMON_CTRL_OEN_4MA 1 | ||
| 193 | #define BM_GPIOMON_CTRL_OEN_4MA 0x2 | ||
| 194 | #define BF_GPIOMON_CTRL_OEN_4MA(v) (((v) << 1) & 0x2) | ||
| 195 | #define BP_GPIOMON_CTRL_OEN_NAND 0 | ||
| 196 | #define BM_GPIOMON_CTRL_OEN_NAND 0x1 | ||
| 197 | #define BF_GPIOMON_CTRL_OEN_NAND(v) (((v) << 0) & 0x1) | ||
| 198 | |||
| 199 | /** | ||
| 200 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK0 | ||
| 201 | * Address: 0xd0 | ||
| 202 | * SCT: yes | ||
| 203 | */ | ||
| 204 | #define HW_GPIOMON_ALT1_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x0)) | ||
| 205 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x4)) | ||
| 206 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x8)) | ||
| 207 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0xc)) | ||
| 208 | #define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0 | ||
| 209 | #define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0xffffffff | ||
| 210 | #define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 211 | |||
| 212 | /** | ||
| 213 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK1 | ||
| 214 | * Address: 0xe0 | ||
| 215 | * SCT: yes | ||
| 216 | */ | ||
| 217 | #define HW_GPIOMON_ALT1_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x0)) | ||
| 218 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x4)) | ||
| 219 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x8)) | ||
| 220 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0xc)) | ||
| 221 | #define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0 | ||
| 222 | #define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0xffffffff | ||
| 223 | #define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 224 | |||
| 225 | /** | ||
| 226 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK2 | ||
| 227 | * Address: 0xf0 | ||
| 228 | * SCT: yes | ||
| 229 | */ | ||
| 230 | #define HW_GPIOMON_ALT1_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x0)) | ||
| 231 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x4)) | ||
| 232 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x8)) | ||
| 233 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0xc)) | ||
| 234 | #define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0 | ||
| 235 | #define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0xffffffff | ||
| 236 | #define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 237 | |||
| 238 | /** | ||
| 239 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK3 | ||
| 240 | * Address: 0x100 | ||
| 241 | * SCT: yes | ||
| 242 | */ | ||
| 243 | #define HW_GPIOMON_ALT1_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x0)) | ||
| 244 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x4)) | ||
| 245 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x8)) | ||
| 246 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0xc)) | ||
| 247 | #define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0 | ||
| 248 | #define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0xffffffff | ||
| 249 | #define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 250 | |||
| 251 | /** | ||
| 252 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK0 | ||
| 253 | * Address: 0x110 | ||
| 254 | * SCT: yes | ||
| 255 | */ | ||
| 256 | #define HW_GPIOMON_ALT2_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x0)) | ||
| 257 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x4)) | ||
| 258 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x8)) | ||
| 259 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0xc)) | ||
| 260 | #define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0 | ||
| 261 | #define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0xffffffff | ||
| 262 | #define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 263 | |||
| 264 | /** | ||
| 265 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK1 | ||
| 266 | * Address: 0x120 | ||
| 267 | * SCT: yes | ||
| 268 | */ | ||
| 269 | #define HW_GPIOMON_ALT2_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x0)) | ||
| 270 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x4)) | ||
| 271 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x8)) | ||
| 272 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0xc)) | ||
| 273 | #define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0 | ||
| 274 | #define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0xffffffff | ||
| 275 | #define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 276 | |||
| 277 | /** | ||
| 278 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK2 | ||
| 279 | * Address: 0x130 | ||
| 280 | * SCT: yes | ||
| 281 | */ | ||
| 282 | #define HW_GPIOMON_ALT2_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x0)) | ||
| 283 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x4)) | ||
| 284 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x8)) | ||
| 285 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0xc)) | ||
| 286 | #define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0 | ||
| 287 | #define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0xffffffff | ||
| 288 | #define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 289 | |||
| 290 | /** | ||
| 291 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK3 | ||
| 292 | * Address: 0x140 | ||
| 293 | * SCT: yes | ||
| 294 | */ | ||
| 295 | #define HW_GPIOMON_ALT2_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x0)) | ||
| 296 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x4)) | ||
| 297 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x8)) | ||
| 298 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0xc)) | ||
| 299 | #define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0 | ||
| 300 | #define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0xffffffff | ||
| 301 | #define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 302 | |||
| 303 | /** | ||
| 304 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK0 | ||
| 305 | * Address: 0x150 | ||
| 306 | * SCT: yes | ||
| 307 | */ | ||
| 308 | #define HW_GPIOMON_ALT3_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x0)) | ||
| 309 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x4)) | ||
| 310 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x8)) | ||
| 311 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0xc)) | ||
| 312 | #define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0 | ||
| 313 | #define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0xffffffff | ||
| 314 | #define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 315 | |||
| 316 | /** | ||
| 317 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK1 | ||
| 318 | * Address: 0x160 | ||
| 319 | * SCT: yes | ||
| 320 | */ | ||
| 321 | #define HW_GPIOMON_ALT3_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x0)) | ||
| 322 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x4)) | ||
| 323 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x8)) | ||
| 324 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0xc)) | ||
| 325 | #define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0 | ||
| 326 | #define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0xffffffff | ||
| 327 | #define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 328 | |||
| 329 | /** | ||
| 330 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK2 | ||
| 331 | * Address: 0x170 | ||
| 332 | * SCT: yes | ||
| 333 | */ | ||
| 334 | #define HW_GPIOMON_ALT3_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x0)) | ||
| 335 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x4)) | ||
| 336 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x8)) | ||
| 337 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0xc)) | ||
| 338 | #define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0 | ||
| 339 | #define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0xffffffff | ||
| 340 | #define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 341 | |||
| 342 | /** | ||
| 343 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK3 | ||
| 344 | * Address: 0x180 | ||
| 345 | * SCT: yes | ||
| 346 | */ | ||
| 347 | #define HW_GPIOMON_ALT3_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x0)) | ||
| 348 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x4)) | ||
| 349 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x8)) | ||
| 350 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0xc)) | ||
| 351 | #define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0 | ||
| 352 | #define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0xffffffff | ||
| 353 | #define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
| 354 | |||
| 355 | #endif /* __HEADERGEN__STMP3700__GPIOMON__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h new file mode 100644 index 0000000000..d8dcb3b5cf --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-gpmi.h | |||
| @@ -0,0 +1,461 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__GPMI__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__GPMI__H__ | ||
| 25 | |||
| 26 | #define REGS_GPMI_BASE (0x8000c000) | ||
| 27 | |||
| 28 | #define REGS_GPMI_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_GPMI_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_GPMI_CTRL0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_GPMI_CTRL0_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_GPMI_CTRL0_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_GPMI_CTRL0_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_GPMI_CTRL0_SFTRST 31 | ||
| 40 | #define BM_GPMI_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BV_GPMI_CTRL0_SFTRST__RUN 0x0 | ||
| 42 | #define BV_GPMI_CTRL0_SFTRST__RESET 0x1 | ||
| 43 | #define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_GPMI_CTRL0_SFTRST_V(v) ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_GPMI_CTRL0_CLKGATE 30 | ||
| 46 | #define BM_GPMI_CTRL0_CLKGATE 0x40000000 | ||
| 47 | #define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_GPMI_CTRL0_CLKGATE_V(v) ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_GPMI_CTRL0_RUN 29 | ||
| 52 | #define BM_GPMI_CTRL0_RUN 0x20000000 | ||
| 53 | #define BV_GPMI_CTRL0_RUN__IDLE 0x0 | ||
| 54 | #define BV_GPMI_CTRL0_RUN__BUSY 0x1 | ||
| 55 | #define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_GPMI_CTRL0_RUN_V(v) ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000) | ||
| 57 | #define BP_GPMI_CTRL0_DEV_IRQ_EN 28 | ||
| 58 | #define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 | ||
| 59 | #define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
| 60 | #define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27 | ||
| 61 | #define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x8000000 | ||
| 62 | #define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & 0x8000000) | ||
| 63 | #define BP_GPMI_CTRL0_UDMA 26 | ||
| 64 | #define BM_GPMI_CTRL0_UDMA 0x4000000 | ||
| 65 | #define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 | ||
| 66 | #define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 | ||
| 67 | #define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & 0x4000000) | ||
| 68 | #define BF_GPMI_CTRL0_UDMA_V(v) ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000) | ||
| 69 | #define BP_GPMI_CTRL0_COMMAND_MODE 24 | ||
| 70 | #define BM_GPMI_CTRL0_COMMAND_MODE 0x3000000 | ||
| 71 | #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 | ||
| 72 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 | ||
| 73 | #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 | ||
| 74 | #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 | ||
| 75 | #define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & 0x3000000) | ||
| 76 | #define BF_GPMI_CTRL0_COMMAND_MODE_V(v) ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000) | ||
| 77 | #define BP_GPMI_CTRL0_WORD_LENGTH 23 | ||
| 78 | #define BM_GPMI_CTRL0_WORD_LENGTH 0x800000 | ||
| 79 | #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 | ||
| 80 | #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 | ||
| 81 | #define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & 0x800000) | ||
| 82 | #define BF_GPMI_CTRL0_WORD_LENGTH_V(v) ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000) | ||
| 83 | #define BP_GPMI_CTRL0_LOCK_CS 22 | ||
| 84 | #define BM_GPMI_CTRL0_LOCK_CS 0x400000 | ||
| 85 | #define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 | ||
| 86 | #define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 | ||
| 87 | #define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & 0x400000) | ||
| 88 | #define BF_GPMI_CTRL0_LOCK_CS_V(v) ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000) | ||
| 89 | #define BP_GPMI_CTRL0_CS 20 | ||
| 90 | #define BM_GPMI_CTRL0_CS 0x300000 | ||
| 91 | #define BF_GPMI_CTRL0_CS(v) (((v) << 20) & 0x300000) | ||
| 92 | #define BP_GPMI_CTRL0_ADDRESS 17 | ||
| 93 | #define BM_GPMI_CTRL0_ADDRESS 0xe0000 | ||
| 94 | #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 | ||
| 95 | #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 | ||
| 96 | #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 | ||
| 97 | #define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & 0xe0000) | ||
| 98 | #define BF_GPMI_CTRL0_ADDRESS_V(v) ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000) | ||
| 99 | #define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16 | ||
| 100 | #define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x10000 | ||
| 101 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 | ||
| 102 | #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 | ||
| 103 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & 0x10000) | ||
| 104 | #define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000) | ||
| 105 | #define BP_GPMI_CTRL0_XFER_COUNT 0 | ||
| 106 | #define BM_GPMI_CTRL0_XFER_COUNT 0xffff | ||
| 107 | #define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Register: HW_GPMI_COMPARE | ||
| 111 | * Address: 0x10 | ||
| 112 | * SCT: no | ||
| 113 | */ | ||
| 114 | #define HW_GPMI_COMPARE (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10)) | ||
| 115 | #define BP_GPMI_COMPARE_MASK 16 | ||
| 116 | #define BM_GPMI_COMPARE_MASK 0xffff0000 | ||
| 117 | #define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & 0xffff0000) | ||
| 118 | #define BP_GPMI_COMPARE_REFERENCE 0 | ||
| 119 | #define BM_GPMI_COMPARE_REFERENCE 0xffff | ||
| 120 | #define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & 0xffff) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_GPMI_ECCCTRL | ||
| 124 | * Address: 0x20 | ||
| 125 | * SCT: yes | ||
| 126 | */ | ||
| 127 | #define HW_GPMI_ECCCTRL (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0)) | ||
| 128 | #define HW_GPMI_ECCCTRL_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4)) | ||
| 129 | #define HW_GPMI_ECCCTRL_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8)) | ||
| 130 | #define HW_GPMI_ECCCTRL_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc)) | ||
| 131 | #define BP_GPMI_ECCCTRL_HANDLE 16 | ||
| 132 | #define BM_GPMI_ECCCTRL_HANDLE 0xffff0000 | ||
| 133 | #define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & 0xffff0000) | ||
| 134 | #define BP_GPMI_ECCCTRL_ECC_CMD 13 | ||
| 135 | #define BM_GPMI_ECCCTRL_ECC_CMD 0x6000 | ||
| 136 | #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 | ||
| 137 | #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 | ||
| 138 | #define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 | ||
| 139 | #define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 | ||
| 140 | #define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & 0x6000) | ||
| 141 | #define BF_GPMI_ECCCTRL_ECC_CMD_V(v) ((BV_GPMI_ECCCTRL_ECC_CMD__##v << 13) & 0x6000) | ||
| 142 | #define BP_GPMI_ECCCTRL_ENABLE_ECC 12 | ||
| 143 | #define BM_GPMI_ECCCTRL_ENABLE_ECC 0x1000 | ||
| 144 | #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 | ||
| 145 | #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 | ||
| 146 | #define BF_GPMI_ECCCTRL_ENABLE_ECC(v) (((v) << 12) & 0x1000) | ||
| 147 | #define BF_GPMI_ECCCTRL_ENABLE_ECC_V(v) ((BV_GPMI_ECCCTRL_ENABLE_ECC__##v << 12) & 0x1000) | ||
| 148 | #define BP_GPMI_ECCCTRL_BUFFER_MASK 0 | ||
| 149 | #define BM_GPMI_ECCCTRL_BUFFER_MASK 0x1ff | ||
| 150 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 | ||
| 151 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x80 | ||
| 152 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x40 | ||
| 153 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x20 | ||
| 154 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x10 | ||
| 155 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x8 | ||
| 156 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x4 | ||
| 157 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x2 | ||
| 158 | #define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x1 | ||
| 159 | #define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & 0x1ff) | ||
| 160 | #define BF_GPMI_ECCCTRL_BUFFER_MASK_V(v) ((BV_GPMI_ECCCTRL_BUFFER_MASK__##v << 0) & 0x1ff) | ||
| 161 | |||
| 162 | /** | ||
| 163 | * Register: HW_GPMI_ECCCOUNT | ||
| 164 | * Address: 0x30 | ||
| 165 | * SCT: no | ||
| 166 | */ | ||
| 167 | #define HW_GPMI_ECCCOUNT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30)) | ||
| 168 | #define BP_GPMI_ECCCOUNT_COUNT 0 | ||
| 169 | #define BM_GPMI_ECCCOUNT_COUNT 0xffff | ||
| 170 | #define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & 0xffff) | ||
| 171 | |||
| 172 | /** | ||
| 173 | * Register: HW_GPMI_PAYLOAD | ||
| 174 | * Address: 0x40 | ||
| 175 | * SCT: no | ||
| 176 | */ | ||
| 177 | #define HW_GPMI_PAYLOAD (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40)) | ||
| 178 | #define BP_GPMI_PAYLOAD_ADDRESS 2 | ||
| 179 | #define BM_GPMI_PAYLOAD_ADDRESS 0xfffffffc | ||
| 180 | #define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
| 181 | |||
| 182 | /** | ||
| 183 | * Register: HW_GPMI_AUXILIARY | ||
| 184 | * Address: 0x50 | ||
| 185 | * SCT: no | ||
| 186 | */ | ||
| 187 | #define HW_GPMI_AUXILIARY (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50)) | ||
| 188 | #define BP_GPMI_AUXILIARY_ADDRESS 2 | ||
| 189 | #define BM_GPMI_AUXILIARY_ADDRESS 0xfffffffc | ||
| 190 | #define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
| 191 | |||
| 192 | /** | ||
| 193 | * Register: HW_GPMI_CTRL1 | ||
| 194 | * Address: 0x60 | ||
| 195 | * SCT: yes | ||
| 196 | */ | ||
| 197 | #define HW_GPMI_CTRL1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x0)) | ||
| 198 | #define HW_GPMI_CTRL1_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x4)) | ||
| 199 | #define HW_GPMI_CTRL1_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0x8)) | ||
| 200 | #define HW_GPMI_CTRL1_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60 + 0xc)) | ||
| 201 | #define BP_GPMI_CTRL1_DSAMPLE_TIME 12 | ||
| 202 | #define BM_GPMI_CTRL1_DSAMPLE_TIME 0x7000 | ||
| 203 | #define BF_GPMI_CTRL1_DSAMPLE_TIME(v) (((v) << 12) & 0x7000) | ||
| 204 | #define BP_GPMI_CTRL1_DMA2ECC_MODE 11 | ||
| 205 | #define BM_GPMI_CTRL1_DMA2ECC_MODE 0x800 | ||
| 206 | #define BF_GPMI_CTRL1_DMA2ECC_MODE(v) (((v) << 11) & 0x800) | ||
| 207 | #define BP_GPMI_CTRL1_DEV_IRQ 10 | ||
| 208 | #define BM_GPMI_CTRL1_DEV_IRQ 0x400 | ||
| 209 | #define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & 0x400) | ||
| 210 | #define BP_GPMI_CTRL1_TIMEOUT_IRQ 9 | ||
| 211 | #define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x200 | ||
| 212 | #define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & 0x200) | ||
| 213 | #define BP_GPMI_CTRL1_BURST_EN 8 | ||
| 214 | #define BM_GPMI_CTRL1_BURST_EN 0x100 | ||
| 215 | #define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & 0x100) | ||
| 216 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7 | ||
| 217 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x80 | ||
| 218 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & 0x80) | ||
| 219 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6 | ||
| 220 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x40 | ||
| 221 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & 0x40) | ||
| 222 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5 | ||
| 223 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x20 | ||
| 224 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & 0x20) | ||
| 225 | #define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4 | ||
| 226 | #define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x10 | ||
| 227 | #define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & 0x10) | ||
| 228 | #define BP_GPMI_CTRL1_DEV_RESET 3 | ||
| 229 | #define BM_GPMI_CTRL1_DEV_RESET 0x8 | ||
| 230 | #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 | ||
| 231 | #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 | ||
| 232 | #define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & 0x8) | ||
| 233 | #define BF_GPMI_CTRL1_DEV_RESET_V(v) ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8) | ||
| 234 | #define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2 | ||
| 235 | #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x4 | ||
| 236 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 | ||
| 237 | #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 | ||
| 238 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & 0x4) | ||
| 239 | #define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v) ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4) | ||
| 240 | #define BP_GPMI_CTRL1_CAMERA_MODE 1 | ||
| 241 | #define BM_GPMI_CTRL1_CAMERA_MODE 0x2 | ||
| 242 | #define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & 0x2) | ||
| 243 | #define BP_GPMI_CTRL1_GPMI_MODE 0 | ||
| 244 | #define BM_GPMI_CTRL1_GPMI_MODE 0x1 | ||
| 245 | #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 | ||
| 246 | #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 | ||
| 247 | #define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & 0x1) | ||
| 248 | #define BF_GPMI_CTRL1_GPMI_MODE_V(v) ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1) | ||
| 249 | |||
| 250 | /** | ||
| 251 | * Register: HW_GPMI_TIMING0 | ||
| 252 | * Address: 0x70 | ||
| 253 | * SCT: no | ||
| 254 | */ | ||
| 255 | #define HW_GPMI_TIMING0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70)) | ||
| 256 | #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 | ||
| 257 | #define BM_GPMI_TIMING0_ADDRESS_SETUP 0xff0000 | ||
| 258 | #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & 0xff0000) | ||
| 259 | #define BP_GPMI_TIMING0_DATA_HOLD 8 | ||
| 260 | #define BM_GPMI_TIMING0_DATA_HOLD 0xff00 | ||
| 261 | #define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
| 262 | #define BP_GPMI_TIMING0_DATA_SETUP 0 | ||
| 263 | #define BM_GPMI_TIMING0_DATA_SETUP 0xff | ||
| 264 | #define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
| 265 | |||
| 266 | /** | ||
| 267 | * Register: HW_GPMI_TIMING1 | ||
| 268 | * Address: 0x80 | ||
| 269 | * SCT: no | ||
| 270 | */ | ||
| 271 | #define HW_GPMI_TIMING1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80)) | ||
| 272 | #define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 | ||
| 273 | #define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xffff0000 | ||
| 274 | #define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
| 275 | |||
| 276 | /** | ||
| 277 | * Register: HW_GPMI_TIMING2 | ||
| 278 | * Address: 0x90 | ||
| 279 | * SCT: no | ||
| 280 | */ | ||
| 281 | #define HW_GPMI_TIMING2 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x90)) | ||
| 282 | #define BP_GPMI_TIMING2_UDMA_TRP 24 | ||
| 283 | #define BM_GPMI_TIMING2_UDMA_TRP 0xff000000 | ||
| 284 | #define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & 0xff000000) | ||
| 285 | #define BP_GPMI_TIMING2_UDMA_ENV 16 | ||
| 286 | #define BM_GPMI_TIMING2_UDMA_ENV 0xff0000 | ||
| 287 | #define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & 0xff0000) | ||
| 288 | #define BP_GPMI_TIMING2_UDMA_HOLD 8 | ||
| 289 | #define BM_GPMI_TIMING2_UDMA_HOLD 0xff00 | ||
| 290 | #define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & 0xff00) | ||
| 291 | #define BP_GPMI_TIMING2_UDMA_SETUP 0 | ||
| 292 | #define BM_GPMI_TIMING2_UDMA_SETUP 0xff | ||
| 293 | #define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & 0xff) | ||
| 294 | |||
| 295 | /** | ||
| 296 | * Register: HW_GPMI_DATA | ||
| 297 | * Address: 0xa0 | ||
| 298 | * SCT: no | ||
| 299 | */ | ||
| 300 | #define HW_GPMI_DATA (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xa0)) | ||
| 301 | #define BP_GPMI_DATA_DATA 0 | ||
| 302 | #define BM_GPMI_DATA_DATA 0xffffffff | ||
| 303 | #define BF_GPMI_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 304 | |||
| 305 | /** | ||
| 306 | * Register: HW_GPMI_STAT | ||
| 307 | * Address: 0xb0 | ||
| 308 | * SCT: no | ||
| 309 | */ | ||
| 310 | #define HW_GPMI_STAT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xb0)) | ||
| 311 | #define BP_GPMI_STAT_PRESENT 31 | ||
| 312 | #define BM_GPMI_STAT_PRESENT 0x80000000 | ||
| 313 | #define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 | ||
| 314 | #define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 | ||
| 315 | #define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 316 | #define BF_GPMI_STAT_PRESENT_V(v) ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000) | ||
| 317 | #define BP_GPMI_STAT_RDY_TIMEOUT 8 | ||
| 318 | #define BM_GPMI_STAT_RDY_TIMEOUT 0xf00 | ||
| 319 | #define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & 0xf00) | ||
| 320 | #define BP_GPMI_STAT_ATA_IRQ 7 | ||
| 321 | #define BM_GPMI_STAT_ATA_IRQ 0x80 | ||
| 322 | #define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & 0x80) | ||
| 323 | #define BP_GPMI_STAT_INVALID_BUFFER_MASK 6 | ||
| 324 | #define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x40 | ||
| 325 | #define BF_GPMI_STAT_INVALID_BUFFER_MASK(v) (((v) << 6) & 0x40) | ||
| 326 | #define BP_GPMI_STAT_FIFO_EMPTY 5 | ||
| 327 | #define BM_GPMI_STAT_FIFO_EMPTY 0x20 | ||
| 328 | #define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 | ||
| 329 | #define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 | ||
| 330 | #define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
| 331 | #define BF_GPMI_STAT_FIFO_EMPTY_V(v) ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20) | ||
| 332 | #define BP_GPMI_STAT_FIFO_FULL 4 | ||
| 333 | #define BM_GPMI_STAT_FIFO_FULL 0x10 | ||
| 334 | #define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 | ||
| 335 | #define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 | ||
| 336 | #define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & 0x10) | ||
| 337 | #define BF_GPMI_STAT_FIFO_FULL_V(v) ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10) | ||
| 338 | #define BP_GPMI_STAT_DEV3_ERROR 3 | ||
| 339 | #define BM_GPMI_STAT_DEV3_ERROR 0x8 | ||
| 340 | #define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & 0x8) | ||
| 341 | #define BP_GPMI_STAT_DEV2_ERROR 2 | ||
| 342 | #define BM_GPMI_STAT_DEV2_ERROR 0x4 | ||
| 343 | #define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & 0x4) | ||
| 344 | #define BP_GPMI_STAT_DEV1_ERROR 1 | ||
| 345 | #define BM_GPMI_STAT_DEV1_ERROR 0x2 | ||
| 346 | #define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & 0x2) | ||
| 347 | #define BP_GPMI_STAT_DEV0_ERROR 0 | ||
| 348 | #define BM_GPMI_STAT_DEV0_ERROR 0x1 | ||
| 349 | #define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & 0x1) | ||
| 350 | |||
| 351 | /** | ||
| 352 | * Register: HW_GPMI_DEBUG | ||
| 353 | * Address: 0xc0 | ||
| 354 | * SCT: no | ||
| 355 | */ | ||
| 356 | #define HW_GPMI_DEBUG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xc0)) | ||
| 357 | #define BP_GPMI_DEBUG_READY3 31 | ||
| 358 | #define BM_GPMI_DEBUG_READY3 0x80000000 | ||
| 359 | #define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & 0x80000000) | ||
| 360 | #define BP_GPMI_DEBUG_READY2 30 | ||
| 361 | #define BM_GPMI_DEBUG_READY2 0x40000000 | ||
| 362 | #define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & 0x40000000) | ||
| 363 | #define BP_GPMI_DEBUG_READY1 29 | ||
| 364 | #define BM_GPMI_DEBUG_READY1 0x20000000 | ||
| 365 | #define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & 0x20000000) | ||
| 366 | #define BP_GPMI_DEBUG_READY0 28 | ||
| 367 | #define BM_GPMI_DEBUG_READY0 0x10000000 | ||
| 368 | #define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & 0x10000000) | ||
| 369 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27 | ||
| 370 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x8000000 | ||
| 371 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & 0x8000000) | ||
| 372 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26 | ||
| 373 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x4000000 | ||
| 374 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & 0x4000000) | ||
| 375 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25 | ||
| 376 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x2000000 | ||
| 377 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & 0x2000000) | ||
| 378 | #define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24 | ||
| 379 | #define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x1000000 | ||
| 380 | #define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & 0x1000000) | ||
| 381 | #define BP_GPMI_DEBUG_SENSE3 23 | ||
| 382 | #define BM_GPMI_DEBUG_SENSE3 0x800000 | ||
| 383 | #define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & 0x800000) | ||
| 384 | #define BP_GPMI_DEBUG_SENSE2 22 | ||
| 385 | #define BM_GPMI_DEBUG_SENSE2 0x400000 | ||
| 386 | #define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & 0x400000) | ||
| 387 | #define BP_GPMI_DEBUG_SENSE1 21 | ||
| 388 | #define BM_GPMI_DEBUG_SENSE1 0x200000 | ||
| 389 | #define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & 0x200000) | ||
| 390 | #define BP_GPMI_DEBUG_SENSE0 20 | ||
| 391 | #define BM_GPMI_DEBUG_SENSE0 0x100000 | ||
| 392 | #define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & 0x100000) | ||
| 393 | #define BP_GPMI_DEBUG_DMAREQ3 19 | ||
| 394 | #define BM_GPMI_DEBUG_DMAREQ3 0x80000 | ||
| 395 | #define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & 0x80000) | ||
| 396 | #define BP_GPMI_DEBUG_DMAREQ2 18 | ||
| 397 | #define BM_GPMI_DEBUG_DMAREQ2 0x40000 | ||
| 398 | #define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & 0x40000) | ||
| 399 | #define BP_GPMI_DEBUG_DMAREQ1 17 | ||
| 400 | #define BM_GPMI_DEBUG_DMAREQ1 0x20000 | ||
| 401 | #define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & 0x20000) | ||
| 402 | #define BP_GPMI_DEBUG_DMAREQ0 16 | ||
| 403 | #define BM_GPMI_DEBUG_DMAREQ0 0x10000 | ||
| 404 | #define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & 0x10000) | ||
| 405 | #define BP_GPMI_DEBUG_CMD_END 12 | ||
| 406 | #define BM_GPMI_DEBUG_CMD_END 0xf000 | ||
| 407 | #define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & 0xf000) | ||
| 408 | #define BP_GPMI_DEBUG_UDMA_STATE 8 | ||
| 409 | #define BM_GPMI_DEBUG_UDMA_STATE 0xf00 | ||
| 410 | #define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & 0xf00) | ||
| 411 | #define BP_GPMI_DEBUG_BUSY 7 | ||
| 412 | #define BM_GPMI_DEBUG_BUSY 0x80 | ||
| 413 | #define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 | ||
| 414 | #define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 | ||
| 415 | #define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & 0x80) | ||
| 416 | #define BF_GPMI_DEBUG_BUSY_V(v) ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80) | ||
| 417 | #define BP_GPMI_DEBUG_PIN_STATE 4 | ||
| 418 | #define BM_GPMI_DEBUG_PIN_STATE 0x70 | ||
| 419 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 | ||
| 420 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 | ||
| 421 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 | ||
| 422 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 | ||
| 423 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 | ||
| 424 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 | ||
| 425 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 | ||
| 426 | #define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 | ||
| 427 | #define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & 0x70) | ||
| 428 | #define BF_GPMI_DEBUG_PIN_STATE_V(v) ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70) | ||
| 429 | #define BP_GPMI_DEBUG_MAIN_STATE 0 | ||
| 430 | #define BM_GPMI_DEBUG_MAIN_STATE 0xf | ||
| 431 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 | ||
| 432 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 | ||
| 433 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 | ||
| 434 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 | ||
| 435 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 | ||
| 436 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 | ||
| 437 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 | ||
| 438 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 | ||
| 439 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 | ||
| 440 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 | ||
| 441 | #define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xa | ||
| 442 | #define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & 0xf) | ||
| 443 | #define BF_GPMI_DEBUG_MAIN_STATE_V(v) ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf) | ||
| 444 | |||
| 445 | /** | ||
| 446 | * Register: HW_GPMI_VERSION | ||
| 447 | * Address: 0xd0 | ||
| 448 | * SCT: no | ||
| 449 | */ | ||
| 450 | #define HW_GPMI_VERSION (*(volatile unsigned long *)(REGS_GPMI_BASE + 0xd0)) | ||
| 451 | #define BP_GPMI_VERSION_MAJOR 24 | ||
| 452 | #define BM_GPMI_VERSION_MAJOR 0xff000000 | ||
| 453 | #define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 454 | #define BP_GPMI_VERSION_MINOR 16 | ||
| 455 | #define BM_GPMI_VERSION_MINOR 0xff0000 | ||
| 456 | #define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 457 | #define BP_GPMI_VERSION_STEP 0 | ||
| 458 | #define BM_GPMI_VERSION_STEP 0xffff | ||
| 459 | #define BF_GPMI_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 460 | |||
| 461 | #endif /* __HEADERGEN__STMP3700__GPMI__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h new file mode 100644 index 0000000000..ea34d27db2 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-i2c.h | |||
| @@ -0,0 +1,537 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__I2C__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__I2C__H__ | ||
| 25 | |||
| 26 | #define REGS_I2C_BASE (0x80058000) | ||
| 27 | |||
| 28 | #define REGS_I2C_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_I2C_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_I2C_CTRL0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_I2C_CTRL0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_I2C_CTRL0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_I2C_CTRL0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_I2C_CTRL0_SFTRST 31 | ||
| 40 | #define BM_I2C_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BV_I2C_CTRL0_SFTRST__RUN 0x0 | ||
| 42 | #define BV_I2C_CTRL0_SFTRST__RESET 0x1 | ||
| 43 | #define BF_I2C_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_I2C_CTRL0_SFTRST_V(v) ((BV_I2C_CTRL0_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_I2C_CTRL0_CLKGATE 30 | ||
| 46 | #define BM_I2C_CTRL0_CLKGATE 0x40000000 | ||
| 47 | #define BV_I2C_CTRL0_CLKGATE__RUN 0x0 | ||
| 48 | #define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 | ||
| 49 | #define BF_I2C_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 50 | #define BF_I2C_CTRL0_CLKGATE_V(v) ((BV_I2C_CTRL0_CLKGATE__##v << 30) & 0x40000000) | ||
| 51 | #define BP_I2C_CTRL0_RUN 29 | ||
| 52 | #define BM_I2C_CTRL0_RUN 0x20000000 | ||
| 53 | #define BV_I2C_CTRL0_RUN__HALT 0x0 | ||
| 54 | #define BV_I2C_CTRL0_RUN__RUN 0x1 | ||
| 55 | #define BF_I2C_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
| 56 | #define BF_I2C_CTRL0_RUN_V(v) ((BV_I2C_CTRL0_RUN__##v << 29) & 0x20000000) | ||
| 57 | #define BP_I2C_CTRL0_PRE_ACK 27 | ||
| 58 | #define BM_I2C_CTRL0_PRE_ACK 0x8000000 | ||
| 59 | #define BF_I2C_CTRL0_PRE_ACK(v) (((v) << 27) & 0x8000000) | ||
| 60 | #define BP_I2C_CTRL0_ACKNOWLEDGE 26 | ||
| 61 | #define BM_I2C_CTRL0_ACKNOWLEDGE 0x4000000 | ||
| 62 | #define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 | ||
| 63 | #define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 | ||
| 64 | #define BF_I2C_CTRL0_ACKNOWLEDGE(v) (((v) << 26) & 0x4000000) | ||
| 65 | #define BF_I2C_CTRL0_ACKNOWLEDGE_V(v) ((BV_I2C_CTRL0_ACKNOWLEDGE__##v << 26) & 0x4000000) | ||
| 66 | #define BP_I2C_CTRL0_SEND_NAK_ON_LAST 25 | ||
| 67 | #define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x2000000 | ||
| 68 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 | ||
| 69 | #define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 | ||
| 70 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST(v) (((v) << 25) & 0x2000000) | ||
| 71 | #define BF_I2C_CTRL0_SEND_NAK_ON_LAST_V(v) ((BV_I2C_CTRL0_SEND_NAK_ON_LAST__##v << 25) & 0x2000000) | ||
| 72 | #define BP_I2C_CTRL0_PIO_MODE 24 | ||
| 73 | #define BM_I2C_CTRL0_PIO_MODE 0x1000000 | ||
| 74 | #define BF_I2C_CTRL0_PIO_MODE(v) (((v) << 24) & 0x1000000) | ||
| 75 | #define BP_I2C_CTRL0_MULTI_MASTER 23 | ||
| 76 | #define BM_I2C_CTRL0_MULTI_MASTER 0x800000 | ||
| 77 | #define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 | ||
| 78 | #define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 | ||
| 79 | #define BF_I2C_CTRL0_MULTI_MASTER(v) (((v) << 23) & 0x800000) | ||
| 80 | #define BF_I2C_CTRL0_MULTI_MASTER_V(v) ((BV_I2C_CTRL0_MULTI_MASTER__##v << 23) & 0x800000) | ||
| 81 | #define BP_I2C_CTRL0_CLOCK_HELD 22 | ||
| 82 | #define BM_I2C_CTRL0_CLOCK_HELD 0x400000 | ||
| 83 | #define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 | ||
| 84 | #define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 | ||
| 85 | #define BF_I2C_CTRL0_CLOCK_HELD(v) (((v) << 22) & 0x400000) | ||
| 86 | #define BF_I2C_CTRL0_CLOCK_HELD_V(v) ((BV_I2C_CTRL0_CLOCK_HELD__##v << 22) & 0x400000) | ||
| 87 | #define BP_I2C_CTRL0_RETAIN_CLOCK 21 | ||
| 88 | #define BM_I2C_CTRL0_RETAIN_CLOCK 0x200000 | ||
| 89 | #define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 | ||
| 90 | #define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 | ||
| 91 | #define BF_I2C_CTRL0_RETAIN_CLOCK(v) (((v) << 21) & 0x200000) | ||
| 92 | #define BF_I2C_CTRL0_RETAIN_CLOCK_V(v) ((BV_I2C_CTRL0_RETAIN_CLOCK__##v << 21) & 0x200000) | ||
| 93 | #define BP_I2C_CTRL0_POST_SEND_STOP 20 | ||
| 94 | #define BM_I2C_CTRL0_POST_SEND_STOP 0x100000 | ||
| 95 | #define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 | ||
| 96 | #define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 | ||
| 97 | #define BF_I2C_CTRL0_POST_SEND_STOP(v) (((v) << 20) & 0x100000) | ||
| 98 | #define BF_I2C_CTRL0_POST_SEND_STOP_V(v) ((BV_I2C_CTRL0_POST_SEND_STOP__##v << 20) & 0x100000) | ||
| 99 | #define BP_I2C_CTRL0_PRE_SEND_START 19 | ||
| 100 | #define BM_I2C_CTRL0_PRE_SEND_START 0x80000 | ||
| 101 | #define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 | ||
| 102 | #define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 | ||
| 103 | #define BF_I2C_CTRL0_PRE_SEND_START(v) (((v) << 19) & 0x80000) | ||
| 104 | #define BF_I2C_CTRL0_PRE_SEND_START_V(v) ((BV_I2C_CTRL0_PRE_SEND_START__##v << 19) & 0x80000) | ||
| 105 | #define BP_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 18 | ||
| 106 | #define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x40000 | ||
| 107 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 | ||
| 108 | #define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 | ||
| 109 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE(v) (((v) << 18) & 0x40000) | ||
| 110 | #define BF_I2C_CTRL0_SLAVE_ADDRESS_ENABLE_V(v) ((BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__##v << 18) & 0x40000) | ||
| 111 | #define BP_I2C_CTRL0_MASTER_MODE 17 | ||
| 112 | #define BM_I2C_CTRL0_MASTER_MODE 0x20000 | ||
| 113 | #define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 | ||
| 114 | #define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 | ||
| 115 | #define BF_I2C_CTRL0_MASTER_MODE(v) (((v) << 17) & 0x20000) | ||
| 116 | #define BF_I2C_CTRL0_MASTER_MODE_V(v) ((BV_I2C_CTRL0_MASTER_MODE__##v << 17) & 0x20000) | ||
| 117 | #define BP_I2C_CTRL0_DIRECTION 16 | ||
| 118 | #define BM_I2C_CTRL0_DIRECTION 0x10000 | ||
| 119 | #define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 | ||
| 120 | #define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 | ||
| 121 | #define BF_I2C_CTRL0_DIRECTION(v) (((v) << 16) & 0x10000) | ||
| 122 | #define BF_I2C_CTRL0_DIRECTION_V(v) ((BV_I2C_CTRL0_DIRECTION__##v << 16) & 0x10000) | ||
| 123 | #define BP_I2C_CTRL0_XFER_COUNT 0 | ||
| 124 | #define BM_I2C_CTRL0_XFER_COUNT 0xffff | ||
| 125 | #define BF_I2C_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 126 | |||
| 127 | /** | ||
| 128 | * Register: HW_I2C_TIMING0 | ||
| 129 | * Address: 0x10 | ||
| 130 | * SCT: yes | ||
| 131 | */ | ||
| 132 | #define HW_I2C_TIMING0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x0)) | ||
| 133 | #define HW_I2C_TIMING0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x4)) | ||
| 134 | #define HW_I2C_TIMING0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0x8)) | ||
| 135 | #define HW_I2C_TIMING0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x10 + 0xc)) | ||
| 136 | #define BP_I2C_TIMING0_HIGH_COUNT 16 | ||
| 137 | #define BM_I2C_TIMING0_HIGH_COUNT 0x3ff0000 | ||
| 138 | #define BF_I2C_TIMING0_HIGH_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
| 139 | #define BP_I2C_TIMING0_RCV_COUNT 0 | ||
| 140 | #define BM_I2C_TIMING0_RCV_COUNT 0x3ff | ||
| 141 | #define BF_I2C_TIMING0_RCV_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 142 | |||
| 143 | /** | ||
| 144 | * Register: HW_I2C_TIMING1 | ||
| 145 | * Address: 0x20 | ||
| 146 | * SCT: yes | ||
| 147 | */ | ||
| 148 | #define HW_I2C_TIMING1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x0)) | ||
| 149 | #define HW_I2C_TIMING1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x4)) | ||
| 150 | #define HW_I2C_TIMING1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0x8)) | ||
| 151 | #define HW_I2C_TIMING1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x20 + 0xc)) | ||
| 152 | #define BP_I2C_TIMING1_LOW_COUNT 16 | ||
| 153 | #define BM_I2C_TIMING1_LOW_COUNT 0x3ff0000 | ||
| 154 | #define BF_I2C_TIMING1_LOW_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
| 155 | #define BP_I2C_TIMING1_XMIT_COUNT 0 | ||
| 156 | #define BM_I2C_TIMING1_XMIT_COUNT 0x3ff | ||
| 157 | #define BF_I2C_TIMING1_XMIT_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 158 | |||
| 159 | /** | ||
| 160 | * Register: HW_I2C_TIMING2 | ||
| 161 | * Address: 0x30 | ||
| 162 | * SCT: yes | ||
| 163 | */ | ||
| 164 | #define HW_I2C_TIMING2 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x0)) | ||
| 165 | #define HW_I2C_TIMING2_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x4)) | ||
| 166 | #define HW_I2C_TIMING2_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0x8)) | ||
| 167 | #define HW_I2C_TIMING2_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x30 + 0xc)) | ||
| 168 | #define BP_I2C_TIMING2_BUS_FREE 16 | ||
| 169 | #define BM_I2C_TIMING2_BUS_FREE 0x3ff0000 | ||
| 170 | #define BF_I2C_TIMING2_BUS_FREE(v) (((v) << 16) & 0x3ff0000) | ||
| 171 | #define BP_I2C_TIMING2_LEADIN_COUNT 0 | ||
| 172 | #define BM_I2C_TIMING2_LEADIN_COUNT 0x3ff | ||
| 173 | #define BF_I2C_TIMING2_LEADIN_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 174 | |||
| 175 | /** | ||
| 176 | * Register: HW_I2C_CTRL1 | ||
| 177 | * Address: 0x40 | ||
| 178 | * SCT: yes | ||
| 179 | */ | ||
| 180 | #define HW_I2C_CTRL1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x0)) | ||
| 181 | #define HW_I2C_CTRL1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x4)) | ||
| 182 | #define HW_I2C_CTRL1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0x8)) | ||
| 183 | #define HW_I2C_CTRL1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x40 + 0xc)) | ||
| 184 | #define BP_I2C_CTRL1_BCAST_SLAVE_EN 24 | ||
| 185 | #define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x1000000 | ||
| 186 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 | ||
| 187 | #define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 | ||
| 188 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN(v) (((v) << 24) & 0x1000000) | ||
| 189 | #define BF_I2C_CTRL1_BCAST_SLAVE_EN_V(v) ((BV_I2C_CTRL1_BCAST_SLAVE_EN__##v << 24) & 0x1000000) | ||
| 190 | #define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 | ||
| 191 | #define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0xff0000 | ||
| 192 | #define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) (((v) << 16) & 0xff0000) | ||
| 193 | #define BP_I2C_CTRL1_BUS_FREE_IRQ_EN 15 | ||
| 194 | #define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x8000 | ||
| 195 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 | ||
| 196 | #define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 | ||
| 197 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
| 198 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_EN_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ_EN__##v << 15) & 0x8000) | ||
| 199 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 14 | ||
| 200 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x4000 | ||
| 201 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 | ||
| 202 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 | ||
| 203 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 204 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__##v << 14) & 0x4000) | ||
| 205 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 13 | ||
| 206 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x2000 | ||
| 207 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 | ||
| 208 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 | ||
| 209 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
| 210 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__##v << 13) & 0x2000) | ||
| 211 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 12 | ||
| 212 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x1000 | ||
| 213 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 | ||
| 214 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 | ||
| 215 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
| 216 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__##v << 12) & 0x1000) | ||
| 217 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ_EN 11 | ||
| 218 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x800 | ||
| 219 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 | ||
| 220 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 | ||
| 221 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN(v) (((v) << 11) & 0x800) | ||
| 222 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_EN_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__##v << 11) & 0x800) | ||
| 223 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ_EN 10 | ||
| 224 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x400 | ||
| 225 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 | ||
| 226 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 | ||
| 227 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN(v) (((v) << 10) & 0x400) | ||
| 228 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_EN_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__##v << 10) & 0x400) | ||
| 229 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ_EN 9 | ||
| 230 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x200 | ||
| 231 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 | ||
| 232 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 | ||
| 233 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN(v) (((v) << 9) & 0x200) | ||
| 234 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__##v << 9) & 0x200) | ||
| 235 | #define BP_I2C_CTRL1_SLAVE_IRQ_EN 8 | ||
| 236 | #define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x100 | ||
| 237 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 | ||
| 238 | #define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 | ||
| 239 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN(v) (((v) << 8) & 0x100) | ||
| 240 | #define BF_I2C_CTRL1_SLAVE_IRQ_EN_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ_EN__##v << 8) & 0x100) | ||
| 241 | #define BP_I2C_CTRL1_BUS_FREE_IRQ 7 | ||
| 242 | #define BM_I2C_CTRL1_BUS_FREE_IRQ 0x80 | ||
| 243 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 | ||
| 244 | #define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 | ||
| 245 | #define BF_I2C_CTRL1_BUS_FREE_IRQ(v) (((v) << 7) & 0x80) | ||
| 246 | #define BF_I2C_CTRL1_BUS_FREE_IRQ_V(v) ((BV_I2C_CTRL1_BUS_FREE_IRQ__##v << 7) & 0x80) | ||
| 247 | #define BP_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 6 | ||
| 248 | #define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | ||
| 249 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 | ||
| 250 | #define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 | ||
| 251 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ(v) (((v) << 6) & 0x40) | ||
| 252 | #define BF_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_V(v) ((BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__##v << 6) & 0x40) | ||
| 253 | #define BP_I2C_CTRL1_NO_SLAVE_ACK_IRQ 5 | ||
| 254 | #define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | ||
| 255 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 | ||
| 256 | #define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 | ||
| 257 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ(v) (((v) << 5) & 0x20) | ||
| 258 | #define BF_I2C_CTRL1_NO_SLAVE_ACK_IRQ_V(v) ((BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__##v << 5) & 0x20) | ||
| 259 | #define BP_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 4 | ||
| 260 | #define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | ||
| 261 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 | ||
| 262 | #define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 | ||
| 263 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ(v) (((v) << 4) & 0x10) | ||
| 264 | #define BF_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_V(v) ((BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__##v << 4) & 0x10) | ||
| 265 | #define BP_I2C_CTRL1_EARLY_TERM_IRQ 3 | ||
| 266 | #define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x8 | ||
| 267 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 | ||
| 268 | #define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 | ||
| 269 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ(v) (((v) << 3) & 0x8) | ||
| 270 | #define BF_I2C_CTRL1_EARLY_TERM_IRQ_V(v) ((BV_I2C_CTRL1_EARLY_TERM_IRQ__##v << 3) & 0x8) | ||
| 271 | #define BP_I2C_CTRL1_MASTER_LOSS_IRQ 2 | ||
| 272 | #define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x4 | ||
| 273 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 | ||
| 274 | #define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 | ||
| 275 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ(v) (((v) << 2) & 0x4) | ||
| 276 | #define BF_I2C_CTRL1_MASTER_LOSS_IRQ_V(v) ((BV_I2C_CTRL1_MASTER_LOSS_IRQ__##v << 2) & 0x4) | ||
| 277 | #define BP_I2C_CTRL1_SLAVE_STOP_IRQ 1 | ||
| 278 | #define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x2 | ||
| 279 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 | ||
| 280 | #define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 | ||
| 281 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ(v) (((v) << 1) & 0x2) | ||
| 282 | #define BF_I2C_CTRL1_SLAVE_STOP_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_STOP_IRQ__##v << 1) & 0x2) | ||
| 283 | #define BP_I2C_CTRL1_SLAVE_IRQ 0 | ||
| 284 | #define BM_I2C_CTRL1_SLAVE_IRQ 0x1 | ||
| 285 | #define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 | ||
| 286 | #define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 | ||
| 287 | #define BF_I2C_CTRL1_SLAVE_IRQ(v) (((v) << 0) & 0x1) | ||
| 288 | #define BF_I2C_CTRL1_SLAVE_IRQ_V(v) ((BV_I2C_CTRL1_SLAVE_IRQ__##v << 0) & 0x1) | ||
| 289 | |||
| 290 | /** | ||
| 291 | * Register: HW_I2C_STAT | ||
| 292 | * Address: 0x50 | ||
| 293 | * SCT: no | ||
| 294 | */ | ||
| 295 | #define HW_I2C_STAT (*(volatile unsigned long *)(REGS_I2C_BASE + 0x50)) | ||
| 296 | #define BP_I2C_STAT_MASTER_PRESENT 31 | ||
| 297 | #define BM_I2C_STAT_MASTER_PRESENT 0x80000000 | ||
| 298 | #define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 | ||
| 299 | #define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 | ||
| 300 | #define BF_I2C_STAT_MASTER_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 301 | #define BF_I2C_STAT_MASTER_PRESENT_V(v) ((BV_I2C_STAT_MASTER_PRESENT__##v << 31) & 0x80000000) | ||
| 302 | #define BP_I2C_STAT_SLAVE_PRESENT 30 | ||
| 303 | #define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 | ||
| 304 | #define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 | ||
| 305 | #define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 | ||
| 306 | #define BF_I2C_STAT_SLAVE_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 307 | #define BF_I2C_STAT_SLAVE_PRESENT_V(v) ((BV_I2C_STAT_SLAVE_PRESENT__##v << 30) & 0x40000000) | ||
| 308 | #define BP_I2C_STAT_ANY_ENABLED_IRQ 29 | ||
| 309 | #define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 | ||
| 310 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 | ||
| 311 | #define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 | ||
| 312 | #define BF_I2C_STAT_ANY_ENABLED_IRQ(v) (((v) << 29) & 0x20000000) | ||
| 313 | #define BF_I2C_STAT_ANY_ENABLED_IRQ_V(v) ((BV_I2C_STAT_ANY_ENABLED_IRQ__##v << 29) & 0x20000000) | ||
| 314 | #define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 | ||
| 315 | #define BM_I2C_STAT_RCVD_SLAVE_ADDR 0xff0000 | ||
| 316 | #define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) (((v) << 16) & 0xff0000) | ||
| 317 | #define BP_I2C_STAT_SLAVE_ADDR_EQ_ZERO 15 | ||
| 318 | #define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x8000 | ||
| 319 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 | ||
| 320 | #define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 | ||
| 321 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO(v) (((v) << 15) & 0x8000) | ||
| 322 | #define BF_I2C_STAT_SLAVE_ADDR_EQ_ZERO_V(v) ((BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__##v << 15) & 0x8000) | ||
| 323 | #define BP_I2C_STAT_SLAVE_FOUND 14 | ||
| 324 | #define BM_I2C_STAT_SLAVE_FOUND 0x4000 | ||
| 325 | #define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 | ||
| 326 | #define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 | ||
| 327 | #define BF_I2C_STAT_SLAVE_FOUND(v) (((v) << 14) & 0x4000) | ||
| 328 | #define BF_I2C_STAT_SLAVE_FOUND_V(v) ((BV_I2C_STAT_SLAVE_FOUND__##v << 14) & 0x4000) | ||
| 329 | #define BP_I2C_STAT_SLAVE_SEARCHING 13 | ||
| 330 | #define BM_I2C_STAT_SLAVE_SEARCHING 0x2000 | ||
| 331 | #define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 | ||
| 332 | #define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 | ||
| 333 | #define BF_I2C_STAT_SLAVE_SEARCHING(v) (((v) << 13) & 0x2000) | ||
| 334 | #define BF_I2C_STAT_SLAVE_SEARCHING_V(v) ((BV_I2C_STAT_SLAVE_SEARCHING__##v << 13) & 0x2000) | ||
| 335 | #define BP_I2C_STAT_DATA_ENGINE_DMA_WAIT 12 | ||
| 336 | #define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x1000 | ||
| 337 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 | ||
| 338 | #define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 | ||
| 339 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT(v) (((v) << 12) & 0x1000) | ||
| 340 | #define BF_I2C_STAT_DATA_ENGINE_DMA_WAIT_V(v) ((BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__##v << 12) & 0x1000) | ||
| 341 | #define BP_I2C_STAT_BUS_BUSY 11 | ||
| 342 | #define BM_I2C_STAT_BUS_BUSY 0x800 | ||
| 343 | #define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 | ||
| 344 | #define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 | ||
| 345 | #define BF_I2C_STAT_BUS_BUSY(v) (((v) << 11) & 0x800) | ||
| 346 | #define BF_I2C_STAT_BUS_BUSY_V(v) ((BV_I2C_STAT_BUS_BUSY__##v << 11) & 0x800) | ||
| 347 | #define BP_I2C_STAT_CLK_GEN_BUSY 10 | ||
| 348 | #define BM_I2C_STAT_CLK_GEN_BUSY 0x400 | ||
| 349 | #define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 | ||
| 350 | #define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 | ||
| 351 | #define BF_I2C_STAT_CLK_GEN_BUSY(v) (((v) << 10) & 0x400) | ||
| 352 | #define BF_I2C_STAT_CLK_GEN_BUSY_V(v) ((BV_I2C_STAT_CLK_GEN_BUSY__##v << 10) & 0x400) | ||
| 353 | #define BP_I2C_STAT_DATA_ENGINE_BUSY 9 | ||
| 354 | #define BM_I2C_STAT_DATA_ENGINE_BUSY 0x200 | ||
| 355 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 | ||
| 356 | #define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 | ||
| 357 | #define BF_I2C_STAT_DATA_ENGINE_BUSY(v) (((v) << 9) & 0x200) | ||
| 358 | #define BF_I2C_STAT_DATA_ENGINE_BUSY_V(v) ((BV_I2C_STAT_DATA_ENGINE_BUSY__##v << 9) & 0x200) | ||
| 359 | #define BP_I2C_STAT_SLAVE_BUSY 8 | ||
| 360 | #define BM_I2C_STAT_SLAVE_BUSY 0x100 | ||
| 361 | #define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 | ||
| 362 | #define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 | ||
| 363 | #define BF_I2C_STAT_SLAVE_BUSY(v) (((v) << 8) & 0x100) | ||
| 364 | #define BF_I2C_STAT_SLAVE_BUSY_V(v) ((BV_I2C_STAT_SLAVE_BUSY__##v << 8) & 0x100) | ||
| 365 | #define BP_I2C_STAT_BUS_FREE_IRQ_SUMMARY 7 | ||
| 366 | #define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x80 | ||
| 367 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 368 | #define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 | ||
| 369 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY(v) (((v) << 7) & 0x80) | ||
| 370 | #define BF_I2C_STAT_BUS_FREE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__##v << 7) & 0x80) | ||
| 371 | #define BP_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 6 | ||
| 372 | #define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x40 | ||
| 373 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 374 | #define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 | ||
| 375 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY(v) (((v) << 6) & 0x40) | ||
| 376 | #define BF_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__##v << 6) & 0x40) | ||
| 377 | #define BP_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 5 | ||
| 378 | #define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x20 | ||
| 379 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 380 | #define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 | ||
| 381 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY(v) (((v) << 5) & 0x20) | ||
| 382 | #define BF_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__##v << 5) & 0x20) | ||
| 383 | #define BP_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 4 | ||
| 384 | #define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x10 | ||
| 385 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 386 | #define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
| 387 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY(v) (((v) << 4) & 0x10) | ||
| 388 | #define BF_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__##v << 4) & 0x10) | ||
| 389 | #define BP_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 3 | ||
| 390 | #define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x8 | ||
| 391 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 392 | #define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 | ||
| 393 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY(v) (((v) << 3) & 0x8) | ||
| 394 | #define BF_I2C_STAT_EARLY_TERM_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__##v << 3) & 0x8) | ||
| 395 | #define BP_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 2 | ||
| 396 | #define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x4 | ||
| 397 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 398 | #define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 | ||
| 399 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4) | ||
| 400 | #define BF_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__##v << 2) & 0x4) | ||
| 401 | #define BP_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 1 | ||
| 402 | #define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x2 | ||
| 403 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 404 | #define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 | ||
| 405 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY(v) (((v) << 1) & 0x2) | ||
| 406 | #define BF_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__##v << 1) & 0x2) | ||
| 407 | #define BP_I2C_STAT_SLAVE_IRQ_SUMMARY 0 | ||
| 408 | #define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x1 | ||
| 409 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 | ||
| 410 | #define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 | ||
| 411 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY(v) (((v) << 0) & 0x1) | ||
| 412 | #define BF_I2C_STAT_SLAVE_IRQ_SUMMARY_V(v) ((BV_I2C_STAT_SLAVE_IRQ_SUMMARY__##v << 0) & 0x1) | ||
| 413 | |||
| 414 | /** | ||
| 415 | * Register: HW_I2C_DATA | ||
| 416 | * Address: 0x60 | ||
| 417 | * SCT: no | ||
| 418 | */ | ||
| 419 | #define HW_I2C_DATA (*(volatile unsigned long *)(REGS_I2C_BASE + 0x60)) | ||
| 420 | #define BP_I2C_DATA_DATA 0 | ||
| 421 | #define BM_I2C_DATA_DATA 0xffffffff | ||
| 422 | #define BF_I2C_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 423 | |||
| 424 | /** | ||
| 425 | * Register: HW_I2C_DEBUG0 | ||
| 426 | * Address: 0x70 | ||
| 427 | * SCT: yes | ||
| 428 | */ | ||
| 429 | #define HW_I2C_DEBUG0 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x0)) | ||
| 430 | #define HW_I2C_DEBUG0_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x4)) | ||
| 431 | #define HW_I2C_DEBUG0_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0x8)) | ||
| 432 | #define HW_I2C_DEBUG0_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x70 + 0xc)) | ||
| 433 | #define BP_I2C_DEBUG0_DMAREQ 31 | ||
| 434 | #define BM_I2C_DEBUG0_DMAREQ 0x80000000 | ||
| 435 | #define BF_I2C_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000) | ||
| 436 | #define BP_I2C_DEBUG0_DMAENDCMD 30 | ||
| 437 | #define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 | ||
| 438 | #define BF_I2C_DEBUG0_DMAENDCMD(v) (((v) << 30) & 0x40000000) | ||
| 439 | #define BP_I2C_DEBUG0_DMAKICK 29 | ||
| 440 | #define BM_I2C_DEBUG0_DMAKICK 0x20000000 | ||
| 441 | #define BF_I2C_DEBUG0_DMAKICK(v) (((v) << 29) & 0x20000000) | ||
| 442 | #define BP_I2C_DEBUG0_TBD 26 | ||
| 443 | #define BM_I2C_DEBUG0_TBD 0x1c000000 | ||
| 444 | #define BF_I2C_DEBUG0_TBD(v) (((v) << 26) & 0x1c000000) | ||
| 445 | #define BP_I2C_DEBUG0_DMA_STATE 16 | ||
| 446 | #define BM_I2C_DEBUG0_DMA_STATE 0x3ff0000 | ||
| 447 | #define BF_I2C_DEBUG0_DMA_STATE(v) (((v) << 16) & 0x3ff0000) | ||
| 448 | #define BP_I2C_DEBUG0_START_TOGGLE 15 | ||
| 449 | #define BM_I2C_DEBUG0_START_TOGGLE 0x8000 | ||
| 450 | #define BF_I2C_DEBUG0_START_TOGGLE(v) (((v) << 15) & 0x8000) | ||
| 451 | #define BP_I2C_DEBUG0_STOP_TOGGLE 14 | ||
| 452 | #define BM_I2C_DEBUG0_STOP_TOGGLE 0x4000 | ||
| 453 | #define BF_I2C_DEBUG0_STOP_TOGGLE(v) (((v) << 14) & 0x4000) | ||
| 454 | #define BP_I2C_DEBUG0_GRAB_TOGGLE 13 | ||
| 455 | #define BM_I2C_DEBUG0_GRAB_TOGGLE 0x2000 | ||
| 456 | #define BF_I2C_DEBUG0_GRAB_TOGGLE(v) (((v) << 13) & 0x2000) | ||
| 457 | #define BP_I2C_DEBUG0_CHANGE_TOGGLE 12 | ||
| 458 | #define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x1000 | ||
| 459 | #define BF_I2C_DEBUG0_CHANGE_TOGGLE(v) (((v) << 12) & 0x1000) | ||
| 460 | #define BP_I2C_DEBUG0_TESTMODE 11 | ||
| 461 | #define BM_I2C_DEBUG0_TESTMODE 0x800 | ||
| 462 | #define BF_I2C_DEBUG0_TESTMODE(v) (((v) << 11) & 0x800) | ||
| 463 | #define BP_I2C_DEBUG0_SLAVE_HOLD_CLK 10 | ||
| 464 | #define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x400 | ||
| 465 | #define BF_I2C_DEBUG0_SLAVE_HOLD_CLK(v) (((v) << 10) & 0x400) | ||
| 466 | #define BP_I2C_DEBUG0_SLAVE_STATE 0 | ||
| 467 | #define BM_I2C_DEBUG0_SLAVE_STATE 0x3ff | ||
| 468 | #define BF_I2C_DEBUG0_SLAVE_STATE(v) (((v) << 0) & 0x3ff) | ||
| 469 | |||
| 470 | /** | ||
| 471 | * Register: HW_I2C_DEBUG1 | ||
| 472 | * Address: 0x80 | ||
| 473 | * SCT: yes | ||
| 474 | */ | ||
| 475 | #define HW_I2C_DEBUG1 (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x0)) | ||
| 476 | #define HW_I2C_DEBUG1_SET (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x4)) | ||
| 477 | #define HW_I2C_DEBUG1_CLR (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0x8)) | ||
| 478 | #define HW_I2C_DEBUG1_TOG (*(volatile unsigned long *)(REGS_I2C_BASE + 0x80 + 0xc)) | ||
| 479 | #define BP_I2C_DEBUG1_I2C_CLK_IN 31 | ||
| 480 | #define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 | ||
| 481 | #define BF_I2C_DEBUG1_I2C_CLK_IN(v) (((v) << 31) & 0x80000000) | ||
| 482 | #define BP_I2C_DEBUG1_I2C_DATA_IN 30 | ||
| 483 | #define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 | ||
| 484 | #define BF_I2C_DEBUG1_I2C_DATA_IN(v) (((v) << 30) & 0x40000000) | ||
| 485 | #define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 | ||
| 486 | #define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0xf000000 | ||
| 487 | #define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) (((v) << 24) & 0xf000000) | ||
| 488 | #define BP_I2C_DEBUG1_CLK_GEN_STATE 16 | ||
| 489 | #define BM_I2C_DEBUG1_CLK_GEN_STATE 0x7f0000 | ||
| 490 | #define BF_I2C_DEBUG1_CLK_GEN_STATE(v) (((v) << 16) & 0x7f0000) | ||
| 491 | #define BP_I2C_DEBUG1_LST_MODE 9 | ||
| 492 | #define BM_I2C_DEBUG1_LST_MODE 0x600 | ||
| 493 | #define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 | ||
| 494 | #define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 | ||
| 495 | #define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 | ||
| 496 | #define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 | ||
| 497 | #define BF_I2C_DEBUG1_LST_MODE(v) (((v) << 9) & 0x600) | ||
| 498 | #define BF_I2C_DEBUG1_LST_MODE_V(v) ((BV_I2C_DEBUG1_LST_MODE__##v << 9) & 0x600) | ||
| 499 | #define BP_I2C_DEBUG1_LOCAL_SLAVE_TEST 8 | ||
| 500 | #define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x100 | ||
| 501 | #define BF_I2C_DEBUG1_LOCAL_SLAVE_TEST(v) (((v) << 8) & 0x100) | ||
| 502 | #define BP_I2C_DEBUG1_FORCE_CLK_ON 5 | ||
| 503 | #define BM_I2C_DEBUG1_FORCE_CLK_ON 0x20 | ||
| 504 | #define BF_I2C_DEBUG1_FORCE_CLK_ON(v) (((v) << 5) & 0x20) | ||
| 505 | #define BP_I2C_DEBUG1_FORCE_CLK_IDLE 4 | ||
| 506 | #define BM_I2C_DEBUG1_FORCE_CLK_IDLE 0x10 | ||
| 507 | #define BF_I2C_DEBUG1_FORCE_CLK_IDLE(v) (((v) << 4) & 0x10) | ||
| 508 | #define BP_I2C_DEBUG1_FORCE_ARB_LOSS 3 | ||
| 509 | #define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x8 | ||
| 510 | #define BF_I2C_DEBUG1_FORCE_ARB_LOSS(v) (((v) << 3) & 0x8) | ||
| 511 | #define BP_I2C_DEBUG1_FORCE_RCV_ACK 2 | ||
| 512 | #define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x4 | ||
| 513 | #define BF_I2C_DEBUG1_FORCE_RCV_ACK(v) (((v) << 2) & 0x4) | ||
| 514 | #define BP_I2C_DEBUG1_FORCE_I2C_DATA_OE 1 | ||
| 515 | #define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x2 | ||
| 516 | #define BF_I2C_DEBUG1_FORCE_I2C_DATA_OE(v) (((v) << 1) & 0x2) | ||
| 517 | #define BP_I2C_DEBUG1_FORCE_I2C_CLK_OE 0 | ||
| 518 | #define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x1 | ||
| 519 | #define BF_I2C_DEBUG1_FORCE_I2C_CLK_OE(v) (((v) << 0) & 0x1) | ||
| 520 | |||
| 521 | /** | ||
| 522 | * Register: HW_I2C_VERSION | ||
| 523 | * Address: 0x90 | ||
| 524 | * SCT: no | ||
| 525 | */ | ||
| 526 | #define HW_I2C_VERSION (*(volatile unsigned long *)(REGS_I2C_BASE + 0x90)) | ||
| 527 | #define BP_I2C_VERSION_MAJOR 24 | ||
| 528 | #define BM_I2C_VERSION_MAJOR 0xff000000 | ||
| 529 | #define BF_I2C_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 530 | #define BP_I2C_VERSION_MINOR 16 | ||
| 531 | #define BM_I2C_VERSION_MINOR 0xff0000 | ||
| 532 | #define BF_I2C_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 533 | #define BP_I2C_VERSION_STEP 0 | ||
| 534 | #define BM_I2C_VERSION_STEP 0xffff | ||
| 535 | #define BF_I2C_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 536 | |||
| 537 | #endif /* __HEADERGEN__STMP3700__I2C__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h new file mode 100644 index 0000000000..a4b7d51519 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-icoll.h | |||
| @@ -0,0 +1,410 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__ICOLL__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__ICOLL__H__ | ||
| 25 | |||
| 26 | #define REGS_ICOLL_BASE (0x80000000) | ||
| 27 | |||
| 28 | #define REGS_ICOLL_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_ICOLL_VECTOR | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_ICOLL_VECTOR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_ICOLL_VECTOR_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_ICOLL_VECTOR_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_ICOLL_VECTOR_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_ICOLL_VECTOR_IRQVECTOR 2 | ||
| 40 | #define BM_ICOLL_VECTOR_IRQVECTOR 0xfffffffc | ||
| 41 | #define BF_ICOLL_VECTOR_IRQVECTOR(v) (((v) << 2) & 0xfffffffc) | ||
| 42 | |||
| 43 | /** | ||
| 44 | * Register: HW_ICOLL_LEVELACK | ||
| 45 | * Address: 0x10 | ||
| 46 | * SCT: no | ||
| 47 | */ | ||
| 48 | #define HW_ICOLL_LEVELACK (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x10)) | ||
| 49 | #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 | ||
| 50 | #define BM_ICOLL_LEVELACK_IRQLEVELACK 0xf | ||
| 51 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | ||
| 52 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 | ||
| 53 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 | ||
| 54 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 | ||
| 55 | #define BF_ICOLL_LEVELACK_IRQLEVELACK(v) (((v) << 0) & 0xf) | ||
| 56 | #define BF_ICOLL_LEVELACK_IRQLEVELACK_V(v) ((BV_ICOLL_LEVELACK_IRQLEVELACK__##v << 0) & 0xf) | ||
| 57 | |||
| 58 | /** | ||
| 59 | * Register: HW_ICOLL_CTRL | ||
| 60 | * Address: 0x20 | ||
| 61 | * SCT: yes | ||
| 62 | */ | ||
| 63 | #define HW_ICOLL_CTRL (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x0)) | ||
| 64 | #define HW_ICOLL_CTRL_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x4)) | ||
| 65 | #define HW_ICOLL_CTRL_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0x8)) | ||
| 66 | #define HW_ICOLL_CTRL_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x20 + 0xc)) | ||
| 67 | #define BP_ICOLL_CTRL_SFTRST 31 | ||
| 68 | #define BM_ICOLL_CTRL_SFTRST 0x80000000 | ||
| 69 | #define BV_ICOLL_CTRL_SFTRST__RUN 0x0 | ||
| 70 | #define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 | ||
| 71 | #define BF_ICOLL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 72 | #define BF_ICOLL_CTRL_SFTRST_V(v) ((BV_ICOLL_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 73 | #define BP_ICOLL_CTRL_CLKGATE 30 | ||
| 74 | #define BM_ICOLL_CTRL_CLKGATE 0x40000000 | ||
| 75 | #define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 | ||
| 76 | #define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 | ||
| 77 | #define BF_ICOLL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 78 | #define BF_ICOLL_CTRL_CLKGATE_V(v) ((BV_ICOLL_CTRL_CLKGATE__##v << 30) & 0x40000000) | ||
| 79 | #define BP_ICOLL_CTRL_VECTOR_PITCH 21 | ||
| 80 | #define BM_ICOLL_CTRL_VECTOR_PITCH 0xe00000 | ||
| 81 | #define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 | ||
| 82 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 | ||
| 83 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 | ||
| 84 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 | ||
| 85 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 | ||
| 86 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 | ||
| 87 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 | ||
| 88 | #define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 | ||
| 89 | #define BF_ICOLL_CTRL_VECTOR_PITCH(v) (((v) << 21) & 0xe00000) | ||
| 90 | #define BF_ICOLL_CTRL_VECTOR_PITCH_V(v) ((BV_ICOLL_CTRL_VECTOR_PITCH__##v << 21) & 0xe00000) | ||
| 91 | #define BP_ICOLL_CTRL_BYPASS_FSM 20 | ||
| 92 | #define BM_ICOLL_CTRL_BYPASS_FSM 0x100000 | ||
| 93 | #define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 | ||
| 94 | #define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 | ||
| 95 | #define BF_ICOLL_CTRL_BYPASS_FSM(v) (((v) << 20) & 0x100000) | ||
| 96 | #define BF_ICOLL_CTRL_BYPASS_FSM_V(v) ((BV_ICOLL_CTRL_BYPASS_FSM__##v << 20) & 0x100000) | ||
| 97 | #define BP_ICOLL_CTRL_NO_NESTING 19 | ||
| 98 | #define BM_ICOLL_CTRL_NO_NESTING 0x80000 | ||
| 99 | #define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 | ||
| 100 | #define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 | ||
| 101 | #define BF_ICOLL_CTRL_NO_NESTING(v) (((v) << 19) & 0x80000) | ||
| 102 | #define BF_ICOLL_CTRL_NO_NESTING_V(v) ((BV_ICOLL_CTRL_NO_NESTING__##v << 19) & 0x80000) | ||
| 103 | #define BP_ICOLL_CTRL_ARM_RSE_MODE 18 | ||
| 104 | #define BM_ICOLL_CTRL_ARM_RSE_MODE 0x40000 | ||
| 105 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__MUST_WRITE 0x0 | ||
| 106 | #define BV_ICOLL_CTRL_ARM_RSE_MODE__READ_SIDE_EFFECT 0x1 | ||
| 107 | #define BF_ICOLL_CTRL_ARM_RSE_MODE(v) (((v) << 18) & 0x40000) | ||
| 108 | #define BF_ICOLL_CTRL_ARM_RSE_MODE_V(v) ((BV_ICOLL_CTRL_ARM_RSE_MODE__##v << 18) & 0x40000) | ||
| 109 | #define BP_ICOLL_CTRL_FIQ_FINAL_ENABLE 17 | ||
| 110 | #define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x20000 | ||
| 111 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 | ||
| 112 | #define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 | ||
| 113 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE(v) (((v) << 17) & 0x20000) | ||
| 114 | #define BF_ICOLL_CTRL_FIQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__##v << 17) & 0x20000) | ||
| 115 | #define BP_ICOLL_CTRL_IRQ_FINAL_ENABLE 16 | ||
| 116 | #define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x10000 | ||
| 117 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 | ||
| 118 | #define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 | ||
| 119 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 120 | #define BF_ICOLL_CTRL_IRQ_FINAL_ENABLE_V(v) ((BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__##v << 16) & 0x10000) | ||
| 121 | #define BP_ICOLL_CTRL_ENABLE2FIQ35 7 | ||
| 122 | #define BM_ICOLL_CTRL_ENABLE2FIQ35 0x80 | ||
| 123 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__DISABLE 0x0 | ||
| 124 | #define BV_ICOLL_CTRL_ENABLE2FIQ35__ENABLE 0x1 | ||
| 125 | #define BF_ICOLL_CTRL_ENABLE2FIQ35(v) (((v) << 7) & 0x80) | ||
| 126 | #define BF_ICOLL_CTRL_ENABLE2FIQ35_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ35__##v << 7) & 0x80) | ||
| 127 | #define BP_ICOLL_CTRL_ENABLE2FIQ34 6 | ||
| 128 | #define BM_ICOLL_CTRL_ENABLE2FIQ34 0x40 | ||
| 129 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__DISABLE 0x0 | ||
| 130 | #define BV_ICOLL_CTRL_ENABLE2FIQ34__ENABLE 0x1 | ||
| 131 | #define BF_ICOLL_CTRL_ENABLE2FIQ34(v) (((v) << 6) & 0x40) | ||
| 132 | #define BF_ICOLL_CTRL_ENABLE2FIQ34_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ34__##v << 6) & 0x40) | ||
| 133 | #define BP_ICOLL_CTRL_ENABLE2FIQ33 5 | ||
| 134 | #define BM_ICOLL_CTRL_ENABLE2FIQ33 0x20 | ||
| 135 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__DISABLE 0x0 | ||
| 136 | #define BV_ICOLL_CTRL_ENABLE2FIQ33__ENABLE 0x1 | ||
| 137 | #define BF_ICOLL_CTRL_ENABLE2FIQ33(v) (((v) << 5) & 0x20) | ||
| 138 | #define BF_ICOLL_CTRL_ENABLE2FIQ33_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ33__##v << 5) & 0x20) | ||
| 139 | #define BP_ICOLL_CTRL_ENABLE2FIQ32 4 | ||
| 140 | #define BM_ICOLL_CTRL_ENABLE2FIQ32 0x10 | ||
| 141 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__DISABLE 0x0 | ||
| 142 | #define BV_ICOLL_CTRL_ENABLE2FIQ32__ENABLE 0x1 | ||
| 143 | #define BF_ICOLL_CTRL_ENABLE2FIQ32(v) (((v) << 4) & 0x10) | ||
| 144 | #define BF_ICOLL_CTRL_ENABLE2FIQ32_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ32__##v << 4) & 0x10) | ||
| 145 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T3 3 | ||
| 146 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T3 0x8 | ||
| 147 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T3__DISABLE 0x0 | ||
| 148 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T3__ENABLE 0x1 | ||
| 149 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T3(v) (((v) << 3) & 0x8) | ||
| 150 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T3_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T3__##v << 3) & 0x8) | ||
| 151 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T2 2 | ||
| 152 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T2 0x4 | ||
| 153 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T2__DISABLE 0x0 | ||
| 154 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T2__ENABLE 0x1 | ||
| 155 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T2(v) (((v) << 2) & 0x4) | ||
| 156 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T2_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T2__##v << 2) & 0x4) | ||
| 157 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T1 1 | ||
| 158 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T1 0x2 | ||
| 159 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T1__DISABLE 0x0 | ||
| 160 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T1__ENABLE 0x1 | ||
| 161 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T1(v) (((v) << 1) & 0x2) | ||
| 162 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T1_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T1__##v << 1) & 0x2) | ||
| 163 | #define BP_ICOLL_CTRL_ENABLE2FIQ_T0 0 | ||
| 164 | #define BM_ICOLL_CTRL_ENABLE2FIQ_T0 0x1 | ||
| 165 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T0__DISABLE 0x0 | ||
| 166 | #define BV_ICOLL_CTRL_ENABLE2FIQ_T0__ENABLE 0x1 | ||
| 167 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T0(v) (((v) << 0) & 0x1) | ||
| 168 | #define BF_ICOLL_CTRL_ENABLE2FIQ_T0_V(v) ((BV_ICOLL_CTRL_ENABLE2FIQ_T0__##v << 0) & 0x1) | ||
| 169 | |||
| 170 | /** | ||
| 171 | * Register: HW_ICOLL_STAT | ||
| 172 | * Address: 0x30 | ||
| 173 | * SCT: no | ||
| 174 | */ | ||
| 175 | #define HW_ICOLL_STAT (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x30)) | ||
| 176 | #define BP_ICOLL_STAT_VECTOR_NUMBER 0 | ||
| 177 | #define BM_ICOLL_STAT_VECTOR_NUMBER 0x3f | ||
| 178 | #define BF_ICOLL_STAT_VECTOR_NUMBER(v) (((v) << 0) & 0x3f) | ||
| 179 | |||
| 180 | /** | ||
| 181 | * Register: HW_ICOLL_RAWn | ||
| 182 | * Address: 0x40+n*0x10 | ||
| 183 | * SCT: no | ||
| 184 | */ | ||
| 185 | #define HW_ICOLL_RAWn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x40+(n)*0x10)) | ||
| 186 | #define BP_ICOLL_RAWn_RAW_IRQS 0 | ||
| 187 | #define BM_ICOLL_RAWn_RAW_IRQS 0xffffffff | ||
| 188 | #define BF_ICOLL_RAWn_RAW_IRQS(v) (((v) << 0) & 0xffffffff) | ||
| 189 | |||
| 190 | /** | ||
| 191 | * Register: HW_ICOLL_PRIORITYn | ||
| 192 | * Address: 0x60+n*0x10 | ||
| 193 | * SCT: yes | ||
| 194 | */ | ||
| 195 | #define HW_ICOLL_PRIORITYn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x0)) | ||
| 196 | #define HW_ICOLL_PRIORITYn_SET(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x4)) | ||
| 197 | #define HW_ICOLL_PRIORITYn_CLR(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0x8)) | ||
| 198 | #define HW_ICOLL_PRIORITYn_TOG(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x60+(n)*0x10 + 0xc)) | ||
| 199 | #define BP_ICOLL_PRIORITYn_SOFTIRQ3 27 | ||
| 200 | #define BM_ICOLL_PRIORITYn_SOFTIRQ3 0x8000000 | ||
| 201 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__NO_INTERRUPT 0x0 | ||
| 202 | #define BV_ICOLL_PRIORITYn_SOFTIRQ3__FORCE_INTERRUPT 0x1 | ||
| 203 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3(v) (((v) << 27) & 0x8000000) | ||
| 204 | #define BF_ICOLL_PRIORITYn_SOFTIRQ3_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ3__##v << 27) & 0x8000000) | ||
| 205 | #define BP_ICOLL_PRIORITYn_ENABLE3 26 | ||
| 206 | #define BM_ICOLL_PRIORITYn_ENABLE3 0x4000000 | ||
| 207 | #define BV_ICOLL_PRIORITYn_ENABLE3__DISABLE 0x0 | ||
| 208 | #define BV_ICOLL_PRIORITYn_ENABLE3__ENABLE 0x1 | ||
| 209 | #define BF_ICOLL_PRIORITYn_ENABLE3(v) (((v) << 26) & 0x4000000) | ||
| 210 | #define BF_ICOLL_PRIORITYn_ENABLE3_V(v) ((BV_ICOLL_PRIORITYn_ENABLE3__##v << 26) & 0x4000000) | ||
| 211 | #define BP_ICOLL_PRIORITYn_PRIORITY3 24 | ||
| 212 | #define BM_ICOLL_PRIORITYn_PRIORITY3 0x3000000 | ||
| 213 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL0 0x0 | ||
| 214 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL1 0x1 | ||
| 215 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL2 0x2 | ||
| 216 | #define BV_ICOLL_PRIORITYn_PRIORITY3__LEVEL3 0x3 | ||
| 217 | #define BF_ICOLL_PRIORITYn_PRIORITY3(v) (((v) << 24) & 0x3000000) | ||
| 218 | #define BF_ICOLL_PRIORITYn_PRIORITY3_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY3__##v << 24) & 0x3000000) | ||
| 219 | #define BP_ICOLL_PRIORITYn_SOFTIRQ2 19 | ||
| 220 | #define BM_ICOLL_PRIORITYn_SOFTIRQ2 0x80000 | ||
| 221 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__NO_INTERRUPT 0x0 | ||
| 222 | #define BV_ICOLL_PRIORITYn_SOFTIRQ2__FORCE_INTERRUPT 0x1 | ||
| 223 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2(v) (((v) << 19) & 0x80000) | ||
| 224 | #define BF_ICOLL_PRIORITYn_SOFTIRQ2_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ2__##v << 19) & 0x80000) | ||
| 225 | #define BP_ICOLL_PRIORITYn_ENABLE2 18 | ||
| 226 | #define BM_ICOLL_PRIORITYn_ENABLE2 0x40000 | ||
| 227 | #define BV_ICOLL_PRIORITYn_ENABLE2__DISABLE 0x0 | ||
| 228 | #define BV_ICOLL_PRIORITYn_ENABLE2__ENABLE 0x1 | ||
| 229 | #define BF_ICOLL_PRIORITYn_ENABLE2(v) (((v) << 18) & 0x40000) | ||
| 230 | #define BF_ICOLL_PRIORITYn_ENABLE2_V(v) ((BV_ICOLL_PRIORITYn_ENABLE2__##v << 18) & 0x40000) | ||
| 231 | #define BP_ICOLL_PRIORITYn_PRIORITY2 16 | ||
| 232 | #define BM_ICOLL_PRIORITYn_PRIORITY2 0x30000 | ||
| 233 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL0 0x0 | ||
| 234 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL1 0x1 | ||
| 235 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL2 0x2 | ||
| 236 | #define BV_ICOLL_PRIORITYn_PRIORITY2__LEVEL3 0x3 | ||
| 237 | #define BF_ICOLL_PRIORITYn_PRIORITY2(v) (((v) << 16) & 0x30000) | ||
| 238 | #define BF_ICOLL_PRIORITYn_PRIORITY2_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY2__##v << 16) & 0x30000) | ||
| 239 | #define BP_ICOLL_PRIORITYn_SOFTIRQ1 11 | ||
| 240 | #define BM_ICOLL_PRIORITYn_SOFTIRQ1 0x800 | ||
| 241 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__NO_INTERRUPT 0x0 | ||
| 242 | #define BV_ICOLL_PRIORITYn_SOFTIRQ1__FORCE_INTERRUPT 0x1 | ||
| 243 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1(v) (((v) << 11) & 0x800) | ||
| 244 | #define BF_ICOLL_PRIORITYn_SOFTIRQ1_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ1__##v << 11) & 0x800) | ||
| 245 | #define BP_ICOLL_PRIORITYn_ENABLE1 10 | ||
| 246 | #define BM_ICOLL_PRIORITYn_ENABLE1 0x400 | ||
| 247 | #define BV_ICOLL_PRIORITYn_ENABLE1__DISABLE 0x0 | ||
| 248 | #define BV_ICOLL_PRIORITYn_ENABLE1__ENABLE 0x1 | ||
| 249 | #define BF_ICOLL_PRIORITYn_ENABLE1(v) (((v) << 10) & 0x400) | ||
| 250 | #define BF_ICOLL_PRIORITYn_ENABLE1_V(v) ((BV_ICOLL_PRIORITYn_ENABLE1__##v << 10) & 0x400) | ||
| 251 | #define BP_ICOLL_PRIORITYn_PRIORITY1 8 | ||
| 252 | #define BM_ICOLL_PRIORITYn_PRIORITY1 0x300 | ||
| 253 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL0 0x0 | ||
| 254 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL1 0x1 | ||
| 255 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL2 0x2 | ||
| 256 | #define BV_ICOLL_PRIORITYn_PRIORITY1__LEVEL3 0x3 | ||
| 257 | #define BF_ICOLL_PRIORITYn_PRIORITY1(v) (((v) << 8) & 0x300) | ||
| 258 | #define BF_ICOLL_PRIORITYn_PRIORITY1_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY1__##v << 8) & 0x300) | ||
| 259 | #define BP_ICOLL_PRIORITYn_SOFTIRQ0 3 | ||
| 260 | #define BM_ICOLL_PRIORITYn_SOFTIRQ0 0x8 | ||
| 261 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__NO_INTERRUPT 0x0 | ||
| 262 | #define BV_ICOLL_PRIORITYn_SOFTIRQ0__FORCE_INTERRUPT 0x1 | ||
| 263 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0(v) (((v) << 3) & 0x8) | ||
| 264 | #define BF_ICOLL_PRIORITYn_SOFTIRQ0_V(v) ((BV_ICOLL_PRIORITYn_SOFTIRQ0__##v << 3) & 0x8) | ||
| 265 | #define BP_ICOLL_PRIORITYn_ENABLE0 2 | ||
| 266 | #define BM_ICOLL_PRIORITYn_ENABLE0 0x4 | ||
| 267 | #define BV_ICOLL_PRIORITYn_ENABLE0__DISABLE 0x0 | ||
| 268 | #define BV_ICOLL_PRIORITYn_ENABLE0__ENABLE 0x1 | ||
| 269 | #define BF_ICOLL_PRIORITYn_ENABLE0(v) (((v) << 2) & 0x4) | ||
| 270 | #define BF_ICOLL_PRIORITYn_ENABLE0_V(v) ((BV_ICOLL_PRIORITYn_ENABLE0__##v << 2) & 0x4) | ||
| 271 | #define BP_ICOLL_PRIORITYn_PRIORITY0 0 | ||
| 272 | #define BM_ICOLL_PRIORITYn_PRIORITY0 0x3 | ||
| 273 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL0 0x0 | ||
| 274 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL1 0x1 | ||
| 275 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL2 0x2 | ||
| 276 | #define BV_ICOLL_PRIORITYn_PRIORITY0__LEVEL3 0x3 | ||
| 277 | #define BF_ICOLL_PRIORITYn_PRIORITY0(v) (((v) << 0) & 0x3) | ||
| 278 | #define BF_ICOLL_PRIORITYn_PRIORITY0_V(v) ((BV_ICOLL_PRIORITYn_PRIORITY0__##v << 0) & 0x3) | ||
| 279 | |||
| 280 | /** | ||
| 281 | * Register: HW_ICOLL_VBASE | ||
| 282 | * Address: 0x160 | ||
| 283 | * SCT: yes | ||
| 284 | */ | ||
| 285 | #define HW_ICOLL_VBASE (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x0)) | ||
| 286 | #define HW_ICOLL_VBASE_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x4)) | ||
| 287 | #define HW_ICOLL_VBASE_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0x8)) | ||
| 288 | #define HW_ICOLL_VBASE_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x160 + 0xc)) | ||
| 289 | #define BP_ICOLL_VBASE_TABLE_ADDRESS 2 | ||
| 290 | #define BM_ICOLL_VBASE_TABLE_ADDRESS 0xfffffffc | ||
| 291 | #define BF_ICOLL_VBASE_TABLE_ADDRESS(v) (((v) << 2) & 0xfffffffc) | ||
| 292 | |||
| 293 | /** | ||
| 294 | * Register: HW_ICOLL_DEBUG | ||
| 295 | * Address: 0x170 | ||
| 296 | * SCT: no | ||
| 297 | */ | ||
| 298 | #define HW_ICOLL_DEBUG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x170)) | ||
| 299 | #define BP_ICOLL_DEBUG_INSERVICE 28 | ||
| 300 | #define BM_ICOLL_DEBUG_INSERVICE 0xf0000000 | ||
| 301 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 | ||
| 302 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 | ||
| 303 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 | ||
| 304 | #define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 | ||
| 305 | #define BF_ICOLL_DEBUG_INSERVICE(v) (((v) << 28) & 0xf0000000) | ||
| 306 | #define BF_ICOLL_DEBUG_INSERVICE_V(v) ((BV_ICOLL_DEBUG_INSERVICE__##v << 28) & 0xf0000000) | ||
| 307 | #define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 | ||
| 308 | #define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0xf000000 | ||
| 309 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 | ||
| 310 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 | ||
| 311 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 | ||
| 312 | #define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 | ||
| 313 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) (((v) << 24) & 0xf000000) | ||
| 314 | #define BF_ICOLL_DEBUG_LEVEL_REQUESTS_V(v) ((BV_ICOLL_DEBUG_LEVEL_REQUESTS__##v << 24) & 0xf000000) | ||
| 315 | #define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 | ||
| 316 | #define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0xf00000 | ||
| 317 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 | ||
| 318 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 | ||
| 319 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 | ||
| 320 | #define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 | ||
| 321 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) (((v) << 20) & 0xf00000) | ||
| 322 | #define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL_V(v) ((BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__##v << 20) & 0xf00000) | ||
| 323 | #define BP_ICOLL_DEBUG_FIQ 17 | ||
| 324 | #define BM_ICOLL_DEBUG_FIQ 0x20000 | ||
| 325 | #define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 | ||
| 326 | #define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 | ||
| 327 | #define BF_ICOLL_DEBUG_FIQ(v) (((v) << 17) & 0x20000) | ||
| 328 | #define BF_ICOLL_DEBUG_FIQ_V(v) ((BV_ICOLL_DEBUG_FIQ__##v << 17) & 0x20000) | ||
| 329 | #define BP_ICOLL_DEBUG_IRQ 16 | ||
| 330 | #define BM_ICOLL_DEBUG_IRQ 0x10000 | ||
| 331 | #define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 | ||
| 332 | #define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 | ||
| 333 | #define BF_ICOLL_DEBUG_IRQ(v) (((v) << 16) & 0x10000) | ||
| 334 | #define BF_ICOLL_DEBUG_IRQ_V(v) ((BV_ICOLL_DEBUG_IRQ__##v << 16) & 0x10000) | ||
| 335 | #define BP_ICOLL_DEBUG_VECTOR_FSM 0 | ||
| 336 | #define BM_ICOLL_DEBUG_VECTOR_FSM 0x3ff | ||
| 337 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x0 | ||
| 338 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x1 | ||
| 339 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x2 | ||
| 340 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x4 | ||
| 341 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x8 | ||
| 342 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x10 | ||
| 343 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x20 | ||
| 344 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x40 | ||
| 345 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x80 | ||
| 346 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 | ||
| 347 | #define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 | ||
| 348 | #define BF_ICOLL_DEBUG_VECTOR_FSM(v) (((v) << 0) & 0x3ff) | ||
| 349 | #define BF_ICOLL_DEBUG_VECTOR_FSM_V(v) ((BV_ICOLL_DEBUG_VECTOR_FSM__##v << 0) & 0x3ff) | ||
| 350 | |||
| 351 | /** | ||
| 352 | * Register: HW_ICOLL_DBGREAD0 | ||
| 353 | * Address: 0x180 | ||
| 354 | * SCT: no | ||
| 355 | */ | ||
| 356 | #define HW_ICOLL_DBGREAD0 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x180)) | ||
| 357 | #define BP_ICOLL_DBGREAD0_VALUE 0 | ||
| 358 | #define BM_ICOLL_DBGREAD0_VALUE 0xffffffff | ||
| 359 | #define BF_ICOLL_DBGREAD0_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 360 | |||
| 361 | /** | ||
| 362 | * Register: HW_ICOLL_DBGREAD1 | ||
| 363 | * Address: 0x190 | ||
| 364 | * SCT: no | ||
| 365 | */ | ||
| 366 | #define HW_ICOLL_DBGREAD1 (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x190)) | ||
| 367 | #define BP_ICOLL_DBGREAD1_VALUE 0 | ||
| 368 | #define BM_ICOLL_DBGREAD1_VALUE 0xffffffff | ||
| 369 | #define BF_ICOLL_DBGREAD1_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 370 | |||
| 371 | /** | ||
| 372 | * Register: HW_ICOLL_DBGFLAG | ||
| 373 | * Address: 0x1a0 | ||
| 374 | * SCT: yes | ||
| 375 | */ | ||
| 376 | #define HW_ICOLL_DBGFLAG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x0)) | ||
| 377 | #define HW_ICOLL_DBGFLAG_SET (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x4)) | ||
| 378 | #define HW_ICOLL_DBGFLAG_CLR (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0x8)) | ||
| 379 | #define HW_ICOLL_DBGFLAG_TOG (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1a0 + 0xc)) | ||
| 380 | #define BP_ICOLL_DBGFLAG_FLAG 0 | ||
| 381 | #define BM_ICOLL_DBGFLAG_FLAG 0xffff | ||
| 382 | #define BF_ICOLL_DBGFLAG_FLAG(v) (((v) << 0) & 0xffff) | ||
| 383 | |||
| 384 | /** | ||
| 385 | * Register: HW_ICOLL_DBGREQUESTn | ||
| 386 | * Address: 0x1b0+n*0x10 | ||
| 387 | * SCT: no | ||
| 388 | */ | ||
| 389 | #define HW_ICOLL_DBGREQUESTn(n) (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1b0+(n)*0x10)) | ||
| 390 | #define BP_ICOLL_DBGREQUESTn_BITS 0 | ||
| 391 | #define BM_ICOLL_DBGREQUESTn_BITS 0xffffffff | ||
| 392 | #define BF_ICOLL_DBGREQUESTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 393 | |||
| 394 | /** | ||
| 395 | * Register: HW_ICOLL_VERSION | ||
| 396 | * Address: 0x1d0 | ||
| 397 | * SCT: no | ||
| 398 | */ | ||
| 399 | #define HW_ICOLL_VERSION (*(volatile unsigned long *)(REGS_ICOLL_BASE + 0x1d0)) | ||
| 400 | #define BP_ICOLL_VERSION_MAJOR 24 | ||
| 401 | #define BM_ICOLL_VERSION_MAJOR 0xff000000 | ||
| 402 | #define BF_ICOLL_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 403 | #define BP_ICOLL_VERSION_MINOR 16 | ||
| 404 | #define BM_ICOLL_VERSION_MINOR 0xff0000 | ||
| 405 | #define BF_ICOLL_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 406 | #define BP_ICOLL_VERSION_STEP 0 | ||
| 407 | #define BM_ICOLL_VERSION_STEP 0xffff | ||
| 408 | #define BF_ICOLL_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 409 | |||
| 410 | #endif /* __HEADERGEN__STMP3700__ICOLL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h new file mode 100644 index 0000000000..d7c14dcecf --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ir.h | |||
| @@ -0,0 +1,493 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__IR__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__IR__H__ | ||
| 25 | |||
| 26 | #define REGS_IR_BASE (0x80078000) | ||
| 27 | |||
| 28 | #define REGS_IR_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_IR_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_IR_CTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_IR_CTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_IR_CTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_IR_CTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_IR_CTRL_SFTRST 31 | ||
| 40 | #define BM_IR_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BV_IR_CTRL_SFTRST__RUN 0x0 | ||
| 42 | #define BV_IR_CTRL_SFTRST__RESET 0x1 | ||
| 43 | #define BF_IR_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 44 | #define BF_IR_CTRL_SFTRST_V(v) ((BV_IR_CTRL_SFTRST__##v << 31) & 0x80000000) | ||
| 45 | #define BP_IR_CTRL_CLKGATE 30 | ||
| 46 | #define BM_IR_CTRL_CLKGATE 0x40000000 | ||
| 47 | #define BF_IR_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 48 | #define BP_IR_CTRL_MTA 24 | ||
| 49 | #define BM_IR_CTRL_MTA 0x7000000 | ||
| 50 | #define BV_IR_CTRL_MTA__MTA_10MS 0x0 | ||
| 51 | #define BV_IR_CTRL_MTA__MTA_5MS 0x1 | ||
| 52 | #define BV_IR_CTRL_MTA__MTA_1MS 0x2 | ||
| 53 | #define BV_IR_CTRL_MTA__MTA_500US 0x3 | ||
| 54 | #define BV_IR_CTRL_MTA__MTA_100US 0x4 | ||
| 55 | #define BV_IR_CTRL_MTA__MTA_50US 0x5 | ||
| 56 | #define BV_IR_CTRL_MTA__MTA_10US 0x6 | ||
| 57 | #define BV_IR_CTRL_MTA__MTA_0 0x7 | ||
| 58 | #define BF_IR_CTRL_MTA(v) (((v) << 24) & 0x7000000) | ||
| 59 | #define BF_IR_CTRL_MTA_V(v) ((BV_IR_CTRL_MTA__##v << 24) & 0x7000000) | ||
| 60 | #define BP_IR_CTRL_MODE 22 | ||
| 61 | #define BM_IR_CTRL_MODE 0xc00000 | ||
| 62 | #define BV_IR_CTRL_MODE__SIR 0x0 | ||
| 63 | #define BV_IR_CTRL_MODE__MIR 0x1 | ||
| 64 | #define BV_IR_CTRL_MODE__FIR 0x2 | ||
| 65 | #define BV_IR_CTRL_MODE__VFIR 0x3 | ||
| 66 | #define BF_IR_CTRL_MODE(v) (((v) << 22) & 0xc00000) | ||
| 67 | #define BF_IR_CTRL_MODE_V(v) ((BV_IR_CTRL_MODE__##v << 22) & 0xc00000) | ||
| 68 | #define BP_IR_CTRL_SPEED 19 | ||
| 69 | #define BM_IR_CTRL_SPEED 0x380000 | ||
| 70 | #define BV_IR_CTRL_SPEED__SPD000 0x0 | ||
| 71 | #define BV_IR_CTRL_SPEED__SPD001 0x1 | ||
| 72 | #define BV_IR_CTRL_SPEED__SPD010 0x2 | ||
| 73 | #define BV_IR_CTRL_SPEED__SPD011 0x3 | ||
| 74 | #define BV_IR_CTRL_SPEED__SPD100 0x4 | ||
| 75 | #define BV_IR_CTRL_SPEED__SPD101 0x5 | ||
| 76 | #define BF_IR_CTRL_SPEED(v) (((v) << 19) & 0x380000) | ||
| 77 | #define BF_IR_CTRL_SPEED_V(v) ((BV_IR_CTRL_SPEED__##v << 19) & 0x380000) | ||
| 78 | #define BP_IR_CTRL_TC_TIME_DIV 8 | ||
| 79 | #define BM_IR_CTRL_TC_TIME_DIV 0x3f00 | ||
| 80 | #define BF_IR_CTRL_TC_TIME_DIV(v) (((v) << 8) & 0x3f00) | ||
| 81 | #define BP_IR_CTRL_TC_TYPE 7 | ||
| 82 | #define BM_IR_CTRL_TC_TYPE 0x80 | ||
| 83 | #define BF_IR_CTRL_TC_TYPE(v) (((v) << 7) & 0x80) | ||
| 84 | #define BP_IR_CTRL_SIR_GAP 4 | ||
| 85 | #define BM_IR_CTRL_SIR_GAP 0x70 | ||
| 86 | #define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0 | ||
| 87 | #define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1 | ||
| 88 | #define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2 | ||
| 89 | #define BV_IR_CTRL_SIR_GAP__GAP_500 0x3 | ||
| 90 | #define BV_IR_CTRL_SIR_GAP__GAP_100 0x4 | ||
| 91 | #define BV_IR_CTRL_SIR_GAP__GAP_50 0x5 | ||
| 92 | #define BV_IR_CTRL_SIR_GAP__GAP_10 0x6 | ||
| 93 | #define BV_IR_CTRL_SIR_GAP__GAP_0 0x7 | ||
| 94 | #define BF_IR_CTRL_SIR_GAP(v) (((v) << 4) & 0x70) | ||
| 95 | #define BF_IR_CTRL_SIR_GAP_V(v) ((BV_IR_CTRL_SIR_GAP__##v << 4) & 0x70) | ||
| 96 | #define BP_IR_CTRL_SIPEN 3 | ||
| 97 | #define BM_IR_CTRL_SIPEN 0x8 | ||
| 98 | #define BF_IR_CTRL_SIPEN(v) (((v) << 3) & 0x8) | ||
| 99 | #define BP_IR_CTRL_TCEN 2 | ||
| 100 | #define BM_IR_CTRL_TCEN 0x4 | ||
| 101 | #define BF_IR_CTRL_TCEN(v) (((v) << 2) & 0x4) | ||
| 102 | #define BP_IR_CTRL_TXEN 1 | ||
| 103 | #define BM_IR_CTRL_TXEN 0x2 | ||
| 104 | #define BF_IR_CTRL_TXEN(v) (((v) << 1) & 0x2) | ||
| 105 | #define BP_IR_CTRL_RXEN 0 | ||
| 106 | #define BM_IR_CTRL_RXEN 0x1 | ||
| 107 | #define BF_IR_CTRL_RXEN(v) (((v) << 0) & 0x1) | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Register: HW_IR_TXDMA | ||
| 111 | * Address: 0x10 | ||
| 112 | * SCT: yes | ||
| 113 | */ | ||
| 114 | #define HW_IR_TXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x0)) | ||
| 115 | #define HW_IR_TXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x4)) | ||
| 116 | #define HW_IR_TXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0x8)) | ||
| 117 | #define HW_IR_TXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x10 + 0xc)) | ||
| 118 | #define BP_IR_TXDMA_RUN 31 | ||
| 119 | #define BM_IR_TXDMA_RUN 0x80000000 | ||
| 120 | #define BF_IR_TXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
| 121 | #define BP_IR_TXDMA_EMPTY 29 | ||
| 122 | #define BM_IR_TXDMA_EMPTY 0x20000000 | ||
| 123 | #define BF_IR_TXDMA_EMPTY(v) (((v) << 29) & 0x20000000) | ||
| 124 | #define BP_IR_TXDMA_INT 28 | ||
| 125 | #define BM_IR_TXDMA_INT 0x10000000 | ||
| 126 | #define BF_IR_TXDMA_INT(v) (((v) << 28) & 0x10000000) | ||
| 127 | #define BP_IR_TXDMA_CHANGE 27 | ||
| 128 | #define BM_IR_TXDMA_CHANGE 0x8000000 | ||
| 129 | #define BF_IR_TXDMA_CHANGE(v) (((v) << 27) & 0x8000000) | ||
| 130 | #define BP_IR_TXDMA_NEW_MTA 24 | ||
| 131 | #define BM_IR_TXDMA_NEW_MTA 0x7000000 | ||
| 132 | #define BF_IR_TXDMA_NEW_MTA(v) (((v) << 24) & 0x7000000) | ||
| 133 | #define BP_IR_TXDMA_NEW_MODE 22 | ||
| 134 | #define BM_IR_TXDMA_NEW_MODE 0xc00000 | ||
| 135 | #define BF_IR_TXDMA_NEW_MODE(v) (((v) << 22) & 0xc00000) | ||
| 136 | #define BP_IR_TXDMA_NEW_SPEED 19 | ||
| 137 | #define BM_IR_TXDMA_NEW_SPEED 0x380000 | ||
| 138 | #define BF_IR_TXDMA_NEW_SPEED(v) (((v) << 19) & 0x380000) | ||
| 139 | #define BP_IR_TXDMA_BOF_TYPE 18 | ||
| 140 | #define BM_IR_TXDMA_BOF_TYPE 0x40000 | ||
| 141 | #define BF_IR_TXDMA_BOF_TYPE(v) (((v) << 18) & 0x40000) | ||
| 142 | #define BP_IR_TXDMA_XBOFS 12 | ||
| 143 | #define BM_IR_TXDMA_XBOFS 0x3f000 | ||
| 144 | #define BF_IR_TXDMA_XBOFS(v) (((v) << 12) & 0x3f000) | ||
| 145 | #define BP_IR_TXDMA_XFER_COUNT 0 | ||
| 146 | #define BM_IR_TXDMA_XFER_COUNT 0xfff | ||
| 147 | #define BF_IR_TXDMA_XFER_COUNT(v) (((v) << 0) & 0xfff) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_IR_RXDMA | ||
| 151 | * Address: 0x20 | ||
| 152 | * SCT: yes | ||
| 153 | */ | ||
| 154 | #define HW_IR_RXDMA (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x0)) | ||
| 155 | #define HW_IR_RXDMA_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x4)) | ||
| 156 | #define HW_IR_RXDMA_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0x8)) | ||
| 157 | #define HW_IR_RXDMA_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x20 + 0xc)) | ||
| 158 | #define BP_IR_RXDMA_RUN 31 | ||
| 159 | #define BM_IR_RXDMA_RUN 0x80000000 | ||
| 160 | #define BF_IR_RXDMA_RUN(v) (((v) << 31) & 0x80000000) | ||
| 161 | #define BP_IR_RXDMA_XFER_COUNT 0 | ||
| 162 | #define BM_IR_RXDMA_XFER_COUNT 0x3ff | ||
| 163 | #define BF_IR_RXDMA_XFER_COUNT(v) (((v) << 0) & 0x3ff) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_IR_DBGCTRL | ||
| 167 | * Address: 0x30 | ||
| 168 | * SCT: yes | ||
| 169 | */ | ||
| 170 | #define HW_IR_DBGCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x0)) | ||
| 171 | #define HW_IR_DBGCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x4)) | ||
| 172 | #define HW_IR_DBGCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0x8)) | ||
| 173 | #define HW_IR_DBGCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x30 + 0xc)) | ||
| 174 | #define BP_IR_DBGCTRL_VFIRSWZ 12 | ||
| 175 | #define BM_IR_DBGCTRL_VFIRSWZ 0x1000 | ||
| 176 | #define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0x0 | ||
| 177 | #define BV_IR_DBGCTRL_VFIRSWZ__SWAP 0x1 | ||
| 178 | #define BF_IR_DBGCTRL_VFIRSWZ(v) (((v) << 12) & 0x1000) | ||
| 179 | #define BF_IR_DBGCTRL_VFIRSWZ_V(v) ((BV_IR_DBGCTRL_VFIRSWZ__##v << 12) & 0x1000) | ||
| 180 | #define BP_IR_DBGCTRL_RXFRMOFF 11 | ||
| 181 | #define BM_IR_DBGCTRL_RXFRMOFF 0x800 | ||
| 182 | #define BF_IR_DBGCTRL_RXFRMOFF(v) (((v) << 11) & 0x800) | ||
| 183 | #define BP_IR_DBGCTRL_RXCRCOFF 10 | ||
| 184 | #define BM_IR_DBGCTRL_RXCRCOFF 0x400 | ||
| 185 | #define BF_IR_DBGCTRL_RXCRCOFF(v) (((v) << 10) & 0x400) | ||
| 186 | #define BP_IR_DBGCTRL_RXINVERT 9 | ||
| 187 | #define BM_IR_DBGCTRL_RXINVERT 0x200 | ||
| 188 | #define BF_IR_DBGCTRL_RXINVERT(v) (((v) << 9) & 0x200) | ||
| 189 | #define BP_IR_DBGCTRL_TXFRMOFF 8 | ||
| 190 | #define BM_IR_DBGCTRL_TXFRMOFF 0x100 | ||
| 191 | #define BF_IR_DBGCTRL_TXFRMOFF(v) (((v) << 8) & 0x100) | ||
| 192 | #define BP_IR_DBGCTRL_TXCRCOFF 7 | ||
| 193 | #define BM_IR_DBGCTRL_TXCRCOFF 0x80 | ||
| 194 | #define BF_IR_DBGCTRL_TXCRCOFF(v) (((v) << 7) & 0x80) | ||
| 195 | #define BP_IR_DBGCTRL_TXINVERT 6 | ||
| 196 | #define BM_IR_DBGCTRL_TXINVERT 0x40 | ||
| 197 | #define BF_IR_DBGCTRL_TXINVERT(v) (((v) << 6) & 0x40) | ||
| 198 | #define BP_IR_DBGCTRL_INTLOOPBACK 5 | ||
| 199 | #define BM_IR_DBGCTRL_INTLOOPBACK 0x20 | ||
| 200 | #define BF_IR_DBGCTRL_INTLOOPBACK(v) (((v) << 5) & 0x20) | ||
| 201 | #define BP_IR_DBGCTRL_DUPLEX 4 | ||
| 202 | #define BM_IR_DBGCTRL_DUPLEX 0x10 | ||
| 203 | #define BF_IR_DBGCTRL_DUPLEX(v) (((v) << 4) & 0x10) | ||
| 204 | #define BP_IR_DBGCTRL_MIO_RX 3 | ||
| 205 | #define BM_IR_DBGCTRL_MIO_RX 0x8 | ||
| 206 | #define BF_IR_DBGCTRL_MIO_RX(v) (((v) << 3) & 0x8) | ||
| 207 | #define BP_IR_DBGCTRL_MIO_TX 2 | ||
| 208 | #define BM_IR_DBGCTRL_MIO_TX 0x4 | ||
| 209 | #define BF_IR_DBGCTRL_MIO_TX(v) (((v) << 2) & 0x4) | ||
| 210 | #define BP_IR_DBGCTRL_MIO_SCLK 1 | ||
| 211 | #define BM_IR_DBGCTRL_MIO_SCLK 0x2 | ||
| 212 | #define BF_IR_DBGCTRL_MIO_SCLK(v) (((v) << 1) & 0x2) | ||
| 213 | #define BP_IR_DBGCTRL_MIO_EN 0 | ||
| 214 | #define BM_IR_DBGCTRL_MIO_EN 0x1 | ||
| 215 | #define BF_IR_DBGCTRL_MIO_EN(v) (((v) << 0) & 0x1) | ||
| 216 | |||
| 217 | /** | ||
| 218 | * Register: HW_IR_INTR | ||
| 219 | * Address: 0x40 | ||
| 220 | * SCT: yes | ||
| 221 | */ | ||
| 222 | #define HW_IR_INTR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x0)) | ||
| 223 | #define HW_IR_INTR_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x4)) | ||
| 224 | #define HW_IR_INTR_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0x8)) | ||
| 225 | #define HW_IR_INTR_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x40 + 0xc)) | ||
| 226 | #define BP_IR_INTR_RXABORT_IRQ_EN 22 | ||
| 227 | #define BM_IR_INTR_RXABORT_IRQ_EN 0x400000 | ||
| 228 | #define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0 | ||
| 229 | #define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1 | ||
| 230 | #define BF_IR_INTR_RXABORT_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
| 231 | #define BF_IR_INTR_RXABORT_IRQ_EN_V(v) ((BV_IR_INTR_RXABORT_IRQ_EN__##v << 22) & 0x400000) | ||
| 232 | #define BP_IR_INTR_SPEED_IRQ_EN 21 | ||
| 233 | #define BM_IR_INTR_SPEED_IRQ_EN 0x200000 | ||
| 234 | #define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0 | ||
| 235 | #define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1 | ||
| 236 | #define BF_IR_INTR_SPEED_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
| 237 | #define BF_IR_INTR_SPEED_IRQ_EN_V(v) ((BV_IR_INTR_SPEED_IRQ_EN__##v << 21) & 0x200000) | ||
| 238 | #define BP_IR_INTR_RXOF_IRQ_EN 20 | ||
| 239 | #define BM_IR_INTR_RXOF_IRQ_EN 0x100000 | ||
| 240 | #define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0 | ||
| 241 | #define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1 | ||
| 242 | #define BF_IR_INTR_RXOF_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
| 243 | #define BF_IR_INTR_RXOF_IRQ_EN_V(v) ((BV_IR_INTR_RXOF_IRQ_EN__##v << 20) & 0x100000) | ||
| 244 | #define BP_IR_INTR_TXUF_IRQ_EN 19 | ||
| 245 | #define BM_IR_INTR_TXUF_IRQ_EN 0x80000 | ||
| 246 | #define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0 | ||
| 247 | #define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1 | ||
| 248 | #define BF_IR_INTR_TXUF_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
| 249 | #define BF_IR_INTR_TXUF_IRQ_EN_V(v) ((BV_IR_INTR_TXUF_IRQ_EN__##v << 19) & 0x80000) | ||
| 250 | #define BP_IR_INTR_TC_IRQ_EN 18 | ||
| 251 | #define BM_IR_INTR_TC_IRQ_EN 0x40000 | ||
| 252 | #define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0 | ||
| 253 | #define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1 | ||
| 254 | #define BF_IR_INTR_TC_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
| 255 | #define BF_IR_INTR_TC_IRQ_EN_V(v) ((BV_IR_INTR_TC_IRQ_EN__##v << 18) & 0x40000) | ||
| 256 | #define BP_IR_INTR_RX_IRQ_EN 17 | ||
| 257 | #define BM_IR_INTR_RX_IRQ_EN 0x20000 | ||
| 258 | #define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0 | ||
| 259 | #define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1 | ||
| 260 | #define BF_IR_INTR_RX_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
| 261 | #define BF_IR_INTR_RX_IRQ_EN_V(v) ((BV_IR_INTR_RX_IRQ_EN__##v << 17) & 0x20000) | ||
| 262 | #define BP_IR_INTR_TX_IRQ_EN 16 | ||
| 263 | #define BM_IR_INTR_TX_IRQ_EN 0x10000 | ||
| 264 | #define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0 | ||
| 265 | #define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1 | ||
| 266 | #define BF_IR_INTR_TX_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
| 267 | #define BF_IR_INTR_TX_IRQ_EN_V(v) ((BV_IR_INTR_TX_IRQ_EN__##v << 16) & 0x10000) | ||
| 268 | #define BP_IR_INTR_RXABORT_IRQ 6 | ||
| 269 | #define BM_IR_INTR_RXABORT_IRQ 0x40 | ||
| 270 | #define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0 | ||
| 271 | #define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1 | ||
| 272 | #define BF_IR_INTR_RXABORT_IRQ(v) (((v) << 6) & 0x40) | ||
| 273 | #define BF_IR_INTR_RXABORT_IRQ_V(v) ((BV_IR_INTR_RXABORT_IRQ__##v << 6) & 0x40) | ||
| 274 | #define BP_IR_INTR_SPEED_IRQ 5 | ||
| 275 | #define BM_IR_INTR_SPEED_IRQ 0x20 | ||
| 276 | #define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0 | ||
| 277 | #define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1 | ||
| 278 | #define BF_IR_INTR_SPEED_IRQ(v) (((v) << 5) & 0x20) | ||
| 279 | #define BF_IR_INTR_SPEED_IRQ_V(v) ((BV_IR_INTR_SPEED_IRQ__##v << 5) & 0x20) | ||
| 280 | #define BP_IR_INTR_RXOF_IRQ 4 | ||
| 281 | #define BM_IR_INTR_RXOF_IRQ 0x10 | ||
| 282 | #define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0 | ||
| 283 | #define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1 | ||
| 284 | #define BF_IR_INTR_RXOF_IRQ(v) (((v) << 4) & 0x10) | ||
| 285 | #define BF_IR_INTR_RXOF_IRQ_V(v) ((BV_IR_INTR_RXOF_IRQ__##v << 4) & 0x10) | ||
| 286 | #define BP_IR_INTR_TXUF_IRQ 3 | ||
| 287 | #define BM_IR_INTR_TXUF_IRQ 0x8 | ||
| 288 | #define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0 | ||
| 289 | #define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1 | ||
| 290 | #define BF_IR_INTR_TXUF_IRQ(v) (((v) << 3) & 0x8) | ||
| 291 | #define BF_IR_INTR_TXUF_IRQ_V(v) ((BV_IR_INTR_TXUF_IRQ__##v << 3) & 0x8) | ||
| 292 | #define BP_IR_INTR_TC_IRQ 2 | ||
| 293 | #define BM_IR_INTR_TC_IRQ 0x4 | ||
| 294 | #define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0 | ||
| 295 | #define BV_IR_INTR_TC_IRQ__REQUEST 0x1 | ||
| 296 | #define BF_IR_INTR_TC_IRQ(v) (((v) << 2) & 0x4) | ||
| 297 | #define BF_IR_INTR_TC_IRQ_V(v) ((BV_IR_INTR_TC_IRQ__##v << 2) & 0x4) | ||
| 298 | #define BP_IR_INTR_RX_IRQ 1 | ||
| 299 | #define BM_IR_INTR_RX_IRQ 0x2 | ||
| 300 | #define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0 | ||
| 301 | #define BV_IR_INTR_RX_IRQ__REQUEST 0x1 | ||
| 302 | #define BF_IR_INTR_RX_IRQ(v) (((v) << 1) & 0x2) | ||
| 303 | #define BF_IR_INTR_RX_IRQ_V(v) ((BV_IR_INTR_RX_IRQ__##v << 1) & 0x2) | ||
| 304 | #define BP_IR_INTR_TX_IRQ 0 | ||
| 305 | #define BM_IR_INTR_TX_IRQ 0x1 | ||
| 306 | #define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0 | ||
| 307 | #define BV_IR_INTR_TX_IRQ__REQUEST 0x1 | ||
| 308 | #define BF_IR_INTR_TX_IRQ(v) (((v) << 0) & 0x1) | ||
| 309 | #define BF_IR_INTR_TX_IRQ_V(v) ((BV_IR_INTR_TX_IRQ__##v << 0) & 0x1) | ||
| 310 | |||
| 311 | /** | ||
| 312 | * Register: HW_IR_DATA | ||
| 313 | * Address: 0x50 | ||
| 314 | * SCT: no | ||
| 315 | */ | ||
| 316 | #define HW_IR_DATA (*(volatile unsigned long *)(REGS_IR_BASE + 0x50)) | ||
| 317 | #define BP_IR_DATA_DATA 0 | ||
| 318 | #define BM_IR_DATA_DATA 0xffffffff | ||
| 319 | #define BF_IR_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 320 | |||
| 321 | /** | ||
| 322 | * Register: HW_IR_STAT | ||
| 323 | * Address: 0x60 | ||
| 324 | * SCT: no | ||
| 325 | */ | ||
| 326 | #define HW_IR_STAT (*(volatile unsigned long *)(REGS_IR_BASE + 0x60)) | ||
| 327 | #define BP_IR_STAT_PRESENT 31 | ||
| 328 | #define BM_IR_STAT_PRESENT 0x80000000 | ||
| 329 | #define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0 | ||
| 330 | #define BV_IR_STAT_PRESENT__AVAILABLE 0x1 | ||
| 331 | #define BF_IR_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 332 | #define BF_IR_STAT_PRESENT_V(v) ((BV_IR_STAT_PRESENT__##v << 31) & 0x80000000) | ||
| 333 | #define BP_IR_STAT_MODE_ALLOWED 29 | ||
| 334 | #define BM_IR_STAT_MODE_ALLOWED 0x60000000 | ||
| 335 | #define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0 | ||
| 336 | #define BV_IR_STAT_MODE_ALLOWED__FIR 0x1 | ||
| 337 | #define BV_IR_STAT_MODE_ALLOWED__MIR 0x2 | ||
| 338 | #define BV_IR_STAT_MODE_ALLOWED__SIR 0x3 | ||
| 339 | #define BF_IR_STAT_MODE_ALLOWED(v) (((v) << 29) & 0x60000000) | ||
| 340 | #define BF_IR_STAT_MODE_ALLOWED_V(v) ((BV_IR_STAT_MODE_ALLOWED__##v << 29) & 0x60000000) | ||
| 341 | #define BP_IR_STAT_ANY_IRQ 28 | ||
| 342 | #define BM_IR_STAT_ANY_IRQ 0x10000000 | ||
| 343 | #define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0 | ||
| 344 | #define BV_IR_STAT_ANY_IRQ__REQUEST 0x1 | ||
| 345 | #define BF_IR_STAT_ANY_IRQ(v) (((v) << 28) & 0x10000000) | ||
| 346 | #define BF_IR_STAT_ANY_IRQ_V(v) ((BV_IR_STAT_ANY_IRQ__##v << 28) & 0x10000000) | ||
| 347 | #define BP_IR_STAT_RXABORT_SUMMARY 22 | ||
| 348 | #define BM_IR_STAT_RXABORT_SUMMARY 0x400000 | ||
| 349 | #define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0 | ||
| 350 | #define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1 | ||
| 351 | #define BF_IR_STAT_RXABORT_SUMMARY(v) (((v) << 22) & 0x400000) | ||
| 352 | #define BF_IR_STAT_RXABORT_SUMMARY_V(v) ((BV_IR_STAT_RXABORT_SUMMARY__##v << 22) & 0x400000) | ||
| 353 | #define BP_IR_STAT_SPEED_SUMMARY 21 | ||
| 354 | #define BM_IR_STAT_SPEED_SUMMARY 0x200000 | ||
| 355 | #define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0 | ||
| 356 | #define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1 | ||
| 357 | #define BF_IR_STAT_SPEED_SUMMARY(v) (((v) << 21) & 0x200000) | ||
| 358 | #define BF_IR_STAT_SPEED_SUMMARY_V(v) ((BV_IR_STAT_SPEED_SUMMARY__##v << 21) & 0x200000) | ||
| 359 | #define BP_IR_STAT_RXOF_SUMMARY 20 | ||
| 360 | #define BM_IR_STAT_RXOF_SUMMARY 0x100000 | ||
| 361 | #define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0 | ||
| 362 | #define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1 | ||
| 363 | #define BF_IR_STAT_RXOF_SUMMARY(v) (((v) << 20) & 0x100000) | ||
| 364 | #define BF_IR_STAT_RXOF_SUMMARY_V(v) ((BV_IR_STAT_RXOF_SUMMARY__##v << 20) & 0x100000) | ||
| 365 | #define BP_IR_STAT_TXUF_SUMMARY 19 | ||
| 366 | #define BM_IR_STAT_TXUF_SUMMARY 0x80000 | ||
| 367 | #define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0 | ||
| 368 | #define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1 | ||
| 369 | #define BF_IR_STAT_TXUF_SUMMARY(v) (((v) << 19) & 0x80000) | ||
| 370 | #define BF_IR_STAT_TXUF_SUMMARY_V(v) ((BV_IR_STAT_TXUF_SUMMARY__##v << 19) & 0x80000) | ||
| 371 | #define BP_IR_STAT_TC_SUMMARY 18 | ||
| 372 | #define BM_IR_STAT_TC_SUMMARY 0x40000 | ||
| 373 | #define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0 | ||
| 374 | #define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1 | ||
| 375 | #define BF_IR_STAT_TC_SUMMARY(v) (((v) << 18) & 0x40000) | ||
| 376 | #define BF_IR_STAT_TC_SUMMARY_V(v) ((BV_IR_STAT_TC_SUMMARY__##v << 18) & 0x40000) | ||
| 377 | #define BP_IR_STAT_RX_SUMMARY 17 | ||
| 378 | #define BM_IR_STAT_RX_SUMMARY 0x20000 | ||
| 379 | #define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0 | ||
| 380 | #define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1 | ||
| 381 | #define BF_IR_STAT_RX_SUMMARY(v) (((v) << 17) & 0x20000) | ||
| 382 | #define BF_IR_STAT_RX_SUMMARY_V(v) ((BV_IR_STAT_RX_SUMMARY__##v << 17) & 0x20000) | ||
| 383 | #define BP_IR_STAT_TX_SUMMARY 16 | ||
| 384 | #define BM_IR_STAT_TX_SUMMARY 0x10000 | ||
| 385 | #define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0 | ||
| 386 | #define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1 | ||
| 387 | #define BF_IR_STAT_TX_SUMMARY(v) (((v) << 16) & 0x10000) | ||
| 388 | #define BF_IR_STAT_TX_SUMMARY_V(v) ((BV_IR_STAT_TX_SUMMARY__##v << 16) & 0x10000) | ||
| 389 | #define BP_IR_STAT_MEDIA_BUSY 2 | ||
| 390 | #define BM_IR_STAT_MEDIA_BUSY 0x4 | ||
| 391 | #define BF_IR_STAT_MEDIA_BUSY(v) (((v) << 2) & 0x4) | ||
| 392 | #define BP_IR_STAT_RX_ACTIVE 1 | ||
| 393 | #define BM_IR_STAT_RX_ACTIVE 0x2 | ||
| 394 | #define BF_IR_STAT_RX_ACTIVE(v) (((v) << 1) & 0x2) | ||
| 395 | #define BP_IR_STAT_TX_ACTIVE 0 | ||
| 396 | #define BM_IR_STAT_TX_ACTIVE 0x1 | ||
| 397 | #define BF_IR_STAT_TX_ACTIVE(v) (((v) << 0) & 0x1) | ||
| 398 | |||
| 399 | /** | ||
| 400 | * Register: HW_IR_TCCTRL | ||
| 401 | * Address: 0x70 | ||
| 402 | * SCT: yes | ||
| 403 | */ | ||
| 404 | #define HW_IR_TCCTRL (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x0)) | ||
| 405 | #define HW_IR_TCCTRL_SET (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x4)) | ||
| 406 | #define HW_IR_TCCTRL_CLR (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0x8)) | ||
| 407 | #define HW_IR_TCCTRL_TOG (*(volatile unsigned long *)(REGS_IR_BASE + 0x70 + 0xc)) | ||
| 408 | #define BP_IR_TCCTRL_INIT 31 | ||
| 409 | #define BM_IR_TCCTRL_INIT 0x80000000 | ||
| 410 | #define BF_IR_TCCTRL_INIT(v) (((v) << 31) & 0x80000000) | ||
| 411 | #define BP_IR_TCCTRL_GO 30 | ||
| 412 | #define BM_IR_TCCTRL_GO 0x40000000 | ||
| 413 | #define BF_IR_TCCTRL_GO(v) (((v) << 30) & 0x40000000) | ||
| 414 | #define BP_IR_TCCTRL_BUSY 29 | ||
| 415 | #define BM_IR_TCCTRL_BUSY 0x20000000 | ||
| 416 | #define BF_IR_TCCTRL_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 417 | #define BP_IR_TCCTRL_TEMIC 24 | ||
| 418 | #define BM_IR_TCCTRL_TEMIC 0x1000000 | ||
| 419 | #define BV_IR_TCCTRL_TEMIC__LOW 0x0 | ||
| 420 | #define BV_IR_TCCTRL_TEMIC__HIGH 0x1 | ||
| 421 | #define BF_IR_TCCTRL_TEMIC(v) (((v) << 24) & 0x1000000) | ||
| 422 | #define BF_IR_TCCTRL_TEMIC_V(v) ((BV_IR_TCCTRL_TEMIC__##v << 24) & 0x1000000) | ||
| 423 | #define BP_IR_TCCTRL_EXT_DATA 16 | ||
| 424 | #define BM_IR_TCCTRL_EXT_DATA 0xff0000 | ||
| 425 | #define BF_IR_TCCTRL_EXT_DATA(v) (((v) << 16) & 0xff0000) | ||
| 426 | #define BP_IR_TCCTRL_DATA 8 | ||
| 427 | #define BM_IR_TCCTRL_DATA 0xff00 | ||
| 428 | #define BF_IR_TCCTRL_DATA(v) (((v) << 8) & 0xff00) | ||
| 429 | #define BP_IR_TCCTRL_ADDR 5 | ||
| 430 | #define BM_IR_TCCTRL_ADDR 0xe0 | ||
| 431 | #define BF_IR_TCCTRL_ADDR(v) (((v) << 5) & 0xe0) | ||
| 432 | #define BP_IR_TCCTRL_INDX 1 | ||
| 433 | #define BM_IR_TCCTRL_INDX 0x1e | ||
| 434 | #define BF_IR_TCCTRL_INDX(v) (((v) << 1) & 0x1e) | ||
| 435 | #define BP_IR_TCCTRL_C 0 | ||
| 436 | #define BM_IR_TCCTRL_C 0x1 | ||
| 437 | #define BF_IR_TCCTRL_C(v) (((v) << 0) & 0x1) | ||
| 438 | |||
| 439 | /** | ||
| 440 | * Register: HW_IR_SI_READ | ||
| 441 | * Address: 0x80 | ||
| 442 | * SCT: no | ||
| 443 | */ | ||
| 444 | #define HW_IR_SI_READ (*(volatile unsigned long *)(REGS_IR_BASE + 0x80)) | ||
| 445 | #define BP_IR_SI_READ_ABORT 8 | ||
| 446 | #define BM_IR_SI_READ_ABORT 0x100 | ||
| 447 | #define BF_IR_SI_READ_ABORT(v) (((v) << 8) & 0x100) | ||
| 448 | #define BP_IR_SI_READ_DATA 0 | ||
| 449 | #define BM_IR_SI_READ_DATA 0xff | ||
| 450 | #define BF_IR_SI_READ_DATA(v) (((v) << 0) & 0xff) | ||
| 451 | |||
| 452 | /** | ||
| 453 | * Register: HW_IR_DEBUG | ||
| 454 | * Address: 0x90 | ||
| 455 | * SCT: no | ||
| 456 | */ | ||
| 457 | #define HW_IR_DEBUG (*(volatile unsigned long *)(REGS_IR_BASE + 0x90)) | ||
| 458 | #define BP_IR_DEBUG_TXDMAKICK 5 | ||
| 459 | #define BM_IR_DEBUG_TXDMAKICK 0x20 | ||
| 460 | #define BF_IR_DEBUG_TXDMAKICK(v) (((v) << 5) & 0x20) | ||
| 461 | #define BP_IR_DEBUG_RXDMAKICK 4 | ||
| 462 | #define BM_IR_DEBUG_RXDMAKICK 0x10 | ||
| 463 | #define BF_IR_DEBUG_RXDMAKICK(v) (((v) << 4) & 0x10) | ||
| 464 | #define BP_IR_DEBUG_TXDMAEND 3 | ||
| 465 | #define BM_IR_DEBUG_TXDMAEND 0x8 | ||
| 466 | #define BF_IR_DEBUG_TXDMAEND(v) (((v) << 3) & 0x8) | ||
| 467 | #define BP_IR_DEBUG_RXDMAEND 2 | ||
| 468 | #define BM_IR_DEBUG_RXDMAEND 0x4 | ||
| 469 | #define BF_IR_DEBUG_RXDMAEND(v) (((v) << 2) & 0x4) | ||
| 470 | #define BP_IR_DEBUG_TXDMAREQ 1 | ||
| 471 | #define BM_IR_DEBUG_TXDMAREQ 0x2 | ||
| 472 | #define BF_IR_DEBUG_TXDMAREQ(v) (((v) << 1) & 0x2) | ||
| 473 | #define BP_IR_DEBUG_RXDMAREQ 0 | ||
| 474 | #define BM_IR_DEBUG_RXDMAREQ 0x1 | ||
| 475 | #define BF_IR_DEBUG_RXDMAREQ(v) (((v) << 0) & 0x1) | ||
| 476 | |||
| 477 | /** | ||
| 478 | * Register: HW_IR_VERSION | ||
| 479 | * Address: 0xa0 | ||
| 480 | * SCT: no | ||
| 481 | */ | ||
| 482 | #define HW_IR_VERSION (*(volatile unsigned long *)(REGS_IR_BASE + 0xa0)) | ||
| 483 | #define BP_IR_VERSION_MAJOR 24 | ||
| 484 | #define BM_IR_VERSION_MAJOR 0xff000000 | ||
| 485 | #define BF_IR_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 486 | #define BP_IR_VERSION_MINOR 16 | ||
| 487 | #define BM_IR_VERSION_MINOR 0xff0000 | ||
| 488 | #define BF_IR_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 489 | #define BP_IR_VERSION_STEP 0 | ||
| 490 | #define BM_IR_VERSION_STEP 0xffff | ||
| 491 | #define BF_IR_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 492 | |||
| 493 | #endif /* __HEADERGEN__STMP3700__IR__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h new file mode 100644 index 0000000000..c528c81fee --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h | |||
| @@ -0,0 +1,451 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__LCDIF__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__LCDIF__H__ | ||
| 25 | |||
| 26 | #define REGS_LCDIF_BASE (0x80030000) | ||
| 27 | |||
| 28 | #define REGS_LCDIF_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_LCDIF_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_LCDIF_CTRL (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_LCDIF_CTRL_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_LCDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_LCDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_LCDIF_CTRL_SFTRST 31 | ||
| 40 | #define BM_LCDIF_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_LCDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_LCDIF_CTRL_CLKGATE 30 | ||
| 43 | #define BM_LCDIF_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_LCDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_LCDIF_CTRL_READ_WRITEB 29 | ||
| 46 | #define BM_LCDIF_CTRL_READ_WRITEB 0x20000000 | ||
| 47 | #define BF_LCDIF_CTRL_READ_WRITEB(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 28 | ||
| 49 | #define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000 | ||
| 50 | #define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_LCDIF_CTRL_DATA_SHIFT_DIR 27 | ||
| 52 | #define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x8000000 | ||
| 53 | #define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 | ||
| 54 | #define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 | ||
| 55 | #define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v) (((v) << 27) & 0x8000000) | ||
| 56 | #define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v) ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 27) & 0x8000000) | ||
| 57 | #define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25 | ||
| 58 | #define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x6000000 | ||
| 59 | #define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) (((v) << 25) & 0x6000000) | ||
| 60 | #define BP_LCDIF_CTRL_DVI_MODE 24 | ||
| 61 | #define BM_LCDIF_CTRL_DVI_MODE 0x1000000 | ||
| 62 | #define BF_LCDIF_CTRL_DVI_MODE(v) (((v) << 24) & 0x1000000) | ||
| 63 | #define BP_LCDIF_CTRL_BYPASS_COUNT 23 | ||
| 64 | #define BM_LCDIF_CTRL_BYPASS_COUNT 0x800000 | ||
| 65 | #define BF_LCDIF_CTRL_BYPASS_COUNT(v) (((v) << 23) & 0x800000) | ||
| 66 | #define BP_LCDIF_CTRL_DATA_SWIZZLE 21 | ||
| 67 | #define BM_LCDIF_CTRL_DATA_SWIZZLE 0x600000 | ||
| 68 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP 0x0 | ||
| 69 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 | ||
| 70 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 | ||
| 71 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 | ||
| 72 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP 0x2 | ||
| 73 | #define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 | ||
| 74 | #define BF_LCDIF_CTRL_DATA_SWIZZLE(v) (((v) << 21) & 0x600000) | ||
| 75 | #define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v) ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000) | ||
| 76 | #define BP_LCDIF_CTRL_VSYNC_MODE 20 | ||
| 77 | #define BM_LCDIF_CTRL_VSYNC_MODE 0x100000 | ||
| 78 | #define BF_LCDIF_CTRL_VSYNC_MODE(v) (((v) << 20) & 0x100000) | ||
| 79 | #define BP_LCDIF_CTRL_DOTCLK_MODE 19 | ||
| 80 | #define BM_LCDIF_CTRL_DOTCLK_MODE 0x80000 | ||
| 81 | #define BF_LCDIF_CTRL_DOTCLK_MODE(v) (((v) << 19) & 0x80000) | ||
| 82 | #define BP_LCDIF_CTRL_DATA_SELECT 18 | ||
| 83 | #define BM_LCDIF_CTRL_DATA_SELECT 0x40000 | ||
| 84 | #define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 | ||
| 85 | #define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 | ||
| 86 | #define BF_LCDIF_CTRL_DATA_SELECT(v) (((v) << 18) & 0x40000) | ||
| 87 | #define BF_LCDIF_CTRL_DATA_SELECT_V(v) ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000) | ||
| 88 | #define BP_LCDIF_CTRL_WORD_LENGTH 17 | ||
| 89 | #define BM_LCDIF_CTRL_WORD_LENGTH 0x20000 | ||
| 90 | #define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 | ||
| 91 | #define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 | ||
| 92 | #define BF_LCDIF_CTRL_WORD_LENGTH(v) (((v) << 17) & 0x20000) | ||
| 93 | #define BF_LCDIF_CTRL_WORD_LENGTH_V(v) ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000) | ||
| 94 | #define BP_LCDIF_CTRL_RUN 16 | ||
| 95 | #define BM_LCDIF_CTRL_RUN 0x10000 | ||
| 96 | #define BF_LCDIF_CTRL_RUN(v) (((v) << 16) & 0x10000) | ||
| 97 | #define BP_LCDIF_CTRL_COUNT 0 | ||
| 98 | #define BM_LCDIF_CTRL_COUNT 0xffff | ||
| 99 | #define BF_LCDIF_CTRL_COUNT(v) (((v) << 0) & 0xffff) | ||
| 100 | |||
| 101 | /** | ||
| 102 | * Register: HW_LCDIF_CTRL1 | ||
| 103 | * Address: 0x10 | ||
| 104 | * SCT: yes | ||
| 105 | */ | ||
| 106 | #define HW_LCDIF_CTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0)) | ||
| 107 | #define HW_LCDIF_CTRL1_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4)) | ||
| 108 | #define HW_LCDIF_CTRL1_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8)) | ||
| 109 | #define HW_LCDIF_CTRL1_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc)) | ||
| 110 | #define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 | ||
| 111 | #define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0xf0000 | ||
| 112 | #define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) (((v) << 16) & 0xf0000) | ||
| 113 | #define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN 15 | ||
| 114 | #define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x8000 | ||
| 115 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v) (((v) << 15) & 0x8000) | ||
| 116 | #define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 14 | ||
| 117 | #define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x4000 | ||
| 118 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 119 | #define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 13 | ||
| 120 | #define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x2000 | ||
| 121 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v) (((v) << 13) & 0x2000) | ||
| 122 | #define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 12 | ||
| 123 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x1000 | ||
| 124 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v) (((v) << 12) & 0x1000) | ||
| 125 | #define BP_LCDIF_CTRL1_OVERFLOW_IRQ 11 | ||
| 126 | #define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x800 | ||
| 127 | #define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 | ||
| 128 | #define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 | ||
| 129 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v) (((v) << 11) & 0x800) | ||
| 130 | #define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v) ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800) | ||
| 131 | #define BP_LCDIF_CTRL1_UNDERFLOW_IRQ 10 | ||
| 132 | #define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x400 | ||
| 133 | #define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 | ||
| 134 | #define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 | ||
| 135 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v) (((v) << 10) & 0x400) | ||
| 136 | #define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v) ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400) | ||
| 137 | #define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 9 | ||
| 138 | #define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x200 | ||
| 139 | #define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 | ||
| 140 | #define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 | ||
| 141 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v) (((v) << 9) & 0x200) | ||
| 142 | #define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v) ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200) | ||
| 143 | #define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ 8 | ||
| 144 | #define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x100 | ||
| 145 | #define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 | ||
| 146 | #define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 | ||
| 147 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v) (((v) << 8) & 0x100) | ||
| 148 | #define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v) ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100) | ||
| 149 | #define BP_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS 5 | ||
| 150 | #define BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS 0xe0 | ||
| 151 | #define BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(v) (((v) << 5) & 0xe0) | ||
| 152 | #define BP_LCDIF_CTRL1_FIRST_READ_DUMMY 4 | ||
| 153 | #define BM_LCDIF_CTRL1_FIRST_READ_DUMMY 0x10 | ||
| 154 | #define BF_LCDIF_CTRL1_FIRST_READ_DUMMY(v) (((v) << 4) & 0x10) | ||
| 155 | #define BP_LCDIF_CTRL1_LCD_CS_CTRL 3 | ||
| 156 | #define BM_LCDIF_CTRL1_LCD_CS_CTRL 0x8 | ||
| 157 | #define BF_LCDIF_CTRL1_LCD_CS_CTRL(v) (((v) << 3) & 0x8) | ||
| 158 | #define BP_LCDIF_CTRL1_BUSY_ENABLE 2 | ||
| 159 | #define BM_LCDIF_CTRL1_BUSY_ENABLE 0x4 | ||
| 160 | #define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 | ||
| 161 | #define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 | ||
| 162 | #define BF_LCDIF_CTRL1_BUSY_ENABLE(v) (((v) << 2) & 0x4) | ||
| 163 | #define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v) ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4) | ||
| 164 | #define BP_LCDIF_CTRL1_MODE86 1 | ||
| 165 | #define BM_LCDIF_CTRL1_MODE86 0x2 | ||
| 166 | #define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 | ||
| 167 | #define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 | ||
| 168 | #define BF_LCDIF_CTRL1_MODE86(v) (((v) << 1) & 0x2) | ||
| 169 | #define BF_LCDIF_CTRL1_MODE86_V(v) ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2) | ||
| 170 | #define BP_LCDIF_CTRL1_RESET 0 | ||
| 171 | #define BM_LCDIF_CTRL1_RESET 0x1 | ||
| 172 | #define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 | ||
| 173 | #define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 | ||
| 174 | #define BF_LCDIF_CTRL1_RESET(v) (((v) << 0) & 0x1) | ||
| 175 | #define BF_LCDIF_CTRL1_RESET_V(v) ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1) | ||
| 176 | |||
| 177 | /** | ||
| 178 | * Register: HW_LCDIF_TIMING | ||
| 179 | * Address: 0x20 | ||
| 180 | * SCT: no | ||
| 181 | */ | ||
| 182 | #define HW_LCDIF_TIMING (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20)) | ||
| 183 | #define BP_LCDIF_TIMING_CMD_HOLD 24 | ||
| 184 | #define BM_LCDIF_TIMING_CMD_HOLD 0xff000000 | ||
| 185 | #define BF_LCDIF_TIMING_CMD_HOLD(v) (((v) << 24) & 0xff000000) | ||
| 186 | #define BP_LCDIF_TIMING_CMD_SETUP 16 | ||
| 187 | #define BM_LCDIF_TIMING_CMD_SETUP 0xff0000 | ||
| 188 | #define BF_LCDIF_TIMING_CMD_SETUP(v) (((v) << 16) & 0xff0000) | ||
| 189 | #define BP_LCDIF_TIMING_DATA_HOLD 8 | ||
| 190 | #define BM_LCDIF_TIMING_DATA_HOLD 0xff00 | ||
| 191 | #define BF_LCDIF_TIMING_DATA_HOLD(v) (((v) << 8) & 0xff00) | ||
| 192 | #define BP_LCDIF_TIMING_DATA_SETUP 0 | ||
| 193 | #define BM_LCDIF_TIMING_DATA_SETUP 0xff | ||
| 194 | #define BF_LCDIF_TIMING_DATA_SETUP(v) (((v) << 0) & 0xff) | ||
| 195 | |||
| 196 | /** | ||
| 197 | * Register: HW_LCDIF_VDCTRL0 | ||
| 198 | * Address: 0x30 | ||
| 199 | * SCT: yes | ||
| 200 | */ | ||
| 201 | #define HW_LCDIF_VDCTRL0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x0)) | ||
| 202 | #define HW_LCDIF_VDCTRL0_SET (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x4)) | ||
| 203 | #define HW_LCDIF_VDCTRL0_CLR (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x8)) | ||
| 204 | #define HW_LCDIF_VDCTRL0_TOG (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0xc)) | ||
| 205 | #define BP_LCDIF_VDCTRL0_VSYNC_OEB 29 | ||
| 206 | #define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 | ||
| 207 | #define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 | ||
| 208 | #define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 | ||
| 209 | #define BF_LCDIF_VDCTRL0_VSYNC_OEB(v) (((v) << 29) & 0x20000000) | ||
| 210 | #define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v) ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000) | ||
| 211 | #define BP_LCDIF_VDCTRL0_ENABLE_PRESENT 28 | ||
| 212 | #define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 | ||
| 213 | #define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 214 | #define BP_LCDIF_VDCTRL0_VSYNC_POL 27 | ||
| 215 | #define BM_LCDIF_VDCTRL0_VSYNC_POL 0x8000000 | ||
| 216 | #define BF_LCDIF_VDCTRL0_VSYNC_POL(v) (((v) << 27) & 0x8000000) | ||
| 217 | #define BP_LCDIF_VDCTRL0_HSYNC_POL 26 | ||
| 218 | #define BM_LCDIF_VDCTRL0_HSYNC_POL 0x4000000 | ||
| 219 | #define BF_LCDIF_VDCTRL0_HSYNC_POL(v) (((v) << 26) & 0x4000000) | ||
| 220 | #define BP_LCDIF_VDCTRL0_DOTCLK_POL 25 | ||
| 221 | #define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x2000000 | ||
| 222 | #define BF_LCDIF_VDCTRL0_DOTCLK_POL(v) (((v) << 25) & 0x2000000) | ||
| 223 | #define BP_LCDIF_VDCTRL0_ENABLE_POL 24 | ||
| 224 | #define BM_LCDIF_VDCTRL0_ENABLE_POL 0x1000000 | ||
| 225 | #define BF_LCDIF_VDCTRL0_ENABLE_POL(v) (((v) << 24) & 0x1000000) | ||
| 226 | #define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 21 | ||
| 227 | #define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x200000 | ||
| 228 | #define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v) (((v) << 21) & 0x200000) | ||
| 229 | #define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 20 | ||
| 230 | #define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x100000 | ||
| 231 | #define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v) (((v) << 20) & 0x100000) | ||
| 232 | #define BP_LCDIF_VDCTRL0_INTERLACE 19 | ||
| 233 | #define BM_LCDIF_VDCTRL0_INTERLACE 0x80000 | ||
| 234 | #define BF_LCDIF_VDCTRL0_INTERLACE(v) (((v) << 19) & 0x80000) | ||
| 235 | #define BP_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT 0 | ||
| 236 | #define BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT 0x3ff | ||
| 237 | #define BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(v) (((v) << 0) & 0x3ff) | ||
| 238 | |||
| 239 | /** | ||
| 240 | * Register: HW_LCDIF_VDCTRL1 | ||
| 241 | * Address: 0x40 | ||
| 242 | * SCT: no | ||
| 243 | */ | ||
| 244 | #define HW_LCDIF_VDCTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40)) | ||
| 245 | #define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20 | ||
| 246 | #define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xfff00000 | ||
| 247 | #define BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(v) (((v) << 20) & 0xfff00000) | ||
| 248 | #define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 | ||
| 249 | #define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xfffff | ||
| 250 | #define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (((v) << 0) & 0xfffff) | ||
| 251 | |||
| 252 | /** | ||
| 253 | * Register: HW_LCDIF_VDCTRL2 | ||
| 254 | * Address: 0x50 | ||
| 255 | * SCT: no | ||
| 256 | */ | ||
| 257 | #define HW_LCDIF_VDCTRL2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50)) | ||
| 258 | #define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23 | ||
| 259 | #define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xff800000 | ||
| 260 | #define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) (((v) << 23) & 0xff800000) | ||
| 261 | #define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11 | ||
| 262 | #define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x7ff800 | ||
| 263 | #define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) (((v) << 11) & 0x7ff800) | ||
| 264 | #define BP_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT 0 | ||
| 265 | #define BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT 0x7ff | ||
| 266 | #define BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x7ff) | ||
| 267 | |||
| 268 | /** | ||
| 269 | * Register: HW_LCDIF_VDCTRL3 | ||
| 270 | * Address: 0x60 | ||
| 271 | * SCT: no | ||
| 272 | */ | ||
| 273 | #define HW_LCDIF_VDCTRL3 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60)) | ||
| 274 | #define BP_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 24 | ||
| 275 | #define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x1000000 | ||
| 276 | #define BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(v) (((v) << 24) & 0x1000000) | ||
| 277 | #define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12 | ||
| 278 | #define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0xfff000 | ||
| 279 | #define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 12) & 0xfff000) | ||
| 280 | #define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 | ||
| 281 | #define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x1ff | ||
| 282 | #define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) (((v) << 0) & 0x1ff) | ||
| 283 | |||
| 284 | /** | ||
| 285 | * Register: HW_LCDIF_DVICTRL0 | ||
| 286 | * Address: 0x70 | ||
| 287 | * SCT: no | ||
| 288 | */ | ||
| 289 | #define HW_LCDIF_DVICTRL0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70)) | ||
| 290 | #define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 | ||
| 291 | #define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7ff00000 | ||
| 292 | #define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) (((v) << 20) & 0x7ff00000) | ||
| 293 | #define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 | ||
| 294 | #define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0xffc00 | ||
| 295 | #define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00) | ||
| 296 | #define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 | ||
| 297 | #define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x3ff | ||
| 298 | #define BF_LCDIF_DVICTRL0_V_LINES_CNT(v) (((v) << 0) & 0x3ff) | ||
| 299 | |||
| 300 | /** | ||
| 301 | * Register: HW_LCDIF_DVICTRL1 | ||
| 302 | * Address: 0x80 | ||
| 303 | * SCT: no | ||
| 304 | */ | ||
| 305 | #define HW_LCDIF_DVICTRL1 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80)) | ||
| 306 | #define BP_LCDIF_DVICTRL1_F1_START_LINE 20 | ||
| 307 | #define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3ff00000 | ||
| 308 | #define BF_LCDIF_DVICTRL1_F1_START_LINE(v) (((v) << 20) & 0x3ff00000) | ||
| 309 | #define BP_LCDIF_DVICTRL1_F1_END_LINE 10 | ||
| 310 | #define BM_LCDIF_DVICTRL1_F1_END_LINE 0xffc00 | ||
| 311 | #define BF_LCDIF_DVICTRL1_F1_END_LINE(v) (((v) << 10) & 0xffc00) | ||
| 312 | #define BP_LCDIF_DVICTRL1_F2_START_LINE 0 | ||
| 313 | #define BM_LCDIF_DVICTRL1_F2_START_LINE 0x3ff | ||
| 314 | #define BF_LCDIF_DVICTRL1_F2_START_LINE(v) (((v) << 0) & 0x3ff) | ||
| 315 | |||
| 316 | /** | ||
| 317 | * Register: HW_LCDIF_DVICTRL2 | ||
| 318 | * Address: 0x90 | ||
| 319 | * SCT: no | ||
| 320 | */ | ||
| 321 | #define HW_LCDIF_DVICTRL2 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90)) | ||
| 322 | #define BP_LCDIF_DVICTRL2_F2_END_LINE 20 | ||
| 323 | #define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3ff00000 | ||
| 324 | #define BF_LCDIF_DVICTRL2_F2_END_LINE(v) (((v) << 20) & 0x3ff00000) | ||
| 325 | #define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 | ||
| 326 | #define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0xffc00 | ||
| 327 | #define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) (((v) << 10) & 0xffc00) | ||
| 328 | #define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 | ||
| 329 | #define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x3ff | ||
| 330 | #define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) (((v) << 0) & 0x3ff) | ||
| 331 | |||
| 332 | /** | ||
| 333 | * Register: HW_LCDIF_DVICTRL3 | ||
| 334 | * Address: 0xa0 | ||
| 335 | * SCT: no | ||
| 336 | */ | ||
| 337 | #define HW_LCDIF_DVICTRL3 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0)) | ||
| 338 | #define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 | ||
| 339 | #define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3ff0000 | ||
| 340 | #define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) (((v) << 16) & 0x3ff0000) | ||
| 341 | #define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 | ||
| 342 | #define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x3ff | ||
| 343 | #define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) (((v) << 0) & 0x3ff) | ||
| 344 | |||
| 345 | /** | ||
| 346 | * Register: HW_LCDIF_DATA | ||
| 347 | * Address: 0xb0 | ||
| 348 | * SCT: no | ||
| 349 | */ | ||
| 350 | #define HW_LCDIF_DATA (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0)) | ||
| 351 | #define BP_LCDIF_DATA_DATA_THREE 24 | ||
| 352 | #define BM_LCDIF_DATA_DATA_THREE 0xff000000 | ||
| 353 | #define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000) | ||
| 354 | #define BP_LCDIF_DATA_DATA_TWO 16 | ||
| 355 | #define BM_LCDIF_DATA_DATA_TWO 0xff0000 | ||
| 356 | #define BF_LCDIF_DATA_DATA_TWO(v) (((v) << 16) & 0xff0000) | ||
| 357 | #define BP_LCDIF_DATA_DATA_ONE 8 | ||
| 358 | #define BM_LCDIF_DATA_DATA_ONE 0xff00 | ||
| 359 | #define BF_LCDIF_DATA_DATA_ONE(v) (((v) << 8) & 0xff00) | ||
| 360 | #define BP_LCDIF_DATA_DATA_ZERO 0 | ||
| 361 | #define BM_LCDIF_DATA_DATA_ZERO 0xff | ||
| 362 | #define BF_LCDIF_DATA_DATA_ZERO(v) (((v) << 0) & 0xff) | ||
| 363 | |||
| 364 | /** | ||
| 365 | * Register: HW_LCDIF_STAT | ||
| 366 | * Address: 0xc0 | ||
| 367 | * SCT: no | ||
| 368 | */ | ||
| 369 | #define HW_LCDIF_STAT (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0)) | ||
| 370 | #define BP_LCDIF_STAT_PRESENT 31 | ||
| 371 | #define BM_LCDIF_STAT_PRESENT 0x80000000 | ||
| 372 | #define BF_LCDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 373 | #define BP_LCDIF_STAT_DMA_REQ 30 | ||
| 374 | #define BM_LCDIF_STAT_DMA_REQ 0x40000000 | ||
| 375 | #define BF_LCDIF_STAT_DMA_REQ(v) (((v) << 30) & 0x40000000) | ||
| 376 | #define BP_LCDIF_STAT_RXFIFO_FULL 29 | ||
| 377 | #define BM_LCDIF_STAT_RXFIFO_FULL 0x20000000 | ||
| 378 | #define BF_LCDIF_STAT_RXFIFO_FULL(v) (((v) << 29) & 0x20000000) | ||
| 379 | #define BP_LCDIF_STAT_RXFIFO_EMPTY 28 | ||
| 380 | #define BM_LCDIF_STAT_RXFIFO_EMPTY 0x10000000 | ||
| 381 | #define BF_LCDIF_STAT_RXFIFO_EMPTY(v) (((v) << 28) & 0x10000000) | ||
| 382 | #define BP_LCDIF_STAT_TXFIFO_FULL 27 | ||
| 383 | #define BM_LCDIF_STAT_TXFIFO_FULL 0x8000000 | ||
| 384 | #define BF_LCDIF_STAT_TXFIFO_FULL(v) (((v) << 27) & 0x8000000) | ||
| 385 | #define BP_LCDIF_STAT_TXFIFO_EMPTY 26 | ||
| 386 | #define BM_LCDIF_STAT_TXFIFO_EMPTY 0x4000000 | ||
| 387 | #define BF_LCDIF_STAT_TXFIFO_EMPTY(v) (((v) << 26) & 0x4000000) | ||
| 388 | #define BP_LCDIF_STAT_BUSY 25 | ||
| 389 | #define BM_LCDIF_STAT_BUSY 0x2000000 | ||
| 390 | #define BF_LCDIF_STAT_BUSY(v) (((v) << 25) & 0x2000000) | ||
| 391 | #define BP_LCDIF_STAT_DVI_CURRENT_FIELD 24 | ||
| 392 | #define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x1000000 | ||
| 393 | #define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v) (((v) << 24) & 0x1000000) | ||
| 394 | |||
| 395 | /** | ||
| 396 | * Register: HW_LCDIF_VERSION | ||
| 397 | * Address: 0xd0 | ||
| 398 | * SCT: no | ||
| 399 | */ | ||
| 400 | #define HW_LCDIF_VERSION (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0)) | ||
| 401 | #define BP_LCDIF_VERSION_MAJOR 24 | ||
| 402 | #define BM_LCDIF_VERSION_MAJOR 0xff000000 | ||
| 403 | #define BF_LCDIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 404 | #define BP_LCDIF_VERSION_MINOR 16 | ||
| 405 | #define BM_LCDIF_VERSION_MINOR 0xff0000 | ||
| 406 | #define BF_LCDIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 407 | #define BP_LCDIF_VERSION_STEP 0 | ||
| 408 | #define BM_LCDIF_VERSION_STEP 0xffff | ||
| 409 | #define BF_LCDIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 410 | |||
| 411 | /** | ||
| 412 | * Register: HW_LCDIF_DEBUG0 | ||
| 413 | * Address: 0xe0 | ||
| 414 | * SCT: no | ||
| 415 | */ | ||
| 416 | #define HW_LCDIF_DEBUG0 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0)) | ||
| 417 | #define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED 31 | ||
| 418 | #define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 | ||
| 419 | #define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v) (((v) << 31) & 0x80000000) | ||
| 420 | #define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 30 | ||
| 421 | #define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 | ||
| 422 | #define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v) (((v) << 30) & 0x40000000) | ||
| 423 | #define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 29 | ||
| 424 | #define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 | ||
| 425 | #define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v) (((v) << 29) & 0x20000000) | ||
| 426 | #define BP_LCDIF_DEBUG0_DMACMDKICK 28 | ||
| 427 | #define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 | ||
| 428 | #define BF_LCDIF_DEBUG0_DMACMDKICK(v) (((v) << 28) & 0x10000000) | ||
| 429 | #define BP_LCDIF_DEBUG0_ENABLE 27 | ||
| 430 | #define BM_LCDIF_DEBUG0_ENABLE 0x8000000 | ||
| 431 | #define BF_LCDIF_DEBUG0_ENABLE(v) (((v) << 27) & 0x8000000) | ||
| 432 | #define BP_LCDIF_DEBUG0_HSYNC 26 | ||
| 433 | #define BM_LCDIF_DEBUG0_HSYNC 0x4000000 | ||
| 434 | #define BF_LCDIF_DEBUG0_HSYNC(v) (((v) << 26) & 0x4000000) | ||
| 435 | #define BP_LCDIF_DEBUG0_VSYNC 25 | ||
| 436 | #define BM_LCDIF_DEBUG0_VSYNC 0x2000000 | ||
| 437 | #define BF_LCDIF_DEBUG0_VSYNC(v) (((v) << 25) & 0x2000000) | ||
| 438 | #define BP_LCDIF_DEBUG0_CUR_FRAME_TX 24 | ||
| 439 | #define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x1000000 | ||
| 440 | #define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v) (((v) << 24) & 0x1000000) | ||
| 441 | #define BP_LCDIF_DEBUG0_EMPTY_WORD 23 | ||
| 442 | #define BM_LCDIF_DEBUG0_EMPTY_WORD 0x800000 | ||
| 443 | #define BF_LCDIF_DEBUG0_EMPTY_WORD(v) (((v) << 23) & 0x800000) | ||
| 444 | #define BP_LCDIF_DEBUG0_CUR_STATE 16 | ||
| 445 | #define BM_LCDIF_DEBUG0_CUR_STATE 0x7f0000 | ||
| 446 | #define BF_LCDIF_DEBUG0_CUR_STATE(v) (((v) << 16) & 0x7f0000) | ||
| 447 | #define BP_LCDIF_DEBUG0_DATA_COUNT 0 | ||
| 448 | #define BM_LCDIF_DEBUG0_DATA_COUNT 0xffff | ||
| 449 | #define BF_LCDIF_DEBUG0_DATA_COUNT(v) (((v) << 0) & 0xffff) | ||
| 450 | |||
| 451 | #endif /* __HEADERGEN__STMP3700__LCDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h new file mode 100644 index 0000000000..ad0beecbae --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lradc.h | |||
| @@ -0,0 +1,708 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__LRADC__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__LRADC__H__ | ||
| 25 | |||
| 26 | #define REGS_LRADC_BASE (0x80050000) | ||
| 27 | |||
| 28 | #define REGS_LRADC_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_LRADC_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_LRADC_CTRL0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_LRADC_CTRL0_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_LRADC_CTRL0_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_LRADC_CTRL0_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_LRADC_CTRL0_SFTRST 31 | ||
| 40 | #define BM_LRADC_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_LRADC_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_LRADC_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_LRADC_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_LRADC_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_LRADC_CTRL0_ONCHIP_GROUNDREF 21 | ||
| 46 | #define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x200000 | ||
| 47 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 | ||
| 48 | #define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 | ||
| 49 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF(v) (((v) << 21) & 0x200000) | ||
| 50 | #define BF_LRADC_CTRL0_ONCHIP_GROUNDREF_V(v) ((BV_LRADC_CTRL0_ONCHIP_GROUNDREF__##v << 21) & 0x200000) | ||
| 51 | #define BP_LRADC_CTRL0_TOUCH_DETECT_ENABLE 20 | ||
| 52 | #define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x100000 | ||
| 53 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 | ||
| 54 | #define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 | ||
| 55 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE(v) (((v) << 20) & 0x100000) | ||
| 56 | #define BF_LRADC_CTRL0_TOUCH_DETECT_ENABLE_V(v) ((BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__##v << 20) & 0x100000) | ||
| 57 | #define BP_LRADC_CTRL0_YMINUS_ENABLE 19 | ||
| 58 | #define BM_LRADC_CTRL0_YMINUS_ENABLE 0x80000 | ||
| 59 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 | ||
| 60 | #define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 | ||
| 61 | #define BF_LRADC_CTRL0_YMINUS_ENABLE(v) (((v) << 19) & 0x80000) | ||
| 62 | #define BF_LRADC_CTRL0_YMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YMINUS_ENABLE__##v << 19) & 0x80000) | ||
| 63 | #define BP_LRADC_CTRL0_XMINUS_ENABLE 18 | ||
| 64 | #define BM_LRADC_CTRL0_XMINUS_ENABLE 0x40000 | ||
| 65 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 | ||
| 66 | #define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 | ||
| 67 | #define BF_LRADC_CTRL0_XMINUS_ENABLE(v) (((v) << 18) & 0x40000) | ||
| 68 | #define BF_LRADC_CTRL0_XMINUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XMINUS_ENABLE__##v << 18) & 0x40000) | ||
| 69 | #define BP_LRADC_CTRL0_YPLUS_ENABLE 17 | ||
| 70 | #define BM_LRADC_CTRL0_YPLUS_ENABLE 0x20000 | ||
| 71 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 | ||
| 72 | #define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 | ||
| 73 | #define BF_LRADC_CTRL0_YPLUS_ENABLE(v) (((v) << 17) & 0x20000) | ||
| 74 | #define BF_LRADC_CTRL0_YPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_YPLUS_ENABLE__##v << 17) & 0x20000) | ||
| 75 | #define BP_LRADC_CTRL0_XPLUS_ENABLE 16 | ||
| 76 | #define BM_LRADC_CTRL0_XPLUS_ENABLE 0x10000 | ||
| 77 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 | ||
| 78 | #define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 | ||
| 79 | #define BF_LRADC_CTRL0_XPLUS_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 80 | #define BF_LRADC_CTRL0_XPLUS_ENABLE_V(v) ((BV_LRADC_CTRL0_XPLUS_ENABLE__##v << 16) & 0x10000) | ||
| 81 | #define BP_LRADC_CTRL0_SCHEDULE 0 | ||
| 82 | #define BM_LRADC_CTRL0_SCHEDULE 0xff | ||
| 83 | #define BF_LRADC_CTRL0_SCHEDULE(v) (((v) << 0) & 0xff) | ||
| 84 | |||
| 85 | /** | ||
| 86 | * Register: HW_LRADC_CTRL1 | ||
| 87 | * Address: 0x10 | ||
| 88 | * SCT: yes | ||
| 89 | */ | ||
| 90 | #define HW_LRADC_CTRL1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x0)) | ||
| 91 | #define HW_LRADC_CTRL1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x4)) | ||
| 92 | #define HW_LRADC_CTRL1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0x8)) | ||
| 93 | #define HW_LRADC_CTRL1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x10 + 0xc)) | ||
| 94 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 24 | ||
| 95 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x1000000 | ||
| 96 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 | ||
| 97 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 | ||
| 98 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
| 99 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__##v << 24) & 0x1000000) | ||
| 100 | #define BP_LRADC_CTRL1_LRADC7_IRQ_EN 23 | ||
| 101 | #define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x800000 | ||
| 102 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 | ||
| 103 | #define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 | ||
| 104 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN(v) (((v) << 23) & 0x800000) | ||
| 105 | #define BF_LRADC_CTRL1_LRADC7_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ_EN__##v << 23) & 0x800000) | ||
| 106 | #define BP_LRADC_CTRL1_LRADC6_IRQ_EN 22 | ||
| 107 | #define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x400000 | ||
| 108 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 | ||
| 109 | #define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 | ||
| 110 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
| 111 | #define BF_LRADC_CTRL1_LRADC6_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ_EN__##v << 22) & 0x400000) | ||
| 112 | #define BP_LRADC_CTRL1_LRADC5_IRQ_EN 21 | ||
| 113 | #define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x200000 | ||
| 114 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 | ||
| 115 | #define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 | ||
| 116 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN(v) (((v) << 21) & 0x200000) | ||
| 117 | #define BF_LRADC_CTRL1_LRADC5_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ_EN__##v << 21) & 0x200000) | ||
| 118 | #define BP_LRADC_CTRL1_LRADC4_IRQ_EN 20 | ||
| 119 | #define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x100000 | ||
| 120 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 | ||
| 121 | #define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 | ||
| 122 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN(v) (((v) << 20) & 0x100000) | ||
| 123 | #define BF_LRADC_CTRL1_LRADC4_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ_EN__##v << 20) & 0x100000) | ||
| 124 | #define BP_LRADC_CTRL1_LRADC3_IRQ_EN 19 | ||
| 125 | #define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x80000 | ||
| 126 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 | ||
| 127 | #define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 | ||
| 128 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN(v) (((v) << 19) & 0x80000) | ||
| 129 | #define BF_LRADC_CTRL1_LRADC3_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ_EN__##v << 19) & 0x80000) | ||
| 130 | #define BP_LRADC_CTRL1_LRADC2_IRQ_EN 18 | ||
| 131 | #define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x40000 | ||
| 132 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 | ||
| 133 | #define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 | ||
| 134 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
| 135 | #define BF_LRADC_CTRL1_LRADC2_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ_EN__##v << 18) & 0x40000) | ||
| 136 | #define BP_LRADC_CTRL1_LRADC1_IRQ_EN 17 | ||
| 137 | #define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x20000 | ||
| 138 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 | ||
| 139 | #define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 | ||
| 140 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN(v) (((v) << 17) & 0x20000) | ||
| 141 | #define BF_LRADC_CTRL1_LRADC1_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ_EN__##v << 17) & 0x20000) | ||
| 142 | #define BP_LRADC_CTRL1_LRADC0_IRQ_EN 16 | ||
| 143 | #define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x10000 | ||
| 144 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 | ||
| 145 | #define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 | ||
| 146 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
| 147 | #define BF_LRADC_CTRL1_LRADC0_IRQ_EN_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ_EN__##v << 16) & 0x10000) | ||
| 148 | #define BP_LRADC_CTRL1_TOUCH_DETECT_IRQ 8 | ||
| 149 | #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x100 | ||
| 150 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 | ||
| 151 | #define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 | ||
| 152 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ(v) (((v) << 8) & 0x100) | ||
| 153 | #define BF_LRADC_CTRL1_TOUCH_DETECT_IRQ_V(v) ((BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__##v << 8) & 0x100) | ||
| 154 | #define BP_LRADC_CTRL1_LRADC7_IRQ 7 | ||
| 155 | #define BM_LRADC_CTRL1_LRADC7_IRQ 0x80 | ||
| 156 | #define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 | ||
| 157 | #define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 | ||
| 158 | #define BF_LRADC_CTRL1_LRADC7_IRQ(v) (((v) << 7) & 0x80) | ||
| 159 | #define BF_LRADC_CTRL1_LRADC7_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC7_IRQ__##v << 7) & 0x80) | ||
| 160 | #define BP_LRADC_CTRL1_LRADC6_IRQ 6 | ||
| 161 | #define BM_LRADC_CTRL1_LRADC6_IRQ 0x40 | ||
| 162 | #define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 | ||
| 163 | #define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 | ||
| 164 | #define BF_LRADC_CTRL1_LRADC6_IRQ(v) (((v) << 6) & 0x40) | ||
| 165 | #define BF_LRADC_CTRL1_LRADC6_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC6_IRQ__##v << 6) & 0x40) | ||
| 166 | #define BP_LRADC_CTRL1_LRADC5_IRQ 5 | ||
| 167 | #define BM_LRADC_CTRL1_LRADC5_IRQ 0x20 | ||
| 168 | #define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 | ||
| 169 | #define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 | ||
| 170 | #define BF_LRADC_CTRL1_LRADC5_IRQ(v) (((v) << 5) & 0x20) | ||
| 171 | #define BF_LRADC_CTRL1_LRADC5_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC5_IRQ__##v << 5) & 0x20) | ||
| 172 | #define BP_LRADC_CTRL1_LRADC4_IRQ 4 | ||
| 173 | #define BM_LRADC_CTRL1_LRADC4_IRQ 0x10 | ||
| 174 | #define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 | ||
| 175 | #define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 | ||
| 176 | #define BF_LRADC_CTRL1_LRADC4_IRQ(v) (((v) << 4) & 0x10) | ||
| 177 | #define BF_LRADC_CTRL1_LRADC4_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC4_IRQ__##v << 4) & 0x10) | ||
| 178 | #define BP_LRADC_CTRL1_LRADC3_IRQ 3 | ||
| 179 | #define BM_LRADC_CTRL1_LRADC3_IRQ 0x8 | ||
| 180 | #define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 | ||
| 181 | #define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 | ||
| 182 | #define BF_LRADC_CTRL1_LRADC3_IRQ(v) (((v) << 3) & 0x8) | ||
| 183 | #define BF_LRADC_CTRL1_LRADC3_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC3_IRQ__##v << 3) & 0x8) | ||
| 184 | #define BP_LRADC_CTRL1_LRADC2_IRQ 2 | ||
| 185 | #define BM_LRADC_CTRL1_LRADC2_IRQ 0x4 | ||
| 186 | #define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 | ||
| 187 | #define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 | ||
| 188 | #define BF_LRADC_CTRL1_LRADC2_IRQ(v) (((v) << 2) & 0x4) | ||
| 189 | #define BF_LRADC_CTRL1_LRADC2_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC2_IRQ__##v << 2) & 0x4) | ||
| 190 | #define BP_LRADC_CTRL1_LRADC1_IRQ 1 | ||
| 191 | #define BM_LRADC_CTRL1_LRADC1_IRQ 0x2 | ||
| 192 | #define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 | ||
| 193 | #define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 | ||
| 194 | #define BF_LRADC_CTRL1_LRADC1_IRQ(v) (((v) << 1) & 0x2) | ||
| 195 | #define BF_LRADC_CTRL1_LRADC1_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC1_IRQ__##v << 1) & 0x2) | ||
| 196 | #define BP_LRADC_CTRL1_LRADC0_IRQ 0 | ||
| 197 | #define BM_LRADC_CTRL1_LRADC0_IRQ 0x1 | ||
| 198 | #define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 | ||
| 199 | #define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 | ||
| 200 | #define BF_LRADC_CTRL1_LRADC0_IRQ(v) (((v) << 0) & 0x1) | ||
| 201 | #define BF_LRADC_CTRL1_LRADC0_IRQ_V(v) ((BV_LRADC_CTRL1_LRADC0_IRQ__##v << 0) & 0x1) | ||
| 202 | |||
| 203 | /** | ||
| 204 | * Register: HW_LRADC_CTRL2 | ||
| 205 | * Address: 0x20 | ||
| 206 | * SCT: yes | ||
| 207 | */ | ||
| 208 | #define HW_LRADC_CTRL2 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x0)) | ||
| 209 | #define HW_LRADC_CTRL2_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x4)) | ||
| 210 | #define HW_LRADC_CTRL2_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0x8)) | ||
| 211 | #define HW_LRADC_CTRL2_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x20 + 0xc)) | ||
| 212 | #define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 | ||
| 213 | #define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xff000000 | ||
| 214 | #define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) (((v) << 24) & 0xff000000) | ||
| 215 | #define BP_LRADC_CTRL2_BL_AMP_BYPASS 23 | ||
| 216 | #define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x800000 | ||
| 217 | #define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0 | ||
| 218 | #define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1 | ||
| 219 | #define BF_LRADC_CTRL2_BL_AMP_BYPASS(v) (((v) << 23) & 0x800000) | ||
| 220 | #define BF_LRADC_CTRL2_BL_AMP_BYPASS_V(v) ((BV_LRADC_CTRL2_BL_AMP_BYPASS__##v << 23) & 0x800000) | ||
| 221 | #define BP_LRADC_CTRL2_BL_ENABLE 22 | ||
| 222 | #define BM_LRADC_CTRL2_BL_ENABLE 0x400000 | ||
| 223 | #define BF_LRADC_CTRL2_BL_ENABLE(v) (((v) << 22) & 0x400000) | ||
| 224 | #define BP_LRADC_CTRL2_BL_MUX_SELECT 21 | ||
| 225 | #define BM_LRADC_CTRL2_BL_MUX_SELECT 0x200000 | ||
| 226 | #define BF_LRADC_CTRL2_BL_MUX_SELECT(v) (((v) << 21) & 0x200000) | ||
| 227 | #define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 | ||
| 228 | #define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x1f0000 | ||
| 229 | #define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) (((v) << 16) & 0x1f0000) | ||
| 230 | #define BP_LRADC_CTRL2_TEMPSENSE_PWD 15 | ||
| 231 | #define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x8000 | ||
| 232 | #define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x0 | ||
| 233 | #define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x1 | ||
| 234 | #define BF_LRADC_CTRL2_TEMPSENSE_PWD(v) (((v) << 15) & 0x8000) | ||
| 235 | #define BF_LRADC_CTRL2_TEMPSENSE_PWD_V(v) ((BV_LRADC_CTRL2_TEMPSENSE_PWD__##v << 15) & 0x8000) | ||
| 236 | #define BP_LRADC_CTRL2_EXT_EN1 13 | ||
| 237 | #define BM_LRADC_CTRL2_EXT_EN1 0x2000 | ||
| 238 | #define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0 | ||
| 239 | #define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1 | ||
| 240 | #define BF_LRADC_CTRL2_EXT_EN1(v) (((v) << 13) & 0x2000) | ||
| 241 | #define BF_LRADC_CTRL2_EXT_EN1_V(v) ((BV_LRADC_CTRL2_EXT_EN1__##v << 13) & 0x2000) | ||
| 242 | #define BP_LRADC_CTRL2_EXT_EN0 12 | ||
| 243 | #define BM_LRADC_CTRL2_EXT_EN0 0x1000 | ||
| 244 | #define BF_LRADC_CTRL2_EXT_EN0(v) (((v) << 12) & 0x1000) | ||
| 245 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 9 | ||
| 246 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x200 | ||
| 247 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 | ||
| 248 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 | ||
| 249 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(v) (((v) << 9) & 0x200) | ||
| 250 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE1_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__##v << 9) & 0x200) | ||
| 251 | #define BP_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 8 | ||
| 252 | #define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x100 | ||
| 253 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 | ||
| 254 | #define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 | ||
| 255 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0(v) (((v) << 8) & 0x100) | ||
| 256 | #define BF_LRADC_CTRL2_TEMP_SENSOR_IENABLE0_V(v) ((BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__##v << 8) & 0x100) | ||
| 257 | #define BP_LRADC_CTRL2_TEMP_ISRC1 4 | ||
| 258 | #define BM_LRADC_CTRL2_TEMP_ISRC1 0xf0 | ||
| 259 | #define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xf | ||
| 260 | #define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xe | ||
| 261 | #define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xd | ||
| 262 | #define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xc | ||
| 263 | #define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xb | ||
| 264 | #define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xa | ||
| 265 | #define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 | ||
| 266 | #define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 | ||
| 267 | #define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 | ||
| 268 | #define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 | ||
| 269 | #define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 | ||
| 270 | #define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 | ||
| 271 | #define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 | ||
| 272 | #define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 | ||
| 273 | #define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 | ||
| 274 | #define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 | ||
| 275 | #define BF_LRADC_CTRL2_TEMP_ISRC1(v) (((v) << 4) & 0xf0) | ||
| 276 | #define BF_LRADC_CTRL2_TEMP_ISRC1_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC1__##v << 4) & 0xf0) | ||
| 277 | #define BP_LRADC_CTRL2_TEMP_ISRC0 0 | ||
| 278 | #define BM_LRADC_CTRL2_TEMP_ISRC0 0xf | ||
| 279 | #define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xf | ||
| 280 | #define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xe | ||
| 281 | #define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xd | ||
| 282 | #define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xc | ||
| 283 | #define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xb | ||
| 284 | #define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xa | ||
| 285 | #define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 | ||
| 286 | #define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 | ||
| 287 | #define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 | ||
| 288 | #define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 | ||
| 289 | #define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 | ||
| 290 | #define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 | ||
| 291 | #define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 | ||
| 292 | #define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 | ||
| 293 | #define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 | ||
| 294 | #define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 | ||
| 295 | #define BF_LRADC_CTRL2_TEMP_ISRC0(v) (((v) << 0) & 0xf) | ||
| 296 | #define BF_LRADC_CTRL2_TEMP_ISRC0_V(v) ((BV_LRADC_CTRL2_TEMP_ISRC0__##v << 0) & 0xf) | ||
| 297 | |||
| 298 | /** | ||
| 299 | * Register: HW_LRADC_CTRL3 | ||
| 300 | * Address: 0x30 | ||
| 301 | * SCT: yes | ||
| 302 | */ | ||
| 303 | #define HW_LRADC_CTRL3 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x0)) | ||
| 304 | #define HW_LRADC_CTRL3_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x4)) | ||
| 305 | #define HW_LRADC_CTRL3_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0x8)) | ||
| 306 | #define HW_LRADC_CTRL3_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x30 + 0xc)) | ||
| 307 | #define BP_LRADC_CTRL3_DISCARD 24 | ||
| 308 | #define BM_LRADC_CTRL3_DISCARD 0x3000000 | ||
| 309 | #define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 | ||
| 310 | #define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 | ||
| 311 | #define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 | ||
| 312 | #define BF_LRADC_CTRL3_DISCARD(v) (((v) << 24) & 0x3000000) | ||
| 313 | #define BF_LRADC_CTRL3_DISCARD_V(v) ((BV_LRADC_CTRL3_DISCARD__##v << 24) & 0x3000000) | ||
| 314 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWUP 23 | ||
| 315 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x800000 | ||
| 316 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 | ||
| 317 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 | ||
| 318 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP(v) (((v) << 23) & 0x800000) | ||
| 319 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWUP_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__##v << 23) & 0x800000) | ||
| 320 | #define BP_LRADC_CTRL3_FORCE_ANALOG_PWDN 22 | ||
| 321 | #define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x400000 | ||
| 322 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 | ||
| 323 | #define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 | ||
| 324 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN(v) (((v) << 22) & 0x400000) | ||
| 325 | #define BF_LRADC_CTRL3_FORCE_ANALOG_PWDN_V(v) ((BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__##v << 22) & 0x400000) | ||
| 326 | #define BP_LRADC_CTRL3_CYCLE_TIME 8 | ||
| 327 | #define BM_LRADC_CTRL3_CYCLE_TIME 0x300 | ||
| 328 | #define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 | ||
| 329 | #define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 | ||
| 330 | #define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 | ||
| 331 | #define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 | ||
| 332 | #define BF_LRADC_CTRL3_CYCLE_TIME(v) (((v) << 8) & 0x300) | ||
| 333 | #define BF_LRADC_CTRL3_CYCLE_TIME_V(v) ((BV_LRADC_CTRL3_CYCLE_TIME__##v << 8) & 0x300) | ||
| 334 | #define BP_LRADC_CTRL3_HIGH_TIME 4 | ||
| 335 | #define BM_LRADC_CTRL3_HIGH_TIME 0x30 | ||
| 336 | #define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 | ||
| 337 | #define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 | ||
| 338 | #define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 | ||
| 339 | #define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 | ||
| 340 | #define BF_LRADC_CTRL3_HIGH_TIME(v) (((v) << 4) & 0x30) | ||
| 341 | #define BF_LRADC_CTRL3_HIGH_TIME_V(v) ((BV_LRADC_CTRL3_HIGH_TIME__##v << 4) & 0x30) | ||
| 342 | #define BP_LRADC_CTRL3_DELAY_CLOCK 1 | ||
| 343 | #define BM_LRADC_CTRL3_DELAY_CLOCK 0x2 | ||
| 344 | #define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 | ||
| 345 | #define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 | ||
| 346 | #define BF_LRADC_CTRL3_DELAY_CLOCK(v) (((v) << 1) & 0x2) | ||
| 347 | #define BF_LRADC_CTRL3_DELAY_CLOCK_V(v) ((BV_LRADC_CTRL3_DELAY_CLOCK__##v << 1) & 0x2) | ||
| 348 | #define BP_LRADC_CTRL3_INVERT_CLOCK 0 | ||
| 349 | #define BM_LRADC_CTRL3_INVERT_CLOCK 0x1 | ||
| 350 | #define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 | ||
| 351 | #define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 | ||
| 352 | #define BF_LRADC_CTRL3_INVERT_CLOCK(v) (((v) << 0) & 0x1) | ||
| 353 | #define BF_LRADC_CTRL3_INVERT_CLOCK_V(v) ((BV_LRADC_CTRL3_INVERT_CLOCK__##v << 0) & 0x1) | ||
| 354 | |||
| 355 | /** | ||
| 356 | * Register: HW_LRADC_STATUS | ||
| 357 | * Address: 0x40 | ||
| 358 | * SCT: no | ||
| 359 | */ | ||
| 360 | #define HW_LRADC_STATUS (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x40)) | ||
| 361 | #define BP_LRADC_STATUS_TEMP1_PRESENT 26 | ||
| 362 | #define BM_LRADC_STATUS_TEMP1_PRESENT 0x4000000 | ||
| 363 | #define BF_LRADC_STATUS_TEMP1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
| 364 | #define BP_LRADC_STATUS_TEMP0_PRESENT 25 | ||
| 365 | #define BM_LRADC_STATUS_TEMP0_PRESENT 0x2000000 | ||
| 366 | #define BF_LRADC_STATUS_TEMP0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
| 367 | #define BP_LRADC_STATUS_TOUCH_PANEL_PRESENT 24 | ||
| 368 | #define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x1000000 | ||
| 369 | #define BF_LRADC_STATUS_TOUCH_PANEL_PRESENT(v) (((v) << 24) & 0x1000000) | ||
| 370 | #define BP_LRADC_STATUS_CHANNEL7_PRESENT 23 | ||
| 371 | #define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x800000 | ||
| 372 | #define BF_LRADC_STATUS_CHANNEL7_PRESENT(v) (((v) << 23) & 0x800000) | ||
| 373 | #define BP_LRADC_STATUS_CHANNEL6_PRESENT 22 | ||
| 374 | #define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x400000 | ||
| 375 | #define BF_LRADC_STATUS_CHANNEL6_PRESENT(v) (((v) << 22) & 0x400000) | ||
| 376 | #define BP_LRADC_STATUS_CHANNEL5_PRESENT 21 | ||
| 377 | #define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x200000 | ||
| 378 | #define BF_LRADC_STATUS_CHANNEL5_PRESENT(v) (((v) << 21) & 0x200000) | ||
| 379 | #define BP_LRADC_STATUS_CHANNEL4_PRESENT 20 | ||
| 380 | #define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x100000 | ||
| 381 | #define BF_LRADC_STATUS_CHANNEL4_PRESENT(v) (((v) << 20) & 0x100000) | ||
| 382 | #define BP_LRADC_STATUS_CHANNEL3_PRESENT 19 | ||
| 383 | #define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x80000 | ||
| 384 | #define BF_LRADC_STATUS_CHANNEL3_PRESENT(v) (((v) << 19) & 0x80000) | ||
| 385 | #define BP_LRADC_STATUS_CHANNEL2_PRESENT 18 | ||
| 386 | #define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x40000 | ||
| 387 | #define BF_LRADC_STATUS_CHANNEL2_PRESENT(v) (((v) << 18) & 0x40000) | ||
| 388 | #define BP_LRADC_STATUS_CHANNEL1_PRESENT 17 | ||
| 389 | #define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x20000 | ||
| 390 | #define BF_LRADC_STATUS_CHANNEL1_PRESENT(v) (((v) << 17) & 0x20000) | ||
| 391 | #define BP_LRADC_STATUS_CHANNEL0_PRESENT 16 | ||
| 392 | #define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x10000 | ||
| 393 | #define BF_LRADC_STATUS_CHANNEL0_PRESENT(v) (((v) << 16) & 0x10000) | ||
| 394 | #define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 | ||
| 395 | #define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x1 | ||
| 396 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 | ||
| 397 | #define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 | ||
| 398 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW(v) (((v) << 0) & 0x1) | ||
| 399 | #define BF_LRADC_STATUS_TOUCH_DETECT_RAW_V(v) ((BV_LRADC_STATUS_TOUCH_DETECT_RAW__##v << 0) & 0x1) | ||
| 400 | |||
| 401 | /** | ||
| 402 | * Register: HW_LRADC_CHn | ||
| 403 | * Address: 0x50+n*0x10 | ||
| 404 | * SCT: yes | ||
| 405 | */ | ||
| 406 | #define HW_LRADC_CHn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x0)) | ||
| 407 | #define HW_LRADC_CHn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x4)) | ||
| 408 | #define HW_LRADC_CHn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0x8)) | ||
| 409 | #define HW_LRADC_CHn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x50+(n)*0x10 + 0xc)) | ||
| 410 | #define BP_LRADC_CHn_TOGGLE 31 | ||
| 411 | #define BM_LRADC_CHn_TOGGLE 0x80000000 | ||
| 412 | #define BF_LRADC_CHn_TOGGLE(v) (((v) << 31) & 0x80000000) | ||
| 413 | #define BP_LRADC_CHn_ACCUMULATE 29 | ||
| 414 | #define BM_LRADC_CHn_ACCUMULATE 0x20000000 | ||
| 415 | #define BF_LRADC_CHn_ACCUMULATE(v) (((v) << 29) & 0x20000000) | ||
| 416 | #define BP_LRADC_CHn_NUM_SAMPLES 24 | ||
| 417 | #define BM_LRADC_CHn_NUM_SAMPLES 0x1f000000 | ||
| 418 | #define BF_LRADC_CHn_NUM_SAMPLES(v) (((v) << 24) & 0x1f000000) | ||
| 419 | #define BP_LRADC_CHn_VALUE 0 | ||
| 420 | #define BM_LRADC_CHn_VALUE 0x3ffff | ||
| 421 | #define BF_LRADC_CHn_VALUE(v) (((v) << 0) & 0x3ffff) | ||
| 422 | |||
| 423 | /** | ||
| 424 | * Register: HW_LRADC_DELAYn | ||
| 425 | * Address: 0xd0+n*0x10 | ||
| 426 | * SCT: yes | ||
| 427 | */ | ||
| 428 | #define HW_LRADC_DELAYn(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x0)) | ||
| 429 | #define HW_LRADC_DELAYn_SET(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x4)) | ||
| 430 | #define HW_LRADC_DELAYn_CLR(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0x8)) | ||
| 431 | #define HW_LRADC_DELAYn_TOG(n) (*(volatile unsigned long *)(REGS_LRADC_BASE + 0xd0+(n)*0x10 + 0xc)) | ||
| 432 | #define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 | ||
| 433 | #define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xff000000 | ||
| 434 | #define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) (((v) << 24) & 0xff000000) | ||
| 435 | #define BP_LRADC_DELAYn_KICK 20 | ||
| 436 | #define BM_LRADC_DELAYn_KICK 0x100000 | ||
| 437 | #define BF_LRADC_DELAYn_KICK(v) (((v) << 20) & 0x100000) | ||
| 438 | #define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 | ||
| 439 | #define BM_LRADC_DELAYn_TRIGGER_DELAYS 0xf0000 | ||
| 440 | #define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) (((v) << 16) & 0xf0000) | ||
| 441 | #define BP_LRADC_DELAYn_LOOP_COUNT 11 | ||
| 442 | #define BM_LRADC_DELAYn_LOOP_COUNT 0xf800 | ||
| 443 | #define BF_LRADC_DELAYn_LOOP_COUNT(v) (((v) << 11) & 0xf800) | ||
| 444 | #define BP_LRADC_DELAYn_DELAY 0 | ||
| 445 | #define BM_LRADC_DELAYn_DELAY 0x7ff | ||
| 446 | #define BF_LRADC_DELAYn_DELAY(v) (((v) << 0) & 0x7ff) | ||
| 447 | |||
| 448 | /** | ||
| 449 | * Register: HW_LRADC_DEBUG0 | ||
| 450 | * Address: 0x110 | ||
| 451 | * SCT: no | ||
| 452 | */ | ||
| 453 | #define HW_LRADC_DEBUG0 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x110)) | ||
| 454 | #define BP_LRADC_DEBUG0_READONLY 16 | ||
| 455 | #define BM_LRADC_DEBUG0_READONLY 0xffff0000 | ||
| 456 | #define BF_LRADC_DEBUG0_READONLY(v) (((v) << 16) & 0xffff0000) | ||
| 457 | #define BP_LRADC_DEBUG0_STATE 0 | ||
| 458 | #define BM_LRADC_DEBUG0_STATE 0xfff | ||
| 459 | #define BF_LRADC_DEBUG0_STATE(v) (((v) << 0) & 0xfff) | ||
| 460 | |||
| 461 | /** | ||
| 462 | * Register: HW_LRADC_DEBUG1 | ||
| 463 | * Address: 0x120 | ||
| 464 | * SCT: yes | ||
| 465 | */ | ||
| 466 | #define HW_LRADC_DEBUG1 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x0)) | ||
| 467 | #define HW_LRADC_DEBUG1_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x4)) | ||
| 468 | #define HW_LRADC_DEBUG1_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0x8)) | ||
| 469 | #define HW_LRADC_DEBUG1_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x120 + 0xc)) | ||
| 470 | #define BP_LRADC_DEBUG1_REQUEST 16 | ||
| 471 | #define BM_LRADC_DEBUG1_REQUEST 0xff0000 | ||
| 472 | #define BF_LRADC_DEBUG1_REQUEST(v) (((v) << 16) & 0xff0000) | ||
| 473 | #define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 | ||
| 474 | #define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x1f00 | ||
| 475 | #define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) (((v) << 8) & 0x1f00) | ||
| 476 | #define BP_LRADC_DEBUG1_TESTMODE6 2 | ||
| 477 | #define BM_LRADC_DEBUG1_TESTMODE6 0x4 | ||
| 478 | #define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 | ||
| 479 | #define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 | ||
| 480 | #define BF_LRADC_DEBUG1_TESTMODE6(v) (((v) << 2) & 0x4) | ||
| 481 | #define BF_LRADC_DEBUG1_TESTMODE6_V(v) ((BV_LRADC_DEBUG1_TESTMODE6__##v << 2) & 0x4) | ||
| 482 | #define BP_LRADC_DEBUG1_TESTMODE5 1 | ||
| 483 | #define BM_LRADC_DEBUG1_TESTMODE5 0x2 | ||
| 484 | #define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 | ||
| 485 | #define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 | ||
| 486 | #define BF_LRADC_DEBUG1_TESTMODE5(v) (((v) << 1) & 0x2) | ||
| 487 | #define BF_LRADC_DEBUG1_TESTMODE5_V(v) ((BV_LRADC_DEBUG1_TESTMODE5__##v << 1) & 0x2) | ||
| 488 | #define BP_LRADC_DEBUG1_TESTMODE 0 | ||
| 489 | #define BM_LRADC_DEBUG1_TESTMODE 0x1 | ||
| 490 | #define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 | ||
| 491 | #define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 | ||
| 492 | #define BF_LRADC_DEBUG1_TESTMODE(v) (((v) << 0) & 0x1) | ||
| 493 | #define BF_LRADC_DEBUG1_TESTMODE_V(v) ((BV_LRADC_DEBUG1_TESTMODE__##v << 0) & 0x1) | ||
| 494 | |||
| 495 | /** | ||
| 496 | * Register: HW_LRADC_CONVERSION | ||
| 497 | * Address: 0x130 | ||
| 498 | * SCT: yes | ||
| 499 | */ | ||
| 500 | #define HW_LRADC_CONVERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x0)) | ||
| 501 | #define HW_LRADC_CONVERSION_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x4)) | ||
| 502 | #define HW_LRADC_CONVERSION_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0x8)) | ||
| 503 | #define HW_LRADC_CONVERSION_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x130 + 0xc)) | ||
| 504 | #define BP_LRADC_CONVERSION_AUTOMATIC 20 | ||
| 505 | #define BM_LRADC_CONVERSION_AUTOMATIC 0x100000 | ||
| 506 | #define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 | ||
| 507 | #define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 | ||
| 508 | #define BF_LRADC_CONVERSION_AUTOMATIC(v) (((v) << 20) & 0x100000) | ||
| 509 | #define BF_LRADC_CONVERSION_AUTOMATIC_V(v) ((BV_LRADC_CONVERSION_AUTOMATIC__##v << 20) & 0x100000) | ||
| 510 | #define BP_LRADC_CONVERSION_SCALE_FACTOR 16 | ||
| 511 | #define BM_LRADC_CONVERSION_SCALE_FACTOR 0x30000 | ||
| 512 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 | ||
| 513 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 | ||
| 514 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 | ||
| 515 | #define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 | ||
| 516 | #define BF_LRADC_CONVERSION_SCALE_FACTOR(v) (((v) << 16) & 0x30000) | ||
| 517 | #define BF_LRADC_CONVERSION_SCALE_FACTOR_V(v) ((BV_LRADC_CONVERSION_SCALE_FACTOR__##v << 16) & 0x30000) | ||
| 518 | #define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 | ||
| 519 | #define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x3ff | ||
| 520 | #define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) (((v) << 0) & 0x3ff) | ||
| 521 | |||
| 522 | /** | ||
| 523 | * Register: HW_LRADC_CTRL4 | ||
| 524 | * Address: 0x140 | ||
| 525 | * SCT: yes | ||
| 526 | */ | ||
| 527 | #define HW_LRADC_CTRL4 (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x0)) | ||
| 528 | #define HW_LRADC_CTRL4_SET (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x4)) | ||
| 529 | #define HW_LRADC_CTRL4_CLR (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0x8)) | ||
| 530 | #define HW_LRADC_CTRL4_TOG (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x140 + 0xc)) | ||
| 531 | #define BP_LRADC_CTRL4_LRADC7SELECT 28 | ||
| 532 | #define BM_LRADC_CTRL4_LRADC7SELECT 0xf0000000 | ||
| 533 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 | ||
| 534 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 | ||
| 535 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 | ||
| 536 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 | ||
| 537 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 | ||
| 538 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 | ||
| 539 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 | ||
| 540 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 | ||
| 541 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 | ||
| 542 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 | ||
| 543 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xa | ||
| 544 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xb | ||
| 545 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xc | ||
| 546 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xd | ||
| 547 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xe | ||
| 548 | #define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xf | ||
| 549 | #define BF_LRADC_CTRL4_LRADC7SELECT(v) (((v) << 28) & 0xf0000000) | ||
| 550 | #define BF_LRADC_CTRL4_LRADC7SELECT_V(v) ((BV_LRADC_CTRL4_LRADC7SELECT__##v << 28) & 0xf0000000) | ||
| 551 | #define BP_LRADC_CTRL4_LRADC6SELECT 24 | ||
| 552 | #define BM_LRADC_CTRL4_LRADC6SELECT 0xf000000 | ||
| 553 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 | ||
| 554 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 | ||
| 555 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 | ||
| 556 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 | ||
| 557 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 | ||
| 558 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 | ||
| 559 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 | ||
| 560 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 | ||
| 561 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 | ||
| 562 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 | ||
| 563 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xa | ||
| 564 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xb | ||
| 565 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xc | ||
| 566 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xd | ||
| 567 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xe | ||
| 568 | #define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xf | ||
| 569 | #define BF_LRADC_CTRL4_LRADC6SELECT(v) (((v) << 24) & 0xf000000) | ||
| 570 | #define BF_LRADC_CTRL4_LRADC6SELECT_V(v) ((BV_LRADC_CTRL4_LRADC6SELECT__##v << 24) & 0xf000000) | ||
| 571 | #define BP_LRADC_CTRL4_LRADC5SELECT 20 | ||
| 572 | #define BM_LRADC_CTRL4_LRADC5SELECT 0xf00000 | ||
| 573 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 | ||
| 574 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 | ||
| 575 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 | ||
| 576 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 | ||
| 577 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 | ||
| 578 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 | ||
| 579 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 | ||
| 580 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 | ||
| 581 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 | ||
| 582 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 | ||
| 583 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xa | ||
| 584 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xb | ||
| 585 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xc | ||
| 586 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xd | ||
| 587 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xe | ||
| 588 | #define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xf | ||
| 589 | #define BF_LRADC_CTRL4_LRADC5SELECT(v) (((v) << 20) & 0xf00000) | ||
| 590 | #define BF_LRADC_CTRL4_LRADC5SELECT_V(v) ((BV_LRADC_CTRL4_LRADC5SELECT__##v << 20) & 0xf00000) | ||
| 591 | #define BP_LRADC_CTRL4_LRADC4SELECT 16 | ||
| 592 | #define BM_LRADC_CTRL4_LRADC4SELECT 0xf0000 | ||
| 593 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 | ||
| 594 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 | ||
| 595 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 | ||
| 596 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 | ||
| 597 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 | ||
| 598 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 | ||
| 599 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 | ||
| 600 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 | ||
| 601 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 | ||
| 602 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 | ||
| 603 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xa | ||
| 604 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xb | ||
| 605 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xc | ||
| 606 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xd | ||
| 607 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xe | ||
| 608 | #define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xf | ||
| 609 | #define BF_LRADC_CTRL4_LRADC4SELECT(v) (((v) << 16) & 0xf0000) | ||
| 610 | #define BF_LRADC_CTRL4_LRADC4SELECT_V(v) ((BV_LRADC_CTRL4_LRADC4SELECT__##v << 16) & 0xf0000) | ||
| 611 | #define BP_LRADC_CTRL4_LRADC3SELECT 12 | ||
| 612 | #define BM_LRADC_CTRL4_LRADC3SELECT 0xf000 | ||
| 613 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 | ||
| 614 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 | ||
| 615 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 | ||
| 616 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 | ||
| 617 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 | ||
| 618 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 | ||
| 619 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 | ||
| 620 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 | ||
| 621 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 | ||
| 622 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 | ||
| 623 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xa | ||
| 624 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xb | ||
| 625 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xc | ||
| 626 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xd | ||
| 627 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xe | ||
| 628 | #define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xf | ||
| 629 | #define BF_LRADC_CTRL4_LRADC3SELECT(v) (((v) << 12) & 0xf000) | ||
| 630 | #define BF_LRADC_CTRL4_LRADC3SELECT_V(v) ((BV_LRADC_CTRL4_LRADC3SELECT__##v << 12) & 0xf000) | ||
| 631 | #define BP_LRADC_CTRL4_LRADC2SELECT 8 | ||
| 632 | #define BM_LRADC_CTRL4_LRADC2SELECT 0xf00 | ||
| 633 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 | ||
| 634 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 | ||
| 635 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 | ||
| 636 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 | ||
| 637 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 | ||
| 638 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 | ||
| 639 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 | ||
| 640 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 | ||
| 641 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 | ||
| 642 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 | ||
| 643 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xa | ||
| 644 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xb | ||
| 645 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xc | ||
| 646 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xd | ||
| 647 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xe | ||
| 648 | #define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xf | ||
| 649 | #define BF_LRADC_CTRL4_LRADC2SELECT(v) (((v) << 8) & 0xf00) | ||
| 650 | #define BF_LRADC_CTRL4_LRADC2SELECT_V(v) ((BV_LRADC_CTRL4_LRADC2SELECT__##v << 8) & 0xf00) | ||
| 651 | #define BP_LRADC_CTRL4_LRADC1SELECT 4 | ||
| 652 | #define BM_LRADC_CTRL4_LRADC1SELECT 0xf0 | ||
| 653 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 | ||
| 654 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 | ||
| 655 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 | ||
| 656 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 | ||
| 657 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 | ||
| 658 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 | ||
| 659 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 | ||
| 660 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 | ||
| 661 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 | ||
| 662 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 | ||
| 663 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xa | ||
| 664 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xb | ||
| 665 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xc | ||
| 666 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xd | ||
| 667 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xe | ||
| 668 | #define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xf | ||
| 669 | #define BF_LRADC_CTRL4_LRADC1SELECT(v) (((v) << 4) & 0xf0) | ||
| 670 | #define BF_LRADC_CTRL4_LRADC1SELECT_V(v) ((BV_LRADC_CTRL4_LRADC1SELECT__##v << 4) & 0xf0) | ||
| 671 | #define BP_LRADC_CTRL4_LRADC0SELECT 0 | ||
| 672 | #define BM_LRADC_CTRL4_LRADC0SELECT 0xf | ||
| 673 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 | ||
| 674 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 | ||
| 675 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 | ||
| 676 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 | ||
| 677 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 | ||
| 678 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 | ||
| 679 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 | ||
| 680 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 | ||
| 681 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 | ||
| 682 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 | ||
| 683 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xa | ||
| 684 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xb | ||
| 685 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xc | ||
| 686 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xd | ||
| 687 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xe | ||
| 688 | #define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xf | ||
| 689 | #define BF_LRADC_CTRL4_LRADC0SELECT(v) (((v) << 0) & 0xf) | ||
| 690 | #define BF_LRADC_CTRL4_LRADC0SELECT_V(v) ((BV_LRADC_CTRL4_LRADC0SELECT__##v << 0) & 0xf) | ||
| 691 | |||
| 692 | /** | ||
| 693 | * Register: HW_LRADC_VERSION | ||
| 694 | * Address: 0x150 | ||
| 695 | * SCT: no | ||
| 696 | */ | ||
| 697 | #define HW_LRADC_VERSION (*(volatile unsigned long *)(REGS_LRADC_BASE + 0x150)) | ||
| 698 | #define BP_LRADC_VERSION_MAJOR 24 | ||
| 699 | #define BM_LRADC_VERSION_MAJOR 0xff000000 | ||
| 700 | #define BF_LRADC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 701 | #define BP_LRADC_VERSION_MINOR 16 | ||
| 702 | #define BM_LRADC_VERSION_MINOR 0xff0000 | ||
| 703 | #define BF_LRADC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 704 | #define BP_LRADC_VERSION_STEP 0 | ||
| 705 | #define BM_LRADC_VERSION_STEP 0xffff | ||
| 706 | #define BF_LRADC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 707 | |||
| 708 | #endif /* __HEADERGEN__STMP3700__LRADC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h new file mode 100644 index 0000000000..082952fc95 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ocotp.h | |||
| @@ -0,0 +1,254 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__OCOTP__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__OCOTP__H__ | ||
| 25 | |||
| 26 | #define REGS_OCOTP_BASE (0x8002c000) | ||
| 27 | |||
| 28 | #define REGS_OCOTP_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_OCOTP_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_OCOTP_CTRL (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_OCOTP_CTRL_SET (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_OCOTP_CTRL_CLR (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_OCOTP_CTRL_TOG (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_OCOTP_CTRL_WR_UNLOCK 16 | ||
| 40 | #define BM_OCOTP_CTRL_WR_UNLOCK 0xffff0000 | ||
| 41 | #define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3e77 | ||
| 42 | #define BF_OCOTP_CTRL_WR_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
| 43 | #define BF_OCOTP_CTRL_WR_UNLOCK_V(v) ((BV_OCOTP_CTRL_WR_UNLOCK__##v << 16) & 0xffff0000) | ||
| 44 | #define BP_OCOTP_CTRL_RELOAD_SHADOWS 13 | ||
| 45 | #define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x2000 | ||
| 46 | #define BF_OCOTP_CTRL_RELOAD_SHADOWS(v) (((v) << 13) & 0x2000) | ||
| 47 | #define BP_OCOTP_CTRL_RD_BANK_OPEN 12 | ||
| 48 | #define BM_OCOTP_CTRL_RD_BANK_OPEN 0x1000 | ||
| 49 | #define BF_OCOTP_CTRL_RD_BANK_OPEN(v) (((v) << 12) & 0x1000) | ||
| 50 | #define BP_OCOTP_CTRL_ERROR 9 | ||
| 51 | #define BM_OCOTP_CTRL_ERROR 0x200 | ||
| 52 | #define BF_OCOTP_CTRL_ERROR(v) (((v) << 9) & 0x200) | ||
| 53 | #define BP_OCOTP_CTRL_BUSY 8 | ||
| 54 | #define BM_OCOTP_CTRL_BUSY 0x100 | ||
| 55 | #define BF_OCOTP_CTRL_BUSY(v) (((v) << 8) & 0x100) | ||
| 56 | #define BP_OCOTP_CTRL_ADDR 0 | ||
| 57 | #define BM_OCOTP_CTRL_ADDR 0x1f | ||
| 58 | #define BF_OCOTP_CTRL_ADDR(v) (((v) << 0) & 0x1f) | ||
| 59 | |||
| 60 | /** | ||
| 61 | * Register: HW_OCOTP_DATA | ||
| 62 | * Address: 0x10 | ||
| 63 | * SCT: no | ||
| 64 | */ | ||
| 65 | #define HW_OCOTP_DATA (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x10)) | ||
| 66 | #define BP_OCOTP_DATA_DATA 0 | ||
| 67 | #define BM_OCOTP_DATA_DATA 0xffffffff | ||
| 68 | #define BF_OCOTP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Register: HW_OCOTP_CUSTn | ||
| 72 | * Address: 0x20+n*0x10 | ||
| 73 | * SCT: no | ||
| 74 | */ | ||
| 75 | #define HW_OCOTP_CUSTn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x20+(n)*0x10)) | ||
| 76 | #define BP_OCOTP_CUSTn_BITS 0 | ||
| 77 | #define BM_OCOTP_CUSTn_BITS 0xffffffff | ||
| 78 | #define BF_OCOTP_CUSTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 79 | |||
| 80 | /** | ||
| 81 | * Register: HW_OCOTP_CRYPTOn | ||
| 82 | * Address: 0x60+n*0x10 | ||
| 83 | * SCT: no | ||
| 84 | */ | ||
| 85 | #define HW_OCOTP_CRYPTOn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x60+(n)*0x10)) | ||
| 86 | #define BP_OCOTP_CRYPTOn_BITS 0 | ||
| 87 | #define BM_OCOTP_CRYPTOn_BITS 0xffffffff | ||
| 88 | #define BF_OCOTP_CRYPTOn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 89 | |||
| 90 | /** | ||
| 91 | * Register: HW_OCOTP_HWCAPn | ||
| 92 | * Address: 0xa0+n*0x10 | ||
| 93 | * SCT: no | ||
| 94 | */ | ||
| 95 | #define HW_OCOTP_HWCAPn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0xa0+(n)*0x10)) | ||
| 96 | #define BP_OCOTP_HWCAPn_BITS 0 | ||
| 97 | #define BM_OCOTP_HWCAPn_BITS 0xffffffff | ||
| 98 | #define BF_OCOTP_HWCAPn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 99 | |||
| 100 | /** | ||
| 101 | * Register: HW_OCOTP_SWCAP | ||
| 102 | * Address: 0x100 | ||
| 103 | * SCT: no | ||
| 104 | */ | ||
| 105 | #define HW_OCOTP_SWCAP (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x100)) | ||
| 106 | #define BP_OCOTP_SWCAP_BITS 0 | ||
| 107 | #define BM_OCOTP_SWCAP_BITS 0xffffffff | ||
| 108 | #define BF_OCOTP_SWCAP_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 109 | |||
| 110 | /** | ||
| 111 | * Register: HW_OCOTP_CUSTCAP | ||
| 112 | * Address: 0x110 | ||
| 113 | * SCT: no | ||
| 114 | */ | ||
| 115 | #define HW_OCOTP_CUSTCAP (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x110)) | ||
| 116 | #define BP_OCOTP_CUSTCAP_BITS 0 | ||
| 117 | #define BM_OCOTP_CUSTCAP_BITS 0xffffffff | ||
| 118 | #define BF_OCOTP_CUSTCAP_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 119 | |||
| 120 | /** | ||
| 121 | * Register: HW_OCOTP_LOCK | ||
| 122 | * Address: 0x120 | ||
| 123 | * SCT: no | ||
| 124 | */ | ||
| 125 | #define HW_OCOTP_LOCK (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x120)) | ||
| 126 | #define BP_OCOTP_LOCK_ROM7 31 | ||
| 127 | #define BM_OCOTP_LOCK_ROM7 0x80000000 | ||
| 128 | #define BF_OCOTP_LOCK_ROM7(v) (((v) << 31) & 0x80000000) | ||
| 129 | #define BP_OCOTP_LOCK_ROM6 30 | ||
| 130 | #define BM_OCOTP_LOCK_ROM6 0x40000000 | ||
| 131 | #define BF_OCOTP_LOCK_ROM6(v) (((v) << 30) & 0x40000000) | ||
| 132 | #define BP_OCOTP_LOCK_ROM5 29 | ||
| 133 | #define BM_OCOTP_LOCK_ROM5 0x20000000 | ||
| 134 | #define BF_OCOTP_LOCK_ROM5(v) (((v) << 29) & 0x20000000) | ||
| 135 | #define BP_OCOTP_LOCK_ROM4 28 | ||
| 136 | #define BM_OCOTP_LOCK_ROM4 0x10000000 | ||
| 137 | #define BF_OCOTP_LOCK_ROM4(v) (((v) << 28) & 0x10000000) | ||
| 138 | #define BP_OCOTP_LOCK_ROM3 27 | ||
| 139 | #define BM_OCOTP_LOCK_ROM3 0x8000000 | ||
| 140 | #define BF_OCOTP_LOCK_ROM3(v) (((v) << 27) & 0x8000000) | ||
| 141 | #define BP_OCOTP_LOCK_ROM2 26 | ||
| 142 | #define BM_OCOTP_LOCK_ROM2 0x4000000 | ||
| 143 | #define BF_OCOTP_LOCK_ROM2(v) (((v) << 26) & 0x4000000) | ||
| 144 | #define BP_OCOTP_LOCK_ROM1 25 | ||
| 145 | #define BM_OCOTP_LOCK_ROM1 0x2000000 | ||
| 146 | #define BF_OCOTP_LOCK_ROM1(v) (((v) << 25) & 0x2000000) | ||
| 147 | #define BP_OCOTP_LOCK_ROM0 24 | ||
| 148 | #define BM_OCOTP_LOCK_ROM0 0x1000000 | ||
| 149 | #define BF_OCOTP_LOCK_ROM0(v) (((v) << 24) & 0x1000000) | ||
| 150 | #define BP_OCOTP_LOCK_HWSW_SHADOW_ALT 23 | ||
| 151 | #define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x800000 | ||
| 152 | #define BF_OCOTP_LOCK_HWSW_SHADOW_ALT(v) (((v) << 23) & 0x800000) | ||
| 153 | #define BP_OCOTP_LOCK_CRYPTODCP_ALT 22 | ||
| 154 | #define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x400000 | ||
| 155 | #define BF_OCOTP_LOCK_CRYPTODCP_ALT(v) (((v) << 22) & 0x400000) | ||
| 156 | #define BP_OCOTP_LOCK_CRYPTOKEY_ALT 21 | ||
| 157 | #define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x200000 | ||
| 158 | #define BF_OCOTP_LOCK_CRYPTOKEY_ALT(v) (((v) << 21) & 0x200000) | ||
| 159 | #define BP_OCOTP_LOCK_PIN 20 | ||
| 160 | #define BM_OCOTP_LOCK_PIN 0x100000 | ||
| 161 | #define BF_OCOTP_LOCK_PIN(v) (((v) << 20) & 0x100000) | ||
| 162 | #define BP_OCOTP_LOCK_OPS 19 | ||
| 163 | #define BM_OCOTP_LOCK_OPS 0x80000 | ||
| 164 | #define BF_OCOTP_LOCK_OPS(v) (((v) << 19) & 0x80000) | ||
| 165 | #define BP_OCOTP_LOCK_UN2 18 | ||
| 166 | #define BM_OCOTP_LOCK_UN2 0x40000 | ||
| 167 | #define BF_OCOTP_LOCK_UN2(v) (((v) << 18) & 0x40000) | ||
| 168 | #define BP_OCOTP_LOCK_UN1 17 | ||
| 169 | #define BM_OCOTP_LOCK_UN1 0x20000 | ||
| 170 | #define BF_OCOTP_LOCK_UN1(v) (((v) << 17) & 0x20000) | ||
| 171 | #define BP_OCOTP_LOCK_UN0 16 | ||
| 172 | #define BM_OCOTP_LOCK_UN0 0x10000 | ||
| 173 | #define BF_OCOTP_LOCK_UN0(v) (((v) << 16) & 0x10000) | ||
| 174 | #define BP_OCOTP_LOCK_UNALLOCATED 10 | ||
| 175 | #define BM_OCOTP_LOCK_UNALLOCATED 0xfc00 | ||
| 176 | #define BF_OCOTP_LOCK_UNALLOCATED(v) (((v) << 10) & 0xfc00) | ||
| 177 | #define BP_OCOTP_LOCK_CUSTCAP 9 | ||
| 178 | #define BM_OCOTP_LOCK_CUSTCAP 0x200 | ||
| 179 | #define BF_OCOTP_LOCK_CUSTCAP(v) (((v) << 9) & 0x200) | ||
| 180 | #define BP_OCOTP_LOCK_HWSW 8 | ||
| 181 | #define BM_OCOTP_LOCK_HWSW 0x100 | ||
| 182 | #define BF_OCOTP_LOCK_HWSW(v) (((v) << 8) & 0x100) | ||
| 183 | #define BP_OCOTP_LOCK_CUSTCAP_SHADOW 7 | ||
| 184 | #define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x80 | ||
| 185 | #define BF_OCOTP_LOCK_CUSTCAP_SHADOW(v) (((v) << 7) & 0x80) | ||
| 186 | #define BP_OCOTP_LOCK_HWSW_SHADOW 6 | ||
| 187 | #define BM_OCOTP_LOCK_HWSW_SHADOW 0x40 | ||
| 188 | #define BF_OCOTP_LOCK_HWSW_SHADOW(v) (((v) << 6) & 0x40) | ||
| 189 | #define BP_OCOTP_LOCK_CRYPTODCP 5 | ||
| 190 | #define BM_OCOTP_LOCK_CRYPTODCP 0x20 | ||
| 191 | #define BF_OCOTP_LOCK_CRYPTODCP(v) (((v) << 5) & 0x20) | ||
| 192 | #define BP_OCOTP_LOCK_CRYPTOKEY 4 | ||
| 193 | #define BM_OCOTP_LOCK_CRYPTOKEY 0x10 | ||
| 194 | #define BF_OCOTP_LOCK_CRYPTOKEY(v) (((v) << 4) & 0x10) | ||
| 195 | #define BP_OCOTP_LOCK_CUST3 3 | ||
| 196 | #define BM_OCOTP_LOCK_CUST3 0x8 | ||
| 197 | #define BF_OCOTP_LOCK_CUST3(v) (((v) << 3) & 0x8) | ||
| 198 | #define BP_OCOTP_LOCK_CUST2 2 | ||
| 199 | #define BM_OCOTP_LOCK_CUST2 0x4 | ||
| 200 | #define BF_OCOTP_LOCK_CUST2(v) (((v) << 2) & 0x4) | ||
| 201 | #define BP_OCOTP_LOCK_CUST1 1 | ||
| 202 | #define BM_OCOTP_LOCK_CUST1 0x2 | ||
| 203 | #define BF_OCOTP_LOCK_CUST1(v) (((v) << 1) & 0x2) | ||
| 204 | #define BP_OCOTP_LOCK_CUST0 0 | ||
| 205 | #define BM_OCOTP_LOCK_CUST0 0x1 | ||
| 206 | #define BF_OCOTP_LOCK_CUST0(v) (((v) << 0) & 0x1) | ||
| 207 | |||
| 208 | /** | ||
| 209 | * Register: HW_OCOTP_OPSn | ||
| 210 | * Address: 0x130+n*0x10 | ||
| 211 | * SCT: no | ||
| 212 | */ | ||
| 213 | #define HW_OCOTP_OPSn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x130+(n)*0x10)) | ||
| 214 | #define BP_OCOTP_OPSn_BITS 0 | ||
| 215 | #define BM_OCOTP_OPSn_BITS 0xffffffff | ||
| 216 | #define BF_OCOTP_OPSn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 217 | |||
| 218 | /** | ||
| 219 | * Register: HW_OCOTP_UNn | ||
| 220 | * Address: 0x170+n*0x10 | ||
| 221 | * SCT: no | ||
| 222 | */ | ||
| 223 | #define HW_OCOTP_UNn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x170+(n)*0x10)) | ||
| 224 | #define BP_OCOTP_UNn_BITS 0 | ||
| 225 | #define BM_OCOTP_UNn_BITS 0xffffffff | ||
| 226 | #define BF_OCOTP_UNn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 227 | |||
| 228 | /** | ||
| 229 | * Register: HW_OCOTP_ROMn | ||
| 230 | * Address: 0x1a0+n*0x10 | ||
| 231 | * SCT: no | ||
| 232 | */ | ||
| 233 | #define HW_OCOTP_ROMn(n) (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x1a0+(n)*0x10)) | ||
| 234 | #define BP_OCOTP_ROMn_BITS 0 | ||
| 235 | #define BM_OCOTP_ROMn_BITS 0xffffffff | ||
| 236 | #define BF_OCOTP_ROMn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 237 | |||
| 238 | /** | ||
| 239 | * Register: HW_OCOTP_VERSION | ||
| 240 | * Address: 0x220 | ||
| 241 | * SCT: no | ||
| 242 | */ | ||
| 243 | #define HW_OCOTP_VERSION (*(volatile unsigned long *)(REGS_OCOTP_BASE + 0x220)) | ||
| 244 | #define BP_OCOTP_VERSION_MAJOR 24 | ||
| 245 | #define BM_OCOTP_VERSION_MAJOR 0xff000000 | ||
| 246 | #define BF_OCOTP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 247 | #define BP_OCOTP_VERSION_MINOR 16 | ||
| 248 | #define BM_OCOTP_VERSION_MINOR 0xff0000 | ||
| 249 | #define BF_OCOTP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 250 | #define BP_OCOTP_VERSION_STEP 0 | ||
| 251 | #define BM_OCOTP_VERSION_STEP 0xffff | ||
| 252 | #define BF_OCOTP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 253 | |||
| 254 | #endif /* __HEADERGEN__STMP3700__OCOTP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h new file mode 100644 index 0000000000..bddc2dcfa9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-pinctrl.h | |||
| @@ -0,0 +1,213 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__PINCTRL__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__PINCTRL__H__ | ||
| 25 | |||
| 26 | #define REGS_PINCTRL_BASE (0x80018000) | ||
| 27 | |||
| 28 | #define REGS_PINCTRL_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_PINCTRL_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_PINCTRL_CTRL (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_PINCTRL_CTRL_SET (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_PINCTRL_CTRL_CLR (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_PINCTRL_CTRL_TOG (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_PINCTRL_CTRL_SFTRST 31 | ||
| 40 | #define BM_PINCTRL_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_PINCTRL_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_PINCTRL_CTRL_CLKGATE 30 | ||
| 43 | #define BM_PINCTRL_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_PINCTRL_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_PINCTRL_CTRL_PRESENT3 29 | ||
| 46 | #define BM_PINCTRL_CTRL_PRESENT3 0x20000000 | ||
| 47 | #define BF_PINCTRL_CTRL_PRESENT3(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_PINCTRL_CTRL_PRESENT2 28 | ||
| 49 | #define BM_PINCTRL_CTRL_PRESENT2 0x10000000 | ||
| 50 | #define BF_PINCTRL_CTRL_PRESENT2(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_PINCTRL_CTRL_PRESENT1 27 | ||
| 52 | #define BM_PINCTRL_CTRL_PRESENT1 0x8000000 | ||
| 53 | #define BF_PINCTRL_CTRL_PRESENT1(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_PINCTRL_CTRL_PRESENT0 26 | ||
| 55 | #define BM_PINCTRL_CTRL_PRESENT0 0x4000000 | ||
| 56 | #define BF_PINCTRL_CTRL_PRESENT0(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_PINCTRL_CTRL_IRQOUT3 3 | ||
| 58 | #define BM_PINCTRL_CTRL_IRQOUT3 0x8 | ||
| 59 | #define BF_PINCTRL_CTRL_IRQOUT3(v) (((v) << 3) & 0x8) | ||
| 60 | #define BP_PINCTRL_CTRL_IRQOUT2 2 | ||
| 61 | #define BM_PINCTRL_CTRL_IRQOUT2 0x4 | ||
| 62 | #define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) << 2) & 0x4) | ||
| 63 | #define BP_PINCTRL_CTRL_IRQOUT1 1 | ||
| 64 | #define BM_PINCTRL_CTRL_IRQOUT1 0x2 | ||
| 65 | #define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) << 1) & 0x2) | ||
| 66 | #define BP_PINCTRL_CTRL_IRQOUT0 0 | ||
| 67 | #define BM_PINCTRL_CTRL_IRQOUT0 0x1 | ||
| 68 | #define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) << 0) & 0x1) | ||
| 69 | |||
| 70 | /** | ||
| 71 | * Register: HW_PINCTRL_MUXSELn | ||
| 72 | * Address: 0x100+n*0x10 | ||
| 73 | * SCT: yes | ||
| 74 | */ | ||
| 75 | #define HW_PINCTRL_MUXSELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x0)) | ||
| 76 | #define HW_PINCTRL_MUXSELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x4)) | ||
| 77 | #define HW_PINCTRL_MUXSELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0x8)) | ||
| 78 | #define HW_PINCTRL_MUXSELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x100+(n)*0x10 + 0xc)) | ||
| 79 | #define BP_PINCTRL_MUXSELn_BITS 0 | ||
| 80 | #define BM_PINCTRL_MUXSELn_BITS 0xffffffff | ||
| 81 | #define BF_PINCTRL_MUXSELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 82 | |||
| 83 | /** | ||
| 84 | * Register: HW_PINCTRL_DRIVEn | ||
| 85 | * Address: 0x200+n*0x10 | ||
| 86 | * SCT: yes | ||
| 87 | */ | ||
| 88 | #define HW_PINCTRL_DRIVEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x0)) | ||
| 89 | #define HW_PINCTRL_DRIVEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x4)) | ||
| 90 | #define HW_PINCTRL_DRIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0x8)) | ||
| 91 | #define HW_PINCTRL_DRIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x200+(n)*0x10 + 0xc)) | ||
| 92 | #define BP_PINCTRL_DRIVEn_BITS 0 | ||
| 93 | #define BM_PINCTRL_DRIVEn_BITS 0xffffffff | ||
| 94 | #define BF_PINCTRL_DRIVEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 95 | |||
| 96 | /** | ||
| 97 | * Register: HW_PINCTRL_PULLn | ||
| 98 | * Address: 0x300+n*0x10 | ||
| 99 | * SCT: yes | ||
| 100 | */ | ||
| 101 | #define HW_PINCTRL_PULLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x0)) | ||
| 102 | #define HW_PINCTRL_PULLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x4)) | ||
| 103 | #define HW_PINCTRL_PULLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0x8)) | ||
| 104 | #define HW_PINCTRL_PULLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x300+(n)*0x10 + 0xc)) | ||
| 105 | #define BP_PINCTRL_PULLn_BITS 0 | ||
| 106 | #define BM_PINCTRL_PULLn_BITS 0xffffffff | ||
| 107 | #define BF_PINCTRL_PULLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 108 | |||
| 109 | /** | ||
| 110 | * Register: HW_PINCTRL_DOUTn | ||
| 111 | * Address: 0x400+n*0x10 | ||
| 112 | * SCT: yes | ||
| 113 | */ | ||
| 114 | #define HW_PINCTRL_DOUTn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x0)) | ||
| 115 | #define HW_PINCTRL_DOUTn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x4)) | ||
| 116 | #define HW_PINCTRL_DOUTn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0x8)) | ||
| 117 | #define HW_PINCTRL_DOUTn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x400+(n)*0x10 + 0xc)) | ||
| 118 | #define BP_PINCTRL_DOUTn_BITS 0 | ||
| 119 | #define BM_PINCTRL_DOUTn_BITS 0xffffffff | ||
| 120 | #define BF_PINCTRL_DOUTn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_PINCTRL_DINn | ||
| 124 | * Address: 0x500+n*0x10 | ||
| 125 | * SCT: yes | ||
| 126 | */ | ||
| 127 | #define HW_PINCTRL_DINn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x0)) | ||
| 128 | #define HW_PINCTRL_DINn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x4)) | ||
| 129 | #define HW_PINCTRL_DINn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0x8)) | ||
| 130 | #define HW_PINCTRL_DINn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x500+(n)*0x10 + 0xc)) | ||
| 131 | #define BP_PINCTRL_DINn_BITS 0 | ||
| 132 | #define BM_PINCTRL_DINn_BITS 0xffffffff | ||
| 133 | #define BF_PINCTRL_DINn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 134 | |||
| 135 | /** | ||
| 136 | * Register: HW_PINCTRL_DOEn | ||
| 137 | * Address: 0x600+n*0x10 | ||
| 138 | * SCT: yes | ||
| 139 | */ | ||
| 140 | #define HW_PINCTRL_DOEn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x0)) | ||
| 141 | #define HW_PINCTRL_DOEn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x4)) | ||
| 142 | #define HW_PINCTRL_DOEn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0x8)) | ||
| 143 | #define HW_PINCTRL_DOEn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x600+(n)*0x10 + 0xc)) | ||
| 144 | #define BP_PINCTRL_DOEn_BITS 0 | ||
| 145 | #define BM_PINCTRL_DOEn_BITS 0xffffffff | ||
| 146 | #define BF_PINCTRL_DOEn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 147 | |||
| 148 | /** | ||
| 149 | * Register: HW_PINCTRL_PIN2IRQn | ||
| 150 | * Address: 0x700+n*0x10 | ||
| 151 | * SCT: yes | ||
| 152 | */ | ||
| 153 | #define HW_PINCTRL_PIN2IRQn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x0)) | ||
| 154 | #define HW_PINCTRL_PIN2IRQn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x4)) | ||
| 155 | #define HW_PINCTRL_PIN2IRQn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0x8)) | ||
| 156 | #define HW_PINCTRL_PIN2IRQn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x700+(n)*0x10 + 0xc)) | ||
| 157 | #define BP_PINCTRL_PIN2IRQn_BITS 0 | ||
| 158 | #define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff | ||
| 159 | #define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 160 | |||
| 161 | /** | ||
| 162 | * Register: HW_PINCTRL_IRQENn | ||
| 163 | * Address: 0x800+n*0x10 | ||
| 164 | * SCT: yes | ||
| 165 | */ | ||
| 166 | #define HW_PINCTRL_IRQENn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x0)) | ||
| 167 | #define HW_PINCTRL_IRQENn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x4)) | ||
| 168 | #define HW_PINCTRL_IRQENn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0x8)) | ||
| 169 | #define HW_PINCTRL_IRQENn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x800+(n)*0x10 + 0xc)) | ||
| 170 | #define BP_PINCTRL_IRQENn_BITS 0 | ||
| 171 | #define BM_PINCTRL_IRQENn_BITS 0xffffffff | ||
| 172 | #define BF_PINCTRL_IRQENn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 173 | |||
| 174 | /** | ||
| 175 | * Register: HW_PINCTRL_IRQLEVELn | ||
| 176 | * Address: 0x900+n*0x10 | ||
| 177 | * SCT: yes | ||
| 178 | */ | ||
| 179 | #define HW_PINCTRL_IRQLEVELn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x0)) | ||
| 180 | #define HW_PINCTRL_IRQLEVELn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x4)) | ||
| 181 | #define HW_PINCTRL_IRQLEVELn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0x8)) | ||
| 182 | #define HW_PINCTRL_IRQLEVELn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0x900+(n)*0x10 + 0xc)) | ||
| 183 | #define BP_PINCTRL_IRQLEVELn_BITS 0 | ||
| 184 | #define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff | ||
| 185 | #define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 186 | |||
| 187 | /** | ||
| 188 | * Register: HW_PINCTRL_IRQPOLn | ||
| 189 | * Address: 0xa00+n*0x10 | ||
| 190 | * SCT: yes | ||
| 191 | */ | ||
| 192 | #define HW_PINCTRL_IRQPOLn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x0)) | ||
| 193 | #define HW_PINCTRL_IRQPOLn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x4)) | ||
| 194 | #define HW_PINCTRL_IRQPOLn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0x8)) | ||
| 195 | #define HW_PINCTRL_IRQPOLn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xa00+(n)*0x10 + 0xc)) | ||
| 196 | #define BP_PINCTRL_IRQPOLn_BITS 0 | ||
| 197 | #define BM_PINCTRL_IRQPOLn_BITS 0xffffffff | ||
| 198 | #define BF_PINCTRL_IRQPOLn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 199 | |||
| 200 | /** | ||
| 201 | * Register: HW_PINCTRL_IRQSTATn | ||
| 202 | * Address: 0xb00+n*0x10 | ||
| 203 | * SCT: yes | ||
| 204 | */ | ||
| 205 | #define HW_PINCTRL_IRQSTATn(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x0)) | ||
| 206 | #define HW_PINCTRL_IRQSTATn_SET(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x4)) | ||
| 207 | #define HW_PINCTRL_IRQSTATn_CLR(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0x8)) | ||
| 208 | #define HW_PINCTRL_IRQSTATn_TOG(n) (*(volatile unsigned long *)(REGS_PINCTRL_BASE + 0xb00+(n)*0x10 + 0xc)) | ||
| 209 | #define BP_PINCTRL_IRQSTATn_BITS 0 | ||
| 210 | #define BM_PINCTRL_IRQSTATn_BITS 0xffffffff | ||
| 211 | #define BF_PINCTRL_IRQSTATn_BITS(v) (((v) << 0) & 0xffffffff) | ||
| 212 | |||
| 213 | #endif /* __HEADERGEN__STMP3700__PINCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-power.h b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h new file mode 100644 index 0000000000..85116c79cb --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-power.h | |||
| @@ -0,0 +1,581 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__POWER__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__POWER__H__ | ||
| 25 | |||
| 26 | #define REGS_POWER_BASE (0x80044000) | ||
| 27 | |||
| 28 | #define REGS_POWER_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_POWER_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_POWER_CTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_POWER_CTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_POWER_CTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_POWER_CTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_POWER_CTRL_CLKGATE 30 | ||
| 40 | #define BM_POWER_CTRL_CLKGATE 0x40000000 | ||
| 41 | #define BF_POWER_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 42 | #define BP_POWER_CTRL_PSWITCH_IRQ 22 | ||
| 43 | #define BM_POWER_CTRL_PSWITCH_IRQ 0x400000 | ||
| 44 | #define BF_POWER_CTRL_PSWITCH_IRQ(v) (((v) << 22) & 0x400000) | ||
| 45 | #define BP_POWER_CTRL_PSWITCH_IRQ_SRC 21 | ||
| 46 | #define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x200000 | ||
| 47 | #define BF_POWER_CTRL_PSWITCH_IRQ_SRC(v) (((v) << 21) & 0x200000) | ||
| 48 | #define BP_POWER_CTRL_POLARITY_PSWITCH 20 | ||
| 49 | #define BM_POWER_CTRL_POLARITY_PSWITCH 0x100000 | ||
| 50 | #define BF_POWER_CTRL_POLARITY_PSWITCH(v) (((v) << 20) & 0x100000) | ||
| 51 | #define BP_POWER_CTRL_ENIRQ_PSWITCH 19 | ||
| 52 | #define BM_POWER_CTRL_ENIRQ_PSWITCH 0x80000 | ||
| 53 | #define BF_POWER_CTRL_ENIRQ_PSWITCH(v) (((v) << 19) & 0x80000) | ||
| 54 | #define BP_POWER_CTRL_POLARITY_LINREG_OK 18 | ||
| 55 | #define BM_POWER_CTRL_POLARITY_LINREG_OK 0x40000 | ||
| 56 | #define BF_POWER_CTRL_POLARITY_LINREG_OK(v) (((v) << 18) & 0x40000) | ||
| 57 | #define BP_POWER_CTRL_LINREG_OK_IRQ 17 | ||
| 58 | #define BM_POWER_CTRL_LINREG_OK_IRQ 0x20000 | ||
| 59 | #define BF_POWER_CTRL_LINREG_OK_IRQ(v) (((v) << 17) & 0x20000) | ||
| 60 | #define BP_POWER_CTRL_ENIRQ_LINREG_OK 16 | ||
| 61 | #define BM_POWER_CTRL_ENIRQ_LINREG_OK 0x10000 | ||
| 62 | #define BF_POWER_CTRL_ENIRQ_LINREG_OK(v) (((v) << 16) & 0x10000) | ||
| 63 | #define BP_POWER_CTRL_DC_OK_IRQ 15 | ||
| 64 | #define BM_POWER_CTRL_DC_OK_IRQ 0x8000 | ||
| 65 | #define BF_POWER_CTRL_DC_OK_IRQ(v) (((v) << 15) & 0x8000) | ||
| 66 | #define BP_POWER_CTRL_ENIRQ_DC_OK 14 | ||
| 67 | #define BM_POWER_CTRL_ENIRQ_DC_OK 0x4000 | ||
| 68 | #define BF_POWER_CTRL_ENIRQ_DC_OK(v) (((v) << 14) & 0x4000) | ||
| 69 | #define BP_POWER_CTRL_BATT_BO_IRQ 13 | ||
| 70 | #define BM_POWER_CTRL_BATT_BO_IRQ 0x2000 | ||
| 71 | #define BF_POWER_CTRL_BATT_BO_IRQ(v) (((v) << 13) & 0x2000) | ||
| 72 | #define BP_POWER_CTRL_ENIRQBATT_BO 12 | ||
| 73 | #define BM_POWER_CTRL_ENIRQBATT_BO 0x1000 | ||
| 74 | #define BF_POWER_CTRL_ENIRQBATT_BO(v) (((v) << 12) & 0x1000) | ||
| 75 | #define BP_POWER_CTRL_VDDIO_BO_IRQ 11 | ||
| 76 | #define BM_POWER_CTRL_VDDIO_BO_IRQ 0x800 | ||
| 77 | #define BF_POWER_CTRL_VDDIO_BO_IRQ(v) (((v) << 11) & 0x800) | ||
| 78 | #define BP_POWER_CTRL_ENIRQ_VDDIO_BO 10 | ||
| 79 | #define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x400 | ||
| 80 | #define BF_POWER_CTRL_ENIRQ_VDDIO_BO(v) (((v) << 10) & 0x400) | ||
| 81 | #define BP_POWER_CTRL_VDDA_BO_IRQ 9 | ||
| 82 | #define BM_POWER_CTRL_VDDA_BO_IRQ 0x200 | ||
| 83 | #define BF_POWER_CTRL_VDDA_BO_IRQ(v) (((v) << 9) & 0x200) | ||
| 84 | #define BP_POWER_CTRL_ENIRQ_VDDA_BO 8 | ||
| 85 | #define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x100 | ||
| 86 | #define BF_POWER_CTRL_ENIRQ_VDDA_BO(v) (((v) << 8) & 0x100) | ||
| 87 | #define BP_POWER_CTRL_VDDD_BO_IRQ 7 | ||
| 88 | #define BM_POWER_CTRL_VDDD_BO_IRQ 0x80 | ||
| 89 | #define BF_POWER_CTRL_VDDD_BO_IRQ(v) (((v) << 7) & 0x80) | ||
| 90 | #define BP_POWER_CTRL_ENIRQ_VDDD_BO 6 | ||
| 91 | #define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x40 | ||
| 92 | #define BF_POWER_CTRL_ENIRQ_VDDD_BO(v) (((v) << 6) & 0x40) | ||
| 93 | #define BP_POWER_CTRL_POLARITY_VBUSVALID 5 | ||
| 94 | #define BM_POWER_CTRL_POLARITY_VBUSVALID 0x20 | ||
| 95 | #define BF_POWER_CTRL_POLARITY_VBUSVALID(v) (((v) << 5) & 0x20) | ||
| 96 | #define BP_POWER_CTRL_VBUSVALID_IRQ 4 | ||
| 97 | #define BM_POWER_CTRL_VBUSVALID_IRQ 0x10 | ||
| 98 | #define BF_POWER_CTRL_VBUSVALID_IRQ(v) (((v) << 4) & 0x10) | ||
| 99 | #define BP_POWER_CTRL_ENIRQ_VBUS_VALID 3 | ||
| 100 | #define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x8 | ||
| 101 | #define BF_POWER_CTRL_ENIRQ_VBUS_VALID(v) (((v) << 3) & 0x8) | ||
| 102 | #define BP_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 2 | ||
| 103 | #define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x4 | ||
| 104 | #define BF_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO(v) (((v) << 2) & 0x4) | ||
| 105 | #define BP_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 1 | ||
| 106 | #define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x2 | ||
| 107 | #define BF_POWER_CTRL_VDD5V_GT_VDDIO_IRQ(v) (((v) << 1) & 0x2) | ||
| 108 | #define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 | ||
| 109 | #define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x1 | ||
| 110 | #define BF_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO(v) (((v) << 0) & 0x1) | ||
| 111 | |||
| 112 | /** | ||
| 113 | * Register: HW_POWER_5VCTRL | ||
| 114 | * Address: 0x10 | ||
| 115 | * SCT: yes | ||
| 116 | */ | ||
| 117 | #define HW_POWER_5VCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x0)) | ||
| 118 | #define HW_POWER_5VCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x4)) | ||
| 119 | #define HW_POWER_5VCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0x8)) | ||
| 120 | #define HW_POWER_5VCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x10 + 0xc)) | ||
| 121 | #define BP_POWER_5VCTRL_VBUSVALID_TRSH 10 | ||
| 122 | #define BM_POWER_5VCTRL_VBUSVALID_TRSH 0xc00 | ||
| 123 | #define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) (((v) << 10) & 0xc00) | ||
| 124 | #define BP_POWER_5VCTRL_PWDN_5VBRNOUT 8 | ||
| 125 | #define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x100 | ||
| 126 | #define BF_POWER_5VCTRL_PWDN_5VBRNOUT(v) (((v) << 8) & 0x100) | ||
| 127 | #define BP_POWER_5VCTRL_ENABLE_ILIMIT 7 | ||
| 128 | #define BM_POWER_5VCTRL_ENABLE_ILIMIT 0x80 | ||
| 129 | #define BF_POWER_5VCTRL_ENABLE_ILIMIT(v) (((v) << 7) & 0x80) | ||
| 130 | #define BP_POWER_5VCTRL_DCDC_XFER 6 | ||
| 131 | #define BM_POWER_5VCTRL_DCDC_XFER 0x40 | ||
| 132 | #define BF_POWER_5VCTRL_DCDC_XFER(v) (((v) << 6) & 0x40) | ||
| 133 | #define BP_POWER_5VCTRL_EN_BATT_PULLDN 5 | ||
| 134 | #define BM_POWER_5VCTRL_EN_BATT_PULLDN 0x20 | ||
| 135 | #define BF_POWER_5VCTRL_EN_BATT_PULLDN(v) (((v) << 5) & 0x20) | ||
| 136 | #define BP_POWER_5VCTRL_VBUSVALID_5VDETECT 4 | ||
| 137 | #define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x10 | ||
| 138 | #define BF_POWER_5VCTRL_VBUSVALID_5VDETECT(v) (((v) << 4) & 0x10) | ||
| 139 | #define BP_POWER_5VCTRL_VBUSVALID_TO_B 3 | ||
| 140 | #define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x8 | ||
| 141 | #define BF_POWER_5VCTRL_VBUSVALID_TO_B(v) (((v) << 3) & 0x8) | ||
| 142 | #define BP_POWER_5VCTRL_ILIMIT_EQ_ZERO 2 | ||
| 143 | #define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x4 | ||
| 144 | #define BF_POWER_5VCTRL_ILIMIT_EQ_ZERO(v) (((v) << 2) & 0x4) | ||
| 145 | #define BP_POWER_5VCTRL_OTG_PWRUP_CMPS 1 | ||
| 146 | #define BM_POWER_5VCTRL_OTG_PWRUP_CMPS 0x2 | ||
| 147 | #define BF_POWER_5VCTRL_OTG_PWRUP_CMPS(v) (((v) << 1) & 0x2) | ||
| 148 | #define BP_POWER_5VCTRL_ENABLE_DCDC 0 | ||
| 149 | #define BM_POWER_5VCTRL_ENABLE_DCDC 0x1 | ||
| 150 | #define BF_POWER_5VCTRL_ENABLE_DCDC(v) (((v) << 0) & 0x1) | ||
| 151 | |||
| 152 | /** | ||
| 153 | * Register: HW_POWER_MINPWR | ||
| 154 | * Address: 0x20 | ||
| 155 | * SCT: yes | ||
| 156 | */ | ||
| 157 | #define HW_POWER_MINPWR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x0)) | ||
| 158 | #define HW_POWER_MINPWR_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x4)) | ||
| 159 | #define HW_POWER_MINPWR_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0x8)) | ||
| 160 | #define HW_POWER_MINPWR_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x20 + 0xc)) | ||
| 161 | #define BP_POWER_MINPWR_PWD_BO 11 | ||
| 162 | #define BM_POWER_MINPWR_PWD_BO 0x800 | ||
| 163 | #define BF_POWER_MINPWR_PWD_BO(v) (((v) << 11) & 0x800) | ||
| 164 | #define BP_POWER_MINPWR_USB_I_SUSPEND 10 | ||
| 165 | #define BM_POWER_MINPWR_USB_I_SUSPEND 0x400 | ||
| 166 | #define BF_POWER_MINPWR_USB_I_SUSPEND(v) (((v) << 10) & 0x400) | ||
| 167 | #define BP_POWER_MINPWR_ENABLE_OSC 9 | ||
| 168 | #define BM_POWER_MINPWR_ENABLE_OSC 0x200 | ||
| 169 | #define BF_POWER_MINPWR_ENABLE_OSC(v) (((v) << 9) & 0x200) | ||
| 170 | #define BP_POWER_MINPWR_SELECT_OSC 8 | ||
| 171 | #define BM_POWER_MINPWR_SELECT_OSC 0x100 | ||
| 172 | #define BF_POWER_MINPWR_SELECT_OSC(v) (((v) << 8) & 0x100) | ||
| 173 | #define BP_POWER_MINPWR_VBG_OFF 7 | ||
| 174 | #define BM_POWER_MINPWR_VBG_OFF 0x80 | ||
| 175 | #define BF_POWER_MINPWR_VBG_OFF(v) (((v) << 7) & 0x80) | ||
| 176 | #define BP_POWER_MINPWR_DOUBLE_FETS 6 | ||
| 177 | #define BM_POWER_MINPWR_DOUBLE_FETS 0x40 | ||
| 178 | #define BF_POWER_MINPWR_DOUBLE_FETS(v) (((v) << 6) & 0x40) | ||
| 179 | #define BP_POWER_MINPWR_HALF_FETS 5 | ||
| 180 | #define BM_POWER_MINPWR_HALF_FETS 0x20 | ||
| 181 | #define BF_POWER_MINPWR_HALF_FETS(v) (((v) << 5) & 0x20) | ||
| 182 | #define BP_POWER_MINPWR_LESSANA_I 4 | ||
| 183 | #define BM_POWER_MINPWR_LESSANA_I 0x10 | ||
| 184 | #define BF_POWER_MINPWR_LESSANA_I(v) (((v) << 4) & 0x10) | ||
| 185 | #define BP_POWER_MINPWR_PWD_XTAL24 3 | ||
| 186 | #define BM_POWER_MINPWR_PWD_XTAL24 0x8 | ||
| 187 | #define BF_POWER_MINPWR_PWD_XTAL24(v) (((v) << 3) & 0x8) | ||
| 188 | #define BP_POWER_MINPWR_DC_STOPCLK 2 | ||
| 189 | #define BM_POWER_MINPWR_DC_STOPCLK 0x4 | ||
| 190 | #define BF_POWER_MINPWR_DC_STOPCLK(v) (((v) << 2) & 0x4) | ||
| 191 | #define BP_POWER_MINPWR_EN_DC_PFM 1 | ||
| 192 | #define BM_POWER_MINPWR_EN_DC_PFM 0x2 | ||
| 193 | #define BF_POWER_MINPWR_EN_DC_PFM(v) (((v) << 1) & 0x2) | ||
| 194 | #define BP_POWER_MINPWR_DC_HALFCLK 0 | ||
| 195 | #define BM_POWER_MINPWR_DC_HALFCLK 0x1 | ||
| 196 | #define BF_POWER_MINPWR_DC_HALFCLK(v) (((v) << 0) & 0x1) | ||
| 197 | |||
| 198 | /** | ||
| 199 | * Register: HW_POWER_CHARGE | ||
| 200 | * Address: 0x30 | ||
| 201 | * SCT: yes | ||
| 202 | */ | ||
| 203 | #define HW_POWER_CHARGE (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x0)) | ||
| 204 | #define HW_POWER_CHARGE_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x4)) | ||
| 205 | #define HW_POWER_CHARGE_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0x8)) | ||
| 206 | #define HW_POWER_CHARGE_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x30 + 0xc)) | ||
| 207 | #define BP_POWER_CHARGE_ENABLE_FAULT_DETECT 20 | ||
| 208 | #define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x100000 | ||
| 209 | #define BF_POWER_CHARGE_ENABLE_FAULT_DETECT(v) (((v) << 20) & 0x100000) | ||
| 210 | #define BP_POWER_CHARGE_CHRG_STS_OFF 19 | ||
| 211 | #define BM_POWER_CHARGE_CHRG_STS_OFF 0x80000 | ||
| 212 | #define BF_POWER_CHARGE_CHRG_STS_OFF(v) (((v) << 19) & 0x80000) | ||
| 213 | #define BP_POWER_CHARGE_USE_EXTERN_R 17 | ||
| 214 | #define BM_POWER_CHARGE_USE_EXTERN_R 0x20000 | ||
| 215 | #define BF_POWER_CHARGE_USE_EXTERN_R(v) (((v) << 17) & 0x20000) | ||
| 216 | #define BP_POWER_CHARGE_PWD_BATTCHRG 16 | ||
| 217 | #define BM_POWER_CHARGE_PWD_BATTCHRG 0x10000 | ||
| 218 | #define BF_POWER_CHARGE_PWD_BATTCHRG(v) (((v) << 16) & 0x10000) | ||
| 219 | #define BP_POWER_CHARGE_STOP_ILIMIT 8 | ||
| 220 | #define BM_POWER_CHARGE_STOP_ILIMIT 0xf00 | ||
| 221 | #define BF_POWER_CHARGE_STOP_ILIMIT(v) (((v) << 8) & 0xf00) | ||
| 222 | #define BP_POWER_CHARGE_BATTCHRG_I 0 | ||
| 223 | #define BM_POWER_CHARGE_BATTCHRG_I 0x3f | ||
| 224 | #define BF_POWER_CHARGE_BATTCHRG_I(v) (((v) << 0) & 0x3f) | ||
| 225 | |||
| 226 | /** | ||
| 227 | * Register: HW_POWER_VDDDCTRL | ||
| 228 | * Address: 0x40 | ||
| 229 | * SCT: no | ||
| 230 | */ | ||
| 231 | #define HW_POWER_VDDDCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x40)) | ||
| 232 | #define BP_POWER_VDDDCTRL_ADJTN 28 | ||
| 233 | #define BM_POWER_VDDDCTRL_ADJTN 0xf0000000 | ||
| 234 | #define BF_POWER_VDDDCTRL_ADJTN(v) (((v) << 28) & 0xf0000000) | ||
| 235 | #define BP_POWER_VDDDCTRL_ALKALINE_CHARGE 24 | ||
| 236 | #define BM_POWER_VDDDCTRL_ALKALINE_CHARGE 0x1000000 | ||
| 237 | #define BF_POWER_VDDDCTRL_ALKALINE_CHARGE(v) (((v) << 24) & 0x1000000) | ||
| 238 | #define BP_POWER_VDDDCTRL_DISABLE_STEPPING 23 | ||
| 239 | #define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x800000 | ||
| 240 | #define BF_POWER_VDDDCTRL_DISABLE_STEPPING(v) (((v) << 23) & 0x800000) | ||
| 241 | #define BP_POWER_VDDDCTRL_LINREG_FROM_BATT 22 | ||
| 242 | #define BM_POWER_VDDDCTRL_LINREG_FROM_BATT 0x400000 | ||
| 243 | #define BF_POWER_VDDDCTRL_LINREG_FROM_BATT(v) (((v) << 22) & 0x400000) | ||
| 244 | #define BP_POWER_VDDDCTRL_ENABLE_LINREG 21 | ||
| 245 | #define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x200000 | ||
| 246 | #define BF_POWER_VDDDCTRL_ENABLE_LINREG(v) (((v) << 21) & 0x200000) | ||
| 247 | #define BP_POWER_VDDDCTRL_DISABLE_FET 20 | ||
| 248 | #define BM_POWER_VDDDCTRL_DISABLE_FET 0x100000 | ||
| 249 | #define BF_POWER_VDDDCTRL_DISABLE_FET(v) (((v) << 20) & 0x100000) | ||
| 250 | #define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 | ||
| 251 | #define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x30000 | ||
| 252 | #define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) (((v) << 16) & 0x30000) | ||
| 253 | #define BP_POWER_VDDDCTRL_BO_OFFSET 8 | ||
| 254 | #define BM_POWER_VDDDCTRL_BO_OFFSET 0x700 | ||
| 255 | #define BF_POWER_VDDDCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
| 256 | #define BP_POWER_VDDDCTRL_TRG 0 | ||
| 257 | #define BM_POWER_VDDDCTRL_TRG 0x1f | ||
| 258 | #define BF_POWER_VDDDCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
| 259 | |||
| 260 | /** | ||
| 261 | * Register: HW_POWER_VDDACTRL | ||
| 262 | * Address: 0x50 | ||
| 263 | * SCT: no | ||
| 264 | */ | ||
| 265 | #define HW_POWER_VDDACTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x50)) | ||
| 266 | #define BP_POWER_VDDACTRL_DISABLE_STEPPING 18 | ||
| 267 | #define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x40000 | ||
| 268 | #define BF_POWER_VDDACTRL_DISABLE_STEPPING(v) (((v) << 18) & 0x40000) | ||
| 269 | #define BP_POWER_VDDACTRL_ENABLE_LINREG 17 | ||
| 270 | #define BM_POWER_VDDACTRL_ENABLE_LINREG 0x20000 | ||
| 271 | #define BF_POWER_VDDACTRL_ENABLE_LINREG(v) (((v) << 17) & 0x20000) | ||
| 272 | #define BP_POWER_VDDACTRL_DISABLE_FET 16 | ||
| 273 | #define BM_POWER_VDDACTRL_DISABLE_FET 0x10000 | ||
| 274 | #define BF_POWER_VDDACTRL_DISABLE_FET(v) (((v) << 16) & 0x10000) | ||
| 275 | #define BP_POWER_VDDACTRL_LINREG_OFFSET 12 | ||
| 276 | #define BM_POWER_VDDACTRL_LINREG_OFFSET 0x3000 | ||
| 277 | #define BF_POWER_VDDACTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
| 278 | #define BP_POWER_VDDACTRL_BO_OFFSET 8 | ||
| 279 | #define BM_POWER_VDDACTRL_BO_OFFSET 0x700 | ||
| 280 | #define BF_POWER_VDDACTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
| 281 | #define BP_POWER_VDDACTRL_TRG 0 | ||
| 282 | #define BM_POWER_VDDACTRL_TRG 0x1f | ||
| 283 | #define BF_POWER_VDDACTRL_TRG(v) (((v) << 0) & 0x1f) | ||
| 284 | |||
| 285 | /** | ||
| 286 | * Register: HW_POWER_VDDIOCTRL | ||
| 287 | * Address: 0x60 | ||
| 288 | * SCT: no | ||
| 289 | */ | ||
| 290 | #define HW_POWER_VDDIOCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x60)) | ||
| 291 | #define BP_POWER_VDDIOCTRL_ADJTN 16 | ||
| 292 | #define BM_POWER_VDDIOCTRL_ADJTN 0xf0000 | ||
| 293 | #define BF_POWER_VDDIOCTRL_ADJTN(v) (((v) << 16) & 0xf0000) | ||
| 294 | #define BP_POWER_VDDIOCTRL_DISABLE_STEPPING 15 | ||
| 295 | #define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x8000 | ||
| 296 | #define BF_POWER_VDDIOCTRL_DISABLE_STEPPING(v) (((v) << 15) & 0x8000) | ||
| 297 | #define BP_POWER_VDDIOCTRL_DISABLE_FET 14 | ||
| 298 | #define BM_POWER_VDDIOCTRL_DISABLE_FET 0x4000 | ||
| 299 | #define BF_POWER_VDDIOCTRL_DISABLE_FET(v) (((v) << 14) & 0x4000) | ||
| 300 | #define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 | ||
| 301 | #define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x3000 | ||
| 302 | #define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) (((v) << 12) & 0x3000) | ||
| 303 | #define BP_POWER_VDDIOCTRL_BO_OFFSET 8 | ||
| 304 | #define BM_POWER_VDDIOCTRL_BO_OFFSET 0x700 | ||
| 305 | #define BF_POWER_VDDIOCTRL_BO_OFFSET(v) (((v) << 8) & 0x700) | ||
| 306 | #define BP_POWER_VDDIOCTRL_TRG 0 | ||
| 307 | #define BM_POWER_VDDIOCTRL_TRG 0x1f | ||
| 308 | #define BF_POWER_VDDIOCTRL_TRG(v) (((v) << 0) & 0x1f) | ||
| 309 | |||
| 310 | /** | ||
| 311 | * Register: HW_POWER_DCFUNCV | ||
| 312 | * Address: 0x70 | ||
| 313 | * SCT: no | ||
| 314 | */ | ||
| 315 | #define HW_POWER_DCFUNCV (*(volatile unsigned long *)(REGS_POWER_BASE + 0x70)) | ||
| 316 | #define BP_POWER_DCFUNCV_VDDD 16 | ||
| 317 | #define BM_POWER_DCFUNCV_VDDD 0x3ff0000 | ||
| 318 | #define BF_POWER_DCFUNCV_VDDD(v) (((v) << 16) & 0x3ff0000) | ||
| 319 | #define BP_POWER_DCFUNCV_VDDIO 0 | ||
| 320 | #define BM_POWER_DCFUNCV_VDDIO 0x3ff | ||
| 321 | #define BF_POWER_DCFUNCV_VDDIO(v) (((v) << 0) & 0x3ff) | ||
| 322 | |||
| 323 | /** | ||
| 324 | * Register: HW_POWER_MISC | ||
| 325 | * Address: 0x80 | ||
| 326 | * SCT: no | ||
| 327 | */ | ||
| 328 | #define HW_POWER_MISC (*(volatile unsigned long *)(REGS_POWER_BASE + 0x80)) | ||
| 329 | #define BP_POWER_MISC_FREQSEL 4 | ||
| 330 | #define BM_POWER_MISC_FREQSEL 0x30 | ||
| 331 | #define BF_POWER_MISC_FREQSEL(v) (((v) << 4) & 0x30) | ||
| 332 | #define BP_POWER_MISC_DELAY_TIMING 3 | ||
| 333 | #define BM_POWER_MISC_DELAY_TIMING 0x8 | ||
| 334 | #define BF_POWER_MISC_DELAY_TIMING(v) (((v) << 3) & 0x8) | ||
| 335 | #define BP_POWER_MISC_TEST 2 | ||
| 336 | #define BM_POWER_MISC_TEST 0x4 | ||
| 337 | #define BF_POWER_MISC_TEST(v) (((v) << 2) & 0x4) | ||
| 338 | #define BP_POWER_MISC_SEL_PLLCLK 1 | ||
| 339 | #define BM_POWER_MISC_SEL_PLLCLK 0x2 | ||
| 340 | #define BF_POWER_MISC_SEL_PLLCLK(v) (((v) << 1) & 0x2) | ||
| 341 | #define BP_POWER_MISC_PERIPHERALSWOFF 0 | ||
| 342 | #define BM_POWER_MISC_PERIPHERALSWOFF 0x1 | ||
| 343 | #define BF_POWER_MISC_PERIPHERALSWOFF(v) (((v) << 0) & 0x1) | ||
| 344 | |||
| 345 | /** | ||
| 346 | * Register: HW_POWER_DCLIMITS | ||
| 347 | * Address: 0x90 | ||
| 348 | * SCT: no | ||
| 349 | */ | ||
| 350 | #define HW_POWER_DCLIMITS (*(volatile unsigned long *)(REGS_POWER_BASE + 0x90)) | ||
| 351 | #define BP_POWER_DCLIMITS_POSLIMIT_BOOST 16 | ||
| 352 | #define BM_POWER_DCLIMITS_POSLIMIT_BOOST 0x7f0000 | ||
| 353 | #define BF_POWER_DCLIMITS_POSLIMIT_BOOST(v) (((v) << 16) & 0x7f0000) | ||
| 354 | #define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 | ||
| 355 | #define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x7f00 | ||
| 356 | #define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) (((v) << 8) & 0x7f00) | ||
| 357 | #define BP_POWER_DCLIMITS_NEGLIMIT 0 | ||
| 358 | #define BM_POWER_DCLIMITS_NEGLIMIT 0x7f | ||
| 359 | #define BF_POWER_DCLIMITS_NEGLIMIT(v) (((v) << 0) & 0x7f) | ||
| 360 | |||
| 361 | /** | ||
| 362 | * Register: HW_POWER_LOOPCTRL | ||
| 363 | * Address: 0xa0 | ||
| 364 | * SCT: yes | ||
| 365 | */ | ||
| 366 | #define HW_POWER_LOOPCTRL (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x0)) | ||
| 367 | #define HW_POWER_LOOPCTRL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x4)) | ||
| 368 | #define HW_POWER_LOOPCTRL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0x8)) | ||
| 369 | #define HW_POWER_LOOPCTRL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xa0 + 0xc)) | ||
| 370 | #define BP_POWER_LOOPCTRL_TOGGLE_DIF 20 | ||
| 371 | #define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x100000 | ||
| 372 | #define BF_POWER_LOOPCTRL_TOGGLE_DIF(v) (((v) << 20) & 0x100000) | ||
| 373 | #define BP_POWER_LOOPCTRL_HYST_SIGN 19 | ||
| 374 | #define BM_POWER_LOOPCTRL_HYST_SIGN 0x80000 | ||
| 375 | #define BF_POWER_LOOPCTRL_HYST_SIGN(v) (((v) << 19) & 0x80000) | ||
| 376 | #define BP_POWER_LOOPCTRL_EN_CM_HYST 18 | ||
| 377 | #define BM_POWER_LOOPCTRL_EN_CM_HYST 0x40000 | ||
| 378 | #define BF_POWER_LOOPCTRL_EN_CM_HYST(v) (((v) << 18) & 0x40000) | ||
| 379 | #define BP_POWER_LOOPCTRL_EN_DF_HYST 17 | ||
| 380 | #define BM_POWER_LOOPCTRL_EN_DF_HYST 0x20000 | ||
| 381 | #define BF_POWER_LOOPCTRL_EN_DF_HYST(v) (((v) << 17) & 0x20000) | ||
| 382 | #define BP_POWER_LOOPCTRL_CM_HYST_THRESH 16 | ||
| 383 | #define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x10000 | ||
| 384 | #define BF_POWER_LOOPCTRL_CM_HYST_THRESH(v) (((v) << 16) & 0x10000) | ||
| 385 | #define BP_POWER_LOOPCTRL_DF_HYST_THRESH 15 | ||
| 386 | #define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x8000 | ||
| 387 | #define BF_POWER_LOOPCTRL_DF_HYST_THRESH(v) (((v) << 15) & 0x8000) | ||
| 388 | #define BP_POWER_LOOPCTRL_RCSCALE_THRESH 14 | ||
| 389 | #define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x4000 | ||
| 390 | #define BF_POWER_LOOPCTRL_RCSCALE_THRESH(v) (((v) << 14) & 0x4000) | ||
| 391 | #define BP_POWER_LOOPCTRL_EN_RCSCALE 12 | ||
| 392 | #define BM_POWER_LOOPCTRL_EN_RCSCALE 0x3000 | ||
| 393 | #define BF_POWER_LOOPCTRL_EN_RCSCALE(v) (((v) << 12) & 0x3000) | ||
| 394 | #define BP_POWER_LOOPCTRL_DC_FF 8 | ||
| 395 | #define BM_POWER_LOOPCTRL_DC_FF 0x700 | ||
| 396 | #define BF_POWER_LOOPCTRL_DC_FF(v) (((v) << 8) & 0x700) | ||
| 397 | #define BP_POWER_LOOPCTRL_DC_R 4 | ||
| 398 | #define BM_POWER_LOOPCTRL_DC_R 0xf0 | ||
| 399 | #define BF_POWER_LOOPCTRL_DC_R(v) (((v) << 4) & 0xf0) | ||
| 400 | #define BP_POWER_LOOPCTRL_DC_C 0 | ||
| 401 | #define BM_POWER_LOOPCTRL_DC_C 0x3 | ||
| 402 | #define BF_POWER_LOOPCTRL_DC_C(v) (((v) << 0) & 0x3) | ||
| 403 | |||
| 404 | /** | ||
| 405 | * Register: HW_POWER_STS | ||
| 406 | * Address: 0xb0 | ||
| 407 | * SCT: no | ||
| 408 | */ | ||
| 409 | #define HW_POWER_STS (*(volatile unsigned long *)(REGS_POWER_BASE + 0xb0)) | ||
| 410 | #define BP_POWER_STS_BATT_CHRG_PRESENT 31 | ||
| 411 | #define BM_POWER_STS_BATT_CHRG_PRESENT 0x80000000 | ||
| 412 | #define BF_POWER_STS_BATT_CHRG_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 413 | #define BP_POWER_STS_PSWITCH 18 | ||
| 414 | #define BM_POWER_STS_PSWITCH 0xc0000 | ||
| 415 | #define BF_POWER_STS_PSWITCH(v) (((v) << 18) & 0xc0000) | ||
| 416 | #define BP_POWER_STS_AVALID_STATUS 17 | ||
| 417 | #define BM_POWER_STS_AVALID_STATUS 0x20000 | ||
| 418 | #define BF_POWER_STS_AVALID_STATUS(v) (((v) << 17) & 0x20000) | ||
| 419 | #define BP_POWER_STS_BVALID_STATUS 16 | ||
| 420 | #define BM_POWER_STS_BVALID_STATUS 0x10000 | ||
| 421 | #define BF_POWER_STS_BVALID_STATUS(v) (((v) << 16) & 0x10000) | ||
| 422 | #define BP_POWER_STS_VBUSVALID_STATUS 15 | ||
| 423 | #define BM_POWER_STS_VBUSVALID_STATUS 0x8000 | ||
| 424 | #define BF_POWER_STS_VBUSVALID_STATUS(v) (((v) << 15) & 0x8000) | ||
| 425 | #define BP_POWER_STS_SESSEND_STATUS 14 | ||
| 426 | #define BM_POWER_STS_SESSEND_STATUS 0x4000 | ||
| 427 | #define BF_POWER_STS_SESSEND_STATUS(v) (((v) << 14) & 0x4000) | ||
| 428 | #define BP_POWER_STS_MODE 13 | ||
| 429 | #define BM_POWER_STS_MODE 0x2000 | ||
| 430 | #define BF_POWER_STS_MODE(v) (((v) << 13) & 0x2000) | ||
| 431 | #define BP_POWER_STS_BATT_BO 12 | ||
| 432 | #define BM_POWER_STS_BATT_BO 0x1000 | ||
| 433 | #define BF_POWER_STS_BATT_BO(v) (((v) << 12) & 0x1000) | ||
| 434 | #define BP_POWER_STS_VDD5V_FAULT 11 | ||
| 435 | #define BM_POWER_STS_VDD5V_FAULT 0x800 | ||
| 436 | #define BF_POWER_STS_VDD5V_FAULT(v) (((v) << 11) & 0x800) | ||
| 437 | #define BP_POWER_STS_CHRGSTS 10 | ||
| 438 | #define BM_POWER_STS_CHRGSTS 0x400 | ||
| 439 | #define BF_POWER_STS_CHRGSTS(v) (((v) << 10) & 0x400) | ||
| 440 | #define BP_POWER_STS_LINREG_OK 9 | ||
| 441 | #define BM_POWER_STS_LINREG_OK 0x200 | ||
| 442 | #define BF_POWER_STS_LINREG_OK(v) (((v) << 9) & 0x200) | ||
| 443 | #define BP_POWER_STS_DC_OK 8 | ||
| 444 | #define BM_POWER_STS_DC_OK 0x100 | ||
| 445 | #define BF_POWER_STS_DC_OK(v) (((v) << 8) & 0x100) | ||
| 446 | #define BP_POWER_STS_VDDIO_BO 7 | ||
| 447 | #define BM_POWER_STS_VDDIO_BO 0x80 | ||
| 448 | #define BF_POWER_STS_VDDIO_BO(v) (((v) << 7) & 0x80) | ||
| 449 | #define BP_POWER_STS_VDDA_BO 6 | ||
| 450 | #define BM_POWER_STS_VDDA_BO 0x40 | ||
| 451 | #define BF_POWER_STS_VDDA_BO(v) (((v) << 6) & 0x40) | ||
| 452 | #define BP_POWER_STS_VDDD_BO 5 | ||
| 453 | #define BM_POWER_STS_VDDD_BO 0x20 | ||
| 454 | #define BF_POWER_STS_VDDD_BO(v) (((v) << 5) & 0x20) | ||
| 455 | #define BP_POWER_STS_VDD5V_GT_VDDIO 4 | ||
| 456 | #define BM_POWER_STS_VDD5V_GT_VDDIO 0x10 | ||
| 457 | #define BF_POWER_STS_VDD5V_GT_VDDIO(v) (((v) << 4) & 0x10) | ||
| 458 | #define BP_POWER_STS_AVALID 3 | ||
| 459 | #define BM_POWER_STS_AVALID 0x8 | ||
| 460 | #define BF_POWER_STS_AVALID(v) (((v) << 3) & 0x8) | ||
| 461 | #define BP_POWER_STS_BVALID 2 | ||
| 462 | #define BM_POWER_STS_BVALID 0x4 | ||
| 463 | #define BF_POWER_STS_BVALID(v) (((v) << 2) & 0x4) | ||
| 464 | #define BP_POWER_STS_VBUSVALID 1 | ||
| 465 | #define BM_POWER_STS_VBUSVALID 0x2 | ||
| 466 | #define BF_POWER_STS_VBUSVALID(v) (((v) << 1) & 0x2) | ||
| 467 | #define BP_POWER_STS_SESSEND 0 | ||
| 468 | #define BM_POWER_STS_SESSEND 0x1 | ||
| 469 | #define BF_POWER_STS_SESSEND(v) (((v) << 0) & 0x1) | ||
| 470 | |||
| 471 | /** | ||
| 472 | * Register: HW_POWER_SPEED | ||
| 473 | * Address: 0xc0 | ||
| 474 | * SCT: yes | ||
| 475 | */ | ||
| 476 | #define HW_POWER_SPEED (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x0)) | ||
| 477 | #define HW_POWER_SPEED_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x4)) | ||
| 478 | #define HW_POWER_SPEED_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0x8)) | ||
| 479 | #define HW_POWER_SPEED_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xc0 + 0xc)) | ||
| 480 | #define BP_POWER_SPEED_STATUS 16 | ||
| 481 | #define BM_POWER_SPEED_STATUS 0xff0000 | ||
| 482 | #define BF_POWER_SPEED_STATUS(v) (((v) << 16) & 0xff0000) | ||
| 483 | #define BP_POWER_SPEED_CTRL 0 | ||
| 484 | #define BM_POWER_SPEED_CTRL 0x3 | ||
| 485 | #define BF_POWER_SPEED_CTRL(v) (((v) << 0) & 0x3) | ||
| 486 | |||
| 487 | /** | ||
| 488 | * Register: HW_POWER_BATTMONITOR | ||
| 489 | * Address: 0xd0 | ||
| 490 | * SCT: no | ||
| 491 | */ | ||
| 492 | #define HW_POWER_BATTMONITOR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xd0)) | ||
| 493 | #define BP_POWER_BATTMONITOR_BATT_VAL 16 | ||
| 494 | #define BM_POWER_BATTMONITOR_BATT_VAL 0x3ff0000 | ||
| 495 | #define BF_POWER_BATTMONITOR_BATT_VAL(v) (((v) << 16) & 0x3ff0000) | ||
| 496 | #define BP_POWER_BATTMONITOR_EN_BATADJ 6 | ||
| 497 | #define BM_POWER_BATTMONITOR_EN_BATADJ 0x40 | ||
| 498 | #define BF_POWER_BATTMONITOR_EN_BATADJ(v) (((v) << 6) & 0x40) | ||
| 499 | #define BP_POWER_BATTMONITOR_PWDN_BATTBRNOUT 5 | ||
| 500 | #define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x20 | ||
| 501 | #define BF_POWER_BATTMONITOR_PWDN_BATTBRNOUT(v) (((v) << 5) & 0x20) | ||
| 502 | #define BP_POWER_BATTMONITOR_BRWNOUT_PWD 4 | ||
| 503 | #define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x10 | ||
| 504 | #define BF_POWER_BATTMONITOR_BRWNOUT_PWD(v) (((v) << 4) & 0x10) | ||
| 505 | #define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 | ||
| 506 | #define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0xf | ||
| 507 | #define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) (((v) << 0) & 0xf) | ||
| 508 | |||
| 509 | /** | ||
| 510 | * Register: HW_POWER_RESET | ||
| 511 | * Address: 0xe0 | ||
| 512 | * SCT: yes | ||
| 513 | */ | ||
| 514 | #define HW_POWER_RESET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x0)) | ||
| 515 | #define HW_POWER_RESET_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x4)) | ||
| 516 | #define HW_POWER_RESET_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0x8)) | ||
| 517 | #define HW_POWER_RESET_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xe0 + 0xc)) | ||
| 518 | #define BP_POWER_RESET_UNLOCK 16 | ||
| 519 | #define BM_POWER_RESET_UNLOCK 0xffff0000 | ||
| 520 | #define BV_POWER_RESET_UNLOCK__KEY 0x3e77 | ||
| 521 | #define BF_POWER_RESET_UNLOCK(v) (((v) << 16) & 0xffff0000) | ||
| 522 | #define BF_POWER_RESET_UNLOCK_V(v) ((BV_POWER_RESET_UNLOCK__##v << 16) & 0xffff0000) | ||
| 523 | #define BP_POWER_RESET_PWD_OFF 1 | ||
| 524 | #define BM_POWER_RESET_PWD_OFF 0x2 | ||
| 525 | #define BF_POWER_RESET_PWD_OFF(v) (((v) << 1) & 0x2) | ||
| 526 | #define BP_POWER_RESET_PWD 0 | ||
| 527 | #define BM_POWER_RESET_PWD 0x1 | ||
| 528 | #define BF_POWER_RESET_PWD(v) (((v) << 0) & 0x1) | ||
| 529 | |||
| 530 | /** | ||
| 531 | * Register: HW_POWER_DEBUG | ||
| 532 | * Address: 0xf0 | ||
| 533 | * SCT: yes | ||
| 534 | */ | ||
| 535 | #define HW_POWER_DEBUG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x0)) | ||
| 536 | #define HW_POWER_DEBUG_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x4)) | ||
| 537 | #define HW_POWER_DEBUG_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0x8)) | ||
| 538 | #define HW_POWER_DEBUG_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0xf0 + 0xc)) | ||
| 539 | #define BP_POWER_DEBUG_VBUSVALIDPIOLOCK 3 | ||
| 540 | #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x8 | ||
| 541 | #define BF_POWER_DEBUG_VBUSVALIDPIOLOCK(v) (((v) << 3) & 0x8) | ||
| 542 | #define BP_POWER_DEBUG_AVALIDPIOLOCK 2 | ||
| 543 | #define BM_POWER_DEBUG_AVALIDPIOLOCK 0x4 | ||
| 544 | #define BF_POWER_DEBUG_AVALIDPIOLOCK(v) (((v) << 2) & 0x4) | ||
| 545 | #define BP_POWER_DEBUG_BVALIDPIOLOCK 1 | ||
| 546 | #define BM_POWER_DEBUG_BVALIDPIOLOCK 0x2 | ||
| 547 | #define BF_POWER_DEBUG_BVALIDPIOLOCK(v) (((v) << 1) & 0x2) | ||
| 548 | #define BP_POWER_DEBUG_SESSENDPIOLOCK 0 | ||
| 549 | #define BM_POWER_DEBUG_SESSENDPIOLOCK 0x1 | ||
| 550 | #define BF_POWER_DEBUG_SESSENDPIOLOCK(v) (((v) << 0) & 0x1) | ||
| 551 | |||
| 552 | /** | ||
| 553 | * Register: HW_POWER_SPECIAL | ||
| 554 | * Address: 0x100 | ||
| 555 | * SCT: yes | ||
| 556 | */ | ||
| 557 | #define HW_POWER_SPECIAL (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x0)) | ||
| 558 | #define HW_POWER_SPECIAL_SET (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x4)) | ||
| 559 | #define HW_POWER_SPECIAL_CLR (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0x8)) | ||
| 560 | #define HW_POWER_SPECIAL_TOG (*(volatile unsigned long *)(REGS_POWER_BASE + 0x100 + 0xc)) | ||
| 561 | #define BP_POWER_SPECIAL_TEST 0 | ||
| 562 | #define BM_POWER_SPECIAL_TEST 0xffffffff | ||
| 563 | #define BF_POWER_SPECIAL_TEST(v) (((v) << 0) & 0xffffffff) | ||
| 564 | |||
| 565 | /** | ||
| 566 | * Register: HW_POWER_VERSION | ||
| 567 | * Address: 0x110 | ||
| 568 | * SCT: no | ||
| 569 | */ | ||
| 570 | #define HW_POWER_VERSION (*(volatile unsigned long *)(REGS_POWER_BASE + 0x110)) | ||
| 571 | #define BP_POWER_VERSION_MAJOR 24 | ||
| 572 | #define BM_POWER_VERSION_MAJOR 0xff000000 | ||
| 573 | #define BF_POWER_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 574 | #define BP_POWER_VERSION_MINOR 16 | ||
| 575 | #define BM_POWER_VERSION_MINOR 0xff0000 | ||
| 576 | #define BF_POWER_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 577 | #define BP_POWER_VERSION_STEP 0 | ||
| 578 | #define BM_POWER_VERSION_STEP 0xffff | ||
| 579 | #define BF_POWER_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 580 | |||
| 581 | #endif /* __HEADERGEN__STMP3700__POWER__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h b/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h new file mode 100644 index 0000000000..4d7b385d10 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-pwm.h | |||
| @@ -0,0 +1,153 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__PWM__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__PWM__H__ | ||
| 25 | |||
| 26 | #define REGS_PWM_BASE (0x80064000) | ||
| 27 | |||
| 28 | #define REGS_PWM_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_PWM_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_PWM_CTRL (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_PWM_CTRL_SET (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_PWM_CTRL_CLR (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_PWM_CTRL_TOG (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_PWM_CTRL_SFTRST 31 | ||
| 40 | #define BM_PWM_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_PWM_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_PWM_CTRL_CLKGATE 30 | ||
| 43 | #define BM_PWM_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_PWM_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_PWM_CTRL_PWM4_PRESENT 29 | ||
| 46 | #define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 | ||
| 47 | #define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_PWM_CTRL_PWM3_PRESENT 28 | ||
| 49 | #define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 | ||
| 50 | #define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_PWM_CTRL_PWM2_PRESENT 27 | ||
| 52 | #define BM_PWM_CTRL_PWM2_PRESENT 0x8000000 | ||
| 53 | #define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_PWM_CTRL_PWM1_PRESENT 26 | ||
| 55 | #define BM_PWM_CTRL_PWM1_PRESENT 0x4000000 | ||
| 56 | #define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_PWM_CTRL_PWM0_PRESENT 25 | ||
| 58 | #define BM_PWM_CTRL_PWM0_PRESENT 0x2000000 | ||
| 59 | #define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
| 60 | #define BP_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 5 | ||
| 61 | #define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x20 | ||
| 62 | #define BF_PWM_CTRL_PWM2_ANA_CTRL_ENABLE(v) (((v) << 5) & 0x20) | ||
| 63 | #define BP_PWM_CTRL_PWM4_ENABLE 4 | ||
| 64 | #define BM_PWM_CTRL_PWM4_ENABLE 0x10 | ||
| 65 | #define BF_PWM_CTRL_PWM4_ENABLE(v) (((v) << 4) & 0x10) | ||
| 66 | #define BP_PWM_CTRL_PWM3_ENABLE 3 | ||
| 67 | #define BM_PWM_CTRL_PWM3_ENABLE 0x8 | ||
| 68 | #define BF_PWM_CTRL_PWM3_ENABLE(v) (((v) << 3) & 0x8) | ||
| 69 | #define BP_PWM_CTRL_PWM2_ENABLE 2 | ||
| 70 | #define BM_PWM_CTRL_PWM2_ENABLE 0x4 | ||
| 71 | #define BF_PWM_CTRL_PWM2_ENABLE(v) (((v) << 2) & 0x4) | ||
| 72 | #define BP_PWM_CTRL_PWM1_ENABLE 1 | ||
| 73 | #define BM_PWM_CTRL_PWM1_ENABLE 0x2 | ||
| 74 | #define BF_PWM_CTRL_PWM1_ENABLE(v) (((v) << 1) & 0x2) | ||
| 75 | #define BP_PWM_CTRL_PWM0_ENABLE 0 | ||
| 76 | #define BM_PWM_CTRL_PWM0_ENABLE 0x1 | ||
| 77 | #define BF_PWM_CTRL_PWM0_ENABLE(v) (((v) << 0) & 0x1) | ||
| 78 | |||
| 79 | /** | ||
| 80 | * Register: HW_PWM_ACTIVEn | ||
| 81 | * Address: 0x10+n*0x20 | ||
| 82 | * SCT: yes | ||
| 83 | */ | ||
| 84 | #define HW_PWM_ACTIVEn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0)) | ||
| 85 | #define HW_PWM_ACTIVEn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4)) | ||
| 86 | #define HW_PWM_ACTIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8)) | ||
| 87 | #define HW_PWM_ACTIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc)) | ||
| 88 | #define BP_PWM_ACTIVEn_INACTIVE 16 | ||
| 89 | #define BM_PWM_ACTIVEn_INACTIVE 0xffff0000 | ||
| 90 | #define BF_PWM_ACTIVEn_INACTIVE(v) (((v) << 16) & 0xffff0000) | ||
| 91 | #define BP_PWM_ACTIVEn_ACTIVE 0 | ||
| 92 | #define BM_PWM_ACTIVEn_ACTIVE 0xffff | ||
| 93 | #define BF_PWM_ACTIVEn_ACTIVE(v) (((v) << 0) & 0xffff) | ||
| 94 | |||
| 95 | /** | ||
| 96 | * Register: HW_PWM_PERIODn | ||
| 97 | * Address: 0x20+n*0x20 | ||
| 98 | * SCT: yes | ||
| 99 | */ | ||
| 100 | #define HW_PWM_PERIODn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0)) | ||
| 101 | #define HW_PWM_PERIODn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4)) | ||
| 102 | #define HW_PWM_PERIODn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8)) | ||
| 103 | #define HW_PWM_PERIODn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc)) | ||
| 104 | #define BP_PWM_PERIODn_MATT 23 | ||
| 105 | #define BM_PWM_PERIODn_MATT 0x800000 | ||
| 106 | #define BF_PWM_PERIODn_MATT(v) (((v) << 23) & 0x800000) | ||
| 107 | #define BP_PWM_PERIODn_CDIV 20 | ||
| 108 | #define BM_PWM_PERIODn_CDIV 0x700000 | ||
| 109 | #define BV_PWM_PERIODn_CDIV__DIV_1 0x0 | ||
| 110 | #define BV_PWM_PERIODn_CDIV__DIV_2 0x1 | ||
| 111 | #define BV_PWM_PERIODn_CDIV__DIV_4 0x2 | ||
| 112 | #define BV_PWM_PERIODn_CDIV__DIV_8 0x3 | ||
| 113 | #define BV_PWM_PERIODn_CDIV__DIV_16 0x4 | ||
| 114 | #define BV_PWM_PERIODn_CDIV__DIV_64 0x5 | ||
| 115 | #define BV_PWM_PERIODn_CDIV__DIV_256 0x6 | ||
| 116 | #define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 | ||
| 117 | #define BF_PWM_PERIODn_CDIV(v) (((v) << 20) & 0x700000) | ||
| 118 | #define BF_PWM_PERIODn_CDIV_V(v) ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000) | ||
| 119 | #define BP_PWM_PERIODn_INACTIVE_STATE 18 | ||
| 120 | #define BM_PWM_PERIODn_INACTIVE_STATE 0xc0000 | ||
| 121 | #define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 | ||
| 122 | #define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 | ||
| 123 | #define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 | ||
| 124 | #define BF_PWM_PERIODn_INACTIVE_STATE(v) (((v) << 18) & 0xc0000) | ||
| 125 | #define BF_PWM_PERIODn_INACTIVE_STATE_V(v) ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000) | ||
| 126 | #define BP_PWM_PERIODn_ACTIVE_STATE 16 | ||
| 127 | #define BM_PWM_PERIODn_ACTIVE_STATE 0x30000 | ||
| 128 | #define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 | ||
| 129 | #define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 | ||
| 130 | #define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 | ||
| 131 | #define BF_PWM_PERIODn_ACTIVE_STATE(v) (((v) << 16) & 0x30000) | ||
| 132 | #define BF_PWM_PERIODn_ACTIVE_STATE_V(v) ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000) | ||
| 133 | #define BP_PWM_PERIODn_PERIOD 0 | ||
| 134 | #define BM_PWM_PERIODn_PERIOD 0xffff | ||
| 135 | #define BF_PWM_PERIODn_PERIOD(v) (((v) << 0) & 0xffff) | ||
| 136 | |||
| 137 | /** | ||
| 138 | * Register: HW_PWM_VERSION | ||
| 139 | * Address: 0xb0 | ||
| 140 | * SCT: no | ||
| 141 | */ | ||
| 142 | #define HW_PWM_VERSION (*(volatile unsigned long *)(REGS_PWM_BASE + 0xb0)) | ||
| 143 | #define BP_PWM_VERSION_MAJOR 24 | ||
| 144 | #define BM_PWM_VERSION_MAJOR 0xff000000 | ||
| 145 | #define BF_PWM_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 146 | #define BP_PWM_VERSION_MINOR 16 | ||
| 147 | #define BM_PWM_VERSION_MINOR 0xff0000 | ||
| 148 | #define BF_PWM_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 149 | #define BP_PWM_VERSION_STEP 0 | ||
| 150 | #define BM_PWM_VERSION_STEP 0xffff | ||
| 151 | #define BF_PWM_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 152 | |||
| 153 | #endif /* __HEADERGEN__STMP3700__PWM__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h new file mode 100644 index 0000000000..ed2bf3270e --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h | |||
| @@ -0,0 +1,312 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__RTC__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__RTC__H__ | ||
| 25 | |||
| 26 | #define REGS_RTC_BASE (0x8005c000) | ||
| 27 | |||
| 28 | #define REGS_RTC_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_RTC_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_RTC_CTRL (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_RTC_CTRL_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_RTC_CTRL_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_RTC_CTRL_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_RTC_CTRL_SFTRST 31 | ||
| 40 | #define BM_RTC_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_RTC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_RTC_CTRL_CLKGATE 30 | ||
| 43 | #define BM_RTC_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_RTC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG 6 | ||
| 46 | #define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x40 | ||
| 47 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40) | ||
| 48 | #define BP_RTC_CTRL_FORCE_UPDATE 5 | ||
| 49 | #define BM_RTC_CTRL_FORCE_UPDATE 0x20 | ||
| 50 | #define BF_RTC_CTRL_FORCE_UPDATE(v) (((v) << 5) & 0x20) | ||
| 51 | #define BP_RTC_CTRL_WATCHDOGEN 4 | ||
| 52 | #define BM_RTC_CTRL_WATCHDOGEN 0x10 | ||
| 53 | #define BF_RTC_CTRL_WATCHDOGEN(v) (((v) << 4) & 0x10) | ||
| 54 | #define BP_RTC_CTRL_ONEMSEC_IRQ 3 | ||
| 55 | #define BM_RTC_CTRL_ONEMSEC_IRQ 0x8 | ||
| 56 | #define BF_RTC_CTRL_ONEMSEC_IRQ(v) (((v) << 3) & 0x8) | ||
| 57 | #define BP_RTC_CTRL_ALARM_IRQ 2 | ||
| 58 | #define BM_RTC_CTRL_ALARM_IRQ 0x4 | ||
| 59 | #define BF_RTC_CTRL_ALARM_IRQ(v) (((v) << 2) & 0x4) | ||
| 60 | #define BP_RTC_CTRL_ONEMSEC_IRQ_EN 1 | ||
| 61 | #define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x2 | ||
| 62 | #define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 63 | #define BP_RTC_CTRL_ALARM_IRQ_EN 0 | ||
| 64 | #define BM_RTC_CTRL_ALARM_IRQ_EN 0x1 | ||
| 65 | #define BF_RTC_CTRL_ALARM_IRQ_EN(v) (((v) << 0) & 0x1) | ||
| 66 | |||
| 67 | /** | ||
| 68 | * Register: HW_RTC_STAT | ||
| 69 | * Address: 0x10 | ||
| 70 | * SCT: no | ||
| 71 | */ | ||
| 72 | #define HW_RTC_STAT (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10)) | ||
| 73 | #define BP_RTC_STAT_RTC_PRESENT 31 | ||
| 74 | #define BM_RTC_STAT_RTC_PRESENT 0x80000000 | ||
| 75 | #define BF_RTC_STAT_RTC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 76 | #define BP_RTC_STAT_ALARM_PRESENT 30 | ||
| 77 | #define BM_RTC_STAT_ALARM_PRESENT 0x40000000 | ||
| 78 | #define BF_RTC_STAT_ALARM_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 79 | #define BP_RTC_STAT_WATCHDOG_PRESENT 29 | ||
| 80 | #define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 | ||
| 81 | #define BF_RTC_STAT_WATCHDOG_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 82 | #define BP_RTC_STAT_XTAL32000_PRESENT 28 | ||
| 83 | #define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 | ||
| 84 | #define BF_RTC_STAT_XTAL32000_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 85 | #define BP_RTC_STAT_XTAL32768_PRESENT 27 | ||
| 86 | #define BM_RTC_STAT_XTAL32768_PRESENT 0x8000000 | ||
| 87 | #define BF_RTC_STAT_XTAL32768_PRESENT(v) (((v) << 27) & 0x8000000) | ||
| 88 | #define BP_RTC_STAT_STALE_REGS 16 | ||
| 89 | #define BM_RTC_STAT_STALE_REGS 0xff0000 | ||
| 90 | #define BF_RTC_STAT_STALE_REGS(v) (((v) << 16) & 0xff0000) | ||
| 91 | #define BP_RTC_STAT_NEW_REGS 8 | ||
| 92 | #define BM_RTC_STAT_NEW_REGS 0xff00 | ||
| 93 | #define BF_RTC_STAT_NEW_REGS(v) (((v) << 8) & 0xff00) | ||
| 94 | |||
| 95 | /** | ||
| 96 | * Register: HW_RTC_MILLISECONDS | ||
| 97 | * Address: 0x20 | ||
| 98 | * SCT: yes | ||
| 99 | */ | ||
| 100 | #define HW_RTC_MILLISECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0)) | ||
| 101 | #define HW_RTC_MILLISECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4)) | ||
| 102 | #define HW_RTC_MILLISECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8)) | ||
| 103 | #define HW_RTC_MILLISECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc)) | ||
| 104 | #define BP_RTC_MILLISECONDS_COUNT 0 | ||
| 105 | #define BM_RTC_MILLISECONDS_COUNT 0xffffffff | ||
| 106 | #define BF_RTC_MILLISECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 107 | |||
| 108 | /** | ||
| 109 | * Register: HW_RTC_SECONDS | ||
| 110 | * Address: 0x30 | ||
| 111 | * SCT: yes | ||
| 112 | */ | ||
| 113 | #define HW_RTC_SECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0)) | ||
| 114 | #define HW_RTC_SECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4)) | ||
| 115 | #define HW_RTC_SECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8)) | ||
| 116 | #define HW_RTC_SECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc)) | ||
| 117 | #define BP_RTC_SECONDS_COUNT 0 | ||
| 118 | #define BM_RTC_SECONDS_COUNT 0xffffffff | ||
| 119 | #define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 120 | |||
| 121 | /** | ||
| 122 | * Register: HW_RTC_ALARM | ||
| 123 | * Address: 0x40 | ||
| 124 | * SCT: yes | ||
| 125 | */ | ||
| 126 | #define HW_RTC_ALARM (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0)) | ||
| 127 | #define HW_RTC_ALARM_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4)) | ||
| 128 | #define HW_RTC_ALARM_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8)) | ||
| 129 | #define HW_RTC_ALARM_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc)) | ||
| 130 | #define BP_RTC_ALARM_VALUE 0 | ||
| 131 | #define BM_RTC_ALARM_VALUE 0xffffffff | ||
| 132 | #define BF_RTC_ALARM_VALUE(v) (((v) << 0) & 0xffffffff) | ||
| 133 | |||
| 134 | /** | ||
| 135 | * Register: HW_RTC_WATCHDOG | ||
| 136 | * Address: 0x50 | ||
| 137 | * SCT: yes | ||
| 138 | */ | ||
| 139 | #define HW_RTC_WATCHDOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0)) | ||
| 140 | #define HW_RTC_WATCHDOG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4)) | ||
| 141 | #define HW_RTC_WATCHDOG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8)) | ||
| 142 | #define HW_RTC_WATCHDOG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc)) | ||
| 143 | #define BP_RTC_WATCHDOG_COUNT 0 | ||
| 144 | #define BM_RTC_WATCHDOG_COUNT 0xffffffff | ||
| 145 | #define BF_RTC_WATCHDOG_COUNT(v) (((v) << 0) & 0xffffffff) | ||
| 146 | |||
| 147 | /** | ||
| 148 | * Register: HW_RTC_PERSISTENT0 | ||
| 149 | * Address: 0x60 | ||
| 150 | * SCT: yes | ||
| 151 | */ | ||
| 152 | #define HW_RTC_PERSISTENT0 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0)) | ||
| 153 | #define HW_RTC_PERSISTENT0_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4)) | ||
| 154 | #define HW_RTC_PERSISTENT0_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8)) | ||
| 155 | #define HW_RTC_PERSISTENT0_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc)) | ||
| 156 | #define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 | ||
| 157 | #define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xfffc0000 | ||
| 158 | #define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) (((v) << 18) & 0xfffc0000) | ||
| 159 | #define BP_RTC_PERSISTENT0_AUTO_RESTART 17 | ||
| 160 | #define BM_RTC_PERSISTENT0_AUTO_RESTART 0x20000 | ||
| 161 | #define BF_RTC_PERSISTENT0_AUTO_RESTART(v) (((v) << 17) & 0x20000) | ||
| 162 | #define BP_RTC_PERSISTENT0_DISABLE_PSWITCH 16 | ||
| 163 | #define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x10000 | ||
| 164 | #define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v) (((v) << 16) & 0x10000) | ||
| 165 | #define BP_RTC_PERSISTENT0_LOWERBIAS 14 | ||
| 166 | #define BM_RTC_PERSISTENT0_LOWERBIAS 0xc000 | ||
| 167 | #define BF_RTC_PERSISTENT0_LOWERBIAS(v) (((v) << 14) & 0xc000) | ||
| 168 | #define BP_RTC_PERSISTENT0_DISABLE_XTALOK 13 | ||
| 169 | #define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x2000 | ||
| 170 | #define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v) (((v) << 13) & 0x2000) | ||
| 171 | #define BP_RTC_PERSISTENT0_MSEC_RES 8 | ||
| 172 | #define BM_RTC_PERSISTENT0_MSEC_RES 0x1f00 | ||
| 173 | #define BF_RTC_PERSISTENT0_MSEC_RES(v) (((v) << 8) & 0x1f00) | ||
| 174 | #define BP_RTC_PERSISTENT0_ALARM_WAKE 7 | ||
| 175 | #define BM_RTC_PERSISTENT0_ALARM_WAKE 0x80 | ||
| 176 | #define BF_RTC_PERSISTENT0_ALARM_WAKE(v) (((v) << 7) & 0x80) | ||
| 177 | #define BP_RTC_PERSISTENT0_XTAL32_FREQ 6 | ||
| 178 | #define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x40 | ||
| 179 | #define BF_RTC_PERSISTENT0_XTAL32_FREQ(v) (((v) << 6) & 0x40) | ||
| 180 | #define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 5 | ||
| 181 | #define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x20 | ||
| 182 | #define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v) (((v) << 5) & 0x20) | ||
| 183 | #define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 4 | ||
| 184 | #define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x10 | ||
| 185 | #define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v) (((v) << 4) & 0x10) | ||
| 186 | #define BP_RTC_PERSISTENT0_LCK_SECS 3 | ||
| 187 | #define BM_RTC_PERSISTENT0_LCK_SECS 0x8 | ||
| 188 | #define BF_RTC_PERSISTENT0_LCK_SECS(v) (((v) << 3) & 0x8) | ||
| 189 | #define BP_RTC_PERSISTENT0_ALARM_EN 2 | ||
| 190 | #define BM_RTC_PERSISTENT0_ALARM_EN 0x4 | ||
| 191 | #define BF_RTC_PERSISTENT0_ALARM_EN(v) (((v) << 2) & 0x4) | ||
| 192 | #define BP_RTC_PERSISTENT0_ALARM_WAKE_EN 1 | ||
| 193 | #define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x2 | ||
| 194 | #define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v) (((v) << 1) & 0x2) | ||
| 195 | #define BP_RTC_PERSISTENT0_CLOCKSOURCE 0 | ||
| 196 | #define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x1 | ||
| 197 | #define BF_RTC_PERSISTENT0_CLOCKSOURCE(v) (((v) << 0) & 0x1) | ||
| 198 | |||
| 199 | /** | ||
| 200 | * Register: HW_RTC_PERSISTENT1 | ||
| 201 | * Address: 0x70 | ||
| 202 | * SCT: yes | ||
| 203 | */ | ||
| 204 | #define HW_RTC_PERSISTENT1 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0)) | ||
| 205 | #define HW_RTC_PERSISTENT1_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4)) | ||
| 206 | #define HW_RTC_PERSISTENT1_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8)) | ||
| 207 | #define HW_RTC_PERSISTENT1_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc)) | ||
| 208 | #define BP_RTC_PERSISTENT1_GENERAL 0 | ||
| 209 | #define BM_RTC_PERSISTENT1_GENERAL 0xffffffff | ||
| 210 | #define BV_RTC_PERSISTENT1_GENERAL__SPARE3 0x4000 | ||
| 211 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_BOOT 0x2000 | ||
| 212 | #define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 | ||
| 213 | #define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x800 | ||
| 214 | #define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x400 | ||
| 215 | #define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x200 | ||
| 216 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x100 | ||
| 217 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x80 | ||
| 218 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_HI 0x40 | ||
| 219 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_LO 0x20 | ||
| 220 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_3 0x10 | ||
| 221 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_2 0x8 | ||
| 222 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_1 0x4 | ||
| 223 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_0 0x2 | ||
| 224 | #define BV_RTC_PERSISTENT1_GENERAL__ETM_ENABLE 0x1 | ||
| 225 | #define BF_RTC_PERSISTENT1_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
| 226 | #define BF_RTC_PERSISTENT1_GENERAL_V(v) ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff) | ||
| 227 | |||
| 228 | /** | ||
| 229 | * Register: HW_RTC_PERSISTENT2 | ||
| 230 | * Address: 0x80 | ||
| 231 | * SCT: yes | ||
| 232 | */ | ||
| 233 | #define HW_RTC_PERSISTENT2 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0)) | ||
| 234 | #define HW_RTC_PERSISTENT2_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4)) | ||
| 235 | #define HW_RTC_PERSISTENT2_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8)) | ||
| 236 | #define HW_RTC_PERSISTENT2_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc)) | ||
| 237 | #define BP_RTC_PERSISTENT2_GENERAL 0 | ||
| 238 | #define BM_RTC_PERSISTENT2_GENERAL 0xffffffff | ||
| 239 | #define BF_RTC_PERSISTENT2_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
| 240 | |||
| 241 | /** | ||
| 242 | * Register: HW_RTC_PERSISTENT3 | ||
| 243 | * Address: 0x90 | ||
| 244 | * SCT: yes | ||
| 245 | */ | ||
| 246 | #define HW_RTC_PERSISTENT3 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0)) | ||
| 247 | #define HW_RTC_PERSISTENT3_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4)) | ||
| 248 | #define HW_RTC_PERSISTENT3_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8)) | ||
| 249 | #define HW_RTC_PERSISTENT3_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc)) | ||
| 250 | #define BP_RTC_PERSISTENT3_GENERAL 0 | ||
| 251 | #define BM_RTC_PERSISTENT3_GENERAL 0xffffffff | ||
| 252 | #define BF_RTC_PERSISTENT3_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
| 253 | |||
| 254 | /** | ||
| 255 | * Register: HW_RTC_PERSISTENT4 | ||
| 256 | * Address: 0xa0 | ||
| 257 | * SCT: yes | ||
| 258 | */ | ||
| 259 | #define HW_RTC_PERSISTENT4 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0)) | ||
| 260 | #define HW_RTC_PERSISTENT4_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4)) | ||
| 261 | #define HW_RTC_PERSISTENT4_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8)) | ||
| 262 | #define HW_RTC_PERSISTENT4_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc)) | ||
| 263 | #define BP_RTC_PERSISTENT4_GENERAL 0 | ||
| 264 | #define BM_RTC_PERSISTENT4_GENERAL 0xffffffff | ||
| 265 | #define BF_RTC_PERSISTENT4_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
| 266 | |||
| 267 | /** | ||
| 268 | * Register: HW_RTC_PERSISTENT5 | ||
| 269 | * Address: 0xb0 | ||
| 270 | * SCT: yes | ||
| 271 | */ | ||
| 272 | #define HW_RTC_PERSISTENT5 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0)) | ||
| 273 | #define HW_RTC_PERSISTENT5_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4)) | ||
| 274 | #define HW_RTC_PERSISTENT5_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8)) | ||
| 275 | #define HW_RTC_PERSISTENT5_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc)) | ||
| 276 | #define BP_RTC_PERSISTENT5_GENERAL 0 | ||
| 277 | #define BM_RTC_PERSISTENT5_GENERAL 0xffffffff | ||
| 278 | #define BF_RTC_PERSISTENT5_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
| 279 | |||
| 280 | /** | ||
| 281 | * Register: HW_RTC_DEBUG | ||
| 282 | * Address: 0xc0 | ||
| 283 | * SCT: yes | ||
| 284 | */ | ||
| 285 | #define HW_RTC_DEBUG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0)) | ||
| 286 | #define HW_RTC_DEBUG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4)) | ||
| 287 | #define HW_RTC_DEBUG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8)) | ||
| 288 | #define HW_RTC_DEBUG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc)) | ||
| 289 | #define BP_RTC_DEBUG_WATCHDOG_RESET_MASK 1 | ||
| 290 | #define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x2 | ||
| 291 | #define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2) | ||
| 292 | #define BP_RTC_DEBUG_WATCHDOG_RESET 0 | ||
| 293 | #define BM_RTC_DEBUG_WATCHDOG_RESET 0x1 | ||
| 294 | #define BF_RTC_DEBUG_WATCHDOG_RESET(v) (((v) << 0) & 0x1) | ||
| 295 | |||
| 296 | /** | ||
| 297 | * Register: HW_RTC_VERSION | ||
| 298 | * Address: 0xd0 | ||
| 299 | * SCT: no | ||
| 300 | */ | ||
| 301 | #define HW_RTC_VERSION (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0)) | ||
| 302 | #define BP_RTC_VERSION_MAJOR 24 | ||
| 303 | #define BM_RTC_VERSION_MAJOR 0xff000000 | ||
| 304 | #define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 305 | #define BP_RTC_VERSION_MINOR 16 | ||
| 306 | #define BM_RTC_VERSION_MINOR 0xff0000 | ||
| 307 | #define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 308 | #define BP_RTC_VERSION_STEP 0 | ||
| 309 | #define BM_RTC_VERSION_STEP 0xffff | ||
| 310 | #define BF_RTC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 311 | |||
| 312 | #endif /* __HEADERGEN__STMP3700__RTC__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h new file mode 100644 index 0000000000..01faeabc62 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-saif.h | |||
| @@ -0,0 +1,154 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__SAIF__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__SAIF__H__ | ||
| 25 | |||
| 26 | #define REGS_SAIF_BASE(i) ((i) == 1 ? 0x80042000 : 0x80046000) | ||
| 27 | |||
| 28 | #define REGS_SAIF_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_SAIF_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_SAIF_CTRL(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x0)) | ||
| 36 | #define HW_SAIF_CTRL_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x4)) | ||
| 37 | #define HW_SAIF_CTRL_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0x8)) | ||
| 38 | #define HW_SAIF_CTRL_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x0 + 0xc)) | ||
| 39 | #define BP_SAIF_CTRL_SFTRST 31 | ||
| 40 | #define BM_SAIF_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_SAIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_SAIF_CTRL_CLKGATE 30 | ||
| 43 | #define BM_SAIF_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_SAIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 | ||
| 46 | #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 | ||
| 47 | #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) (((v) << 27) & 0x38000000) | ||
| 48 | #define BP_SAIF_CTRL_BITCLK_BASE_RATE 26 | ||
| 49 | #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x4000000 | ||
| 50 | #define BF_SAIF_CTRL_BITCLK_BASE_RATE(v) (((v) << 26) & 0x4000000) | ||
| 51 | #define BP_SAIF_CTRL_FIFO_ERROR_IRQ_EN 25 | ||
| 52 | #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x2000000 | ||
| 53 | #define BF_SAIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 25) & 0x2000000) | ||
| 54 | #define BP_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 24 | ||
| 55 | #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x1000000 | ||
| 56 | #define BF_SAIF_CTRL_FIFO_SERVICE_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
| 57 | #define BP_SAIF_CTRL_DMAWAIT_COUNT 16 | ||
| 58 | #define BM_SAIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
| 59 | #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 60 | #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 | ||
| 61 | #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0xc000 | ||
| 62 | #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) (((v) << 14) & 0xc000) | ||
| 63 | #define BP_SAIF_CTRL_BIT_ORDER 12 | ||
| 64 | #define BM_SAIF_CTRL_BIT_ORDER 0x1000 | ||
| 65 | #define BF_SAIF_CTRL_BIT_ORDER(v) (((v) << 12) & 0x1000) | ||
| 66 | #define BP_SAIF_CTRL_DELAY 11 | ||
| 67 | #define BM_SAIF_CTRL_DELAY 0x800 | ||
| 68 | #define BF_SAIF_CTRL_DELAY(v) (((v) << 11) & 0x800) | ||
| 69 | #define BP_SAIF_CTRL_JUSTIFY 10 | ||
| 70 | #define BM_SAIF_CTRL_JUSTIFY 0x400 | ||
| 71 | #define BF_SAIF_CTRL_JUSTIFY(v) (((v) << 10) & 0x400) | ||
| 72 | #define BP_SAIF_CTRL_LRCLK_POLARITY 9 | ||
| 73 | #define BM_SAIF_CTRL_LRCLK_POLARITY 0x200 | ||
| 74 | #define BF_SAIF_CTRL_LRCLK_POLARITY(v) (((v) << 9) & 0x200) | ||
| 75 | #define BP_SAIF_CTRL_BITCLK_EDGE 8 | ||
| 76 | #define BM_SAIF_CTRL_BITCLK_EDGE 0x100 | ||
| 77 | #define BF_SAIF_CTRL_BITCLK_EDGE(v) (((v) << 8) & 0x100) | ||
| 78 | #define BP_SAIF_CTRL_WORD_LENGTH 4 | ||
| 79 | #define BM_SAIF_CTRL_WORD_LENGTH 0xf0 | ||
| 80 | #define BF_SAIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
| 81 | #define BP_SAIF_CTRL_BITCLK_48XFS_ENABLE 3 | ||
| 82 | #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x8 | ||
| 83 | #define BF_SAIF_CTRL_BITCLK_48XFS_ENABLE(v) (((v) << 3) & 0x8) | ||
| 84 | #define BP_SAIF_CTRL_SLAVE_MODE 2 | ||
| 85 | #define BM_SAIF_CTRL_SLAVE_MODE 0x4 | ||
| 86 | #define BF_SAIF_CTRL_SLAVE_MODE(v) (((v) << 2) & 0x4) | ||
| 87 | #define BP_SAIF_CTRL_READ_MODE 1 | ||
| 88 | #define BM_SAIF_CTRL_READ_MODE 0x2 | ||
| 89 | #define BF_SAIF_CTRL_READ_MODE(v) (((v) << 1) & 0x2) | ||
| 90 | #define BP_SAIF_CTRL_RUN 0 | ||
| 91 | #define BM_SAIF_CTRL_RUN 0x1 | ||
| 92 | #define BF_SAIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 93 | |||
| 94 | /** | ||
| 95 | * Register: HW_SAIF_STAT | ||
| 96 | * Address: 0x10 | ||
| 97 | * SCT: yes | ||
| 98 | */ | ||
| 99 | #define HW_SAIF_STAT(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x0)) | ||
| 100 | #define HW_SAIF_STAT_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x4)) | ||
| 101 | #define HW_SAIF_STAT_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0x8)) | ||
| 102 | #define HW_SAIF_STAT_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x10 + 0xc)) | ||
| 103 | #define BP_SAIF_STAT_PRESENT 31 | ||
| 104 | #define BM_SAIF_STAT_PRESENT 0x80000000 | ||
| 105 | #define BF_SAIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 106 | #define BP_SAIF_STAT_DMA_PREQ 16 | ||
| 107 | #define BM_SAIF_STAT_DMA_PREQ 0x10000 | ||
| 108 | #define BF_SAIF_STAT_DMA_PREQ(v) (((v) << 16) & 0x10000) | ||
| 109 | #define BP_SAIF_STAT_FIFO_UNDERFLOW_IRQ 6 | ||
| 110 | #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x40 | ||
| 111 | #define BF_SAIF_STAT_FIFO_UNDERFLOW_IRQ(v) (((v) << 6) & 0x40) | ||
| 112 | #define BP_SAIF_STAT_FIFO_OVERFLOW_IRQ 5 | ||
| 113 | #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x20 | ||
| 114 | #define BF_SAIF_STAT_FIFO_OVERFLOW_IRQ(v) (((v) << 5) & 0x20) | ||
| 115 | #define BP_SAIF_STAT_FIFO_SERVICE_IRQ 4 | ||
| 116 | #define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x10 | ||
| 117 | #define BF_SAIF_STAT_FIFO_SERVICE_IRQ(v) (((v) << 4) & 0x10) | ||
| 118 | #define BP_SAIF_STAT_BUSY 0 | ||
| 119 | #define BM_SAIF_STAT_BUSY 0x1 | ||
| 120 | #define BF_SAIF_STAT_BUSY(v) (((v) << 0) & 0x1) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_SAIF_DATA | ||
| 124 | * Address: 0x20 | ||
| 125 | * SCT: yes | ||
| 126 | */ | ||
| 127 | #define HW_SAIF_DATA(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x0)) | ||
| 128 | #define HW_SAIF_DATA_SET(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x4)) | ||
| 129 | #define HW_SAIF_DATA_CLR(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0x8)) | ||
| 130 | #define HW_SAIF_DATA_TOG(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x20 + 0xc)) | ||
| 131 | #define BP_SAIF_DATA_PCM_RIGHT 16 | ||
| 132 | #define BM_SAIF_DATA_PCM_RIGHT 0xffff0000 | ||
| 133 | #define BF_SAIF_DATA_PCM_RIGHT(v) (((v) << 16) & 0xffff0000) | ||
| 134 | #define BP_SAIF_DATA_PCM_LEFT 0 | ||
| 135 | #define BM_SAIF_DATA_PCM_LEFT 0xffff | ||
| 136 | #define BF_SAIF_DATA_PCM_LEFT(v) (((v) << 0) & 0xffff) | ||
| 137 | |||
| 138 | /** | ||
| 139 | * Register: HW_SAIF_VERSION | ||
| 140 | * Address: 0x30 | ||
| 141 | * SCT: no | ||
| 142 | */ | ||
| 143 | #define HW_SAIF_VERSION(d) (*(volatile unsigned long *)(REGS_SAIF_BASE(d) + 0x30)) | ||
| 144 | #define BP_SAIF_VERSION_MAJOR 24 | ||
| 145 | #define BM_SAIF_VERSION_MAJOR 0xff000000 | ||
| 146 | #define BF_SAIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 147 | #define BP_SAIF_VERSION_MINOR 16 | ||
| 148 | #define BM_SAIF_VERSION_MINOR 0xff0000 | ||
| 149 | #define BF_SAIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 150 | #define BP_SAIF_VERSION_STEP 0 | ||
| 151 | #define BM_SAIF_VERSION_STEP 0xffff | ||
| 152 | #define BF_SAIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 153 | |||
| 154 | #endif /* __HEADERGEN__STMP3700__SAIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h new file mode 100644 index 0000000000..4d58761ba9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-spdif.h | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__SPDIF__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__SPDIF__H__ | ||
| 25 | |||
| 26 | #define REGS_SPDIF_BASE (0x80054000) | ||
| 27 | |||
| 28 | #define REGS_SPDIF_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_SPDIF_CTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_SPDIF_CTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_SPDIF_CTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_SPDIF_CTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_SPDIF_CTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_SPDIF_CTRL_SFTRST 31 | ||
| 40 | #define BM_SPDIF_CTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_SPDIF_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_SPDIF_CTRL_CLKGATE 30 | ||
| 43 | #define BM_SPDIF_CTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_SPDIF_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 | ||
| 46 | #define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x1f0000 | ||
| 47 | #define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) (((v) << 16) & 0x1f0000) | ||
| 48 | #define BP_SPDIF_CTRL_WAIT_END_XFER 5 | ||
| 49 | #define BM_SPDIF_CTRL_WAIT_END_XFER 0x20 | ||
| 50 | #define BF_SPDIF_CTRL_WAIT_END_XFER(v) (((v) << 5) & 0x20) | ||
| 51 | #define BP_SPDIF_CTRL_WORD_LENGTH 4 | ||
| 52 | #define BM_SPDIF_CTRL_WORD_LENGTH 0x10 | ||
| 53 | #define BF_SPDIF_CTRL_WORD_LENGTH(v) (((v) << 4) & 0x10) | ||
| 54 | #define BP_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 3 | ||
| 55 | #define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x8 | ||
| 56 | #define BF_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) << 3) & 0x8) | ||
| 57 | #define BP_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 2 | ||
| 58 | #define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x4 | ||
| 59 | #define BF_SPDIF_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) << 2) & 0x4) | ||
| 60 | #define BP_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 1 | ||
| 61 | #define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x2 | ||
| 62 | #define BF_SPDIF_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) << 1) & 0x2) | ||
| 63 | #define BP_SPDIF_CTRL_RUN 0 | ||
| 64 | #define BM_SPDIF_CTRL_RUN 0x1 | ||
| 65 | #define BF_SPDIF_CTRL_RUN(v) (((v) << 0) & 0x1) | ||
| 66 | |||
| 67 | /** | ||
| 68 | * Register: HW_SPDIF_STAT | ||
| 69 | * Address: 0x10 | ||
| 70 | * SCT: no | ||
| 71 | */ | ||
| 72 | #define HW_SPDIF_STAT (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x10)) | ||
| 73 | #define BP_SPDIF_STAT_PRESENT 31 | ||
| 74 | #define BM_SPDIF_STAT_PRESENT 0x80000000 | ||
| 75 | #define BF_SPDIF_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 76 | #define BP_SPDIF_STAT_END_XFER 0 | ||
| 77 | #define BM_SPDIF_STAT_END_XFER 0x1 | ||
| 78 | #define BF_SPDIF_STAT_END_XFER(v) (((v) << 0) & 0x1) | ||
| 79 | |||
| 80 | /** | ||
| 81 | * Register: HW_SPDIF_FRAMECTRL | ||
| 82 | * Address: 0x20 | ||
| 83 | * SCT: yes | ||
| 84 | */ | ||
| 85 | #define HW_SPDIF_FRAMECTRL (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x0)) | ||
| 86 | #define HW_SPDIF_FRAMECTRL_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x4)) | ||
| 87 | #define HW_SPDIF_FRAMECTRL_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0x8)) | ||
| 88 | #define HW_SPDIF_FRAMECTRL_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x20 + 0xc)) | ||
| 89 | #define BP_SPDIF_FRAMECTRL_V_CONFIG 17 | ||
| 90 | #define BM_SPDIF_FRAMECTRL_V_CONFIG 0x20000 | ||
| 91 | #define BF_SPDIF_FRAMECTRL_V_CONFIG(v) (((v) << 17) & 0x20000) | ||
| 92 | #define BP_SPDIF_FRAMECTRL_AUTO_MUTE 16 | ||
| 93 | #define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x10000 | ||
| 94 | #define BF_SPDIF_FRAMECTRL_AUTO_MUTE(v) (((v) << 16) & 0x10000) | ||
| 95 | #define BP_SPDIF_FRAMECTRL_USER_DATA 14 | ||
| 96 | #define BM_SPDIF_FRAMECTRL_USER_DATA 0x4000 | ||
| 97 | #define BF_SPDIF_FRAMECTRL_USER_DATA(v) (((v) << 14) & 0x4000) | ||
| 98 | #define BP_SPDIF_FRAMECTRL_V 13 | ||
| 99 | #define BM_SPDIF_FRAMECTRL_V 0x2000 | ||
| 100 | #define BF_SPDIF_FRAMECTRL_V(v) (((v) << 13) & 0x2000) | ||
| 101 | #define BP_SPDIF_FRAMECTRL_L 12 | ||
| 102 | #define BM_SPDIF_FRAMECTRL_L 0x1000 | ||
| 103 | #define BF_SPDIF_FRAMECTRL_L(v) (((v) << 12) & 0x1000) | ||
| 104 | #define BP_SPDIF_FRAMECTRL_CC 4 | ||
| 105 | #define BM_SPDIF_FRAMECTRL_CC 0x7f0 | ||
| 106 | #define BF_SPDIF_FRAMECTRL_CC(v) (((v) << 4) & 0x7f0) | ||
| 107 | #define BP_SPDIF_FRAMECTRL_PRE 3 | ||
| 108 | #define BM_SPDIF_FRAMECTRL_PRE 0x8 | ||
| 109 | #define BF_SPDIF_FRAMECTRL_PRE(v) (((v) << 3) & 0x8) | ||
| 110 | #define BP_SPDIF_FRAMECTRL_COPY 2 | ||
| 111 | #define BM_SPDIF_FRAMECTRL_COPY 0x4 | ||
| 112 | #define BF_SPDIF_FRAMECTRL_COPY(v) (((v) << 2) & 0x4) | ||
| 113 | #define BP_SPDIF_FRAMECTRL_AUDIO 1 | ||
| 114 | #define BM_SPDIF_FRAMECTRL_AUDIO 0x2 | ||
| 115 | #define BF_SPDIF_FRAMECTRL_AUDIO(v) (((v) << 1) & 0x2) | ||
| 116 | #define BP_SPDIF_FRAMECTRL_PRO 0 | ||
| 117 | #define BM_SPDIF_FRAMECTRL_PRO 0x1 | ||
| 118 | #define BF_SPDIF_FRAMECTRL_PRO(v) (((v) << 0) & 0x1) | ||
| 119 | |||
| 120 | /** | ||
| 121 | * Register: HW_SPDIF_SRR | ||
| 122 | * Address: 0x30 | ||
| 123 | * SCT: yes | ||
| 124 | */ | ||
| 125 | #define HW_SPDIF_SRR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x0)) | ||
| 126 | #define HW_SPDIF_SRR_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x4)) | ||
| 127 | #define HW_SPDIF_SRR_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0x8)) | ||
| 128 | #define HW_SPDIF_SRR_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x30 + 0xc)) | ||
| 129 | #define BP_SPDIF_SRR_BASEMULT 28 | ||
| 130 | #define BM_SPDIF_SRR_BASEMULT 0x70000000 | ||
| 131 | #define BF_SPDIF_SRR_BASEMULT(v) (((v) << 28) & 0x70000000) | ||
| 132 | #define BP_SPDIF_SRR_RATE 0 | ||
| 133 | #define BM_SPDIF_SRR_RATE 0xfffff | ||
| 134 | #define BF_SPDIF_SRR_RATE(v) (((v) << 0) & 0xfffff) | ||
| 135 | |||
| 136 | /** | ||
| 137 | * Register: HW_SPDIF_DEBUG | ||
| 138 | * Address: 0x40 | ||
| 139 | * SCT: no | ||
| 140 | */ | ||
| 141 | #define HW_SPDIF_DEBUG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x40)) | ||
| 142 | #define BP_SPDIF_DEBUG_DMA_PREQ 1 | ||
| 143 | #define BM_SPDIF_DEBUG_DMA_PREQ 0x2 | ||
| 144 | #define BF_SPDIF_DEBUG_DMA_PREQ(v) (((v) << 1) & 0x2) | ||
| 145 | #define BP_SPDIF_DEBUG_FIFO_STATUS 0 | ||
| 146 | #define BM_SPDIF_DEBUG_FIFO_STATUS 0x1 | ||
| 147 | #define BF_SPDIF_DEBUG_FIFO_STATUS(v) (((v) << 0) & 0x1) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_SPDIF_DATA | ||
| 151 | * Address: 0x50 | ||
| 152 | * SCT: yes | ||
| 153 | */ | ||
| 154 | #define HW_SPDIF_DATA (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x0)) | ||
| 155 | #define HW_SPDIF_DATA_SET (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x4)) | ||
| 156 | #define HW_SPDIF_DATA_CLR (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0x8)) | ||
| 157 | #define HW_SPDIF_DATA_TOG (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x50 + 0xc)) | ||
| 158 | #define BP_SPDIF_DATA_HIGH 16 | ||
| 159 | #define BM_SPDIF_DATA_HIGH 0xffff0000 | ||
| 160 | #define BF_SPDIF_DATA_HIGH(v) (((v) << 16) & 0xffff0000) | ||
| 161 | #define BP_SPDIF_DATA_LOW 0 | ||
| 162 | #define BM_SPDIF_DATA_LOW 0xffff | ||
| 163 | #define BF_SPDIF_DATA_LOW(v) (((v) << 0) & 0xffff) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_SPDIF_VERSION | ||
| 167 | * Address: 0x60 | ||
| 168 | * SCT: no | ||
| 169 | */ | ||
| 170 | #define HW_SPDIF_VERSION (*(volatile unsigned long *)(REGS_SPDIF_BASE + 0x60)) | ||
| 171 | #define BP_SPDIF_VERSION_MAJOR 24 | ||
| 172 | #define BM_SPDIF_VERSION_MAJOR 0xff000000 | ||
| 173 | #define BF_SPDIF_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 174 | #define BP_SPDIF_VERSION_MINOR 16 | ||
| 175 | #define BM_SPDIF_VERSION_MINOR 0xff0000 | ||
| 176 | #define BF_SPDIF_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 177 | #define BP_SPDIF_VERSION_STEP 0 | ||
| 178 | #define BM_SPDIF_VERSION_STEP 0xffff | ||
| 179 | #define BF_SPDIF_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 180 | |||
| 181 | #endif /* __HEADERGEN__STMP3700__SPDIF__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h new file mode 100644 index 0000000000..463cf26cf7 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-ssp.h | |||
| @@ -0,0 +1,558 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__SSP__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__SSP__H__ | ||
| 25 | |||
| 26 | #define REGS_SSP_BASE(i) ((i) == 1 ? 0x80010000 : 0x80034000) | ||
| 27 | |||
| 28 | #define REGS_SSP_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_SSP_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_SSP_CTRL0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x0)) | ||
| 36 | #define HW_SSP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x4)) | ||
| 37 | #define HW_SSP_CTRL0_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0x8)) | ||
| 38 | #define HW_SSP_CTRL0_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x0 + 0xc)) | ||
| 39 | #define BP_SSP_CTRL0_SFTRST 31 | ||
| 40 | #define BM_SSP_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_SSP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_SSP_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_SSP_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_SSP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_SSP_CTRL0_RUN 29 | ||
| 46 | #define BM_SSP_CTRL0_RUN 0x20000000 | ||
| 47 | #define BF_SSP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_SSP_CTRL0_SDIO_IRQ_CHECK 28 | ||
| 49 | #define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 | ||
| 50 | #define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_SSP_CTRL0_LOCK_CS 27 | ||
| 52 | #define BM_SSP_CTRL0_LOCK_CS 0x8000000 | ||
| 53 | #define BF_SSP_CTRL0_LOCK_CS(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_SSP_CTRL0_IGNORE_CRC 26 | ||
| 55 | #define BM_SSP_CTRL0_IGNORE_CRC 0x4000000 | ||
| 56 | #define BF_SSP_CTRL0_IGNORE_CRC(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_SSP_CTRL0_READ 25 | ||
| 58 | #define BM_SSP_CTRL0_READ 0x2000000 | ||
| 59 | #define BF_SSP_CTRL0_READ(v) (((v) << 25) & 0x2000000) | ||
| 60 | #define BP_SSP_CTRL0_DATA_XFER 24 | ||
| 61 | #define BM_SSP_CTRL0_DATA_XFER 0x1000000 | ||
| 62 | #define BF_SSP_CTRL0_DATA_XFER(v) (((v) << 24) & 0x1000000) | ||
| 63 | #define BP_SSP_CTRL0_BUS_WIDTH 22 | ||
| 64 | #define BM_SSP_CTRL0_BUS_WIDTH 0xc00000 | ||
| 65 | #define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 | ||
| 66 | #define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 | ||
| 67 | #define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 | ||
| 68 | #define BF_SSP_CTRL0_BUS_WIDTH(v) (((v) << 22) & 0xc00000) | ||
| 69 | #define BF_SSP_CTRL0_BUS_WIDTH_V(v) ((BV_SSP_CTRL0_BUS_WIDTH__##v << 22) & 0xc00000) | ||
| 70 | #define BP_SSP_CTRL0_WAIT_FOR_IRQ 21 | ||
| 71 | #define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x200000 | ||
| 72 | #define BF_SSP_CTRL0_WAIT_FOR_IRQ(v) (((v) << 21) & 0x200000) | ||
| 73 | #define BP_SSP_CTRL0_WAIT_FOR_CMD 20 | ||
| 74 | #define BM_SSP_CTRL0_WAIT_FOR_CMD 0x100000 | ||
| 75 | #define BF_SSP_CTRL0_WAIT_FOR_CMD(v) (((v) << 20) & 0x100000) | ||
| 76 | #define BP_SSP_CTRL0_LONG_RESP 19 | ||
| 77 | #define BM_SSP_CTRL0_LONG_RESP 0x80000 | ||
| 78 | #define BF_SSP_CTRL0_LONG_RESP(v) (((v) << 19) & 0x80000) | ||
| 79 | #define BP_SSP_CTRL0_CHECK_RESP 18 | ||
| 80 | #define BM_SSP_CTRL0_CHECK_RESP 0x40000 | ||
| 81 | #define BF_SSP_CTRL0_CHECK_RESP(v) (((v) << 18) & 0x40000) | ||
| 82 | #define BP_SSP_CTRL0_GET_RESP 17 | ||
| 83 | #define BM_SSP_CTRL0_GET_RESP 0x20000 | ||
| 84 | #define BF_SSP_CTRL0_GET_RESP(v) (((v) << 17) & 0x20000) | ||
| 85 | #define BP_SSP_CTRL0_ENABLE 16 | ||
| 86 | #define BM_SSP_CTRL0_ENABLE 0x10000 | ||
| 87 | #define BF_SSP_CTRL0_ENABLE(v) (((v) << 16) & 0x10000) | ||
| 88 | #define BP_SSP_CTRL0_XFER_COUNT 0 | ||
| 89 | #define BM_SSP_CTRL0_XFER_COUNT 0xffff | ||
| 90 | #define BF_SSP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 91 | |||
| 92 | /** | ||
| 93 | * Register: HW_SSP_CMD0 | ||
| 94 | * Address: 0x10 | ||
| 95 | * SCT: yes | ||
| 96 | */ | ||
| 97 | #define HW_SSP_CMD0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x0)) | ||
| 98 | #define HW_SSP_CMD0_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x4)) | ||
| 99 | #define HW_SSP_CMD0_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0x8)) | ||
| 100 | #define HW_SSP_CMD0_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x10 + 0xc)) | ||
| 101 | #define BP_SSP_CMD0_APPEND_8CYC 20 | ||
| 102 | #define BM_SSP_CMD0_APPEND_8CYC 0x100000 | ||
| 103 | #define BF_SSP_CMD0_APPEND_8CYC(v) (((v) << 20) & 0x100000) | ||
| 104 | #define BP_SSP_CMD0_BLOCK_SIZE 16 | ||
| 105 | #define BM_SSP_CMD0_BLOCK_SIZE 0xf0000 | ||
| 106 | #define BF_SSP_CMD0_BLOCK_SIZE(v) (((v) << 16) & 0xf0000) | ||
| 107 | #define BP_SSP_CMD0_BLOCK_COUNT 8 | ||
| 108 | #define BM_SSP_CMD0_BLOCK_COUNT 0xff00 | ||
| 109 | #define BF_SSP_CMD0_BLOCK_COUNT(v) (((v) << 8) & 0xff00) | ||
| 110 | #define BP_SSP_CMD0_CMD 0 | ||
| 111 | #define BM_SSP_CMD0_CMD 0xff | ||
| 112 | #define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x0 | ||
| 113 | #define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x1 | ||
| 114 | #define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x2 | ||
| 115 | #define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x3 | ||
| 116 | #define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x4 | ||
| 117 | #define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x5 | ||
| 118 | #define BV_SSP_CMD0_CMD__MMC_SWITCH 0x6 | ||
| 119 | #define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x7 | ||
| 120 | #define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x8 | ||
| 121 | #define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x9 | ||
| 122 | #define BV_SSP_CMD0_CMD__MMC_SEND_CID 0xa | ||
| 123 | #define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0xb | ||
| 124 | #define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0xc | ||
| 125 | #define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0xd | ||
| 126 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0xe | ||
| 127 | #define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0xf | ||
| 128 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 | ||
| 129 | #define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 | ||
| 130 | #define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 | ||
| 131 | #define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 | ||
| 132 | #define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 | ||
| 133 | #define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 | ||
| 134 | #define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 | ||
| 135 | #define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 | ||
| 136 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1a | ||
| 137 | #define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1b | ||
| 138 | #define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1c | ||
| 139 | #define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1d | ||
| 140 | #define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1e | ||
| 141 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 | ||
| 142 | #define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 | ||
| 143 | #define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 | ||
| 144 | #define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 | ||
| 145 | #define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 | ||
| 146 | #define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2a | ||
| 147 | #define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 | ||
| 148 | #define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 | ||
| 149 | #define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x0 | ||
| 150 | #define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x2 | ||
| 151 | #define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x3 | ||
| 152 | #define BV_SSP_CMD0_CMD__SD_SET_DSR 0x4 | ||
| 153 | #define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x5 | ||
| 154 | #define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x7 | ||
| 155 | #define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x9 | ||
| 156 | #define BV_SSP_CMD0_CMD__SD_SEND_CID 0xa | ||
| 157 | #define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0xc | ||
| 158 | #define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0xd | ||
| 159 | #define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0xf | ||
| 160 | #define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 | ||
| 161 | #define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 | ||
| 162 | #define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 | ||
| 163 | #define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 | ||
| 164 | #define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 | ||
| 165 | #define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1b | ||
| 166 | #define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1c | ||
| 167 | #define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1d | ||
| 168 | #define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1e | ||
| 169 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 | ||
| 170 | #define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 | ||
| 171 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 | ||
| 172 | #define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 | ||
| 173 | #define BV_SSP_CMD0_CMD__SD_ERASE 0x26 | ||
| 174 | #define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2a | ||
| 175 | #define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 | ||
| 176 | #define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 | ||
| 177 | #define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 | ||
| 178 | #define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 | ||
| 179 | #define BF_SSP_CMD0_CMD(v) (((v) << 0) & 0xff) | ||
| 180 | #define BF_SSP_CMD0_CMD_V(v) ((BV_SSP_CMD0_CMD__##v << 0) & 0xff) | ||
| 181 | |||
| 182 | /** | ||
| 183 | * Register: HW_SSP_CMD1 | ||
| 184 | * Address: 0x20 | ||
| 185 | * SCT: no | ||
| 186 | */ | ||
| 187 | #define HW_SSP_CMD1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x20)) | ||
| 188 | #define BP_SSP_CMD1_CMD_ARG 0 | ||
| 189 | #define BM_SSP_CMD1_CMD_ARG 0xffffffff | ||
| 190 | #define BF_SSP_CMD1_CMD_ARG(v) (((v) << 0) & 0xffffffff) | ||
| 191 | |||
| 192 | /** | ||
| 193 | * Register: HW_SSP_COMPREF | ||
| 194 | * Address: 0x30 | ||
| 195 | * SCT: no | ||
| 196 | */ | ||
| 197 | #define HW_SSP_COMPREF(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x30)) | ||
| 198 | #define BP_SSP_COMPREF_REFERENCE 0 | ||
| 199 | #define BM_SSP_COMPREF_REFERENCE 0xffffffff | ||
| 200 | #define BF_SSP_COMPREF_REFERENCE(v) (((v) << 0) & 0xffffffff) | ||
| 201 | |||
| 202 | /** | ||
| 203 | * Register: HW_SSP_COMPMASK | ||
| 204 | * Address: 0x40 | ||
| 205 | * SCT: no | ||
| 206 | */ | ||
| 207 | #define HW_SSP_COMPMASK(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x40)) | ||
| 208 | #define BP_SSP_COMPMASK_MASK 0 | ||
| 209 | #define BM_SSP_COMPMASK_MASK 0xffffffff | ||
| 210 | #define BF_SSP_COMPMASK_MASK(v) (((v) << 0) & 0xffffffff) | ||
| 211 | |||
| 212 | /** | ||
| 213 | * Register: HW_SSP_TIMING | ||
| 214 | * Address: 0x50 | ||
| 215 | * SCT: no | ||
| 216 | */ | ||
| 217 | #define HW_SSP_TIMING(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x50)) | ||
| 218 | #define BP_SSP_TIMING_TIMEOUT 16 | ||
| 219 | #define BM_SSP_TIMING_TIMEOUT 0xffff0000 | ||
| 220 | #define BF_SSP_TIMING_TIMEOUT(v) (((v) << 16) & 0xffff0000) | ||
| 221 | #define BP_SSP_TIMING_CLOCK_DIVIDE 8 | ||
| 222 | #define BM_SSP_TIMING_CLOCK_DIVIDE 0xff00 | ||
| 223 | #define BF_SSP_TIMING_CLOCK_DIVIDE(v) (((v) << 8) & 0xff00) | ||
| 224 | #define BP_SSP_TIMING_CLOCK_RATE 0 | ||
| 225 | #define BM_SSP_TIMING_CLOCK_RATE 0xff | ||
| 226 | #define BF_SSP_TIMING_CLOCK_RATE(v) (((v) << 0) & 0xff) | ||
| 227 | |||
| 228 | /** | ||
| 229 | * Register: HW_SSP_CTRL1 | ||
| 230 | * Address: 0x60 | ||
| 231 | * SCT: yes | ||
| 232 | */ | ||
| 233 | #define HW_SSP_CTRL1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x0)) | ||
| 234 | #define HW_SSP_CTRL1_SET(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x4)) | ||
| 235 | #define HW_SSP_CTRL1_CLR(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0x8)) | ||
| 236 | #define HW_SSP_CTRL1_TOG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x60 + 0xc)) | ||
| 237 | #define BP_SSP_CTRL1_SDIO_IRQ 31 | ||
| 238 | #define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 | ||
| 239 | #define BF_SSP_CTRL1_SDIO_IRQ(v) (((v) << 31) & 0x80000000) | ||
| 240 | #define BP_SSP_CTRL1_SDIO_IRQ_EN 30 | ||
| 241 | #define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 | ||
| 242 | #define BF_SSP_CTRL1_SDIO_IRQ_EN(v) (((v) << 30) & 0x40000000) | ||
| 243 | #define BP_SSP_CTRL1_RESP_ERR_IRQ 29 | ||
| 244 | #define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 | ||
| 245 | #define BF_SSP_CTRL1_RESP_ERR_IRQ(v) (((v) << 29) & 0x20000000) | ||
| 246 | #define BP_SSP_CTRL1_RESP_ERR_IRQ_EN 28 | ||
| 247 | #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 | ||
| 248 | #define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v) (((v) << 28) & 0x10000000) | ||
| 249 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ 27 | ||
| 250 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x8000000 | ||
| 251 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v) (((v) << 27) & 0x8000000) | ||
| 252 | #define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 26 | ||
| 253 | #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x4000000 | ||
| 254 | #define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v) (((v) << 26) & 0x4000000) | ||
| 255 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ 25 | ||
| 256 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x2000000 | ||
| 257 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v) (((v) << 25) & 0x2000000) | ||
| 258 | #define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 24 | ||
| 259 | #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x1000000 | ||
| 260 | #define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v) (((v) << 24) & 0x1000000) | ||
| 261 | #define BP_SSP_CTRL1_DATA_CRC_IRQ 23 | ||
| 262 | #define BM_SSP_CTRL1_DATA_CRC_IRQ 0x800000 | ||
| 263 | #define BF_SSP_CTRL1_DATA_CRC_IRQ(v) (((v) << 23) & 0x800000) | ||
| 264 | #define BP_SSP_CTRL1_DATA_CRC_IRQ_EN 22 | ||
| 265 | #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x400000 | ||
| 266 | #define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v) (((v) << 22) & 0x400000) | ||
| 267 | #define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ 21 | ||
| 268 | #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x200000 | ||
| 269 | #define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v) (((v) << 21) & 0x200000) | ||
| 270 | #define BP_SSP_CTRL1_FIFO_UNDERRUN_EN 20 | ||
| 271 | #define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x100000 | ||
| 272 | #define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v) (((v) << 20) & 0x100000) | ||
| 273 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ 19 | ||
| 274 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x80000 | ||
| 275 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v) (((v) << 19) & 0x80000) | ||
| 276 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 18 | ||
| 277 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x40000 | ||
| 278 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v) (((v) << 18) & 0x40000) | ||
| 279 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ 17 | ||
| 280 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x20000 | ||
| 281 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v) (((v) << 17) & 0x20000) | ||
| 282 | #define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 16 | ||
| 283 | #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x10000 | ||
| 284 | #define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v) (((v) << 16) & 0x10000) | ||
| 285 | #define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ 15 | ||
| 286 | #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x8000 | ||
| 287 | #define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v) (((v) << 15) & 0x8000) | ||
| 288 | #define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 14 | ||
| 289 | #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x4000 | ||
| 290 | #define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 291 | #define BP_SSP_CTRL1_DMA_ENABLE 13 | ||
| 292 | #define BM_SSP_CTRL1_DMA_ENABLE 0x2000 | ||
| 293 | #define BF_SSP_CTRL1_DMA_ENABLE(v) (((v) << 13) & 0x2000) | ||
| 294 | #define BP_SSP_CTRL1_CEATA_CCS_ERR_EN 12 | ||
| 295 | #define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x1000 | ||
| 296 | #define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v) (((v) << 12) & 0x1000) | ||
| 297 | #define BP_SSP_CTRL1_SLAVE_OUT_DISABLE 11 | ||
| 298 | #define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x800 | ||
| 299 | #define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v) (((v) << 11) & 0x800) | ||
| 300 | #define BP_SSP_CTRL1_PHASE 10 | ||
| 301 | #define BM_SSP_CTRL1_PHASE 0x400 | ||
| 302 | #define BF_SSP_CTRL1_PHASE(v) (((v) << 10) & 0x400) | ||
| 303 | #define BP_SSP_CTRL1_POLARITY 9 | ||
| 304 | #define BM_SSP_CTRL1_POLARITY 0x200 | ||
| 305 | #define BF_SSP_CTRL1_POLARITY(v) (((v) << 9) & 0x200) | ||
| 306 | #define BP_SSP_CTRL1_SLAVE_MODE 8 | ||
| 307 | #define BM_SSP_CTRL1_SLAVE_MODE 0x100 | ||
| 308 | #define BF_SSP_CTRL1_SLAVE_MODE(v) (((v) << 8) & 0x100) | ||
| 309 | #define BP_SSP_CTRL1_WORD_LENGTH 4 | ||
| 310 | #define BM_SSP_CTRL1_WORD_LENGTH 0xf0 | ||
| 311 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 | ||
| 312 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 | ||
| 313 | #define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 | ||
| 314 | #define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 | ||
| 315 | #define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 | ||
| 316 | #define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xf | ||
| 317 | #define BF_SSP_CTRL1_WORD_LENGTH(v) (((v) << 4) & 0xf0) | ||
| 318 | #define BF_SSP_CTRL1_WORD_LENGTH_V(v) ((BV_SSP_CTRL1_WORD_LENGTH__##v << 4) & 0xf0) | ||
| 319 | #define BP_SSP_CTRL1_SSP_MODE 0 | ||
| 320 | #define BM_SSP_CTRL1_SSP_MODE 0xf | ||
| 321 | #define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 | ||
| 322 | #define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 | ||
| 323 | #define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 | ||
| 324 | #define BV_SSP_CTRL1_SSP_MODE__MS 0x4 | ||
| 325 | #define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7 | ||
| 326 | #define BF_SSP_CTRL1_SSP_MODE(v) (((v) << 0) & 0xf) | ||
| 327 | #define BF_SSP_CTRL1_SSP_MODE_V(v) ((BV_SSP_CTRL1_SSP_MODE__##v << 0) & 0xf) | ||
| 328 | |||
| 329 | /** | ||
| 330 | * Register: HW_SSP_DATA | ||
| 331 | * Address: 0x70 | ||
| 332 | * SCT: no | ||
| 333 | */ | ||
| 334 | #define HW_SSP_DATA(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x70)) | ||
| 335 | #define BP_SSP_DATA_DATA 0 | ||
| 336 | #define BM_SSP_DATA_DATA 0xffffffff | ||
| 337 | #define BF_SSP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 338 | |||
| 339 | /** | ||
| 340 | * Register: HW_SSP_SDRESP0 | ||
| 341 | * Address: 0x80 | ||
| 342 | * SCT: no | ||
| 343 | */ | ||
| 344 | #define HW_SSP_SDRESP0(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x80)) | ||
| 345 | #define BP_SSP_SDRESP0_RESP0 0 | ||
| 346 | #define BM_SSP_SDRESP0_RESP0 0xffffffff | ||
| 347 | #define BF_SSP_SDRESP0_RESP0(v) (((v) << 0) & 0xffffffff) | ||
| 348 | |||
| 349 | /** | ||
| 350 | * Register: HW_SSP_SDRESP1 | ||
| 351 | * Address: 0x90 | ||
| 352 | * SCT: no | ||
| 353 | */ | ||
| 354 | #define HW_SSP_SDRESP1(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x90)) | ||
| 355 | #define BP_SSP_SDRESP1_RESP1 0 | ||
| 356 | #define BM_SSP_SDRESP1_RESP1 0xffffffff | ||
| 357 | #define BF_SSP_SDRESP1_RESP1(v) (((v) << 0) & 0xffffffff) | ||
| 358 | |||
| 359 | /** | ||
| 360 | * Register: HW_SSP_SDRESP2 | ||
| 361 | * Address: 0xa0 | ||
| 362 | * SCT: no | ||
| 363 | */ | ||
| 364 | #define HW_SSP_SDRESP2(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xa0)) | ||
| 365 | #define BP_SSP_SDRESP2_RESP2 0 | ||
| 366 | #define BM_SSP_SDRESP2_RESP2 0xffffffff | ||
| 367 | #define BF_SSP_SDRESP2_RESP2(v) (((v) << 0) & 0xffffffff) | ||
| 368 | |||
| 369 | /** | ||
| 370 | * Register: HW_SSP_SDRESP3 | ||
| 371 | * Address: 0xb0 | ||
| 372 | * SCT: no | ||
| 373 | */ | ||
| 374 | #define HW_SSP_SDRESP3(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xb0)) | ||
| 375 | #define BP_SSP_SDRESP3_RESP3 0 | ||
| 376 | #define BM_SSP_SDRESP3_RESP3 0xffffffff | ||
| 377 | #define BF_SSP_SDRESP3_RESP3(v) (((v) << 0) & 0xffffffff) | ||
| 378 | |||
| 379 | /** | ||
| 380 | * Register: HW_SSP_STATUS | ||
| 381 | * Address: 0xc0 | ||
| 382 | * SCT: no | ||
| 383 | */ | ||
| 384 | #define HW_SSP_STATUS(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0xc0)) | ||
| 385 | #define BP_SSP_STATUS_PRESENT 31 | ||
| 386 | #define BM_SSP_STATUS_PRESENT 0x80000000 | ||
| 387 | #define BF_SSP_STATUS_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 388 | #define BP_SSP_STATUS_MS_PRESENT 30 | ||
| 389 | #define BM_SSP_STATUS_MS_PRESENT 0x40000000 | ||
| 390 | #define BF_SSP_STATUS_MS_PRESENT(v) (((v) << 30) & 0x40000000) | ||
| 391 | #define BP_SSP_STATUS_SD_PRESENT 29 | ||
| 392 | #define BM_SSP_STATUS_SD_PRESENT 0x20000000 | ||
| 393 | #define BF_SSP_STATUS_SD_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 394 | #define BP_SSP_STATUS_CARD_DETECT 28 | ||
| 395 | #define BM_SSP_STATUS_CARD_DETECT 0x10000000 | ||
| 396 | #define BF_SSP_STATUS_CARD_DETECT(v) (((v) << 28) & 0x10000000) | ||
| 397 | #define BP_SSP_STATUS_DMASENSE 21 | ||
| 398 | #define BM_SSP_STATUS_DMASENSE 0x200000 | ||
| 399 | #define BF_SSP_STATUS_DMASENSE(v) (((v) << 21) & 0x200000) | ||
| 400 | #define BP_SSP_STATUS_DMATERM 20 | ||
| 401 | #define BM_SSP_STATUS_DMATERM 0x100000 | ||
| 402 | #define BF_SSP_STATUS_DMATERM(v) (((v) << 20) & 0x100000) | ||
| 403 | #define BP_SSP_STATUS_DMAREQ 19 | ||
| 404 | #define BM_SSP_STATUS_DMAREQ 0x80000 | ||
| 405 | #define BF_SSP_STATUS_DMAREQ(v) (((v) << 19) & 0x80000) | ||
| 406 | #define BP_SSP_STATUS_DMAEND 18 | ||
| 407 | #define BM_SSP_STATUS_DMAEND 0x40000 | ||
| 408 | #define BF_SSP_STATUS_DMAEND(v) (((v) << 18) & 0x40000) | ||
| 409 | #define BP_SSP_STATUS_SDIO_IRQ 17 | ||
| 410 | #define BM_SSP_STATUS_SDIO_IRQ 0x20000 | ||
| 411 | #define BF_SSP_STATUS_SDIO_IRQ(v) (((v) << 17) & 0x20000) | ||
| 412 | #define BP_SSP_STATUS_RESP_CRC_ERR 16 | ||
| 413 | #define BM_SSP_STATUS_RESP_CRC_ERR 0x10000 | ||
| 414 | #define BF_SSP_STATUS_RESP_CRC_ERR(v) (((v) << 16) & 0x10000) | ||
| 415 | #define BP_SSP_STATUS_RESP_ERR 15 | ||
| 416 | #define BM_SSP_STATUS_RESP_ERR 0x8000 | ||
| 417 | #define BF_SSP_STATUS_RESP_ERR(v) (((v) << 15) & 0x8000) | ||
| 418 | #define BP_SSP_STATUS_RESP_TIMEOUT 14 | ||
| 419 | #define BM_SSP_STATUS_RESP_TIMEOUT 0x4000 | ||
| 420 | #define BF_SSP_STATUS_RESP_TIMEOUT(v) (((v) << 14) & 0x4000) | ||
| 421 | #define BP_SSP_STATUS_DATA_CRC_ERR 13 | ||
| 422 | #define BM_SSP_STATUS_DATA_CRC_ERR 0x2000 | ||
| 423 | #define BF_SSP_STATUS_DATA_CRC_ERR(v) (((v) << 13) & 0x2000) | ||
| 424 | #define BP_SSP_STATUS_TIMEOUT 12 | ||
| 425 | #define BM_SSP_STATUS_TIMEOUT 0x1000 | ||
| 426 | #define BF_SSP_STATUS_TIMEOUT(v) (((v) << 12) & 0x1000) | ||
| 427 | #define BP_SSP_STATUS_RECV_TIMEOUT_STAT 11 | ||
| 428 | #define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x800 | ||
| 429 | #define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v) (((v) << 11) & 0x800) | ||
| 430 | #define BP_SSP_STATUS_CEATA_CCS_ERR 10 | ||
| 431 | #define BM_SSP_STATUS_CEATA_CCS_ERR 0x400 | ||
| 432 | #define BF_SSP_STATUS_CEATA_CCS_ERR(v) (((v) << 10) & 0x400) | ||
| 433 | #define BP_SSP_STATUS_FIFO_OVRFLW 9 | ||
| 434 | #define BM_SSP_STATUS_FIFO_OVRFLW 0x200 | ||
| 435 | #define BF_SSP_STATUS_FIFO_OVRFLW(v) (((v) << 9) & 0x200) | ||
| 436 | #define BP_SSP_STATUS_FIFO_FULL 8 | ||
| 437 | #define BM_SSP_STATUS_FIFO_FULL 0x100 | ||
| 438 | #define BF_SSP_STATUS_FIFO_FULL(v) (((v) << 8) & 0x100) | ||
| 439 | #define BP_SSP_STATUS_FIFO_EMPTY 5 | ||
| 440 | #define BM_SSP_STATUS_FIFO_EMPTY 0x20 | ||
| 441 | #define BF_SSP_STATUS_FIFO_EMPTY(v) (((v) << 5) & 0x20) | ||
| 442 | #define BP_SSP_STATUS_FIFO_UNDRFLW 4 | ||
| 443 | #define BM_SSP_STATUS_FIFO_UNDRFLW 0x10 | ||
| 444 | #define BF_SSP_STATUS_FIFO_UNDRFLW(v) (((v) << 4) & 0x10) | ||
| 445 | #define BP_SSP_STATUS_CMD_BUSY 3 | ||
| 446 | #define BM_SSP_STATUS_CMD_BUSY 0x8 | ||
| 447 | #define BF_SSP_STATUS_CMD_BUSY(v) (((v) << 3) & 0x8) | ||
| 448 | #define BP_SSP_STATUS_DATA_BUSY 2 | ||
| 449 | #define BM_SSP_STATUS_DATA_BUSY 0x4 | ||
| 450 | #define BF_SSP_STATUS_DATA_BUSY(v) (((v) << 2) & 0x4) | ||
| 451 | #define BP_SSP_STATUS_BUSY 0 | ||
| 452 | #define BM_SSP_STATUS_BUSY 0x1 | ||
| 453 | #define BF_SSP_STATUS_BUSY(v) (((v) << 0) & 0x1) | ||
| 454 | |||
| 455 | /** | ||
| 456 | * Register: HW_SSP_DEBUG | ||
| 457 | * Address: 0x100 | ||
| 458 | * SCT: no | ||
| 459 | */ | ||
| 460 | #define HW_SSP_DEBUG(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x100)) | ||
| 461 | #define BP_SSP_DEBUG_DATACRC_ERR 28 | ||
| 462 | #define BM_SSP_DEBUG_DATACRC_ERR 0xf0000000 | ||
| 463 | #define BF_SSP_DEBUG_DATACRC_ERR(v) (((v) << 28) & 0xf0000000) | ||
| 464 | #define BP_SSP_DEBUG_DATA_STALL 27 | ||
| 465 | #define BM_SSP_DEBUG_DATA_STALL 0x8000000 | ||
| 466 | #define BF_SSP_DEBUG_DATA_STALL(v) (((v) << 27) & 0x8000000) | ||
| 467 | #define BP_SSP_DEBUG_DAT_SM 24 | ||
| 468 | #define BM_SSP_DEBUG_DAT_SM 0x7000000 | ||
| 469 | #define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 | ||
| 470 | #define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 | ||
| 471 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 | ||
| 472 | #define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 | ||
| 473 | #define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 | ||
| 474 | #define BF_SSP_DEBUG_DAT_SM(v) (((v) << 24) & 0x7000000) | ||
| 475 | #define BF_SSP_DEBUG_DAT_SM_V(v) ((BV_SSP_DEBUG_DAT_SM__##v << 24) & 0x7000000) | ||
| 476 | #define BP_SSP_DEBUG_MSTK_SM 20 | ||
| 477 | #define BM_SSP_DEBUG_MSTK_SM 0xf00000 | ||
| 478 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 | ||
| 479 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 | ||
| 480 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 | ||
| 481 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 | ||
| 482 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 | ||
| 483 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 | ||
| 484 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 | ||
| 485 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 | ||
| 486 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 | ||
| 487 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 | ||
| 488 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xa | ||
| 489 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xb | ||
| 490 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xc | ||
| 491 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xd | ||
| 492 | #define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xe | ||
| 493 | #define BF_SSP_DEBUG_MSTK_SM(v) (((v) << 20) & 0xf00000) | ||
| 494 | #define BF_SSP_DEBUG_MSTK_SM_V(v) ((BV_SSP_DEBUG_MSTK_SM__##v << 20) & 0xf00000) | ||
| 495 | #define BP_SSP_DEBUG_CMD_OE 19 | ||
| 496 | #define BM_SSP_DEBUG_CMD_OE 0x80000 | ||
| 497 | #define BF_SSP_DEBUG_CMD_OE(v) (((v) << 19) & 0x80000) | ||
| 498 | #define BP_SSP_DEBUG_DMA_SM 16 | ||
| 499 | #define BM_SSP_DEBUG_DMA_SM 0x70000 | ||
| 500 | #define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 | ||
| 501 | #define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 | ||
| 502 | #define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 | ||
| 503 | #define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 | ||
| 504 | #define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 | ||
| 505 | #define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 | ||
| 506 | #define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 | ||
| 507 | #define BF_SSP_DEBUG_DMA_SM(v) (((v) << 16) & 0x70000) | ||
| 508 | #define BF_SSP_DEBUG_DMA_SM_V(v) ((BV_SSP_DEBUG_DMA_SM__##v << 16) & 0x70000) | ||
| 509 | #define BP_SSP_DEBUG_MMC_SM 12 | ||
| 510 | #define BM_SSP_DEBUG_MMC_SM 0xf000 | ||
| 511 | #define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 | ||
| 512 | #define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 | ||
| 513 | #define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 | ||
| 514 | #define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 | ||
| 515 | #define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 | ||
| 516 | #define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 | ||
| 517 | #define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 | ||
| 518 | #define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 | ||
| 519 | #define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 | ||
| 520 | #define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 | ||
| 521 | #define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xa | ||
| 522 | #define BF_SSP_DEBUG_MMC_SM(v) (((v) << 12) & 0xf000) | ||
| 523 | #define BF_SSP_DEBUG_MMC_SM_V(v) ((BV_SSP_DEBUG_MMC_SM__##v << 12) & 0xf000) | ||
| 524 | #define BP_SSP_DEBUG_CMD_SM 10 | ||
| 525 | #define BM_SSP_DEBUG_CMD_SM 0xc00 | ||
| 526 | #define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 | ||
| 527 | #define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 | ||
| 528 | #define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 | ||
| 529 | #define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 | ||
| 530 | #define BF_SSP_DEBUG_CMD_SM(v) (((v) << 10) & 0xc00) | ||
| 531 | #define BF_SSP_DEBUG_CMD_SM_V(v) ((BV_SSP_DEBUG_CMD_SM__##v << 10) & 0xc00) | ||
| 532 | #define BP_SSP_DEBUG_SSP_CMD 9 | ||
| 533 | #define BM_SSP_DEBUG_SSP_CMD 0x200 | ||
| 534 | #define BF_SSP_DEBUG_SSP_CMD(v) (((v) << 9) & 0x200) | ||
| 535 | #define BP_SSP_DEBUG_SSP_RESP 8 | ||
| 536 | #define BM_SSP_DEBUG_SSP_RESP 0x100 | ||
| 537 | #define BF_SSP_DEBUG_SSP_RESP(v) (((v) << 8) & 0x100) | ||
| 538 | #define BP_SSP_DEBUG_SSP_RXD 0 | ||
| 539 | #define BM_SSP_DEBUG_SSP_RXD 0xff | ||
| 540 | #define BF_SSP_DEBUG_SSP_RXD(v) (((v) << 0) & 0xff) | ||
| 541 | |||
| 542 | /** | ||
| 543 | * Register: HW_SSP_VERSION | ||
| 544 | * Address: 0x110 | ||
| 545 | * SCT: no | ||
| 546 | */ | ||
| 547 | #define HW_SSP_VERSION(d) (*(volatile unsigned long *)(REGS_SSP_BASE(d) + 0x110)) | ||
| 548 | #define BP_SSP_VERSION_MAJOR 24 | ||
| 549 | #define BM_SSP_VERSION_MAJOR 0xff000000 | ||
| 550 | #define BF_SSP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 551 | #define BP_SSP_VERSION_MINOR 16 | ||
| 552 | #define BM_SSP_VERSION_MINOR 0xff0000 | ||
| 553 | #define BF_SSP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 554 | #define BP_SSP_VERSION_STEP 0 | ||
| 555 | #define BM_SSP_VERSION_STEP 0xffff | ||
| 556 | #define BF_SSP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 557 | |||
| 558 | #endif /* __HEADERGEN__STMP3700__SSP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h b/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h new file mode 100644 index 0000000000..a741fc6856 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-timrot.h | |||
| @@ -0,0 +1,283 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__TIMROT__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__TIMROT__H__ | ||
| 25 | |||
| 26 | #define REGS_TIMROT_BASE (0x80068000) | ||
| 27 | |||
| 28 | #define REGS_TIMROT_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_TIMROT_ROTCTRL | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_TIMROT_ROTCTRL (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_TIMROT_ROTCTRL_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_TIMROT_ROTCTRL_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_TIMROT_ROTCTRL_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_TIMROT_ROTCTRL_SFTRST 31 | ||
| 40 | #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 | ||
| 41 | #define BF_TIMROT_ROTCTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_TIMROT_ROTCTRL_CLKGATE 30 | ||
| 43 | #define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 | ||
| 44 | #define BF_TIMROT_ROTCTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_TIMROT_ROTCTRL_ROTARY_PRESENT 29 | ||
| 46 | #define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 | ||
| 47 | #define BF_TIMROT_ROTCTRL_ROTARY_PRESENT(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_TIMROT_ROTCTRL_TIM3_PRESENT 28 | ||
| 49 | #define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 | ||
| 50 | #define BF_TIMROT_ROTCTRL_TIM3_PRESENT(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_TIMROT_ROTCTRL_TIM2_PRESENT 27 | ||
| 52 | #define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x8000000 | ||
| 53 | #define BF_TIMROT_ROTCTRL_TIM2_PRESENT(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_TIMROT_ROTCTRL_TIM1_PRESENT 26 | ||
| 55 | #define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x4000000 | ||
| 56 | #define BF_TIMROT_ROTCTRL_TIM1_PRESENT(v) (((v) << 26) & 0x4000000) | ||
| 57 | #define BP_TIMROT_ROTCTRL_TIM0_PRESENT 25 | ||
| 58 | #define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x2000000 | ||
| 59 | #define BF_TIMROT_ROTCTRL_TIM0_PRESENT(v) (((v) << 25) & 0x2000000) | ||
| 60 | #define BP_TIMROT_ROTCTRL_STATE 22 | ||
| 61 | #define BM_TIMROT_ROTCTRL_STATE 0x1c00000 | ||
| 62 | #define BF_TIMROT_ROTCTRL_STATE(v) (((v) << 22) & 0x1c00000) | ||
| 63 | #define BP_TIMROT_ROTCTRL_DIVIDER 16 | ||
| 64 | #define BM_TIMROT_ROTCTRL_DIVIDER 0x3f0000 | ||
| 65 | #define BF_TIMROT_ROTCTRL_DIVIDER(v) (((v) << 16) & 0x3f0000) | ||
| 66 | #define BP_TIMROT_ROTCTRL_RELATIVE 12 | ||
| 67 | #define BM_TIMROT_ROTCTRL_RELATIVE 0x1000 | ||
| 68 | #define BF_TIMROT_ROTCTRL_RELATIVE(v) (((v) << 12) & 0x1000) | ||
| 69 | #define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 | ||
| 70 | #define BM_TIMROT_ROTCTRL_OVERSAMPLE 0xc00 | ||
| 71 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 | ||
| 72 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 | ||
| 73 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 | ||
| 74 | #define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 | ||
| 75 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) (((v) << 10) & 0xc00) | ||
| 76 | #define BF_TIMROT_ROTCTRL_OVERSAMPLE_V(v) ((BV_TIMROT_ROTCTRL_OVERSAMPLE__##v << 10) & 0xc00) | ||
| 77 | #define BP_TIMROT_ROTCTRL_POLARITY_B 9 | ||
| 78 | #define BM_TIMROT_ROTCTRL_POLARITY_B 0x200 | ||
| 79 | #define BF_TIMROT_ROTCTRL_POLARITY_B(v) (((v) << 9) & 0x200) | ||
| 80 | #define BP_TIMROT_ROTCTRL_POLARITY_A 8 | ||
| 81 | #define BM_TIMROT_ROTCTRL_POLARITY_A 0x100 | ||
| 82 | #define BF_TIMROT_ROTCTRL_POLARITY_A(v) (((v) << 8) & 0x100) | ||
| 83 | #define BP_TIMROT_ROTCTRL_SELECT_B 4 | ||
| 84 | #define BM_TIMROT_ROTCTRL_SELECT_B 0x70 | ||
| 85 | #define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 | ||
| 86 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 | ||
| 87 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 | ||
| 88 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 | ||
| 89 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 | ||
| 90 | #define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 | ||
| 91 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 | ||
| 92 | #define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 | ||
| 93 | #define BF_TIMROT_ROTCTRL_SELECT_B(v) (((v) << 4) & 0x70) | ||
| 94 | #define BF_TIMROT_ROTCTRL_SELECT_B_V(v) ((BV_TIMROT_ROTCTRL_SELECT_B__##v << 4) & 0x70) | ||
| 95 | #define BP_TIMROT_ROTCTRL_SELECT_A 0 | ||
| 96 | #define BM_TIMROT_ROTCTRL_SELECT_A 0x7 | ||
| 97 | #define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 | ||
| 98 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 | ||
| 99 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 | ||
| 100 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 | ||
| 101 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 | ||
| 102 | #define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 | ||
| 103 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 | ||
| 104 | #define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 | ||
| 105 | #define BF_TIMROT_ROTCTRL_SELECT_A(v) (((v) << 0) & 0x7) | ||
| 106 | #define BF_TIMROT_ROTCTRL_SELECT_A_V(v) ((BV_TIMROT_ROTCTRL_SELECT_A__##v << 0) & 0x7) | ||
| 107 | |||
| 108 | /** | ||
| 109 | * Register: HW_TIMROT_ROTCOUNT | ||
| 110 | * Address: 0x10 | ||
| 111 | * SCT: no | ||
| 112 | */ | ||
| 113 | #define HW_TIMROT_ROTCOUNT (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x10)) | ||
| 114 | #define BP_TIMROT_ROTCOUNT_UPDOWN 0 | ||
| 115 | #define BM_TIMROT_ROTCOUNT_UPDOWN 0xffff | ||
| 116 | #define BF_TIMROT_ROTCOUNT_UPDOWN(v) (((v) << 0) & 0xffff) | ||
| 117 | |||
| 118 | /** | ||
| 119 | * Register: HW_TIMROT_TIMCTRLn | ||
| 120 | * Address: 0x20+n*0x20 | ||
| 121 | * SCT: yes | ||
| 122 | */ | ||
| 123 | #define HW_TIMROT_TIMCTRLn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x0)) | ||
| 124 | #define HW_TIMROT_TIMCTRLn_SET(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x4)) | ||
| 125 | #define HW_TIMROT_TIMCTRLn_CLR(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0x8)) | ||
| 126 | #define HW_TIMROT_TIMCTRLn_TOG(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x20+(n)*0x20 + 0xc)) | ||
| 127 | #define BP_TIMROT_TIMCTRLn_IRQ 15 | ||
| 128 | #define BM_TIMROT_TIMCTRLn_IRQ 0x8000 | ||
| 129 | #define BF_TIMROT_TIMCTRLn_IRQ(v) (((v) << 15) & 0x8000) | ||
| 130 | #define BP_TIMROT_TIMCTRLn_IRQ_EN 14 | ||
| 131 | #define BM_TIMROT_TIMCTRLn_IRQ_EN 0x4000 | ||
| 132 | #define BF_TIMROT_TIMCTRLn_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 133 | #define BP_TIMROT_TIMCTRLn_POLARITY 8 | ||
| 134 | #define BM_TIMROT_TIMCTRLn_POLARITY 0x100 | ||
| 135 | #define BF_TIMROT_TIMCTRLn_POLARITY(v) (((v) << 8) & 0x100) | ||
| 136 | #define BP_TIMROT_TIMCTRLn_UPDATE 7 | ||
| 137 | #define BM_TIMROT_TIMCTRLn_UPDATE 0x80 | ||
| 138 | #define BF_TIMROT_TIMCTRLn_UPDATE(v) (((v) << 7) & 0x80) | ||
| 139 | #define BP_TIMROT_TIMCTRLn_RELOAD 6 | ||
| 140 | #define BM_TIMROT_TIMCTRLn_RELOAD 0x40 | ||
| 141 | #define BF_TIMROT_TIMCTRLn_RELOAD(v) (((v) << 6) & 0x40) | ||
| 142 | #define BP_TIMROT_TIMCTRLn_PRESCALE 4 | ||
| 143 | #define BM_TIMROT_TIMCTRLn_PRESCALE 0x30 | ||
| 144 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 | ||
| 145 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 | ||
| 146 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 | ||
| 147 | #define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 | ||
| 148 | #define BF_TIMROT_TIMCTRLn_PRESCALE(v) (((v) << 4) & 0x30) | ||
| 149 | #define BF_TIMROT_TIMCTRLn_PRESCALE_V(v) ((BV_TIMROT_TIMCTRLn_PRESCALE__##v << 4) & 0x30) | ||
| 150 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
| 151 | #define BM_TIMROT_TIMCTRLn_SELECT 0xf | ||
| 152 | #define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 | ||
| 153 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 | ||
| 154 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 | ||
| 155 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 | ||
| 156 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 | ||
| 157 | #define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 | ||
| 158 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 | ||
| 159 | #define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 | ||
| 160 | #define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
| 161 | #define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 | ||
| 162 | #define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xa | ||
| 163 | #define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xb | ||
| 164 | #define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xc | ||
| 165 | #define BF_TIMROT_TIMCTRLn_SELECT(v) (((v) << 0) & 0xf) | ||
| 166 | #define BF_TIMROT_TIMCTRLn_SELECT_V(v) ((BV_TIMROT_TIMCTRLn_SELECT__##v << 0) & 0xf) | ||
| 167 | |||
| 168 | /** | ||
| 169 | * Register: HW_TIMROT_TIMCOUNTn | ||
| 170 | * Address: 0x30+n*0x20 | ||
| 171 | * SCT: no | ||
| 172 | */ | ||
| 173 | #define HW_TIMROT_TIMCOUNTn(n) (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x30+(n)*0x20)) | ||
| 174 | #define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 | ||
| 175 | #define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xffff0000 | ||
| 176 | #define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 177 | #define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 | ||
| 178 | #define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0xffff | ||
| 179 | #define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
| 180 | |||
| 181 | /** | ||
| 182 | * Register: HW_TIMROT_TIMCTRL3 | ||
| 183 | * Address: 0x80 | ||
| 184 | * SCT: yes | ||
| 185 | */ | ||
| 186 | #define HW_TIMROT_TIMCTRL3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x0)) | ||
| 187 | #define HW_TIMROT_TIMCTRL3_SET (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x4)) | ||
| 188 | #define HW_TIMROT_TIMCTRL3_CLR (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0x8)) | ||
| 189 | #define HW_TIMROT_TIMCTRL3_TOG (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x80 + 0xc)) | ||
| 190 | #define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 | ||
| 191 | #define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0xf0000 | ||
| 192 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 | ||
| 193 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 | ||
| 194 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 | ||
| 195 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 | ||
| 196 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 | ||
| 197 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 | ||
| 198 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 | ||
| 199 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 | ||
| 200 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 | ||
| 201 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 | ||
| 202 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xa | ||
| 203 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xb | ||
| 204 | #define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xc | ||
| 205 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) (((v) << 16) & 0xf0000) | ||
| 206 | #define BF_TIMROT_TIMCTRL3_TEST_SIGNAL_V(v) ((BV_TIMROT_TIMCTRL3_TEST_SIGNAL__##v << 16) & 0xf0000) | ||
| 207 | #define BP_TIMROT_TIMCTRL3_IRQ 15 | ||
| 208 | #define BM_TIMROT_TIMCTRL3_IRQ 0x8000 | ||
| 209 | #define BF_TIMROT_TIMCTRL3_IRQ(v) (((v) << 15) & 0x8000) | ||
| 210 | #define BP_TIMROT_TIMCTRL3_IRQ_EN 14 | ||
| 211 | #define BM_TIMROT_TIMCTRL3_IRQ_EN 0x4000 | ||
| 212 | #define BF_TIMROT_TIMCTRL3_IRQ_EN(v) (((v) << 14) & 0x4000) | ||
| 213 | #define BP_TIMROT_TIMCTRL3_DUTY_VALID 10 | ||
| 214 | #define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x400 | ||
| 215 | #define BF_TIMROT_TIMCTRL3_DUTY_VALID(v) (((v) << 10) & 0x400) | ||
| 216 | #define BP_TIMROT_TIMCTRL3_DUTY_CYCLE 9 | ||
| 217 | #define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x200 | ||
| 218 | #define BF_TIMROT_TIMCTRL3_DUTY_CYCLE(v) (((v) << 9) & 0x200) | ||
| 219 | #define BP_TIMROT_TIMCTRL3_POLARITY 8 | ||
| 220 | #define BM_TIMROT_TIMCTRL3_POLARITY 0x100 | ||
| 221 | #define BF_TIMROT_TIMCTRL3_POLARITY(v) (((v) << 8) & 0x100) | ||
| 222 | #define BP_TIMROT_TIMCTRL3_UPDATE 7 | ||
| 223 | #define BM_TIMROT_TIMCTRL3_UPDATE 0x80 | ||
| 224 | #define BF_TIMROT_TIMCTRL3_UPDATE(v) (((v) << 7) & 0x80) | ||
| 225 | #define BP_TIMROT_TIMCTRL3_RELOAD 6 | ||
| 226 | #define BM_TIMROT_TIMCTRL3_RELOAD 0x40 | ||
| 227 | #define BF_TIMROT_TIMCTRL3_RELOAD(v) (((v) << 6) & 0x40) | ||
| 228 | #define BP_TIMROT_TIMCTRL3_PRESCALE 4 | ||
| 229 | #define BM_TIMROT_TIMCTRL3_PRESCALE 0x30 | ||
| 230 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 | ||
| 231 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 | ||
| 232 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 | ||
| 233 | #define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 | ||
| 234 | #define BF_TIMROT_TIMCTRL3_PRESCALE(v) (((v) << 4) & 0x30) | ||
| 235 | #define BF_TIMROT_TIMCTRL3_PRESCALE_V(v) ((BV_TIMROT_TIMCTRL3_PRESCALE__##v << 4) & 0x30) | ||
| 236 | #define BP_TIMROT_TIMCTRL3_SELECT 0 | ||
| 237 | #define BM_TIMROT_TIMCTRL3_SELECT 0xf | ||
| 238 | #define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 | ||
| 239 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 | ||
| 240 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 | ||
| 241 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 | ||
| 242 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 | ||
| 243 | #define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 | ||
| 244 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 | ||
| 245 | #define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 | ||
| 246 | #define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 | ||
| 247 | #define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 | ||
| 248 | #define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xa | ||
| 249 | #define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xb | ||
| 250 | #define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xc | ||
| 251 | #define BF_TIMROT_TIMCTRL3_SELECT(v) (((v) << 0) & 0xf) | ||
| 252 | #define BF_TIMROT_TIMCTRL3_SELECT_V(v) ((BV_TIMROT_TIMCTRL3_SELECT__##v << 0) & 0xf) | ||
| 253 | |||
| 254 | /** | ||
| 255 | * Register: HW_TIMROT_TIMCOUNT3 | ||
| 256 | * Address: 0x90 | ||
| 257 | * SCT: no | ||
| 258 | */ | ||
| 259 | #define HW_TIMROT_TIMCOUNT3 (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0x90)) | ||
| 260 | #define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 | ||
| 261 | #define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xffff0000 | ||
| 262 | #define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) (((v) << 16) & 0xffff0000) | ||
| 263 | #define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 | ||
| 264 | #define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0xffff | ||
| 265 | #define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) (((v) << 0) & 0xffff) | ||
| 266 | |||
| 267 | /** | ||
| 268 | * Register: HW_TIMROT_VERSION | ||
| 269 | * Address: 0xa0 | ||
| 270 | * SCT: no | ||
| 271 | */ | ||
| 272 | #define HW_TIMROT_VERSION (*(volatile unsigned long *)(REGS_TIMROT_BASE + 0xa0)) | ||
| 273 | #define BP_TIMROT_VERSION_MAJOR 24 | ||
| 274 | #define BM_TIMROT_VERSION_MAJOR 0xff000000 | ||
| 275 | #define BF_TIMROT_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 276 | #define BP_TIMROT_VERSION_MINOR 16 | ||
| 277 | #define BM_TIMROT_VERSION_MINOR 0xff0000 | ||
| 278 | #define BF_TIMROT_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 279 | #define BP_TIMROT_VERSION_STEP 0 | ||
| 280 | #define BM_TIMROT_VERSION_STEP 0xffff | ||
| 281 | #define BF_TIMROT_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 282 | |||
| 283 | #endif /* __HEADERGEN__STMP3700__TIMROT__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h new file mode 100644 index 0000000000..a346fc1246 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-uartapp.h | |||
| @@ -0,0 +1,427 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__UARTAPP__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__UARTAPP__H__ | ||
| 25 | |||
| 26 | #define REGS_UARTAPP_BASE(i) ((i) == 1 ? 0x8006c000 : 0x8006e000) | ||
| 27 | |||
| 28 | #define REGS_UARTAPP_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_UARTAPP_CTRL0 | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_UARTAPP_CTRL0(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x0)) | ||
| 36 | #define HW_UARTAPP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x4)) | ||
| 37 | #define HW_UARTAPP_CTRL0_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0x8)) | ||
| 38 | #define HW_UARTAPP_CTRL0_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x0 + 0xc)) | ||
| 39 | #define BP_UARTAPP_CTRL0_SFTRST 31 | ||
| 40 | #define BM_UARTAPP_CTRL0_SFTRST 0x80000000 | ||
| 41 | #define BF_UARTAPP_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 42 | #define BP_UARTAPP_CTRL0_CLKGATE 30 | ||
| 43 | #define BM_UARTAPP_CTRL0_CLKGATE 0x40000000 | ||
| 44 | #define BF_UARTAPP_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 45 | #define BP_UARTAPP_CTRL0_RUN 29 | ||
| 46 | #define BM_UARTAPP_CTRL0_RUN 0x20000000 | ||
| 47 | #define BF_UARTAPP_CTRL0_RUN(v) (((v) << 29) & 0x20000000) | ||
| 48 | #define BP_UARTAPP_CTRL0_RX_SOURCE 28 | ||
| 49 | #define BM_UARTAPP_CTRL0_RX_SOURCE 0x10000000 | ||
| 50 | #define BF_UARTAPP_CTRL0_RX_SOURCE(v) (((v) << 28) & 0x10000000) | ||
| 51 | #define BP_UARTAPP_CTRL0_RXTO_ENABLE 27 | ||
| 52 | #define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x8000000 | ||
| 53 | #define BF_UARTAPP_CTRL0_RXTO_ENABLE(v) (((v) << 27) & 0x8000000) | ||
| 54 | #define BP_UARTAPP_CTRL0_RXTIMEOUT 16 | ||
| 55 | #define BM_UARTAPP_CTRL0_RXTIMEOUT 0x7ff0000 | ||
| 56 | #define BF_UARTAPP_CTRL0_RXTIMEOUT(v) (((v) << 16) & 0x7ff0000) | ||
| 57 | #define BP_UARTAPP_CTRL0_XFER_COUNT 0 | ||
| 58 | #define BM_UARTAPP_CTRL0_XFER_COUNT 0xffff | ||
| 59 | #define BF_UARTAPP_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 60 | |||
| 61 | /** | ||
| 62 | * Register: HW_UARTAPP_CTRL1 | ||
| 63 | * Address: 0x10 | ||
| 64 | * SCT: yes | ||
| 65 | */ | ||
| 66 | #define HW_UARTAPP_CTRL1(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x0)) | ||
| 67 | #define HW_UARTAPP_CTRL1_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x4)) | ||
| 68 | #define HW_UARTAPP_CTRL1_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0x8)) | ||
| 69 | #define HW_UARTAPP_CTRL1_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x10 + 0xc)) | ||
| 70 | #define BP_UARTAPP_CTRL1_RUN 28 | ||
| 71 | #define BM_UARTAPP_CTRL1_RUN 0x10000000 | ||
| 72 | #define BF_UARTAPP_CTRL1_RUN(v) (((v) << 28) & 0x10000000) | ||
| 73 | #define BP_UARTAPP_CTRL1_XFER_COUNT 0 | ||
| 74 | #define BM_UARTAPP_CTRL1_XFER_COUNT 0xffff | ||
| 75 | #define BF_UARTAPP_CTRL1_XFER_COUNT(v) (((v) << 0) & 0xffff) | ||
| 76 | |||
| 77 | /** | ||
| 78 | * Register: HW_UARTAPP_CTRL2 | ||
| 79 | * Address: 0x20 | ||
| 80 | * SCT: yes | ||
| 81 | */ | ||
| 82 | #define HW_UARTAPP_CTRL2(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x0)) | ||
| 83 | #define HW_UARTAPP_CTRL2_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x4)) | ||
| 84 | #define HW_UARTAPP_CTRL2_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0x8)) | ||
| 85 | #define HW_UARTAPP_CTRL2_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x20 + 0xc)) | ||
| 86 | #define BP_UARTAPP_CTRL2_INVERT_RTS 31 | ||
| 87 | #define BM_UARTAPP_CTRL2_INVERT_RTS 0x80000000 | ||
| 88 | #define BF_UARTAPP_CTRL2_INVERT_RTS(v) (((v) << 31) & 0x80000000) | ||
| 89 | #define BP_UARTAPP_CTRL2_INVERT_CTS 30 | ||
| 90 | #define BM_UARTAPP_CTRL2_INVERT_CTS 0x40000000 | ||
| 91 | #define BF_UARTAPP_CTRL2_INVERT_CTS(v) (((v) << 30) & 0x40000000) | ||
| 92 | #define BP_UARTAPP_CTRL2_INVERT_TX 29 | ||
| 93 | #define BM_UARTAPP_CTRL2_INVERT_TX 0x20000000 | ||
| 94 | #define BF_UARTAPP_CTRL2_INVERT_TX(v) (((v) << 29) & 0x20000000) | ||
| 95 | #define BP_UARTAPP_CTRL2_INVERT_RX 28 | ||
| 96 | #define BM_UARTAPP_CTRL2_INVERT_RX 0x10000000 | ||
| 97 | #define BF_UARTAPP_CTRL2_INVERT_RX(v) (((v) << 28) & 0x10000000) | ||
| 98 | #define BP_UARTAPP_CTRL2_RTS_SEMAPHORE 27 | ||
| 99 | #define BM_UARTAPP_CTRL2_RTS_SEMAPHORE 0x8000000 | ||
| 100 | #define BF_UARTAPP_CTRL2_RTS_SEMAPHORE(v) (((v) << 27) & 0x8000000) | ||
| 101 | #define BP_UARTAPP_CTRL2_DMAONERR 26 | ||
| 102 | #define BM_UARTAPP_CTRL2_DMAONERR 0x4000000 | ||
| 103 | #define BF_UARTAPP_CTRL2_DMAONERR(v) (((v) << 26) & 0x4000000) | ||
| 104 | #define BP_UARTAPP_CTRL2_TXDMAE 25 | ||
| 105 | #define BM_UARTAPP_CTRL2_TXDMAE 0x2000000 | ||
| 106 | #define BF_UARTAPP_CTRL2_TXDMAE(v) (((v) << 25) & 0x2000000) | ||
| 107 | #define BP_UARTAPP_CTRL2_RXDMAE 24 | ||
| 108 | #define BM_UARTAPP_CTRL2_RXDMAE 0x1000000 | ||
| 109 | #define BF_UARTAPP_CTRL2_RXDMAE(v) (((v) << 24) & 0x1000000) | ||
| 110 | #define BP_UARTAPP_CTRL2_RXIFLSEL 20 | ||
| 111 | #define BM_UARTAPP_CTRL2_RXIFLSEL 0x700000 | ||
| 112 | #define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 | ||
| 113 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 | ||
| 114 | #define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 | ||
| 115 | #define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 | ||
| 116 | #define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 117 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 | ||
| 118 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 | ||
| 119 | #define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 | ||
| 120 | #define BF_UARTAPP_CTRL2_RXIFLSEL(v) (((v) << 20) & 0x700000) | ||
| 121 | #define BF_UARTAPP_CTRL2_RXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_RXIFLSEL__##v << 20) & 0x700000) | ||
| 122 | #define BP_UARTAPP_CTRL2_TXIFLSEL 16 | ||
| 123 | #define BM_UARTAPP_CTRL2_TXIFLSEL 0x70000 | ||
| 124 | #define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 | ||
| 125 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 | ||
| 126 | #define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 | ||
| 127 | #define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 | ||
| 128 | #define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 129 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 | ||
| 130 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 | ||
| 131 | #define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 | ||
| 132 | #define BF_UARTAPP_CTRL2_TXIFLSEL(v) (((v) << 16) & 0x70000) | ||
| 133 | #define BF_UARTAPP_CTRL2_TXIFLSEL_V(v) ((BV_UARTAPP_CTRL2_TXIFLSEL__##v << 16) & 0x70000) | ||
| 134 | #define BP_UARTAPP_CTRL2_CTSEN 15 | ||
| 135 | #define BM_UARTAPP_CTRL2_CTSEN 0x8000 | ||
| 136 | #define BF_UARTAPP_CTRL2_CTSEN(v) (((v) << 15) & 0x8000) | ||
| 137 | #define BP_UARTAPP_CTRL2_RTSEN 14 | ||
| 138 | #define BM_UARTAPP_CTRL2_RTSEN 0x4000 | ||
| 139 | #define BF_UARTAPP_CTRL2_RTSEN(v) (((v) << 14) & 0x4000) | ||
| 140 | #define BP_UARTAPP_CTRL2_OUT2 13 | ||
| 141 | #define BM_UARTAPP_CTRL2_OUT2 0x2000 | ||
| 142 | #define BF_UARTAPP_CTRL2_OUT2(v) (((v) << 13) & 0x2000) | ||
| 143 | #define BP_UARTAPP_CTRL2_OUT1 12 | ||
| 144 | #define BM_UARTAPP_CTRL2_OUT1 0x1000 | ||
| 145 | #define BF_UARTAPP_CTRL2_OUT1(v) (((v) << 12) & 0x1000) | ||
| 146 | #define BP_UARTAPP_CTRL2_RTS 11 | ||
| 147 | #define BM_UARTAPP_CTRL2_RTS 0x800 | ||
| 148 | #define BF_UARTAPP_CTRL2_RTS(v) (((v) << 11) & 0x800) | ||
| 149 | #define BP_UARTAPP_CTRL2_DTR 10 | ||
| 150 | #define BM_UARTAPP_CTRL2_DTR 0x400 | ||
| 151 | #define BF_UARTAPP_CTRL2_DTR(v) (((v) << 10) & 0x400) | ||
| 152 | #define BP_UARTAPP_CTRL2_RXE 9 | ||
| 153 | #define BM_UARTAPP_CTRL2_RXE 0x200 | ||
| 154 | #define BF_UARTAPP_CTRL2_RXE(v) (((v) << 9) & 0x200) | ||
| 155 | #define BP_UARTAPP_CTRL2_TXE 8 | ||
| 156 | #define BM_UARTAPP_CTRL2_TXE 0x100 | ||
| 157 | #define BF_UARTAPP_CTRL2_TXE(v) (((v) << 8) & 0x100) | ||
| 158 | #define BP_UARTAPP_CTRL2_LBE 7 | ||
| 159 | #define BM_UARTAPP_CTRL2_LBE 0x80 | ||
| 160 | #define BF_UARTAPP_CTRL2_LBE(v) (((v) << 7) & 0x80) | ||
| 161 | #define BP_UARTAPP_CTRL2_USE_LCR2 6 | ||
| 162 | #define BM_UARTAPP_CTRL2_USE_LCR2 0x40 | ||
| 163 | #define BF_UARTAPP_CTRL2_USE_LCR2(v) (((v) << 6) & 0x40) | ||
| 164 | #define BP_UARTAPP_CTRL2_SIRLP 2 | ||
| 165 | #define BM_UARTAPP_CTRL2_SIRLP 0x4 | ||
| 166 | #define BF_UARTAPP_CTRL2_SIRLP(v) (((v) << 2) & 0x4) | ||
| 167 | #define BP_UARTAPP_CTRL2_SIREN 1 | ||
| 168 | #define BM_UARTAPP_CTRL2_SIREN 0x2 | ||
| 169 | #define BF_UARTAPP_CTRL2_SIREN(v) (((v) << 1) & 0x2) | ||
| 170 | #define BP_UARTAPP_CTRL2_UARTEN 0 | ||
| 171 | #define BM_UARTAPP_CTRL2_UARTEN 0x1 | ||
| 172 | #define BF_UARTAPP_CTRL2_UARTEN(v) (((v) << 0) & 0x1) | ||
| 173 | |||
| 174 | /** | ||
| 175 | * Register: HW_UARTAPP_LINECTRL | ||
| 176 | * Address: 0x30 | ||
| 177 | * SCT: yes | ||
| 178 | */ | ||
| 179 | #define HW_UARTAPP_LINECTRL(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x0)) | ||
| 180 | #define HW_UARTAPP_LINECTRL_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x4)) | ||
| 181 | #define HW_UARTAPP_LINECTRL_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0x8)) | ||
| 182 | #define HW_UARTAPP_LINECTRL_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x30 + 0xc)) | ||
| 183 | #define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 | ||
| 184 | #define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xffff0000 | ||
| 185 | #define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
| 186 | #define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 | ||
| 187 | #define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x3f00 | ||
| 188 | #define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
| 189 | #define BP_UARTAPP_LINECTRL_SPS 7 | ||
| 190 | #define BM_UARTAPP_LINECTRL_SPS 0x80 | ||
| 191 | #define BF_UARTAPP_LINECTRL_SPS(v) (((v) << 7) & 0x80) | ||
| 192 | #define BP_UARTAPP_LINECTRL_WLEN 5 | ||
| 193 | #define BM_UARTAPP_LINECTRL_WLEN 0x60 | ||
| 194 | #define BF_UARTAPP_LINECTRL_WLEN(v) (((v) << 5) & 0x60) | ||
| 195 | #define BP_UARTAPP_LINECTRL_FEN 4 | ||
| 196 | #define BM_UARTAPP_LINECTRL_FEN 0x10 | ||
| 197 | #define BF_UARTAPP_LINECTRL_FEN(v) (((v) << 4) & 0x10) | ||
| 198 | #define BP_UARTAPP_LINECTRL_STP2 3 | ||
| 199 | #define BM_UARTAPP_LINECTRL_STP2 0x8 | ||
| 200 | #define BF_UARTAPP_LINECTRL_STP2(v) (((v) << 3) & 0x8) | ||
| 201 | #define BP_UARTAPP_LINECTRL_EPS 2 | ||
| 202 | #define BM_UARTAPP_LINECTRL_EPS 0x4 | ||
| 203 | #define BF_UARTAPP_LINECTRL_EPS(v) (((v) << 2) & 0x4) | ||
| 204 | #define BP_UARTAPP_LINECTRL_PEN 1 | ||
| 205 | #define BM_UARTAPP_LINECTRL_PEN 0x2 | ||
| 206 | #define BF_UARTAPP_LINECTRL_PEN(v) (((v) << 1) & 0x2) | ||
| 207 | #define BP_UARTAPP_LINECTRL_BRK 0 | ||
| 208 | #define BM_UARTAPP_LINECTRL_BRK 0x1 | ||
| 209 | #define BF_UARTAPP_LINECTRL_BRK(v) (((v) << 0) & 0x1) | ||
| 210 | |||
| 211 | /** | ||
| 212 | * Register: HW_UARTAPP_LINECTRL2 | ||
| 213 | * Address: 0x40 | ||
| 214 | * SCT: yes | ||
| 215 | */ | ||
| 216 | #define HW_UARTAPP_LINECTRL2(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x0)) | ||
| 217 | #define HW_UARTAPP_LINECTRL2_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x4)) | ||
| 218 | #define HW_UARTAPP_LINECTRL2_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0x8)) | ||
| 219 | #define HW_UARTAPP_LINECTRL2_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x40 + 0xc)) | ||
| 220 | #define BP_UARTAPP_LINECTRL2_BAUD_DIVINT 16 | ||
| 221 | #define BM_UARTAPP_LINECTRL2_BAUD_DIVINT 0xffff0000 | ||
| 222 | #define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v) (((v) << 16) & 0xffff0000) | ||
| 223 | #define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC 8 | ||
| 224 | #define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC 0x3f00 | ||
| 225 | #define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v) (((v) << 8) & 0x3f00) | ||
| 226 | #define BP_UARTAPP_LINECTRL2_SPS 7 | ||
| 227 | #define BM_UARTAPP_LINECTRL2_SPS 0x80 | ||
| 228 | #define BF_UARTAPP_LINECTRL2_SPS(v) (((v) << 7) & 0x80) | ||
| 229 | #define BP_UARTAPP_LINECTRL2_WLEN 5 | ||
| 230 | #define BM_UARTAPP_LINECTRL2_WLEN 0x60 | ||
| 231 | #define BF_UARTAPP_LINECTRL2_WLEN(v) (((v) << 5) & 0x60) | ||
| 232 | #define BP_UARTAPP_LINECTRL2_FEN 4 | ||
| 233 | #define BM_UARTAPP_LINECTRL2_FEN 0x10 | ||
| 234 | #define BF_UARTAPP_LINECTRL2_FEN(v) (((v) << 4) & 0x10) | ||
| 235 | #define BP_UARTAPP_LINECTRL2_STP2 3 | ||
| 236 | #define BM_UARTAPP_LINECTRL2_STP2 0x8 | ||
| 237 | #define BF_UARTAPP_LINECTRL2_STP2(v) (((v) << 3) & 0x8) | ||
| 238 | #define BP_UARTAPP_LINECTRL2_EPS 2 | ||
| 239 | #define BM_UARTAPP_LINECTRL2_EPS 0x4 | ||
| 240 | #define BF_UARTAPP_LINECTRL2_EPS(v) (((v) << 2) & 0x4) | ||
| 241 | #define BP_UARTAPP_LINECTRL2_PEN 1 | ||
| 242 | #define BM_UARTAPP_LINECTRL2_PEN 0x2 | ||
| 243 | #define BF_UARTAPP_LINECTRL2_PEN(v) (((v) << 1) & 0x2) | ||
| 244 | |||
| 245 | /** | ||
| 246 | * Register: HW_UARTAPP_INTR | ||
| 247 | * Address: 0x50 | ||
| 248 | * SCT: yes | ||
| 249 | */ | ||
| 250 | #define HW_UARTAPP_INTR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x0)) | ||
| 251 | #define HW_UARTAPP_INTR_SET(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x4)) | ||
| 252 | #define HW_UARTAPP_INTR_CLR(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0x8)) | ||
| 253 | #define HW_UARTAPP_INTR_TOG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x50 + 0xc)) | ||
| 254 | #define BP_UARTAPP_INTR_OEIEN 26 | ||
| 255 | #define BM_UARTAPP_INTR_OEIEN 0x4000000 | ||
| 256 | #define BF_UARTAPP_INTR_OEIEN(v) (((v) << 26) & 0x4000000) | ||
| 257 | #define BP_UARTAPP_INTR_BEIEN 25 | ||
| 258 | #define BM_UARTAPP_INTR_BEIEN 0x2000000 | ||
| 259 | #define BF_UARTAPP_INTR_BEIEN(v) (((v) << 25) & 0x2000000) | ||
| 260 | #define BP_UARTAPP_INTR_PEIEN 24 | ||
| 261 | #define BM_UARTAPP_INTR_PEIEN 0x1000000 | ||
| 262 | #define BF_UARTAPP_INTR_PEIEN(v) (((v) << 24) & 0x1000000) | ||
| 263 | #define BP_UARTAPP_INTR_FEIEN 23 | ||
| 264 | #define BM_UARTAPP_INTR_FEIEN 0x800000 | ||
| 265 | #define BF_UARTAPP_INTR_FEIEN(v) (((v) << 23) & 0x800000) | ||
| 266 | #define BP_UARTAPP_INTR_RTIEN 22 | ||
| 267 | #define BM_UARTAPP_INTR_RTIEN 0x400000 | ||
| 268 | #define BF_UARTAPP_INTR_RTIEN(v) (((v) << 22) & 0x400000) | ||
| 269 | #define BP_UARTAPP_INTR_TXIEN 21 | ||
| 270 | #define BM_UARTAPP_INTR_TXIEN 0x200000 | ||
| 271 | #define BF_UARTAPP_INTR_TXIEN(v) (((v) << 21) & 0x200000) | ||
| 272 | #define BP_UARTAPP_INTR_RXIEN 20 | ||
| 273 | #define BM_UARTAPP_INTR_RXIEN 0x100000 | ||
| 274 | #define BF_UARTAPP_INTR_RXIEN(v) (((v) << 20) & 0x100000) | ||
| 275 | #define BP_UARTAPP_INTR_DSRMIEN 19 | ||
| 276 | #define BM_UARTAPP_INTR_DSRMIEN 0x80000 | ||
| 277 | #define BF_UARTAPP_INTR_DSRMIEN(v) (((v) << 19) & 0x80000) | ||
| 278 | #define BP_UARTAPP_INTR_DCDMIEN 18 | ||
| 279 | #define BM_UARTAPP_INTR_DCDMIEN 0x40000 | ||
| 280 | #define BF_UARTAPP_INTR_DCDMIEN(v) (((v) << 18) & 0x40000) | ||
| 281 | #define BP_UARTAPP_INTR_CTSMIEN 17 | ||
| 282 | #define BM_UARTAPP_INTR_CTSMIEN 0x20000 | ||
| 283 | #define BF_UARTAPP_INTR_CTSMIEN(v) (((v) << 17) & 0x20000) | ||
| 284 | #define BP_UARTAPP_INTR_RIMIEN 16 | ||
| 285 | #define BM_UARTAPP_INTR_RIMIEN 0x10000 | ||
| 286 | #define BF_UARTAPP_INTR_RIMIEN(v) (((v) << 16) & 0x10000) | ||
| 287 | #define BP_UARTAPP_INTR_OEIS 10 | ||
| 288 | #define BM_UARTAPP_INTR_OEIS 0x400 | ||
| 289 | #define BF_UARTAPP_INTR_OEIS(v) (((v) << 10) & 0x400) | ||
| 290 | #define BP_UARTAPP_INTR_BEIS 9 | ||
| 291 | #define BM_UARTAPP_INTR_BEIS 0x200 | ||
| 292 | #define BF_UARTAPP_INTR_BEIS(v) (((v) << 9) & 0x200) | ||
| 293 | #define BP_UARTAPP_INTR_PEIS 8 | ||
| 294 | #define BM_UARTAPP_INTR_PEIS 0x100 | ||
| 295 | #define BF_UARTAPP_INTR_PEIS(v) (((v) << 8) & 0x100) | ||
| 296 | #define BP_UARTAPP_INTR_FEIS 7 | ||
| 297 | #define BM_UARTAPP_INTR_FEIS 0x80 | ||
| 298 | #define BF_UARTAPP_INTR_FEIS(v) (((v) << 7) & 0x80) | ||
| 299 | #define BP_UARTAPP_INTR_RTIS 6 | ||
| 300 | #define BM_UARTAPP_INTR_RTIS 0x40 | ||
| 301 | #define BF_UARTAPP_INTR_RTIS(v) (((v) << 6) & 0x40) | ||
| 302 | #define BP_UARTAPP_INTR_TXIS 5 | ||
| 303 | #define BM_UARTAPP_INTR_TXIS 0x20 | ||
| 304 | #define BF_UARTAPP_INTR_TXIS(v) (((v) << 5) & 0x20) | ||
| 305 | #define BP_UARTAPP_INTR_RXIS 4 | ||
| 306 | #define BM_UARTAPP_INTR_RXIS 0x10 | ||
| 307 | #define BF_UARTAPP_INTR_RXIS(v) (((v) << 4) & 0x10) | ||
| 308 | #define BP_UARTAPP_INTR_DSRMIS 3 | ||
| 309 | #define BM_UARTAPP_INTR_DSRMIS 0x8 | ||
| 310 | #define BF_UARTAPP_INTR_DSRMIS(v) (((v) << 3) & 0x8) | ||
| 311 | #define BP_UARTAPP_INTR_DCDMIS 2 | ||
| 312 | #define BM_UARTAPP_INTR_DCDMIS 0x4 | ||
| 313 | #define BF_UARTAPP_INTR_DCDMIS(v) (((v) << 2) & 0x4) | ||
| 314 | #define BP_UARTAPP_INTR_CTSMIS 1 | ||
| 315 | #define BM_UARTAPP_INTR_CTSMIS 0x2 | ||
| 316 | #define BF_UARTAPP_INTR_CTSMIS(v) (((v) << 1) & 0x2) | ||
| 317 | #define BP_UARTAPP_INTR_RIMIS 0 | ||
| 318 | #define BM_UARTAPP_INTR_RIMIS 0x1 | ||
| 319 | #define BF_UARTAPP_INTR_RIMIS(v) (((v) << 0) & 0x1) | ||
| 320 | |||
| 321 | /** | ||
| 322 | * Register: HW_UARTAPP_DATA | ||
| 323 | * Address: 0x60 | ||
| 324 | * SCT: no | ||
| 325 | */ | ||
| 326 | #define HW_UARTAPP_DATA(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x60)) | ||
| 327 | #define BP_UARTAPP_DATA_DATA 0 | ||
| 328 | #define BM_UARTAPP_DATA_DATA 0xffffffff | ||
| 329 | #define BF_UARTAPP_DATA_DATA(v) (((v) << 0) & 0xffffffff) | ||
| 330 | |||
| 331 | /** | ||
| 332 | * Register: HW_UARTAPP_STAT | ||
| 333 | * Address: 0x70 | ||
| 334 | * SCT: no | ||
| 335 | */ | ||
| 336 | #define HW_UARTAPP_STAT(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x70)) | ||
| 337 | #define BP_UARTAPP_STAT_PRESENT 31 | ||
| 338 | #define BM_UARTAPP_STAT_PRESENT 0x80000000 | ||
| 339 | #define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 | ||
| 340 | #define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 | ||
| 341 | #define BF_UARTAPP_STAT_PRESENT(v) (((v) << 31) & 0x80000000) | ||
| 342 | #define BF_UARTAPP_STAT_PRESENT_V(v) ((BV_UARTAPP_STAT_PRESENT__##v << 31) & 0x80000000) | ||
| 343 | #define BP_UARTAPP_STAT_HISPEED 30 | ||
| 344 | #define BM_UARTAPP_STAT_HISPEED 0x40000000 | ||
| 345 | #define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 | ||
| 346 | #define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 | ||
| 347 | #define BF_UARTAPP_STAT_HISPEED(v) (((v) << 30) & 0x40000000) | ||
| 348 | #define BF_UARTAPP_STAT_HISPEED_V(v) ((BV_UARTAPP_STAT_HISPEED__##v << 30) & 0x40000000) | ||
| 349 | #define BP_UARTAPP_STAT_BUSY 29 | ||
| 350 | #define BM_UARTAPP_STAT_BUSY 0x20000000 | ||
| 351 | #define BF_UARTAPP_STAT_BUSY(v) (((v) << 29) & 0x20000000) | ||
| 352 | #define BP_UARTAPP_STAT_CTS 28 | ||
| 353 | #define BM_UARTAPP_STAT_CTS 0x10000000 | ||
| 354 | #define BF_UARTAPP_STAT_CTS(v) (((v) << 28) & 0x10000000) | ||
| 355 | #define BP_UARTAPP_STAT_TXFE 27 | ||
| 356 | #define BM_UARTAPP_STAT_TXFE 0x8000000 | ||
| 357 | #define BF_UARTAPP_STAT_TXFE(v) (((v) << 27) & 0x8000000) | ||
| 358 | #define BP_UARTAPP_STAT_RXFF 26 | ||
| 359 | #define BM_UARTAPP_STAT_RXFF 0x4000000 | ||
| 360 | #define BF_UARTAPP_STAT_RXFF(v) (((v) << 26) & 0x4000000) | ||
| 361 | #define BP_UARTAPP_STAT_TXFF 25 | ||
| 362 | #define BM_UARTAPP_STAT_TXFF 0x2000000 | ||
| 363 | #define BF_UARTAPP_STAT_TXFF(v) (((v) << 25) & 0x2000000) | ||
| 364 | #define BP_UARTAPP_STAT_RXFE 24 | ||
| 365 | #define BM_UARTAPP_STAT_RXFE 0x1000000 | ||
| 366 | #define BF_UARTAPP_STAT_RXFE(v) (((v) << 24) & 0x1000000) | ||
| 367 | #define BP_UARTAPP_STAT_RXBYTE_INVALID 20 | ||
| 368 | #define BM_UARTAPP_STAT_RXBYTE_INVALID 0xf00000 | ||
| 369 | #define BF_UARTAPP_STAT_RXBYTE_INVALID(v) (((v) << 20) & 0xf00000) | ||
| 370 | #define BP_UARTAPP_STAT_OERR 19 | ||
| 371 | #define BM_UARTAPP_STAT_OERR 0x80000 | ||
| 372 | #define BF_UARTAPP_STAT_OERR(v) (((v) << 19) & 0x80000) | ||
| 373 | #define BP_UARTAPP_STAT_BERR 18 | ||
| 374 | #define BM_UARTAPP_STAT_BERR 0x40000 | ||
| 375 | #define BF_UARTAPP_STAT_BERR(v) (((v) << 18) & 0x40000) | ||
| 376 | #define BP_UARTAPP_STAT_PERR 17 | ||
| 377 | #define BM_UARTAPP_STAT_PERR 0x20000 | ||
| 378 | #define BF_UARTAPP_STAT_PERR(v) (((v) << 17) & 0x20000) | ||
| 379 | #define BP_UARTAPP_STAT_FERR 16 | ||
| 380 | #define BM_UARTAPP_STAT_FERR 0x10000 | ||
| 381 | #define BF_UARTAPP_STAT_FERR(v) (((v) << 16) & 0x10000) | ||
| 382 | #define BP_UARTAPP_STAT_RXCOUNT 0 | ||
| 383 | #define BM_UARTAPP_STAT_RXCOUNT 0xffff | ||
| 384 | #define BF_UARTAPP_STAT_RXCOUNT(v) (((v) << 0) & 0xffff) | ||
| 385 | |||
| 386 | /** | ||
| 387 | * Register: HW_UARTAPP_DEBUG | ||
| 388 | * Address: 0x80 | ||
| 389 | * SCT: no | ||
| 390 | */ | ||
| 391 | #define HW_UARTAPP_DEBUG(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x80)) | ||
| 392 | #define BP_UARTAPP_DEBUG_TXDMARUN 5 | ||
| 393 | #define BM_UARTAPP_DEBUG_TXDMARUN 0x20 | ||
| 394 | #define BF_UARTAPP_DEBUG_TXDMARUN(v) (((v) << 5) & 0x20) | ||
| 395 | #define BP_UARTAPP_DEBUG_RXDMARUN 4 | ||
| 396 | #define BM_UARTAPP_DEBUG_RXDMARUN 0x10 | ||
| 397 | #define BF_UARTAPP_DEBUG_RXDMARUN(v) (((v) << 4) & 0x10) | ||
| 398 | #define BP_UARTAPP_DEBUG_TXCMDEND 3 | ||
| 399 | #define BM_UARTAPP_DEBUG_TXCMDEND 0x8 | ||
| 400 | #define BF_UARTAPP_DEBUG_TXCMDEND(v) (((v) << 3) & 0x8) | ||
| 401 | #define BP_UARTAPP_DEBUG_RXCMDEND 2 | ||
| 402 | #define BM_UARTAPP_DEBUG_RXCMDEND 0x4 | ||
| 403 | #define BF_UARTAPP_DEBUG_RXCMDEND(v) (((v) << 2) & 0x4) | ||
| 404 | #define BP_UARTAPP_DEBUG_TXDMARQ 1 | ||
| 405 | #define BM_UARTAPP_DEBUG_TXDMARQ 0x2 | ||
| 406 | #define BF_UARTAPP_DEBUG_TXDMARQ(v) (((v) << 1) & 0x2) | ||
| 407 | #define BP_UARTAPP_DEBUG_RXDMARQ 0 | ||
| 408 | #define BM_UARTAPP_DEBUG_RXDMARQ 0x1 | ||
| 409 | #define BF_UARTAPP_DEBUG_RXDMARQ(v) (((v) << 0) & 0x1) | ||
| 410 | |||
| 411 | /** | ||
| 412 | * Register: HW_UARTAPP_VERSION | ||
| 413 | * Address: 0x90 | ||
| 414 | * SCT: no | ||
| 415 | */ | ||
| 416 | #define HW_UARTAPP_VERSION(d) (*(volatile unsigned long *)(REGS_UARTAPP_BASE(d) + 0x90)) | ||
| 417 | #define BP_UARTAPP_VERSION_MAJOR 24 | ||
| 418 | #define BM_UARTAPP_VERSION_MAJOR 0xff000000 | ||
| 419 | #define BF_UARTAPP_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 420 | #define BP_UARTAPP_VERSION_MINOR 16 | ||
| 421 | #define BM_UARTAPP_VERSION_MINOR 0xff0000 | ||
| 422 | #define BF_UARTAPP_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 423 | #define BP_UARTAPP_VERSION_STEP 0 | ||
| 424 | #define BM_UARTAPP_VERSION_STEP 0xffff | ||
| 425 | #define BF_UARTAPP_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 426 | |||
| 427 | #endif /* __HEADERGEN__STMP3700__UARTAPP__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h b/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h new file mode 100644 index 0000000000..d1ef6f2608 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-uartdbg.h | |||
| @@ -0,0 +1,491 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__UARTDBG__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__UARTDBG__H__ | ||
| 25 | |||
| 26 | #define REGS_UARTDBG_BASE (0x80070000) | ||
| 27 | |||
| 28 | #define REGS_UARTDBG_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_UARTDBG_DR | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: no | ||
| 34 | */ | ||
| 35 | #define HW_UARTDBG_DR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x0)) | ||
| 36 | #define BP_UARTDBG_DR_UNAVAILABLE 16 | ||
| 37 | #define BM_UARTDBG_DR_UNAVAILABLE 0xffff0000 | ||
| 38 | #define BF_UARTDBG_DR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 39 | #define BP_UARTDBG_DR_RESERVED 12 | ||
| 40 | #define BM_UARTDBG_DR_RESERVED 0xf000 | ||
| 41 | #define BF_UARTDBG_DR_RESERVED(v) (((v) << 12) & 0xf000) | ||
| 42 | #define BP_UARTDBG_DR_OE 11 | ||
| 43 | #define BM_UARTDBG_DR_OE 0x800 | ||
| 44 | #define BF_UARTDBG_DR_OE(v) (((v) << 11) & 0x800) | ||
| 45 | #define BP_UARTDBG_DR_BE 10 | ||
| 46 | #define BM_UARTDBG_DR_BE 0x400 | ||
| 47 | #define BF_UARTDBG_DR_BE(v) (((v) << 10) & 0x400) | ||
| 48 | #define BP_UARTDBG_DR_PE 9 | ||
| 49 | #define BM_UARTDBG_DR_PE 0x200 | ||
| 50 | #define BF_UARTDBG_DR_PE(v) (((v) << 9) & 0x200) | ||
| 51 | #define BP_UARTDBG_DR_FE 8 | ||
| 52 | #define BM_UARTDBG_DR_FE 0x100 | ||
| 53 | #define BF_UARTDBG_DR_FE(v) (((v) << 8) & 0x100) | ||
| 54 | #define BP_UARTDBG_DR_DATA 0 | ||
| 55 | #define BM_UARTDBG_DR_DATA 0xff | ||
| 56 | #define BF_UARTDBG_DR_DATA(v) (((v) << 0) & 0xff) | ||
| 57 | |||
| 58 | /** | ||
| 59 | * Register: HW_UARTDBG_RSR_ECR | ||
| 60 | * Address: 0x4 | ||
| 61 | * SCT: no | ||
| 62 | */ | ||
| 63 | #define HW_UARTDBG_RSR_ECR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x4)) | ||
| 64 | #define BP_UARTDBG_RSR_ECR_UNAVAILABLE 8 | ||
| 65 | #define BM_UARTDBG_RSR_ECR_UNAVAILABLE 0xffffff00 | ||
| 66 | #define BF_UARTDBG_RSR_ECR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
| 67 | #define BP_UARTDBG_RSR_ECR_EC 4 | ||
| 68 | #define BM_UARTDBG_RSR_ECR_EC 0xf0 | ||
| 69 | #define BF_UARTDBG_RSR_ECR_EC(v) (((v) << 4) & 0xf0) | ||
| 70 | #define BP_UARTDBG_RSR_ECR_OE 3 | ||
| 71 | #define BM_UARTDBG_RSR_ECR_OE 0x8 | ||
| 72 | #define BF_UARTDBG_RSR_ECR_OE(v) (((v) << 3) & 0x8) | ||
| 73 | #define BP_UARTDBG_RSR_ECR_BE 2 | ||
| 74 | #define BM_UARTDBG_RSR_ECR_BE 0x4 | ||
| 75 | #define BF_UARTDBG_RSR_ECR_BE(v) (((v) << 2) & 0x4) | ||
| 76 | #define BP_UARTDBG_RSR_ECR_PE 1 | ||
| 77 | #define BM_UARTDBG_RSR_ECR_PE 0x2 | ||
| 78 | #define BF_UARTDBG_RSR_ECR_PE(v) (((v) << 1) & 0x2) | ||
| 79 | #define BP_UARTDBG_RSR_ECR_FE 0 | ||
| 80 | #define BM_UARTDBG_RSR_ECR_FE 0x1 | ||
| 81 | #define BF_UARTDBG_RSR_ECR_FE(v) (((v) << 0) & 0x1) | ||
| 82 | |||
| 83 | /** | ||
| 84 | * Register: HW_UARTDBG_FR | ||
| 85 | * Address: 0x18 | ||
| 86 | * SCT: no | ||
| 87 | */ | ||
| 88 | #define HW_UARTDBG_FR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x18)) | ||
| 89 | #define BP_UARTDBG_FR_UNAVAILABLE 16 | ||
| 90 | #define BM_UARTDBG_FR_UNAVAILABLE 0xffff0000 | ||
| 91 | #define BF_UARTDBG_FR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 92 | #define BP_UARTDBG_FR_RESERVED 9 | ||
| 93 | #define BM_UARTDBG_FR_RESERVED 0xfe00 | ||
| 94 | #define BF_UARTDBG_FR_RESERVED(v) (((v) << 9) & 0xfe00) | ||
| 95 | #define BP_UARTDBG_FR_RI 8 | ||
| 96 | #define BM_UARTDBG_FR_RI 0x100 | ||
| 97 | #define BF_UARTDBG_FR_RI(v) (((v) << 8) & 0x100) | ||
| 98 | #define BP_UARTDBG_FR_TXFE 7 | ||
| 99 | #define BM_UARTDBG_FR_TXFE 0x80 | ||
| 100 | #define BF_UARTDBG_FR_TXFE(v) (((v) << 7) & 0x80) | ||
| 101 | #define BP_UARTDBG_FR_RXFF 6 | ||
| 102 | #define BM_UARTDBG_FR_RXFF 0x40 | ||
| 103 | #define BF_UARTDBG_FR_RXFF(v) (((v) << 6) & 0x40) | ||
| 104 | #define BP_UARTDBG_FR_TXFF 5 | ||
| 105 | #define BM_UARTDBG_FR_TXFF 0x20 | ||
| 106 | #define BF_UARTDBG_FR_TXFF(v) (((v) << 5) & 0x20) | ||
| 107 | #define BP_UARTDBG_FR_RXFE 4 | ||
| 108 | #define BM_UARTDBG_FR_RXFE 0x10 | ||
| 109 | #define BF_UARTDBG_FR_RXFE(v) (((v) << 4) & 0x10) | ||
| 110 | #define BP_UARTDBG_FR_BUSY 3 | ||
| 111 | #define BM_UARTDBG_FR_BUSY 0x8 | ||
| 112 | #define BF_UARTDBG_FR_BUSY(v) (((v) << 3) & 0x8) | ||
| 113 | #define BP_UARTDBG_FR_DCD 2 | ||
| 114 | #define BM_UARTDBG_FR_DCD 0x4 | ||
| 115 | #define BF_UARTDBG_FR_DCD(v) (((v) << 2) & 0x4) | ||
| 116 | #define BP_UARTDBG_FR_DSR 1 | ||
| 117 | #define BM_UARTDBG_FR_DSR 0x2 | ||
| 118 | #define BF_UARTDBG_FR_DSR(v) (((v) << 1) & 0x2) | ||
| 119 | #define BP_UARTDBG_FR_CTS 0 | ||
| 120 | #define BM_UARTDBG_FR_CTS 0x1 | ||
| 121 | #define BF_UARTDBG_FR_CTS(v) (((v) << 0) & 0x1) | ||
| 122 | |||
| 123 | /** | ||
| 124 | * Register: HW_UARTDBG_ILPR | ||
| 125 | * Address: 0x20 | ||
| 126 | * SCT: no | ||
| 127 | */ | ||
| 128 | #define HW_UARTDBG_ILPR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x20)) | ||
| 129 | #define BP_UARTDBG_ILPR_UNAVAILABLE 8 | ||
| 130 | #define BM_UARTDBG_ILPR_UNAVAILABLE 0xffffff00 | ||
| 131 | #define BF_UARTDBG_ILPR_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
| 132 | #define BP_UARTDBG_ILPR_ILPDVSR 0 | ||
| 133 | #define BM_UARTDBG_ILPR_ILPDVSR 0xff | ||
| 134 | #define BF_UARTDBG_ILPR_ILPDVSR(v) (((v) << 0) & 0xff) | ||
| 135 | |||
| 136 | /** | ||
| 137 | * Register: HW_UARTDBG_IBRD | ||
| 138 | * Address: 0x24 | ||
| 139 | * SCT: no | ||
| 140 | */ | ||
| 141 | #define HW_UARTDBG_IBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x24)) | ||
| 142 | #define BP_UARTDBG_IBRD_UNAVAILABLE 16 | ||
| 143 | #define BM_UARTDBG_IBRD_UNAVAILABLE 0xffff0000 | ||
| 144 | #define BF_UARTDBG_IBRD_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 145 | #define BP_UARTDBG_IBRD_BAUD_DIVINT 0 | ||
| 146 | #define BM_UARTDBG_IBRD_BAUD_DIVINT 0xffff | ||
| 147 | #define BF_UARTDBG_IBRD_BAUD_DIVINT(v) (((v) << 0) & 0xffff) | ||
| 148 | |||
| 149 | /** | ||
| 150 | * Register: HW_UARTDBG_FBRD | ||
| 151 | * Address: 0x28 | ||
| 152 | * SCT: no | ||
| 153 | */ | ||
| 154 | #define HW_UARTDBG_FBRD (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x28)) | ||
| 155 | #define BP_UARTDBG_FBRD_UNAVAILABLE 8 | ||
| 156 | #define BM_UARTDBG_FBRD_UNAVAILABLE 0xffffff00 | ||
| 157 | #define BF_UARTDBG_FBRD_UNAVAILABLE(v) (((v) << 8) & 0xffffff00) | ||
| 158 | #define BP_UARTDBG_FBRD_RESERVED 6 | ||
| 159 | #define BM_UARTDBG_FBRD_RESERVED 0xc0 | ||
| 160 | #define BF_UARTDBG_FBRD_RESERVED(v) (((v) << 6) & 0xc0) | ||
| 161 | #define BP_UARTDBG_FBRD_BAUD_DIVFRAC 0 | ||
| 162 | #define BM_UARTDBG_FBRD_BAUD_DIVFRAC 0x3f | ||
| 163 | #define BF_UARTDBG_FBRD_BAUD_DIVFRAC(v) (((v) << 0) & 0x3f) | ||
| 164 | |||
| 165 | /** | ||
| 166 | * Register: HW_UARTDBG_LCR_H | ||
| 167 | * Address: 0x2c | ||
| 168 | * SCT: no | ||
| 169 | */ | ||
| 170 | #define HW_UARTDBG_LCR_H (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x2c)) | ||
| 171 | #define BP_UARTDBG_LCR_H_UNAVAILABLE 16 | ||
| 172 | #define BM_UARTDBG_LCR_H_UNAVAILABLE 0xffff0000 | ||
| 173 | #define BF_UARTDBG_LCR_H_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 174 | #define BP_UARTDBG_LCR_H_RESERVED 8 | ||
| 175 | #define BM_UARTDBG_LCR_H_RESERVED 0xff00 | ||
| 176 | #define BF_UARTDBG_LCR_H_RESERVED(v) (((v) << 8) & 0xff00) | ||
| 177 | #define BP_UARTDBG_LCR_H_SPS 7 | ||
| 178 | #define BM_UARTDBG_LCR_H_SPS 0x80 | ||
| 179 | #define BF_UARTDBG_LCR_H_SPS(v) (((v) << 7) & 0x80) | ||
| 180 | #define BP_UARTDBG_LCR_H_WLEN 5 | ||
| 181 | #define BM_UARTDBG_LCR_H_WLEN 0x60 | ||
| 182 | #define BF_UARTDBG_LCR_H_WLEN(v) (((v) << 5) & 0x60) | ||
| 183 | #define BP_UARTDBG_LCR_H_FEN 4 | ||
| 184 | #define BM_UARTDBG_LCR_H_FEN 0x10 | ||
| 185 | #define BF_UARTDBG_LCR_H_FEN(v) (((v) << 4) & 0x10) | ||
| 186 | #define BP_UARTDBG_LCR_H_STP2 3 | ||
| 187 | #define BM_UARTDBG_LCR_H_STP2 0x8 | ||
| 188 | #define BF_UARTDBG_LCR_H_STP2(v) (((v) << 3) & 0x8) | ||
| 189 | #define BP_UARTDBG_LCR_H_EPS 2 | ||
| 190 | #define BM_UARTDBG_LCR_H_EPS 0x4 | ||
| 191 | #define BF_UARTDBG_LCR_H_EPS(v) (((v) << 2) & 0x4) | ||
| 192 | #define BP_UARTDBG_LCR_H_PEN 1 | ||
| 193 | #define BM_UARTDBG_LCR_H_PEN 0x2 | ||
| 194 | #define BF_UARTDBG_LCR_H_PEN(v) (((v) << 1) & 0x2) | ||
| 195 | #define BP_UARTDBG_LCR_H_BRK 0 | ||
| 196 | #define BM_UARTDBG_LCR_H_BRK 0x1 | ||
| 197 | #define BF_UARTDBG_LCR_H_BRK(v) (((v) << 0) & 0x1) | ||
| 198 | |||
| 199 | /** | ||
| 200 | * Register: HW_UARTDBG_CR | ||
| 201 | * Address: 0x30 | ||
| 202 | * SCT: no | ||
| 203 | */ | ||
| 204 | #define HW_UARTDBG_CR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x30)) | ||
| 205 | #define BP_UARTDBG_CR_UNAVAILABLE 16 | ||
| 206 | #define BM_UARTDBG_CR_UNAVAILABLE 0xffff0000 | ||
| 207 | #define BF_UARTDBG_CR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 208 | #define BP_UARTDBG_CR_CTSEN 15 | ||
| 209 | #define BM_UARTDBG_CR_CTSEN 0x8000 | ||
| 210 | #define BF_UARTDBG_CR_CTSEN(v) (((v) << 15) & 0x8000) | ||
| 211 | #define BP_UARTDBG_CR_RTSEN 14 | ||
| 212 | #define BM_UARTDBG_CR_RTSEN 0x4000 | ||
| 213 | #define BF_UARTDBG_CR_RTSEN(v) (((v) << 14) & 0x4000) | ||
| 214 | #define BP_UARTDBG_CR_OUT2 13 | ||
| 215 | #define BM_UARTDBG_CR_OUT2 0x2000 | ||
| 216 | #define BF_UARTDBG_CR_OUT2(v) (((v) << 13) & 0x2000) | ||
| 217 | #define BP_UARTDBG_CR_OUT1 12 | ||
| 218 | #define BM_UARTDBG_CR_OUT1 0x1000 | ||
| 219 | #define BF_UARTDBG_CR_OUT1(v) (((v) << 12) & 0x1000) | ||
| 220 | #define BP_UARTDBG_CR_RTS 11 | ||
| 221 | #define BM_UARTDBG_CR_RTS 0x800 | ||
| 222 | #define BF_UARTDBG_CR_RTS(v) (((v) << 11) & 0x800) | ||
| 223 | #define BP_UARTDBG_CR_DTR 10 | ||
| 224 | #define BM_UARTDBG_CR_DTR 0x400 | ||
| 225 | #define BF_UARTDBG_CR_DTR(v) (((v) << 10) & 0x400) | ||
| 226 | #define BP_UARTDBG_CR_RXE 9 | ||
| 227 | #define BM_UARTDBG_CR_RXE 0x200 | ||
| 228 | #define BF_UARTDBG_CR_RXE(v) (((v) << 9) & 0x200) | ||
| 229 | #define BP_UARTDBG_CR_TXE 8 | ||
| 230 | #define BM_UARTDBG_CR_TXE 0x100 | ||
| 231 | #define BF_UARTDBG_CR_TXE(v) (((v) << 8) & 0x100) | ||
| 232 | #define BP_UARTDBG_CR_LBE 7 | ||
| 233 | #define BM_UARTDBG_CR_LBE 0x80 | ||
| 234 | #define BF_UARTDBG_CR_LBE(v) (((v) << 7) & 0x80) | ||
| 235 | #define BP_UARTDBG_CR_RESERVED 3 | ||
| 236 | #define BM_UARTDBG_CR_RESERVED 0x78 | ||
| 237 | #define BF_UARTDBG_CR_RESERVED(v) (((v) << 3) & 0x78) | ||
| 238 | #define BP_UARTDBG_CR_SIRLP 2 | ||
| 239 | #define BM_UARTDBG_CR_SIRLP 0x4 | ||
| 240 | #define BF_UARTDBG_CR_SIRLP(v) (((v) << 2) & 0x4) | ||
| 241 | #define BP_UARTDBG_CR_SIREN 1 | ||
| 242 | #define BM_UARTDBG_CR_SIREN 0x2 | ||
| 243 | #define BF_UARTDBG_CR_SIREN(v) (((v) << 1) & 0x2) | ||
| 244 | #define BP_UARTDBG_CR_UARTEN 0 | ||
| 245 | #define BM_UARTDBG_CR_UARTEN 0x1 | ||
| 246 | #define BF_UARTDBG_CR_UARTEN(v) (((v) << 0) & 0x1) | ||
| 247 | |||
| 248 | /** | ||
| 249 | * Register: HW_UARTDBG_IFLS | ||
| 250 | * Address: 0x34 | ||
| 251 | * SCT: no | ||
| 252 | */ | ||
| 253 | #define HW_UARTDBG_IFLS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x34)) | ||
| 254 | #define BP_UARTDBG_IFLS_UNAVAILABLE 16 | ||
| 255 | #define BM_UARTDBG_IFLS_UNAVAILABLE 0xffff0000 | ||
| 256 | #define BF_UARTDBG_IFLS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 257 | #define BP_UARTDBG_IFLS_RESERVED 6 | ||
| 258 | #define BM_UARTDBG_IFLS_RESERVED 0xffc0 | ||
| 259 | #define BF_UARTDBG_IFLS_RESERVED(v) (((v) << 6) & 0xffc0) | ||
| 260 | #define BP_UARTDBG_IFLS_RXIFLSEL 3 | ||
| 261 | #define BM_UARTDBG_IFLS_RXIFLSEL 0x38 | ||
| 262 | #define BV_UARTDBG_IFLS_RXIFLSEL__NOT_EMPTY 0x0 | ||
| 263 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_QUARTER 0x1 | ||
| 264 | #define BV_UARTDBG_IFLS_RXIFLSEL__ONE_HALF 0x2 | ||
| 265 | #define BV_UARTDBG_IFLS_RXIFLSEL__THREE_QUARTERS 0x3 | ||
| 266 | #define BV_UARTDBG_IFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 267 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID5 0x5 | ||
| 268 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID6 0x6 | ||
| 269 | #define BV_UARTDBG_IFLS_RXIFLSEL__INVALID7 0x7 | ||
| 270 | #define BF_UARTDBG_IFLS_RXIFLSEL(v) (((v) << 3) & 0x38) | ||
| 271 | #define BF_UARTDBG_IFLS_RXIFLSEL_V(v) ((BV_UARTDBG_IFLS_RXIFLSEL__##v << 3) & 0x38) | ||
| 272 | #define BP_UARTDBG_IFLS_TXIFLSEL 0 | ||
| 273 | #define BM_UARTDBG_IFLS_TXIFLSEL 0x7 | ||
| 274 | #define BV_UARTDBG_IFLS_TXIFLSEL__EMPTY 0x0 | ||
| 275 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_QUARTER 0x1 | ||
| 276 | #define BV_UARTDBG_IFLS_TXIFLSEL__ONE_HALF 0x2 | ||
| 277 | #define BV_UARTDBG_IFLS_TXIFLSEL__THREE_QUARTERS 0x3 | ||
| 278 | #define BV_UARTDBG_IFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 | ||
| 279 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID5 0x5 | ||
| 280 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID6 0x6 | ||
| 281 | #define BV_UARTDBG_IFLS_TXIFLSEL__INVALID7 0x7 | ||
| 282 | #define BF_UARTDBG_IFLS_TXIFLSEL(v) (((v) << 0) & 0x7) | ||
| 283 | #define BF_UARTDBG_IFLS_TXIFLSEL_V(v) ((BV_UARTDBG_IFLS_TXIFLSEL__##v << 0) & 0x7) | ||
| 284 | |||
| 285 | /** | ||
| 286 | * Register: HW_UARTDBG_IMSC | ||
| 287 | * Address: 0x38 | ||
| 288 | * SCT: no | ||
| 289 | */ | ||
| 290 | #define HW_UARTDBG_IMSC (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x38)) | ||
| 291 | #define BP_UARTDBG_IMSC_UNAVAILABLE 16 | ||
| 292 | #define BM_UARTDBG_IMSC_UNAVAILABLE 0xffff0000 | ||
| 293 | #define BF_UARTDBG_IMSC_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 294 | #define BP_UARTDBG_IMSC_RESERVED 11 | ||
| 295 | #define BM_UARTDBG_IMSC_RESERVED 0xf800 | ||
| 296 | #define BF_UARTDBG_IMSC_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 297 | #define BP_UARTDBG_IMSC_OEIM 10 | ||
| 298 | #define BM_UARTDBG_IMSC_OEIM 0x400 | ||
| 299 | #define BF_UARTDBG_IMSC_OEIM(v) (((v) << 10) & 0x400) | ||
| 300 | #define BP_UARTDBG_IMSC_BEIM 9 | ||
| 301 | #define BM_UARTDBG_IMSC_BEIM 0x200 | ||
| 302 | #define BF_UARTDBG_IMSC_BEIM(v) (((v) << 9) & 0x200) | ||
| 303 | #define BP_UARTDBG_IMSC_PEIM 8 | ||
| 304 | #define BM_UARTDBG_IMSC_PEIM 0x100 | ||
| 305 | #define BF_UARTDBG_IMSC_PEIM(v) (((v) << 8) & 0x100) | ||
| 306 | #define BP_UARTDBG_IMSC_FEIM 7 | ||
| 307 | #define BM_UARTDBG_IMSC_FEIM 0x80 | ||
| 308 | #define BF_UARTDBG_IMSC_FEIM(v) (((v) << 7) & 0x80) | ||
| 309 | #define BP_UARTDBG_IMSC_RTIM 6 | ||
| 310 | #define BM_UARTDBG_IMSC_RTIM 0x40 | ||
| 311 | #define BF_UARTDBG_IMSC_RTIM(v) (((v) << 6) & 0x40) | ||
| 312 | #define BP_UARTDBG_IMSC_TXIM 5 | ||
| 313 | #define BM_UARTDBG_IMSC_TXIM 0x20 | ||
| 314 | #define BF_UARTDBG_IMSC_TXIM(v) (((v) << 5) & 0x20) | ||
| 315 | #define BP_UARTDBG_IMSC_RXIM 4 | ||
| 316 | #define BM_UARTDBG_IMSC_RXIM 0x10 | ||
| 317 | #define BF_UARTDBG_IMSC_RXIM(v) (((v) << 4) & 0x10) | ||
| 318 | #define BP_UARTDBG_IMSC_DSRMIM 3 | ||
| 319 | #define BM_UARTDBG_IMSC_DSRMIM 0x8 | ||
| 320 | #define BF_UARTDBG_IMSC_DSRMIM(v) (((v) << 3) & 0x8) | ||
| 321 | #define BP_UARTDBG_IMSC_DCDMIM 2 | ||
| 322 | #define BM_UARTDBG_IMSC_DCDMIM 0x4 | ||
| 323 | #define BF_UARTDBG_IMSC_DCDMIM(v) (((v) << 2) & 0x4) | ||
| 324 | #define BP_UARTDBG_IMSC_CTSMIM 1 | ||
| 325 | #define BM_UARTDBG_IMSC_CTSMIM 0x2 | ||
| 326 | #define BF_UARTDBG_IMSC_CTSMIM(v) (((v) << 1) & 0x2) | ||
| 327 | #define BP_UARTDBG_IMSC_RIMIM 0 | ||
| 328 | #define BM_UARTDBG_IMSC_RIMIM 0x1 | ||
| 329 | #define BF_UARTDBG_IMSC_RIMIM(v) (((v) << 0) & 0x1) | ||
| 330 | |||
| 331 | /** | ||
| 332 | * Register: HW_UARTDBG_RIS | ||
| 333 | * Address: 0x3c | ||
| 334 | * SCT: no | ||
| 335 | */ | ||
| 336 | #define HW_UARTDBG_RIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x3c)) | ||
| 337 | #define BP_UARTDBG_RIS_UNAVAILABLE 16 | ||
| 338 | #define BM_UARTDBG_RIS_UNAVAILABLE 0xffff0000 | ||
| 339 | #define BF_UARTDBG_RIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 340 | #define BP_UARTDBG_RIS_RESERVED 11 | ||
| 341 | #define BM_UARTDBG_RIS_RESERVED 0xf800 | ||
| 342 | #define BF_UARTDBG_RIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 343 | #define BP_UARTDBG_RIS_OERIS 10 | ||
| 344 | #define BM_UARTDBG_RIS_OERIS 0x400 | ||
| 345 | #define BF_UARTDBG_RIS_OERIS(v) (((v) << 10) & 0x400) | ||
| 346 | #define BP_UARTDBG_RIS_BERIS 9 | ||
| 347 | #define BM_UARTDBG_RIS_BERIS 0x200 | ||
| 348 | #define BF_UARTDBG_RIS_BERIS(v) (((v) << 9) & 0x200) | ||
| 349 | #define BP_UARTDBG_RIS_PERIS 8 | ||
| 350 | #define BM_UARTDBG_RIS_PERIS 0x100 | ||
| 351 | #define BF_UARTDBG_RIS_PERIS(v) (((v) << 8) & 0x100) | ||
| 352 | #define BP_UARTDBG_RIS_FERIS 7 | ||
| 353 | #define BM_UARTDBG_RIS_FERIS 0x80 | ||
| 354 | #define BF_UARTDBG_RIS_FERIS(v) (((v) << 7) & 0x80) | ||
| 355 | #define BP_UARTDBG_RIS_RTRIS 6 | ||
| 356 | #define BM_UARTDBG_RIS_RTRIS 0x40 | ||
| 357 | #define BF_UARTDBG_RIS_RTRIS(v) (((v) << 6) & 0x40) | ||
| 358 | #define BP_UARTDBG_RIS_TXRIS 5 | ||
| 359 | #define BM_UARTDBG_RIS_TXRIS 0x20 | ||
| 360 | #define BF_UARTDBG_RIS_TXRIS(v) (((v) << 5) & 0x20) | ||
| 361 | #define BP_UARTDBG_RIS_RXRIS 4 | ||
| 362 | #define BM_UARTDBG_RIS_RXRIS 0x10 | ||
| 363 | #define BF_UARTDBG_RIS_RXRIS(v) (((v) << 4) & 0x10) | ||
| 364 | #define BP_UARTDBG_RIS_DSRRMIS 3 | ||
| 365 | #define BM_UARTDBG_RIS_DSRRMIS 0x8 | ||
| 366 | #define BF_UARTDBG_RIS_DSRRMIS(v) (((v) << 3) & 0x8) | ||
| 367 | #define BP_UARTDBG_RIS_DCDRMIS 2 | ||
| 368 | #define BM_UARTDBG_RIS_DCDRMIS 0x4 | ||
| 369 | #define BF_UARTDBG_RIS_DCDRMIS(v) (((v) << 2) & 0x4) | ||
| 370 | #define BP_UARTDBG_RIS_CTSRMIS 1 | ||
| 371 | #define BM_UARTDBG_RIS_CTSRMIS 0x2 | ||
| 372 | #define BF_UARTDBG_RIS_CTSRMIS(v) (((v) << 1) & 0x2) | ||
| 373 | #define BP_UARTDBG_RIS_RIRMIS 0 | ||
| 374 | #define BM_UARTDBG_RIS_RIRMIS 0x1 | ||
| 375 | #define BF_UARTDBG_RIS_RIRMIS(v) (((v) << 0) & 0x1) | ||
| 376 | |||
| 377 | /** | ||
| 378 | * Register: HW_UARTDBG_MIS | ||
| 379 | * Address: 0x40 | ||
| 380 | * SCT: no | ||
| 381 | */ | ||
| 382 | #define HW_UARTDBG_MIS (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x40)) | ||
| 383 | #define BP_UARTDBG_MIS_UNAVAILABLE 16 | ||
| 384 | #define BM_UARTDBG_MIS_UNAVAILABLE 0xffff0000 | ||
| 385 | #define BF_UARTDBG_MIS_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 386 | #define BP_UARTDBG_MIS_RESERVED 11 | ||
| 387 | #define BM_UARTDBG_MIS_RESERVED 0xf800 | ||
| 388 | #define BF_UARTDBG_MIS_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 389 | #define BP_UARTDBG_MIS_OEMIS 10 | ||
| 390 | #define BM_UARTDBG_MIS_OEMIS 0x400 | ||
| 391 | #define BF_UARTDBG_MIS_OEMIS(v) (((v) << 10) & 0x400) | ||
| 392 | #define BP_UARTDBG_MIS_BEMIS 9 | ||
| 393 | #define BM_UARTDBG_MIS_BEMIS 0x200 | ||
| 394 | #define BF_UARTDBG_MIS_BEMIS(v) (((v) << 9) & 0x200) | ||
| 395 | #define BP_UARTDBG_MIS_PEMIS 8 | ||
| 396 | #define BM_UARTDBG_MIS_PEMIS 0x100 | ||
| 397 | #define BF_UARTDBG_MIS_PEMIS(v) (((v) << 8) & 0x100) | ||
| 398 | #define BP_UARTDBG_MIS_FEMIS 7 | ||
| 399 | #define BM_UARTDBG_MIS_FEMIS 0x80 | ||
| 400 | #define BF_UARTDBG_MIS_FEMIS(v) (((v) << 7) & 0x80) | ||
| 401 | #define BP_UARTDBG_MIS_RTMIS 6 | ||
| 402 | #define BM_UARTDBG_MIS_RTMIS 0x40 | ||
| 403 | #define BF_UARTDBG_MIS_RTMIS(v) (((v) << 6) & 0x40) | ||
| 404 | #define BP_UARTDBG_MIS_TXMIS 5 | ||
| 405 | #define BM_UARTDBG_MIS_TXMIS 0x20 | ||
| 406 | #define BF_UARTDBG_MIS_TXMIS(v) (((v) << 5) & 0x20) | ||
| 407 | #define BP_UARTDBG_MIS_RXMIS 4 | ||
| 408 | #define BM_UARTDBG_MIS_RXMIS 0x10 | ||
| 409 | #define BF_UARTDBG_MIS_RXMIS(v) (((v) << 4) & 0x10) | ||
| 410 | #define BP_UARTDBG_MIS_DSRMMIS 3 | ||
| 411 | #define BM_UARTDBG_MIS_DSRMMIS 0x8 | ||
| 412 | #define BF_UARTDBG_MIS_DSRMMIS(v) (((v) << 3) & 0x8) | ||
| 413 | #define BP_UARTDBG_MIS_DCDMMIS 2 | ||
| 414 | #define BM_UARTDBG_MIS_DCDMMIS 0x4 | ||
| 415 | #define BF_UARTDBG_MIS_DCDMMIS(v) (((v) << 2) & 0x4) | ||
| 416 | #define BP_UARTDBG_MIS_CTSMMIS 1 | ||
| 417 | #define BM_UARTDBG_MIS_CTSMMIS 0x2 | ||
| 418 | #define BF_UARTDBG_MIS_CTSMMIS(v) (((v) << 1) & 0x2) | ||
| 419 | #define BP_UARTDBG_MIS_RIMMIS 0 | ||
| 420 | #define BM_UARTDBG_MIS_RIMMIS 0x1 | ||
| 421 | #define BF_UARTDBG_MIS_RIMMIS(v) (((v) << 0) & 0x1) | ||
| 422 | |||
| 423 | /** | ||
| 424 | * Register: HW_UARTDBG_ICR | ||
| 425 | * Address: 0x44 | ||
| 426 | * SCT: no | ||
| 427 | */ | ||
| 428 | #define HW_UARTDBG_ICR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x44)) | ||
| 429 | #define BP_UARTDBG_ICR_UNAVAILABLE 16 | ||
| 430 | #define BM_UARTDBG_ICR_UNAVAILABLE 0xffff0000 | ||
| 431 | #define BF_UARTDBG_ICR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 432 | #define BP_UARTDBG_ICR_RESERVED 11 | ||
| 433 | #define BM_UARTDBG_ICR_RESERVED 0xf800 | ||
| 434 | #define BF_UARTDBG_ICR_RESERVED(v) (((v) << 11) & 0xf800) | ||
| 435 | #define BP_UARTDBG_ICR_OEIC 10 | ||
| 436 | #define BM_UARTDBG_ICR_OEIC 0x400 | ||
| 437 | #define BF_UARTDBG_ICR_OEIC(v) (((v) << 10) & 0x400) | ||
| 438 | #define BP_UARTDBG_ICR_BEIC 9 | ||
| 439 | #define BM_UARTDBG_ICR_BEIC 0x200 | ||
| 440 | #define BF_UARTDBG_ICR_BEIC(v) (((v) << 9) & 0x200) | ||
| 441 | #define BP_UARTDBG_ICR_PEIC 8 | ||
| 442 | #define BM_UARTDBG_ICR_PEIC 0x100 | ||
| 443 | #define BF_UARTDBG_ICR_PEIC(v) (((v) << 8) & 0x100) | ||
| 444 | #define BP_UARTDBG_ICR_FEIC 7 | ||
| 445 | #define BM_UARTDBG_ICR_FEIC 0x80 | ||
| 446 | #define BF_UARTDBG_ICR_FEIC(v) (((v) << 7) & 0x80) | ||
| 447 | #define BP_UARTDBG_ICR_RTIC 6 | ||
| 448 | #define BM_UARTDBG_ICR_RTIC 0x40 | ||
| 449 | #define BF_UARTDBG_ICR_RTIC(v) (((v) << 6) & 0x40) | ||
| 450 | #define BP_UARTDBG_ICR_TXIC 5 | ||
| 451 | #define BM_UARTDBG_ICR_TXIC 0x20 | ||
| 452 | #define BF_UARTDBG_ICR_TXIC(v) (((v) << 5) & 0x20) | ||
| 453 | #define BP_UARTDBG_ICR_RXIC 4 | ||
| 454 | #define BM_UARTDBG_ICR_RXIC 0x10 | ||
| 455 | #define BF_UARTDBG_ICR_RXIC(v) (((v) << 4) & 0x10) | ||
| 456 | #define BP_UARTDBG_ICR_DSRMIC 3 | ||
| 457 | #define BM_UARTDBG_ICR_DSRMIC 0x8 | ||
| 458 | #define BF_UARTDBG_ICR_DSRMIC(v) (((v) << 3) & 0x8) | ||
| 459 | #define BP_UARTDBG_ICR_DCDMIC 2 | ||
| 460 | #define BM_UARTDBG_ICR_DCDMIC 0x4 | ||
| 461 | #define BF_UARTDBG_ICR_DCDMIC(v) (((v) << 2) & 0x4) | ||
| 462 | #define BP_UARTDBG_ICR_CTSMIC 1 | ||
| 463 | #define BM_UARTDBG_ICR_CTSMIC 0x2 | ||
| 464 | #define BF_UARTDBG_ICR_CTSMIC(v) (((v) << 1) & 0x2) | ||
| 465 | #define BP_UARTDBG_ICR_RIMIC 0 | ||
| 466 | #define BM_UARTDBG_ICR_RIMIC 0x1 | ||
| 467 | #define BF_UARTDBG_ICR_RIMIC(v) (((v) << 0) & 0x1) | ||
| 468 | |||
| 469 | /** | ||
| 470 | * Register: HW_UARTDBG_DMACR | ||
| 471 | * Address: 0x48 | ||
| 472 | * SCT: no | ||
| 473 | */ | ||
| 474 | #define HW_UARTDBG_DMACR (*(volatile unsigned long *)(REGS_UARTDBG_BASE + 0x48)) | ||
| 475 | #define BP_UARTDBG_DMACR_UNAVAILABLE 16 | ||
| 476 | #define BM_UARTDBG_DMACR_UNAVAILABLE 0xffff0000 | ||
| 477 | #define BF_UARTDBG_DMACR_UNAVAILABLE(v) (((v) << 16) & 0xffff0000) | ||
| 478 | #define BP_UARTDBG_DMACR_RESERVED 3 | ||
| 479 | #define BM_UARTDBG_DMACR_RESERVED 0xfff8 | ||
| 480 | #define BF_UARTDBG_DMACR_RESERVED(v) (((v) << 3) & 0xfff8) | ||
| 481 | #define BP_UARTDBG_DMACR_DMAONERR 2 | ||
| 482 | #define BM_UARTDBG_DMACR_DMAONERR 0x4 | ||
| 483 | #define BF_UARTDBG_DMACR_DMAONERR(v) (((v) << 2) & 0x4) | ||
| 484 | #define BP_UARTDBG_DMACR_TXDMAE 1 | ||
| 485 | #define BM_UARTDBG_DMACR_TXDMAE 0x2 | ||
| 486 | #define BF_UARTDBG_DMACR_TXDMAE(v) (((v) << 1) & 0x2) | ||
| 487 | #define BP_UARTDBG_DMACR_RXDMAE 0 | ||
| 488 | #define BM_UARTDBG_DMACR_RXDMAE 0x1 | ||
| 489 | #define BF_UARTDBG_DMACR_RXDMAE(v) (((v) << 0) & 0x1) | ||
| 490 | |||
| 491 | #endif /* __HEADERGEN__STMP3700__UARTDBG__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h new file mode 100644 index 0000000000..d621bac1e9 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-usbctrl.h | |||
| @@ -0,0 +1,877 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__USBCTRL__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__USBCTRL__H__ | ||
| 25 | |||
| 26 | #define REGS_USBCTRL_BASE (0x80080000) | ||
| 27 | |||
| 28 | #define REGS_USBCTRL_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_USBCTRL_ID | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: no | ||
| 34 | */ | ||
| 35 | #define HW_USBCTRL_ID (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x0)) | ||
| 36 | #define BP_USBCTRL_ID_REV 16 | ||
| 37 | #define BM_USBCTRL_ID_REV 0xff0000 | ||
| 38 | #define BF_USBCTRL_ID_REV(v) (((v) << 16) & 0xff0000) | ||
| 39 | #define BP_USBCTRL_ID_ID_N 8 | ||
| 40 | #define BM_USBCTRL_ID_ID_N 0xff00 | ||
| 41 | #define BF_USBCTRL_ID_ID_N(v) (((v) << 8) & 0xff00) | ||
| 42 | #define BP_USBCTRL_ID_ID 0 | ||
| 43 | #define BM_USBCTRL_ID_ID 0xff | ||
| 44 | #define BF_USBCTRL_ID_ID(v) (((v) << 0) & 0xff) | ||
| 45 | |||
| 46 | /** | ||
| 47 | * Register: HW_USBCTRL_GENERAL | ||
| 48 | * Address: 0x4 | ||
| 49 | * SCT: no | ||
| 50 | */ | ||
| 51 | #define HW_USBCTRL_GENERAL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x4)) | ||
| 52 | #define BP_USBCTRL_GENERAL_SM 9 | ||
| 53 | #define BM_USBCTRL_GENERAL_SM 0x200 | ||
| 54 | #define BF_USBCTRL_GENERAL_SM(v) (((v) << 9) & 0x200) | ||
| 55 | #define BP_USBCTRL_GENERAL_PHYM 6 | ||
| 56 | #define BM_USBCTRL_GENERAL_PHYM 0x1c0 | ||
| 57 | #define BF_USBCTRL_GENERAL_PHYM(v) (((v) << 6) & 0x1c0) | ||
| 58 | #define BP_USBCTRL_GENERAL_PHYW 4 | ||
| 59 | #define BM_USBCTRL_GENERAL_PHYW 0x30 | ||
| 60 | #define BF_USBCTRL_GENERAL_PHYW(v) (((v) << 4) & 0x30) | ||
| 61 | #define BP_USBCTRL_GENERAL_BWT 3 | ||
| 62 | #define BM_USBCTRL_GENERAL_BWT 0x8 | ||
| 63 | #define BF_USBCTRL_GENERAL_BWT(v) (((v) << 3) & 0x8) | ||
| 64 | #define BP_USBCTRL_GENERAL_CLKC 1 | ||
| 65 | #define BM_USBCTRL_GENERAL_CLKC 0x6 | ||
| 66 | #define BF_USBCTRL_GENERAL_CLKC(v) (((v) << 1) & 0x6) | ||
| 67 | #define BP_USBCTRL_GENERAL_RT 0 | ||
| 68 | #define BM_USBCTRL_GENERAL_RT 0x1 | ||
| 69 | #define BF_USBCTRL_GENERAL_RT(v) (((v) << 0) & 0x1) | ||
| 70 | |||
| 71 | /** | ||
| 72 | * Register: HW_USBCTRL_HOST | ||
| 73 | * Address: 0x8 | ||
| 74 | * SCT: no | ||
| 75 | */ | ||
| 76 | #define HW_USBCTRL_HOST (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x8)) | ||
| 77 | #define BP_USBCTRL_HOST_TTPER 24 | ||
| 78 | #define BM_USBCTRL_HOST_TTPER 0xff000000 | ||
| 79 | #define BF_USBCTRL_HOST_TTPER(v) (((v) << 24) & 0xff000000) | ||
| 80 | #define BP_USBCTRL_HOST_TTASY 16 | ||
| 81 | #define BM_USBCTRL_HOST_TTASY 0xff0000 | ||
| 82 | #define BF_USBCTRL_HOST_TTASY(v) (((v) << 16) & 0xff0000) | ||
| 83 | #define BP_USBCTRL_HOST_NPORT 1 | ||
| 84 | #define BM_USBCTRL_HOST_NPORT 0xe | ||
| 85 | #define BF_USBCTRL_HOST_NPORT(v) (((v) << 1) & 0xe) | ||
| 86 | #define BP_USBCTRL_HOST_HC 0 | ||
| 87 | #define BM_USBCTRL_HOST_HC 0x1 | ||
| 88 | #define BF_USBCTRL_HOST_HC(v) (((v) << 0) & 0x1) | ||
| 89 | |||
| 90 | /** | ||
| 91 | * Register: HW_USBCTRL_DEVICE | ||
| 92 | * Address: 0xc | ||
| 93 | * SCT: no | ||
| 94 | */ | ||
| 95 | #define HW_USBCTRL_DEVICE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0xc)) | ||
| 96 | #define BP_USBCTRL_DEVICE_DEVEP 1 | ||
| 97 | #define BM_USBCTRL_DEVICE_DEVEP 0x3e | ||
| 98 | #define BF_USBCTRL_DEVICE_DEVEP(v) (((v) << 1) & 0x3e) | ||
| 99 | #define BP_USBCTRL_DEVICE_DC 0 | ||
| 100 | #define BM_USBCTRL_DEVICE_DC 0x1 | ||
| 101 | #define BF_USBCTRL_DEVICE_DC(v) (((v) << 0) & 0x1) | ||
| 102 | |||
| 103 | /** | ||
| 104 | * Register: HW_USBCTRL_TXBUF | ||
| 105 | * Address: 0x10 | ||
| 106 | * SCT: no | ||
| 107 | */ | ||
| 108 | #define HW_USBCTRL_TXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x10)) | ||
| 109 | #define BP_USBCTRL_TXBUF_TXLCR 31 | ||
| 110 | #define BM_USBCTRL_TXBUF_TXLCR 0x80000000 | ||
| 111 | #define BF_USBCTRL_TXBUF_TXLCR(v) (((v) << 31) & 0x80000000) | ||
| 112 | #define BP_USBCTRL_TXBUF_TXCHANADD 16 | ||
| 113 | #define BM_USBCTRL_TXBUF_TXCHANADD 0xff0000 | ||
| 114 | #define BF_USBCTRL_TXBUF_TXCHANADD(v) (((v) << 16) & 0xff0000) | ||
| 115 | #define BP_USBCTRL_TXBUF_TXADD 8 | ||
| 116 | #define BM_USBCTRL_TXBUF_TXADD 0xff00 | ||
| 117 | #define BF_USBCTRL_TXBUF_TXADD(v) (((v) << 8) & 0xff00) | ||
| 118 | #define BP_USBCTRL_TXBUF_TXBURST 0 | ||
| 119 | #define BM_USBCTRL_TXBUF_TXBURST 0xff | ||
| 120 | #define BF_USBCTRL_TXBUF_TXBURST(v) (((v) << 0) & 0xff) | ||
| 121 | |||
| 122 | /** | ||
| 123 | * Register: HW_USBCTRL_RXBUF | ||
| 124 | * Address: 0x14 | ||
| 125 | * SCT: no | ||
| 126 | */ | ||
| 127 | #define HW_USBCTRL_RXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14)) | ||
| 128 | #define BP_USBCTRL_RXBUF_RXADD 8 | ||
| 129 | #define BM_USBCTRL_RXBUF_RXADD 0xff00 | ||
| 130 | #define BF_USBCTRL_RXBUF_RXADD(v) (((v) << 8) & 0xff00) | ||
| 131 | #define BP_USBCTRL_RXBUF_RXBURST 0 | ||
| 132 | #define BM_USBCTRL_RXBUF_RXBURST 0xff | ||
| 133 | #define BF_USBCTRL_RXBUF_RXBURST(v) (((v) << 0) & 0xff) | ||
| 134 | |||
| 135 | /** | ||
| 136 | * Register: HW_USBCTRL_TTTXBUF | ||
| 137 | * Address: 0x18 | ||
| 138 | * SCT: no | ||
| 139 | */ | ||
| 140 | #define HW_USBCTRL_TTTXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x18)) | ||
| 141 | #define BP_USBCTRL_TTTXBUF_TTTXBUF 0 | ||
| 142 | #define BM_USBCTRL_TTTXBUF_TTTXBUF 0xffffffff | ||
| 143 | #define BF_USBCTRL_TTTXBUF_TTTXBUF(v) (((v) << 0) & 0xffffffff) | ||
| 144 | |||
| 145 | /** | ||
| 146 | * Register: HW_USBCTRL_TTRXBUF | ||
| 147 | * Address: 0x1c | ||
| 148 | * SCT: no | ||
| 149 | */ | ||
| 150 | #define HW_USBCTRL_TTRXBUF (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c)) | ||
| 151 | #define BP_USBCTRL_TTRXBUF_TTRXBUF 0 | ||
| 152 | #define BM_USBCTRL_TTRXBUF_TTRXBUF 0xffffffff | ||
| 153 | #define BF_USBCTRL_TTRXBUF_TTRXBUF(v) (((v) << 0) & 0xffffffff) | ||
| 154 | |||
| 155 | /** | ||
| 156 | * Register: HW_USBCTRL_CAPLENGTH | ||
| 157 | * Address: 0x100 | ||
| 158 | * SCT: no | ||
| 159 | */ | ||
| 160 | #define HW_USBCTRL_CAPLENGTH (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x100)) | ||
| 161 | #define BP_USBCTRL_CAPLENGTH_HCIVER 16 | ||
| 162 | #define BM_USBCTRL_CAPLENGTH_HCIVER 0xffff0000 | ||
| 163 | #define BF_USBCTRL_CAPLENGTH_HCIVER(v) (((v) << 16) & 0xffff0000) | ||
| 164 | #define BP_USBCTRL_CAPLENGTH_LENGTH 0 | ||
| 165 | #define BM_USBCTRL_CAPLENGTH_LENGTH 0xff | ||
| 166 | #define BF_USBCTRL_CAPLENGTH_LENGTH(v) (((v) << 0) & 0xff) | ||
| 167 | |||
| 168 | /** | ||
| 169 | * Register: HW_USBCTRL_HCSPARAMS | ||
| 170 | * Address: 0x104 | ||
| 171 | * SCT: no | ||
| 172 | */ | ||
| 173 | #define HW_USBCTRL_HCSPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x104)) | ||
| 174 | #define BP_USBCTRL_HCSPARAMS_NPORTS 0 | ||
| 175 | #define BM_USBCTRL_HCSPARAMS_NPORTS 0xf | ||
| 176 | #define BF_USBCTRL_HCSPARAMS_NPORTS(v) (((v) << 0) & 0xf) | ||
| 177 | #define BP_USBCTRL_HCSPARAMS_PPC 4 | ||
| 178 | #define BM_USBCTRL_HCSPARAMS_PPC 0x10 | ||
| 179 | #define BF_USBCTRL_HCSPARAMS_PPC(v) (((v) << 4) & 0x10) | ||
| 180 | #define BP_USBCTRL_HCSPARAMS_NPCC 8 | ||
| 181 | #define BM_USBCTRL_HCSPARAMS_NPCC 0xf00 | ||
| 182 | #define BF_USBCTRL_HCSPARAMS_NPCC(v) (((v) << 8) & 0xf00) | ||
| 183 | #define BP_USBCTRL_HCSPARAMS_NCC 12 | ||
| 184 | #define BM_USBCTRL_HCSPARAMS_NCC 0xf000 | ||
| 185 | #define BF_USBCTRL_HCSPARAMS_NCC(v) (((v) << 12) & 0xf000) | ||
| 186 | #define BP_USBCTRL_HCSPARAMS_PI 16 | ||
| 187 | #define BM_USBCTRL_HCSPARAMS_PI 0x10000 | ||
| 188 | #define BF_USBCTRL_HCSPARAMS_PI(v) (((v) << 16) & 0x10000) | ||
| 189 | #define BP_USBCTRL_HCSPARAMS_NPTT 20 | ||
| 190 | #define BM_USBCTRL_HCSPARAMS_NPTT 0xf00000 | ||
| 191 | #define BF_USBCTRL_HCSPARAMS_NPTT(v) (((v) << 20) & 0xf00000) | ||
| 192 | #define BP_USBCTRL_HCSPARAMS_NTT 24 | ||
| 193 | #define BM_USBCTRL_HCSPARAMS_NTT 0xf000000 | ||
| 194 | #define BF_USBCTRL_HCSPARAMS_NTT(v) (((v) << 24) & 0xf000000) | ||
| 195 | |||
| 196 | /** | ||
| 197 | * Register: HW_USBCTRL_HCCPARAMS | ||
| 198 | * Address: 0x108 | ||
| 199 | * SCT: no | ||
| 200 | */ | ||
| 201 | #define HW_USBCTRL_HCCPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x108)) | ||
| 202 | #define BP_USBCTRL_HCCPARAMS_ADDR64BITCAP 0 | ||
| 203 | #define BM_USBCTRL_HCCPARAMS_ADDR64BITCAP 0x1 | ||
| 204 | #define BF_USBCTRL_HCCPARAMS_ADDR64BITCAP(v) (((v) << 0) & 0x1) | ||
| 205 | #define BP_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG 1 | ||
| 206 | #define BM_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG 0x2 | ||
| 207 | #define BF_USBCTRL_HCCPARAMS_PGM_FRM_LIST_FLAG(v) (((v) << 1) & 0x2) | ||
| 208 | #define BP_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP 2 | ||
| 209 | #define BM_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP 0x4 | ||
| 210 | #define BF_USBCTRL_HCCPARAMS_ASYNC_PARK_CAP(v) (((v) << 2) & 0x4) | ||
| 211 | #define BP_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD 8 | ||
| 212 | #define BM_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD 0xff00 | ||
| 213 | #define BF_USBCTRL_HCCPARAMS_ISO_SCH_THRESHOLD(v) (((v) << 8) & 0xff00) | ||
| 214 | |||
| 215 | /** | ||
| 216 | * Register: HW_USBCTRL_DCIVERSION | ||
| 217 | * Address: 0x120 | ||
| 218 | * SCT: no | ||
| 219 | */ | ||
| 220 | #define HW_USBCTRL_DCIVERSION (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x120)) | ||
| 221 | #define BP_USBCTRL_DCIVERSION_DCIVER 0 | ||
| 222 | #define BM_USBCTRL_DCIVERSION_DCIVER 0xffff | ||
| 223 | #define BF_USBCTRL_DCIVERSION_DCIVER(v) (((v) << 0) & 0xffff) | ||
| 224 | |||
| 225 | /** | ||
| 226 | * Register: HW_USBCTRL_DCCPARAMS | ||
| 227 | * Address: 0x124 | ||
| 228 | * SCT: no | ||
| 229 | */ | ||
| 230 | #define HW_USBCTRL_DCCPARAMS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x124)) | ||
| 231 | #define BP_USBCTRL_DCCPARAMS_HC 8 | ||
| 232 | #define BM_USBCTRL_DCCPARAMS_HC 0x100 | ||
| 233 | #define BF_USBCTRL_DCCPARAMS_HC(v) (((v) << 8) & 0x100) | ||
| 234 | #define BP_USBCTRL_DCCPARAMS_DC 7 | ||
| 235 | #define BM_USBCTRL_DCCPARAMS_DC 0x80 | ||
| 236 | #define BF_USBCTRL_DCCPARAMS_DC(v) (((v) << 7) & 0x80) | ||
| 237 | #define BP_USBCTRL_DCCPARAMS_DEN 0 | ||
| 238 | #define BM_USBCTRL_DCCPARAMS_DEN 0x1f | ||
| 239 | #define BF_USBCTRL_DCCPARAMS_DEN(v) (((v) << 0) & 0x1f) | ||
| 240 | |||
| 241 | /** | ||
| 242 | * Register: HW_USBCTRL_USBCMD | ||
| 243 | * Address: 0x140 | ||
| 244 | * SCT: no | ||
| 245 | */ | ||
| 246 | #define HW_USBCTRL_USBCMD (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x140)) | ||
| 247 | #define BP_USBCTRL_USBCMD_RS 0 | ||
| 248 | #define BM_USBCTRL_USBCMD_RS 0x1 | ||
| 249 | #define BF_USBCTRL_USBCMD_RS(v) (((v) << 0) & 0x1) | ||
| 250 | #define BP_USBCTRL_USBCMD_RST 1 | ||
| 251 | #define BM_USBCTRL_USBCMD_RST 0x2 | ||
| 252 | #define BF_USBCTRL_USBCMD_RST(v) (((v) << 1) & 0x2) | ||
| 253 | #define BP_USBCTRL_USBCMD_FS0 2 | ||
| 254 | #define BM_USBCTRL_USBCMD_FS0 0x4 | ||
| 255 | #define BF_USBCTRL_USBCMD_FS0(v) (((v) << 2) & 0x4) | ||
| 256 | #define BP_USBCTRL_USBCMD_FS1 3 | ||
| 257 | #define BM_USBCTRL_USBCMD_FS1 0x8 | ||
| 258 | #define BF_USBCTRL_USBCMD_FS1(v) (((v) << 3) & 0x8) | ||
| 259 | #define BP_USBCTRL_USBCMD_PSE 4 | ||
| 260 | #define BM_USBCTRL_USBCMD_PSE 0x10 | ||
| 261 | #define BF_USBCTRL_USBCMD_PSE(v) (((v) << 4) & 0x10) | ||
| 262 | #define BP_USBCTRL_USBCMD_ASE 5 | ||
| 263 | #define BM_USBCTRL_USBCMD_ASE 0x20 | ||
| 264 | #define BF_USBCTRL_USBCMD_ASE(v) (((v) << 5) & 0x20) | ||
| 265 | #define BP_USBCTRL_USBCMD_IAA 6 | ||
| 266 | #define BM_USBCTRL_USBCMD_IAA 0x40 | ||
| 267 | #define BF_USBCTRL_USBCMD_IAA(v) (((v) << 6) & 0x40) | ||
| 268 | #define BP_USBCTRL_USBCMD_LR 7 | ||
| 269 | #define BM_USBCTRL_USBCMD_LR 0x80 | ||
| 270 | #define BF_USBCTRL_USBCMD_LR(v) (((v) << 7) & 0x80) | ||
| 271 | #define BP_USBCTRL_USBCMD_ASP0 8 | ||
| 272 | #define BM_USBCTRL_USBCMD_ASP0 0x100 | ||
| 273 | #define BF_USBCTRL_USBCMD_ASP0(v) (((v) << 8) & 0x100) | ||
| 274 | #define BP_USBCTRL_USBCMD_ASP1 9 | ||
| 275 | #define BM_USBCTRL_USBCMD_ASP1 0x200 | ||
| 276 | #define BF_USBCTRL_USBCMD_ASP1(v) (((v) << 9) & 0x200) | ||
| 277 | #define BP_USBCTRL_USBCMD_ASPE 11 | ||
| 278 | #define BM_USBCTRL_USBCMD_ASPE 0x800 | ||
| 279 | #define BF_USBCTRL_USBCMD_ASPE(v) (((v) << 11) & 0x800) | ||
| 280 | #define BP_USBCTRL_USBCMD_FS2 15 | ||
| 281 | #define BM_USBCTRL_USBCMD_FS2 0x8000 | ||
| 282 | #define BF_USBCTRL_USBCMD_FS2(v) (((v) << 15) & 0x8000) | ||
| 283 | #define BP_USBCTRL_USBCMD_ITC 16 | ||
| 284 | #define BM_USBCTRL_USBCMD_ITC 0xff0000 | ||
| 285 | #define BF_USBCTRL_USBCMD_ITC(v) (((v) << 16) & 0xff0000) | ||
| 286 | |||
| 287 | /** | ||
| 288 | * Register: HW_USBCTRL_USBSTS | ||
| 289 | * Address: 0x144 | ||
| 290 | * SCT: no | ||
| 291 | */ | ||
| 292 | #define HW_USBCTRL_USBSTS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x144)) | ||
| 293 | #define BP_USBCTRL_USBSTS_UI 0 | ||
| 294 | #define BM_USBCTRL_USBSTS_UI 0x1 | ||
| 295 | #define BF_USBCTRL_USBSTS_UI(v) (((v) << 0) & 0x1) | ||
| 296 | #define BP_USBCTRL_USBSTS_UEI 1 | ||
| 297 | #define BM_USBCTRL_USBSTS_UEI 0x2 | ||
| 298 | #define BF_USBCTRL_USBSTS_UEI(v) (((v) << 1) & 0x2) | ||
| 299 | #define BP_USBCTRL_USBSTS_PCI 2 | ||
| 300 | #define BM_USBCTRL_USBSTS_PCI 0x4 | ||
| 301 | #define BF_USBCTRL_USBSTS_PCI(v) (((v) << 2) & 0x4) | ||
| 302 | #define BP_USBCTRL_USBSTS_FRI 3 | ||
| 303 | #define BM_USBCTRL_USBSTS_FRI 0x8 | ||
| 304 | #define BF_USBCTRL_USBSTS_FRI(v) (((v) << 3) & 0x8) | ||
| 305 | #define BP_USBCTRL_USBSTS_SEI 4 | ||
| 306 | #define BM_USBCTRL_USBSTS_SEI 0x10 | ||
| 307 | #define BF_USBCTRL_USBSTS_SEI(v) (((v) << 4) & 0x10) | ||
| 308 | #define BP_USBCTRL_USBSTS_AAI 5 | ||
| 309 | #define BM_USBCTRL_USBSTS_AAI 0x20 | ||
| 310 | #define BF_USBCTRL_USBSTS_AAI(v) (((v) << 5) & 0x20) | ||
| 311 | #define BP_USBCTRL_USBSTS_URI 6 | ||
| 312 | #define BM_USBCTRL_USBSTS_URI 0x40 | ||
| 313 | #define BF_USBCTRL_USBSTS_URI(v) (((v) << 6) & 0x40) | ||
| 314 | #define BP_USBCTRL_USBSTS_SRI 7 | ||
| 315 | #define BM_USBCTRL_USBSTS_SRI 0x80 | ||
| 316 | #define BF_USBCTRL_USBSTS_SRI(v) (((v) << 7) & 0x80) | ||
| 317 | #define BP_USBCTRL_USBSTS_SLI 8 | ||
| 318 | #define BM_USBCTRL_USBSTS_SLI 0x100 | ||
| 319 | #define BF_USBCTRL_USBSTS_SLI(v) (((v) << 8) & 0x100) | ||
| 320 | #define BP_USBCTRL_USBSTS_ULPII 10 | ||
| 321 | #define BM_USBCTRL_USBSTS_ULPII 0x400 | ||
| 322 | #define BF_USBCTRL_USBSTS_ULPII(v) (((v) << 10) & 0x400) | ||
| 323 | #define BP_USBCTRL_USBSTS_HCH 12 | ||
| 324 | #define BM_USBCTRL_USBSTS_HCH 0x1000 | ||
| 325 | #define BF_USBCTRL_USBSTS_HCH(v) (((v) << 12) & 0x1000) | ||
| 326 | #define BP_USBCTRL_USBSTS_RCL 13 | ||
| 327 | #define BM_USBCTRL_USBSTS_RCL 0x2000 | ||
| 328 | #define BF_USBCTRL_USBSTS_RCL(v) (((v) << 13) & 0x2000) | ||
| 329 | #define BP_USBCTRL_USBSTS_PS 14 | ||
| 330 | #define BM_USBCTRL_USBSTS_PS 0x4000 | ||
| 331 | #define BF_USBCTRL_USBSTS_PS(v) (((v) << 14) & 0x4000) | ||
| 332 | #define BP_USBCTRL_USBSTS_AS 15 | ||
| 333 | #define BM_USBCTRL_USBSTS_AS 0x8000 | ||
| 334 | #define BF_USBCTRL_USBSTS_AS(v) (((v) << 15) & 0x8000) | ||
| 335 | #define BP_USBCTRL_USBSTS_NAKI 16 | ||
| 336 | #define BM_USBCTRL_USBSTS_NAKI 0x10000 | ||
| 337 | #define BF_USBCTRL_USBSTS_NAKI(v) (((v) << 16) & 0x10000) | ||
| 338 | |||
| 339 | /** | ||
| 340 | * Register: HW_USBCTRL_USBINTR | ||
| 341 | * Address: 0x148 | ||
| 342 | * SCT: no | ||
| 343 | */ | ||
| 344 | #define HW_USBCTRL_USBINTR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x148)) | ||
| 345 | #define BP_USBCTRL_USBINTR_UE 0 | ||
| 346 | #define BM_USBCTRL_USBINTR_UE 0x1 | ||
| 347 | #define BF_USBCTRL_USBINTR_UE(v) (((v) << 0) & 0x1) | ||
| 348 | #define BP_USBCTRL_USBINTR_UEE 1 | ||
| 349 | #define BM_USBCTRL_USBINTR_UEE 0x2 | ||
| 350 | #define BF_USBCTRL_USBINTR_UEE(v) (((v) << 1) & 0x2) | ||
| 351 | #define BP_USBCTRL_USBINTR_PCE 2 | ||
| 352 | #define BM_USBCTRL_USBINTR_PCE 0x4 | ||
| 353 | #define BF_USBCTRL_USBINTR_PCE(v) (((v) << 2) & 0x4) | ||
| 354 | #define BP_USBCTRL_USBINTR_FRE 3 | ||
| 355 | #define BM_USBCTRL_USBINTR_FRE 0x8 | ||
| 356 | #define BF_USBCTRL_USBINTR_FRE(v) (((v) << 3) & 0x8) | ||
| 357 | #define BP_USBCTRL_USBINTR_SEE 4 | ||
| 358 | #define BM_USBCTRL_USBINTR_SEE 0x10 | ||
| 359 | #define BF_USBCTRL_USBINTR_SEE(v) (((v) << 4) & 0x10) | ||
| 360 | #define BP_USBCTRL_USBINTR_AAE 5 | ||
| 361 | #define BM_USBCTRL_USBINTR_AAE 0x20 | ||
| 362 | #define BF_USBCTRL_USBINTR_AAE(v) (((v) << 5) & 0x20) | ||
| 363 | #define BP_USBCTRL_USBINTR_URE 6 | ||
| 364 | #define BM_USBCTRL_USBINTR_URE 0x40 | ||
| 365 | #define BF_USBCTRL_USBINTR_URE(v) (((v) << 6) & 0x40) | ||
| 366 | #define BP_USBCTRL_USBINTR_SRE 7 | ||
| 367 | #define BM_USBCTRL_USBINTR_SRE 0x80 | ||
| 368 | #define BF_USBCTRL_USBINTR_SRE(v) (((v) << 7) & 0x80) | ||
| 369 | #define BP_USBCTRL_USBINTR_SLE 8 | ||
| 370 | #define BM_USBCTRL_USBINTR_SLE 0x100 | ||
| 371 | #define BF_USBCTRL_USBINTR_SLE(v) (((v) << 8) & 0x100) | ||
| 372 | #define BP_USBCTRL_USBINTR_ULPIE 10 | ||
| 373 | #define BM_USBCTRL_USBINTR_ULPIE 0x400 | ||
| 374 | #define BF_USBCTRL_USBINTR_ULPIE(v) (((v) << 10) & 0x400) | ||
| 375 | #define BP_USBCTRL_USBINTR_NAKE 16 | ||
| 376 | #define BM_USBCTRL_USBINTR_NAKE 0x10000 | ||
| 377 | #define BF_USBCTRL_USBINTR_NAKE(v) (((v) << 16) & 0x10000) | ||
| 378 | |||
| 379 | /** | ||
| 380 | * Register: HW_USBCTRL_FRINDEX | ||
| 381 | * Address: 0x14c | ||
| 382 | * SCT: no | ||
| 383 | */ | ||
| 384 | #define HW_USBCTRL_FRINDEX (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x14c)) | ||
| 385 | #define BP_USBCTRL_FRINDEX_LISTINDEX 3 | ||
| 386 | #define BM_USBCTRL_FRINDEX_LISTINDEX 0x3ff8 | ||
| 387 | #define BF_USBCTRL_FRINDEX_LISTINDEX(v) (((v) << 3) & 0x3ff8) | ||
| 388 | #define BP_USBCTRL_FRINDEX_UINDEX 0 | ||
| 389 | #define BM_USBCTRL_FRINDEX_UINDEX 0x7 | ||
| 390 | #define BF_USBCTRL_FRINDEX_UINDEX(v) (((v) << 0) & 0x7) | ||
| 391 | |||
| 392 | /** | ||
| 393 | * Register: HW_USBCTRL_CTRLDSSEGMENT | ||
| 394 | * Address: 0x150 | ||
| 395 | * SCT: no | ||
| 396 | */ | ||
| 397 | #define HW_USBCTRL_CTRLDSSEGMENT (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x150)) | ||
| 398 | #define BP_USBCTRL_CTRLDSSEGMENT_EMPTY 0 | ||
| 399 | #define BM_USBCTRL_CTRLDSSEGMENT_EMPTY 0xffffffff | ||
| 400 | #define BF_USBCTRL_CTRLDSSEGMENT_EMPTY(v) (((v) << 0) & 0xffffffff) | ||
| 401 | |||
| 402 | /** | ||
| 403 | * Register: HW_USBCTRL_PERIODICLISTBASE | ||
| 404 | * Address: 0x154 | ||
| 405 | * SCT: no | ||
| 406 | */ | ||
| 407 | #define HW_USBCTRL_PERIODICLISTBASE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x154)) | ||
| 408 | #define BP_USBCTRL_PERIODICLISTBASE_BASEADDR 12 | ||
| 409 | #define BM_USBCTRL_PERIODICLISTBASE_BASEADDR 0xfffff000 | ||
| 410 | #define BF_USBCTRL_PERIODICLISTBASE_BASEADDR(v) (((v) << 12) & 0xfffff000) | ||
| 411 | |||
| 412 | /** | ||
| 413 | * Register: HW_USBCTRL_ASYNCLISTADDR | ||
| 414 | * Address: 0x158 | ||
| 415 | * SCT: no | ||
| 416 | */ | ||
| 417 | #define HW_USBCTRL_ASYNCLISTADDR (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x158)) | ||
| 418 | #define BP_USBCTRL_ASYNCLISTADDR_ASYBASE 5 | ||
| 419 | #define BM_USBCTRL_ASYNCLISTADDR_ASYBASE 0xffffffe0 | ||
| 420 | #define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) (((v) << 5) & 0xffffffe0) | ||
| 421 | |||
| 422 | /** | ||
| 423 | * Register: HW_USBCTRL_TTCTRL | ||
| 424 | * Address: 0x15c | ||
| 425 | * SCT: no | ||
| 426 | */ | ||
| 427 | #define HW_USBCTRL_TTCTRL (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x15c)) | ||
| 428 | #define BP_USBCTRL_TTCTRL_TTHA 24 | ||
| 429 | #define BM_USBCTRL_TTCTRL_TTHA 0x7f000000 | ||
| 430 | #define BF_USBCTRL_TTCTRL_TTHA(v) (((v) << 24) & 0x7f000000) | ||
| 431 | |||
| 432 | /** | ||
| 433 | * Register: HW_USBCTRL_BURSTSIZE | ||
| 434 | * Address: 0x160 | ||
| 435 | * SCT: no | ||
| 436 | */ | ||
| 437 | #define HW_USBCTRL_BURSTSIZE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x160)) | ||
| 438 | #define BP_USBCTRL_BURSTSIZE_TX 8 | ||
| 439 | #define BM_USBCTRL_BURSTSIZE_TX 0xff00 | ||
| 440 | #define BF_USBCTRL_BURSTSIZE_TX(v) (((v) << 8) & 0xff00) | ||
| 441 | #define BP_USBCTRL_BURSTSIZE_RX 0 | ||
| 442 | #define BM_USBCTRL_BURSTSIZE_RX 0xff | ||
| 443 | #define BF_USBCTRL_BURSTSIZE_RX(v) (((v) << 0) & 0xff) | ||
| 444 | |||
| 445 | /** | ||
| 446 | * Register: HW_USBCTRL_TXFILLTUNING | ||
| 447 | * Address: 0x164 | ||
| 448 | * SCT: no | ||
| 449 | */ | ||
| 450 | #define HW_USBCTRL_TXFILLTUNING (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x164)) | ||
| 451 | #define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES 16 | ||
| 452 | #define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES 0x3f0000 | ||
| 453 | #define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v) (((v) << 16) & 0x3f0000) | ||
| 454 | #define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH 8 | ||
| 455 | #define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH 0x1f00 | ||
| 456 | #define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v) (((v) << 8) & 0x1f00) | ||
| 457 | #define BP_USBCTRL_TXFILLTUNING_TXSCHOH 0 | ||
| 458 | #define BM_USBCTRL_TXFILLTUNING_TXSCHOH 0xff | ||
| 459 | #define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v) (((v) << 0) & 0xff) | ||
| 460 | |||
| 461 | /** | ||
| 462 | * Register: HW_USBCTRL_TXTTFILLTUNING | ||
| 463 | * Address: 0x168 | ||
| 464 | * SCT: no | ||
| 465 | */ | ||
| 466 | #define HW_USBCTRL_TXTTFILLTUNING (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x168)) | ||
| 467 | #define BP_USBCTRL_TXTTFILLTUNING_EMPTY 0 | ||
| 468 | #define BM_USBCTRL_TXTTFILLTUNING_EMPTY 0xffffffff | ||
| 469 | #define BF_USBCTRL_TXTTFILLTUNING_EMPTY(v) (((v) << 0) & 0xffffffff) | ||
| 470 | |||
| 471 | /** | ||
| 472 | * Register: HW_USBCTRL_ULPI | ||
| 473 | * Address: 0x170 | ||
| 474 | * SCT: no | ||
| 475 | */ | ||
| 476 | #define HW_USBCTRL_ULPI (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x170)) | ||
| 477 | #define BP_USBCTRL_ULPI_WAKEUP 31 | ||
| 478 | #define BM_USBCTRL_ULPI_WAKEUP 0x80000000 | ||
| 479 | #define BF_USBCTRL_ULPI_WAKEUP(v) (((v) << 31) & 0x80000000) | ||
| 480 | #define BP_USBCTRL_ULPI_RUN 30 | ||
| 481 | #define BM_USBCTRL_ULPI_RUN 0x40000000 | ||
| 482 | #define BF_USBCTRL_ULPI_RUN(v) (((v) << 30) & 0x40000000) | ||
| 483 | #define BP_USBCTRL_ULPI_RDWR 29 | ||
| 484 | #define BM_USBCTRL_ULPI_RDWR 0x20000000 | ||
| 485 | #define BF_USBCTRL_ULPI_RDWR(v) (((v) << 29) & 0x20000000) | ||
| 486 | #define BP_USBCTRL_ULPI_ERROR 28 | ||
| 487 | #define BM_USBCTRL_ULPI_ERROR 0x10000000 | ||
| 488 | #define BF_USBCTRL_ULPI_ERROR(v) (((v) << 28) & 0x10000000) | ||
| 489 | #define BP_USBCTRL_ULPI_SYNC 27 | ||
| 490 | #define BM_USBCTRL_ULPI_SYNC 0x8000000 | ||
| 491 | #define BF_USBCTRL_ULPI_SYNC(v) (((v) << 27) & 0x8000000) | ||
| 492 | #define BP_USBCTRL_ULPI_PORT 24 | ||
| 493 | #define BM_USBCTRL_ULPI_PORT 0x7000000 | ||
| 494 | #define BF_USBCTRL_ULPI_PORT(v) (((v) << 24) & 0x7000000) | ||
| 495 | #define BP_USBCTRL_ULPI_ADDR 16 | ||
| 496 | #define BM_USBCTRL_ULPI_ADDR 0xff0000 | ||
| 497 | #define BF_USBCTRL_ULPI_ADDR(v) (((v) << 16) & 0xff0000) | ||
| 498 | #define BP_USBCTRL_ULPI_DATARD 8 | ||
| 499 | #define BM_USBCTRL_ULPI_DATARD 0xff00 | ||
| 500 | #define BF_USBCTRL_ULPI_DATARD(v) (((v) << 8) & 0xff00) | ||
| 501 | #define BP_USBCTRL_ULPI_DATAWR 0 | ||
| 502 | #define BM_USBCTRL_ULPI_DATAWR 0xff | ||
| 503 | #define BF_USBCTRL_ULPI_DATAWR(v) (((v) << 0) & 0xff) | ||
| 504 | |||
| 505 | /** | ||
| 506 | * Register: HW_USBCTRL_VFRAME | ||
| 507 | * Address: 0x174 | ||
| 508 | * SCT: no | ||
| 509 | */ | ||
| 510 | #define HW_USBCTRL_VFRAME (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x174)) | ||
| 511 | #define BP_USBCTRL_VFRAME_EMPTY 0 | ||
| 512 | #define BM_USBCTRL_VFRAME_EMPTY 0xffffffff | ||
| 513 | #define BF_USBCTRL_VFRAME_EMPTY(v) (((v) << 0) & 0xffffffff) | ||
| 514 | |||
| 515 | /** | ||
| 516 | * Register: HW_USBCTRL_EPNAK | ||
| 517 | * Address: 0x178 | ||
| 518 | * SCT: no | ||
| 519 | */ | ||
| 520 | #define HW_USBCTRL_EPNAK (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x178)) | ||
| 521 | #define BP_USBCTRL_EPNAK_EPTN 16 | ||
| 522 | #define BM_USBCTRL_EPNAK_EPTN 0xffff0000 | ||
| 523 | #define BF_USBCTRL_EPNAK_EPTN(v) (((v) << 16) & 0xffff0000) | ||
| 524 | #define BP_USBCTRL_EPNAK_EPRN 0 | ||
| 525 | #define BM_USBCTRL_EPNAK_EPRN 0xffff | ||
| 526 | #define BF_USBCTRL_EPNAK_EPRN(v) (((v) << 0) & 0xffff) | ||
| 527 | |||
| 528 | /** | ||
| 529 | * Register: HW_USBCTRL_EPNAKEN | ||
| 530 | * Address: 0x17c | ||
| 531 | * SCT: no | ||
| 532 | */ | ||
| 533 | #define HW_USBCTRL_EPNAKEN (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x17c)) | ||
| 534 | #define BP_USBCTRL_EPNAKEN_EPTNE 16 | ||
| 535 | #define BM_USBCTRL_EPNAKEN_EPTNE 0xffff0000 | ||
| 536 | #define BF_USBCTRL_EPNAKEN_EPTNE(v) (((v) << 16) & 0xffff0000) | ||
| 537 | #define BP_USBCTRL_EPNAKEN_EPRNE 0 | ||
| 538 | #define BM_USBCTRL_EPNAKEN_EPRNE 0xffff | ||
| 539 | #define BF_USBCTRL_EPNAKEN_EPRNE(v) (((v) << 0) & 0xffff) | ||
| 540 | |||
| 541 | /** | ||
| 542 | * Register: HW_USBCTRL_CONFIGFLAG | ||
| 543 | * Address: 0x180 | ||
| 544 | * SCT: no | ||
| 545 | */ | ||
| 546 | #define HW_USBCTRL_CONFIGFLAG (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x180)) | ||
| 547 | #define BP_USBCTRL_CONFIGFLAG_FLAG 0 | ||
| 548 | #define BM_USBCTRL_CONFIGFLAG_FLAG 0x1 | ||
| 549 | #define BF_USBCTRL_CONFIGFLAG_FLAG(v) (((v) << 0) & 0x1) | ||
| 550 | |||
| 551 | /** | ||
| 552 | * Register: HW_USBCTRL_PORTSC1 | ||
| 553 | * Address: 0x184 | ||
| 554 | * SCT: no | ||
| 555 | */ | ||
| 556 | #define HW_USBCTRL_PORTSC1 (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x184)) | ||
| 557 | #define BP_USBCTRL_PORTSC1_PTS 30 | ||
| 558 | #define BM_USBCTRL_PORTSC1_PTS 0xc0000000 | ||
| 559 | #define BV_USBCTRL_PORTSC1_PTS__UTMI 0x0 | ||
| 560 | #define BV_USBCTRL_PORTSC1_PTS__PHIL 0x1 | ||
| 561 | #define BV_USBCTRL_PORTSC1_PTS__ULPI 0x2 | ||
| 562 | #define BV_USBCTRL_PORTSC1_PTS__SERIAL 0x3 | ||
| 563 | #define BF_USBCTRL_PORTSC1_PTS(v) (((v) << 30) & 0xc0000000) | ||
| 564 | #define BF_USBCTRL_PORTSC1_PTS_V(v) ((BV_USBCTRL_PORTSC1_PTS__##v << 30) & 0xc0000000) | ||
| 565 | #define BP_USBCTRL_PORTSC1_STS 29 | ||
| 566 | #define BM_USBCTRL_PORTSC1_STS 0x20000000 | ||
| 567 | #define BF_USBCTRL_PORTSC1_STS(v) (((v) << 29) & 0x20000000) | ||
| 568 | #define BP_USBCTRL_PORTSC1_PTW 28 | ||
| 569 | #define BM_USBCTRL_PORTSC1_PTW 0x10000000 | ||
| 570 | #define BF_USBCTRL_PORTSC1_PTW(v) (((v) << 28) & 0x10000000) | ||
| 571 | #define BP_USBCTRL_PORTSC1_PSPD 26 | ||
| 572 | #define BM_USBCTRL_PORTSC1_PSPD 0xc000000 | ||
| 573 | #define BV_USBCTRL_PORTSC1_PSPD__FULL 0x0 | ||
| 574 | #define BV_USBCTRL_PORTSC1_PSPD__LO 0x1 | ||
| 575 | #define BV_USBCTRL_PORTSC1_PSPD__HI 0x2 | ||
| 576 | #define BF_USBCTRL_PORTSC1_PSPD(v) (((v) << 26) & 0xc000000) | ||
| 577 | #define BF_USBCTRL_PORTSC1_PSPD_V(v) ((BV_USBCTRL_PORTSC1_PSPD__##v << 26) & 0xc000000) | ||
| 578 | #define BP_USBCTRL_PORTSC1_PFSC 24 | ||
| 579 | #define BM_USBCTRL_PORTSC1_PFSC 0x1000000 | ||
| 580 | #define BF_USBCTRL_PORTSC1_PFSC(v) (((v) << 24) & 0x1000000) | ||
| 581 | #define BP_USBCTRL_PORTSC1_PHCD 23 | ||
| 582 | #define BM_USBCTRL_PORTSC1_PHCD 0x800000 | ||
| 583 | #define BF_USBCTRL_PORTSC1_PHCD(v) (((v) << 23) & 0x800000) | ||
| 584 | #define BP_USBCTRL_PORTSC1_WKOC 22 | ||
| 585 | #define BM_USBCTRL_PORTSC1_WKOC 0x400000 | ||
| 586 | #define BF_USBCTRL_PORTSC1_WKOC(v) (((v) << 22) & 0x400000) | ||
| 587 | #define BP_USBCTRL_PORTSC1_WKDS 21 | ||
| 588 | #define BM_USBCTRL_PORTSC1_WKDS 0x200000 | ||
| 589 | #define BF_USBCTRL_PORTSC1_WKDS(v) (((v) << 21) & 0x200000) | ||
| 590 | #define BP_USBCTRL_PORTSC1_WKCN 20 | ||
| 591 | #define BM_USBCTRL_PORTSC1_WKCN 0x100000 | ||
| 592 | #define BF_USBCTRL_PORTSC1_WKCN(v) (((v) << 20) & 0x100000) | ||
| 593 | #define BP_USBCTRL_PORTSC1_PTC 16 | ||
| 594 | #define BM_USBCTRL_PORTSC1_PTC 0xf0000 | ||
| 595 | #define BV_USBCTRL_PORTSC1_PTC__DISABLE 0x0 | ||
| 596 | #define BV_USBCTRL_PORTSC1_PTC__J 0x1 | ||
| 597 | #define BV_USBCTRL_PORTSC1_PTC__K 0x2 | ||
| 598 | #define BV_USBCTRL_PORTSC1_PTC__SE0orNAK 0x3 | ||
| 599 | #define BV_USBCTRL_PORTSC1_PTC__Packet 0x4 | ||
| 600 | #define BV_USBCTRL_PORTSC1_PTC__ForceEnableHS 0x5 | ||
| 601 | #define BV_USBCTRL_PORTSC1_PTC__ForceEnableFS 0x6 | ||
| 602 | #define BV_USBCTRL_PORTSC1_PTC__ForceEnableLS 0x7 | ||
| 603 | #define BF_USBCTRL_PORTSC1_PTC(v) (((v) << 16) & 0xf0000) | ||
| 604 | #define BF_USBCTRL_PORTSC1_PTC_V(v) ((BV_USBCTRL_PORTSC1_PTC__##v << 16) & 0xf0000) | ||
| 605 | #define BP_USBCTRL_PORTSC1_PIC 14 | ||
| 606 | #define BM_USBCTRL_PORTSC1_PIC 0xc000 | ||
| 607 | #define BV_USBCTRL_PORTSC1_PIC__OFF 0x0 | ||
| 608 | #define BV_USBCTRL_PORTSC1_PIC__AMBER 0x1 | ||
| 609 | #define BV_USBCTRL_PORTSC1_PIC__GREEN 0x2 | ||
| 610 | #define BV_USBCTRL_PORTSC1_PIC__UNDEF 0x3 | ||
| 611 | #define BF_USBCTRL_PORTSC1_PIC(v) (((v) << 14) & 0xc000) | ||
| 612 | #define BF_USBCTRL_PORTSC1_PIC_V(v) ((BV_USBCTRL_PORTSC1_PIC__##v << 14) & 0xc000) | ||
| 613 | #define BP_USBCTRL_PORTSC1_PO 13 | ||
| 614 | #define BM_USBCTRL_PORTSC1_PO 0x2000 | ||
| 615 | #define BF_USBCTRL_PORTSC1_PO(v) (((v) << 13) & 0x2000) | ||
| 616 | #define BP_USBCTRL_PORTSC1_PP 12 | ||
| 617 | #define BM_USBCTRL_PORTSC1_PP 0x1000 | ||
| 618 | #define BF_USBCTRL_PORTSC1_PP(v) (((v) << 12) & 0x1000) | ||
| 619 | #define BP_USBCTRL_PORTSC1_LS 10 | ||
| 620 | #define BM_USBCTRL_PORTSC1_LS 0xc00 | ||
| 621 | #define BV_USBCTRL_PORTSC1_LS__SE0 0x0 | ||
| 622 | #define BV_USBCTRL_PORTSC1_LS__K 0x1 | ||
| 623 | #define BV_USBCTRL_PORTSC1_LS__J 0x2 | ||
| 624 | #define BF_USBCTRL_PORTSC1_LS(v) (((v) << 10) & 0xc00) | ||
| 625 | #define BF_USBCTRL_PORTSC1_LS_V(v) ((BV_USBCTRL_PORTSC1_LS__##v << 10) & 0xc00) | ||
| 626 | #define BP_USBCTRL_PORTSC1_HSP 9 | ||
| 627 | #define BM_USBCTRL_PORTSC1_HSP 0x200 | ||
| 628 | #define BF_USBCTRL_PORTSC1_HSP(v) (((v) << 9) & 0x200) | ||
| 629 | #define BP_USBCTRL_PORTSC1_PR 8 | ||
| 630 | #define BM_USBCTRL_PORTSC1_PR 0x100 | ||
| 631 | #define BF_USBCTRL_PORTSC1_PR(v) (((v) << 8) & 0x100) | ||
| 632 | #define BP_USBCTRL_PORTSC1_SUSP 7 | ||
| 633 | #define BM_USBCTRL_PORTSC1_SUSP 0x80 | ||
| 634 | #define BF_USBCTRL_PORTSC1_SUSP(v) (((v) << 7) & 0x80) | ||
| 635 | #define BP_USBCTRL_PORTSC1_FPR 6 | ||
| 636 | #define BM_USBCTRL_PORTSC1_FPR 0x40 | ||
| 637 | #define BF_USBCTRL_PORTSC1_FPR(v) (((v) << 6) & 0x40) | ||
| 638 | #define BP_USBCTRL_PORTSC1_OCC 5 | ||
| 639 | #define BM_USBCTRL_PORTSC1_OCC 0x20 | ||
| 640 | #define BF_USBCTRL_PORTSC1_OCC(v) (((v) << 5) & 0x20) | ||
| 641 | #define BP_USBCTRL_PORTSC1_OCA 4 | ||
| 642 | #define BM_USBCTRL_PORTSC1_OCA 0x10 | ||
| 643 | #define BF_USBCTRL_PORTSC1_OCA(v) (((v) << 4) & 0x10) | ||
| 644 | #define BP_USBCTRL_PORTSC1_PEC 3 | ||
| 645 | #define BM_USBCTRL_PORTSC1_PEC 0x8 | ||
| 646 | #define BF_USBCTRL_PORTSC1_PEC(v) (((v) << 3) & 0x8) | ||
| 647 | #define BP_USBCTRL_PORTSC1_PE 2 | ||
| 648 | #define BM_USBCTRL_PORTSC1_PE 0x4 | ||
| 649 | #define BF_USBCTRL_PORTSC1_PE(v) (((v) << 2) & 0x4) | ||
| 650 | #define BP_USBCTRL_PORTSC1_CSC 1 | ||
| 651 | #define BM_USBCTRL_PORTSC1_CSC 0x2 | ||
| 652 | #define BF_USBCTRL_PORTSC1_CSC(v) (((v) << 1) & 0x2) | ||
| 653 | #define BP_USBCTRL_PORTSC1_CCS 0 | ||
| 654 | #define BM_USBCTRL_PORTSC1_CCS 0x1 | ||
| 655 | #define BF_USBCTRL_PORTSC1_CCS(v) (((v) << 0) & 0x1) | ||
| 656 | |||
| 657 | /** | ||
| 658 | * Register: HW_USBCTRL_OTGSC | ||
| 659 | * Address: 0x1a4 | ||
| 660 | * SCT: no | ||
| 661 | */ | ||
| 662 | #define HW_USBCTRL_OTGSC (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a4)) | ||
| 663 | #define BP_USBCTRL_OTGSC_DPIE 30 | ||
| 664 | #define BM_USBCTRL_OTGSC_DPIE 0x40000000 | ||
| 665 | #define BF_USBCTRL_OTGSC_DPIE(v) (((v) << 30) & 0x40000000) | ||
| 666 | #define BP_USBCTRL_OTGSC_ONEMSE 29 | ||
| 667 | #define BM_USBCTRL_OTGSC_ONEMSE 0x20000000 | ||
| 668 | #define BF_USBCTRL_OTGSC_ONEMSE(v) (((v) << 29) & 0x20000000) | ||
| 669 | #define BP_USBCTRL_OTGSC_BSEIE 28 | ||
| 670 | #define BM_USBCTRL_OTGSC_BSEIE 0x10000000 | ||
| 671 | #define BF_USBCTRL_OTGSC_BSEIE(v) (((v) << 28) & 0x10000000) | ||
| 672 | #define BP_USBCTRL_OTGSC_BSVIE 27 | ||
| 673 | #define BM_USBCTRL_OTGSC_BSVIE 0x8000000 | ||
| 674 | #define BF_USBCTRL_OTGSC_BSVIE(v) (((v) << 27) & 0x8000000) | ||
| 675 | #define BP_USBCTRL_OTGSC_ASVIE 26 | ||
| 676 | #define BM_USBCTRL_OTGSC_ASVIE 0x4000000 | ||
| 677 | #define BF_USBCTRL_OTGSC_ASVIE(v) (((v) << 26) & 0x4000000) | ||
| 678 | #define BP_USBCTRL_OTGSC_AVVIE 25 | ||
| 679 | #define BM_USBCTRL_OTGSC_AVVIE 0x2000000 | ||
| 680 | #define BF_USBCTRL_OTGSC_AVVIE(v) (((v) << 25) & 0x2000000) | ||
| 681 | #define BP_USBCTRL_OTGSC_IDIE 24 | ||
| 682 | #define BM_USBCTRL_OTGSC_IDIE 0x1000000 | ||
| 683 | #define BF_USBCTRL_OTGSC_IDIE(v) (((v) << 24) & 0x1000000) | ||
| 684 | #define BP_USBCTRL_OTGSC_DPIS 22 | ||
| 685 | #define BM_USBCTRL_OTGSC_DPIS 0x400000 | ||
| 686 | #define BF_USBCTRL_OTGSC_DPIS(v) (((v) << 22) & 0x400000) | ||
| 687 | #define BP_USBCTRL_OTGSC_ONEMSS 21 | ||
| 688 | #define BM_USBCTRL_OTGSC_ONEMSS 0x200000 | ||
| 689 | #define BF_USBCTRL_OTGSC_ONEMSS(v) (((v) << 21) & 0x200000) | ||
| 690 | #define BP_USBCTRL_OTGSC_BSEIS 20 | ||
| 691 | #define BM_USBCTRL_OTGSC_BSEIS 0x100000 | ||
| 692 | #define BF_USBCTRL_OTGSC_BSEIS(v) (((v) << 20) & 0x100000) | ||
| 693 | #define BP_USBCTRL_OTGSC_BSVIS 19 | ||
| 694 | #define BM_USBCTRL_OTGSC_BSVIS 0x80000 | ||
| 695 | #define BF_USBCTRL_OTGSC_BSVIS(v) (((v) << 19) & 0x80000) | ||
| 696 | #define BP_USBCTRL_OTGSC_ASVIS 18 | ||
| 697 | #define BM_USBCTRL_OTGSC_ASVIS 0x40000 | ||
| 698 | #define BF_USBCTRL_OTGSC_ASVIS(v) (((v) << 18) & 0x40000) | ||
| 699 | #define BP_USBCTRL_OTGSC_AVVIS 17 | ||
| 700 | #define BM_USBCTRL_OTGSC_AVVIS 0x20000 | ||
| 701 | #define BF_USBCTRL_OTGSC_AVVIS(v) (((v) << 17) & 0x20000) | ||
| 702 | #define BP_USBCTRL_OTGSC_IDIS 16 | ||
| 703 | #define BM_USBCTRL_OTGSC_IDIS 0x10000 | ||
| 704 | #define BF_USBCTRL_OTGSC_IDIS(v) (((v) << 16) & 0x10000) | ||
| 705 | #define BP_USBCTRL_OTGSC_DPS 14 | ||
| 706 | #define BM_USBCTRL_OTGSC_DPS 0x4000 | ||
| 707 | #define BF_USBCTRL_OTGSC_DPS(v) (((v) << 14) & 0x4000) | ||
| 708 | #define BP_USBCTRL_OTGSC_ONEMST 13 | ||
| 709 | #define BM_USBCTRL_OTGSC_ONEMST 0x2000 | ||
| 710 | #define BF_USBCTRL_OTGSC_ONEMST(v) (((v) << 13) & 0x2000) | ||
| 711 | #define BP_USBCTRL_OTGSC_BSE 12 | ||
| 712 | #define BM_USBCTRL_OTGSC_BSE 0x1000 | ||
| 713 | #define BF_USBCTRL_OTGSC_BSE(v) (((v) << 12) & 0x1000) | ||
| 714 | #define BP_USBCTRL_OTGSC_BSV 11 | ||
| 715 | #define BM_USBCTRL_OTGSC_BSV 0x800 | ||
| 716 | #define BF_USBCTRL_OTGSC_BSV(v) (((v) << 11) & 0x800) | ||
| 717 | #define BP_USBCTRL_OTGSC_ASV 10 | ||
| 718 | #define BM_USBCTRL_OTGSC_ASV 0x400 | ||
| 719 | #define BF_USBCTRL_OTGSC_ASV(v) (((v) << 10) & 0x400) | ||
| 720 | #define BP_USBCTRL_OTGSC_AVV 9 | ||
| 721 | #define BM_USBCTRL_OTGSC_AVV 0x200 | ||
| 722 | #define BF_USBCTRL_OTGSC_AVV(v) (((v) << 9) & 0x200) | ||
| 723 | #define BP_USBCTRL_OTGSC_ID 8 | ||
| 724 | #define BM_USBCTRL_OTGSC_ID 0x100 | ||
| 725 | #define BF_USBCTRL_OTGSC_ID(v) (((v) << 8) & 0x100) | ||
| 726 | #define BP_USBCTRL_OTGSC_HABA 7 | ||
| 727 | #define BM_USBCTRL_OTGSC_HABA 0x80 | ||
| 728 | #define BF_USBCTRL_OTGSC_HABA(v) (((v) << 7) & 0x80) | ||
| 729 | #define BP_USBCTRL_OTGSC_HADP 6 | ||
| 730 | #define BM_USBCTRL_OTGSC_HADP 0x40 | ||
| 731 | #define BF_USBCTRL_OTGSC_HADP(v) (((v) << 6) & 0x40) | ||
| 732 | #define BP_USBCTRL_OTGSC_IDPU 5 | ||
| 733 | #define BM_USBCTRL_OTGSC_IDPU 0x20 | ||
| 734 | #define BF_USBCTRL_OTGSC_IDPU(v) (((v) << 5) & 0x20) | ||
| 735 | #define BP_USBCTRL_OTGSC_DP 4 | ||
| 736 | #define BM_USBCTRL_OTGSC_DP 0x10 | ||
| 737 | #define BF_USBCTRL_OTGSC_DP(v) (((v) << 4) & 0x10) | ||
| 738 | #define BP_USBCTRL_OTGSC_OT 3 | ||
| 739 | #define BM_USBCTRL_OTGSC_OT 0x8 | ||
| 740 | #define BF_USBCTRL_OTGSC_OT(v) (((v) << 3) & 0x8) | ||
| 741 | #define BP_USBCTRL_OTGSC_HAAR 2 | ||
| 742 | #define BM_USBCTRL_OTGSC_HAAR 0x4 | ||
| 743 | #define BF_USBCTRL_OTGSC_HAAR(v) (((v) << 2) & 0x4) | ||
| 744 | #define BP_USBCTRL_OTGSC_VC 1 | ||
| 745 | #define BM_USBCTRL_OTGSC_VC 0x2 | ||
| 746 | #define BF_USBCTRL_OTGSC_VC(v) (((v) << 1) & 0x2) | ||
| 747 | #define BP_USBCTRL_OTGSC_VD 0 | ||
| 748 | #define BM_USBCTRL_OTGSC_VD 0x1 | ||
| 749 | #define BF_USBCTRL_OTGSC_VD(v) (((v) << 0) & 0x1) | ||
| 750 | |||
| 751 | /** | ||
| 752 | * Register: HW_USBCTRL_USBMODE | ||
| 753 | * Address: 0x1a8 | ||
| 754 | * SCT: no | ||
| 755 | */ | ||
| 756 | #define HW_USBCTRL_USBMODE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1a8)) | ||
| 757 | #define BP_USBCTRL_USBMODE_SDIS 4 | ||
| 758 | #define BM_USBCTRL_USBMODE_SDIS 0x10 | ||
| 759 | #define BF_USBCTRL_USBMODE_SDIS(v) (((v) << 4) & 0x10) | ||
| 760 | #define BP_USBCTRL_USBMODE_SLOM 3 | ||
| 761 | #define BM_USBCTRL_USBMODE_SLOM 0x8 | ||
| 762 | #define BF_USBCTRL_USBMODE_SLOM(v) (((v) << 3) & 0x8) | ||
| 763 | #define BP_USBCTRL_USBMODE_ES 2 | ||
| 764 | #define BM_USBCTRL_USBMODE_ES 0x4 | ||
| 765 | #define BF_USBCTRL_USBMODE_ES(v) (((v) << 2) & 0x4) | ||
| 766 | #define BP_USBCTRL_USBMODE_CM 0 | ||
| 767 | #define BM_USBCTRL_USBMODE_CM 0x3 | ||
| 768 | #define BV_USBCTRL_USBMODE_CM__IDLE 0x0 | ||
| 769 | #define BV_USBCTRL_USBMODE_CM__DEVICE 0x2 | ||
| 770 | #define BV_USBCTRL_USBMODE_CM__HOST 0x3 | ||
| 771 | #define BF_USBCTRL_USBMODE_CM(v) (((v) << 0) & 0x3) | ||
| 772 | #define BF_USBCTRL_USBMODE_CM_V(v) ((BV_USBCTRL_USBMODE_CM__##v << 0) & 0x3) | ||
| 773 | |||
| 774 | /** | ||
| 775 | * Register: HW_USBCTRL_ENDPTSETUPSTAT | ||
| 776 | * Address: 0x1ac | ||
| 777 | * SCT: no | ||
| 778 | */ | ||
| 779 | #define HW_USBCTRL_ENDPTSETUPSTAT (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1ac)) | ||
| 780 | #define BP_USBCTRL_ENDPTSETUPSTAT_STS 0 | ||
| 781 | #define BM_USBCTRL_ENDPTSETUPSTAT_STS 0xffff | ||
| 782 | #define BF_USBCTRL_ENDPTSETUPSTAT_STS(v) (((v) << 0) & 0xffff) | ||
| 783 | |||
| 784 | /** | ||
| 785 | * Register: HW_USBCTRL_ENDPTPRIME | ||
| 786 | * Address: 0x1b0 | ||
| 787 | * SCT: no | ||
| 788 | */ | ||
| 789 | #define HW_USBCTRL_ENDPTPRIME (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b0)) | ||
| 790 | #define BP_USBCTRL_ENDPTPRIME_PETB 16 | ||
| 791 | #define BM_USBCTRL_ENDPTPRIME_PETB 0xffff0000 | ||
| 792 | #define BF_USBCTRL_ENDPTPRIME_PETB(v) (((v) << 16) & 0xffff0000) | ||
| 793 | #define BP_USBCTRL_ENDPTPRIME_PERB 0 | ||
| 794 | #define BM_USBCTRL_ENDPTPRIME_PERB 0xffff | ||
| 795 | #define BF_USBCTRL_ENDPTPRIME_PERB(v) (((v) << 0) & 0xffff) | ||
| 796 | |||
| 797 | /** | ||
| 798 | * Register: HW_USBCTRL_ENDPTFLUSH | ||
| 799 | * Address: 0x1b4 | ||
| 800 | * SCT: no | ||
| 801 | */ | ||
| 802 | #define HW_USBCTRL_ENDPTFLUSH (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b4)) | ||
| 803 | #define BP_USBCTRL_ENDPTFLUSH_FETB 16 | ||
| 804 | #define BM_USBCTRL_ENDPTFLUSH_FETB 0xffff0000 | ||
| 805 | #define BF_USBCTRL_ENDPTFLUSH_FETB(v) (((v) << 16) & 0xffff0000) | ||
| 806 | #define BP_USBCTRL_ENDPTFLUSH_FERB 0 | ||
| 807 | #define BM_USBCTRL_ENDPTFLUSH_FERB 0xffff | ||
| 808 | #define BF_USBCTRL_ENDPTFLUSH_FERB(v) (((v) << 0) & 0xffff) | ||
| 809 | |||
| 810 | /** | ||
| 811 | * Register: HW_USBCTRL_ENDPTSTATUS | ||
| 812 | * Address: 0x1b8 | ||
| 813 | * SCT: no | ||
| 814 | */ | ||
| 815 | #define HW_USBCTRL_ENDPTSTATUS (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1b8)) | ||
| 816 | #define BP_USBCTRL_ENDPTSTATUS_ETBR 16 | ||
| 817 | #define BM_USBCTRL_ENDPTSTATUS_ETBR 0xffff0000 | ||
| 818 | #define BF_USBCTRL_ENDPTSTATUS_ETBR(v) (((v) << 16) & 0xffff0000) | ||
| 819 | #define BP_USBCTRL_ENDPTSTATUS_ERBR 0 | ||
| 820 | #define BM_USBCTRL_ENDPTSTATUS_ERBR 0xffff | ||
| 821 | #define BF_USBCTRL_ENDPTSTATUS_ERBR(v) (((v) << 0) & 0xffff) | ||
| 822 | |||
| 823 | /** | ||
| 824 | * Register: HW_USBCTRL_ENDPTCOMPLETE | ||
| 825 | * Address: 0x1bc | ||
| 826 | * SCT: no | ||
| 827 | */ | ||
| 828 | #define HW_USBCTRL_ENDPTCOMPLETE (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1bc)) | ||
| 829 | #define BP_USBCTRL_ENDPTCOMPLETE_ETCE 16 | ||
| 830 | #define BM_USBCTRL_ENDPTCOMPLETE_ETCE 0xffff0000 | ||
| 831 | #define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v) (((v) << 16) & 0xffff0000) | ||
| 832 | #define BP_USBCTRL_ENDPTCOMPLETE_ERCE 0 | ||
| 833 | #define BM_USBCTRL_ENDPTCOMPLETE_ERCE 0xffff | ||
| 834 | #define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v) (((v) << 0) & 0xffff) | ||
| 835 | |||
| 836 | /** | ||
| 837 | * Register: HW_USBCTRL_ENDPTCTRLn | ||
| 838 | * Address: 0x1c0+n*0x4 | ||
| 839 | * SCT: no | ||
| 840 | */ | ||
| 841 | #define HW_USBCTRL_ENDPTCTRLn(n) (*(volatile unsigned long *)(REGS_USBCTRL_BASE + 0x1c0+(n)*0x4)) | ||
| 842 | #define BP_USBCTRL_ENDPTCTRLn_TXE 23 | ||
| 843 | #define BM_USBCTRL_ENDPTCTRLn_TXE 0x800000 | ||
| 844 | #define BF_USBCTRL_ENDPTCTRLn_TXE(v) (((v) << 23) & 0x800000) | ||
| 845 | #define BP_USBCTRL_ENDPTCTRLn_TXR 22 | ||
| 846 | #define BM_USBCTRL_ENDPTCTRLn_TXR 0x400000 | ||
| 847 | #define BF_USBCTRL_ENDPTCTRLn_TXR(v) (((v) << 22) & 0x400000) | ||
| 848 | #define BP_USBCTRL_ENDPTCTRLn_TXI 21 | ||
| 849 | #define BM_USBCTRL_ENDPTCTRLn_TXI 0x200000 | ||
| 850 | #define BF_USBCTRL_ENDPTCTRLn_TXI(v) (((v) << 21) & 0x200000) | ||
| 851 | #define BP_USBCTRL_ENDPTCTRLn_TXT 18 | ||
| 852 | #define BM_USBCTRL_ENDPTCTRLn_TXT 0xc0000 | ||
| 853 | #define BV_USBCTRL_ENDPTCTRLn_TXT__ISOCHRONOUS 0x1 | ||
| 854 | #define BV_USBCTRL_ENDPTCTRLn_TXT__BULK 0x2 | ||
| 855 | #define BV_USBCTRL_ENDPTCTRLn_TXT__INT 0x3 | ||
| 856 | #define BF_USBCTRL_ENDPTCTRLn_TXT(v) (((v) << 18) & 0xc0000) | ||
| 857 | #define BF_USBCTRL_ENDPTCTRLn_TXT_V(v) ((BV_USBCTRL_ENDPTCTRLn_TXT__##v << 18) & 0xc0000) | ||
| 858 | #define BP_USBCTRL_ENDPTCTRLn_TXS 16 | ||
| 859 | #define BM_USBCTRL_ENDPTCTRLn_TXS 0x10000 | ||
| 860 | #define BF_USBCTRL_ENDPTCTRLn_TXS(v) (((v) << 16) & 0x10000) | ||
| 861 | #define BP_USBCTRL_ENDPTCTRLn_RXE 7 | ||
| 862 | #define BM_USBCTRL_ENDPTCTRLn_RXE 0x80 | ||
| 863 | #define BF_USBCTRL_ENDPTCTRLn_RXE(v) (((v) << 7) & 0x80) | ||
| 864 | #define BP_USBCTRL_ENDPTCTRLn_RXR 6 | ||
| 865 | #define BM_USBCTRL_ENDPTCTRLn_RXR 0x40 | ||
| 866 | #define BF_USBCTRL_ENDPTCTRLn_RXR(v) (((v) << 6) & 0x40) | ||
| 867 | #define BP_USBCTRL_ENDPTCTRLn_RXI 5 | ||
| 868 | #define BM_USBCTRL_ENDPTCTRLn_RXI 0x20 | ||
| 869 | #define BF_USBCTRL_ENDPTCTRLn_RXI(v) (((v) << 5) & 0x20) | ||
| 870 | #define BP_USBCTRL_ENDPTCTRLn_RXT 2 | ||
| 871 | #define BM_USBCTRL_ENDPTCTRLn_RXT 0xc | ||
| 872 | #define BF_USBCTRL_ENDPTCTRLn_RXT(v) (((v) << 2) & 0xc) | ||
| 873 | #define BP_USBCTRL_ENDPTCTRLn_RXS 0 | ||
| 874 | #define BM_USBCTRL_ENDPTCTRLn_RXS 0x1 | ||
| 875 | #define BF_USBCTRL_ENDPTCTRLn_RXS(v) (((v) << 0) & 0x1) | ||
| 876 | |||
| 877 | #endif /* __HEADERGEN__STMP3700__USBCTRL__H__ */ | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h b/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h new file mode 100644 index 0000000000..ae9359e1dd --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-usbphy.h | |||
| @@ -0,0 +1,300 @@ | |||
| 1 | /*************************************************************************** | ||
| 2 | * __________ __ ___. | ||
| 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
| 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
| 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
| 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
| 7 | * \/ \/ \/ \/ \/ | ||
| 8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
| 9 | * headergen version: 2.1.7 | ||
| 10 | * XML versions: stmp3700:3.2.0 | ||
| 11 | * | ||
| 12 | * Copyright (C) 2013 by Amaury Pouly | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or | ||
| 15 | * modify it under the terms of the GNU General Public License | ||
| 16 | * as published by the Free Software Foundation; either version 2 | ||
| 17 | * of the License, or (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
| 20 | * KIND, either express or implied. | ||
| 21 | * | ||
| 22 | ****************************************************************************/ | ||
| 23 | #ifndef __HEADERGEN__STMP3700__USBPHY__H__ | ||
| 24 | #define __HEADERGEN__STMP3700__USBPHY__H__ | ||
| 25 | |||
| 26 | #define REGS_USBPHY_BASE (0x8007c000) | ||
| 27 | |||
| 28 | #define REGS_USBPHY_VERSION "3.2.0" | ||
| 29 | |||
| 30 | /** | ||
| 31 | * Register: HW_USBPHY_PWD | ||
| 32 | * Address: 0 | ||
| 33 | * SCT: yes | ||
| 34 | */ | ||
| 35 | #define HW_USBPHY_PWD (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x0)) | ||
| 36 | #define HW_USBPHY_PWD_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x4)) | ||
| 37 | #define HW_USBPHY_PWD_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0x8)) | ||
| 38 | #define HW_USBPHY_PWD_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x0 + 0xc)) | ||
| 39 | #define BP_USBPHY_PWD_RXPWDRX 20 | ||
| 40 | #define BM_USBPHY_PWD_RXPWDRX 0x100000 | ||
| 41 | #define BF_USBPHY_PWD_RXPWDRX(v) (((v) << 20) & 0x100000) | ||
| 42 | #define BP_USBPHY_PWD_RXPWDDIFF 19 | ||
| 43 | #define BM_USBPHY_PWD_RXPWDDIFF 0x80000 | ||
| 44 | #define BF_USBPHY_PWD_RXPWDDIFF(v) (((v) << 19) & 0x80000) | ||
| 45 | #define BP_USBPHY_PWD_RXPWD1PT1 18 | ||
| 46 | #define BM_USBPHY_PWD_RXPWD1PT1 0x40000 | ||
| 47 | #define BF_USBPHY_PWD_RXPWD1PT1(v) (((v) << 18) & 0x40000) | ||
| 48 | #define BP_USBPHY_PWD_RXPWDENV 17 | ||
| 49 | #define BM_USBPHY_PWD_RXPWDENV 0x20000 | ||
| 50 | #define BF_USBPHY_PWD_RXPWDENV(v) (((v) << 17) & 0x20000) | ||
| 51 | #define BP_USBPHY_PWD_TXPWDCOMP 14 | ||
| 52 | #define BM_USBPHY_PWD_TXPWDCOMP 0x4000 | ||
| 53 | #define BF_USBPHY_PWD_TXPWDCOMP(v) (((v) << 14) & 0x4000) | ||
| 54 | #define BP_USBPHY_PWD_TXPWDVBG 13 | ||
| 55 | #define BM_USBPHY_PWD_TXPWDVBG 0x2000 | ||
| 56 | #define BF_USBPHY_PWD_TXPWDVBG(v) (((v) << 13) & 0x2000) | ||
| 57 | #define BP_USBPHY_PWD_TXPWDV2I 12 | ||
| 58 | #define BM_USBPHY_PWD_TXPWDV2I 0x1000 | ||
| 59 | #define BF_USBPHY_PWD_TXPWDV2I(v) (((v) << 12) & 0x1000) | ||
| 60 | #define BP_USBPHY_PWD_TXPWDIBIAS 11 | ||
| 61 | #define BM_USBPHY_PWD_TXPWDIBIAS 0x800 | ||
| 62 | #define BF_USBPHY_PWD_TXPWDIBIAS(v) (((v) << 11) & 0x800) | ||
| 63 | #define BP_USBPHY_PWD_TXPWDFS 10 | ||
| 64 | #define BM_USBPHY_PWD_TXPWDFS 0x400 | ||
| 65 | #define BF_USBPHY_PWD_TXPWDFS(v) (((v) << 10) & 0x400) | ||
| 66 | |||
| 67 | /** | ||
| 68 | * Register: HW_USBPHY_TX | ||
| 69 | * Address: 0x10 | ||
| 70 | * SCT: yes | ||
| 71 | */ | ||
| 72 | #define HW_USBPHY_TX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x0)) | ||
| 73 | #define HW_USBPHY_TX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x4)) | ||
| 74 | #define HW_USBPHY_TX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0x8)) | ||
| 75 | #define HW_USBPHY_TX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x10 + 0xc)) | ||
| 76 | #define BP_USBPHY_TX_USBPHY_TX_EDGECTRL 26 | ||
| 77 | #define BM_USBPHY_TX_USBPHY_TX_EDGECTRL 0x1c000000 | ||
| 78 | #define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v) (((v) << 26) & 0x1c000000) | ||
| 79 | #define BP_USBPHY_TX_USBPHY_TX_SYNC_INVERT 25 | ||
| 80 | #define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT 0x2000000 | ||
| 81 | #define BF_USBPHY_TX_USBPHY_TX_SYNC_INVERT(v) (((v) << 25) & 0x2000000) | ||
| 82 | #define BP_USBPHY_TX_USBPHY_TX_SYNC_MUX 24 | ||
| 83 | #define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX 0x1000000 | ||
| 84 | #define BF_USBPHY_TX_USBPHY_TX_SYNC_MUX(v) (((v) << 24) & 0x1000000) | ||
| 85 | #define BP_USBPHY_TX_TXCMPOUT_STATUS 23 | ||
| 86 | #define BM_USBPHY_TX_TXCMPOUT_STATUS 0x800000 | ||
| 87 | #define BF_USBPHY_TX_TXCMPOUT_STATUS(v) (((v) << 23) & 0x800000) | ||
| 88 | #define BP_USBPHY_TX_TXENCAL45DP 21 | ||
| 89 | #define BM_USBPHY_TX_TXENCAL45DP 0x200000 | ||
| 90 | #define BF_USBPHY_TX_TXENCAL45DP(v) (((v) << 21) & 0x200000) | ||
| 91 | #define BP_USBPHY_TX_TXCAL45DP 16 | ||
| 92 | #define BM_USBPHY_TX_TXCAL45DP 0xf0000 | ||
| 93 | #define BF_USBPHY_TX_TXCAL45DP(v) (((v) << 16) & 0xf0000) | ||
| 94 | #define BP_USBPHY_TX_TXENCAL45DN 13 | ||
| 95 | #define BM_USBPHY_TX_TXENCAL45DN 0x2000 | ||
| 96 | #define BF_USBPHY_TX_TXENCAL45DN(v) (((v) << 13) & 0x2000) | ||
| 97 | #define BP_USBPHY_TX_TXCAL45DN 8 | ||
| 98 | #define BM_USBPHY_TX_TXCAL45DN 0xf00 | ||
| 99 | #define BF_USBPHY_TX_TXCAL45DN(v) (((v) << 8) & 0xf00) | ||
| 100 | #define BP_USBPHY_TX_TXCALIBRATE 7 | ||
| 101 | #define BM_USBPHY_TX_TXCALIBRATE 0x80 | ||
| 102 | #define BF_USBPHY_TX_TXCALIBRATE(v) (((v) << 7) & 0x80) | ||
| 103 | #define BP_USBPHY_TX_D_CAL 0 | ||
| 104 | #define BM_USBPHY_TX_D_CAL 0xf | ||
| 105 | #define BF_USBPHY_TX_D_CAL(v) (((v) << 0) & 0xf) | ||
| 106 | |||
| 107 | /** | ||
| 108 | * Register: HW_USBPHY_RX | ||
| 109 | * Address: 0x20 | ||
| 110 | * SCT: yes | ||
| 111 | */ | ||
| 112 | #define HW_USBPHY_RX (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x0)) | ||
| 113 | #define HW_USBPHY_RX_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x4)) | ||
| 114 | #define HW_USBPHY_RX_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0x8)) | ||
| 115 | #define HW_USBPHY_RX_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x20 + 0xc)) | ||
| 116 | #define BP_USBPHY_RX_RXDBYPASS 22 | ||
| 117 | #define BM_USBPHY_RX_RXDBYPASS 0x400000 | ||
| 118 | #define BF_USBPHY_RX_RXDBYPASS(v) (((v) << 22) & 0x400000) | ||
| 119 | #define BP_USBPHY_RX_DISCONADJ 4 | ||
| 120 | #define BM_USBPHY_RX_DISCONADJ 0x30 | ||
| 121 | #define BF_USBPHY_RX_DISCONADJ(v) (((v) << 4) & 0x30) | ||
| 122 | #define BP_USBPHY_RX_ENVADJ 0 | ||
| 123 | #define BM_USBPHY_RX_ENVADJ 0x3 | ||
| 124 | #define BF_USBPHY_RX_ENVADJ(v) (((v) << 0) & 0x3) | ||
| 125 | |||
| 126 | /** | ||
| 127 | * Register: HW_USBPHY_CTRL | ||
| 128 | * Address: 0x30 | ||
| 129 | * SCT: yes | ||
| 130 | */ | ||
| 131 | #define HW_USBPHY_CTRL (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x0)) | ||
| 132 | #define HW_USBPHY_CTRL_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x4)) | ||
| 133 | #define HW_USBPHY_CTRL_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0x8)) | ||
| 134 | #define HW_USBPHY_CTRL_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x30 + 0xc)) | ||
| 135 | #define BP_USBPHY_CTRL_SFTRST 31 | ||
| 136 | #define BM_USBPHY_CTRL_SFTRST 0x80000000 | ||
| 137 | #define BF_USBPHY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
| 138 | #define BP_USBPHY_CTRL_CLKGATE 30 | ||
| 139 | #define BM_USBPHY_CTRL_CLKGATE 0x40000000 | ||
| 140 | #define BF_USBPHY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 141 | #define BP_USBPHY_CTRL_UTMI_SUSPENDM 29 | ||
| 142 | #define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 | ||
| 143 | #define BF_USBPHY_CTRL_UTMI_SUSPENDM(v) (((v) << 29) & 0x20000000) | ||
| 144 | #define BP_USBPHY_CTRL_HOST_FORCE_LS_SE0 28 | ||
| 145 | #define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 0x10000000 | ||
| 146 | #define BF_USBPHY_CTRL_HOST_FORCE_LS_SE0(v) (((v) << 28) & 0x10000000) | ||
| 147 | #define BP_USBPHY_CTRL_DATA_ON_LRADC 13 | ||
| 148 | #define BM_USBPHY_CTRL_DATA_ON_LRADC 0x2000 | ||
| 149 | #define BF_USBPHY_CTRL_DATA_ON_LRADC(v) (((v) << 13) & 0x2000) | ||
| 150 | #define BP_USBPHY_CTRL_DEVPLUGIN_IRQ 12 | ||
| 151 | #define BM_USBPHY_CTRL_DEVPLUGIN_IRQ 0x1000 | ||
| 152 | #define BF_USBPHY_CTRL_DEVPLUGIN_IRQ(v) (((v) << 12) & 0x1000) | ||
| 153 | #define BP_USBPHY_CTRL_ENIRQDEVPLUGIN 11 | ||
| 154 | #define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x800 | ||
| 155 | #define BF_USBPHY_CTRL_ENIRQDEVPLUGIN(v) (((v) << 11) & 0x800) | ||
| 156 | #define BP_USBPHY_CTRL_RESUME_IRQ 10 | ||
| 157 | #define BM_USBPHY_CTRL_RESUME_IRQ 0x400 | ||
| 158 | #define BF_USBPHY_CTRL_RESUME_IRQ(v) (((v) << 10) & 0x400) | ||
| 159 | #define BP_USBPHY_CTRL_ENIRQRESUMEDETECT 9 | ||
| 160 | #define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x200 | ||
| 161 | #define BF_USBPHY_CTRL_ENIRQRESUMEDETECT(v) (((v) << 9) & 0x200) | ||
| 162 | #define BP_USBPHY_CTRL_ENOTGIDDETECT 7 | ||
| 163 | #define BM_USBPHY_CTRL_ENOTGIDDETECT 0x80 | ||
| 164 | #define BF_USBPHY_CTRL_ENOTGIDDETECT(v) (((v) << 7) & 0x80) | ||
| 165 | #define BP_USBPHY_CTRL_DEVPLUGIN_POLARITY 5 | ||
| 166 | #define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY 0x20 | ||
| 167 | #define BF_USBPHY_CTRL_DEVPLUGIN_POLARITY(v) (((v) << 5) & 0x20) | ||
| 168 | #define BP_USBPHY_CTRL_ENDEVPLUGINDETECT 4 | ||
| 169 | #define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x10 | ||
| 170 | #define BF_USBPHY_CTRL_ENDEVPLUGINDETECT(v) (((v) << 4) & 0x10) | ||
| 171 | #define BP_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 3 | ||
| 172 | #define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x8 | ||
| 173 | #define BF_USBPHY_CTRL_HOSTDISCONDETECT_IRQ(v) (((v) << 3) & 0x8) | ||
| 174 | #define BP_USBPHY_CTRL_ENIRQHOSTDISCON 2 | ||
| 175 | #define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x4 | ||
| 176 | #define BF_USBPHY_CTRL_ENIRQHOSTDISCON(v) (((v) << 2) & 0x4) | ||
| 177 | #define BP_USBPHY_CTRL_ENHOSTDISCONDETECT 1 | ||
| 178 | #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x2 | ||
| 179 | #define BF_USBPHY_CTRL_ENHOSTDISCONDETECT(v) (((v) << 1) & 0x2) | ||
| 180 | #define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0 | ||
| 181 | #define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x1 | ||
| 182 | #define BF_USBPHY_CTRL_ENHSPRECHARGEXMIT(v) (((v) << 0) & 0x1) | ||
| 183 | |||
| 184 | /** | ||
| 185 | * Register: HW_USBPHY_STATUS | ||
| 186 | * Address: 0x40 | ||
| 187 | * SCT: no | ||
| 188 | */ | ||
| 189 | #define HW_USBPHY_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x40)) | ||
| 190 | #define BP_USBPHY_STATUS_RESUME_STATUS 10 | ||
| 191 | #define BM_USBPHY_STATUS_RESUME_STATUS 0x400 | ||
| 192 | #define BF_USBPHY_STATUS_RESUME_STATUS(v) (((v) << 10) & 0x400) | ||
| 193 | #define BP_USBPHY_STATUS_OTGID_STATUS 8 | ||
| 194 | #define BM_USBPHY_STATUS_OTGID_STATUS 0x100 | ||
| 195 | #define BF_USBPHY_STATUS_OTGID_STATUS(v) (((v) << 8) & 0x100) | ||
| 196 | #define BP_USBPHY_STATUS_DEVPLUGIN_STATUS 6 | ||
| 197 | #define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x40 | ||
| 198 | #define BF_USBPHY_STATUS_DEVPLUGIN_STATUS(v) (((v) << 6) & 0x40) | ||
| 199 | #define BP_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 3 | ||
| 200 | #define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x8 | ||
| 201 | #define BF_USBPHY_STATUS_HOSTDISCONDETECT_STATUS(v) (((v) << 3) & 0x8) | ||
| 202 | |||
| 203 | /** | ||
| 204 | * Register: HW_USBPHY_DEBUG | ||
| 205 | * Address: 0x50 | ||
| 206 | * SCT: yes | ||
| 207 | */ | ||
| 208 | #define HW_USBPHY_DEBUG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x0)) | ||
| 209 | #define HW_USBPHY_DEBUG_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x4)) | ||
| 210 | #define HW_USBPHY_DEBUG_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0x8)) | ||
| 211 | #define HW_USBPHY_DEBUG_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x50 + 0xc)) | ||
| 212 | #define BP_USBPHY_DEBUG_CLKGATE 30 | ||
| 213 | #define BM_USBPHY_DEBUG_CLKGATE 0x40000000 | ||
| 214 | #define BF_USBPHY_DEBUG_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
| 215 | #define BP_USBPHY_DEBUG_HOST_RESUME_DEBUG 29 | ||
| 216 | #define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG 0x20000000 | ||
| 217 | #define BF_USBPHY_DEBUG_HOST_RESUME_DEBUG(v) (((v) << 29) & 0x20000000) | ||
| 218 | #define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 | ||
| 219 | #define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1e000000 | ||
| 220 | #define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) (((v) << 25) & 0x1e000000) | ||
| 221 | #define BP_USBPHY_DEBUG_ENSQUELCHRESET 24 | ||
| 222 | #define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x1000000 | ||
| 223 | #define BF_USBPHY_DEBUG_ENSQUELCHRESET(v) (((v) << 24) & 0x1000000) | ||
| 224 | #define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 | ||
| 225 | #define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x1f0000 | ||
| 226 | #define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) (((v) << 16) & 0x1f0000) | ||
| 227 | #define BP_USBPHY_DEBUG_ENTX2RXCOUNT 12 | ||
| 228 | #define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x1000 | ||
| 229 | #define BF_USBPHY_DEBUG_ENTX2RXCOUNT(v) (((v) << 12) & 0x1000) | ||
| 230 | #define BP_USBPHY_DEBUG_TX2RXCOUNT 8 | ||
| 231 | #define BM_USBPHY_DEBUG_TX2RXCOUNT 0xf00 | ||
| 232 | #define BF_USBPHY_DEBUG_TX2RXCOUNT(v) (((v) << 8) & 0xf00) | ||
| 233 | #define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 | ||
| 234 | #define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x30 | ||
| 235 | #define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) (((v) << 4) & 0x30) | ||
| 236 | #define BP_USBPHY_DEBUG_HSTPULLDOWN 2 | ||
| 237 | #define BM_USBPHY_DEBUG_HSTPULLDOWN 0xc | ||
| 238 | #define BF_USBPHY_DEBUG_HSTPULLDOWN(v) (((v) << 2) & 0xc) | ||
| 239 | #define BP_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 1 | ||
| 240 | #define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x2 | ||
| 241 | #define BF_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(v) (((v) << 1) & 0x2) | ||
| 242 | #define BP_USBPHY_DEBUG_OTGIDPIOLOCK 0 | ||
| 243 | #define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x1 | ||
| 244 | #define BF_USBPHY_DEBUG_OTGIDPIOLOCK(v) (((v) << 0) & 0x1) | ||
| 245 | |||
| 246 | /** | ||
| 247 | * Register: HW_USBPHY_DEBUG0_STATUS | ||
| 248 | * Address: 0x60 | ||
| 249 | * SCT: no | ||
| 250 | */ | ||
| 251 | #define HW_USBPHY_DEBUG0_STATUS (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x60)) | ||
| 252 | #define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 | ||
| 253 | #define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xfc000000 | ||
| 254 | #define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) (((v) << 26) & 0xfc000000) | ||
| 255 | #define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 | ||
| 256 | #define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x3ff0000 | ||
| 257 | #define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) (((v) << 16) & 0x3ff0000) | ||
| 258 | #define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 | ||
| 259 | #define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0xffff | ||
| 260 | #define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) (((v) << 0) & 0xffff) | ||
| 261 | |||
| 262 | /** | ||
| 263 | * Register: HW_USBPHY_DEBUG1 | ||
| 264 | * Address: 0x70 | ||
| 265 | * SCT: yes | ||
| 266 | */ | ||
| 267 | #define HW_USBPHY_DEBUG1 (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x0)) | ||
| 268 | #define HW_USBPHY_DEBUG1_SET (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x4)) | ||
| 269 | #define HW_USBPHY_DEBUG1_CLR (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0x8)) | ||
| 270 | #define HW_USBPHY_DEBUG1_TOG (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x70 + 0xc)) | ||
| 271 | #define BP_USBPHY_DEBUG1_ENTAILADJVD 13 | ||
| 272 | #define BM_USBPHY_DEBUG1_ENTAILADJVD 0x6000 | ||
| 273 | #define BF_USBPHY_DEBUG1_ENTAILADJVD(v) (((v) << 13) & 0x6000) | ||
| 274 | #define BP_USBPHY_DEBUG1_ENTX2TX 12 | ||
| 275 | #define BM_USBPHY_DEBUG1_ENTX2TX 0x1000 | ||
| 276 | #define BF_USBPHY_DEBUG1_ENTX2TX(v) (((v) << 12) & 0x1000) | ||
| 277 | #define BP_USBPHY_DEBUG1_PLL_IS_240 8 | ||
| 278 | #define BM_USBPHY_DEBUG1_PLL_IS_240 0x100 | ||
| 279 | #define BF_USBPHY_DEBUG1_PLL_IS_240(v) (((v) << 8) & 0x100) | ||
| 280 | #define BP_USBPHY_DEBUG1_DBG_ADDRESS 0 | ||
| 281 | #define BM_USBPHY_DEBUG1_DBG_ADDRESS 0xf | ||
| 282 | #define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) (((v) << 0) & 0xf) | ||
| 283 | |||
| 284 | /** | ||
| 285 | * Register: HW_USBPHY_VERSION | ||
| 286 | * Address: 0x80 | ||
| 287 | * SCT: no | ||
| 288 | */ | ||
| 289 | #define HW_USBPHY_VERSION (*(volatile unsigned long *)(REGS_USBPHY_BASE + 0x80)) | ||
| 290 | #define BP_USBPHY_VERSION_MAJOR 24 | ||
| 291 | #define BM_USBPHY_VERSION_MAJOR 0xff000000 | ||
| 292 | #define BF_USBPHY_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
| 293 | #define BP_USBPHY_VERSION_MINOR 16 | ||
| 294 | #define BM_USBPHY_VERSION_MINOR 0xff0000 | ||
| 295 | #define BF_USBPHY_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
| 296 | #define BP_USBPHY_VERSION_STEP 0 | ||
| 297 | #define BM_USBPHY_VERSION_STEP 0xffff | ||
| 298 | #define BF_USBPHY_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
| 299 | |||
| 300 | #endif /* __HEADERGEN__STMP3700__USBPHY__H__ */ | ||