Merge the Gigabeat S branch back into trunk. Fingers crossed nothing breaks.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14805 a1c6a512-1295-4272-9138-f99709370657

57 files changed, 4016 insertions, 17 deletions

diff --git a/apps/SOURCES b/apps/SOURCES
index 04d9e76c51..5a3dc89c2e 100644
--- a/apps/SOURCES
+++ b/apps/SOURCES
@@ -143,6 +143,8 @@ keymaps/keymap-player.c
 keymaps/keymap-x5.c
 #elif CONFIG_KEYPAD == GIGABEAT_PAD
 keymaps/keymap-gigabeat.c
+#elif CONFIG_KEYPAD == GIGABEAT_S_PAD
+keymaps/keymap-gigabeat-s.c
 #elif CONFIG_KEYPAD == IRIVER_H10_PAD
 keymaps/keymap-h10.c
 #elif CONFIG_KEYPAD == IRIVER_IFP7XX_PAD
diff --git a/apps/keymaps/keymap-gigabeat-s.c b/apps/keymaps/keymap-gigabeat-s.c
new file mode 100644
index 0000000000..2458976425
--- /dev/null
+++ b/apps/keymaps/keymap-gigabeat-s.c
@@ -0,0 +1,315 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 Jonathan Gordon
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Button Code Definitions for the toshiba gigabeat target */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "config.h"
+#include "action.h"
+#include "button.h"
+#include "settings.h"
+
+/*
+ * The format of the list is as follows
+ * { Action Code,   Button code,    Prereq button code }
+ * if there's no need to check the previous button's value, use BUTTON_NONE
+ * Insert LAST_ITEM_IN_LIST at the end of each mapping
+ */
+
+/* CONTEXT_CUSTOM's used in this file...
+
+CONTEXT_CUSTOM|CONTEXT_TREE = the standard list/tree defines (without directions)
+CONTEXT_CUSTOM|CONTEXT_SETTINGS = the direction keys for the eq/col picker screens
+                                  i.e where up/down is inc/dec
+               CONTEXT_SETTINGS = up/down is prev/next, l/r is inc/dec
+
+*/
+
+
+static const struct button_mapping button_context_standard[]  = {
+    { ACTION_STD_PREV,          BUTTON_UP,                  BUTTON_NONE },
+    { ACTION_STD_PREVREPEAT,    BUTTON_UP|BUTTON_REPEAT,    BUTTON_NONE },
+    { ACTION_STD_NEXT,          BUTTON_DOWN,                BUTTON_NONE },
+    { ACTION_STD_NEXTREPEAT,    BUTTON_DOWN|BUTTON_REPEAT,  BUTTON_NONE },
+
+    { ACTION_STD_CANCEL,        BUTTON_LEFT,                BUTTON_NONE },
+    { ACTION_STD_CANCEL,        BUTTON_POWER,               BUTTON_NONE },
+
+    { ACTION_STD_CONTEXT,       BUTTON_SELECT|BUTTON_REPEAT,BUTTON_SELECT },
+
+    { ACTION_STD_QUICKSCREEN,   BUTTON_MENU|BUTTON_REPEAT,  BUTTON_MENU },
+    { ACTION_STD_MENU,          BUTTON_MENU|BUTTON_REL,     BUTTON_MENU },
+
+    { ACTION_STD_OK,            BUTTON_SELECT|BUTTON_REL,   BUTTON_SELECT },
+    { ACTION_STD_OK,            BUTTON_RIGHT,               BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST
+}; /* button_context_standard */
+
+
+static const struct button_mapping button_context_wps[]  = {
+    { ACTION_WPS_PLAY,          BUTTON_SELECT|BUTTON_REL,           BUTTON_SELECT },
+    { ACTION_WPS_STOP,          BUTTON_POWER|BUTTON_REL,          BUTTON_POWER },
+
+    { ACTION_WPS_SKIPNEXT,      BUTTON_RIGHT|BUTTON_REL,        BUTTON_RIGHT },
+    { ACTION_WPS_SKIPPREV,      BUTTON_LEFT|BUTTON_REL,         BUTTON_LEFT },
+
+    { ACTION_WPS_SEEKBACK,      BUTTON_LEFT|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_WPS_SEEKFWD,       BUTTON_RIGHT|BUTTON_REPEAT,     BUTTON_NONE },
+    { ACTION_WPS_STOPSEEK,      BUTTON_LEFT|BUTTON_REL,         BUTTON_LEFT|BUTTON_REPEAT },
+    { ACTION_WPS_STOPSEEK,      BUTTON_RIGHT|BUTTON_REL,        BUTTON_RIGHT|BUTTON_REPEAT },
+
+    { ACTION_WPS_ABSETB_NEXTDIR,       BUTTON_BACK|BUTTON_RIGHT,         BUTTON_BACK },
+    { ACTION_WPS_ABSETA_PREVDIR,       BUTTON_BACK|BUTTON_LEFT,          BUTTON_BACK },
+    { ACTION_WPS_ABRESET,       BUTTON_BACK|BUTTON_SELECT,        BUTTON_BACK },
+
+    { ACTION_WPS_VOLDOWN,       BUTTON_DOWN|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_WPS_VOLDOWN,       BUTTON_DOWN,                    BUTTON_NONE },
+    { ACTION_WPS_VOLDOWN,       BUTTON_VOL_DOWN,                BUTTON_NONE },
+    { ACTION_WPS_VOLDOWN,       BUTTON_VOL_DOWN|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_WPS_VOLUP,         BUTTON_UP|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_WPS_VOLUP,         BUTTON_UP,                      BUTTON_NONE },
+    { ACTION_WPS_VOLUP,         BUTTON_VOL_UP|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_WPS_VOLUP,         BUTTON_VOL_UP,                      BUTTON_NONE },
+
+    { ACTION_WPS_PITCHSCREEN,   BUTTON_BACK|BUTTON_UP,            BUTTON_BACK },
+    { ACTION_WPS_PITCHSCREEN,   BUTTON_BACK|BUTTON_DOWN,          BUTTON_BACK },
+
+    { ACTION_WPS_QUICKSCREEN,   BUTTON_MENU|BUTTON_REPEAT,      BUTTON_MENU },
+    { ACTION_WPS_MENU,          BUTTON_MENU|BUTTON_REL,         BUTTON_MENU },
+    { ACTION_WPS_CONTEXT,       BUTTON_SELECT|BUTTON_REPEAT,    BUTTON_SELECT },
+
+    { ACTION_WPS_ID3SCREEN,     BUTTON_BACK|BUTTON_MENU,          BUTTON_NONE },
+    { ACTION_WPS_BROWSE,        BUTTON_BACK|BUTTON_REL,       BUTTON_BACK },
+
+    LAST_ITEM_IN_LIST
+}; /* button_context_wps */
+
+static const struct button_mapping button_context_list[]  = {
+    { ACTION_LISTTREE_PGUP,         BUTTON_BACK|BUTTON_UP,                    BUTTON_BACK },
+    { ACTION_LISTTREE_PGUP,         BUTTON_UP|BUTTON_REL,                   BUTTON_BACK|BUTTON_UP },
+    { ACTION_LISTTREE_PGUP,         BUTTON_BACK|BUTTON_UP|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_LISTTREE_PGDOWN,       BUTTON_BACK|BUTTON_DOWN,                  BUTTON_BACK },
+    { ACTION_LISTTREE_PGDOWN,       BUTTON_DOWN|BUTTON_REL,                 BUTTON_BACK|BUTTON_DOWN },
+    { ACTION_LISTTREE_PGDOWN,       BUTTON_BACK|BUTTON_DOWN|BUTTON_REPEAT,    BUTTON_NONE },
+#ifdef HAVE_VOLUME_IN_LIST
+    { ACTION_LIST_VOLUP,         BUTTON_VOL_UP|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_LIST_VOLUP,         BUTTON_VOL_UP,                      BUTTON_NONE },
+    { ACTION_LIST_VOLDOWN,       BUTTON_VOL_DOWN,                    BUTTON_NONE },
+    { ACTION_LIST_VOLDOWN,       BUTTON_VOL_DOWN|BUTTON_REPEAT,      BUTTON_NONE },
+#endif
+    
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_list */
+
+static const struct button_mapping button_context_tree[]  = {
+    { ACTION_TREE_WPS,    BUTTON_BACK|BUTTON_REL,         BUTTON_BACK },
+    { ACTION_TREE_STOP,   BUTTON_POWER,                   BUTTON_NONE },
+    { ACTION_TREE_STOP,   BUTTON_POWER|BUTTON_REL,        BUTTON_POWER },
+    { ACTION_TREE_STOP,   BUTTON_POWER|BUTTON_REPEAT,     BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST)
+}; /* button_context_tree */
+
+static const struct button_mapping button_context_listtree_scroll_with_combo[]  = {
+    { ACTION_NONE,              BUTTON_BACK,                              BUTTON_NONE },
+    { ACTION_TREE_PGLEFT,       BUTTON_BACK|BUTTON_LEFT,                  BUTTON_BACK },
+    { ACTION_TREE_PGLEFT,       BUTTON_LEFT|BUTTON_REL,                 BUTTON_BACK|BUTTON_LEFT },
+    { ACTION_TREE_PGLEFT,       BUTTON_BACK|BUTTON_LEFT,                  BUTTON_LEFT|BUTTON_REL },
+    { ACTION_TREE_ROOT_INIT,    BUTTON_BACK|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_BACK|BUTTON_LEFT },
+    { ACTION_TREE_PGLEFT,       BUTTON_BACK|BUTTON_LEFT|BUTTON_REPEAT,    BUTTON_NONE },
+    { ACTION_TREE_PGRIGHT,      BUTTON_BACK|BUTTON_RIGHT,                 BUTTON_BACK },
+    { ACTION_TREE_PGRIGHT,      BUTTON_RIGHT|BUTTON_REL,                BUTTON_BACK|BUTTON_RIGHT },
+    { ACTION_TREE_PGRIGHT,      BUTTON_BACK|BUTTON_RIGHT,                 BUTTON_RIGHT|BUTTON_REL },
+    { ACTION_TREE_PGRIGHT,      BUTTON_BACK|BUTTON_RIGHT|BUTTON_REPEAT,   BUTTON_NONE },
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE),
+};
+
+static const struct button_mapping button_context_listtree_scroll_without_combo[]  = {
+    { ACTION_NONE,              BUTTON_LEFT,                BUTTON_NONE },
+    { ACTION_STD_CANCEL,        BUTTON_LEFT|BUTTON_REL,     BUTTON_LEFT },
+    { ACTION_TREE_ROOT_INIT,    BUTTON_LEFT|BUTTON_REPEAT,  BUTTON_LEFT },
+    { ACTION_TREE_PGLEFT,       BUTTON_LEFT|BUTTON_REPEAT,  BUTTON_NONE },
+    { ACTION_TREE_PGLEFT,       BUTTON_LEFT|BUTTON_REL,     BUTTON_LEFT|BUTTON_REPEAT },
+    { ACTION_NONE,              BUTTON_RIGHT,               BUTTON_NONE },
+    { ACTION_STD_OK,            BUTTON_RIGHT|BUTTON_REL,    BUTTON_RIGHT },
+    { ACTION_TREE_PGRIGHT,      BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+    { ACTION_TREE_PGRIGHT,      BUTTON_RIGHT|BUTTON_REL,    BUTTON_RIGHT|BUTTON_REPEAT },
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE),
+};
+
+static const struct button_mapping button_context_settings[]  = {
+    { ACTION_SETTINGS_INC,          BUTTON_UP,                      BUTTON_NONE },
+    { ACTION_SETTINGS_INCREPEAT,    BUTTON_UP|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_SETTINGS_DEC,          BUTTON_DOWN,                    BUTTON_NONE },
+    { ACTION_SETTINGS_DECREPEAT,    BUTTON_DOWN|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_STD_PREV,              BUTTON_LEFT,                    BUTTON_NONE },
+    { ACTION_STD_PREVREPEAT,        BUTTON_LEFT|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_STD_NEXT,              BUTTON_RIGHT,                   BUTTON_NONE },
+    { ACTION_STD_NEXTREPEAT,        BUTTON_RIGHT|BUTTON_REPEAT,     BUTTON_NONE },
+    { ACTION_SETTINGS_RESET,        BUTTON_BACK,                      BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settings */
+
+static const struct button_mapping button_context_settings_right_is_inc[]  = {
+    { ACTION_SETTINGS_INC,          BUTTON_RIGHT,               BUTTON_NONE },
+    { ACTION_SETTINGS_INCREPEAT,    BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+    { ACTION_SETTINGS_DEC,          BUTTON_LEFT,                BUTTON_NONE },
+    { ACTION_SETTINGS_DECREPEAT,    BUTTON_LEFT|BUTTON_REPEAT,  BUTTON_NONE },
+    { ACTION_STD_PREV,              BUTTON_UP,                  BUTTON_NONE },
+    { ACTION_STD_PREVREPEAT,        BUTTON_UP|BUTTON_REPEAT,    BUTTON_NONE },
+    { ACTION_STD_NEXT,              BUTTON_DOWN,                BUTTON_NONE },
+    { ACTION_STD_NEXTREPEAT,        BUTTON_DOWN|BUTTON_REPEAT,  BUTTON_NONE },
+    { ACTION_SETTINGS_RESET,        BUTTON_BACK,                  BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settingsgraphical */
+
+static const struct button_mapping button_context_yesno[]  = {
+    { ACTION_YESNO_ACCEPT,          BUTTON_SELECT,                  BUTTON_NONE },
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settings_yesno */
+
+static const struct button_mapping button_context_colorchooser[]  = {
+    { ACTION_STD_OK,            BUTTON_BACK|BUTTON_REL,   BUTTON_NONE },
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS),
+}; /* button_context_colorchooser */
+
+static const struct button_mapping button_context_eq[]  = {
+    { ACTION_STD_OK,            BUTTON_SELECT|BUTTON_REL,   BUTTON_NONE },
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS),
+}; /* button_context_eq */
+
+/** Bookmark Screen **/
+static const struct button_mapping button_context_bmark[]  = {
+    { ACTION_BMS_DELETE,       BUTTON_BACK, BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST),
+}; /* button_context_bmark */
+
+static const struct button_mapping button_context_time[]  = {
+    { ACTION_STD_CANCEL,       BUTTON_POWER,  BUTTON_NONE },
+    { ACTION_STD_OK,           BUTTON_BACK,   BUTTON_NONE },
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_SETTINGS),
+}; /* button_context_time */
+
+static const struct button_mapping button_context_quickscreen[]  = {
+    { ACTION_QS_DOWNINV,    BUTTON_UP,                      BUTTON_NONE },
+    { ACTION_QS_DOWNINV,    BUTTON_UP|BUTTON_REPEAT,        BUTTON_NONE },
+    { ACTION_QS_DOWN,       BUTTON_DOWN,                    BUTTON_NONE },
+    { ACTION_QS_DOWN,       BUTTON_DOWN|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_QS_LEFT,       BUTTON_LEFT,                    BUTTON_NONE },
+    { ACTION_QS_LEFT,       BUTTON_LEFT|BUTTON_REPEAT,      BUTTON_NONE },
+    { ACTION_QS_RIGHT,      BUTTON_RIGHT,                   BUTTON_NONE },
+    { ACTION_QS_RIGHT,      BUTTON_RIGHT|BUTTON_REPEAT,     BUTTON_NONE },
+    { ACTION_STD_CANCEL,    BUTTON_MENU,                    BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_quickscreen */
+
+static const struct button_mapping button_context_pitchscreen[]  = {
+    { ACTION_PS_INC_SMALL,      BUTTON_UP,                  BUTTON_NONE },
+    { ACTION_PS_INC_BIG,        BUTTON_UP|BUTTON_REPEAT,    BUTTON_NONE },
+    { ACTION_PS_DEC_SMALL,      BUTTON_DOWN,                BUTTON_NONE },
+    { ACTION_PS_DEC_BIG,        BUTTON_DOWN|BUTTON_REPEAT,  BUTTON_NONE },
+    { ACTION_PS_NUDGE_LEFT,     BUTTON_LEFT,                BUTTON_NONE },
+    { ACTION_PS_NUDGE_LEFTOFF,  BUTTON_LEFT|BUTTON_REL,     BUTTON_NONE },
+    { ACTION_PS_NUDGE_RIGHT,    BUTTON_RIGHT,               BUTTON_NONE },
+    { ACTION_PS_NUDGE_RIGHTOFF, BUTTON_RIGHT|BUTTON_REL,    BUTTON_NONE },
+    { ACTION_PS_TOGGLE_MODE,    BUTTON_MENU,                BUTTON_NONE },
+    { ACTION_PS_RESET,          BUTTON_BACK,               BUTTON_NONE },
+    { ACTION_PS_EXIT,           BUTTON_POWER,                   BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_pitchcreen */
+
+static const struct button_mapping button_context_keyboard[]  = {
+    { ACTION_KBD_LEFT,         BUTTON_LEFT,                             BUTTON_NONE },
+    { ACTION_KBD_LEFT,         BUTTON_LEFT|BUTTON_REPEAT,               BUTTON_NONE },
+    { ACTION_KBD_RIGHT,        BUTTON_RIGHT,                            BUTTON_NONE },
+    { ACTION_KBD_RIGHT,        BUTTON_RIGHT|BUTTON_REPEAT,              BUTTON_NONE },
+    { ACTION_KBD_CURSOR_LEFT,  BUTTON_BACK|BUTTON_LEFT,                BUTTON_NONE },
+    { ACTION_KBD_CURSOR_LEFT,  BUTTON_BACK|BUTTON_LEFT|BUTTON_REPEAT,  BUTTON_NONE },
+    { ACTION_KBD_CURSOR_RIGHT, BUTTON_BACK|BUTTON_RIGHT,               BUTTON_NONE },
+    { ACTION_KBD_CURSOR_RIGHT, BUTTON_BACK|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+    { ACTION_KBD_SELECT,       BUTTON_SELECT,                           BUTTON_NONE },
+    { ACTION_KBD_PAGE_FLIP,    BUTTON_BACK|BUTTON_MENU,                BUTTON_NONE },
+    { ACTION_KBD_DONE,         BUTTON_BACK|BUTTON_REL,                 BUTTON_BACK },
+    { ACTION_KBD_ABORT,        BUTTON_POWER|BUTTON_REL,                     BUTTON_POWER },
+    { ACTION_KBD_BACKSPACE,    BUTTON_MENU,                             BUTTON_NONE },
+    { ACTION_KBD_BACKSPACE,    BUTTON_MENU|BUTTON_REPEAT,               BUTTON_NONE },
+    { ACTION_KBD_UP,           BUTTON_UP,                               BUTTON_NONE },
+    { ACTION_KBD_UP,           BUTTON_UP|BUTTON_REPEAT,                 BUTTON_NONE },
+    { ACTION_KBD_DOWN,         BUTTON_DOWN,                             BUTTON_NONE },
+    { ACTION_KBD_DOWN,         BUTTON_DOWN|BUTTON_REPEAT,               BUTTON_NONE },
+    { ACTION_KBD_MORSE_INPUT,  BUTTON_BACK|BUTTON_POWER,                   BUTTON_NONE },
+    { ACTION_KBD_MORSE_SELECT, BUTTON_SELECT|BUTTON_REL,                BUTTON_NONE },
+
+    LAST_ITEM_IN_LIST
+}; /* button_context_keyboard */
+
+const struct button_mapping* get_context_mapping(int context)
+{
+    switch (context)
+    {
+        case CONTEXT_STD:
+            return button_context_standard;
+        case CONTEXT_WPS:
+            return button_context_wps;
+
+        case CONTEXT_LIST:
+            return button_context_list;
+        case CONTEXT_MAINMENU:
+        case CONTEXT_TREE:
+            if (global_settings.hold_lr_for_scroll_in_list)
+                return button_context_listtree_scroll_without_combo;
+            else
+                return button_context_listtree_scroll_with_combo;
+        case CONTEXT_CUSTOM|CONTEXT_TREE:
+            return button_context_tree;
+
+        case CONTEXT_SETTINGS:
+            return button_context_settings;
+        case CONTEXT_CUSTOM|CONTEXT_SETTINGS:
+            return button_context_settings_right_is_inc;
+
+        case CONTEXT_SETTINGS_COLOURCHOOSER:
+            return button_context_colorchooser;
+        case CONTEXT_SETTINGS_EQ:
+            return button_context_eq;
+
+        case CONTEXT_SETTINGS_TIME:
+            return button_context_time;
+
+        case CONTEXT_YESNOSCREEN:
+            return button_context_yesno;
+        case CONTEXT_BOOKMARKSCREEN:
+            return button_context_bmark;
+        case CONTEXT_QUICKSCREEN:
+            return button_context_quickscreen;
+        case CONTEXT_PITCHSCREEN:
+            return button_context_pitchscreen;
+        case CONTEXT_KEYBOARD:
+            return button_context_keyboard;
+    }
+    return button_context_standard;
+}
diff --git a/apps/plugins/SOURCES b/apps/plugins/SOURCES
index 8479cd8b9b..d581906637 100644
--- a/apps/plugins/SOURCES
+++ b/apps/plugins/SOURCES
@@ -1,3 +1,4 @@
+#ifndef GIGABEAT_S
 /* plugins common to all models */
 battery_bench.c
 chessclock.c
@@ -13,6 +14,7 @@ random_folder_advance_config.c
 rockblox.c
 rockbox_flash.c
 search.c
+shortcuts.c
 snow.c
 sort.c
 stats.c
@@ -144,3 +146,4 @@ iriver_flash.c
 /* Built for bitmap targets except H10 5/6gb, Archoses, iPod mini and ifp */
 superdom.c
 #endif
+#endif /* GIGABEAT_S */
diff --git a/apps/plugins/SUBDIRS b/apps/plugins/SUBDIRS
index f537fb8965..24333be3b9 100644
--- a/apps/plugins/SUBDIRS
+++ b/apps/plugins/SUBDIRS
@@ -1,4 +1,5 @@
 #ifndef IRIVER_IFP7XX_SERIES
+#ifndef GIGABEAT_S
 
 /* For all targets */
 shortcuts
@@ -45,4 +46,5 @@ doom
 mpegplayer
 #endif
 
+#endif /* GIGABEAT_S */
 #endif /* IRIVER_IFP7XX_SERIES */
diff --git a/apps/plugins/plugin.lds b/apps/plugins/plugin.lds
index f38f60656a..6b4310c0b7 100644
--- a/apps/plugins/plugin.lds
+++ b/apps/plugins/plugin.lds
@@ -43,6 +43,10 @@ OUTPUT_FORMAT(elf32-sh)
 #define IRAMORIG DRAMORIG
 #define IRAMSIZE 4K
 #define IRAM DRAM
+#elif CONFIG_CPU == IMX31L
+#define DRAMORIG 0x80000000
+#define IRAMORIG 0x1FFFC000
+#define IRAMSIZE 0x4000
 #else
 #define DRAMORIG 0x09000000 + STUBOFFSET
 #endif
diff --git a/bootloader/SOURCES b/bootloader/SOURCES
index 2b499c1944..919e002f1b 100644
--- a/bootloader/SOURCES
+++ b/bootloader/SOURCES
@@ -4,6 +4,9 @@ common.c
 ipod.c
 #elif defined(GIGABEAT_F)
 gigabeat.c
+#elif defined(GIGABEAT_S)
+gigabeat-s.c
+../firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c
 #elif defined(IRIVER_H10) || defined(IRIVER_H10_5GB) || \
       defined(SANSA_E200) || defined(SANSA_C200)
 #ifdef E200R_INSTALLER
diff --git a/bootloader/gigabeat-s.c b/bootloader/gigabeat-s.c
new file mode 100644
index 0000000000..25b9ab5f35
--- /dev/null
+++ b/bootloader/gigabeat-s.c
@@ -0,0 +1,94 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Greg White
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "inttypes.h"
+#include "string.h"
+#include "cpu.h"
+#include "system.h"
+#include "lcd.h"
+#include "kernel.h"
+#include "thread.h"
+#include "ata.h"
+#include "fat.h"
+#include "disk.h"
+#include "font.h"
+#include "adc.h"
+#include "backlight.h"
+#include "backlight-target.h"
+#include "button.h"
+#include "panic.h"
+#include "power.h"
+#include "file.h"
+#include "common.h"
+#include "rbunicode.h"
+#include "usb.h"
+#include "mmu-imx31.h"
+#include "lcd-target.h"
+#include "avic-imx31.h"
+#include <stdarg.h>
+
+char version[] = APPSVERSION;
+
+void main(void)
+{
+    lcd_clear_display();
+    printf("Hello world!");
+    printf("Gigabeat S Rockbox Bootloader v.00000001");          
+    kernel_init();
+    int rc;
+
+    rc = ata_init();
+    if(rc)
+    {
+        reset_screen();
+        error(EATA, rc);
+    }
+
+    disk_init();
+
+    rc = disk_mount_all();
+    if (rc<=0)
+    {
+        error(EDISK,rc);
+    }
+
+    printf("Congratulations!");
+    while(1);
+
+#if 0
+    printf("Loading firmware");
+
+    loadbuffer = (unsigned char*) 0x100;
+    buffer_size = (unsigned char*)0x400000 - loadbuffer;
+
+    rc = load_firmware(loadbuffer, BOOTFILE, buffer_size);
+    if(rc < 0)
+        error(EBOOTFILE, rc);
+
+    if (rc == EOK)
+    {
+        kernel_entry = (void*) loadbuffer;
+        rc = kernel_entry();
+    }
+#endif
+}
+
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 3a606e5bfd..92e2c1d8c5 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -588,6 +588,31 @@ target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
 #endif /* SIMULATOR */
 #endif /* GIGABEAT_F */
 
+#ifdef GIGABEAT_S
+#ifndef SIMULATOR
+target/arm/imx31/gigabeat-s/adc-imx31.c
+target/arm/imx31/gigabeat-s/ata-imx31.c
+target/arm/imx31/gigabeat-s/backlight-imx31.c
+target/arm/imx31/gigabeat-s/button-imx31.c
+target/arm/imx31/gigabeat-s/i2c-imx31.c
+target/arm/imx31/gigabeat-s/i2s-imx31.c
+target/arm/imx31/gigabeat-s/lcd-as-imx31.S
+target/arm/imx31/gigabeat-s/lcd-imx31.c
+target/arm/imx31/gigabeat-s/power-imx31.c
+target/arm/imx31/gigabeat-s/powermgmt-imx31.c
+target/arm/imx31/gigabeat-s/usb-imx31.c
+target/arm/imx31/gigabeat-s/wmcodec-imx31.c
+target/arm/imx31/gigabeat-s/dma_start.c
+target/arm/imx31/gigabeat-s/system-imx31.c
+target/arm/imx31/gigabeat-s/mmu-imx31.c
+target/arm/imx31/gigabeat-s/avic-imx31.c
+target/arm/imx31/gigabeat-s/spi-imx31.c
+#ifndef BOOTLOADER
+target/arm/imx31/gigabeat-fx/pcm-imx31.c
+#endif
+#endif /* SIMULATOR */
+#endif /* GIGABEAT_S */
+
 #ifdef MROBE_500
 #ifndef SIMULATOR
 target/arm/olympus/mrobe-500/adc-mr500.c
diff --git a/firmware/app.lds b/firmware/app.lds
index 998ac40791..6c67a96481 100644
--- a/firmware/app.lds
+++ b/firmware/app.lds
@@ -60,6 +60,10 @@ INPUT(target/sh/crt0.o)
 #define DRAMORIG 0x00900000 + STUBOFFSET
 #define IRAMORIG 0x00000000
 #define IRAMSIZE 0x4000
+#elif CONFIG_CPU==IMX31L
+#define DRAMORIG (0x80000000 + STUBOFFSET)
+#define IRAMORIG 0x1FFFC000
+#define IRAMSIZE 0x4000
 #else
 #define DRAMORIG 0x09000000 + STUBOFFSET
 #define IRAMORIG 0x0f000000
diff --git a/firmware/boot.lds b/firmware/boot.lds
index 0e2ccc1b90..999e1b0f26 100644
--- a/firmware/boot.lds
+++ b/firmware/boot.lds
@@ -69,6 +69,12 @@ INPUT(target/sh/crt0.o)
 #define IRAMSIZE 0x18000
 #define FLASHORIG 0x001f0000
 #define FLASHSIZE 2M
+#elif CONFIG_CPU == IMX31L
+#define DRAMORIG 0x80000000
+#define IRAMORIG 0x1FFFC000
+#define IRAMSIZE 16K
+#define FLASHORIG 0x0000000
+#define FLASHSIZE 1M
 #else
 #define DRAMORIG 0x09000000
 #define IRAMORIG 0x0f000000
@@ -77,7 +83,7 @@ INPUT(target/sh/crt0.o)
 #define FLASHSIZE 256K - ROM_START
 #endif
 
-#if !defined(CPU_PP) && (CONFIG_CPU!=S3C2440)
+#if !defined(CPU_PP) && (CONFIG_CPU!=S3C2440) && (CONFIG_CPU!=IMX31L)
 MEMORY
 {
    DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
@@ -216,6 +222,41 @@ SECTIONS
          _end = .;
      }>DRAM
 }
+#elif (CONFIG_CPU==IMX31L)
+{
+  . = 0x88201000;
+  .vectors : 
+  {  
+    KEEP(*(.vectors*));
+    *(.vectors*);
+  }  
+  .text : {
+    *(.init.text)
+    *(.text*)
+  }
+  .data : {
+    *(.icode)
+    *(.irodata)
+    *(.idata)
+    *(.data*)
+    _dataend = . ;
+   }
+  .stack :
+  {
+     *(.stack)
+     _stackbegin = .;
+     stackbegin = .;
+     . += 0x2000;
+     _stackend = .;
+     stackend = .;
+  }
+  .bss : {
+     _edata = .;
+     *(.bss*);
+     *(.ibss);
+     _end = .;
+   }
+}
 #else
 {
     .vectors :
diff --git a/firmware/drivers/lcd-16bit.c b/firmware/drivers/lcd-16bit.c
index bd5d09368c..96a9e1a4d7 100644
--- a/firmware/drivers/lcd-16bit.c
+++ b/firmware/drivers/lcd-16bit.c
@@ -668,7 +668,8 @@ void lcd_bitmap(const fb_data *src, int x, int y, int width, int height)
     lcd_bitmap_part(src, 0, 0, width, x, y, width, height);
 }
 
-#if !defined(TOSHIBA_GIGABEAT_F) || defined(SIMULATOR)
+#if !defined(TOSHIBA_GIGABEAT_F) && !defined(TOSHIBA_GIGABEAT_S) \
+    || defined(SIMULATOR)
 /* Draw a partial native bitmap */
 void lcd_bitmap_transparent_part(const fb_data *src, int src_x, int src_y,
                                  int stride, int x, int y, int width,
diff --git a/firmware/export/audiohw.h b/firmware/export/audiohw.h
index df155e2256..ec0177d091 100644
--- a/firmware/export/audiohw.h
+++ b/firmware/export/audiohw.h
@@ -27,7 +27,7 @@
 #include "uda1380.h"
 #elif defined(HAVE_WM8751)
 #include "wm8751.h"
-#elif defined(HAVE_WM8975)
+#elif defined(HAVE_WM8975) || defined(HAVE_WM8978)
 #include "wm8975.h"
 #elif defined(HAVE_WM8758)
 #include "wm8758.h"
@@ -60,7 +60,7 @@ enum {
 #endif
 #if CONFIG_CODEC == MAS3587F || defined(HAVE_UDA1380) || defined(HAVE_TLV320)\
     || defined(HAVE_WM8975) || defined(HAVE_WM8758) || defined(HAVE_WM8731) \
-    || defined(HAVE_AS3514)
+    || defined(HAVE_AS3514) || defined(HAVE_WM8978)
     SOUND_LEFT_GAIN,
     SOUND_RIGHT_GAIN,
     SOUND_MIC_GAIN,
diff --git a/firmware/export/config-gigabeat-s.h b/firmware/export/config-gigabeat-s.h
new file mode 100644
index 0000000000..285b381480
--- /dev/null
+++ b/firmware/export/config-gigabeat-s.h
@@ -0,0 +1,139 @@
+/*
+ * This config file is for toshiba Gigabeat S
+ */
+#define TARGET_TREE /* this target is using the target tree system */
+
+#define TOSHIBA_GIGABEAT_S 1
+
+/* For Rolo and boot loader */
+#define MODEL_NUMBER 19
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you have a colour LCD */
+#define HAVE_LCD_COLOR
+
+/* define this if you have access to the quickscreen */
+#define HAVE_QUICKSCREEN
+
+/* define this if you have access to the pitchscreen */
+#define HAVE_PITCHSCREEN
+
+/* define this if you would like tagcache to build on this target */
+#define HAVE_TAGCACHE
+
+/* define this if the target has volume keys which can be used in the lists */
+#define HAVE_VOLUME_IN_LIST
+
+/* LCD dimensions */
+#define LCD_WIDTH  240
+#define LCD_HEIGHT 320
+#define LCD_DEPTH  16   /* 65k colours */
+#define LCD_PIXELFORMAT RGB565 /* rgb565 */
+
+#define CONFIG_KEYPAD GIGABEAT_S_PAD
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+
+/* define this if you have a real-time clock */
+//#define CONFIG_RTC RTC_IMX31L
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+
+#define HAVE_LCD_ENABLE
+
+//#define HAVE_BACKLIGHT_BRIGHTNESS
+
+/* Main LCD backlight brightness range and defaults */
+#define MIN_BRIGHTNESS_SETTING          0   /* 0.5 mA */
+#define MAX_DIM_BRIGHTNESS_SETTING      15  /* highest 'dimness' */
+#define MAX_BRIGHTNESS_SETTING          63  /* 32 mA */
+#define DEFAULT_BRIGHTNESS_SETTING      39  /* 20 mA */
+#define DEFAULT_DIMNESS_SETTING          9  /* 5 mA */
+
+/* Define this if you have a software controlled poweroff */
+#define HAVE_SW_POWEROFF
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x80000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x80000
+
+/* Define this if you have the WM8975 audio codec */
+#define HAVE_WM8978
+
+
+#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \
+                       SAMPR_CAP_11)
+
+#ifndef SIMULATOR
+
+/* The LCD on a Gigabeat is 240x320 - it is portrait */
+#define HAVE_PORTRAIT_LCD
+
+#define CONFIG_CPU IMX31L
+
+/* Define this if you want to use coldfire's i2c interface */
+#define CONFIG_I2C I2C_IMX31L
+
+/* Type of mobile power - check this out */
+#define BATTERY_CAPACITY_DEFAULT 2000 /* default battery capacity */
+#define BATTERY_CAPACITY_MIN 1500        /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX 2500        /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC 25         /* capacity increment */
+#define BATTERY_TYPES_COUNT  1          /* only one type */
+
+/* Hardware controlled charging with monitoring */
+#define CONFIG_CHARGING CHARGING_MONITOR
+
+/* define this if the hardware can be powered off while charging */
+#define HAVE_POWEROFF_WHILE_CHARGING
+
+/* The size of the flash ROM */
+#define FLASH_SIZE 0x400000
+
+/* Define this to the CPU frequency */
+/* TODO */
+#define CPU_FREQ 16934400
+
+/* define this if the unit can be powered or charged via USB */
+#define HAVE_USB_POWER
+
+/* Define this if you have ATA power-off control */
+#define HAVE_ATA_POWER_OFF
+
+/* Virtual LED (icon) */
+#define CONFIG_LED LED_VIRTUAL
+
+#define CONFIG_LCD LCD_GIGABEAT
+
+/* define this if the backlight can be set to a brightness */
+//#define HAVE_BACKLIGHT_SET_FADING
+#define __BACKLIGHT_INIT
+
+/* Offset ( in the firmware file's header ) to the file CRC */
+#define FIRMWARE_OFFSET_FILE_CRC 0
+
+/* Offset ( in the firmware file's header ) to the real data */
+#define FIRMWARE_OFFSET_FILE_DATA 8
+
+#define HAVE_SERIAL
+
+/*Remove Comments from UART_INT to enable the UART interrupts,*/
+/*otherwise iterrupts will be disabled. For now we will test */
+/*UART state by polling the registers, and if necessary update this */
+/*method by using the interrupts instead*/
+//#define UART_INT
+
+/* Define this if you have adjustable CPU frequency */
+/* #define HAVE_ADJUSTABLE_CPU_FREQ */
+
+#define BOOTFILE_EXT "gigabeat"
+#define BOOTFILE "rockbox." BOOTFILE_EXT
+#define BOOTDIR "/.rockbox"
+
+#endif
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 4a4185fdc3..40d1c168a3 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -30,6 +30,7 @@
 #define S1A0903X01 0x01 /* Samsung */
 #define TEA5767    0x02 /* Philips */
 #define LV24020LP  0x04 /* Sanyo */
+#define SI4700     0x08 /* Silicon Labs */
 
 /* CONFIG_CODEC */
 #define MAS3587F 3587
@@ -49,6 +50,7 @@
 #define S3C2440      2440
 #define TMS320DSC25    25
 #define DM320         320
+#define IMX31L         31
 
 /* CONFIG_KEYPAD */
 #define PLAYER_PAD          1
@@ -68,6 +70,7 @@
 #define ELIO_TPJ1022_PAD   15
 #define ARCHOS_AV300_PAD   16
 #define MROBE500_PAD       17
+#define GIGABEAT_S_PAD     18
 
 /* CONFIG_REMOTE_KEYPAD */
 #define H100_REMOTE 1
@@ -118,6 +121,7 @@
 #define I2C_PNX0101  6 /* PNX0101 style */
 #define I2C_S3C2440  7
 #define I2C_PP5024   8 /* PP5024 style */
+#define I2C_IMX31L   9
 
 /* CONFIG_LED */
 #define LED_REAL     1 /* SW controlled LED (Archos recorders, player) */
@@ -135,6 +139,7 @@
 #define RTC_E8564    5 /* iriver H10 */
 #define RTC_AS3514   6 /* Sandisk Sansa e200 series */
 #define RTC_DS1339_DS3231   7 /* h1x0 RTC mod */
+#define RTC_IMX31L   8
 
 /* USB On-the-go */
 #define USBOTG_ISP1362 1362 /* iriver H300 */
@@ -186,6 +191,8 @@
 #include "config-ifp7xx.h"
 #elif defined(GIGABEAT_F)
 #include "config-gigabeat.h"
+#elif defined(GIGABEAT_S)
+#include "config-gigabeat-s.h"
 #elif defined(IPOD_MINI)
 #include "config-ipodmini.h"
 #elif defined(IPOD_MINI2G)
@@ -299,7 +306,8 @@
 
 /* define for all cpus from ARM family */
 #if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \
-    || (CONFIG_CPU == TMS320DSC25) || (CONFIG_CPU == DM320)
+    || (CONFIG_CPU == TMS320DSC25) || (CONFIG_CPU == DM320) \
+    || (CONFIG_CPU == IMX31L)
 #define CPU_ARM
 #endif
 
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index ff9fbeec3a..893e7ffaa8 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -45,3 +45,6 @@
 #if CONFIG_CPU == DM320
 #include "dm320.h"
 #endif
+#if CONFIG_CPU == IMX31L
+#include "imx31l.h"
+#endif
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
new file mode 100755
index 0000000000..1fa5e6ba5e
--- /dev/null
+++ b/firmware/export/imx31l.h
@@ -0,0 +1,476 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by James Espinoza
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
+
+#define L2CC_BASE_ADDR          0x30000000
+ 
+/*Frame Buffer and TTB defines from gigabeat f/x build*/
+#define LCDSADDR1 (*(volatile int *)0x80100000) /* STN/TFT: frame buffer start address 1 */
+#define FRAME1 ((short *)0x80100000) //Foreground FB 
+#define FRAME2 ((short *)0x84100000) //Background FB - Set to Graphic Window, hence the reason why text is only visible
+                                                                         //when background memory is written.
+#define LCD_BUFFER_SIZE ((320*240*2))
+#define TTB_SIZE (0x4000)
+#define TTB_BASE (0x80000000 + (32*1024*1024*2)-TTB_SIZE); /*64 megs*/
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR           0x43F04000
+#define EVTMON_BASE_ADDR        0x43F08000
+#define CLKCTL_BASE_ADDR        0x43F0C000
+#define ETB_SLOT4_BASE_ADDR     0x43F10000
+#define ETB_SLOT5_BASE_ADDR     0x43F14000
+#define ECT_CTIO_BASE_ADDR      0x43F18000
+#define I2C_BASE_ADDR           0x43F80000
+#define I2C3_BASE_ADDR          0x43F84000
+#define OTG_BASE_ADDR           0x43F88000
+#define ATA_BASE_ADDR           0x43F8C000
+#define UART1_BASE_ADDR         0x43F90000
+#define UART2_BASE_ADDR         0x43F94000
+#define I2C2_BASE_ADDR          0x43F98000
+#define OWIRE_BASE_ADDR         0x43F9C000
+#define SSI1_BASE_ADDR          0x43FA0000
+#define CSPI1_BASE_ADDR         0x43FA4000
+#define KPP_BASE_ADDR           0x43FA8000
+#define IOMUXC_BASE_ADDR        0x43FAC000
+#define UART4_BASE_ADDR         0x43FB0000
+#define UART5_BASE_ADDR         0x43FB4000
+#define ECT_IP1_BASE_ADDR       0x43FB8000
+#define ECT_IP2_BASE_ADDR       0x43FBC000
+ 
+/*
+ * SPBA
+ */
+#define SPBA_BASE_ADDR          0x50000000
+#define MMC_SDHC1_BASE_ADDR     0x50004000
+#define MMC_SDHC2_BASE_ADDR     0x50008000
+#define UART3_BASE_ADDR         0x5000C000
+#define CSPI2_BASE_ADDR         0x50010000
+#define SSI2_BASE_ADDR          0x50014000
+#define SIM_BASE_ADDR           0x50018000
+#define IIM_BASE_ADDR           0x5001C000
+#define ATA_DMA_BASE_ADDR       0x50020000
+#define SPBA_CTRL_BASE_ADDR     0x5003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR           0x53F80000
+#define FIRI_BASE_ADDR          0x53F8C000
+#define GPT1_BASE_ADDR          0x53F90000
+#define EPIT1_BASE_ADDR         0x53F94000
+#define EPIT2_BASE_ADDR         0x53F98000
+#define GPIO3_BASE_ADDR         0x53FA4000
+#define SCC_BASE                0x53FAC000
+#define SCM_BASE                0x53FAE000
+#define SMN_BASE                0x53FAF000
+#define RNGA_BASE_ADDR          0x53FB0000
+#define IPU_CTRL_BASE_ADDR      0x53FC0000
+#define AUDMUX_BASE             0x53FC4000
+#define MPEG4_ENC_BASE          0x53FC8000
+#define GPIO1_BASE_ADDR         0x53FCC000
+#define GPIO2_BASE_ADDR         0x53FD0000
+#define SDMA_BASE_ADDR          0x53FD4000
+#define RTC_BASE_ADDR           0x53FD8000
+#define WDOG_BASE_ADDR          0x53FDC000
+#define PWM_BASE_ADDR           0x53FE0000
+#define RTIC_BASE_ADDR          0x53FEC000
+
+#define WDOG1_BASE_ADDR       WDOG_BASE_ADDR
+#define CRM_MCU_BASE_ADDR     CCM_BASE_ADDR
+
+/* ATA */
+#define TIME_OFF                (*(volatile unsigned char*)0x43F8C000)
+#define TIME_ON                 (*(volatile unsigned char*)0x43F8C001)
+#define TIME_1                  (*(volatile unsigned char*)0x43F8C002)
+#define TIME_2W                 (*(volatile unsigned char*)0x43F8C003)
+#define TIME_2R                 (*(volatile unsigned char*)0x43F8C004)
+#define TIME_AX                 (*(volatile unsigned char*)0x43F8C005)
+#define TIME_PIO_RDX            (*(volatile unsigned char*)0x43F8C00F)
+#define TIME_4                  (*(volatile unsigned char*)0x43F8C007)
+#define TIME_9                  (*(volatile unsigned char*)0x43F8C008)
+
+/* Timers */
+#define EPITCR1                 (*(volatile long*)EPIT1_BASE_ADDR)
+#define EPITSR1                 (*(volatile long*)(EPIT1_BASE_ADDR+0x04))
+#define EPITLR1                 (*(volatile long*)(EPIT1_BASE_ADDR+0x08))
+#define EPITCMPR1               (*(volatile long*)(EPIT1_BASE_ADDR+0x0C))
+#define EPITCNT1                (*(volatile long*)(EPIT1_BASE_ADDR+0x10))
+#define EPITCR2                 (*(volatile long*)EPIT2_BASE_ADDR)
+#define EPITSR2                 (*(volatile long*)(EPIT2_BASE_ADDR+0x04))
+#define EPITLR2                 (*(volatile long*)(EPIT2_BASE_ADDR+0x08))
+#define EPITCMPR2               (*(volatile long*)(EPIT2_BASE_ADDR+0x0C))
+#define EPITCNT2                (*(volatile long*)(EPIT2_BASE_ADDR+0x10))
+
+/* GPIO */
+#define GPIO1_DR                (*(volatile long*)GPIO1_BASE_ADDR)
+#define GPIO1_GDIR              (*(volatile long*)(GPIO1_BASE_ADDR+0x04))
+#define GPIO1_PSR               (*(volatile long*)(GPIO1_BASE_ADDR+0x08))
+#define GPIO1_ICR1              (*(volatile long*)(GPIO1_BASE_ADDR+0x0C))
+#define GPIO1_ICR2              (*(volatile long*)(GPIO1_BASE_ADDR+0x10))
+#define GPIO1_IMR               (*(volatile long*)(GPIO1_BASE_ADDR+0x14))
+#define GPIO1_ISR               (*(volatile long*)(GPIO1_BASE_ADDR+0x18))
+
+#define GPIO2_DR                (*(volatile long*)GPIO2_BASE_ADDR)
+#define GPIO2_GDIR              (*(volatile long*)(GPIO2_BASE_ADDR+0x04))
+#define GPIO2_PSR               (*(volatile long*)(GPIO2_BASE_ADDR+0x08))
+#define GPIO2_ICR1              (*(volatile long*)(GPIO2_BASE_ADDR+0x0C))
+#define GPIO2_ICR2              (*(volatile long*)(GPIO2_BASE_ADDR+0x10))
+#define GPIO2_IMR               (*(volatile long*)(GPIO2_BASE_ADDR+0x14))
+#define GPIO2_ISR               (*(volatile long*)(GPIO2_BASE_ADDR+0x18))
+
+#define GPIO3_DR                (*(volatile long*)GPIO3_BASE_ADDR)
+#define GPIO3_GDIR              (*(volatile long*)(GPIO3_BASE_ADDR+0x04))
+#define GPIO3_PSR               (*(volatile long*)(GPIO3_BASE_ADDR+0x08))
+#define GPIO3_ICR1              (*(volatile long*)(GPIO3_BASE_ADDR+0x0C))
+#define GPIO3_ICR2              (*(volatile long*)(GPIO3_BASE_ADDR+0x10))
+#define GPIO3_IMR               (*(volatile long*)(GPIO3_BASE_ADDR+0x14))
+#define GPIO3_ISR               (*(volatile long*)(GPIO3_BASE_ADDR+0x18))
+
+/* SPI */
+#define CSPI_RXDATA1            (*(volatile long*)CSPI1_BASE_ADDR)
+#define CSPI_TXDATA1            (*(volatile long*)(CSPI1_BASE_ADDR+0x04))
+#define CSPI_CONREG1            (*(volatile long*)(CSPI1_BASE_ADDR+0x08))
+#define CSPI_INTREG1            (*(volatile long*)(CSPI1_BASE_ADDR+0x0C))
+#define CSPI_DMAREG1            (*(volatile long*)(CSPI1_BASE_ADDR+0x10))
+#define CSPI_STATREG1           (*(volatile long*)(CSPI1_BASE_ADDR+0x14))
+#define CSPI_PERIODREG1         (*(volatile long*)(CSPI1_BASE_ADDR+0x18))
+#define CSPI_TESTREG1           (*(volatile long*)(CSPI1_BASE_ADDR+0x1C0))
+
+#define CSPI_RXDATA2            (*(volatile long*)CSPI2_BASE_ADDR)
+#define CSPI_TXDATA2            (*(volatile long*)(CSPI2_BASE_ADDR+0x04))
+#define CSPI_CONREG2            (*(volatile long*)(CSPI2_BASE_ADDR+0x08))
+#define CSPI_INTREG2            (*(volatile long*)(CSPI2_BASE_ADDR+0x0C))
+#define CSPI_DMAREG2            (*(volatile long*)(CSPI2_BASE_ADDR+0x10))
+#define CSPI_STATREG2           (*(volatile long*)(CSPI2_BASE_ADDR+0x14))
+#define CSPI_PERIODREG2         (*(volatile long*)(CSPI2_BASE_ADDR+0x18))
+#define CSPI_TESTREG2           (*(volatile long*)(CSPI2_BASE_ADDR+0x1C0))
+
+/* RTC */
+#define RTC_HOURMIN             (*(volatile long*)RTC_BASE_ADDR)
+#define RTC_SECONDS             (*(volatile long*)(RTC_BASE_ADDR+0x04))
+#define RTC_ALRM_HM             (*(volatile long*)(RTC_BASE_ADDR+0x08))
+#define RTC_ALRM_SEC            (*(volatile long*)(RTC_BASE_ADDR+0x0C))
+#define RTC_CTL                 (*(volatile long*)(RTC_BASE_ADDR+0x10))
+#define RTC_ISR                 (*(volatile long*)(RTC_BASE_ADDR+0x14))
+#define RTC_IENR                (*(volatile long*)(RTC_BASE_ADDR+0x18))
+#define RTC_STPWCH              (*(volatile long*)(RTC_BASE_ADDR+0x1C))
+#define RTC_DAYR                (*(volatile long*)(RTC_BASE_ADDR+0x20))
+#define RTC_DAYALARM            (*(volatile long*)(RTC_BASE_ADDR+0x24))
+
+/* Keypad */
+#define KPP_KPCR                (*(volatile short*)KPP_BASE_ADDR)
+#define KPP_KPSR                (*(volatile short*)(KPP_BASE_ADDR+0x2))
+#define KPP_KDDR                (*(volatile short*)(KPP_BASE_ADDR+0x4))
+#define KPP_KPDR                (*(volatile short*)(KPP_BASE_ADDR+0x6))
+
+/* ROMPATCH and AVIC */
+#define ROMPATCH_BASE_ADDR      0x60000000
+#define AVIC_BASE_ADDR          0x68000000
+
+#define INTCNTL                 (*(volatile long*)AVIC_BASE_ADDR)
+#define NIMASK                  (*(volatile long*)(AVIC_BASE_ADDR+0x004))
+#define INTENNUM                (*(volatile long*)(AVIC_BASE_ADDR+0x008))
+#define INTDISNUM               (*(volatile long*)(AVIC_BASE_ADDR+0x00C))
+#define INTENABLEH              (*(volatile long*)(AVIC_BASE_ADDR+0x010))
+#define INTENABLEL              (*(volatile long*)(AVIC_BASE_ADDR+0x014))
+#define INTTYPEH                (*(volatile long*)(AVIC_BASE_ADDR+0x018))
+#define INTTYPEL                (*(volatile long*)(AVIC_BASE_ADDR+0x01C))
+#define NIPRIORITY7             (*(volatile long*)(AVIC_BASE_ADDR+0x020))
+#define NIPRIORITY6             (*(volatile long*)(AVIC_BASE_ADDR+0x024))
+#define NIPRIORITY5             (*(volatile long*)(AVIC_BASE_ADDR+0x028))
+#define NIPRIORITY4             (*(volatile long*)(AVIC_BASE_ADDR+0x02C))
+#define NIPRIORITY3             (*(volatile long*)(AVIC_BASE_ADDR+0x030))
+#define NIPRIORITY2             (*(volatile long*)(AVIC_BASE_ADDR+0x034))
+#define NIPRIORITY1             (*(volatile long*)(AVIC_BASE_ADDR+0x038))
+#define NIPRIORITY0             (*(volatile long*)(AVIC_BASE_ADDR+0x03C))
+#define NIVECSR                 (*(volatile long*)(AVIC_BASE_ADDR+0x040))
+#define FIVECSR                 (*(volatile long*)(AVIC_BASE_ADDR+0x044))
+#define INTSRCH                 (*(volatile long*)(AVIC_BASE_ADDR+0x048))
+#define INTSRCL                 (*(volatile long*)(AVIC_BASE_ADDR+0x04C))
+#define INTFRCH                 (*(volatile long*)(AVIC_BASE_ADDR+0x050))
+#define INTFRCL                 (*(volatile long*)(AVIC_BASE_ADDR+0x054))
+#define NIPNDH                  (*(volatile long*)(AVIC_BASE_ADDR+0x058))
+#define NIPNDL                  (*(volatile long*)(AVIC_BASE_ADDR+0x05C))
+#define FIPNDH                  (*(volatile long*)(AVIC_BASE_ADDR+0x060))
+#define FIPNDL                  (*(volatile long*)(AVIC_BASE_ADDR+0x064))
+
+/* The vectors go all the way up to 63. 4 bytes for each */
+#define VECTOR_BASE_ADDR        AVIC_BASE_ADDR+0x100
+#define VECTOR0                 (*(volatile long*)VECTOR_BASE_ADDR)
+
+#define NIDIS                   (1 << 22)
+#define FIDIS                   (1 << 21)
+ 
+/* Since AVIC vector registers are NOT used, we reserve some for various
+ * purposes. Copied from Linux source code. */
+#define AVIC_VEC_0              0x100   /* For WFI workaround used by Linux kernel */
+#define AVIC_VEC_1              0x104   /* For system revision used by Linux kernel */
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_2_0            0x20
+#define SYSTEM_REV_ID_REG       (AVIC_BASE_ADDR + AVIC_VEC_1)
+#define SYSTEM_REV_ID_MAG       0xF00C
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE       0xB8000000
+#define NFC_BASE                EXT_MEM_CTRL_BASE
+#define ESDCTL_BASE             0xB8001000
+#define WEIM_BASE_ADDR          0xB8002000
+#define WEIM_CTRL_CS0           WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1           (WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2           (WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3           (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4           (WEIM_BASE_ADDR + 0x40)
+#define M3IF_BASE               0xB8003000
+#define PCMCIA_CTL_BASE         0xB8004000
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR       0x70000000
+#define CSD0_BASE_ADDR          0x80000000
+#define CSD1_BASE_ADDR          0x90000000
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_PSRAM          0xB5000000
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xC0000000
+
+#define INTERNAL_ROM_VA         0xF0000000
+
+// SDRAM
+#define RAM_BANK0_BASE          SDRAM_BASE_ADDR
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define AVIC_NIMASK                     REG32_PTR(AVIC_BASE_ADDR + (0x04))
+#define AVIC_INTTYPEH                   REG32_PTR(AVIC_BASE_ADDR + (0x18))
+#define AVIC_INTTYPEL                   REG32_PTR(AVIC_BASE_ADDR + (0x1C))
+
+/* L210 */
+#define L2CC_BASE_ADDR                  0x30000000
+#define L2_CACHE_LINE_SIZE              32
+#define L2_CACHE_CTL_REG                0x100
+#define L2_CACHE_AUX_CTL_REG            0x104
+#define L2_CACHE_SYNC_REG               0x730
+#define L2_CACHE_INV_LINE_REG           0x770
+#define L2_CACHE_INV_WAY_REG            0x77C
+#define L2_CACHE_CLEAN_LINE_REG         0x7B0
+#define L2_CACHE_CLEAN_INV_LINE_REG     0x7F0
+
+/* CCM */
+#define CLKCTL_CCMR                     (*(volatile long*)(CCM_BASE_ADDR+0x00))
+#define CLKCTL_PDR0                     (*(volatile long*)(CCM_BASE_ADDR+0x04))
+#define CLKCTL_PDR1                     (*(volatile long*)(CCM_BASE_ADDR+0x08))
+#define CLKCTL_PDR2                     (*(volatile long*)(CCM_BASE_ADDR+0x64))
+#define CLKCTL_RCSR                     (*(volatile long*)(CCM_BASE_ADDR+0x0C))
+#define CLKCTL_MPCTL                    (*(volatile long*)(CCM_BASE_ADDR+0x10))
+#define CLKCTL_UPCTL                    (*(volatile long*)(CCM_BASE_ADDR+0x14))
+#define CLKCTL_SPCTL                    (*(volatile long*)(CCM_BASE_ADDR+0x18))
+#define CLKCTL_COSR                     (*(volatile long*)(CCM_BASE_ADDR+0x1C))
+#define CLKCTL_PMCR0                    (*(volatile long*)(CCM_BASE_ADDR+0x5C))
+#define PLL_REF_CLK                     26000000
+
+/* WEIM - CS0 */
+#define CSCRU                           0x00
+#define CSCRL                           0x04
+#define CSCRA                           0x08
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0                  0x00
+#define ESDCTL_ESDCFG0                  0x04
+#define ESDCTL_ESDCTL1                  0x08
+#define ESDCTL_ESDCFG1                  0x0C
+#define ESDCTL_ESDMISC                  0x10
+
+/* More UART 1 Register defines */
+#define URXD1 (*(volatile int*)UART1_BASE_ADDR)
+#define UTXD1 (*(volatile int*)(UART1_BASE_ADDR+0x40))
+#define UCR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x80))
+#define UCR2_1 (*(volatile int* )(UART1_BASE_ADDR+0x84))
+#define UCR3_1 (*(volatile int* )(UART1_BASE_ADDR+0x88))
+#define UCR4_1 (*(volatile int* )(UART1_BASE_ADDR+0x8C))
+#define UFCR1 (*(volatile int *)(UART1_BASE_ADDR+ 0x90))
+#define USR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x94))
+#define USR2_1 (*(volatile int *)(UART1_BASE_ADDR+0x98))
+#define UTS1    (*(volatile int *)(UART1_BASE_ADDR+0xB4))
+
+/*
+ * UART Control Register 0 Bit Fields.
+ */
+#define         EUartUCR1_ADEN      (1 << 15)   // Auto detect interrupt
+#define         EUartUCR1_ADBR      (1 << 14)   // Auto detect baud rate
+#define         EUartUCR1_TRDYEN    (1 << 13)   // Transmitter ready interrupt enable
+#define         EUartUCR1_IDEN      (1 << 12)   // Idle condition interrupt
+#define         EUartUCR1_RRDYEN    (1 << 9)    // Recv ready interrupt enable
+#define         EUartUCR1_RDMAEN    (1 << 8)    // Recv ready DMA enable
+#define         EUartUCR1_IREN      (1 << 7)    // Infrared interface enable
+#define         EUartUCR1_TXMPTYEN  (1 << 6)    // Transimitter empt  interrupt enable
+#define         EUartUCR1_RTSDEN    (1 << 5)    // RTS delta interrupt enable
+#define         EUartUCR1_SNDBRK    (1 << 4)    // Send break
+#define         EUartUCR1_TDMAEN    (1 << 3)    // Transmitter ready DMA enable
+#define         EUartUCR1_DOZE      (1 << 1)    // Doze
+#define         EUartUCR1_UARTEN    (1 << 0)    // UART enabled
+#define         EUartUCR2_ESCI      (1 << 15)   // Escape seq interrupt enable
+#define         EUartUCR2_IRTS      (1 << 14)   // Ignore RTS pin
+#define         EUartUCR2_CTSC      (1 << 13)   // CTS pin control
+#define         EUartUCR2_CTS       (1 << 12)   // Clear to send
+#define         EUartUCR2_ESCEN     (1 << 11)   // Escape enable
+#define         EUartUCR2_PREN      (1 << 8)    // Parity enable
+#define         EUartUCR2_PROE      (1 << 7)    // Parity odd/even
+#define         EUartUCR2_STPB      (1 << 6)    // Stop
+#define         EUartUCR2_WS        (1 << 5)    // Word size
+#define         EUartUCR2_RTSEN     (1 << 4)    // Request to send interrupt enable
+#define         EUartUCR2_ATEN      (1 << 3)    // Aging timer enable
+#define         EUartUCR2_TXEN      (1 << 2)    // Transmitter enabled
+#define         EUartUCR2_RXEN      (1 << 1)    // Receiver enabled
+#define         EUartUCR2_SRST_     (1 << 0)    // SW reset
+#define         EUartUCR3_PARERREN  (1 << 12)   // Parity enable
+#define         EUartUCR3_FRAERREN  (1 << 11)   // Frame error interrupt enable
+#define         EUartUCR3_ADNIMP    (1 << 7)    // Autobaud detection not improved
+#define         EUartUCR3_RXDSEN    (1 << 6)    // Receive status interrupt  enable
+#define         EUartUCR3_AIRINTEN  (1 << 5)    // Async IR wake interrupt enable
+#define         EUartUCR3_AWAKEN    (1 << 4)    // Async wake interrupt enable
+#define         EUartUCR3_RXDMUXSEL (1 << 2)    // RXD muxed input selected
+#define         EUartUCR3_INVT      (1 << 1)    // Inverted Infrared transmission
+#define         EUartUCR3_ACIEN     (1 << 0)    // Autobaud counter interrupt  enable
+#define         EUartUCR4_CTSTL_32  (32 << 10)  // CTS trigger level (32 chars)
+#define         EUartUCR4_INVR      (1 << 9)    // Inverted infrared reception
+#define         EUartUCR4_ENIRI     (1 << 8)    // Serial infrared interrupt enable
+#define         EUartUCR4_WKEN      (1 << 7)    // Wake interrupt enable
+#define         EUartUCR4_IRSC      (1 << 5)    // IR special case
+#define         EUartUCR4_LPBYP     (1 << 4)    // Low power bypass
+#define         EUartUCR4_TCEN      (1 << 3)    // Transmit complete interrupt  enable
+#define         EUartUCR4_BKEN      (1 << 2)    // Break condition interrupt enable
+#define         EUartUCR4_OREN      (1 << 1)    // Receiver overrun interrupt enable
+#define         EUartUCR4_DREN      (1 << 0)    // Recv data ready interrupt enable
+#define         EUartUFCR_RXTL_SHF  0           // Receiver trigger level shift
+#define         EUartUFCR_RFDIV_1   (5 << 7)    // Reference freq divider (div> 1)
+#define         EUartUFCR_RFDIV_2   (4 << 7)    // Reference freq divider (div> 2)
+#define         EUartUFCR_RFDIV_3   (3 << 7)            // Reference freq  divider (div 3)
+#define         EUartUFCR_RFDIV_4   (2 << 7)            // Reference freq divider (div 4)
+#define         EUartUFCR_RFDIV_5   (1 << 7)            // Reference freq divider (div 5)
+#define         EUartUFCR_RFDIV_6   (0 << 7)            // Reference freq divider (div 6)
+#define         EUartUFCR_RFDIV_7   (6 << 7)            // Reference freq divider (div 7)
+#define         EUartUFCR_TXTL_SHF  10          // Transmitter trigger level shift
+#define         EUartUSR1_PARITYERR (1 << 15)   // Parity error interrupt flag
+#define         EUartUSR1_RTSS      (1 << 14)   // RTS pin status
+#define         EUartUSR1_TRDY      (1 << 13)   // Transmitter ready interrupt/dma flag
+#define         EUartUSR1_RTSD      (1 << 12)   // RTS delta
+#define         EUartUSR1_ESCF      (1 << 11)   // Escape seq interrupt flag
+#define         EUartUSR1_FRAMERR   (1 << 10)   // Frame error interrupt flag
+#define         EUartUSR1_RRDY      (1 << 9)    // Receiver ready  interrupt/dma flag
+#define         EUartUSR1_AGTIM     (1 << 8)    // Aging timeout interrupt status
+#define         EUartUSR1_RXDS      (1 << 6)    // Receiver idle interrupt flag
+#define         EUartUSR1_AIRINT    (1 << 5)    // Async IR wake interrupt flag
+#define         EUartUSR1_AWAKE     (1 << 4)    // Aysnc wake interrupt flag
+#define         EUartUSR2_ADET      (1 << 15)   // Auto baud rate detect  complete
+#define         EUartUSR2_TXFE      (1 << 14)   // Transmit buffer FIFO empty
+#define         EUartUSR2_IDLE      (1 << 12)   // Idle condition
+#define         EUartUSR2_ACST      (1 << 11)   // Autobaud counter stopped
+#define         EUartUSR2_IRINT     (1 << 8)    // Serial infrared interrupt flag
+#define         EUartUSR2_WAKE      (1 << 7)    // Wake
+#define         EUartUSR2_RTSF      (1 << 4)    // RTS edge interrupt flag
+#define         EUartUSR2_TXDC      (1 << 3)    // Transmitter complete
+#define         EUartUSR2_BRCD      (1 << 2)    // Break condition
+#define         EUartUSR2_ORE       (1 << 1)    // Overrun error
+#define         EUartUSR2_RDR       (1 << 0)    // Recv data ready
+#define         EUartUTS_FRCPERR    (1 << 13)   // Force parity error
+#define         EUartUTS_LOOP       (1 << 12)   // Loop tx and rx
+#define         EUartUTS_TXEMPTY    (1 << 6)    // TxFIFO empty
+#define         EUartUTS_RXEMPTY    (1 << 5)    // RxFIFO empty
+#define         EUartUTS_TXFULL     (1 << 4)    // TxFIFO full
+#define         EUartUTS_RXFULL     (1 << 3)    // RxFIFO full
+#define         EUartUTS_SOFTRST    (1 << 0)    // Software reset
+
+#define         DelayTimerPresVal   3
+
+#define         L2CC_ENABLED
+
+/* Assuming 26MHz input clock */
+/*                         PD          MFD           MFI          MFN */
+#define         MPCTL_PARAM_208  ((1 << 26) + (0   << 16) + (8  << 10) + (0 << 0))
+#define         MPCTL_PARAM_399  ((0 << 26) + (51  << 16) + (7  << 10) + (35 << 0))
+#define         MPCTL_PARAM_532  ((0 << 26) + (51  << 16) + (10 << 10) + (12 << 0))
+
+/* UPCTL                   PD             MFD              MFI          MFN */
+#define UPCTL_PARAM_288  (((1-1) << 26) + ((13-1) << 16) + (5  << 10) + (7  << 0))
+#define UPCTL_PARAM_240  (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
+
+/* PDR0 */
+#define PDR0_208_104_52     0xFF870D48  /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
+#define PDR0_399_66_66      0xFF872B28  /* ARM=399MHz, HCLK=IPG=66.5MHz */
+#define PDR0_399_133_66     0xFF871650  /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
+#define PDR0_532_133_66     0xFF871E58  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
+#define PDR0_665_83_66      0xFF873D78  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
+#define PDR0_665_133_66     0xFF872660  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
+
+#define PBC_BASE            CS4_BASE_ADDR    /* Peripheral Bus Controller */
+
+#define PBC_BSTAT2                   0x2
+#define PBC_BCTRL1                   0x4
+#define PBC_BCTRL1_CLR               0x6
+#define PBC_BCTRL2                   0x8
+#define PBC_BCTRL2_CLR               0xA
+#define PBC_BCTRL3                   0xC
+#define PBC_BCTRL3_CLR               0xE
+#define PBC_BCTRL4                   0x10
+#define PBC_BCTRL4_CLR               0x12
+#define PBC_BSTAT1                   0x14
+#define MX31EVB_CS_LAN_BASE        (CS4_BASE_ADDR + 0x00020000 +  0x300)
+#define MX31EVB_CS_UART_BASE       (CS4_BASE_ADDR + 0x00010000)
+
+#define         REDBOOT_IMAGE_SIZE              0x40000
+ 
+#define         SDRAM_WORKAROUND_FULL_PAGE
+ 
+#define       ARMHIPG_208_52_52         /* ARM: 208MHz, HCLK=IPG=52MHz*/
+#define       ARMHIPG_52_52_52          /* ARM: 52MHz, HCLK=IPG=52MHz*/
+#define       ARMHIPG_399_66_66
+#define         ARMHIPG_399_133_66
+ 
+/* MX31 EVB SDRAM is from 0x80000000, 64M */
+#define         SDRAM_BASE_ADDR                 CSD0_BASE_ADDR
+#define         SDRAM_SIZE                      0x04000000
+
+#define         UART_WIDTH_32         /* internal UART is 32bit access only */
+#define         EXT_UART_x16
+
+#define         UART_WIDTH_32         /* internal UART is 32bit access only */
+
+#define         FLASH_BURST_MODE_ENABLE 1
+#define         SDRAM_COMPARE_CONST1    0x55555555
+#define         SDRAM_COMPARE_CONST2    0xAAAAAAAA
+#define         UART_FIFO_CTRL          0x881
+#define         TIMEOUT                 1000
+#define         writel(v,a)         (*(volatile int *) (a) = (v))
+#define         readl(a)            (*(volatile int *)(a))
+#define         writew(v,a)         (*(volatile short *) (a) = (v))
+#define         readw(a)            (*(volatile short *)(a))
diff --git a/firmware/export/kernel.h b/firmware/export/kernel.h
index 9ada8eb59c..50c9bdc0ae 100644
--- a/firmware/export/kernel.h
+++ b/firmware/export/kernel.h
@@ -113,6 +113,8 @@ struct mutex
 /* We don't enable interrupts in the iPod bootloader, so we need to fake
    the current_tick variable */
 #define current_tick (signed)(USEC_TIMER/10000)
+#elif (CONFIG_CPU == IMX31L) && defined(BOOTLOADER)
+#define current_tick (signed)((0xFFFFFFFF - EPITCNT1)/10000)
 #else
 extern volatile long current_tick;
 #endif
diff --git a/firmware/export/usb.h b/firmware/export/usb.h
index 0c4231a4e5..17dbafa10e 100644
--- a/firmware/export/usb.h
+++ b/firmware/export/usb.h
@@ -47,6 +47,9 @@
 #elif CONFIG_KEYPAD == GIGABEAT_PAD
 #define USBPOWER_BUTTON BUTTON_MENU
 #define USBPOWER_BTN_IGNORE BUTTON_POWER
+#elif CONFIG_KEYPAD == GIGABEAT_S_PAD
+#define USBPOWER_BUTTON BUTTON_MENU
+#define USBPOWER_BTN_IGNORE BUTTON_BACK
 #elif CONFIG_KEYPAD == IRIVER_H10_PAD
 #define USBPOWER_BUTTON BUTTON_NONE
 #define USBPOWER_BTN_IGNORE BUTTON_POWER
diff --git a/firmware/kernel.c b/firmware/kernel.c
index bb67ced64d..11b10e287e 100644
--- a/firmware/kernel.c
+++ b/firmware/kernel.c
@@ -24,8 +24,11 @@
 #include "cpu.h"
 #include "system.h"
 #include "panic.h"
+#if CONFIG_CPU == IMX31L
+#include "avic-imx31.h"
+#endif
 
-#if !defined(CPU_PP) || !defined(BOOTLOADER) 
+#if (!defined(CPU_PP) && (CONFIG_CPU != IMX31L)) || !defined(BOOTLOADER) 
 volatile long current_tick NOCACHEDATA_ATTR = 0;
 #endif
 
@@ -83,7 +86,7 @@ void sleep(int ticks)
 
 void yield(void)
 {
-#if ((CONFIG_CPU == S3C2440 || defined(ELIO_TPJ1022)) && defined(BOOTLOADER))
+#if ((CONFIG_CPU == S3C2440 || defined(ELIO_TPJ1022) || CONFIG_CPU == IMX31L) && defined(BOOTLOADER))
     /* Some targets don't like yielding in the bootloader */
 #else
     switch_thread(true, NULL);
@@ -708,6 +711,48 @@ void tick_start(unsigned int interval_in_ms)
 
     TIMER0.ctrl |= 0x80;  /* Enable the counter */
 }
+#elif CONFIG_CPU == IMX31L
+void tick_start(unsigned int interval_in_ms)
+{
+    EPITCR1 &= ~0x1;        /* Disable the counter */
+
+    EPITCR1 &= ~0xE;        /* Disable interrupt, count down from 0xFFFFFFFF */
+    EPITCR1 &= ~0xFFF0;     /* Clear prescaler */
+#ifdef BOOTLOADER
+    EPITCR1 |= (2700 << 2); /* Prescaler = 2700 */
+#endif
+    EPITCR1 &= ~(0x3 << 24);
+    EPITCR1 |= (0x2 << 24); /* Set clock source to external clock (27mhz) */
+    EPITSR1 = 1;            /* Clear the interrupt request */
+#ifndef BOOTLOADER
+    EPITLR1 = 27000000 * interval_in_ms / 1000;
+    EPITCMPR1 = 27000000 * interval_in_ms / 1000;
+#else
+    (void)interval_in_ms;
+#endif
+
+    //avic_enable_int(EPIT1, IRQ, EPIT_HANDLER);
+
+    EPITCR1 |= 0x1;           /* Enable the counter */
+}
+
+#ifndef BOOTLOADER
+void EPIT_HANDLER(void) __attribute__((interrupt("IRQ")));
+void EPIT_HANDLER(void) {
+    int i;
+
+    /* Run through the list of tick tasks */
+    for(i = 0;i < MAX_NUM_TICK_TASKS;i++)
+    {
+        if(tick_funcs[i])
+            tick_funcs[i]();
+    }
+
+    current_tick++;
+
+    EPITSR1 = 1;            /* Clear the interrupt request */
+}
+#endif
 #endif
 
 int tick_add_task(void (*f)(void))
diff --git a/firmware/pcm_playback.c b/firmware/pcm_playback.c
index e6e59ca604..1b16eb47db 100644
--- a/firmware/pcm_playback.c
+++ b/firmware/pcm_playback.c
@@ -50,7 +50,7 @@ void pcm_play_pause_unpause(void);
 
 /** Functions that require targeted implementation **/
 
-#if defined(CPU_COLDFIRE) || (CONFIG_CPU == S3C2440)
+#if defined(CPU_COLDFIRE) || (CONFIG_CPU == S3C2440) || (CONFIG_CPU == IMX31L)
 /* Implemented in target/... */
 #else
 /* dummy functions for those not actually supporting all this yet */
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S
index 56876ca9b1..d734f82df8 100644
--- a/firmware/target/arm/crt0.S
+++ b/firmware/target/arm/crt0.S
@@ -23,6 +23,9 @@
 
     .global    start
 start:
+    b      newstart     
+    .space 4*16
+
 
 /* Arm bootloader and startup code based on startup.s from the iPodLinux loader
  *
@@ -31,7 +34,13 @@ start:
  *
  */
 
-    msr    cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
+newstart:
+#if CONFIG_CPU == IMX31L
+    mov r0,#0xD3
+    msr cpsr, r0
+#else
+    msr    cpsr, #0xd3 /* enter supervisor mode, disable IRQ */
+#endif  
 
 #if !defined(BOOTLOADER) || (CONFIG_CPU == DM320)
 #if !defined(DEBUG)
@@ -95,7 +104,7 @@ start:
     cmp    r3, r2
     strhi  r4, [r2], #4
     bhi    1b
-
+    
 #ifdef BOOTLOADER
 /* Code for ARM bootloader targets other than iPod go here */
 
@@ -274,6 +283,151 @@ start:
 start_loc:
      bl main
      
+#elif CONFIG_CPU == IMX31L
+          
+    mov r0, #0
+    mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
+    mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
+    mcr 15, 0, r0, c7, c10, 4        /* Drain the write buffer */
+
+    /* Also setup the Peripheral Port Remap register inside the core */
+    ldr r0, =0x40000015        /* start from AIPS 2GB region */
+    mcr p15, 0, r0, c15, c2, 4
+
+    /*** L2 Cache setup/invalidation/disable ***/
+    /* Disable L2 cache first */
+    ldr r0, =L2CC_BASE_ADDR
+    ldr r2, [r0, #L2_CACHE_CTL_REG]
+    bic r2, r2, #0x1
+    str r2, [r0, #L2_CACHE_CTL_REG]
+
+
+    /*
+     * Configure L2 Cache:
+     * - 128k size(16k way)
+     * - 8-way associativity
+     * - 0 ws TAG/VALID/DIRTY
+     * - 4 ws DATA R/W
+     */
+    ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+    and r1, r1, #0xFE000000
+    ldr r2, =0x00030024
+    orr r1, r1, r2
+    str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+
+    /* Invalidate L2 */
+    ldr r1, =0x000000FF
+    str r1, [r0, #L2_CACHE_INV_WAY_REG]
+L2_loop:
+    /* Poll Invalidate By Way register */
+    ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+    cmp r2, #0
+    bne L2_loop
+    /*** End of L2 operations ***/
+                 /* Set up stack for IRQ mode */ 
+        mov    r0,#0xd2
+    msr    cpsr, r0
+    ldr    sp, =irq_stack
+    /* Set up stack for FIQ mode */ 
+    mov    r0,#0xd1
+    msr    cpsr, r0
+    ldr    sp, =fiq_stack
+
+    /* Let abort and undefined modes use IRQ stack */
+    mov    r0,#0xd7
+    msr    cpsr, r0
+    ldr    sp, =irq_stack
+    mov    r0,#0xdb
+    msr    cpsr, r0
+    ldr    sp, =irq_stack
+    /* Switch to supervisor mode */
+    mov    r0,#0xd3
+    msr    cpsr, r0
+    ldr    sp, =stackend
+    
+    /*remap memory as well as exception vectors*/
+    /*for now this will be done in bootloader, especially
+      if usb will be needed within the bootloader to load the 
+      main firmware file. Interrupts will be needed for this
+      (whether they be swi or irq)*/
+        bl memory_init
+        mov r0,#0
+        ldr r1,=_vectorstart
+        mov r2,#0
+        
+lp: ldr r3,[r1]
+        add r1,r1,#4
+        str r3,[r0]
+        add r0,r0,#4
+        add r2,r2,#1
+        cmp r2,#16
+        bne lp
+        bl main
+
+.section .vectors,"aw"
+_vectorstart:
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+    ldr    pc, [pc, #24]
+
+    /* Exception vectors */
+    .global vectors
+vectors:
+    .word  start 
+    .word  undef_instr_handler
+    .word  software_int_handler
+    .word  prefetch_abort_handler
+    .word  data_abort_handler
+    .word  reserved_handler
+    .word  irqz
+    .word  fiqz
+
+    .text
+    .global irq
+    .global fiq
+    .global UIE
+
+undef_instr_handler:
+    mov    r0, lr
+    mov    r1, #0
+    b      UIE
+
+software_int_handler:
+reserved_handler:
+        bl     irq_handler
+    movs   pc, lr
+
+prefetch_abort_handler:
+    sub    r0, lr, #4
+    mov    r1, #1
+    b      UIE
+
+data_abort_handler:
+    sub    r0, lr, #8 
+    mov    r1, #2
+    b      UIE
+
+/*not working....if we get here, let someone
+know....*/
+irqz: bl irq_handler
+fiqz: bl fiq_handler
+
+UIE:
+    b UIE
+
+/* 256 words of IRQ stack */
+    .space 256*4
+irq_stack:
+
+/* 256 words of FIQ stack */
+    .space 256*4
+fiq_stack:
+
 #else
     /* get the high part of our execute address */
     ldr    r2, =0xffffff00
@@ -295,11 +449,15 @@ start_loc:
     
 start_loc:
      bl main
+
 #endif
 
 #else /* BOOTLOADER */
     
-    /* Set up stack for IRQ mode */ 
+
+
+
+         /* Set up stack for IRQ mode */ 
     msr    cpsr_c, #0xd2
     ldr    sp, =irq_stack
     /* Set up stack for FIQ mode */ 
@@ -316,8 +474,11 @@ start_loc:
     ldr    sp, =stackend
     bl     main
     /* main() should never return */
-   
+
 /* Exception handlers. Will be copied to address 0 after memory remapping */
+#if CONFIG_CPU == IMX31L
+_vectorstart:
+#endif
     .section .vectors,"aw"
     ldr    pc, [pc, #24]
     ldr    pc, [pc, #24]
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
new file mode 100644
index 0000000000..1fd2247ef1
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
@@ -0,0 +1,52 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Wade Brown
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "cpu.h"
+#include "adc-target.h"
+#include "kernel.h"
+
+/* prototypes */
+static unsigned short __adc_read(int channel);
+static void adc_tick(void);
+
+void adc_init(void) 
+{
+}
+
+/* Called to get the recent ADC reading */
+inline unsigned short adc_read(int channel)
+{
+    (void)channel;
+    return 0;
+}
+
+/** 
+  * Read the ADC by polling
+  * @param channel The ADC channel to read
+  * @return 10bit reading from ADC channel or ADC_READ_ERROR if timeout
+  */
+static unsigned short __adc_read(int channel) 
+{
+    (void)channel;
+    return 0;
+}
+
+/* add this to the tick so that the ADC converts are done in the background */
+static void adc_tick(void)
+{
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-target.h b/firmware/target/arm/imx31/gigabeat-s/adc-target.h
new file mode 100644
index 0000000000..8d2beaf320
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/adc-target.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Barry Wardell
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _ADC_TARGET_H_
+#define _ADC_TARGET_H_
+
+/* only two channels used by the Gigabeat */
+#define NUM_ADC_CHANNELS 2
+
+#define ADC_BATTERY     0
+#define ADC_HPREMOTE    1
+#define ADC_UNKNOWN_3   2
+#define ADC_UNKNOWN_4   3
+#define ADC_UNKNOWN_5   4
+#define ADC_UNKNOWN_6   5
+#define ADC_UNKNOWN_7   6
+#define ADC_UNKNOWN_8   7
+
+#define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */
+#define ADC_READ_ERROR 0xFFFF
+
+#endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
new file mode 100644
index 0000000000..58659c7d53
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
@@ -0,0 +1,137 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Will Robertson
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "cpu.h"
+#include "kernel.h"
+#include "thread.h"
+#include "system.h"
+#include "power.h"
+#include "panic.h"
+#include "pcf50606.h"
+#include "ata-target.h"
+#include "mmu-imx31.h"
+#include "backlight-target.h"
+
+#define ATA_RST (1 << 6)
+
+void ata_reset(void)
+{
+    ATA_CONTROL &= ~ATA_RST;
+    sleep(1);
+    ATA_CONTROL |= ATA_RST;
+    sleep(1);
+}
+
+/* This function is called before enabling the USB bus */
+void ata_enable(bool on)
+{
+    (void)on;
+}
+
+bool ata_is_coldstart(void)
+{
+    return 0;
+}
+
+unsigned long get_pll(bool serial) {
+    unsigned long mfi, mfn, mfd, pdf, ref_clk;
+    unsigned long reg = 0, ccmr;
+    unsigned long long temp;
+    unsigned int prcs;
+
+    ccmr = CLKCTL_CCMR;
+    prcs = (ccmr & 0x6) >> 1;
+    if(prcs == 0x1) {
+        ref_clk = 32768 * 1024;
+    } else {
+        ref_clk = 27000000;
+    }
+
+    if(serial) {
+        reg = CLKCTL_SPCTL;
+    } else {
+        if((ccmr & 0x8) == 0)
+            return ref_clk;
+        if((ccmr & 0x80) != 0)
+            return ref_clk;
+        reg = CLKCTL_MPCTL;
+    }
+    pdf = (reg & (0x7 << 26)) >> 26;
+    mfd = (reg & (0x3FF << 16)) >> 16;
+    mfi = (reg & (0xF << 10)) >> 10;
+    mfi = (mfi <= 5) ? 5 : mfi;
+    mfn = (reg & 0x3FF);
+
+    if(mfn < 0x200) {
+        temp = (unsigned long long)2 *ref_clk * mfn;
+        temp /= (mfd + 1);
+        temp = (unsigned long long)2 *ref_clk * mfi + temp;
+        temp /= (pdf + 1);
+    } else {
+        temp = (unsigned long long)2 *ref_clk * (0x400 - mfn);
+        temp /= (mfd + 1);
+        temp = (unsigned long long)2 *ref_clk * mfi - temp;
+        temp /= (pdf + 1);
+
+    }
+    return (unsigned long)temp;
+}
+
+unsigned long get_ata_clock(void) {
+    unsigned long pll, ret_val, hclk, max_pdf, ipg_pdf, mcu_pdf;
+
+    max_pdf = (CLKCTL_PDR0 & (0x7 << 3)) >> 3;
+    ipg_pdf = (CLKCTL_PDR0 & (0x3 << 6)) >> 6;
+    mcu_pdf = (CLKCTL_PDR0 & 0x7);
+    if((CLKCTL_PMCR0 & 0xC0000000 ) == 0) {
+        pll = get_pll(true);
+    } else {
+        pll = get_pll(false);
+    }
+    hclk = pll/(max_pdf + 1);
+    ret_val = hclk / (ipg_pdf + 1);
+
+    return ret_val;
+}
+
+void ata_device_init(void)
+{
+    ATA_CONTROL |= ATA_RST; /* Make sure we're not in reset mode */
+
+    /* Setup the timing for PIO mode */
+    int T = 1000 * 1000 * 1000 / get_ata_clock();
+    TIME_OFF = 3;
+    TIME_ON = 3;
+
+    TIME_1 = (T + 70)/T;
+    TIME_2W = (T + 290)/T;
+    TIME_2R = (T + 290)/T;
+    TIME_AX = (T + 50)/T;
+    TIME_PIO_RDX = 1;
+    TIME_4 = (T + 30)/T;
+    TIME_9 = (T + 20)/T;
+}
+
+#if !defined(BOOTLOADER)
+void copy_read_sectors(unsigned char* buf, int wordcount)
+{
+    (void)buf;
+    (void)wordcount;
+}
+#endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-target.h b/firmware/target/arm/imx31/gigabeat-s/ata-target.h
new file mode 100644
index 0000000000..6dd6da9134
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/ata-target.h
@@ -0,0 +1,70 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef ATA_TARGET_H
+#define ATA_TARGET_H
+
+/* Plain C read & write loops */
+#define PREFER_C_READING
+#define PREFER_C_WRITING
+#if !defined(BOOTLOADER)
+#define ATA_OPTIMIZED_READING
+void copy_read_sectors(unsigned char* buf, int wordcount);
+#endif
+
+#define ATA_IOBASE      0x43F8C000
+#define ATA_DATA        (*((volatile unsigned short*)(ATA_IOBASE + 0xA0)))
+#define ATA_ERROR       (*((volatile unsigned char*)(ATA_IOBASE + 0xA4)))
+#define ATA_NSECTOR     (*((volatile unsigned char*)(ATA_IOBASE + 0xA8)))
+#define ATA_SECTOR      (*((volatile unsigned char*)(ATA_IOBASE + 0xAC)))
+#define ATA_LCYL        (*((volatile unsigned char*)(ATA_IOBASE + 0xB0)))
+#define ATA_HCYL        (*((volatile unsigned char*)(ATA_IOBASE + 0xB4)))
+#define ATA_SELECT      (*((volatile unsigned char*)(ATA_IOBASE + 0xB8)))
+#define ATA_COMMAND     (*((volatile unsigned char*)(ATA_IOBASE + 0xBC)))
+#define ATA_CONTROL     (*((volatile unsigned char*)(ATA_IOBASE + 0xD8)))
+
+#define STATUS_BSY      0x80
+#define STATUS_RDY      0x40
+#define STATUS_DF       0x20
+#define STATUS_DRQ      0x08
+#define STATUS_ERR      0x01
+#define ERROR_ABRT      0x04
+
+#define WRITE_PATTERN1 0xa5
+#define WRITE_PATTERN2 0x5a
+#define WRITE_PATTERN3 0xaa
+#define WRITE_PATTERN4 0x55
+
+#define READ_PATTERN1 0xa5
+#define READ_PATTERN2 0x5a
+#define READ_PATTERN3 0xaa
+#define READ_PATTERN4 0x55
+
+#define READ_PATTERN1_MASK 0xff
+#define READ_PATTERN2_MASK 0xff
+#define READ_PATTERN3_MASK 0xff
+#define READ_PATTERN4_MASK 0xff
+
+#define SET_REG(reg,val) reg = (val)
+#define SET_16BITREG(reg,val) reg = (val)
+
+void ata_reset(void);
+void ata_device_init(void);
+bool ata_is_coldstart(void);
+
+#endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
new file mode 100644
index 0000000000..8236a38014
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
@@ -0,0 +1,223 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by James Espinoza
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <stdio.h>
+#include "system.h"
+#include "imx31l.h"
+#include "avic-imx31.h"
+#include "debug.h"
+
+void avic_init(void) 
+{
+        /*following the steps in the AVIC setup in imx31 man*/
+        
+        /*Initialize interrupt structures*/
+        int i,avicstart;
+        /*get start of avic_init section for address calculation*/
+        __asm__ ("ldr %0,=_avicstart\n\t"
+                     :"=r"(avicstart):);
+
+        for(i=0; i < 64;i++)
+        {
+                imx31_int[i].name = (char *)&imx31_int_names[i];
+                imx31_int[i].int_type=IRQ;
+                /*integer i MUST be multiplied by 8 b/c gnu as
+                  generates 2 instructions for each vector instruction
+                  in vector_init(). Hence the value of 8 byte intervals
+                  between each vector start address*/
+                imx31_int[i].addr=(avicstart+(i*8));
+                imx31_int[i].priority=0;
+                imx31_int[i].pInt_Handler=Unhandled_Int;
+        }
+        
+        /*enable all Interrupts*/
+        avic_enable_int(ALL,IRQ,0);
+        
+        /*Setup all interrupt type IRQ*/
+        avic_set_int_type(ALL,IRQ);
+        
+        /*Set NM bit to enable VIC*/
+        INTCNTL |= (1 << 18);
+
+        /*Setup Registers Vector0-Vector63 for interrupt handler functions*/
+        for(i=0; i < 64;i++)
+                writel(imx31_int[i].addr,(VECTOR_BASE_ADDR+(i*8)));
+        
+        /*disable FIQ for now until the interrupt handlers are more mature...*/
+        disable_fiq();
+        /*enable_fiq();*/
+        
+        /*enable IRQ in imx31 INTCNTL reg*/
+        INTCNTL &= ~(NIDIS);    
+        /*disable FIQ in imx31 INTCNTL reg*/
+        INTCNTL |= FIDIS;
+
+        /*enable IRQ in ARM11 core, enable VE bit in CP15 Control reg to enable VIC*/
+        __asm__ ("mrs r0,cpsr\t\n"
+                  "bic r0,r0,#0x80\t\n"
+                  "msr cpsr,r0\t\n"
+                  "mrc p15,0,r0,c1,c0,0\n\t"
+                  "orr r0,r0,#0x1000000\n\t"
+                  "mcr p15,0,r0,c1,c0,0\n\t":::
+                  "r0");
+}
+
+void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
+                     void (*pInt_Handler) (void))
+{       
+        int i;
+
+        if(ints == ALL) 
+        {
+                avic_set_int_type(ALL,intstype);
+                for(i=0;i<64;i++)
+                        INTENNUM= (long)i;
+                if(!(*pInt_Handler))
+                        pInt_Handler=Unhandled_Int;
+                return;
+        } 
+
+        imx31_int[ints].int_type=intstype;
+        imx31_int[ints].pInt_Handler=pInt_Handler;
+        avic_set_int_type(ints,intstype);
+        INTENNUM=(long)ints;
+}
+
+void avic_disable_int(enum IMX31_INT_LIST ints)
+{
+        int i;
+
+        if(ints == ALL)
+        {
+                for(i=0;i<64;i++)               
+                        INTDISNUM=(long)i;
+                imx31_int[ints].pInt_Handler=Unhandled_Int;
+                return;
+        }
+        
+        INTDISNUM=(long)ints;
+}
+
+void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype)
+{
+        int i;
+        if(ints == ALL)
+        {       
+                imx31_int[ints].int_type=intstype;
+                for(i=0;i<64;i++)
+                {
+                        if(intstype > CCM_DVFS)
+                                INTTYPEH=(long)(intstype-32);
+                        else INTTYPEL=(long)intstype;
+                }
+                return;
+        }
+        
+        imx31_int[ints].int_type=intstype;
+        if(intstype > CCM_DVFS)
+                INTTYPEH=(long)(intstype-32);
+        else INTTYPEL=(long)intstype;
+}
+
+void Unhandled_Int(void) 
+{
+        enum IMX31_INT_LIST ints = 0;
+        DEBUGF("Unhandled Interrupt:\n");
+        DEBUGF("Name : %s\n",imx31_int[ints].name);
+        DEBUGF("Interrupt Type : ");
+        if(imx31_int[ints].int_type==IRQ)
+                DEBUGF("IRQ\n");
+        else DEBUGF("FIQ\n");
+        DEBUGF("Handler Address : 0x%x\n",imx31_int[ints].addr);
+        DEBUGF("Priority : %d",imx31_int[ints].priority);
+}
+
+void vector_init(void)
+{
+                
+                /*64 branch instructions, one for every vector in avic
+                A better idea would to calculate the shellcode for each of these 
+                instructions...*/
+                
+                
+            __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED0].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C3].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MPEG4_ENCODER].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RTIC].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[FIR].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MMC_SDHC2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MMC_SDHC1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SSI2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SSI1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[ATA].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MBX].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI3].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART3].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IIM].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SIM1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SIM2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RNGA].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EVTMON].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[KPP].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RTC].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PWN].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EPIT2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EPIT1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPT].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PWR_FAIL].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CCM_DVFS].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[NANDFC].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SDMA].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_HOST1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_HOST2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_OTG].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED3].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MSHC1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MSHC2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IPU_ERR].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IPU].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED4].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED5].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART4].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART5].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[ETC_IRQ].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SCC_SCM].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SCC_SMN].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CCM_CLK].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PCMCIA].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[WDOG].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO3].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED6].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_PWMG].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_TEMP].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_SENS1].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_SENS2].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_WDOG].pInt_Handler));
+                __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_TV].pInt_Handler));
+        
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
new file mode 100644
index 0000000000..53a37b353b
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
@@ -0,0 +1,125 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by James Espinoza
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef AVIC_IMX31_H
+#define AVIC_IMX31_H
+
+
+enum INT_TYPE {IRQ=0,FIQ};
+
+struct int_names {
+        char name[16];
+};
+
+static const struct int_names imx31_int_names[64] =
+{  {"RESERVED0"},
+   {"RESERVED1"},
+   {"RESERVED2"},
+   {"I2C3"},
+   {"I2C2"},
+   {"MPEG4_ENCODER"},
+   {"RTIC"},
+   {"FIR"},
+   {"MMC/SDHC2"},
+   {"MMC/SDHC1"},
+   {"I2C1"},
+   {"SSI2"},
+   {"SSI1"},
+   {"CSPI2"},
+   {"CSPI1"},
+   {"ATA"},
+   {"MBX"},
+   {"CSPI3"},
+   {"UART3"},
+   {"IIM"},
+   {"SIM1"},
+   {"SIM2"},
+   {"RNGA"},
+   {"EVTMON"},
+   {"KPP"},
+   {"RTC"},
+   {"PWN"},
+   {"EPIT2"},
+   {"EPIT1"},
+   {"GPT"},
+   {"PWR_FAIL"},
+   {"CCM_DVFS"},
+   {"UART2"},
+   {"NANDFC"},
+   {"SDMA"},
+   {"USB_HOST1"},
+   {"USB_HOST2"},
+   {"USB_OTG"},
+   {"RESERVED3"},
+   {"MSHC1"},
+   {"MSHC2"},
+   {"IPU_ERR"},
+   {"IPU"},
+   {"RESERVED4"},
+   {"RESERVED5"},
+   {"UART1"},
+   {"UART4"},
+   {"UART5"},
+   {"ETC_IRQ"},
+   {"SCC_SCM"},
+   {"SCC_SMN"},
+   {"GPIO2"},
+   {"GPIO1"},
+   {"CCM_CLK"},
+   {"PCMCIA"},
+   {"WDOG"},
+   {"GPIO3"},
+   {"RESERVED6"},             
+   {"EXT_PWMG"},
+   {"EXT_TEMP"},
+   {"EXT_SENS1"},
+   {"EXT_SENS2"},
+   {"EXT_WDOG"},
+   {"EXT_TV"} };
+
+enum IMX31_INT_LIST {
+   RESERVED0 = 0,RESERVED1,RESERVED2,I2C3,
+   I2C2,MPEG4_ENCODER,RTIC,FIR,MMC_SDHC2,
+   MMC_SDHC1,I2C1,SSI2,SSI1,CSPI2,CSPI1,
+   ATA,MBX,CSPI3,UART3,IIM,SIM1,SIM2,
+   RNGA,EVTMON,KPP,RTC,PWN,EPIT2,EPIT1,
+   GPT,PWR_FAIL,CCM_DVFS,UART2,NANDFC,
+   SDMA,USB_HOST1,USB_HOST2,USB_OTG,
+   RESERVED3,MSHC1,MSHC2,IPU_ERR,IPU,
+   RESERVED4,RESERVED5,UART1,UART4,UART5,
+   ETC_IRQ,SCC_SCM,SCC_SMN,GPIO2,GPIO1,
+   CCM_CLK,PCMCIA,WDOG,GPIO3,RESERVED6,    
+   EXT_PWMG,EXT_TEMP,EXT_SENS1,EXT_SENS2,
+   EXT_WDOG,EXT_TV,ALL };
+
+static struct avic_int {
+        char * name;
+        enum INT_TYPE int_type;
+        unsigned int addr;
+        unsigned int priority;
+        void (*pInt_Handler) (void);
+} imx31_int[64];
+
+void avic_init(void);
+void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
+                                         void (*pInt_Handler) (void));
+void avic_disable_int(enum IMX31_INT_LIST ints) ;
+void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype);
+void Unhandled_Int(void);
+void vector_init(void) __attribute__ ((section(".avic_int"),naked));
+#endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
new file mode 100644
index 0000000000..37cf086a0e
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
@@ -0,0 +1,51 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "cpu.h"
+#include "system.h"
+#include "backlight-target.h"
+#include "backlight.h"
+#include "lcd.h"
+#include "power.h"
+#include "spi-imx31.h"
+#include "debug.h"
+
+bool __backlight_init(void)
+{
+    return true;
+}
+
+void __backlight_on(void)
+{
+    // This relies on the SPI interface being initialised already
+    spi_send(51, 1);
+}
+
+void __backlight_off(void)
+{
+    // This relies on the SPI interface being initialised already
+    spi_send(51, 0);
+}
+
+/* Assumes that the backlight has been initialized */
+void __backlight_set_brightness(int brightness)
+{
+    (void)brightness;
+}
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-target.h b/firmware/target/arm/imx31/gigabeat-s/backlight-target.h
new file mode 100644
index 0000000000..8f14c76138
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/backlight-target.h
@@ -0,0 +1,29 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef BACKLIGHT_TARGET_H
+#define BACKLIGHT_TARGET_H
+
+bool __backlight_init(void);
+void __backlight_on(void);
+void __backlight_off(void);
+void __backlight_set_brightness(int brightness);
+
+/* true: backlight fades off - false: backlight fades on */
+void __backlight_dim(bool dim);
+#endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
new file mode 100644
index 0000000000..32d2a63c49
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
@@ -0,0 +1,180 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "cpu.h"
+#include "system.h"
+#include "button.h"
+#include "kernel.h"
+#include "backlight.h"
+#include "adc.h"
+#include "system.h"
+#include "backlight-target.h"
+#include "debug.h"
+#include "stdio.h"
+
+/* Most code in here is taken from the Linux BSP provided by Freescale
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. */
+
+void button_init_device(void)
+{
+    unsigned int reg_val;
+    /* Enable keypad clock */
+    //mxc_clks_enable(KPP_CLK);
+    
+   /* Enable number of rows in keypad (KPCR[7:0])
+    * Configure keypad columns as open-drain (KPCR[15:8])
+    *
+    * Configure the rows/cols in KPP
+    * LSB nibble in KPP is for 8 rows
+    * MSB nibble in KPP is for 8 cols
+    */
+   reg_val = KPP_KPCR;
+   reg_val |= (1 << 8) - 1;   /* LSB */
+   reg_val |= ((1 << 8) - 1) << 8;    /* MSB */
+   KPP_KPCR = reg_val;
+
+   /* Write 0's to KPDR[15:8] */
+   reg_val = KPP_KPDR;
+   reg_val &= 0x00ff;
+   KPP_KPDR = reg_val;
+
+   /* Configure columns as output, rows as input (KDDR[15:0]) */
+   KPP_KDDR = 0xff00;
+
+   reg_val = 0xD;
+   reg_val |= (1 << 8);
+   KPP_KPSR = reg_val;
+}
+
+inline bool button_hold(void)
+{
+    return GPIO3_DR & 0x10;
+}
+
+int button_read_device(void)
+{
+    unsigned short reg_val;
+    int col, row;
+    int button = BUTTON_NONE;
+
+    if(!button_hold()) {
+        for (col = 0; col < 3; col++) {  /* Col */
+            /* 1. Write 1s to KPDR[15:8] setting column data to 1s */
+            reg_val = KPP_KPDR;
+            reg_val |= 0xff00;
+            KPP_KPDR = reg_val;
+
+            /*
+             * 2. Configure columns as totem pole outputs(for quick
+             * discharging of keypad capacitance)
+             */
+            reg_val = KPP_KPCR;
+            reg_val &= 0x00ff;
+            KPP_KPCR = reg_val;
+
+            /* Give the columns time to discharge */
+            udelay(2);
+
+            /* 3. Configure columns as open-drain */
+            reg_val = KPP_KPCR;
+            reg_val |= ((1 << 8) - 1) << 8;
+            KPP_KPCR = reg_val;
+
+            /* 4. Write a single column to 0, others to 1.
+             * 5. Sample row inputs and save data. Multiple key presses
+             * can be detected on a single column.
+             * 6. Repeat steps 1 - 5 for remaining columns.
+             */
+
+            /* Col bit starts at 8th bit in KPDR */
+            reg_val = KPP_KPDR;
+            reg_val &= ~(1 << (8 + col));
+            KPP_KPDR = reg_val;
+
+            /* Delay added to avoid propagating the 0 from column to row
+             * when scanning. */
+            udelay(2);
+
+            /* Read row input */
+            reg_val = KPP_KPDR;
+            for (row = 0; row < 5; row++) {  /* sample row */
+                if (!(reg_val & (1 << row))) {
+                    if(row == 0) {
+                            if(col == 0) {
+                                button |= BUTTON_LEFT;
+                            }
+                            if(col == 1) {
+                                button |= BUTTON_BACK;
+                            }
+                            if(col == 2) {
+                                button |= BUTTON_VOL_UP;
+                            }
+                    } else if(row == 1) {
+                            if(col == 0) {
+                                button |= BUTTON_UP;
+                            }
+                            if(col == 1) {
+                                button |= BUTTON_MENU;
+                            }
+                            if(col == 2) {
+                                button |= BUTTON_VOL_DOWN;
+                            }
+                    } else if(row == 2) {
+                            if(col == 0) {
+                                button |= BUTTON_DOWN;
+                            }
+                            if(col == 2) {
+                                button |= BUTTON_PREV;
+                            }
+                    } else if(row == 3) {
+                            if(col == 0) {
+                                button |= BUTTON_RIGHT;
+                            }
+                            if(col == 2) {
+                                button |= BUTTON_PLAY;
+                            }
+                    } else if(row == 4) {
+                            if(col == 0) {
+                                button |= BUTTON_SELECT;
+                            }
+                            if(col == 2) {
+                                button |= BUTTON_NEXT;
+                            }
+                    }
+                }
+            }
+        }
+
+        /*
+         * 7. Return all columns to 0 in preparation for standby mode.
+         * 8. Clear KPKD and KPKR status bit(s) by writing to a .1.,
+         * set the KPKR synchronizer chain by writing "1" to KRSS register,
+         * clear the KPKD synchronizer chain by writing "1" to KDSC register
+         */
+        reg_val = 0x00;
+        KPP_KPDR = reg_val;
+        reg_val = KPP_KPDR;
+        reg_val = KPP_KPSR;
+        reg_val |= 0xF;
+        KPP_KPSR = reg_val;
+    }
+
+    return button;
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-target.h b/firmware/target/arm/imx31/gigabeat-s/button-target.h
new file mode 100644
index 0000000000..33f018e0bf
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/button-target.h
@@ -0,0 +1,59 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _BUTTON_TARGET_H_
+#define _BUTTON_TARGET_H_
+
+#include <stdbool.h>
+#include "config.h"
+
+#define HAS_BUTTON_HOLD
+
+bool button_hold(void);
+void button_init_device(void);
+int button_read_device(void);
+
+/* Toshiba Gigabeat specific button codes */
+
+#define BUTTON_BACK         (1 << 0)
+#define BUTTON_MENU         (1 << 1)
+
+#define BUTTON_LEFT         (1 << 2)
+#define BUTTON_RIGHT        (1 << 3)
+#define BUTTON_UP           (1 << 4)
+#define BUTTON_DOWN         (1 << 5)
+#define BUTTON_SELECT       (1 << 6)
+
+#define BUTTON_POWER        (1 << 7)
+#define BUTTON_VOL_UP       (1 << 8)
+#define BUTTON_VOL_DOWN     (1 << 9)
+#define BUTTON_NEXT         (1 << 10)
+#define BUTTON_PREV         (1 << 11)
+#define BUTTON_PLAY         (1 << 12)
+
+#define BUTTON_MAIN (BUTTON_BACK|BUTTON_MENU|BUTTON_LEFT|BUTTON_RIGHT \
+                |BUTTON_UP|BUTTON_DOWN|BUTTON_SELECT|BUTTON_POWER \
+                |BUTTON_VOL_UP|BUTTON_VOL_DOWN|BUTTON_NEXT|BUTTON_PREV \
+                |BUTTON_PLAY)
+
+#define BUTTON_REMOTE 0
+
+#define POWEROFF_BUTTON BUTTON_POWER
+#define POWEROFF_COUNT 10
+
+#endif /* _BUTTON_TARGET_H_ */
diff --git a/firmware/target/arm/imx31/gigabeat-s/dma_start.c b/firmware/target/arm/imx31/gigabeat-s/dma_start.c
new file mode 100644
index 0000000000..c1ab6c15cb
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/dma_start.c
@@ -0,0 +1,8 @@
+#include <sys/types.h>
+
+void dma_start(const void* addr, size_t size) {
+  (void) addr;
+  (void) size;
+  //TODO:
+}
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
new file mode 100644
index 0000000000..7c608c172d
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
@@ -0,0 +1,51 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Michael Sevakis
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "system.h"
+#include "i2c-imx31.h"
+
+static int i2c_getack(void)
+{
+    return 0;
+}
+
+static int i2c_start(void)
+{
+    return 0;
+}
+
+static void i2c_stop(void)
+{
+}
+
+static int i2c_outb(unsigned char byte)
+{
+    (void)byte;
+    return 0;
+}
+
+void i2c_write(int addr, const unsigned char *buf, int count)
+{
+    (void)addr;
+    (void)*buf;
+    (void)count;
+}
+
+void i2c_init(void)
+{
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.h b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.h
new file mode 100644
index 0000000000..c708ebbfb4
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.h
@@ -0,0 +1,22 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Michael Sevakis
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+void i2c_init(void);
+void i2c_write(int addr, const unsigned char *data, int count);
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2s-imx31.c b/firmware/target/arm/imx31/gigabeat-s/i2s-imx31.c
new file mode 100644
index 0000000000..a8607babae
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/i2s-imx31.c
@@ -0,0 +1,22 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Michael Sevakis
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+void i2s_reset(void)
+{
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
new file mode 100644
index 0000000000..9df90a2344
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -0,0 +1,25 @@
+#include "kernel.h"
+#include "thread.h"
+
+#include <stdio.h>
+#include "lcd.h"
+
+extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
+
+void timer4(void) {
+        int i;
+    /* Run through the list of tick tasks */
+    for(i = 0; i < MAX_NUM_TICK_TASKS; i++)
+    {
+        if(tick_funcs[i])
+        {
+            tick_funcs[i]();
+        }
+    }
+
+    current_tick++;
+
+    /* following needs to be fixed.  */
+    /*wake_up_thread();*/
+}
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-as-imx31.S b/firmware/target/arm/imx31/gigabeat-s/lcd-as-imx31.S
new file mode 100644
index 0000000000..d431c95f29
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/lcd-as-imx31.S
@@ -0,0 +1,222 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Michael Sevakis
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "cpu.h"
+
+/****************************************************************************
+ * void lcd_write_yuv_420_lines(fb_data *dst,
+ *                              unsigned char chroma_buf[LCD_HEIGHT/2*3],
+                                unsigned char const * const src[3],
+ *                              int width,
+ *                              int stride);
+ *
+ *   |R|   |1.000000 -0.000001  1.402000| |Y'|
+ *   |G| = |1.000000 -0.334136 -0.714136| |Pb|
+ *   |B|   |1.000000  1.772000  0.000000| |Pr|
+ *   Scaled, normalized, rounded and tweaked to yield RGB 565:
+ *   |R|   |74   0 101| |Y' -  16| >> 9
+ *   |G| = |74 -24 -51| |Cb - 128| >> 8
+ *   |B|   |74 128   0| |Cr - 128| >> 9
+ */
+    .section    .icode, "ax", %progbits
+    .align      2
+    .global     lcd_write_yuv420_lines
+    .type       lcd_write_yuv420_lines, %function
+lcd_write_yuv420_lines:
+                                        @ r0   = dst
+                                        @ r1   = chroma_buf
+                                        @ r2   = yuv_src
+                                        @ r3   = width
+                                        @ [sp] = stride
+    stmdb       sp!, { r4-r12, lr }     @ save non-scratch
+    stmdb       sp!, { r0, r3 }         @ save dst and width
+    mov         r14, #74                @ r14 = Y factor
+    ldmia       r2, { r4, r5, r6 }      @ r4 = yuv_src[0] = Y'_p
+                                        @ r5 = yuv_src[1] = Cb_p
+                                        @ r6 = yuv_src[2] = Cr_p
+10: @ loop line 1                       @
+    ldrb        r2, [r4], #1            @ r2  = *Y'_p++;
+    ldrb        r8, [r5], #1            @ r8  = *Cb_p++;
+    ldrb        r11, [r6], #1           @ r11 = *Cr_p++;
+                                        @
+                                        @ compute Y
+    sub         r2, r2, #16             @ r7 = Y = (Y' - 16)*74
+    mul         r7, r2, r14             @
+                                        @
+    sub         r8, r8, #128            @ Cb -= 128
+    sub         r11, r11, #128          @ Cr -= 128
+                                        @
+    mvn         r2, #24                 @ compute guv
+    mul         r10, r2, r8             @ r10 = Cb*-24
+    mvn         r2, #51                 @
+    mla         r10, r2, r11, r10       @ r10 = r10 + Cr*-51
+                                        @
+    mov         r2, #101                @ compute rv
+    mul         r9, r11, r2             @ r9 = rv = Cr*101
+                                        @
+                                        @ store chromas in line buffer
+    add         r8, r8, #2              @ bu = (Cb + 2) >> 2
+    mov         r8, r8, asr #2          @ 
+    strb        r8, [r1], #1            @
+    add         r9, r9, #256            @ rv = (Cr + 256) >> 9
+    mov         r9, r9, asr #9          @
+    strb        r9, [r1], #1            @
+    mov         r10, r10, asr #8        @ guv >>= 8
+    strb        r10, [r1], #1           @
+                                        @ compute R, G, and B
+    add         r2, r8, r7, asr #9      @ r2  = b = (Y >> 9) + bu
+    add         r11, r9, r7, asr #9     @ r11 = r = (Y >> 9) + rv
+    add         r7, r10, r7, asr #8     @ r7  = g = (Y >> 8) + guv
+                                        @
+    orr         r12, r2, r11            @ check if clamping is needed...
+    orr         r12, r12, r7, asr #1    @ ...at all
+    cmp         r12, #31                @
+    bls         15f @ no clamp          @
+    mov         r12, #31                @
+    cmp         r12, r2                 @ clamp b
+    andlo       r2, r12, r2, asr #31    @
+    eorlo       r2, r2, r12             @
+    cmp         r12, r11                @ clamp r
+    andlo       r11, r12, r11, asr #31  @
+    eorlo       r11, r11, r12           @
+    cmp         r12, r7, asr #1         @ clamp g
+    andlo       r7, r12, r7, asr #31    @
+    eorlo       r7, r7, r12             @
+    orrlo       r7, r7, r7, asl #1      @
+15: @ no clamp                          @
+                                        @
+    orr         r12, r2, r7, lsl #5     @ r4 |= (g << 5)
+    ldrb        r2, [r4], #1            @ r2 = Y' = *Y'_p++
+    orr         r12, r12, r11, lsl #11  @ r4 = b | (r << 11)
+    strh        r12, [r0], #240         @ store pixel
+                                        @
+    sub         r2, r2, #16             @ r7 = Y = (Y' - 16)*74
+    mul         r7, r2, r14             @ next Y
+                                        @ compute R, G, and B
+    add         r2, r8, r7, asr #9      @ r2  = b = (Y >> 9) + bu
+    add         r11, r9, r7, asr #9     @ r11 = r = (Y >> 9) + rv
+    add         r7, r10, r7, asr #8     @ r7  = g = (Y >> 8) + guv
+                                        @
+    orr         r12, r2, r11            @ check if clamping is needed...
+    orr         r12, r12, r7, asr #1    @ ...at all
+    cmp         r12, #31                @
+    bls         15f @ no clamp          @
+    mov         r12, #31                @
+    cmp         r12, r2                 @ clamp b
+    andlo       r2, r12, r2, asr #31    @
+    eorlo       r2, r2, r12             @
+    cmp         r12, r11                @ clamp r
+    andlo       r11, r12, r11, asr #31  @
+    eorlo       r11, r11, r12           @
+    cmp         r12, r7, asr #1         @ clamp g
+    andlo       r7, r12, r7, asr #31    @
+    eorlo       r7, r7, r12             @
+    orrlo       r7, r7, r7, asl #1      @
+15: @ no clamp                          @
+                                        @
+    orr         r12, r2, r11, lsl #11   @ r4 = b | (r << 11)
+    orr         r12, r12, r7, lsl #5    @ r4 |= (g << 5)
+    strh        r12, [r0, #240]!        @ store pixel
+    add         r0, r0, #2*240          @
+                                        @
+    subs        r3, r3, #2              @
+    bgt         10b @ loop line 1       @
+                                        @ do second line
+                                        @
+    ldmia       sp!, { r0, r3 }         @ pop dst and width
+    sub         r0, r0, #2              @ set dst to start of next line
+    sub         r1, r1, r3, asl #1      @ rewind chroma pointer...
+    ldr         r2, [sp, #40]           @ r2 = stride
+    add         r1, r1, r3, asr #1      @ ... (r1 -= width/2*3)
+                                        @ move sources to start of next line
+    sub         r2, r2, r3              @ r2 = skip = stride - width
+    add         r4, r4, r2              @ r4 = Y'_p + skip
+                                        @
+20: @ loop line 2                       @
+    ldrb        r2, [r4], #1            @ r7 = Y' = *Y'_p++
+    ldrsb       r8, [r1], #1            @ reload saved chromas
+    ldrsb       r9, [r1], #1            @
+    ldrsb       r10, [r1], #1           @
+                                        @
+    sub         r2, r2, #16             @ r2 = Y = (Y' - 16)*74
+    mul         r7, r2, r14             @
+                                        @ compute R, G, and B
+    add         r2, r8, r7, asr #9      @ r2  = b = (Y >> 9) + bu
+    add         r11, r9, r7, asr #9     @ r11 = r = (Y >> 9) + rv
+    add         r7, r10, r7, asr #8     @ r7  = g = (Y >> 8) + guv
+                                        @
+    orr         r12, r2, r11            @ check if clamping is needed...
+    orr         r12, r12, r7, asr #1    @ ...at all
+    cmp         r12, #31                @
+    bls         25f @ no clamp          @
+    mov         r12, #31                @
+    cmp         r12, r2                 @ clamp b
+    andlo       r2, r12, r2, asr #31    @
+    eorlo       r2, r2, r12             @
+    cmp         r12, r11                @ clamp r
+    andlo       r11, r12, r11, asr #31  @
+    eorlo       r11, r11, r12           @
+    cmp         r12, r7, asr #1         @ clamp g
+    andlo       r7, r12, r7, asr #31    @
+    eorlo       r7, r7, r12             @
+    orrlo       r7, r7, r7, asl #1      @
+25: @ no clamp                          @
+                                        @
+    orr         r12, r2, r11, lsl #11   @ r4 = b | (r << 11)
+    ldrb        r2, [r4], #1            @ r2 = Y' = *Y'_p++
+    orr         r12, r12, r7, lsl #5    @ r4 |= (g << 5)
+    strh        r12, [r0], #240         @ store pixel
+                                        @
+                                        @ do second pixel
+                                        @
+    sub         r2, r2, #16             @ r2 = Y = (Y' - 16)*74
+    mul         r7, r2, r14             @
+                                        @ compute R, G, and B
+    add         r2, r8, r7, asr #9      @ r2  = b = (Y >> 9) + bu
+    add         r11, r9, r7, asr #9     @ r11 = r = (Y >> 9) + rv
+    add         r7, r10, r7, asr #8     @ r7  = g = (Y >> 8) + guv
+                                        @
+    orr         r12, r2, r11            @ check if clamping is needed...
+    orr         r12, r12, r7, asr #1    @ ...at all
+    cmp         r12, #31                @
+    bls         25f @ no clamp          @
+    mov         r12, #31                @
+    cmp         r12, r2                 @ clamp b
+    andlo       r2, r12, r2, asr #31    @
+    eorlo       r2, r2, r12             @
+    cmp         r12, r11                @ clamp r
+    andlo       r11, r12, r11, asr #31  @
+    eorlo       r11, r11, r12           @
+    cmp         r12, r7, asr #1         @ clamp g
+    andlo       r7, r12, r7, asr #31    @
+    eorlo       r7, r7, r12             @
+    orrlo       r7, r7, r7, asl #1      @
+25: @ no clamp                          @
+                                        @
+    orr         r12, r2, r11, lsl #11   @ r4 = b | (r << 11)
+    orr         r12, r12, r7, lsl #5    @ r4 |= (g << 5)
+    strh        r12, [r0, #240]!        @ store pixel
+    add         r0, r0, #2*240          @
+                                        @
+    subs        r3, r3, #2              @
+    bgt         20b @ loop line 2       @
+                                        @
+    ldmia       sp!, { r4-r12, pc }     @ restore registers and return
+    .size   lcd_write_yuv420_lines, .-lcd_write_yuv420_lines
diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c b/firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c
new file mode 100644
index 0000000000..c9cce6d653
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/lcd-imx31.c
@@ -0,0 +1,230 @@
+#include "config.h"
+#include "cpu.h"
+#include "string.h"
+#include "lcd.h"
+#include "kernel.h"
+#include "lcd-target.h"
+
+#define LCDADDR(x, y) (&lcd_framebuffer[(y)][(x)])
+
+static volatile bool lcd_on = true;
+volatile bool lcd_poweroff = false;
+/*
+** These are imported from lcd-16bit.c
+*/
+extern unsigned fg_pattern;
+extern unsigned bg_pattern;
+
+#if 0
+bool lcd_enabled()
+{
+    return lcd_on;
+}
+#endif
+
+void printscreen(unsigned int colour) {
+    int i;
+    int base = 0x84100000;
+    for(i=0;i<(320*240*2);i++) {
+        writel(colour,base);
+        base++;
+    }
+}
+
+unsigned int LCDBANK(unsigned int address)
+{
+    return ((address >> 22) & 0xff);
+}
+
+unsigned int LCDBASEU(unsigned int address)
+{
+    return (address & ((1 << 22)-1)) >> 1;
+}
+
+unsigned int LCDBASEL(unsigned int address)
+{
+    address += 320*240*2;
+    return (address & ((1 << 22)-1)) >> 1;
+}
+
+
+/* LCD init */
+void lcd_init_device(void)
+{
+    int i;
+#ifdef BOOTLOADER
+    /* When the Rockbox bootloader starts, we are changing framebuffer address,
+       but we don't want what's shown on the LCD to change until we do an
+       lcd_update(), so copy the data from the old framebuffer to the new one */
+    unsigned short *buf = (unsigned short*)FRAME1;
+        
+    memcpy(FRAME1, (short *)((LCDSADDR1)<<1), 320*240*2);
+
+    /* The Rockbox bootloader is transitioning from RGB555I to RGB565 mode
+       so convert the frambuffer data accordingly */
+    for(i=0; i< 320*240; i++){
+        *buf = ((*buf>>1) & 0x1F) | (*buf & 0xffc0);
+        buf++;
+    }
+    return;
+#endif
+}
+
+/* Update a fraction of the display. */
+void lcd_update_rect(int x, int y, int width, int height)
+{
+    (void)x;
+    (void)width;
+    (void)y;
+    (void)height;
+
+    if(!lcd_on)
+    {
+        sleep(200);
+        return;
+    }
+    memcpy(((char*)FRAME2) + (y * sizeof(fb_data) * LCD_WIDTH), ((char *)&lcd_framebuffer) + (y * sizeof(fb_data) * LCD_WIDTH), ((height * sizeof(fb_data) * LCD_WIDTH)));
+}
+
+void lcd_enable(bool state)
+{
+    (void)state;
+}
+
+bool lcd_enabled(void)
+{
+    return true;
+}
+
+/* Update the display.
+   This must be called after all other LCD functions that change the display. */
+void lcd_update(void)
+{
+    lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
+}
+
+void lcd_bitmap_transparent_part(const fb_data *src, int src_x, int src_y,
+                                 int stride, int x, int y, int width,
+                                 int height)
+{
+    fb_data *dst, *dst_end;
+    unsigned int transcolor;
+
+    /* nothing to draw? */
+    if ((width <= 0) || (height <= 0) || (x >= LCD_WIDTH) || (y >= LCD_HEIGHT)
+        || (x + width <= 0) || (y + height <= 0))
+        return;
+
+    /* clipping */
+    if (x < 0)
+    {
+        width += x;
+        src_x -= x;
+        x = 0;
+    }
+    if (y < 0)
+    {
+        height += y;
+        src_y -= y;
+        y = 0;
+    }
+    if (x + width > LCD_WIDTH)
+        width = LCD_WIDTH - x;
+    if (y + height > LCD_HEIGHT)
+        height = LCD_HEIGHT - y;
+
+    src += stride * src_y + src_x; /* move starting point */
+    dst = &lcd_framebuffer[(y)][(x)];
+    dst_end = dst + height * LCD_WIDTH;
+    width *= 2;
+    stride *= 2;
+    transcolor = TRANSPARENT_COLOR;
+    asm volatile(
+    "rowstart:  \n"
+        "mov    r0, #0  \n"
+    "nextpixel:  \n"
+        "ldrh   r1, [%0, r0]   \n"  /* Load word src+r0 */
+        "cmp    r1, %5 \n"             /* Compare to transparent color */
+        "strneh r1, [%1, r0]   \n"  /* Store dst+r0 if not transparent */
+        "add    r0, r0, #2  \n"
+        "cmp    r0, %2 \n"             /* r0 == width? */         
+        "bne    nextpixel \n"        /* More in this row? */
+        "add    %0, %0, %4  \n"     /* src += stride */
+        "add    %1, %1, #480 \n"    /* dst += LCD_WIDTH (x2) */
+        "cmp    %1, %3 \n"             
+        "bne    rowstart \n"        /* if(dst != dst_end), keep going */
+        : : "r" (src), "r" (dst), "r" (width), "r" (dst_end), "r" (stride), "r" (transcolor) : "r0", "r1" );
+}
+
+/* Line write helper function for lcd_yuv_blit. Write two lines of yuv420. */
+extern void lcd_write_yuv420_lines(fb_data *dst,
+                                   unsigned char chroma_buf[LCD_HEIGHT/2*3],
+                                   unsigned char const * const src[3],
+                                   int width,
+                                   int stride);
+/* Performance function to blit a YUV bitmap directly to the LCD */
+/* For the Gigabeat - show it rotated */
+/* So the LCD_WIDTH is now the height */
+void lcd_yuv_blit(unsigned char * const src[3],
+                  int src_x, int src_y, int stride,
+                  int x, int y, int width, int height)
+{
+    /* Caches for chroma data so it only need be recaculated every other
+       line */
+    unsigned char chroma_buf[LCD_HEIGHT/2*3]; /* 480 bytes */
+    unsigned char const * yuv_src[3];
+    off_t z;
+
+    if (!lcd_on)
+        return;
+
+    /* Sorry, but width and height must be >= 2 or else */
+    width &= ~1;
+    height >>= 1;
+
+    fb_data *dst = (fb_data*)FRAME1 + x * LCD_WIDTH + (LCD_WIDTH - y) - 1;
+
+    z = stride*src_y;
+    yuv_src[0] = src[0] + z + src_x;
+    yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1);
+    yuv_src[2] = src[2] + (yuv_src[1] - src[1]);
+
+    do
+    {
+        lcd_write_yuv420_lines(dst, chroma_buf, yuv_src, width,
+                               stride);
+        yuv_src[0] += stride << 1; /* Skip down two luma lines */
+        yuv_src[1] += stride >> 1; /* Skip down one chroma line */
+        yuv_src[2] += stride >> 1;
+        dst -= 2;
+    }
+    while (--height > 0);
+}
+
+void lcd_set_contrast(int val) {
+  (void) val;
+  // TODO:
+}
+
+void lcd_set_invert_display(bool yesno) {
+  (void) yesno;
+  // TODO:
+}
+
+void lcd_blit(const fb_data* data, int bx, int y, int bwidth,
+              int height, int stride)
+{
+  (void) data;
+  (void) bx;
+  (void) y;
+  (void) bwidth;
+  (void) height;
+  (void) stride;
+  //TODO:
+}
+
+void lcd_set_flip(bool yesno) {
+  (void) yesno;
+  // TODO:
+}
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-target.h b/firmware/target/arm/imx31/gigabeat-s/lcd-target.h
new file mode 100644
index 0000000000..48e304752c
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/lcd-target.h
@@ -0,0 +1,21 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id $
+ *
+ * Copyright (C) 2007 by Greg White
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+//extern void lcd_enable(bool state);
+void printscreen(unsigned int colour);
diff --git a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c
new file mode 100644
index 0000000000..ee86ccc95c
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.c
@@ -0,0 +1,237 @@
+#include <string.h>
+#include "mmu-imx31.h"
+#include "cpu.h"
+
+static void enable_mmu(void);
+static void set_ttb(void);
+static void set_page_tables(void);
+static void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags);
+
+#define SECTION_ADDRESS_MASK (-1 << 20)
+#define CACHE_ALL (1 << 3 | 1 << 2 )
+#define CACHE_NONE 0
+#define BUFFERED (1 << 2)
+#define MB (1 << 20)
+
+void memory_init(void) {
+    set_ttb();
+    set_page_tables();
+    enable_mmu();
+}
+
+unsigned int* ttb_base = (unsigned int *) TTB_BASE;
+const int ttb_size = 4096;
+
+void set_ttb() {
+    int i;
+    int* ttbPtr;
+    int domain_access;
+
+    /* must be 16Kb (0x4000) aligned */
+    ttb_base = (int*) TTB_BASE;
+    for (i=0; i<ttb_size; i++,ttbPtr++)
+    ttbPtr = 0;
+    asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb_base));
+
+    /* set domain D0 to "client" permission access */
+
+    domain_access = 3;
+    asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (domain_access));
+
+}
+
+void set_page_tables() {
+
+    map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */
+        /*This pa *might* change*/
+    map_section(0x80000000, 0, 64, CACHE_ALL); /* map RAM to 0 and enable caching for it */
+    map_section((int)FRAME1, (int)FRAME1, 1, BUFFERED); /* enable buffered writing for the framebuffer */
+        map_section((int)FRAME2, (int)FRAME2, 1, BUFFERED);
+}
+
+void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) {
+    unsigned int* ttbPtr;
+    int i;
+    int section_no;
+
+    section_no = va >> 20; /* sections are 1Mb size */
+    ttbPtr = ttb_base + section_no;
+    pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */
+    for(i=0; i<mb; i++, pa += MB) {
+    *(ttbPtr + i) =
+        pa |
+        1 << 10 |    /* superuser - r/w, user - no access */
+        0 << 5 |    /* domain 0th */
+        1 << 4 |    /* should be "1" */
+        cache_flags |
+        1 << 1;    /* Section signature */
+    }
+}
+
+static void enable_mmu(void) {
+    int regread;
+
+    asm volatile(
+        "MRC p15, 0, %r0, c1, c0, 0\n"  /* Read reg1, control register */
+    : /* outputs */
+        "=r"(regread)
+    : /* inputs */
+    : /* clobbers */
+        "r0"
+    );
+
+    if ( !(regread & 0x04) || !(regread & 0x00001000) ) /* Was the ICache or DCache Enabled? */
+        clean_dcache(); /* If so we need to clean the DCache before invalidating below */
+
+    asm volatile("mov r0, #0\n"
+        "mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */
+
+        "mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */
+
+        "mrc p15, 0, r0, c1, c0, 0\n"
+        "orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */
+        "orr r0, r0, #1<<2\n" /* enable dcache */
+        "orr r0, r0, #1<<12\n" /* enable icache */
+        "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
+    asm volatile("nop \n nop \n nop \n nop");
+}
+
+/* Invalidate DCache for this range  */
+/* Will do write back */
+void invalidate_dcache_range(const void *base, unsigned int size) {
+    unsigned int addr = (((int) base) & ~31);    /* Align start to cache line*/
+    unsigned int end = ((addr+size) & ~31)+64;  /* Align end to cache line, pad */
+    asm volatile(
+"inv_start: \n"
+    "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "add %0, %0, #32 \n"
+    "cmp %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
+    "addne %0, %0, #32 \n"
+    "cmpne %0, %1 \n"
+    "bne inv_start \n"
+    "mov %0, #0\n"
+    "mcr p15,0,%0,c7,c10,4\n"    /* Drain write buffer */
+        : : "r" (addr), "r" (end));
+}
+
+/* clean DCache for this range  */
+/* forces DCache writeback for the specified range */
+void clean_dcache_range(const void *base, unsigned int size) {
+    unsigned int addr = (int) base;
+    unsigned int end = addr+size+32;
+    asm      volatile(
+    "bic %0, %0, #31 \n"
+"clean_start: \n"
+    "mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "add %0, %0, #32 \n"
+    "cmp %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
+    "addlo %0, %0, #32 \n"
+    "cmplo %0, %1 \n"
+    "blo clean_start \n"
+    "mov %0, #0\n"
+    "mcr p15,0,%0,c7,c10,4 \n"    /* Drain write buffer */
+        : : "r" (addr), "r" (end));
+}
+
+/* Dump DCache for this range  */
+/* Will *NOT* do write back */
+void dump_dcache_range(const void *base, unsigned int size) {
+    unsigned int addr = (int) base;
+    unsigned int end = addr+size;
+    asm volatile(
+    "tst %0, #31 \n"                    /* Check to see if low five bits are set */
+    "bic %0, %0, #31 \n"                /* Clear them */
+    "mcrne p15, 0, %0, c7, c14, 1 \n"     /* Clean and invalidate this line, if those bits were set */
+    "add %0, %0, #32 \n"                /* Move to the next cache line */
+    "tst %1, #31 \n"                    /* Check last line for bits set */
+    "bic %1, %1, #31 \n"                /* Clear those bits */
+    "mcrne p15, 0, %1, c7, c14, 1 \n"     /* Clean and invalidate this line, if not cache aligned */
+"dump_start: \n"
+    "mcr p15, 0, %0, c7, c6, 1 \n"         /* Invalidate this line */
+    "add %0, %0, #32 \n"                /* Next cache line */
+    "cmp %0, %1 \n"
+    "bne dump_start \n"
+"dump_end: \n"
+    "mcr p15,0,%0,c7,c10,4 \n"    /* Drain write buffer */
+        : : "r" (addr), "r" (end));
+}
+/* Cleans entire DCache */
+void clean_dcache(void)
+{
+    unsigned int index, addr;
+
+    for(index = 0; index <= 63; index++) {
+        addr = (0 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (1 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (2 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (3 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (4 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (5 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (6 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+        addr = (7 << 5) | (index << 26);
+        asm volatile(
+            "mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
+            : : "r" (addr));
+    }
+}
+
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h
new file mode 100644
index 0000000000..524978852d
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/mmu-imx31.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006,2007 by Greg White
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Invalidate DCache for this range  */
+/* Will do write back */
+void invalidate_dcache_range(const void *base, unsigned int size);
+
+/* clean DCache for this range  */
+/* forces DCache writeback for the specified range */
+void clean_dcache_range(const void *base, unsigned int size);
+
+/* Dump DCache for this range  */
+/* Will *NOT* do write back */
+void dump_dcache_range(const void *base, unsigned int size);
+
+/* Cleans entire DCache */
+void clean_dcache(void);
+
+void memory_init(void);
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
new file mode 100644
index 0000000000..73bd9fef14
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
@@ -0,0 +1,93 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Michael Sevakis
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <stdlib.h>
+#include "system.h"
+#include "kernel.h"
+#include "logf.h"
+#include "audio.h"
+#include "sound.h"
+#include "file.h"
+#include "mmu-imx31.h"
+
+void fiq_handler(void) __attribute__((naked));
+
+static void _pcm_apply_settings(void)
+{
+}
+
+void pcm_apply_settings(void)
+{
+}
+
+void pcm_init(void)
+{
+}
+
+void pcm_postinit(void)
+{
+}
+
+void pcm_play_dma_start(const void *addr, size_t size)
+{
+    (void)addr;
+    (void)size;
+}
+
+static void pcm_play_dma_stop_fiq(void)
+{
+}
+
+void fiq_handler(void)
+{
+}
+
+/* Disconnect the DMA and wait for the FIFO to clear */
+void pcm_play_dma_stop(void)
+{
+}
+
+void pcm_play_pause_pause(void)
+{
+}
+
+void pcm_play_pause_unpause(void)
+{
+}
+
+void pcm_set_frequency(unsigned int frequency)
+{
+    (void)frequency;
+}
+
+size_t pcm_get_bytes_waiting(void)
+{
+}
+
+void pcm_mute(bool mute)
+{
+}
+
+/**
+ * Return playback peaks - Peaks ahead in the DMA buffer based upon the
+ *                         calling period to attempt to compensate for
+ *                         delay.
+ */
+void pcm_calculate_peaks(int *left, int *right)
+{
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/power-imx31.c b/firmware/target/arm/imx31/gigabeat-s/power-imx31.c
new file mode 100644
index 0000000000..c739a19cba
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/power-imx31.c
@@ -0,0 +1,81 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "cpu.h"
+#include <stdbool.h>
+#include "kernel.h"
+#include "system.h"
+#include "power.h"
+#include "pcf50606.h"
+#include "backlight.h"
+#include "backlight-target.h"
+
+#ifndef SIMULATOR
+
+void power_init(void)
+{
+}
+
+bool charger_inserted(void)
+{
+    return false;
+}
+
+/* Returns true if the unit is charging the batteries. */
+bool charging_state(void) {
+    return false;
+}
+
+void ide_power_enable(bool on)
+{
+    (void)on;
+}
+
+bool ide_powered(void)
+{
+    return true;
+}
+
+void power_off(void)
+{
+}
+
+#else /* SIMULATOR */
+
+bool charger_inserted(void)
+{
+    return false;
+}
+
+void charger_enable(bool on)
+{
+    (void)on;
+}
+
+void power_off(void)
+{
+}
+
+void ide_power_enable(bool on)
+{
+   (void)on;
+}
+
+#endif /* SIMULATOR */
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/powermgmt-imx31.c b/firmware/target/arm/imx31/gigabeat-s/powermgmt-imx31.c
new file mode 100644
index 0000000000..7441100a7d
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/powermgmt-imx31.c
@@ -0,0 +1,60 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2002 by Heikki Hannikainen, Uwe Freese
+ * Revisions copyright (C) 2005 by Gerald Van Baren
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* FIXME: This is just the Gigabeat F/X file with a different name... */
+
+#include "config.h"
+#include "adc.h"
+#include "powermgmt.h"
+
+const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] =
+{
+    3450
+};
+
+const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] =
+{
+    3400
+};
+
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging disabled */
+const unsigned short percent_to_volt_discharge[BATTERY_TYPES_COUNT][11] =
+{
+    /* Toshiba Gigabeat Li Ion 830mAH figured from discharge curve */
+    { 3480, 3550, 3590, 3610, 3630, 3650, 3700, 3760, 3800, 3910, 3990 },
+};
+
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging enabled */
+const unsigned short percent_to_volt_charge[11] =
+{
+    /* Toshiba Gigabeat Li Ion 830mAH */
+    3480, 3550, 3590, 3610, 3630, 3650, 3700, 3760, 3800, 3910, 3990
+};
+
+/* ADC[0] is (530) at discharge and 625 at full charge */
+#define BATTERY_SCALE_FACTOR 6605
+/* full-scale ADC readout (2^10) in millivolt */
+
+/* Returns battery voltage from ADC [millivolts] */
+unsigned int battery_adc_voltage(void)
+{
+    return (adc_read(ADC_UNREG_POWER) * BATTERY_SCALE_FACTOR) >> 10;
+}
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/serial-imx31.h b/firmware/target/arm/imx31/gigabeat-s/serial-imx31.h
new file mode 100644
index 0000000000..62babe0abf
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/serial-imx31.h
@@ -0,0 +1,12 @@
+#ifndef SERIAL_IMX31_H
+#define SERIAL_IMX31_H
+
+#include <stdarg.h>
+#include <stdio.h>
+
+int Tx_Rdy(void);
+void Tx_Writec(const char c);
+void dprintf(const char * str, ... );
+
+#endif
+
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
new file mode 100644
index 0000000000..7d6e8efd22
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
@@ -0,0 +1,81 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (c) 2007 Will Robertson
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "cpu.h"
+#include "spi-imx31.h"
+#include "debug.h"
+#include "kernel.h"
+
+    /* This is all based on communicating with the MC13783 PMU which is on 
+     * CSPI2 with the chip select at 0. The LCD controller resides on
+     * CSPI3 cs1, but we have no idea how to communicate to it */
+
+void spi_init(void) {
+    CSPI_CONREG2 |= (2 << 20);      // Burst will be triggered at SPI_RDY low
+    CSPI_CONREG2 |= (2 << 16);      // Clock = IPG_CLK/16  - we want about 20mhz
+    CSPI_CONREG2 |= (31 << 8);      // All 32 bits are to be transferred
+    CSPI_CONREG2 |= (1 << 3);       // Start burst on TXFIFO write.
+    CSPI_CONREG2 |= (1 << 1);       // Master mode.
+    CSPI_CONREG2 |= 1;              // Enable CSPI2;
+}
+
+static int spi_transfer(int address, long data, long* buffer, bool read) {
+    unsigned long packet = 0;
+    if(!read) {
+        /* Set the appropriate bit in the packet to indicate a write */
+        packet |= (1<<31);
+    }
+    /* Set the address of the packet */
+    packet |= (address << 25);
+
+    /* Ensure data only occupies 24 bits, then mash the data into the packet */
+    data &= ~(DATAMASK);
+    packet |= data;
+
+    /* Wait for some room in TXFIFO */
+    while(CSPI_STATREG2 & (1<<2));
+
+    /* Send the packet */
+    CSPI_TXDATA2 = packet;
+
+    /* Poll the XCH bit to wait for the end of the transfer, with
+     * a one second timeout */
+    int newtick = current_tick + HZ;
+    while((CSPI_CONREG2 & (1<<2)) && (current_tick < newtick));
+
+    if(newtick > current_tick) {
+        *buffer = CSPI_RXDATA2;
+        return 0;
+    } else {
+        /* Indicate the fact that the transfer timed out */
+        return -1;
+    }
+}
+
+void spi_send(int address, unsigned long data) {
+    long dummy;
+    if(spi_transfer(address, data, &dummy, false)) {
+        DEBUGF("SPI Send timed out");
+    }
+}
+
+void spi_read(int address, unsigned long* buffer) {
+    if(spi_transfer(address, 0, buffer, true)) {
+        DEBUGF("SPI read timed out");
+    }
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.h b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.h
new file mode 100644
index 0000000000..5f6cfc984f
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.h
@@ -0,0 +1,23 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (c) 2007 Will Robertson
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#define DATAMASK 0xFF000000
+
+void spi_init(void);
+void spi_send(int address, unsigned long data);
+void spi_read(int address, unsigned long* buffer);
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
new file mode 100644
index 0000000000..544ae3afe6
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
@@ -0,0 +1,93 @@
+#include "kernel.h"
+#include "system.h"
+#include "panic.h"
+#include "mmu-imx31.h"
+#include "system-target.h"
+#include "lcd.h"
+#include "serial-imx31.h"
+#include "debug.h"
+
+int system_memory_guard(int newmode)
+{
+    (void)newmode;
+    return 0;
+}
+
+extern void timer4(void);
+extern void dma0(void); /* free */
+extern void dma1(void);
+extern void dma3(void);
+
+void irq_handler(void)
+{
+}
+
+#ifdef BOOTLOADER
+void fiq_handler(void)
+{
+}
+#endif
+
+void system_reboot(void)
+{
+}
+
+void system_init(void)
+{
+}
+
+inline void dumpregs(void) 
+{
+        asm volatile ("mov %0,r0\n\t"
+                                  "mov %1,r1\n\t"
+                                  "mov %2,r2\n\t"
+                                  "mov %3,r3":
+                                  "=r"(regs.r0),"=r"(regs.r1),
+                                  "=r"(regs.r2),"=r"(regs.r3):);
+
+    asm volatile ("mov %0,r4\n\t"
+                                  "mov %1,r5\n\t"
+                                  "mov %2,r6\n\t"
+                                  "mov %3,r7":
+                                  "=r"(regs.r4),"=r"(regs.r5),
+                                  "=r"(regs.r6),"=r"(regs.r7):);
+
+    asm volatile ("mov %0,r8\n\t"
+                                  "mov %1,r9\n\t"
+                                  "mov %2,r10\n\t"
+                                  "mov %3,r12":
+                                  "=r"(regs.r8),"=r"(regs.r9),
+                                  "=r"(regs.r10),"=r"(regs.r11):);
+  
+        asm volatile ("mov %0,r12\n\t"
+                                   "mov %1,sp\n\t"
+                                   "mov %2,lr\n\t"
+                                   "mov %3,pc\n"
+                                   "sub %3,%3,#8":
+                                   "=r"(regs.r12),"=r"(regs.sp),
+                                   "=r"(regs.lr),"=r"(regs.pc):);
+#ifdef HAVE_SERIAL
+    dprintf("Register Dump :\n");
+        dprintf("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
+    dprintf("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
+        dprintf("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
+        dprintf("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
+        //dprintf("CPSR=0x%x\t\n",regs.cpsr);
+#endif
+        DEBUGF("Register Dump :\n");
+        DEBUGF("R0=0x%x\tR1=0x%x\tR2=0x%x\tR3=0x%x\n",regs.r0,regs.r1,regs.r2,regs.r3);
+    DEBUGF("R4=0x%x\tR5=0x%x\tR6=0x%x\tR7=0x%x\n",regs.r4,regs.r5,regs.r6,regs.r7);
+        DEBUGF("R8=0x%x\tR9=0x%x\tR10=0x%x\tR11=0x%x\n",regs.r8,regs.r9,regs.r10,regs.r11);
+        DEBUGF("R12=0x%x\tSP=0x%x\tLR=0x%x\tPC=0x%x\n",regs.r12,regs.sp,regs.lr,regs.pc);
+        //DEBUGF("CPSR=0x%x\t\n",regs.cpsr);
+    
+ }
+
+#ifdef HAVE_ADJUSTABLE_CPU_FREQ
+
+void set_cpu_frequency(long frequency)
+{
+    (void)freqency;
+}
+
+#endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
new file mode 100644
index 0000000000..b1803d01cb
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -0,0 +1,61 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Greg White
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef SYSTEM_TARGET_H
+#define SYSTEM_TARGET_H
+
+#include "mmu-imx31.h"
+#include "system-arm.h"
+
+#define CPUFREQ_NORMAL 532000000
+
+static inline void udelay(unsigned int usecs)
+{
+    volatile signed int stop = EPITCNT1 - usecs;
+    while (EPITCNT1 > stop);
+}
+
+
+#define HAVE_INVALIDATE_ICACHE
+static inline void invalidate_icache(void)
+{
+}
+
+struct ARM_REGS {
+        int r0;
+        int r1;
+        int r2;
+        int r3;
+        int r4;
+        int r5;
+        int r6;
+        int r7;
+        int r8;
+        int r9;
+        int r10;
+        int r11;
+        int r12;
+        int sp;
+        int lr;
+        int pc;
+        int cpsr;
+} regs;
+
+inline void dumpregs(void);
+
+#endif /* SYSTEM_TARGET_H */
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
new file mode 100644
index 0000000000..94b5c82791
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
@@ -0,0 +1,37 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "cpu.h"
+#include "system.h"
+#include "kernel.h"
+#include "ata.h"
+
+inline int usb_detect(void)
+{
+    return 0;
+}
+
+void usb_init_device(void)
+{
+}
+
+void usb_enable(bool on)
+{
+    (void)on;
+}
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-target.h b/firmware/target/arm/imx31/gigabeat-s/usb-target.h
new file mode 100644
index 0000000000..de5bdac52b
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/usb-target.h
@@ -0,0 +1,26 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef USB_TARGET_H
+#define USB_TARGET_H
+
+bool usb_init_device(void);
+int usb_detect(void);
+void usb_enable(bool on);
+
+#endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
new file mode 100644
index 0000000000..238ee3aeb2
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
@@ -0,0 +1,39 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Gigabeat specific code for the Wolfson codec
+ *
+ * Based on code from the ipodlinux project - http://ipodlinux.org/
+ * Adapted for Rockbox in December 2005
+ *
+ * Original file: linux/arch/armnommu/mach-ipod/audio.c
+ *
+ * Copyright (c) 2003-2005 Bernard Leach (leachbj@bouncycastle.org)
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "cpu.h"
+#include "kernel.h"
+#include "sound.h"
+#include "i2c-imx31.h"
+
+void audiohw_init(void)
+{
+}
+
+void wmcodec_write(int reg, int data)
+{
+    (void)reg;
+    (void)data;
+}
diff --git a/tools/Makefile b/tools/Makefile
index b7f445ebf6..74d82affab 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -16,13 +16,14 @@ CLEANALL := scramble descramble iriver sh2d bmp2rb rdf2binary convbdf	\
 all:
         @echo "Run make in your build directory!"
 
-scramble: scramble.o iriver.o mi4.o gigabeat.o
+scramble: scramble.o iriver.o mi4.o gigabeat.o gigabeats.o
 descramble: descramble.o iriver.o gigabeat.o
 
 scramble.o: scramble.c iriver.h mi4.h gigabeat.h
 descramble.o: descramble.c iriver.h gigabeat.h
 iriver.o: iriver.c iriver.h
 gigabeat.o: gigabeat.c gigabeat.h
+gigabeats.o: gigabeats.c gigabeats.h
 mi4.o: mi4.c mi4.h
 
 sh2d: sh2d.c
diff --git a/tools/configure b/tools/configure
index 63e5512c01..73e6a50e79 100755
--- a/tools/configure
+++ b/tools/configure
@@ -615,7 +615,7 @@ cat <<EOF
 
  ==iAudio==            ==Toshiba==            ==SanDisk==
  30) X5/X5V/X5L        40) Gigabeat F         50) Sansa e200
- 31) M5/M5L                                   51) Sansa e200R
+ 31) M5/M5L            41) Gigabeat S         51) Sansa e200R
                                               52) Sansa c200
 
  ==Tatung==            ==Olympus==
@@ -1257,6 +1257,30 @@ EOF
     t_model="gigabeat-fx"
     ;;
 
+    41|gigabeats)
+    target_id=26
+    archos="gigabeats"
+    target="-DGIGABEAT_S"
+    memory=32 # always
+    arm9tdmicc
+    tool="$rootdir/tools/scramble -add=gigs"
+    bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
+    bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
+    output="rockbox.gigabeat"
+    appextra="recorder:gui"
+    archosrom=""
+    flash=""
+    plugins="yes"
+    codecs="libmad liba52 libffmpegFLAC libwma libTremor libwavpack libmusepack libalac libfaad libm4a libspeex libdemac"
+    toolset=$gigabeatbitmaptools
+    boottool="$rootdir/tools/scramble -gigabeats"
+    bootoutput="nk.bin"
+    # architecture, manufacturer and model for the target-tree build
+    t_cpu="arm"
+    t_manufacturer="imx31"
+    t_model="gigabeat-s"
+    ;;
+
     70|mrobe500)
     target_id=20
     archos="mrobe500"
@@ -1349,7 +1373,7 @@ EOF
     appextra="recorder:gui"
     archosrom=""
     flash=""
-    plugins="yes"
+    plugins=""
     swcodec="yes"
     boottool="$rootdir/tools/scramble -mi4v3 -model=c200 -type=RBBL"
     bootoutput="firmware.mi4"
@@ -1387,7 +1411,7 @@ EOF
     t_manufacturer="tatung"
     t_model="tpj1022"
     ;;
-
+    
    *)
     echo "Please select a supported target platform!"
     exit
diff --git a/tools/gigabeats.c b/tools/gigabeats.c
new file mode 100644
index 0000000000..0d60eae781
--- /dev/null
+++ b/tools/gigabeats.c
@@ -0,0 +1,171 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Will Robertson
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+
+static FILE * openinfile( const char * filename )
+{
+    FILE * F = fopen( filename, "rb" );
+    if( F == NULL )
+    {
+        fprintf( stderr, "Couldn't open input file %s\n", filename );
+        perror( "Error was " );
+        exit( -1 );
+    };
+    return F;
+};
+
+static FILE * openoutfile( const char * filename )
+{
+    FILE * F = fopen( filename, "wb" );
+    if( F == NULL )
+    {
+        fprintf( stderr, "Couldn't open output file %s\n", filename );
+        perror( "Error was " );
+        exit( -1 );
+    };
+    return F;
+};
+
+unsigned long calc_csum(const unsigned char* pb, int cb)
+{
+    unsigned long l = 0;
+    while (cb--)
+        l += *pb++;
+    return l;
+}
+
+int gigabeat_s_code(char *infile, char *outfile)
+{
+    FILE *in, *out;
+    unsigned long size = 0;
+    unsigned long data;
+    int imagelength;
+
+    in = openinfile(infile);
+    out = openoutfile(outfile);
+
+    fseek(in, 0, SEEK_END);
+    size = ftell(in);
+    fseek(in, 0, SEEK_SET);
+    unsigned long *binptr = malloc(size);
+    if(binptr == NULL) {
+        fprintf(stderr, "Not enough memory to perform the requested operation. Aborting.\n" );
+        return 0;
+    }
+    fread(binptr, size/4, 4, in);
+    /* 15 bytes for header, three 12 byte headers, the data for the first three
+     * records, 12 byte header for code, code and the 12 byte footer
+     * However, the original nk.bin's length doesn't correspond with
+     * the length of the file, so I don't know what's up...
+     */
+
+    unsigned long header[2];
+    header[0] = 0x88200000;
+    /* header[1] = 15 + 12 + 4 + 12 + 8 + 12 + 4 + 12 + size + 12; */
+    header[1] = 0xCC0CD8; /* The bootloader checks this value and compares */
+    fwrite("B000FF\n", 7, 1, out);
+    fwrite(header, sizeof(header), 1, out);
+    
+    unsigned long record[4];
+    unsigned long extra;
+
+    /*First record*/
+    record[0] = 0x88200000;
+    record[1] = 4;
+    record[2] = 0x1eb;
+    record[3] = 0xEA0003FE;
+    fwrite(record, sizeof(record), 1, out);
+
+    /*Second record*/
+    record[0] = 0x88200040;
+    record[1] = 8;
+    record[2] = 0x3e9;
+    record[3] = 0x43454345;
+    extra = 0x88EBF274;
+    fwrite(record, sizeof(record), 1, out);
+    fwrite(&extra, sizeof(extra), 1, out);
+
+    /*Third record*/
+    record[0] = 0x88200048;
+    record[1] = 4;
+    record[2] = 0x231;
+    record[3] = 0x00CBF274;
+    fwrite(record, sizeof(record), 1, out);
+
+    /*Signature bypass record*/
+    unsigned long magic = 0xE3A00001;
+    record[0] = 0x88065A10;
+    record[1] = 4;
+    record[2] = calc_csum((unsigned char*)&magic,4);
+    record[3] = magic;
+    fwrite(record, sizeof(record), 1, out);
+
+    /*The actual code*/
+    header[0] = 0x88201000;
+    header[1] = size;
+    extra = calc_csum((unsigned char*)binptr, size);
+    fwrite(header, sizeof(header), 1, out);
+    fwrite(&extra, sizeof(extra), 1, out);
+    fwrite(binptr, size, 1, out);
+
+    /* Table of contents. It's a start, but it still won't boot.
+     * Looks like it needs the file/module info as well... */
+    binptr[0] = 0x02000000;
+    binptr[1] = 0x02000000;
+    binptr[2] = 0x88040000;
+    binptr[3] = 0x88076338;
+    binptr[4] = 0x1;
+    binptr[5] = 0x88080000;
+    binptr[6] = 0x8809C000;
+    binptr[7] = 0x88100000;
+    binptr[8] = 0x0;
+    binptr[9] = 0x0;
+    binptr[10] = 0x0;
+    binptr[11] = 0x0;
+    binptr[12] = 0x0;
+    binptr[13] = 0x0;
+    binptr[14] = 0x80808080;
+    binptr[15] = 0x0;
+    binptr[16] = 0x0;
+    binptr[17] = 0x201C2;
+    binptr[18] = 0x88050940;
+    binptr[19] = 0x0;
+    binptr[20] = 0x0;
+    header[0] = 0x88EBF274;
+    header[1] = 0x54;
+    extra = calc_csum((unsigned char*)binptr, 84);
+    fwrite(header, sizeof(header), 1, out);
+    fwrite(&extra, sizeof(extra), 1, out);
+    fwrite(binptr, 84, 1, out);
+
+    /*The footer*/
+    header[0] = 0;
+    header[1] = 0x88201000;
+    extra = 0;
+    fwrite(header, sizeof(header), 1, out);
+    fwrite(&extra, sizeof(extra), 1, out);
+    
+    fprintf(stderr, "File processed successfully\n" );
+
+    fclose(in);
+    fclose(out);
+    return(0);
+}
diff --git a/tools/gigabeats.h b/tools/gigabeats.h
new file mode 100644
index 0000000000..f682a9d887
--- /dev/null
+++ b/tools/gigabeats.h
@@ -0,0 +1,20 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Marcoen Hirschberg
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+int gigabeat_s_code(char *infile, char *outfile);
diff --git a/tools/scramble.c b/tools/scramble.c
index 9f18e96e85..8534d41832 100644
--- a/tools/scramble.c
+++ b/tools/scramble.c
@@ -23,6 +23,7 @@
 #include <string.h>
 #include "iriver.h"
 #include "gigabeat.h"
+#include "gigabeats.h"
 #include "mi4.h"
 
 int iaudio_encode(char *iname, char *oname, char *idstring);
@@ -92,7 +93,8 @@ void usage(void)
            "\t-ipod3g ipod firmware partition format (3rd Gen)\n"
            "\t-ipod4g ipod firmware partition format (4th Gen, Mini, Nano, Photo/Color)\n"
            "\t-ipod5g ipod firmware partition format (5th Gen - aka Video)\n"
-           "\t-gigabeat Toshiba Gigabeat format\n"
+           "\t-gigabeat Toshiba Gigabeat F/X format\n"
+           "\t-gigabeats Toshiba Gigabeat S format\n"
            "\t-mi4v2  PortalPlayer .mi4 format (revision 010201)\n"
            "\t-mi4v3  PortalPlayer .mi4 format (revision 010301)\n"
            "\t-mi4r   Sandisk Rhapsody .mi4 format\n"
@@ -231,6 +233,8 @@ int main (int argc, char** argv)
             modelnum = 19;
         else if(!strcmp(&argv[1][5], "c200"))
             modelnum = 20;
+             else if(!strcmp(&argv[1][5], "gigs"))
+            modelnum = 21;
         else {
             fprintf(stderr, "unsupported model: %s\n", &argv[1][5]);
             return 2;
@@ -254,6 +258,12 @@ int main (int argc, char** argv)
         gigabeat_code(iname, oname);
         return 0;
     }
+    else if(!strcmp(argv[1], "-gigabeats")) {
+        iname = argv[2];
+        oname = argv[3];
+        gigabeat_s_code(iname, oname);
+        return 0;
+    }
     else if(!strcmp(argv[1], "-iaudiox5")) {
         iname = argv[2];
         oname = argv[3];