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Diffstat (limited to 'firmware/export/imx31l.h')
-rwxr-xr-x | firmware/export/imx31l.h | 476 |
1 files changed, 476 insertions, 0 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h new file mode 100755 index 0000000000..1fa5e6ba5e --- /dev/null +++ b/firmware/export/imx31l.h | |||
@@ -0,0 +1,476 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 by James Espinoza | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/ | ||
21 | |||
22 | #define L2CC_BASE_ADDR 0x30000000 | ||
23 | |||
24 | /*Frame Buffer and TTB defines from gigabeat f/x build*/ | ||
25 | #define LCDSADDR1 (*(volatile int *)0x80100000) /* STN/TFT: frame buffer start address 1 */ | ||
26 | #define FRAME1 ((short *)0x80100000) //Foreground FB | ||
27 | #define FRAME2 ((short *)0x84100000) //Background FB - Set to Graphic Window, hence the reason why text is only visible | ||
28 | //when background memory is written. | ||
29 | #define LCD_BUFFER_SIZE ((320*240*2)) | ||
30 | #define TTB_SIZE (0x4000) | ||
31 | #define TTB_BASE (0x80000000 + (32*1024*1024*2)-TTB_SIZE); /*64 megs*/ | ||
32 | /* | ||
33 | * AIPS 1 | ||
34 | */ | ||
35 | #define AIPS1_BASE_ADDR 0x43F00000 | ||
36 | #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR | ||
37 | #define MAX_BASE_ADDR 0x43F04000 | ||
38 | #define EVTMON_BASE_ADDR 0x43F08000 | ||
39 | #define CLKCTL_BASE_ADDR 0x43F0C000 | ||
40 | #define ETB_SLOT4_BASE_ADDR 0x43F10000 | ||
41 | #define ETB_SLOT5_BASE_ADDR 0x43F14000 | ||
42 | #define ECT_CTIO_BASE_ADDR 0x43F18000 | ||
43 | #define I2C_BASE_ADDR 0x43F80000 | ||
44 | #define I2C3_BASE_ADDR 0x43F84000 | ||
45 | #define OTG_BASE_ADDR 0x43F88000 | ||
46 | #define ATA_BASE_ADDR 0x43F8C000 | ||
47 | #define UART1_BASE_ADDR 0x43F90000 | ||
48 | #define UART2_BASE_ADDR 0x43F94000 | ||
49 | #define I2C2_BASE_ADDR 0x43F98000 | ||
50 | #define OWIRE_BASE_ADDR 0x43F9C000 | ||
51 | #define SSI1_BASE_ADDR 0x43FA0000 | ||
52 | #define CSPI1_BASE_ADDR 0x43FA4000 | ||
53 | #define KPP_BASE_ADDR 0x43FA8000 | ||
54 | #define IOMUXC_BASE_ADDR 0x43FAC000 | ||
55 | #define UART4_BASE_ADDR 0x43FB0000 | ||
56 | #define UART5_BASE_ADDR 0x43FB4000 | ||
57 | #define ECT_IP1_BASE_ADDR 0x43FB8000 | ||
58 | #define ECT_IP2_BASE_ADDR 0x43FBC000 | ||
59 | |||
60 | /* | ||
61 | * SPBA | ||
62 | */ | ||
63 | #define SPBA_BASE_ADDR 0x50000000 | ||
64 | #define MMC_SDHC1_BASE_ADDR 0x50004000 | ||
65 | #define MMC_SDHC2_BASE_ADDR 0x50008000 | ||
66 | #define UART3_BASE_ADDR 0x5000C000 | ||
67 | #define CSPI2_BASE_ADDR 0x50010000 | ||
68 | #define SSI2_BASE_ADDR 0x50014000 | ||
69 | #define SIM_BASE_ADDR 0x50018000 | ||
70 | #define IIM_BASE_ADDR 0x5001C000 | ||
71 | #define ATA_DMA_BASE_ADDR 0x50020000 | ||
72 | #define SPBA_CTRL_BASE_ADDR 0x5003C000 | ||
73 | |||
74 | /* | ||
75 | * AIPS 2 | ||
76 | */ | ||
77 | #define AIPS2_BASE_ADDR 0x53F00000 | ||
78 | #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR | ||
79 | #define CCM_BASE_ADDR 0x53F80000 | ||
80 | #define FIRI_BASE_ADDR 0x53F8C000 | ||
81 | #define GPT1_BASE_ADDR 0x53F90000 | ||
82 | #define EPIT1_BASE_ADDR 0x53F94000 | ||
83 | #define EPIT2_BASE_ADDR 0x53F98000 | ||
84 | #define GPIO3_BASE_ADDR 0x53FA4000 | ||
85 | #define SCC_BASE 0x53FAC000 | ||
86 | #define SCM_BASE 0x53FAE000 | ||
87 | #define SMN_BASE 0x53FAF000 | ||
88 | #define RNGA_BASE_ADDR 0x53FB0000 | ||
89 | #define IPU_CTRL_BASE_ADDR 0x53FC0000 | ||
90 | #define AUDMUX_BASE 0x53FC4000 | ||
91 | #define MPEG4_ENC_BASE 0x53FC8000 | ||
92 | #define GPIO1_BASE_ADDR 0x53FCC000 | ||
93 | #define GPIO2_BASE_ADDR 0x53FD0000 | ||
94 | #define SDMA_BASE_ADDR 0x53FD4000 | ||
95 | #define RTC_BASE_ADDR 0x53FD8000 | ||
96 | #define WDOG_BASE_ADDR 0x53FDC000 | ||
97 | #define PWM_BASE_ADDR 0x53FE0000 | ||
98 | #define RTIC_BASE_ADDR 0x53FEC000 | ||
99 | |||
100 | #define WDOG1_BASE_ADDR WDOG_BASE_ADDR | ||
101 | #define CRM_MCU_BASE_ADDR CCM_BASE_ADDR | ||
102 | |||
103 | /* ATA */ | ||
104 | #define TIME_OFF (*(volatile unsigned char*)0x43F8C000) | ||
105 | #define TIME_ON (*(volatile unsigned char*)0x43F8C001) | ||
106 | #define TIME_1 (*(volatile unsigned char*)0x43F8C002) | ||
107 | #define TIME_2W (*(volatile unsigned char*)0x43F8C003) | ||
108 | #define TIME_2R (*(volatile unsigned char*)0x43F8C004) | ||
109 | #define TIME_AX (*(volatile unsigned char*)0x43F8C005) | ||
110 | #define TIME_PIO_RDX (*(volatile unsigned char*)0x43F8C00F) | ||
111 | #define TIME_4 (*(volatile unsigned char*)0x43F8C007) | ||
112 | #define TIME_9 (*(volatile unsigned char*)0x43F8C008) | ||
113 | |||
114 | /* Timers */ | ||
115 | #define EPITCR1 (*(volatile long*)EPIT1_BASE_ADDR) | ||
116 | #define EPITSR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x04)) | ||
117 | #define EPITLR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x08)) | ||
118 | #define EPITCMPR1 (*(volatile long*)(EPIT1_BASE_ADDR+0x0C)) | ||
119 | #define EPITCNT1 (*(volatile long*)(EPIT1_BASE_ADDR+0x10)) | ||
120 | #define EPITCR2 (*(volatile long*)EPIT2_BASE_ADDR) | ||
121 | #define EPITSR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x04)) | ||
122 | #define EPITLR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x08)) | ||
123 | #define EPITCMPR2 (*(volatile long*)(EPIT2_BASE_ADDR+0x0C)) | ||
124 | #define EPITCNT2 (*(volatile long*)(EPIT2_BASE_ADDR+0x10)) | ||
125 | |||
126 | /* GPIO */ | ||
127 | #define GPIO1_DR (*(volatile long*)GPIO1_BASE_ADDR) | ||
128 | #define GPIO1_GDIR (*(volatile long*)(GPIO1_BASE_ADDR+0x04)) | ||
129 | #define GPIO1_PSR (*(volatile long*)(GPIO1_BASE_ADDR+0x08)) | ||
130 | #define GPIO1_ICR1 (*(volatile long*)(GPIO1_BASE_ADDR+0x0C)) | ||
131 | #define GPIO1_ICR2 (*(volatile long*)(GPIO1_BASE_ADDR+0x10)) | ||
132 | #define GPIO1_IMR (*(volatile long*)(GPIO1_BASE_ADDR+0x14)) | ||
133 | #define GPIO1_ISR (*(volatile long*)(GPIO1_BASE_ADDR+0x18)) | ||
134 | |||
135 | #define GPIO2_DR (*(volatile long*)GPIO2_BASE_ADDR) | ||
136 | #define GPIO2_GDIR (*(volatile long*)(GPIO2_BASE_ADDR+0x04)) | ||
137 | #define GPIO2_PSR (*(volatile long*)(GPIO2_BASE_ADDR+0x08)) | ||
138 | #define GPIO2_ICR1 (*(volatile long*)(GPIO2_BASE_ADDR+0x0C)) | ||
139 | #define GPIO2_ICR2 (*(volatile long*)(GPIO2_BASE_ADDR+0x10)) | ||
140 | #define GPIO2_IMR (*(volatile long*)(GPIO2_BASE_ADDR+0x14)) | ||
141 | #define GPIO2_ISR (*(volatile long*)(GPIO2_BASE_ADDR+0x18)) | ||
142 | |||
143 | #define GPIO3_DR (*(volatile long*)GPIO3_BASE_ADDR) | ||
144 | #define GPIO3_GDIR (*(volatile long*)(GPIO3_BASE_ADDR+0x04)) | ||
145 | #define GPIO3_PSR (*(volatile long*)(GPIO3_BASE_ADDR+0x08)) | ||
146 | #define GPIO3_ICR1 (*(volatile long*)(GPIO3_BASE_ADDR+0x0C)) | ||
147 | #define GPIO3_ICR2 (*(volatile long*)(GPIO3_BASE_ADDR+0x10)) | ||
148 | #define GPIO3_IMR (*(volatile long*)(GPIO3_BASE_ADDR+0x14)) | ||
149 | #define GPIO3_ISR (*(volatile long*)(GPIO3_BASE_ADDR+0x18)) | ||
150 | |||
151 | /* SPI */ | ||
152 | #define CSPI_RXDATA1 (*(volatile long*)CSPI1_BASE_ADDR) | ||
153 | #define CSPI_TXDATA1 (*(volatile long*)(CSPI1_BASE_ADDR+0x04)) | ||
154 | #define CSPI_CONREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x08)) | ||
155 | #define CSPI_INTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x0C)) | ||
156 | #define CSPI_DMAREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x10)) | ||
157 | #define CSPI_STATREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x14)) | ||
158 | #define CSPI_PERIODREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x18)) | ||
159 | #define CSPI_TESTREG1 (*(volatile long*)(CSPI1_BASE_ADDR+0x1C0)) | ||
160 | |||
161 | #define CSPI_RXDATA2 (*(volatile long*)CSPI2_BASE_ADDR) | ||
162 | #define CSPI_TXDATA2 (*(volatile long*)(CSPI2_BASE_ADDR+0x04)) | ||
163 | #define CSPI_CONREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x08)) | ||
164 | #define CSPI_INTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x0C)) | ||
165 | #define CSPI_DMAREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x10)) | ||
166 | #define CSPI_STATREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x14)) | ||
167 | #define CSPI_PERIODREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x18)) | ||
168 | #define CSPI_TESTREG2 (*(volatile long*)(CSPI2_BASE_ADDR+0x1C0)) | ||
169 | |||
170 | /* RTC */ | ||
171 | #define RTC_HOURMIN (*(volatile long*)RTC_BASE_ADDR) | ||
172 | #define RTC_SECONDS (*(volatile long*)(RTC_BASE_ADDR+0x04)) | ||
173 | #define RTC_ALRM_HM (*(volatile long*)(RTC_BASE_ADDR+0x08)) | ||
174 | #define RTC_ALRM_SEC (*(volatile long*)(RTC_BASE_ADDR+0x0C)) | ||
175 | #define RTC_CTL (*(volatile long*)(RTC_BASE_ADDR+0x10)) | ||
176 | #define RTC_ISR (*(volatile long*)(RTC_BASE_ADDR+0x14)) | ||
177 | #define RTC_IENR (*(volatile long*)(RTC_BASE_ADDR+0x18)) | ||
178 | #define RTC_STPWCH (*(volatile long*)(RTC_BASE_ADDR+0x1C)) | ||
179 | #define RTC_DAYR (*(volatile long*)(RTC_BASE_ADDR+0x20)) | ||
180 | #define RTC_DAYALARM (*(volatile long*)(RTC_BASE_ADDR+0x24)) | ||
181 | |||
182 | /* Keypad */ | ||
183 | #define KPP_KPCR (*(volatile short*)KPP_BASE_ADDR) | ||
184 | #define KPP_KPSR (*(volatile short*)(KPP_BASE_ADDR+0x2)) | ||
185 | #define KPP_KDDR (*(volatile short*)(KPP_BASE_ADDR+0x4)) | ||
186 | #define KPP_KPDR (*(volatile short*)(KPP_BASE_ADDR+0x6)) | ||
187 | |||
188 | /* ROMPATCH and AVIC */ | ||
189 | #define ROMPATCH_BASE_ADDR 0x60000000 | ||
190 | #define AVIC_BASE_ADDR 0x68000000 | ||
191 | |||
192 | #define INTCNTL (*(volatile long*)AVIC_BASE_ADDR) | ||
193 | #define NIMASK (*(volatile long*)(AVIC_BASE_ADDR+0x004)) | ||
194 | #define INTENNUM (*(volatile long*)(AVIC_BASE_ADDR+0x008)) | ||
195 | #define INTDISNUM (*(volatile long*)(AVIC_BASE_ADDR+0x00C)) | ||
196 | #define INTENABLEH (*(volatile long*)(AVIC_BASE_ADDR+0x010)) | ||
197 | #define INTENABLEL (*(volatile long*)(AVIC_BASE_ADDR+0x014)) | ||
198 | #define INTTYPEH (*(volatile long*)(AVIC_BASE_ADDR+0x018)) | ||
199 | #define INTTYPEL (*(volatile long*)(AVIC_BASE_ADDR+0x01C)) | ||
200 | #define NIPRIORITY7 (*(volatile long*)(AVIC_BASE_ADDR+0x020)) | ||
201 | #define NIPRIORITY6 (*(volatile long*)(AVIC_BASE_ADDR+0x024)) | ||
202 | #define NIPRIORITY5 (*(volatile long*)(AVIC_BASE_ADDR+0x028)) | ||
203 | #define NIPRIORITY4 (*(volatile long*)(AVIC_BASE_ADDR+0x02C)) | ||
204 | #define NIPRIORITY3 (*(volatile long*)(AVIC_BASE_ADDR+0x030)) | ||
205 | #define NIPRIORITY2 (*(volatile long*)(AVIC_BASE_ADDR+0x034)) | ||
206 | #define NIPRIORITY1 (*(volatile long*)(AVIC_BASE_ADDR+0x038)) | ||
207 | #define NIPRIORITY0 (*(volatile long*)(AVIC_BASE_ADDR+0x03C)) | ||
208 | #define NIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x040)) | ||
209 | #define FIVECSR (*(volatile long*)(AVIC_BASE_ADDR+0x044)) | ||
210 | #define INTSRCH (*(volatile long*)(AVIC_BASE_ADDR+0x048)) | ||
211 | #define INTSRCL (*(volatile long*)(AVIC_BASE_ADDR+0x04C)) | ||
212 | #define INTFRCH (*(volatile long*)(AVIC_BASE_ADDR+0x050)) | ||
213 | #define INTFRCL (*(volatile long*)(AVIC_BASE_ADDR+0x054)) | ||
214 | #define NIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x058)) | ||
215 | #define NIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x05C)) | ||
216 | #define FIPNDH (*(volatile long*)(AVIC_BASE_ADDR+0x060)) | ||
217 | #define FIPNDL (*(volatile long*)(AVIC_BASE_ADDR+0x064)) | ||
218 | |||
219 | /* The vectors go all the way up to 63. 4 bytes for each */ | ||
220 | #define VECTOR_BASE_ADDR AVIC_BASE_ADDR+0x100 | ||
221 | #define VECTOR0 (*(volatile long*)VECTOR_BASE_ADDR) | ||
222 | |||
223 | #define NIDIS (1 << 22) | ||
224 | #define FIDIS (1 << 21) | ||
225 | |||
226 | /* Since AVIC vector registers are NOT used, we reserve some for various | ||
227 | * purposes. Copied from Linux source code. */ | ||
228 | #define AVIC_VEC_0 0x100 /* For WFI workaround used by Linux kernel */ | ||
229 | #define AVIC_VEC_1 0x104 /* For system revision used by Linux kernel */ | ||
230 | #define CHIP_REV_1_0 0x10 | ||
231 | #define CHIP_REV_2_0 0x20 | ||
232 | #define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1) | ||
233 | #define SYSTEM_REV_ID_MAG 0xF00C | ||
234 | |||
235 | /* | ||
236 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
237 | */ | ||
238 | #define EXT_MEM_CTRL_BASE 0xB8000000 | ||
239 | #define NFC_BASE EXT_MEM_CTRL_BASE | ||
240 | #define ESDCTL_BASE 0xB8001000 | ||
241 | #define WEIM_BASE_ADDR 0xB8002000 | ||
242 | #define WEIM_CTRL_CS0 WEIM_BASE_ADDR | ||
243 | #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) | ||
244 | #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) | ||
245 | #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) | ||
246 | #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) | ||
247 | #define M3IF_BASE 0xB8003000 | ||
248 | #define PCMCIA_CTL_BASE 0xB8004000 | ||
249 | |||
250 | /* | ||
251 | * Memory regions and CS | ||
252 | */ | ||
253 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
254 | #define CSD0_BASE_ADDR 0x80000000 | ||
255 | #define CSD1_BASE_ADDR 0x90000000 | ||
256 | #define CS0_BASE_ADDR 0xA0000000 | ||
257 | #define CS1_BASE_ADDR 0xA8000000 | ||
258 | #define CS2_BASE_ADDR 0xB0000000 | ||
259 | #define CS3_BASE_ADDR 0xB2000000 | ||
260 | #define CS4_BASE_ADDR 0xB4000000 | ||
261 | #define CS4_BASE_PSRAM 0xB5000000 | ||
262 | #define CS5_BASE_ADDR 0xB6000000 | ||
263 | #define PCMCIA_MEM_BASE_ADDR 0xC0000000 | ||
264 | |||
265 | #define INTERNAL_ROM_VA 0xF0000000 | ||
266 | |||
267 | // SDRAM | ||
268 | #define RAM_BANK0_BASE SDRAM_BASE_ADDR | ||
269 | |||
270 | /* | ||
271 | * IRQ Controller Register Definitions. | ||
272 | */ | ||
273 | #define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04)) | ||
274 | #define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18)) | ||
275 | #define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C)) | ||
276 | |||
277 | /* L210 */ | ||
278 | #define L2CC_BASE_ADDR 0x30000000 | ||
279 | #define L2_CACHE_LINE_SIZE 32 | ||
280 | #define L2_CACHE_CTL_REG 0x100 | ||
281 | #define L2_CACHE_AUX_CTL_REG 0x104 | ||
282 | #define L2_CACHE_SYNC_REG 0x730 | ||
283 | #define L2_CACHE_INV_LINE_REG 0x770 | ||
284 | #define L2_CACHE_INV_WAY_REG 0x77C | ||
285 | #define L2_CACHE_CLEAN_LINE_REG 0x7B0 | ||
286 | #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 | ||
287 | |||
288 | /* CCM */ | ||
289 | #define CLKCTL_CCMR (*(volatile long*)(CCM_BASE_ADDR+0x00)) | ||
290 | #define CLKCTL_PDR0 (*(volatile long*)(CCM_BASE_ADDR+0x04)) | ||
291 | #define CLKCTL_PDR1 (*(volatile long*)(CCM_BASE_ADDR+0x08)) | ||
292 | #define CLKCTL_PDR2 (*(volatile long*)(CCM_BASE_ADDR+0x64)) | ||
293 | #define CLKCTL_RCSR (*(volatile long*)(CCM_BASE_ADDR+0x0C)) | ||
294 | #define CLKCTL_MPCTL (*(volatile long*)(CCM_BASE_ADDR+0x10)) | ||
295 | #define CLKCTL_UPCTL (*(volatile long*)(CCM_BASE_ADDR+0x14)) | ||
296 | #define CLKCTL_SPCTL (*(volatile long*)(CCM_BASE_ADDR+0x18)) | ||
297 | #define CLKCTL_COSR (*(volatile long*)(CCM_BASE_ADDR+0x1C)) | ||
298 | #define CLKCTL_PMCR0 (*(volatile long*)(CCM_BASE_ADDR+0x5C)) | ||
299 | #define PLL_REF_CLK 26000000 | ||
300 | |||
301 | /* WEIM - CS0 */ | ||
302 | #define CSCRU 0x00 | ||
303 | #define CSCRL 0x04 | ||
304 | #define CSCRA 0x08 | ||
305 | |||
306 | /* ESDCTL */ | ||
307 | #define ESDCTL_ESDCTL0 0x00 | ||
308 | #define ESDCTL_ESDCFG0 0x04 | ||
309 | #define ESDCTL_ESDCTL1 0x08 | ||
310 | #define ESDCTL_ESDCFG1 0x0C | ||
311 | #define ESDCTL_ESDMISC 0x10 | ||
312 | |||
313 | /* More UART 1 Register defines */ | ||
314 | #define URXD1 (*(volatile int*)UART1_BASE_ADDR) | ||
315 | #define UTXD1 (*(volatile int*)(UART1_BASE_ADDR+0x40)) | ||
316 | #define UCR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x80)) | ||
317 | #define UCR2_1 (*(volatile int* )(UART1_BASE_ADDR+0x84)) | ||
318 | #define UCR3_1 (*(volatile int* )(UART1_BASE_ADDR+0x88)) | ||
319 | #define UCR4_1 (*(volatile int* )(UART1_BASE_ADDR+0x8C)) | ||
320 | #define UFCR1 (*(volatile int *)(UART1_BASE_ADDR+ 0x90)) | ||
321 | #define USR1_1 (*(volatile int *)(UART1_BASE_ADDR+0x94)) | ||
322 | #define USR2_1 (*(volatile int *)(UART1_BASE_ADDR+0x98)) | ||
323 | #define UTS1 (*(volatile int *)(UART1_BASE_ADDR+0xB4)) | ||
324 | |||
325 | /* | ||
326 | * UART Control Register 0 Bit Fields. | ||
327 | */ | ||
328 | #define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt | ||
329 | #define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate | ||
330 | #define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable | ||
331 | #define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt | ||
332 | #define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable | ||
333 | #define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable | ||
334 | #define EUartUCR1_IREN (1 << 7) // Infrared interface enable | ||
335 | #define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable | ||
336 | #define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable | ||
337 | #define EUartUCR1_SNDBRK (1 << 4) // Send break | ||
338 | #define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable | ||
339 | #define EUartUCR1_DOZE (1 << 1) // Doze | ||
340 | #define EUartUCR1_UARTEN (1 << 0) // UART enabled | ||
341 | #define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable | ||
342 | #define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin | ||
343 | #define EUartUCR2_CTSC (1 << 13) // CTS pin control | ||
344 | #define EUartUCR2_CTS (1 << 12) // Clear to send | ||
345 | #define EUartUCR2_ESCEN (1 << 11) // Escape enable | ||
346 | #define EUartUCR2_PREN (1 << 8) // Parity enable | ||
347 | #define EUartUCR2_PROE (1 << 7) // Parity odd/even | ||
348 | #define EUartUCR2_STPB (1 << 6) // Stop | ||
349 | #define EUartUCR2_WS (1 << 5) // Word size | ||
350 | #define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable | ||
351 | #define EUartUCR2_ATEN (1 << 3) // Aging timer enable | ||
352 | #define EUartUCR2_TXEN (1 << 2) // Transmitter enabled | ||
353 | #define EUartUCR2_RXEN (1 << 1) // Receiver enabled | ||
354 | #define EUartUCR2_SRST_ (1 << 0) // SW reset | ||
355 | #define EUartUCR3_PARERREN (1 << 12) // Parity enable | ||
356 | #define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable | ||
357 | #define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved | ||
358 | #define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable | ||
359 | #define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable | ||
360 | #define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable | ||
361 | #define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected | ||
362 | #define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission | ||
363 | #define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable | ||
364 | #define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars) | ||
365 | #define EUartUCR4_INVR (1 << 9) // Inverted infrared reception | ||
366 | #define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable | ||
367 | #define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable | ||
368 | #define EUartUCR4_IRSC (1 << 5) // IR special case | ||
369 | #define EUartUCR4_LPBYP (1 << 4) // Low power bypass | ||
370 | #define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable | ||
371 | #define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable | ||
372 | #define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable | ||
373 | #define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable | ||
374 | #define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift | ||
375 | #define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1) | ||
376 | #define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2) | ||
377 | #define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3) | ||
378 | #define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4) | ||
379 | #define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5) | ||
380 | #define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6) | ||
381 | #define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7) | ||
382 | #define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift | ||
383 | #define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag | ||
384 | #define EUartUSR1_RTSS (1 << 14) // RTS pin status | ||
385 | #define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag | ||
386 | #define EUartUSR1_RTSD (1 << 12) // RTS delta | ||
387 | #define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag | ||
388 | #define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag | ||
389 | #define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag | ||
390 | #define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status | ||
391 | #define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag | ||
392 | #define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag | ||
393 | #define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag | ||
394 | #define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete | ||
395 | #define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty | ||
396 | #define EUartUSR2_IDLE (1 << 12) // Idle condition | ||
397 | #define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped | ||
398 | #define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag | ||
399 | #define EUartUSR2_WAKE (1 << 7) // Wake | ||
400 | #define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag | ||
401 | #define EUartUSR2_TXDC (1 << 3) // Transmitter complete | ||
402 | #define EUartUSR2_BRCD (1 << 2) // Break condition | ||
403 | #define EUartUSR2_ORE (1 << 1) // Overrun error | ||
404 | #define EUartUSR2_RDR (1 << 0) // Recv data ready | ||
405 | #define EUartUTS_FRCPERR (1 << 13) // Force parity error | ||
406 | #define EUartUTS_LOOP (1 << 12) // Loop tx and rx | ||
407 | #define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty | ||
408 | #define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty | ||
409 | #define EUartUTS_TXFULL (1 << 4) // TxFIFO full | ||
410 | #define EUartUTS_RXFULL (1 << 3) // RxFIFO full | ||
411 | #define EUartUTS_SOFTRST (1 << 0) // Software reset | ||
412 | |||
413 | #define DelayTimerPresVal 3 | ||
414 | |||
415 | #define L2CC_ENABLED | ||
416 | |||
417 | /* Assuming 26MHz input clock */ | ||
418 | /* PD MFD MFI MFN */ | ||
419 | #define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0)) | ||
420 | #define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0)) | ||
421 | #define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0)) | ||
422 | |||
423 | /* UPCTL PD MFD MFI MFN */ | ||
424 | #define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0)) | ||
425 | #define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) | ||
426 | |||
427 | /* PDR0 */ | ||
428 | #define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */ | ||
429 | #define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */ | ||
430 | #define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */ | ||
431 | #define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ | ||
432 | #define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ | ||
433 | #define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */ | ||
434 | |||
435 | #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */ | ||
436 | |||
437 | #define PBC_BSTAT2 0x2 | ||
438 | #define PBC_BCTRL1 0x4 | ||
439 | #define PBC_BCTRL1_CLR 0x6 | ||
440 | #define PBC_BCTRL2 0x8 | ||
441 | #define PBC_BCTRL2_CLR 0xA | ||
442 | #define PBC_BCTRL3 0xC | ||
443 | #define PBC_BCTRL3_CLR 0xE | ||
444 | #define PBC_BCTRL4 0x10 | ||
445 | #define PBC_BCTRL4_CLR 0x12 | ||
446 | #define PBC_BSTAT1 0x14 | ||
447 | #define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300) | ||
448 | #define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000) | ||
449 | |||
450 | #define REDBOOT_IMAGE_SIZE 0x40000 | ||
451 | |||
452 | #define SDRAM_WORKAROUND_FULL_PAGE | ||
453 | |||
454 | #define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/ | ||
455 | #define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/ | ||
456 | #define ARMHIPG_399_66_66 | ||
457 | #define ARMHIPG_399_133_66 | ||
458 | |||
459 | /* MX31 EVB SDRAM is from 0x80000000, 64M */ | ||
460 | #define SDRAM_BASE_ADDR CSD0_BASE_ADDR | ||
461 | #define SDRAM_SIZE 0x04000000 | ||
462 | |||
463 | #define UART_WIDTH_32 /* internal UART is 32bit access only */ | ||
464 | #define EXT_UART_x16 | ||
465 | |||
466 | #define UART_WIDTH_32 /* internal UART is 32bit access only */ | ||
467 | |||
468 | #define FLASH_BURST_MODE_ENABLE 1 | ||
469 | #define SDRAM_COMPARE_CONST1 0x55555555 | ||
470 | #define SDRAM_COMPARE_CONST2 0xAAAAAAAA | ||
471 | #define UART_FIFO_CTRL 0x881 | ||
472 | #define TIMEOUT 1000 | ||
473 | #define writel(v,a) (*(volatile int *) (a) = (v)) | ||
474 | #define readl(a) (*(volatile int *)(a)) | ||
475 | #define writew(v,a) (*(volatile short *) (a) = (v)) | ||
476 | #define readw(a) (*(volatile short *)(a)) | ||