diff options
Diffstat (limited to 'firmware/target/arm/crt0.S')
-rw-r--r-- | firmware/target/arm/crt0.S | 169 |
1 files changed, 165 insertions, 4 deletions
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S index 56876ca9b1..d734f82df8 100644 --- a/firmware/target/arm/crt0.S +++ b/firmware/target/arm/crt0.S | |||
@@ -23,6 +23,9 @@ | |||
23 | 23 | ||
24 | .global start | 24 | .global start |
25 | start: | 25 | start: |
26 | b newstart | ||
27 | .space 4*16 | ||
28 | |||
26 | 29 | ||
27 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader | 30 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader |
28 | * | 31 | * |
@@ -31,7 +34,13 @@ start: | |||
31 | * | 34 | * |
32 | */ | 35 | */ |
33 | 36 | ||
34 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ | 37 | newstart: |
38 | #if CONFIG_CPU == IMX31L | ||
39 | mov r0,#0xD3 | ||
40 | msr cpsr, r0 | ||
41 | #else | ||
42 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ | ||
43 | #endif | ||
35 | 44 | ||
36 | #if !defined(BOOTLOADER) || (CONFIG_CPU == DM320) | 45 | #if !defined(BOOTLOADER) || (CONFIG_CPU == DM320) |
37 | #if !defined(DEBUG) | 46 | #if !defined(DEBUG) |
@@ -95,7 +104,7 @@ start: | |||
95 | cmp r3, r2 | 104 | cmp r3, r2 |
96 | strhi r4, [r2], #4 | 105 | strhi r4, [r2], #4 |
97 | bhi 1b | 106 | bhi 1b |
98 | 107 | ||
99 | #ifdef BOOTLOADER | 108 | #ifdef BOOTLOADER |
100 | /* Code for ARM bootloader targets other than iPod go here */ | 109 | /* Code for ARM bootloader targets other than iPod go here */ |
101 | 110 | ||
@@ -274,6 +283,151 @@ start: | |||
274 | start_loc: | 283 | start_loc: |
275 | bl main | 284 | bl main |
276 | 285 | ||
286 | #elif CONFIG_CPU == IMX31L | ||
287 | |||
288 | mov r0, #0 | ||
289 | mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ | ||
290 | mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ | ||
291 | mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ | ||
292 | |||
293 | /* Also setup the Peripheral Port Remap register inside the core */ | ||
294 | ldr r0, =0x40000015 /* start from AIPS 2GB region */ | ||
295 | mcr p15, 0, r0, c15, c2, 4 | ||
296 | |||
297 | /*** L2 Cache setup/invalidation/disable ***/ | ||
298 | /* Disable L2 cache first */ | ||
299 | ldr r0, =L2CC_BASE_ADDR | ||
300 | ldr r2, [r0, #L2_CACHE_CTL_REG] | ||
301 | bic r2, r2, #0x1 | ||
302 | str r2, [r0, #L2_CACHE_CTL_REG] | ||
303 | |||
304 | |||
305 | /* | ||
306 | * Configure L2 Cache: | ||
307 | * - 128k size(16k way) | ||
308 | * - 8-way associativity | ||
309 | * - 0 ws TAG/VALID/DIRTY | ||
310 | * - 4 ws DATA R/W | ||
311 | */ | ||
312 | ldr r1, [r0, #L2_CACHE_AUX_CTL_REG] | ||
313 | and r1, r1, #0xFE000000 | ||
314 | ldr r2, =0x00030024 | ||
315 | orr r1, r1, r2 | ||
316 | str r1, [r0, #L2_CACHE_AUX_CTL_REG] | ||
317 | |||
318 | /* Invalidate L2 */ | ||
319 | ldr r1, =0x000000FF | ||
320 | str r1, [r0, #L2_CACHE_INV_WAY_REG] | ||
321 | L2_loop: | ||
322 | /* Poll Invalidate By Way register */ | ||
323 | ldr r2, [r0, #L2_CACHE_INV_WAY_REG] | ||
324 | cmp r2, #0 | ||
325 | bne L2_loop | ||
326 | /*** End of L2 operations ***/ | ||
327 | /* Set up stack for IRQ mode */ | ||
328 | mov r0,#0xd2 | ||
329 | msr cpsr, r0 | ||
330 | ldr sp, =irq_stack | ||
331 | /* Set up stack for FIQ mode */ | ||
332 | mov r0,#0xd1 | ||
333 | msr cpsr, r0 | ||
334 | ldr sp, =fiq_stack | ||
335 | |||
336 | /* Let abort and undefined modes use IRQ stack */ | ||
337 | mov r0,#0xd7 | ||
338 | msr cpsr, r0 | ||
339 | ldr sp, =irq_stack | ||
340 | mov r0,#0xdb | ||
341 | msr cpsr, r0 | ||
342 | ldr sp, =irq_stack | ||
343 | /* Switch to supervisor mode */ | ||
344 | mov r0,#0xd3 | ||
345 | msr cpsr, r0 | ||
346 | ldr sp, =stackend | ||
347 | |||
348 | /*remap memory as well as exception vectors*/ | ||
349 | /*for now this will be done in bootloader, especially | ||
350 | if usb will be needed within the bootloader to load the | ||
351 | main firmware file. Interrupts will be needed for this | ||
352 | (whether they be swi or irq)*/ | ||
353 | bl memory_init | ||
354 | mov r0,#0 | ||
355 | ldr r1,=_vectorstart | ||
356 | mov r2,#0 | ||
357 | |||
358 | lp: ldr r3,[r1] | ||
359 | add r1,r1,#4 | ||
360 | str r3,[r0] | ||
361 | add r0,r0,#4 | ||
362 | add r2,r2,#1 | ||
363 | cmp r2,#16 | ||
364 | bne lp | ||
365 | bl main | ||
366 | |||
367 | .section .vectors,"aw" | ||
368 | _vectorstart: | ||
369 | ldr pc, [pc, #24] | ||
370 | ldr pc, [pc, #24] | ||
371 | ldr pc, [pc, #24] | ||
372 | ldr pc, [pc, #24] | ||
373 | ldr pc, [pc, #24] | ||
374 | ldr pc, [pc, #24] | ||
375 | ldr pc, [pc, #24] | ||
376 | ldr pc, [pc, #24] | ||
377 | |||
378 | /* Exception vectors */ | ||
379 | .global vectors | ||
380 | vectors: | ||
381 | .word start | ||
382 | .word undef_instr_handler | ||
383 | .word software_int_handler | ||
384 | .word prefetch_abort_handler | ||
385 | .word data_abort_handler | ||
386 | .word reserved_handler | ||
387 | .word irqz | ||
388 | .word fiqz | ||
389 | |||
390 | .text | ||
391 | .global irq | ||
392 | .global fiq | ||
393 | .global UIE | ||
394 | |||
395 | undef_instr_handler: | ||
396 | mov r0, lr | ||
397 | mov r1, #0 | ||
398 | b UIE | ||
399 | |||
400 | software_int_handler: | ||
401 | reserved_handler: | ||
402 | bl irq_handler | ||
403 | movs pc, lr | ||
404 | |||
405 | prefetch_abort_handler: | ||
406 | sub r0, lr, #4 | ||
407 | mov r1, #1 | ||
408 | b UIE | ||
409 | |||
410 | data_abort_handler: | ||
411 | sub r0, lr, #8 | ||
412 | mov r1, #2 | ||
413 | b UIE | ||
414 | |||
415 | /*not working....if we get here, let someone | ||
416 | know....*/ | ||
417 | irqz: bl irq_handler | ||
418 | fiqz: bl fiq_handler | ||
419 | |||
420 | UIE: | ||
421 | b UIE | ||
422 | |||
423 | /* 256 words of IRQ stack */ | ||
424 | .space 256*4 | ||
425 | irq_stack: | ||
426 | |||
427 | /* 256 words of FIQ stack */ | ||
428 | .space 256*4 | ||
429 | fiq_stack: | ||
430 | |||
277 | #else | 431 | #else |
278 | /* get the high part of our execute address */ | 432 | /* get the high part of our execute address */ |
279 | ldr r2, =0xffffff00 | 433 | ldr r2, =0xffffff00 |
@@ -295,11 +449,15 @@ start_loc: | |||
295 | 449 | ||
296 | start_loc: | 450 | start_loc: |
297 | bl main | 451 | bl main |
452 | |||
298 | #endif | 453 | #endif |
299 | 454 | ||
300 | #else /* BOOTLOADER */ | 455 | #else /* BOOTLOADER */ |
301 | 456 | ||
302 | /* Set up stack for IRQ mode */ | 457 | |
458 | |||
459 | |||
460 | /* Set up stack for IRQ mode */ | ||
303 | msr cpsr_c, #0xd2 | 461 | msr cpsr_c, #0xd2 |
304 | ldr sp, =irq_stack | 462 | ldr sp, =irq_stack |
305 | /* Set up stack for FIQ mode */ | 463 | /* Set up stack for FIQ mode */ |
@@ -316,8 +474,11 @@ start_loc: | |||
316 | ldr sp, =stackend | 474 | ldr sp, =stackend |
317 | bl main | 475 | bl main |
318 | /* main() should never return */ | 476 | /* main() should never return */ |
319 | 477 | ||
320 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | 478 | /* Exception handlers. Will be copied to address 0 after memory remapping */ |
479 | #if CONFIG_CPU == IMX31L | ||
480 | _vectorstart: | ||
481 | #endif | ||
321 | .section .vectors,"aw" | 482 | .section .vectors,"aw" |
322 | ldr pc, [pc, #24] | 483 | ldr pc, [pc, #24] |
323 | ldr pc, [pc, #24] | 484 | ldr pc, [pc, #24] |