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Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/avic-imx31.c')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/avic-imx31.c223
1 files changed, 223 insertions, 0 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
new file mode 100644
index 0000000000..8236a38014
--- /dev/null
+++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
@@ -0,0 +1,223 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 by James Espinoza
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19#include <stdio.h>
20#include "system.h"
21#include "imx31l.h"
22#include "avic-imx31.h"
23#include "debug.h"
24
25void avic_init(void)
26{
27 /*following the steps in the AVIC setup in imx31 man*/
28
29 /*Initialize interrupt structures*/
30 int i,avicstart;
31 /*get start of avic_init section for address calculation*/
32 __asm__ ("ldr %0,=_avicstart\n\t"
33 :"=r"(avicstart):);
34
35 for(i=0; i < 64;i++)
36 {
37 imx31_int[i].name = (char *)&imx31_int_names[i];
38 imx31_int[i].int_type=IRQ;
39 /*integer i MUST be multiplied by 8 b/c gnu as
40 generates 2 instructions for each vector instruction
41 in vector_init(). Hence the value of 8 byte intervals
42 between each vector start address*/
43 imx31_int[i].addr=(avicstart+(i*8));
44 imx31_int[i].priority=0;
45 imx31_int[i].pInt_Handler=Unhandled_Int;
46 }
47
48 /*enable all Interrupts*/
49 avic_enable_int(ALL,IRQ,0);
50
51 /*Setup all interrupt type IRQ*/
52 avic_set_int_type(ALL,IRQ);
53
54 /*Set NM bit to enable VIC*/
55 INTCNTL |= (1 << 18);
56
57 /*Setup Registers Vector0-Vector63 for interrupt handler functions*/
58 for(i=0; i < 64;i++)
59 writel(imx31_int[i].addr,(VECTOR_BASE_ADDR+(i*8)));
60
61 /*disable FIQ for now until the interrupt handlers are more mature...*/
62 disable_fiq();
63 /*enable_fiq();*/
64
65 /*enable IRQ in imx31 INTCNTL reg*/
66 INTCNTL &= ~(NIDIS);
67 /*disable FIQ in imx31 INTCNTL reg*/
68 INTCNTL |= FIDIS;
69
70 /*enable IRQ in ARM11 core, enable VE bit in CP15 Control reg to enable VIC*/
71 __asm__ ("mrs r0,cpsr\t\n"
72 "bic r0,r0,#0x80\t\n"
73 "msr cpsr,r0\t\n"
74 "mrc p15,0,r0,c1,c0,0\n\t"
75 "orr r0,r0,#0x1000000\n\t"
76 "mcr p15,0,r0,c1,c0,0\n\t":::
77 "r0");
78}
79
80void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
81 void (*pInt_Handler) (void))
82{
83 int i;
84
85 if(ints == ALL)
86 {
87 avic_set_int_type(ALL,intstype);
88 for(i=0;i<64;i++)
89 INTENNUM= (long)i;
90 if(!(*pInt_Handler))
91 pInt_Handler=Unhandled_Int;
92 return;
93 }
94
95 imx31_int[ints].int_type=intstype;
96 imx31_int[ints].pInt_Handler=pInt_Handler;
97 avic_set_int_type(ints,intstype);
98 INTENNUM=(long)ints;
99}
100
101void avic_disable_int(enum IMX31_INT_LIST ints)
102{
103 int i;
104
105 if(ints == ALL)
106 {
107 for(i=0;i<64;i++)
108 INTDISNUM=(long)i;
109 imx31_int[ints].pInt_Handler=Unhandled_Int;
110 return;
111 }
112
113 INTDISNUM=(long)ints;
114}
115
116void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype)
117{
118 int i;
119 if(ints == ALL)
120 {
121 imx31_int[ints].int_type=intstype;
122 for(i=0;i<64;i++)
123 {
124 if(intstype > CCM_DVFS)
125 INTTYPEH=(long)(intstype-32);
126 else INTTYPEL=(long)intstype;
127 }
128 return;
129 }
130
131 imx31_int[ints].int_type=intstype;
132 if(intstype > CCM_DVFS)
133 INTTYPEH=(long)(intstype-32);
134 else INTTYPEL=(long)intstype;
135}
136
137void Unhandled_Int(void)
138{
139 enum IMX31_INT_LIST ints = 0;
140 DEBUGF("Unhandled Interrupt:\n");
141 DEBUGF("Name : %s\n",imx31_int[ints].name);
142 DEBUGF("Interrupt Type : ");
143 if(imx31_int[ints].int_type==IRQ)
144 DEBUGF("IRQ\n");
145 else DEBUGF("FIQ\n");
146 DEBUGF("Handler Address : 0x%x\n",imx31_int[ints].addr);
147 DEBUGF("Priority : %d",imx31_int[ints].priority);
148}
149
150void vector_init(void)
151{
152
153 /*64 branch instructions, one for every vector in avic
154 A better idea would to calculate the shellcode for each of these
155 instructions...*/
156
157
158 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED0].pInt_Handler));
159 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED1].pInt_Handler));
160 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED2].pInt_Handler));
161 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C3].pInt_Handler));
162 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C2].pInt_Handler));
163 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MPEG4_ENCODER].pInt_Handler));
164 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RTIC].pInt_Handler));
165 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[FIR].pInt_Handler));
166 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MMC_SDHC2].pInt_Handler));
167 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MMC_SDHC1].pInt_Handler));
168 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[I2C1].pInt_Handler));
169 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SSI2].pInt_Handler));
170 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SSI1].pInt_Handler));
171 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI2].pInt_Handler));
172 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI1].pInt_Handler));
173 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[ATA].pInt_Handler));
174 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MBX].pInt_Handler));
175 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CSPI3].pInt_Handler));
176 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART3].pInt_Handler));
177 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IIM].pInt_Handler));
178 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SIM1].pInt_Handler));
179 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SIM2].pInt_Handler));
180 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RNGA].pInt_Handler));
181 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EVTMON].pInt_Handler));
182 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[KPP].pInt_Handler));
183 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RTC].pInt_Handler));
184 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PWN].pInt_Handler));
185 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EPIT2].pInt_Handler));
186 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EPIT1].pInt_Handler));
187 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPT].pInt_Handler));
188 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PWR_FAIL].pInt_Handler));
189 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CCM_DVFS].pInt_Handler));
190 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART2].pInt_Handler));
191 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[NANDFC].pInt_Handler));
192 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SDMA].pInt_Handler));
193 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_HOST1].pInt_Handler));
194 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_HOST2].pInt_Handler));
195 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[USB_OTG].pInt_Handler));
196 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED3].pInt_Handler));
197 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MSHC1].pInt_Handler));
198 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[MSHC2].pInt_Handler));
199 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IPU_ERR].pInt_Handler));
200 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[IPU].pInt_Handler));
201 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED4].pInt_Handler));
202 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED5].pInt_Handler));
203 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART1].pInt_Handler));
204 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART4].pInt_Handler));
205 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[UART5].pInt_Handler));
206 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[ETC_IRQ].pInt_Handler));
207 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SCC_SCM].pInt_Handler));
208 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[SCC_SMN].pInt_Handler));
209 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO2].pInt_Handler));
210 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO1].pInt_Handler));
211 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[CCM_CLK].pInt_Handler));
212 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[PCMCIA].pInt_Handler));
213 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[WDOG].pInt_Handler));
214 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[GPIO3].pInt_Handler));
215 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[RESERVED6].pInt_Handler));
216 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_PWMG].pInt_Handler));
217 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_TEMP].pInt_Handler));
218 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_SENS1].pInt_Handler));
219 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_SENS2].pInt_Handler));
220 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_WDOG].pInt_Handler));
221 __asm__("ldr pc, %0\n\t"::"g"(imx31_int[EXT_TV].pInt_Handler));
222
223}
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