Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 9 insertions, 52 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c
index 80b6f22397..f458561731 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c
@@ -186,18 +186,18 @@ void INIT_ATTR system_init(void)
     cpu_frequency = ccm_get_mcu_clk();
 
     /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */
-    imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM);
+    bitclr32(&CCM_CCMR, CCM_CCMR_LPM);
 
     iim_init();
 
-    imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
-    imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
-    imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
-    imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN);
+    bitset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
+    bitset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
+    bitset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
+    bitclr32(&UCR1_1, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_2, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_3, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_4, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_5, EUARTUCR1_UARTEN);
 
     for (i = 0; i < ARRAYLEN(disable_clocks); i++)
         ccm_module_clock_gating(disable_clocks[i], CGM_OFF);
@@ -207,49 +207,6 @@ void INIT_ATTR system_init(void)
     gpio_init();
 }
 
-void  __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p,
-                                            uint32_t value,
-                                            uint32_t mask)
-{
-    asm volatile("and    r1, r1, r2 \n"
-                 "mrs    ip, cpsr   \n"
-                 "cpsid  if         \n"
-                 "ldr    r3, [r0]   \n"
-                 "bic    r3, r3, r2 \n" 
-                 "orr    r3, r3, r1 \n"
-                 "str    r3, [r0]   \n"
-                 "msr    cpsr_c, ip \n"
-                 "bx     lr         \n");
-    (void)reg_p; (void)value; (void)mask;
-}
-
-void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p,
-                                           uint32_t mask)
-{
-    asm volatile("mrs    r3, cpsr   \n"
-                 "cpsid  if         \n"
-                 "ldr    r2, [r0]   \n"
-                 "orr    r2, r2, r1 \n"
-                 "str    r2, [r0]   \n"
-                 "msr    cpsr_c, r3 \n"
-                 "bx     lr         \n");
-    (void)reg_p; (void)mask;
-}
-
-void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p,
-                                           uint32_t mask)
-{
-    asm volatile("mrs    r3, cpsr   \n"
-                 "cpsid  if         \n"
-                 "ldr    r2, [r0]   \n"
-                 "bic    r2, r2, r1 \n"
-                 "str    r2, [r0]   \n"
-                 "msr    cpsr_c, r3 \n"
-                 "bx     lr         \n");
-    (void)reg_p; (void)mask;
-}
-
-
 void system_prepare_fw_start(void)
 {
     dvfs_dptc_stop();