diff options
28 files changed, 271 insertions, 190 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index 53c38e0ee9..ea309a12f4 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -893,6 +893,7 @@ target/arm/usb-fw-pp502x.c | |||
893 | 893 | ||
894 | #ifdef GIGABEAT_F | 894 | #ifdef GIGABEAT_F |
895 | #ifndef SIMULATOR | 895 | #ifndef SIMULATOR |
896 | target/arm/bits-armv4.S | ||
896 | target/arm/lcd-as-memframe.S | 897 | target/arm/lcd-as-memframe.S |
897 | target/arm/mmu-arm.S | 898 | target/arm/mmu-arm.S |
898 | target/arm/s3c2440/adc-s3c2440.c | 899 | target/arm/s3c2440/adc-s3c2440.c |
@@ -918,6 +919,7 @@ target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c | |||
918 | 919 | ||
919 | #ifdef GIGABEAT_S | 920 | #ifdef GIGABEAT_S |
920 | #ifndef SIMULATOR | 921 | #ifndef SIMULATOR |
922 | target/arm/bits-armv6.S | ||
921 | target/arm/lcd-as-memframe.S | 923 | target/arm/lcd-as-memframe.S |
922 | target/arm/mmu-armv6.S | 924 | target/arm/mmu-armv6.S |
923 | target/arm/imx31/ata-imx31.c | 925 | target/arm/imx31/ata-imx31.c |
@@ -1553,6 +1555,7 @@ target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c | |||
1553 | 1555 | ||
1554 | #if defined(MINI2440) | 1556 | #if defined(MINI2440) |
1555 | #ifndef SIMULATOR | 1557 | #ifndef SIMULATOR |
1558 | target/arm/bits-armv4.S | ||
1556 | target/arm/lcd-as-memframe.S | 1559 | target/arm/lcd-as-memframe.S |
1557 | target/arm/mmu-arm.S | 1560 | target/arm/mmu-arm.S |
1558 | target/arm/s3c2440/debug-s3c2440.c | 1561 | target/arm/s3c2440/debug-s3c2440.c |
diff --git a/firmware/export/system.h b/firmware/export/system.h index fe8121ce20..ee668c87e4 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h | |||
@@ -214,6 +214,11 @@ static inline __attribute__((always_inline)) | |||
214 | uint32_t isolate_first_bit(uint32_t val) | 214 | uint32_t isolate_first_bit(uint32_t val) |
215 | { return val & -val; } | 215 | { return val & -val; } |
216 | 216 | ||
217 | /* Functions to set and clear register or variable bits atomically */ | ||
218 | void bitmod32(volatile uint32_t *addr, uint32_t bits, uint32_t mask); | ||
219 | void bitset32(volatile uint32_t *addr, uint32_t mask); | ||
220 | void bitclr32(volatile uint32_t *addr, uint32_t mask); | ||
221 | |||
217 | /* gcc 3.4 changed the format of the constraints */ | 222 | /* gcc 3.4 changed the format of the constraints */ |
218 | #if (__GNUC__ >= 3) && (__GNUC_MINOR__ > 3) || (__GNUC__ >= 4) | 223 | #if (__GNUC__ >= 3) && (__GNUC_MINOR__ > 3) || (__GNUC__ >= 4) |
219 | #define I_CONSTRAINT "I08" | 224 | #define I_CONSTRAINT "I08" |
diff --git a/firmware/target/arm/bits-armv4.S b/firmware/target/arm/bits-armv4.S new file mode 100644 index 0000000000..05d61b8b7e --- /dev/null +++ b/firmware/target/arm/bits-armv4.S | |||
@@ -0,0 +1,77 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2010 by Michael Sevakis | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /*************************************************************************** | ||
23 | * void bitmod32(volatile uint32_t *addr, uint32_t bits, uint32_t mask) | ||
24 | */ | ||
25 | .section .text, "ax", %progbits | ||
26 | .align 2 | ||
27 | .global bitmod32 | ||
28 | .type bitmod32, %function | ||
29 | bitmod32: | ||
30 | mrs r12, cpsr | ||
31 | orr r3, r12, #0xc0 | ||
32 | msr cpsr_c, r3 | ||
33 | ldr r3, [r0] | ||
34 | and r1, r1, r2 @ Only allow mod of bits in 'mask' | ||
35 | bic r3, r3, r2 @ Clear mask bits | ||
36 | orr r3, r3, r1 @ Set according to 'bits' | ||
37 | str r3, [r0] | ||
38 | msr cpsr_c, r12 | ||
39 | bx lr | ||
40 | .size bitmod32, .-bitmod32 | ||
41 | |||
42 | /*************************************************************************** | ||
43 | * void bitset32(volatile uint32_t *addr, uint32_t mask) | ||
44 | */ | ||
45 | .section .text, "ax", %progbits | ||
46 | .align 2 | ||
47 | .global bitset32 | ||
48 | .type bitset32, %function | ||
49 | bitset32: | ||
50 | mrs r12, cpsr | ||
51 | orr r2, r12, #0xc0 | ||
52 | msr cpsr_c, r2 | ||
53 | ldr r2, [r0] | ||
54 | orr r2, r2, r1 | ||
55 | str r2, [r0] | ||
56 | msr cpsr_c, r12 | ||
57 | bx lr | ||
58 | .size bitset32, .-bitset32 | ||
59 | |||
60 | |||
61 | /*************************************************************************** | ||
62 | * void bitclr32(volatile uint32_t *addr, uint32_t mask) | ||
63 | */ | ||
64 | .section .text, "ax", %progbits | ||
65 | .align 2 | ||
66 | .global bitclr32 | ||
67 | .type bitclr32, %function | ||
68 | bitclr32: | ||
69 | mrs r12, cpsr | ||
70 | orr r2, r12, #0xc0 | ||
71 | msr cpsr_c, r2 | ||
72 | ldr r2, [r0] | ||
73 | bic r2, r2, r1 | ||
74 | str r2, [r0] | ||
75 | msr cpsr_c, r12 | ||
76 | bx lr | ||
77 | .size bitclr32, .-bitclr32 | ||
diff --git a/firmware/target/arm/bits-armv6.S b/firmware/target/arm/bits-armv6.S new file mode 100644 index 0000000000..0a15805f87 --- /dev/null +++ b/firmware/target/arm/bits-armv6.S | |||
@@ -0,0 +1,74 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2010 by Michael Sevakis | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | /*************************************************************************** | ||
23 | * void bitmod32(volatile uint32_t *addr, uint32_t bits, uint32_t mask) | ||
24 | */ | ||
25 | .section .text, "ax", %progbits | ||
26 | .align 2 | ||
27 | .global bitmod32 | ||
28 | .type bitmod32, %function | ||
29 | bitmod32: | ||
30 | mrs r12, cpsr | ||
31 | cpsid if | ||
32 | ldr r3, [r0] | ||
33 | and r1, r1, r2 @ Only allow mod of bits in 'mask' | ||
34 | bic r3, r3, r2 @ Clear mask bits | ||
35 | orr r3, r3, r1 @ Set according to 'bits' | ||
36 | str r3, [r0] | ||
37 | msr cpsr_c, r12 | ||
38 | bx lr | ||
39 | .size bitmod32, .-bitmod32 | ||
40 | |||
41 | /*************************************************************************** | ||
42 | * void bitset32(volatile uint32_t *addr, uint32_t mask) | ||
43 | */ | ||
44 | .section .text, "ax", %progbits | ||
45 | .align 2 | ||
46 | .global bitset32 | ||
47 | .type bitset32, %function | ||
48 | bitset32: | ||
49 | mrs r12, cpsr | ||
50 | cpsid if | ||
51 | ldr r2, [r0] | ||
52 | orr r2, r2, r1 | ||
53 | str r2, [r0] | ||
54 | msr cpsr_c, r12 | ||
55 | bx lr | ||
56 | .size bitset32, .-bitset32 | ||
57 | |||
58 | |||
59 | /*************************************************************************** | ||
60 | * void bitclr32(volatile uint32_t *addr, uint32_t mask) | ||
61 | */ | ||
62 | .section .text, "ax", %progbits | ||
63 | .align 2 | ||
64 | .global bitclr32 | ||
65 | .type bitclr32, %function | ||
66 | bitclr32: | ||
67 | mrs r12, cpsr | ||
68 | cpsid if | ||
69 | ldr r2, [r0] | ||
70 | bic r2, r2, r1 | ||
71 | str r2, [r0] | ||
72 | msr cpsr_c, r12 | ||
73 | bx lr | ||
74 | .size bitclr32, .-bitclr32 | ||
diff --git a/firmware/target/arm/imx31/ccm-imx31.c b/firmware/target/arm/imx31/ccm-imx31.c index 2cf2080cf1..00a7d859b1 100644 --- a/firmware/target/arm/imx31/ccm-imx31.c +++ b/firmware/target/arm/imx31/ccm-imx31.c | |||
@@ -43,7 +43,7 @@ void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode) | |||
43 | shift = 2*(cg % 16); /* Get field shift */ | 43 | shift = 2*(cg % 16); /* Get field shift */ |
44 | mask = CG_MASK << shift; /* Select field */ | 44 | mask = CG_MASK << shift; /* Select field */ |
45 | 45 | ||
46 | imx31_regmod32(reg, mode << shift, mask); | 46 | bitmod32(reg, mode << shift, mask); |
47 | } | 47 | } |
48 | 48 | ||
49 | /* Decode PLL output frequency from register value */ | 49 | /* Decode PLL output frequency from register value */ |
diff --git a/firmware/target/arm/imx31/dvfs_dptc-imx31.c b/firmware/target/arm/imx31/dvfs_dptc-imx31.c index 6bacc20c10..aa8d0f52fb 100644 --- a/firmware/target/arm/imx31/dvfs_dptc-imx31.c +++ b/firmware/target/arm/imx31/dvfs_dptc-imx31.c | |||
@@ -275,7 +275,7 @@ static void INIT_ATTR dvfs_init(void) | |||
275 | 275 | ||
276 | #ifndef DVFS_NO_PWRRDY | 276 | #ifndef DVFS_NO_PWRRDY |
277 | /* Configure PWRRDY signal pin. */ | 277 | /* Configure PWRRDY signal pin. */ |
278 | imx31_regclr32(&GPIO1_GDIR, (1 << 5)); | 278 | bitclr32(&GPIO1_GDIR, (1 << 5)); |
279 | iomuxc_set_pin_mux(IOMUXC_GPIO1_5, | 279 | iomuxc_set_pin_mux(IOMUXC_GPIO1_5, |
280 | IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL); | 280 | IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL); |
281 | #endif | 281 | #endif |
@@ -289,27 +289,26 @@ static void INIT_ATTR dvfs_init(void) | |||
289 | } | 289 | } |
290 | 290 | ||
291 | /* Set up LTR0. */ | 291 | /* Set up LTR0. */ |
292 | imx31_regmod32(&CCM_LTR0, | 292 | bitmod32(&CCM_LTR0, |
293 | DVFS_UPTHR << CCM_LTR0_UPTHR_POS | | 293 | DVFS_UPTHR << CCM_LTR0_UPTHR_POS | |
294 | DVFS_DNTHR << CCM_LTR0_DNTHR_POS | | 294 | DVFS_DNTHR << CCM_LTR0_DNTHR_POS | |
295 | DVFS_DIV3CK << CCM_LTR0_DIV3CK_POS, | 295 | DVFS_DIV3CK << CCM_LTR0_DIV3CK_POS, |
296 | CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK); | 296 | CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK); |
297 | 297 | ||
298 | /* Set up LTR1. */ | 298 | /* Set up LTR1. */ |
299 | imx31_regmod32(&CCM_LTR1, | 299 | bitmod32(&CCM_LTR1, |
300 | DVFS_DNCNT << CCM_LTR1_DNCNT_POS | | 300 | DVFS_DNCNT << CCM_LTR1_DNCNT_POS | |
301 | DVFS_UPCNT << CCM_LTR1_UPCNT_POS | | 301 | DVFS_UPCNT << CCM_LTR1_UPCNT_POS | |
302 | DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS | | 302 | DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS | |
303 | CCM_LTR1_LTBRSR, | 303 | CCM_LTR1_LTBRSR, |
304 | CCM_LTR1_DNCNT | CCM_LTR1_UPCNT | | 304 | CCM_LTR1_DNCNT | CCM_LTR1_UPCNT | |
305 | CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR); | 305 | CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR); |
306 | 306 | ||
307 | /* Set up LTR2-- EMA configuration. */ | 307 | /* Set up LTR2-- EMA configuration. */ |
308 | imx31_regmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS, | 308 | bitmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS, CCM_LTR2_EMAC); |
309 | CCM_LTR2_EMAC); | ||
310 | 309 | ||
311 | /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */ | 310 | /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */ |
312 | imx31_regset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI); | 311 | bitset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI); |
313 | 312 | ||
314 | /* Initialize current core PLL and dividers for default level. Assumes | 313 | /* Initialize current core PLL and dividers for default level. Assumes |
315 | * clocking scheme has been set up appropriately in other init code. */ | 314 | * clocking scheme has been set up appropriately in other init code. */ |
@@ -517,8 +516,8 @@ static __attribute__((interrupt("IRQ"))) void CCM_CLK_HANDLER(void) | |||
517 | static void INIT_ATTR dptc_init(void) | 516 | static void INIT_ATTR dptc_init(void) |
518 | { | 517 | { |
519 | /* Force DPTC off if running for some reason. */ | 518 | /* Force DPTC off if running for some reason. */ |
520 | imx31_regmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM, | 519 | bitmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM, |
521 | CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN); | 520 | CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN); |
522 | 521 | ||
523 | /* Shadow the regulator registers */ | 522 | /* Shadow the regulator registers */ |
524 | mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2); | 523 | mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2); |
@@ -528,14 +527,14 @@ static void INIT_ATTR dptc_init(void) | |||
528 | 527 | ||
529 | /* Interrupt goes to MCU, specified reference circuits enabled when | 528 | /* Interrupt goes to MCU, specified reference circuits enabled when |
530 | * DPTC is active. */ | 529 | * DPTC is active. */ |
531 | imx31_regset32(&CCM_PMCR0, CCM_PMCR0_PTVIS); | 530 | bitset32(&CCM_PMCR0, CCM_PMCR0_PTVIS); |
532 | 531 | ||
533 | imx31_regmod32(&CCM_PMCR0, DPTC_DRCE_MASK, | 532 | bitmod32(&CCM_PMCR0, DPTC_DRCE_MASK, |
534 | CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 | | 533 | CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 | |
535 | CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3); | 534 | CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3); |
536 | 535 | ||
537 | /* DPTC counting range = 256 system clocks */ | 536 | /* DPTC counting range = 256 system clocks */ |
538 | imx31_regclr32(&CCM_PMCR0, CCM_PMCR0_DCR); | 537 | bitclr32(&CCM_PMCR0, CCM_PMCR0_DCR); |
539 | 538 | ||
540 | logf("DPTC: Initialized"); | 539 | logf("DPTC: Initialized"); |
541 | } | 540 | } |
@@ -629,7 +628,7 @@ void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value) | |||
629 | shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */ | 628 | shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */ |
630 | } | 629 | } |
631 | 630 | ||
632 | imx31_regmod32(reg_p, value << shift, 0x7 << shift); | 631 | bitmod32(reg_p, value << shift, 0x7 << shift); |
633 | } | 632 | } |
634 | 633 | ||
635 | 634 | ||
@@ -643,7 +642,7 @@ void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge) | |||
643 | else if ((unsigned)index < 16) | 642 | else if ((unsigned)index < 16) |
644 | bit = 1ul << (index + 29); | 643 | bit = 1ul << (index + 29); |
645 | 644 | ||
646 | imx31_regmod32(&CCM_LTR0, edge ? bit : 0, bit); | 645 | bitmod32(&CCM_LTR0, edge ? bit : 0, bit); |
647 | } | 646 | } |
648 | 647 | ||
649 | 648 | ||
@@ -652,7 +651,7 @@ void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert) | |||
652 | if ((unsigned)dvgp <= 3) | 651 | if ((unsigned)dvgp <= 3) |
653 | { | 652 | { |
654 | unsigned long bit = 1ul << dvgp; | 653 | unsigned long bit = 1ul << dvgp; |
655 | imx31_regmod32(&CCM_PMCR1, assert ? bit : 0, bit); | 654 | bitmod32(&CCM_PMCR1, assert ? bit : 0, bit); |
656 | } | 655 | } |
657 | } | 656 | } |
658 | 657 | ||
@@ -660,8 +659,7 @@ void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert) | |||
660 | /* Turn the wait-for-interrupt monitoring on or off */ | 659 | /* Turn the wait-for-interrupt monitoring on or off */ |
661 | void dvfs_wfi_monitor(bool on) | 660 | void dvfs_wfi_monitor(bool on) |
662 | { | 661 | { |
663 | imx31_regmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM, | 662 | bitmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM, CCM_PMCR0_WFIM); |
664 | CCM_PMCR0_WFIM); | ||
665 | } | 663 | } |
666 | 664 | ||
667 | 665 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c index f720921fad..39a2cdab04 100644 --- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |||
@@ -38,14 +38,14 @@ static struct i2c_node si4700_i2c_node = | |||
38 | void fmradio_i2c_init(void) | 38 | void fmradio_i2c_init(void) |
39 | { | 39 | { |
40 | /* RST: LOW */ | 40 | /* RST: LOW */ |
41 | imx31_regclr32(&GPIO1_DR, (1 << 26)); | 41 | bitclr32(&GPIO1_DR, (1 << 26)); |
42 | /* RST: OUT */ | 42 | /* RST: OUT */ |
43 | imx31_regset32(&GPIO1_GDIR, (1 << 26)); | 43 | bitset32(&GPIO1_GDIR, (1 << 26)); |
44 | 44 | ||
45 | /* I2C2 SCL: IN, I2C2: SDA IN */ | 45 | /* I2C2 SCL: IN, I2C2: SDA IN */ |
46 | imx31_regclr32(&GPIO2_GDIR, (3 << 14)); | 46 | bitclr32(&GPIO2_GDIR, (3 << 14)); |
47 | /* I2C2 SCL LO, I2C2 SDA LO */ | 47 | /* I2C2 SCL LO, I2C2 SDA LO */ |
48 | imx31_regclr32(&GPIO2_DR, (3 << 14)); | 48 | bitclr32(&GPIO2_DR, (3 << 14)); |
49 | 49 | ||
50 | /* open-drain pins - external pullups on PCB. Pullup default but | 50 | /* open-drain pins - external pullups on PCB. Pullup default but |
51 | * disabled */ | 51 | * disabled */ |
@@ -73,17 +73,17 @@ void fmradio_i2c_enable(bool enable) | |||
73 | { | 73 | { |
74 | /* place in GPIO mode to hold SDIO low during RESET release, | 74 | /* place in GPIO mode to hold SDIO low during RESET release, |
75 | * SEN1 should be high already (pullup) and GPIO3 left alone */ | 75 | * SEN1 should be high already (pullup) and GPIO3 left alone */ |
76 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ | 76 | bitset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ |
77 | /* I2C2_SDA => MCU2_15 */ | 77 | /* I2C2_SDA => MCU2_15 */ |
78 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, | 78 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
79 | IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO); | 79 | IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO); |
80 | /* enable CLK32KMCU clock */ | 80 | /* enable CLK32KMCU clock */ |
81 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 81 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
82 | /* enable the fm chip (release RESET) */ | 82 | /* enable the fm chip (release RESET) */ |
83 | imx31_regset32(&GPIO1_DR, (1 << 26)); | 83 | bitset32(&GPIO1_DR, (1 << 26)); |
84 | sleep(HZ/100); | 84 | sleep(HZ/100); |
85 | /* busmode should be selected - OK to release SDIO */ | 85 | /* busmode should be selected - OK to release SDIO */ |
86 | imx31_regclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ | 86 | bitclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ |
87 | /* restore pin mux (MCU2_15 => I2C2_SDA) */ | 87 | /* restore pin mux (MCU2_15 => I2C2_SDA) */ |
88 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, | 88 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
89 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); | 89 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); |
@@ -97,7 +97,7 @@ void fmradio_i2c_enable(bool enable) | |||
97 | we can diable the i2c module when not in use */ | 97 | we can diable the i2c module when not in use */ |
98 | i2c_enable_node(&si4700_i2c_node, false); | 98 | i2c_enable_node(&si4700_i2c_node, false); |
99 | /* disable the fm chip */ | 99 | /* disable the fm chip */ |
100 | imx31_regclr32(&GPIO1_DR, (1 << 26)); | 100 | bitclr32(&GPIO1_DR, (1 << 26)); |
101 | /* disable CLK32KMCU clock */ | 101 | /* disable CLK32KMCU clock */ |
102 | mc13783_clear(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 102 | mc13783_clear(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
103 | } | 103 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c index c2ec0d6cab..6291a9cf18 100644 --- a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c | |||
@@ -35,11 +35,11 @@ void i2s_reset(void) | |||
35 | * WM Codec post divider (MCLKDIV=1.5): | 35 | * WM Codec post divider (MCLKDIV=1.5): |
36 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK | 36 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK |
37 | */ | 37 | */ |
38 | imx31_regmod32(&CCM_PDR1, | 38 | bitmod32(&CCM_PDR1, |
39 | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | | 39 | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | |
40 | ((5-1) << CCM_PDR1_SSI1_PODF_POS) | | 40 | ((5-1) << CCM_PDR1_SSI1_PODF_POS) | |
41 | ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | | 41 | ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | |
42 | ((64-1) << CCM_PDR1_SSI2_PODF_POS), | 42 | ((64-1) << CCM_PDR1_SSI2_PODF_POS), |
43 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | | 43 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | |
44 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); | 44 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); |
45 | } | 45 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c index cadd0e7ae8..cd583ecd6b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c | |||
@@ -133,13 +133,13 @@ static void lcd_set_power(bool powered) | |||
133 | lcd_powered = false; | 133 | lcd_powered = false; |
134 | lcd_write_reg(0x04, 0x00); | 134 | lcd_write_reg(0x04, 0x00); |
135 | lcd_enable_interface(false); | 135 | lcd_enable_interface(false); |
136 | imx31_regclr32(&GPIO3_DR, (1 << 12)); | 136 | bitclr32(&GPIO3_DR, (1 << 12)); |
137 | mc13783_clear(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); | 137 | mc13783_clear(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); |
138 | } | 138 | } |
139 | else | 139 | else |
140 | { | 140 | { |
141 | mc13783_set(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); | 141 | mc13783_set(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); |
142 | imx31_regset32(&GPIO3_DR, (1 << 12)); | 142 | bitset32(&GPIO3_DR, (1 << 12)); |
143 | lcd_enable_interface(true); | 143 | lcd_enable_interface(true); |
144 | lcd_write_reg(0x04, 0x01); | 144 | lcd_write_reg(0x04, 0x01); |
145 | lcd_powered = true; | 145 | lcd_powered = true; |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c index cfd83f0794..15f9d0bd1c 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | |||
@@ -458,7 +458,7 @@ void pcm_rec_dma_stop(void) | |||
458 | /* Stop receiving data */ | 458 | /* Stop receiving data */ |
459 | sdma_channel_stop(DMA_REC_CH_NUM); | 459 | sdma_channel_stop(DMA_REC_CH_NUM); |
460 | 460 | ||
461 | imx31_regclr32(&SSI_SIER1, SSI_SIER_RDMAE); | 461 | bitclr32(&SSI_SIER1, SSI_SIER_RDMAE); |
462 | 462 | ||
463 | SSI_SCR1 &= ~SSI_SCR_RE; /* Disable RX */ | 463 | SSI_SCR1 &= ~SSI_SCR_RE; /* Disable RX */ |
464 | SSI_SRCR1 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */ | 464 | SSI_SRCR1 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c index 4540be671a..9d7d30547b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c | |||
@@ -85,17 +85,17 @@ void ide_power_enable(bool on) | |||
85 | if (!on) | 85 | if (!on) |
86 | { | 86 | { |
87 | /* Bus must be isolated before power off */ | 87 | /* Bus must be isolated before power off */ |
88 | imx31_regset32(&GPIO2_DR, (1 << 16)); | 88 | bitset32(&GPIO2_DR, (1 << 16)); |
89 | } | 89 | } |
90 | 90 | ||
91 | /* HD power switch */ | 91 | /* HD power switch */ |
92 | imx31_regmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5)); | 92 | bitmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5)); |
93 | 93 | ||
94 | if (on) | 94 | if (on) |
95 | { | 95 | { |
96 | /* Bus switch may be turned on after powerup */ | 96 | /* Bus switch may be turned on after powerup */ |
97 | sleep(HZ/10); | 97 | sleep(HZ/10); |
98 | imx31_regclr32(&GPIO2_DR, (1 << 16)); | 98 | bitclr32(&GPIO2_DR, (1 << 16)); |
99 | } | 99 | } |
100 | } | 100 | } |
101 | 101 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c index 80b6f22397..f458561731 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c | |||
@@ -186,18 +186,18 @@ void INIT_ATTR system_init(void) | |||
186 | cpu_frequency = ccm_get_mcu_clk(); | 186 | cpu_frequency = ccm_get_mcu_clk(); |
187 | 187 | ||
188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ | 188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ |
189 | imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM); | 189 | bitclr32(&CCM_CCMR, CCM_CCMR_LPM); |
190 | 190 | ||
191 | iim_init(); | 191 | iim_init(); |
192 | 192 | ||
193 | imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); | 193 | bitset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); |
194 | imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); | 194 | bitset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); |
195 | imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); | 195 | bitset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); |
196 | imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN); | 196 | bitclr32(&UCR1_1, EUARTUCR1_UARTEN); |
197 | imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN); | 197 | bitclr32(&UCR1_2, EUARTUCR1_UARTEN); |
198 | imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN); | 198 | bitclr32(&UCR1_3, EUARTUCR1_UARTEN); |
199 | imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN); | 199 | bitclr32(&UCR1_4, EUARTUCR1_UARTEN); |
200 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); | 200 | bitclr32(&UCR1_5, EUARTUCR1_UARTEN); |
201 | 201 | ||
202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) | 202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) |
203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); | 203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); |
@@ -207,49 +207,6 @@ void INIT_ATTR system_init(void) | |||
207 | gpio_init(); | 207 | gpio_init(); |
208 | } | 208 | } |
209 | 209 | ||
210 | void __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p, | ||
211 | uint32_t value, | ||
212 | uint32_t mask) | ||
213 | { | ||
214 | asm volatile("and r1, r1, r2 \n" | ||
215 | "mrs ip, cpsr \n" | ||
216 | "cpsid if \n" | ||
217 | "ldr r3, [r0] \n" | ||
218 | "bic r3, r3, r2 \n" | ||
219 | "orr r3, r3, r1 \n" | ||
220 | "str r3, [r0] \n" | ||
221 | "msr cpsr_c, ip \n" | ||
222 | "bx lr \n"); | ||
223 | (void)reg_p; (void)value; (void)mask; | ||
224 | } | ||
225 | |||
226 | void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p, | ||
227 | uint32_t mask) | ||
228 | { | ||
229 | asm volatile("mrs r3, cpsr \n" | ||
230 | "cpsid if \n" | ||
231 | "ldr r2, [r0] \n" | ||
232 | "orr r2, r2, r1 \n" | ||
233 | "str r2, [r0] \n" | ||
234 | "msr cpsr_c, r3 \n" | ||
235 | "bx lr \n"); | ||
236 | (void)reg_p; (void)mask; | ||
237 | } | ||
238 | |||
239 | void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p, | ||
240 | uint32_t mask) | ||
241 | { | ||
242 | asm volatile("mrs r3, cpsr \n" | ||
243 | "cpsid if \n" | ||
244 | "ldr r2, [r0] \n" | ||
245 | "bic r2, r2, r1 \n" | ||
246 | "str r2, [r0] \n" | ||
247 | "msr cpsr_c, r3 \n" | ||
248 | "bx lr \n"); | ||
249 | (void)reg_p; (void)mask; | ||
250 | } | ||
251 | |||
252 | |||
253 | void system_prepare_fw_start(void) | 210 | void system_prepare_fw_start(void) |
254 | { | 211 | { |
255 | dvfs_dptc_stop(); | 212 | dvfs_dptc_stop(); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index af95471db6..a13f87a4cd 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h | |||
@@ -51,11 +51,6 @@ void tick_stop(void); | |||
51 | void kernel_device_init(void); | 51 | void kernel_device_init(void); |
52 | void system_halt(void); | 52 | void system_halt(void); |
53 | 53 | ||
54 | void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value, | ||
55 | uint32_t mask); | ||
56 | void imx31_regset32(volatile uint32_t *reg_p, uint32_t mask); | ||
57 | void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask); | ||
58 | |||
59 | #define KDEV_INIT | 54 | #define KDEV_INIT |
60 | 55 | ||
61 | struct ARM_REGS { | 56 | struct ARM_REGS { |
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c index d873c19ed3..016f24fc48 100644 --- a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c | |||
@@ -40,16 +40,16 @@ static void enable_transceiver(bool enable) | |||
40 | { | 40 | { |
41 | if (GPIO1_DR & (1 << 30)) | 41 | if (GPIO1_DR & (1 << 30)) |
42 | { | 42 | { |
43 | imx31_regclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */ | 43 | bitclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */ |
44 | sleep(HZ/100); | 44 | sleep(HZ/100); |
45 | imx31_regset32(&GPIO3_DR, (1 << 16)); | 45 | bitset32(&GPIO3_DR, (1 << 16)); |
46 | sleep(HZ/10); | 46 | sleep(HZ/10); |
47 | imx31_regclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */ | 47 | bitclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */ |
48 | } | 48 | } |
49 | } | 49 | } |
50 | else | 50 | else |
51 | { | 51 | { |
52 | imx31_regset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */ | 52 | bitset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */ |
53 | } | 53 | } |
54 | } | 54 | } |
55 | 55 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c index 96324cc162..36ab33a5dc 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c | |||
@@ -48,13 +48,13 @@ void audiohw_init(void) | |||
48 | 48 | ||
49 | audiohw_preinit(); | 49 | audiohw_preinit(); |
50 | 50 | ||
51 | imx31_regset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */ | 51 | bitset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */ |
52 | } | 52 | } |
53 | 53 | ||
54 | void audiohw_enable_headphone_jack(bool enable) | 54 | void audiohw_enable_headphone_jack(bool enable) |
55 | { | 55 | { |
56 | /* Turn headphone jack output on or off. */ | 56 | /* Turn headphone jack output on or off. */ |
57 | imx31_regmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22)); | 57 | bitmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22)); |
58 | } | 58 | } |
59 | 59 | ||
60 | void wmcodec_write(int reg, int data) | 60 | void wmcodec_write(int reg, int data) |
diff --git a/firmware/target/arm/imx31/iomuxc-imx31.c b/firmware/target/arm/imx31/iomuxc-imx31.c index 876b8b2a9c..412693e221 100644 --- a/firmware/target/arm/imx31/iomuxc-imx31.c +++ b/firmware/target/arm/imx31/iomuxc-imx31.c | |||
@@ -32,8 +32,8 @@ void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin, | |||
32 | unsigned long index = pin / 4; | 32 | unsigned long index = pin / 4; |
33 | unsigned int shift = 8*(pin % 4); | 33 | unsigned int shift = 8*(pin % 4); |
34 | 34 | ||
35 | imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index, | 35 | bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index, |
36 | mux << shift, IOMUXC_MUX_MASK << shift); | 36 | mux << shift, IOMUXC_MUX_MASK << shift); |
37 | } | 37 | } |
38 | 38 | ||
39 | 39 | ||
@@ -45,6 +45,6 @@ void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin, | |||
45 | unsigned long index = padoffs / 3; | 45 | unsigned long index = padoffs / 3; |
46 | unsigned int shift = 10*(padoffs % 3); | 46 | unsigned int shift = 10*(padoffs % 3); |
47 | 47 | ||
48 | imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index, | 48 | bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index, |
49 | config << shift, IOMUXC_PAD_MASK << shift); | 49 | config << shift, IOMUXC_PAD_MASK << shift); |
50 | } | 50 | } |
diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c index 6e982af3d3..b236dcd2ab 100644 --- a/firmware/target/arm/imx31/mc13783-imx31.c +++ b/firmware/target/arm/imx31/mc13783-imx31.c | |||
@@ -106,7 +106,7 @@ static void mc13783_interrupt_thread(void) | |||
106 | * acknowledged. Reenable interrupt and if anything was still | 106 | * acknowledged. Reenable interrupt and if anything was still |
107 | * pending or became pending again, another signal will be | 107 | * pending or became pending again, another signal will be |
108 | * generated. */ | 108 | * generated. */ |
109 | imx31_regset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); | 109 | bitset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); |
110 | 110 | ||
111 | event = mc13783_events; | 111 | event = mc13783_events; |
112 | event_last = event + MC13783_NUM_EVENTS; | 112 | event_last = event + MC13783_NUM_EVENTS; |
@@ -138,7 +138,7 @@ static void mc13783_interrupt_thread(void) | |||
138 | void mc13783_event(void) | 138 | void mc13783_event(void) |
139 | { | 139 | { |
140 | /* Mask the interrupt (unmasked when PMIC thread services it). */ | 140 | /* Mask the interrupt (unmasked when PMIC thread services it). */ |
141 | imx31_regclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); | 141 | bitclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); |
142 | MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE); | 142 | MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE); |
143 | wakeup_signal(&mc13783_svc_wake); | 143 | wakeup_signal(&mc13783_svc_wake); |
144 | } | 144 | } |
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c index 4928108f67..381e589c08 100644 --- a/firmware/target/arm/imx31/sdma-imx31.c +++ b/firmware/target/arm/imx31/sdma-imx31.c | |||
@@ -414,12 +414,12 @@ static void set_channel_ownership(unsigned int channel, unsigned int config) | |||
414 | 414 | ||
415 | /* DSP side */ | 415 | /* DSP side */ |
416 | #if 0 /* Not using this */ | 416 | #if 0 /* Not using this */ |
417 | imx31_regmod32(&SDMA_DSPOVR, (config & CH_OWNSHP_DSP) ? 0 : bit, bit); | 417 | bitmod32(&SDMA_DSPOVR, (config & CH_OWNSHP_DSP) ? 0 : bit, bit); |
418 | #endif | 418 | #endif |
419 | /* Event */ | 419 | /* Event */ |
420 | imx31_regmod32(&SDMA_EVTOVR, (config & CH_OWNSHP_EVT) ? 0 : bit, bit); | 420 | bitmod32(&SDMA_EVTOVR, (config & CH_OWNSHP_EVT) ? 0 : bit, bit); |
421 | /* MCU side */ | 421 | /* MCU side */ |
422 | imx31_regmod32(&SDMA_HOSTOVR, (config & CH_OWNSHP_MCU) ? 0 : bit, bit); | 422 | bitmod32(&SDMA_HOSTOVR, (config & CH_OWNSHP_MCU) ? 0 : bit, bit); |
423 | } | 423 | } |
424 | 424 | ||
425 | static bool setup_channel(struct channel_control_block *ccb_p) | 425 | static bool setup_channel(struct channel_control_block *ccb_p) |
@@ -485,12 +485,12 @@ static bool setup_channel(struct channel_control_block *ccb_p) | |||
485 | if (channel_cfg & CH_OWNSHP_EVT) | 485 | if (channel_cfg & CH_OWNSHP_EVT) |
486 | { | 486 | { |
487 | /* Set event ID to channel activation bitmapping */ | 487 | /* Set event ID to channel activation bitmapping */ |
488 | imx31_regset32(&SDMA_CHNENBL(cd_p->event_id1), 1ul << channel); | 488 | bitset32(&SDMA_CHNENBL(cd_p->event_id1), 1ul << channel); |
489 | 489 | ||
490 | if (cd_p->per_type == SDMA_PER_ATA) | 490 | if (cd_p->per_type == SDMA_PER_ATA) |
491 | { | 491 | { |
492 | /* ATA has two */ | 492 | /* ATA has two */ |
493 | imx31_regset32(&SDMA_CHNENBL(cd_p->event_id2), 1ul << channel); | 493 | bitset32(&SDMA_CHNENBL(cd_p->event_id2), 1ul << channel); |
494 | } | 494 | } |
495 | } | 495 | } |
496 | 496 | ||
@@ -676,7 +676,7 @@ void sdma_channel_stop(unsigned int channel) | |||
676 | 676 | ||
677 | /* Unlock callback if it was set */ | 677 | /* Unlock callback if it was set */ |
678 | if (intmsk & chmsk) | 678 | if (intmsk & chmsk) |
679 | imx31_regset32(&sdma_enabled_ints, chmsk); | 679 | bitset32(&sdma_enabled_ints, chmsk); |
680 | 680 | ||
681 | logf("SDMA ch closed: %d", channel); | 681 | logf("SDMA ch closed: %d", channel); |
682 | } | 682 | } |
@@ -721,7 +721,7 @@ bool sdma_channel_init(unsigned int channel, | |||
721 | 721 | ||
722 | /* Enable interrupt if a callback is specified. */ | 722 | /* Enable interrupt if a callback is specified. */ |
723 | if (cd_p->callback != NULL) | 723 | if (cd_p->callback != NULL) |
724 | imx31_regset32(&sdma_enabled_ints, 1ul << channel); | 724 | bitset32(&sdma_enabled_ints, 1ul << channel); |
725 | 725 | ||
726 | /* Minimum schedulable = 1 */ | 726 | /* Minimum schedulable = 1 */ |
727 | sdma_channel_set_priority(channel, 1); | 727 | sdma_channel_set_priority(channel, 1); |
@@ -741,7 +741,7 @@ void sdma_channel_close(unsigned int channel) | |||
741 | ccb_p = &ccb_array[channel]; | 741 | ccb_p = &ccb_array[channel]; |
742 | 742 | ||
743 | /* Block callbacks (if not initialized, it won't be set). */ | 743 | /* Block callbacks (if not initialized, it won't be set). */ |
744 | imx31_regclr32(&sdma_enabled_ints, 1ul << channel); | 744 | bitclr32(&sdma_enabled_ints, 1ul << channel); |
745 | 745 | ||
746 | if (ccb_p->status.opened_init == 0) | 746 | if (ccb_p->status.opened_init == 0) |
747 | return; | 747 | return; |
diff --git a/firmware/target/arm/s3c2440/adc-s3c2440.c b/firmware/target/arm/s3c2440/adc-s3c2440.c index f42a3d2b6a..2e0cf8a512 100644 --- a/firmware/target/arm/s3c2440/adc-s3c2440.c +++ b/firmware/target/arm/s3c2440/adc-s3c2440.c | |||
@@ -39,7 +39,7 @@ void adc_init(void) | |||
39 | int i; | 39 | int i; |
40 | 40 | ||
41 | /* Turn on the ADC PCLK */ | 41 | /* Turn on the ADC PCLK */ |
42 | s3c_regset32(&CLKCON, 1<<15); | 42 | bitset32(&CLKCON, 1<<15); |
43 | 43 | ||
44 | /* Set channel 0, normal mode, disable "start by read" */ | 44 | /* Set channel 0, normal mode, disable "start by read" */ |
45 | ADCCON &= ~(0x3F); | 45 | ADCCON &= ~(0x3F); |
diff --git a/firmware/target/arm/s3c2440/dma-s3c2440.c b/firmware/target/arm/s3c2440/dma-s3c2440.c index b83897cb22..c8df4fcc75 100644 --- a/firmware/target/arm/s3c2440/dma-s3c2440.c +++ b/firmware/target/arm/s3c2440/dma-s3c2440.c | |||
@@ -76,8 +76,8 @@ void dma_init(void) | |||
76 | INTPND = DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK; | 76 | INTPND = DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK; |
77 | 77 | ||
78 | /* Enable interrupt in controller */ | 78 | /* Enable interrupt in controller */ |
79 | s3c_regclr32(&INTMOD, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); | 79 | bitclr32(&INTMOD, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); |
80 | s3c_regclr32(&INTMSK, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); | 80 | bitclr32(&INTMSK, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK); |
81 | } | 81 | } |
82 | 82 | ||
83 | void dma_retain(void) | 83 | void dma_retain(void) |
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c index e9f55479c7..c1c9017fbb 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c | |||
@@ -50,14 +50,14 @@ void fiq_handler(void) __attribute__((interrupt ("FIQ"))); | |||
50 | void pcm_play_lock(void) | 50 | void pcm_play_lock(void) |
51 | { | 51 | { |
52 | if (++dma_play_lock.locked == 1) | 52 | if (++dma_play_lock.locked == 1) |
53 | s3c_regset32(&INTMSK, DMA2_MASK); | 53 | bitset32(&INTMSK, DMA2_MASK); |
54 | } | 54 | } |
55 | 55 | ||
56 | /* Unmask the DMA interrupt if enabled */ | 56 | /* Unmask the DMA interrupt if enabled */ |
57 | void pcm_play_unlock(void) | 57 | void pcm_play_unlock(void) |
58 | { | 58 | { |
59 | if (--dma_play_lock.locked == 0) | 59 | if (--dma_play_lock.locked == 0) |
60 | s3c_regclr32(&INTMSK, dma_play_lock.state); | 60 | bitclr32(&INTMSK, dma_play_lock.state); |
61 | } | 61 | } |
62 | 62 | ||
63 | void pcm_play_dma_init(void) | 63 | void pcm_play_dma_init(void) |
@@ -65,7 +65,7 @@ void pcm_play_dma_init(void) | |||
65 | /* There seem to be problems when changing the IIS interface configuration | 65 | /* There seem to be problems when changing the IIS interface configuration |
66 | * when a clock is not present. | 66 | * when a clock is not present. |
67 | */ | 67 | */ |
68 | s3c_regset32(&CLKCON, 1<<17); | 68 | bitset32(&CLKCON, 1<<17); |
69 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - | 69 | /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz - |
70 | BCLK 32fs */ | 70 | BCLK 32fs */ |
71 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); | 71 | IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0); |
@@ -73,7 +73,7 @@ void pcm_play_dma_init(void) | |||
73 | /* RX,TX off,on */ | 73 | /* RX,TX off,on */ |
74 | IISCON |= (1<<3) | (1<<2); | 74 | IISCON |= (1<<3) | (1<<2); |
75 | 75 | ||
76 | s3c_regclr32(&CLKCON, 1<<17); | 76 | bitclr32(&CLKCON, 1<<17); |
77 | 77 | ||
78 | audiohw_init(); | 78 | audiohw_init(); |
79 | 79 | ||
@@ -86,11 +86,11 @@ void pcm_play_dma_init(void) | |||
86 | /* Do not service DMA requests, yet */ | 86 | /* Do not service DMA requests, yet */ |
87 | 87 | ||
88 | /* clear any pending int and mask it */ | 88 | /* clear any pending int and mask it */ |
89 | s3c_regset32(&INTMSK, DMA2_MASK); | 89 | bitset32(&INTMSK, DMA2_MASK); |
90 | SRCPND = DMA2_MASK; | 90 | SRCPND = DMA2_MASK; |
91 | 91 | ||
92 | /* connect to FIQ */ | 92 | /* connect to FIQ */ |
93 | s3c_regset32(&INTMOD, DMA2_MASK); | 93 | bitset32(&INTMOD, DMA2_MASK); |
94 | } | 94 | } |
95 | 95 | ||
96 | void pcm_postinit(void) | 96 | void pcm_postinit(void) |
@@ -132,7 +132,7 @@ static void play_start_pcm(void) | |||
132 | static void play_stop_pcm(void) | 132 | static void play_stop_pcm(void) |
133 | { | 133 | { |
134 | /* Mask DMA interrupt */ | 134 | /* Mask DMA interrupt */ |
135 | s3c_regset32(&INTMSK, DMA2_MASK); | 135 | bitset32(&INTMSK, DMA2_MASK); |
136 | 136 | ||
137 | /* De-Activate the DMA channel */ | 137 | /* De-Activate the DMA channel */ |
138 | DMASKTRIG2 = 0x4; | 138 | DMASKTRIG2 = 0x4; |
@@ -160,7 +160,7 @@ static void play_stop_pcm(void) | |||
160 | void pcm_play_dma_start(const void *addr, size_t size) | 160 | void pcm_play_dma_start(const void *addr, size_t size) |
161 | { | 161 | { |
162 | /* Enable the IIS clock */ | 162 | /* Enable the IIS clock */ |
163 | s3c_regset32(&CLKCON, 1<<17); | 163 | bitset32(&CLKCON, 1<<17); |
164 | 164 | ||
165 | /* stop any DMA in progress - idle IIS */ | 165 | /* stop any DMA in progress - idle IIS */ |
166 | play_stop_pcm(); | 166 | play_stop_pcm(); |
@@ -191,7 +191,7 @@ void pcm_play_dma_stop(void) | |||
191 | play_stop_pcm(); | 191 | play_stop_pcm(); |
192 | 192 | ||
193 | /* Disconnect the IIS clock */ | 193 | /* Disconnect the IIS clock */ |
194 | s3c_regclr32(&CLKCON, 1<<17); | 194 | bitclr32(&CLKCON, 1<<17); |
195 | } | 195 | } |
196 | 196 | ||
197 | void pcm_play_dma_pause(bool pause) | 197 | void pcm_play_dma_pause(bool pause) |
diff --git a/firmware/target/arm/s3c2440/i2c-s3c2440.c b/firmware/target/arm/s3c2440/i2c-s3c2440.c index 4669186a4c..155eb2f956 100644 --- a/firmware/target/arm/s3c2440/i2c-s3c2440.c +++ b/firmware/target/arm/s3c2440/i2c-s3c2440.c | |||
@@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
43 | mutex_lock(&i2c_mtx); | 43 | mutex_lock(&i2c_mtx); |
44 | 44 | ||
45 | /* Turn on I2C clock */ | 45 | /* Turn on I2C clock */ |
46 | s3c_regset32(&CLKCON, 1 << 16); | 46 | bitset32(&CLKCON, 1 << 16); |
47 | 47 | ||
48 | /* Set mode to master transmitter and enable lines */ | 48 | /* Set mode to master transmitter and enable lines */ |
49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; | 49 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; |
@@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
76 | IICSTAT = 0; | 76 | IICSTAT = 0; |
77 | 77 | ||
78 | /* Turn off I2C clock */ | 78 | /* Turn off I2C clock */ |
79 | s3c_regclr32(&CLKCON, 1 << 16); | 79 | bitclr32(&CLKCON, 1 << 16); |
80 | 80 | ||
81 | mutex_unlock(&i2c_mtx); | 81 | mutex_unlock(&i2c_mtx); |
82 | } | 82 | } |
@@ -92,11 +92,11 @@ void i2c_init(void) | |||
92 | INTPND = IIC_MASK; | 92 | INTPND = IIC_MASK; |
93 | 93 | ||
94 | /* Enable i2c interrupt in controller */ | 94 | /* Enable i2c interrupt in controller */ |
95 | s3c_regclr32(&INTMOD, IIC_MASK); | 95 | bitclr32(&INTMOD, IIC_MASK); |
96 | s3c_regclr32(&INTMSK, IIC_MASK); | 96 | bitclr32(&INTMSK, IIC_MASK); |
97 | 97 | ||
98 | /* Turn on I2C clock */ | 98 | /* Turn on I2C clock */ |
99 | s3c_regset32(&CLKCON, 1 << 16); | 99 | bitset32(&CLKCON, 1 << 16); |
100 | 100 | ||
101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ | 101 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ |
102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | | 102 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | |
@@ -110,7 +110,7 @@ void i2c_init(void) | |||
110 | IICLC = (0 << 0); | 110 | IICLC = (0 << 0); |
111 | 111 | ||
112 | /* Turn off I2C clock */ | 112 | /* Turn off I2C clock */ |
113 | s3c_regclr32(&CLKCON, 1 << 16); | 113 | bitclr32(&CLKCON, 1 << 16); |
114 | } | 114 | } |
115 | 115 | ||
116 | void IIC(void) | 116 | void IIC(void) |
diff --git a/firmware/target/arm/s3c2440/kernel-s3c2440.c b/firmware/target/arm/s3c2440/kernel-s3c2440.c index 6cabc8dc81..892758e147 100644 --- a/firmware/target/arm/s3c2440/kernel-s3c2440.c +++ b/firmware/target/arm/s3c2440/kernel-s3c2440.c | |||
@@ -62,7 +62,7 @@ void tick_start(unsigned int interval_in_ms) | |||
62 | #ifdef BOOTLOADER | 62 | #ifdef BOOTLOADER |
63 | void tick_stop(void) | 63 | void tick_stop(void) |
64 | { | 64 | { |
65 | s3c_regset32(&INTMSK, TIMER4_MASK); | 65 | bitset32(&INTMSK, TIMER4_MASK); |
66 | TCON &= ~(1 << 20); | 66 | TCON &= ~(1 << 20); |
67 | SRCPND = TIMER4_MASK; | 67 | SRCPND = TIMER4_MASK; |
68 | INTPND = TIMER4_MASK; | 68 | INTPND = TIMER4_MASK; |
diff --git a/firmware/target/arm/s3c2440/lcd-s3c2440.c b/firmware/target/arm/s3c2440/lcd-s3c2440.c index b9f7d3ef3d..77be29f556 100644 --- a/firmware/target/arm/s3c2440/lcd-s3c2440.c +++ b/firmware/target/arm/s3c2440/lcd-s3c2440.c | |||
@@ -101,7 +101,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
101 | GPDCON |= 0xAAA0AAA0; | 101 | GPDCON |= 0xAAA0AAA0; |
102 | GPDUP |= 0xFCFC; | 102 | GPDUP |= 0xFCFC; |
103 | 103 | ||
104 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ | 104 | bitset32(&CLKCON, 0x20); /* enable LCD clock */ |
105 | LCDCON1 |= LCD_ENVID; | 105 | LCDCON1 |= LCD_ENVID; |
106 | } | 106 | } |
107 | else | 107 | else |
@@ -113,7 +113,7 @@ static void LCD_CTRL_clock(bool onoff) | |||
113 | GPDUP &= ~0xFCFC; | 113 | GPDUP &= ~0xFCFC; |
114 | 114 | ||
115 | LCDCON1 &= ~LCD_ENVID; /* Must disable first or bus may freeze */ | 115 | LCDCON1 &= ~LCD_ENVID; /* Must disable first or bus may freeze */ |
116 | s3c_regclr32(&CLKCON, 0x20); /* disable LCD clock */ | 116 | bitclr32(&CLKCON, 0x20); /* disable LCD clock */ |
117 | } | 117 | } |
118 | } | 118 | } |
119 | 119 | ||
@@ -165,7 +165,7 @@ static void LCD_SPI_SS(bool select) | |||
165 | 165 | ||
166 | static void LCD_SPI_start(void) | 166 | static void LCD_SPI_start(void) |
167 | { | 167 | { |
168 | s3c_regset32(&CLKCON, 0x40000); /* enable SPI clock */ | 168 | bitset32(&CLKCON, 0x40000); /* enable SPI clock */ |
169 | LCD_SPI_SS(false); | 169 | LCD_SPI_SS(false); |
170 | SPCON0=0x3E; | 170 | SPCON0=0x3E; |
171 | SPPRE0=24; | 171 | SPPRE0=24; |
@@ -179,7 +179,7 @@ static void LCD_SPI_stop(void) | |||
179 | LCD_SPI_SS(false); | 179 | LCD_SPI_SS(false); |
180 | 180 | ||
181 | SPCON0 &= ~0x10; | 181 | SPCON0 &= ~0x10; |
182 | s3c_regclr32(&CLKCON, 0x40000); /* disable SPI clock */ | 182 | bitclr32(&CLKCON, 0x40000); /* disable SPI clock */ |
183 | } | 183 | } |
184 | 184 | ||
185 | static void LCD_SPI_init(void) | 185 | static void LCD_SPI_init(void) |
@@ -253,7 +253,7 @@ void lcd_init_device(void) | |||
253 | GPBUP |= 0x181; | 253 | GPBUP |= 0x181; |
254 | #endif | 254 | #endif |
255 | 255 | ||
256 | s3c_regset32(&CLKCON, 0x20); /* enable LCD clock */ | 256 | bitset32(&CLKCON, 0x20); /* enable LCD clock */ |
257 | 257 | ||
258 | LCD_CTRL_setup(); | 258 | LCD_CTRL_setup(); |
259 | #ifdef GIGABEAT_F | 259 | #ifdef GIGABEAT_F |
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c index 30db29c42c..8a6b62f31f 100644 --- a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c +++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | |||
@@ -62,14 +62,14 @@ void fiq_handler(void) __attribute__((interrupt ("FIQ"))); | |||
62 | void pcm_play_lock(void) | 62 | void pcm_play_lock(void) |
63 | { | 63 | { |
64 | if (++dma_play_lock.locked == 1) | 64 | if (++dma_play_lock.locked == 1) |
65 | s3c_regset32(&INTMSK, DMA2_MASK); | 65 | bitset32(&INTMSK, DMA2_MASK); |
66 | } | 66 | } |
67 | 67 | ||
68 | /* Unmask the DMA interrupt if enabled */ | 68 | /* Unmask the DMA interrupt if enabled */ |
69 | void pcm_play_unlock(void) | 69 | void pcm_play_unlock(void) |
70 | { | 70 | { |
71 | if (--dma_play_lock.locked == 0) | 71 | if (--dma_play_lock.locked == 0) |
72 | s3c_regclr32(&INTMSK, dma_play_lock.state); | 72 | bitclr32(&INTMSK, dma_play_lock.state); |
73 | } | 73 | } |
74 | 74 | ||
75 | void pcm_play_dma_init(void) | 75 | void pcm_play_dma_init(void) |
@@ -77,7 +77,7 @@ void pcm_play_dma_init(void) | |||
77 | /* There seem to be problems when changing the IIS interface configuration | 77 | /* There seem to be problems when changing the IIS interface configuration |
78 | * when a clock is not present. | 78 | * when a clock is not present. |
79 | */ | 79 | */ |
80 | s3c_regset32(&CLKCON, 1<<17); | 80 | bitset32(&CLKCON, 1<<17); |
81 | 81 | ||
82 | #ifdef HAVE_UDA1341 | 82 | #ifdef HAVE_UDA1341 |
83 | /* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */ | 83 | /* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */ |
@@ -95,7 +95,7 @@ void pcm_play_dma_init(void) | |||
95 | IISCON |= (1<<3) | (1<<2); | 95 | IISCON |= (1<<3) | (1<<2); |
96 | #endif | 96 | #endif |
97 | 97 | ||
98 | s3c_regclr32(&CLKCON, 1<<17); | 98 | bitclr32(&CLKCON, 1<<17); |
99 | 99 | ||
100 | audiohw_init(); | 100 | audiohw_init(); |
101 | 101 | ||
@@ -112,11 +112,11 @@ void pcm_play_dma_init(void) | |||
112 | /* Do not service DMA requests, yet */ | 112 | /* Do not service DMA requests, yet */ |
113 | 113 | ||
114 | /* clear any pending int and mask it */ | 114 | /* clear any pending int and mask it */ |
115 | s3c_regset32(&INTMSK, DMA2_MASK); | 115 | bitset32(&INTMSK, DMA2_MASK); |
116 | SRCPND = DMA2_MASK; | 116 | SRCPND = DMA2_MASK; |
117 | 117 | ||
118 | /* connect to FIQ */ | 118 | /* connect to FIQ */ |
119 | s3c_regset32(&INTMOD, DMA2_MASK); | 119 | bitset32(&INTMOD, DMA2_MASK); |
120 | } | 120 | } |
121 | 121 | ||
122 | void pcm_postinit(void) | 122 | void pcm_postinit(void) |
@@ -172,7 +172,7 @@ static void play_start_pcm(void) | |||
172 | static void play_stop_pcm(void) | 172 | static void play_stop_pcm(void) |
173 | { | 173 | { |
174 | /* Mask DMA interrupt */ | 174 | /* Mask DMA interrupt */ |
175 | s3c_regset32(&INTMSK, DMA2_MASK); | 175 | bitset32(&INTMSK, DMA2_MASK); |
176 | 176 | ||
177 | /* De-Activate the DMA channel */ | 177 | /* De-Activate the DMA channel */ |
178 | DMASKTRIG2 = 0x4; | 178 | DMASKTRIG2 = 0x4; |
@@ -200,7 +200,7 @@ static void play_stop_pcm(void) | |||
200 | void pcm_play_dma_start(const void *addr, size_t size) | 200 | void pcm_play_dma_start(const void *addr, size_t size) |
201 | { | 201 | { |
202 | /* Enable the IIS clock */ | 202 | /* Enable the IIS clock */ |
203 | s3c_regset32(&CLKCON, 1<<17); | 203 | bitset32(&CLKCON, 1<<17); |
204 | 204 | ||
205 | /* stop any DMA in progress - idle IIS */ | 205 | /* stop any DMA in progress - idle IIS */ |
206 | play_stop_pcm(); | 206 | play_stop_pcm(); |
@@ -231,7 +231,7 @@ void pcm_play_dma_stop(void) | |||
231 | play_stop_pcm(); | 231 | play_stop_pcm(); |
232 | 232 | ||
233 | /* Disconnect the IIS clock */ | 233 | /* Disconnect the IIS clock */ |
234 | s3c_regclr32(&CLKCON, 1<<17); | 234 | bitclr32(&CLKCON, 1<<17); |
235 | } | 235 | } |
236 | 236 | ||
237 | void pcm_play_dma_pause(bool pause) | 237 | void pcm_play_dma_pause(bool pause) |
diff --git a/firmware/target/arm/s3c2440/sd-s3c2440.c b/firmware/target/arm/s3c2440/sd-s3c2440.c index f4c8a4f599..d42405db65 100644 --- a/firmware/target/arm/s3c2440/sd-s3c2440.c +++ b/firmware/target/arm/s3c2440/sd-s3c2440.c | |||
@@ -299,8 +299,8 @@ static void init_sdi_controller(const int card_no) | |||
299 | 299 | ||
300 | #if 1 | 300 | #if 1 |
301 | /* Enable interrupt in controller */ | 301 | /* Enable interrupt in controller */ |
302 | s3c_regclr32(&INTMOD, SDI_MASK); | 302 | bitclr32(&INTMOD, SDI_MASK); |
303 | s3c_regclr32(&INTMSK, SDI_MASK); | 303 | bitclr32(&INTMSK, SDI_MASK); |
304 | 304 | ||
305 | SDIIMSK |= S3C2410_SDIIMSK_DATAFINISH | 305 | SDIIMSK |= S3C2410_SDIIMSK_DATAFINISH |
306 | | S3C2410_SDIIMSK_DATATIMEOUT | 306 | | S3C2410_SDIIMSK_DATATIMEOUT |
diff --git a/firmware/target/arm/s3c2440/system-s3c2440.c b/firmware/target/arm/s3c2440/system-s3c2440.c index cb273ad4df..577b46966c 100644 --- a/firmware/target/arm/s3c2440/system-s3c2440.c +++ b/firmware/target/arm/s3c2440/system-s3c2440.c | |||
@@ -136,24 +136,6 @@ void memory_init(void) | |||
136 | enable_mmu(); | 136 | enable_mmu(); |
137 | } | 137 | } |
138 | 138 | ||
139 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, | ||
140 | unsigned long mask) | ||
141 | { | ||
142 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | ||
143 | *reg = (*reg & ~mask) | (bits & mask); | ||
144 | restore_interrupt(oldstatus); | ||
145 | } | ||
146 | |||
147 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits) | ||
148 | { | ||
149 | s3c_regmod32(reg, bits, bits); | ||
150 | } | ||
151 | |||
152 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits) | ||
153 | { | ||
154 | s3c_regmod32(reg, 0, bits); | ||
155 | } | ||
156 | |||
157 | #ifdef BOOTLOADER | 139 | #ifdef BOOTLOADER |
158 | void system_prepare_fw_start(void) | 140 | void system_prepare_fw_start(void) |
159 | { | 141 | { |
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index ad32f89552..c48a62cf47 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h | |||
@@ -69,14 +69,4 @@ | |||
69 | void system_prepare_fw_start(void); | 69 | void system_prepare_fw_start(void); |
70 | void tick_stop(void); | 70 | void tick_stop(void); |
71 | 71 | ||
72 | /* Functions to set and clear register bits atomically */ | ||
73 | |||
74 | /* Set and clear register bits */ | ||
75 | void s3c_regmod32(volatile unsigned long *reg, unsigned long bits, | ||
76 | unsigned long mask); | ||
77 | /* Set register bits */ | ||
78 | void s3c_regset32(volatile unsigned long *reg, unsigned long bits); | ||
79 | /* Clear register bits */ | ||
80 | void s3c_regclr32(volatile unsigned long *reg, unsigned long bits); | ||
81 | |||
82 | #endif /* SYSTEM_TARGET_H */ | 72 | #endif /* SYSTEM_TARGET_H */ |