diff options
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c | 61 |
1 files changed, 9 insertions, 52 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c index 80b6f22397..f458561731 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c | |||
@@ -186,18 +186,18 @@ void INIT_ATTR system_init(void) | |||
186 | cpu_frequency = ccm_get_mcu_clk(); | 186 | cpu_frequency = ccm_get_mcu_clk(); |
187 | 187 | ||
188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ | 188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ |
189 | imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM); | 189 | bitclr32(&CCM_CCMR, CCM_CCMR_LPM); |
190 | 190 | ||
191 | iim_init(); | 191 | iim_init(); |
192 | 192 | ||
193 | imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); | 193 | bitset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); |
194 | imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); | 194 | bitset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); |
195 | imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); | 195 | bitset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); |
196 | imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN); | 196 | bitclr32(&UCR1_1, EUARTUCR1_UARTEN); |
197 | imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN); | 197 | bitclr32(&UCR1_2, EUARTUCR1_UARTEN); |
198 | imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN); | 198 | bitclr32(&UCR1_3, EUARTUCR1_UARTEN); |
199 | imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN); | 199 | bitclr32(&UCR1_4, EUARTUCR1_UARTEN); |
200 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); | 200 | bitclr32(&UCR1_5, EUARTUCR1_UARTEN); |
201 | 201 | ||
202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) | 202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) |
203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); | 203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); |
@@ -207,49 +207,6 @@ void INIT_ATTR system_init(void) | |||
207 | gpio_init(); | 207 | gpio_init(); |
208 | } | 208 | } |
209 | 209 | ||
210 | void __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p, | ||
211 | uint32_t value, | ||
212 | uint32_t mask) | ||
213 | { | ||
214 | asm volatile("and r1, r1, r2 \n" | ||
215 | "mrs ip, cpsr \n" | ||
216 | "cpsid if \n" | ||
217 | "ldr r3, [r0] \n" | ||
218 | "bic r3, r3, r2 \n" | ||
219 | "orr r3, r3, r1 \n" | ||
220 | "str r3, [r0] \n" | ||
221 | "msr cpsr_c, ip \n" | ||
222 | "bx lr \n"); | ||
223 | (void)reg_p; (void)value; (void)mask; | ||
224 | } | ||
225 | |||
226 | void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p, | ||
227 | uint32_t mask) | ||
228 | { | ||
229 | asm volatile("mrs r3, cpsr \n" | ||
230 | "cpsid if \n" | ||
231 | "ldr r2, [r0] \n" | ||
232 | "orr r2, r2, r1 \n" | ||
233 | "str r2, [r0] \n" | ||
234 | "msr cpsr_c, r3 \n" | ||
235 | "bx lr \n"); | ||
236 | (void)reg_p; (void)mask; | ||
237 | } | ||
238 | |||
239 | void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p, | ||
240 | uint32_t mask) | ||
241 | { | ||
242 | asm volatile("mrs r3, cpsr \n" | ||
243 | "cpsid if \n" | ||
244 | "ldr r2, [r0] \n" | ||
245 | "bic r2, r2, r1 \n" | ||
246 | "str r2, [r0] \n" | ||
247 | "msr cpsr_c, r3 \n" | ||
248 | "bx lr \n"); | ||
249 | (void)reg_p; (void)mask; | ||
250 | } | ||
251 | |||
252 | |||
253 | void system_prepare_fw_start(void) | 210 | void system_prepare_fw_start(void) |
254 | { | 211 | { |
255 | dvfs_dptc_stop(); | 212 | dvfs_dptc_stop(); |