Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657

9 files changed, 36 insertions, 84 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
index f720921fad..39a2cdab04 100644
--- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
@@ -38,14 +38,14 @@ static struct i2c_node si4700_i2c_node =
 void fmradio_i2c_init(void)
 {
     /* RST: LOW */
-    imx31_regclr32(&GPIO1_DR, (1 << 26));
+    bitclr32(&GPIO1_DR, (1 << 26));
     /* RST: OUT */
-    imx31_regset32(&GPIO1_GDIR, (1 << 26));
+    bitset32(&GPIO1_GDIR, (1 << 26));
 
     /* I2C2 SCL: IN, I2C2: SDA IN */
-    imx31_regclr32(&GPIO2_GDIR, (3 << 14));
+    bitclr32(&GPIO2_GDIR, (3 << 14));
     /* I2C2 SCL LO, I2C2 SDA LO */
-    imx31_regclr32(&GPIO2_DR, (3 << 14));
+    bitclr32(&GPIO2_DR, (3 << 14));
 
     /* open-drain pins - external pullups on PCB. Pullup default but
      * disabled */
@@ -73,17 +73,17 @@ void fmradio_i2c_enable(bool enable)
     {
         /* place in GPIO mode to hold SDIO low during RESET release,
          * SEN1 should be high already (pullup) and GPIO3 left alone */
-        imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */
+        bitset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */
         /* I2C2_SDA => MCU2_15 */ 
         iomuxc_set_pin_mux(IOMUXC_DCD_DTE1,
                            IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO);
         /* enable CLK32KMCU clock */
         mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN);
         /* enable the fm chip (release RESET) */
-        imx31_regset32(&GPIO1_DR, (1 << 26));
+        bitset32(&GPIO1_DR, (1 << 26));
         sleep(HZ/100);
         /* busmode should be selected - OK to release SDIO */
-        imx31_regclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */
+        bitclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */
         /* restore pin mux (MCU2_15 => I2C2_SDA) */
         iomuxc_set_pin_mux(IOMUXC_DCD_DTE1,
                            IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2);
@@ -97,7 +97,7 @@ void fmradio_i2c_enable(bool enable)
            we can diable the i2c module when not in use */
         i2c_enable_node(&si4700_i2c_node, false);
         /* disable the fm chip */
-        imx31_regclr32(&GPIO1_DR, (1 << 26));
+        bitclr32(&GPIO1_DR, (1 << 26));
         /* disable CLK32KMCU clock */
         mc13783_clear(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN);
     }
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c
index c2ec0d6cab..6291a9cf18 100644
--- a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c
@@ -35,11 +35,11 @@ void i2s_reset(void)
      * WM Codec post divider (MCLKDIV=1.5):
      * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK
      */
-    imx31_regmod32(&CCM_PDR1,
-                   ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) |
-                   ((5-1) << CCM_PDR1_SSI1_PODF_POS) |
-                   ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) |
-                   ((64-1) << CCM_PDR1_SSI2_PODF_POS),
-                   CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF |
-                   CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF);
+    bitmod32(&CCM_PDR1,
+             ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) |
+             ((5-1) << CCM_PDR1_SSI1_PODF_POS) |
+             ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) |
+             ((64-1) << CCM_PDR1_SSI2_PODF_POS),
+             CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF |
+             CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF);
 }
diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c
index cadd0e7ae8..cd583ecd6b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c
@@ -133,13 +133,13 @@ static void lcd_set_power(bool powered)
         lcd_powered = false;
         lcd_write_reg(0x04, 0x00);
         lcd_enable_interface(false);
-        imx31_regclr32(&GPIO3_DR, (1 << 12));
+        bitclr32(&GPIO3_DR, (1 << 12));
         mc13783_clear(MC13783_REGULATOR_MODE1, MC13783_VCAMEN);
     }
     else
     {
         mc13783_set(MC13783_REGULATOR_MODE1, MC13783_VCAMEN);
-        imx31_regset32(&GPIO3_DR, (1 << 12));
+        bitset32(&GPIO3_DR, (1 << 12));
         lcd_enable_interface(true);
         lcd_write_reg(0x04, 0x01);
         lcd_powered = true;
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
index cfd83f0794..15f9d0bd1c 100644
--- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
@@ -458,7 +458,7 @@ void pcm_rec_dma_stop(void)
     /* Stop receiving data */
     sdma_channel_stop(DMA_REC_CH_NUM);
 
-    imx31_regclr32(&SSI_SIER1, SSI_SIER_RDMAE);
+    bitclr32(&SSI_SIER1, SSI_SIER_RDMAE);
 
     SSI_SCR1 &= ~SSI_SCR_RE;      /* Disable RX */
     SSI_SRCR1 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */
diff --git a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c
index 4540be671a..9d7d30547b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c
@@ -85,17 +85,17 @@ void ide_power_enable(bool on)
     if (!on)
     {
         /* Bus must be isolated before power off */
-        imx31_regset32(&GPIO2_DR, (1 << 16));
+        bitset32(&GPIO2_DR, (1 << 16));
     }
 
     /* HD power switch */
-    imx31_regmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5));
+    bitmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5));
 
     if (on)
     {
         /* Bus switch may be turned on after powerup */
         sleep(HZ/10);
-        imx31_regclr32(&GPIO2_DR, (1 << 16));
+        bitclr32(&GPIO2_DR, (1 << 16));
     }
 }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c
index 80b6f22397..f458561731 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c
@@ -186,18 +186,18 @@ void INIT_ATTR system_init(void)
     cpu_frequency = ccm_get_mcu_clk();
 
     /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */
-    imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM);
+    bitclr32(&CCM_CCMR, CCM_CCMR_LPM);
 
     iim_init();
 
-    imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
-    imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
-    imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
-    imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN);
-    imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN);
+    bitset32(&SDHC1_CLOCK_CONTROL, STOP_CLK);
+    bitset32(&SDHC2_CLOCK_CONTROL, STOP_CLK);
+    bitset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP);
+    bitclr32(&UCR1_1, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_2, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_3, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_4, EUARTUCR1_UARTEN);
+    bitclr32(&UCR1_5, EUARTUCR1_UARTEN);
 
     for (i = 0; i < ARRAYLEN(disable_clocks); i++)
         ccm_module_clock_gating(disable_clocks[i], CGM_OFF);
@@ -207,49 +207,6 @@ void INIT_ATTR system_init(void)
     gpio_init();
 }
 
-void  __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p,
-                                            uint32_t value,
-                                            uint32_t mask)
-{
-    asm volatile("and    r1, r1, r2 \n"
-                 "mrs    ip, cpsr   \n"
-                 "cpsid  if         \n"
-                 "ldr    r3, [r0]   \n"
-                 "bic    r3, r3, r2 \n" 
-                 "orr    r3, r3, r1 \n"
-                 "str    r3, [r0]   \n"
-                 "msr    cpsr_c, ip \n"
-                 "bx     lr         \n");
-    (void)reg_p; (void)value; (void)mask;
-}
-
-void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p,
-                                           uint32_t mask)
-{
-    asm volatile("mrs    r3, cpsr   \n"
-                 "cpsid  if         \n"
-                 "ldr    r2, [r0]   \n"
-                 "orr    r2, r2, r1 \n"
-                 "str    r2, [r0]   \n"
-                 "msr    cpsr_c, r3 \n"
-                 "bx     lr         \n");
-    (void)reg_p; (void)mask;
-}
-
-void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p,
-                                           uint32_t mask)
-{
-    asm volatile("mrs    r3, cpsr   \n"
-                 "cpsid  if         \n"
-                 "ldr    r2, [r0]   \n"
-                 "bic    r2, r2, r1 \n"
-                 "str    r2, [r0]   \n"
-                 "msr    cpsr_c, r3 \n"
-                 "bx     lr         \n");
-    (void)reg_p; (void)mask;
-}
-
-
 void system_prepare_fw_start(void)
 {
     dvfs_dptc_stop();
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h
index af95471db6..a13f87a4cd 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h
@@ -51,11 +51,6 @@ void tick_stop(void);
 void kernel_device_init(void);
 void system_halt(void);
 
-void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value,
-                    uint32_t mask);
-void imx31_regset32(volatile uint32_t *reg_p, uint32_t mask);
-void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask);
-
 #define KDEV_INIT
 
 struct ARM_REGS {
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c
index d873c19ed3..016f24fc48 100644
--- a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c
@@ -40,16 +40,16 @@ static void enable_transceiver(bool enable)
     {
         if (GPIO1_DR & (1 << 30))
         {
-            imx31_regclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */
+            bitclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */
             sleep(HZ/100);
-            imx31_regset32(&GPIO3_DR, (1 << 16));
+            bitset32(&GPIO3_DR, (1 << 16));
             sleep(HZ/10);
-            imx31_regclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */
+            bitclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */
         }
     }
     else
     {
-        imx31_regset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */
+        bitset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */
     }
 }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c
index 96324cc162..36ab33a5dc 100644
--- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c
@@ -48,13 +48,13 @@ void audiohw_init(void)
 
     audiohw_preinit();
 
-    imx31_regset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */
+    bitset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */
 }
 
 void audiohw_enable_headphone_jack(bool enable)
 {
     /* Turn headphone jack output on or off. */
-    imx31_regmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22));
+    bitmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22));
 }
 
 void wmcodec_write(int reg, int data)