diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
commit | e286b0bbc04a34c181978efce19c6d0814e228c0 (patch) | |
tree | 841288761e20dc9a7a25e5ba83306adf52547d65 /firmware/target/arm/imx31 | |
parent | f4a00174b50c209f2a23b7a73fe7cb544ef59d02 (diff) | |
download | rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.tar.gz rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.zip |
Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31')
14 files changed, 77 insertions, 127 deletions
diff --git a/firmware/target/arm/imx31/ccm-imx31.c b/firmware/target/arm/imx31/ccm-imx31.c index 2cf2080cf1..00a7d859b1 100644 --- a/firmware/target/arm/imx31/ccm-imx31.c +++ b/firmware/target/arm/imx31/ccm-imx31.c | |||
@@ -43,7 +43,7 @@ void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode) | |||
43 | shift = 2*(cg % 16); /* Get field shift */ | 43 | shift = 2*(cg % 16); /* Get field shift */ |
44 | mask = CG_MASK << shift; /* Select field */ | 44 | mask = CG_MASK << shift; /* Select field */ |
45 | 45 | ||
46 | imx31_regmod32(reg, mode << shift, mask); | 46 | bitmod32(reg, mode << shift, mask); |
47 | } | 47 | } |
48 | 48 | ||
49 | /* Decode PLL output frequency from register value */ | 49 | /* Decode PLL output frequency from register value */ |
diff --git a/firmware/target/arm/imx31/dvfs_dptc-imx31.c b/firmware/target/arm/imx31/dvfs_dptc-imx31.c index 6bacc20c10..aa8d0f52fb 100644 --- a/firmware/target/arm/imx31/dvfs_dptc-imx31.c +++ b/firmware/target/arm/imx31/dvfs_dptc-imx31.c | |||
@@ -275,7 +275,7 @@ static void INIT_ATTR dvfs_init(void) | |||
275 | 275 | ||
276 | #ifndef DVFS_NO_PWRRDY | 276 | #ifndef DVFS_NO_PWRRDY |
277 | /* Configure PWRRDY signal pin. */ | 277 | /* Configure PWRRDY signal pin. */ |
278 | imx31_regclr32(&GPIO1_GDIR, (1 << 5)); | 278 | bitclr32(&GPIO1_GDIR, (1 << 5)); |
279 | iomuxc_set_pin_mux(IOMUXC_GPIO1_5, | 279 | iomuxc_set_pin_mux(IOMUXC_GPIO1_5, |
280 | IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL); | 280 | IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL); |
281 | #endif | 281 | #endif |
@@ -289,27 +289,26 @@ static void INIT_ATTR dvfs_init(void) | |||
289 | } | 289 | } |
290 | 290 | ||
291 | /* Set up LTR0. */ | 291 | /* Set up LTR0. */ |
292 | imx31_regmod32(&CCM_LTR0, | 292 | bitmod32(&CCM_LTR0, |
293 | DVFS_UPTHR << CCM_LTR0_UPTHR_POS | | 293 | DVFS_UPTHR << CCM_LTR0_UPTHR_POS | |
294 | DVFS_DNTHR << CCM_LTR0_DNTHR_POS | | 294 | DVFS_DNTHR << CCM_LTR0_DNTHR_POS | |
295 | DVFS_DIV3CK << CCM_LTR0_DIV3CK_POS, | 295 | DVFS_DIV3CK << CCM_LTR0_DIV3CK_POS, |
296 | CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK); | 296 | CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK); |
297 | 297 | ||
298 | /* Set up LTR1. */ | 298 | /* Set up LTR1. */ |
299 | imx31_regmod32(&CCM_LTR1, | 299 | bitmod32(&CCM_LTR1, |
300 | DVFS_DNCNT << CCM_LTR1_DNCNT_POS | | 300 | DVFS_DNCNT << CCM_LTR1_DNCNT_POS | |
301 | DVFS_UPCNT << CCM_LTR1_UPCNT_POS | | 301 | DVFS_UPCNT << CCM_LTR1_UPCNT_POS | |
302 | DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS | | 302 | DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS | |
303 | CCM_LTR1_LTBRSR, | 303 | CCM_LTR1_LTBRSR, |
304 | CCM_LTR1_DNCNT | CCM_LTR1_UPCNT | | 304 | CCM_LTR1_DNCNT | CCM_LTR1_UPCNT | |
305 | CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR); | 305 | CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR); |
306 | 306 | ||
307 | /* Set up LTR2-- EMA configuration. */ | 307 | /* Set up LTR2-- EMA configuration. */ |
308 | imx31_regmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS, | 308 | bitmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS, CCM_LTR2_EMAC); |
309 | CCM_LTR2_EMAC); | ||
310 | 309 | ||
311 | /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */ | 310 | /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */ |
312 | imx31_regset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI); | 311 | bitset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI); |
313 | 312 | ||
314 | /* Initialize current core PLL and dividers for default level. Assumes | 313 | /* Initialize current core PLL and dividers for default level. Assumes |
315 | * clocking scheme has been set up appropriately in other init code. */ | 314 | * clocking scheme has been set up appropriately in other init code. */ |
@@ -517,8 +516,8 @@ static __attribute__((interrupt("IRQ"))) void CCM_CLK_HANDLER(void) | |||
517 | static void INIT_ATTR dptc_init(void) | 516 | static void INIT_ATTR dptc_init(void) |
518 | { | 517 | { |
519 | /* Force DPTC off if running for some reason. */ | 518 | /* Force DPTC off if running for some reason. */ |
520 | imx31_regmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM, | 519 | bitmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM, |
521 | CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN); | 520 | CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN); |
522 | 521 | ||
523 | /* Shadow the regulator registers */ | 522 | /* Shadow the regulator registers */ |
524 | mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2); | 523 | mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2); |
@@ -528,14 +527,14 @@ static void INIT_ATTR dptc_init(void) | |||
528 | 527 | ||
529 | /* Interrupt goes to MCU, specified reference circuits enabled when | 528 | /* Interrupt goes to MCU, specified reference circuits enabled when |
530 | * DPTC is active. */ | 529 | * DPTC is active. */ |
531 | imx31_regset32(&CCM_PMCR0, CCM_PMCR0_PTVIS); | 530 | bitset32(&CCM_PMCR0, CCM_PMCR0_PTVIS); |
532 | 531 | ||
533 | imx31_regmod32(&CCM_PMCR0, DPTC_DRCE_MASK, | 532 | bitmod32(&CCM_PMCR0, DPTC_DRCE_MASK, |
534 | CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 | | 533 | CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 | |
535 | CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3); | 534 | CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3); |
536 | 535 | ||
537 | /* DPTC counting range = 256 system clocks */ | 536 | /* DPTC counting range = 256 system clocks */ |
538 | imx31_regclr32(&CCM_PMCR0, CCM_PMCR0_DCR); | 537 | bitclr32(&CCM_PMCR0, CCM_PMCR0_DCR); |
539 | 538 | ||
540 | logf("DPTC: Initialized"); | 539 | logf("DPTC: Initialized"); |
541 | } | 540 | } |
@@ -629,7 +628,7 @@ void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value) | |||
629 | shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */ | 628 | shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */ |
630 | } | 629 | } |
631 | 630 | ||
632 | imx31_regmod32(reg_p, value << shift, 0x7 << shift); | 631 | bitmod32(reg_p, value << shift, 0x7 << shift); |
633 | } | 632 | } |
634 | 633 | ||
635 | 634 | ||
@@ -643,7 +642,7 @@ void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge) | |||
643 | else if ((unsigned)index < 16) | 642 | else if ((unsigned)index < 16) |
644 | bit = 1ul << (index + 29); | 643 | bit = 1ul << (index + 29); |
645 | 644 | ||
646 | imx31_regmod32(&CCM_LTR0, edge ? bit : 0, bit); | 645 | bitmod32(&CCM_LTR0, edge ? bit : 0, bit); |
647 | } | 646 | } |
648 | 647 | ||
649 | 648 | ||
@@ -652,7 +651,7 @@ void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert) | |||
652 | if ((unsigned)dvgp <= 3) | 651 | if ((unsigned)dvgp <= 3) |
653 | { | 652 | { |
654 | unsigned long bit = 1ul << dvgp; | 653 | unsigned long bit = 1ul << dvgp; |
655 | imx31_regmod32(&CCM_PMCR1, assert ? bit : 0, bit); | 654 | bitmod32(&CCM_PMCR1, assert ? bit : 0, bit); |
656 | } | 655 | } |
657 | } | 656 | } |
658 | 657 | ||
@@ -660,8 +659,7 @@ void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert) | |||
660 | /* Turn the wait-for-interrupt monitoring on or off */ | 659 | /* Turn the wait-for-interrupt monitoring on or off */ |
661 | void dvfs_wfi_monitor(bool on) | 660 | void dvfs_wfi_monitor(bool on) |
662 | { | 661 | { |
663 | imx31_regmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM, | 662 | bitmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM, CCM_PMCR0_WFIM); |
664 | CCM_PMCR0_WFIM); | ||
665 | } | 663 | } |
666 | 664 | ||
667 | 665 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c index f720921fad..39a2cdab04 100644 --- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |||
@@ -38,14 +38,14 @@ static struct i2c_node si4700_i2c_node = | |||
38 | void fmradio_i2c_init(void) | 38 | void fmradio_i2c_init(void) |
39 | { | 39 | { |
40 | /* RST: LOW */ | 40 | /* RST: LOW */ |
41 | imx31_regclr32(&GPIO1_DR, (1 << 26)); | 41 | bitclr32(&GPIO1_DR, (1 << 26)); |
42 | /* RST: OUT */ | 42 | /* RST: OUT */ |
43 | imx31_regset32(&GPIO1_GDIR, (1 << 26)); | 43 | bitset32(&GPIO1_GDIR, (1 << 26)); |
44 | 44 | ||
45 | /* I2C2 SCL: IN, I2C2: SDA IN */ | 45 | /* I2C2 SCL: IN, I2C2: SDA IN */ |
46 | imx31_regclr32(&GPIO2_GDIR, (3 << 14)); | 46 | bitclr32(&GPIO2_GDIR, (3 << 14)); |
47 | /* I2C2 SCL LO, I2C2 SDA LO */ | 47 | /* I2C2 SCL LO, I2C2 SDA LO */ |
48 | imx31_regclr32(&GPIO2_DR, (3 << 14)); | 48 | bitclr32(&GPIO2_DR, (3 << 14)); |
49 | 49 | ||
50 | /* open-drain pins - external pullups on PCB. Pullup default but | 50 | /* open-drain pins - external pullups on PCB. Pullup default but |
51 | * disabled */ | 51 | * disabled */ |
@@ -73,17 +73,17 @@ void fmradio_i2c_enable(bool enable) | |||
73 | { | 73 | { |
74 | /* place in GPIO mode to hold SDIO low during RESET release, | 74 | /* place in GPIO mode to hold SDIO low during RESET release, |
75 | * SEN1 should be high already (pullup) and GPIO3 left alone */ | 75 | * SEN1 should be high already (pullup) and GPIO3 left alone */ |
76 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ | 76 | bitset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ |
77 | /* I2C2_SDA => MCU2_15 */ | 77 | /* I2C2_SDA => MCU2_15 */ |
78 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, | 78 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
79 | IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO); | 79 | IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO); |
80 | /* enable CLK32KMCU clock */ | 80 | /* enable CLK32KMCU clock */ |
81 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 81 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
82 | /* enable the fm chip (release RESET) */ | 82 | /* enable the fm chip (release RESET) */ |
83 | imx31_regset32(&GPIO1_DR, (1 << 26)); | 83 | bitset32(&GPIO1_DR, (1 << 26)); |
84 | sleep(HZ/100); | 84 | sleep(HZ/100); |
85 | /* busmode should be selected - OK to release SDIO */ | 85 | /* busmode should be selected - OK to release SDIO */ |
86 | imx31_regclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ | 86 | bitclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ |
87 | /* restore pin mux (MCU2_15 => I2C2_SDA) */ | 87 | /* restore pin mux (MCU2_15 => I2C2_SDA) */ |
88 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, | 88 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
89 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); | 89 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); |
@@ -97,7 +97,7 @@ void fmradio_i2c_enable(bool enable) | |||
97 | we can diable the i2c module when not in use */ | 97 | we can diable the i2c module when not in use */ |
98 | i2c_enable_node(&si4700_i2c_node, false); | 98 | i2c_enable_node(&si4700_i2c_node, false); |
99 | /* disable the fm chip */ | 99 | /* disable the fm chip */ |
100 | imx31_regclr32(&GPIO1_DR, (1 << 26)); | 100 | bitclr32(&GPIO1_DR, (1 << 26)); |
101 | /* disable CLK32KMCU clock */ | 101 | /* disable CLK32KMCU clock */ |
102 | mc13783_clear(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 102 | mc13783_clear(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
103 | } | 103 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c index c2ec0d6cab..6291a9cf18 100644 --- a/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/i2s-gigabeat-s.c | |||
@@ -35,11 +35,11 @@ void i2s_reset(void) | |||
35 | * WM Codec post divider (MCLKDIV=1.5): | 35 | * WM Codec post divider (MCLKDIV=1.5): |
36 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK | 36 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK |
37 | */ | 37 | */ |
38 | imx31_regmod32(&CCM_PDR1, | 38 | bitmod32(&CCM_PDR1, |
39 | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | | 39 | ((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) | |
40 | ((5-1) << CCM_PDR1_SSI1_PODF_POS) | | 40 | ((5-1) << CCM_PDR1_SSI1_PODF_POS) | |
41 | ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | | 41 | ((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) | |
42 | ((64-1) << CCM_PDR1_SSI2_PODF_POS), | 42 | ((64-1) << CCM_PDR1_SSI2_PODF_POS), |
43 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | | 43 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | |
44 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); | 44 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); |
45 | } | 45 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c index cadd0e7ae8..cd583ecd6b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/lcd-gigabeat-s.c | |||
@@ -133,13 +133,13 @@ static void lcd_set_power(bool powered) | |||
133 | lcd_powered = false; | 133 | lcd_powered = false; |
134 | lcd_write_reg(0x04, 0x00); | 134 | lcd_write_reg(0x04, 0x00); |
135 | lcd_enable_interface(false); | 135 | lcd_enable_interface(false); |
136 | imx31_regclr32(&GPIO3_DR, (1 << 12)); | 136 | bitclr32(&GPIO3_DR, (1 << 12)); |
137 | mc13783_clear(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); | 137 | mc13783_clear(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); |
138 | } | 138 | } |
139 | else | 139 | else |
140 | { | 140 | { |
141 | mc13783_set(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); | 141 | mc13783_set(MC13783_REGULATOR_MODE1, MC13783_VCAMEN); |
142 | imx31_regset32(&GPIO3_DR, (1 << 12)); | 142 | bitset32(&GPIO3_DR, (1 << 12)); |
143 | lcd_enable_interface(true); | 143 | lcd_enable_interface(true); |
144 | lcd_write_reg(0x04, 0x01); | 144 | lcd_write_reg(0x04, 0x01); |
145 | lcd_powered = true; | 145 | lcd_powered = true; |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c index cfd83f0794..15f9d0bd1c 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | |||
@@ -458,7 +458,7 @@ void pcm_rec_dma_stop(void) | |||
458 | /* Stop receiving data */ | 458 | /* Stop receiving data */ |
459 | sdma_channel_stop(DMA_REC_CH_NUM); | 459 | sdma_channel_stop(DMA_REC_CH_NUM); |
460 | 460 | ||
461 | imx31_regclr32(&SSI_SIER1, SSI_SIER_RDMAE); | 461 | bitclr32(&SSI_SIER1, SSI_SIER_RDMAE); |
462 | 462 | ||
463 | SSI_SCR1 &= ~SSI_SCR_RE; /* Disable RX */ | 463 | SSI_SCR1 &= ~SSI_SCR_RE; /* Disable RX */ |
464 | SSI_SRCR1 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */ | 464 | SSI_SRCR1 &= ~SSI_SRCR_RFEN0; /* Disable RX FIFO */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c index 4540be671a..9d7d30547b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c | |||
@@ -85,17 +85,17 @@ void ide_power_enable(bool on) | |||
85 | if (!on) | 85 | if (!on) |
86 | { | 86 | { |
87 | /* Bus must be isolated before power off */ | 87 | /* Bus must be isolated before power off */ |
88 | imx31_regset32(&GPIO2_DR, (1 << 16)); | 88 | bitset32(&GPIO2_DR, (1 << 16)); |
89 | } | 89 | } |
90 | 90 | ||
91 | /* HD power switch */ | 91 | /* HD power switch */ |
92 | imx31_regmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5)); | 92 | bitmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5)); |
93 | 93 | ||
94 | if (on) | 94 | if (on) |
95 | { | 95 | { |
96 | /* Bus switch may be turned on after powerup */ | 96 | /* Bus switch may be turned on after powerup */ |
97 | sleep(HZ/10); | 97 | sleep(HZ/10); |
98 | imx31_regclr32(&GPIO2_DR, (1 << 16)); | 98 | bitclr32(&GPIO2_DR, (1 << 16)); |
99 | } | 99 | } |
100 | } | 100 | } |
101 | 101 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c index 80b6f22397..f458561731 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-gigabeat-s.c | |||
@@ -186,18 +186,18 @@ void INIT_ATTR system_init(void) | |||
186 | cpu_frequency = ccm_get_mcu_clk(); | 186 | cpu_frequency = ccm_get_mcu_clk(); |
187 | 187 | ||
188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ | 188 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ |
189 | imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM); | 189 | bitclr32(&CCM_CCMR, CCM_CCMR_LPM); |
190 | 190 | ||
191 | iim_init(); | 191 | iim_init(); |
192 | 192 | ||
193 | imx31_regset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); | 193 | bitset32(&SDHC1_CLOCK_CONTROL, STOP_CLK); |
194 | imx31_regset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); | 194 | bitset32(&SDHC2_CLOCK_CONTROL, STOP_CLK); |
195 | imx31_regset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); | 195 | bitset32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP); |
196 | imx31_regclr32(&UCR1_1, EUARTUCR1_UARTEN); | 196 | bitclr32(&UCR1_1, EUARTUCR1_UARTEN); |
197 | imx31_regclr32(&UCR1_2, EUARTUCR1_UARTEN); | 197 | bitclr32(&UCR1_2, EUARTUCR1_UARTEN); |
198 | imx31_regclr32(&UCR1_3, EUARTUCR1_UARTEN); | 198 | bitclr32(&UCR1_3, EUARTUCR1_UARTEN); |
199 | imx31_regclr32(&UCR1_4, EUARTUCR1_UARTEN); | 199 | bitclr32(&UCR1_4, EUARTUCR1_UARTEN); |
200 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); | 200 | bitclr32(&UCR1_5, EUARTUCR1_UARTEN); |
201 | 201 | ||
202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) | 202 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) |
203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); | 203 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); |
@@ -207,49 +207,6 @@ void INIT_ATTR system_init(void) | |||
207 | gpio_init(); | 207 | gpio_init(); |
208 | } | 208 | } |
209 | 209 | ||
210 | void __attribute__((naked)) imx31_regmod32(volatile uint32_t *reg_p, | ||
211 | uint32_t value, | ||
212 | uint32_t mask) | ||
213 | { | ||
214 | asm volatile("and r1, r1, r2 \n" | ||
215 | "mrs ip, cpsr \n" | ||
216 | "cpsid if \n" | ||
217 | "ldr r3, [r0] \n" | ||
218 | "bic r3, r3, r2 \n" | ||
219 | "orr r3, r3, r1 \n" | ||
220 | "str r3, [r0] \n" | ||
221 | "msr cpsr_c, ip \n" | ||
222 | "bx lr \n"); | ||
223 | (void)reg_p; (void)value; (void)mask; | ||
224 | } | ||
225 | |||
226 | void __attribute__((naked)) imx31_regset32(volatile uint32_t *reg_p, | ||
227 | uint32_t mask) | ||
228 | { | ||
229 | asm volatile("mrs r3, cpsr \n" | ||
230 | "cpsid if \n" | ||
231 | "ldr r2, [r0] \n" | ||
232 | "orr r2, r2, r1 \n" | ||
233 | "str r2, [r0] \n" | ||
234 | "msr cpsr_c, r3 \n" | ||
235 | "bx lr \n"); | ||
236 | (void)reg_p; (void)mask; | ||
237 | } | ||
238 | |||
239 | void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p, | ||
240 | uint32_t mask) | ||
241 | { | ||
242 | asm volatile("mrs r3, cpsr \n" | ||
243 | "cpsid if \n" | ||
244 | "ldr r2, [r0] \n" | ||
245 | "bic r2, r2, r1 \n" | ||
246 | "str r2, [r0] \n" | ||
247 | "msr cpsr_c, r3 \n" | ||
248 | "bx lr \n"); | ||
249 | (void)reg_p; (void)mask; | ||
250 | } | ||
251 | |||
252 | |||
253 | void system_prepare_fw_start(void) | 210 | void system_prepare_fw_start(void) |
254 | { | 211 | { |
255 | dvfs_dptc_stop(); | 212 | dvfs_dptc_stop(); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index af95471db6..a13f87a4cd 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h | |||
@@ -51,11 +51,6 @@ void tick_stop(void); | |||
51 | void kernel_device_init(void); | 51 | void kernel_device_init(void); |
52 | void system_halt(void); | 52 | void system_halt(void); |
53 | 53 | ||
54 | void imx31_regmod32(volatile uint32_t *reg_p, uint32_t value, | ||
55 | uint32_t mask); | ||
56 | void imx31_regset32(volatile uint32_t *reg_p, uint32_t mask); | ||
57 | void imx31_regclr32(volatile uint32_t *reg_p, uint32_t mask); | ||
58 | |||
59 | #define KDEV_INIT | 54 | #define KDEV_INIT |
60 | 55 | ||
61 | struct ARM_REGS { | 56 | struct ARM_REGS { |
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c index d873c19ed3..016f24fc48 100644 --- a/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/usb-gigabeat-s.c | |||
@@ -40,16 +40,16 @@ static void enable_transceiver(bool enable) | |||
40 | { | 40 | { |
41 | if (GPIO1_DR & (1 << 30)) | 41 | if (GPIO1_DR & (1 << 30)) |
42 | { | 42 | { |
43 | imx31_regclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */ | 43 | bitclr32(&GPIO3_DR, (1 << 16)); /* Reset ISP1504 */ |
44 | sleep(HZ/100); | 44 | sleep(HZ/100); |
45 | imx31_regset32(&GPIO3_DR, (1 << 16)); | 45 | bitset32(&GPIO3_DR, (1 << 16)); |
46 | sleep(HZ/10); | 46 | sleep(HZ/10); |
47 | imx31_regclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */ | 47 | bitclr32(&GPIO1_DR, (1 << 30)); /* Select ISP1504 */ |
48 | } | 48 | } |
49 | } | 49 | } |
50 | else | 50 | else |
51 | { | 51 | { |
52 | imx31_regset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */ | 52 | bitset32(&GPIO1_DR, (1 << 30)); /* Deselect ISP1504 */ |
53 | } | 53 | } |
54 | } | 54 | } |
55 | 55 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c index 96324cc162..36ab33a5dc 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c | |||
@@ -48,13 +48,13 @@ void audiohw_init(void) | |||
48 | 48 | ||
49 | audiohw_preinit(); | 49 | audiohw_preinit(); |
50 | 50 | ||
51 | imx31_regset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */ | 51 | bitset32(&GPIO3_DR, (1 << 21)); /* Turn on analogue LDO */ |
52 | } | 52 | } |
53 | 53 | ||
54 | void audiohw_enable_headphone_jack(bool enable) | 54 | void audiohw_enable_headphone_jack(bool enable) |
55 | { | 55 | { |
56 | /* Turn headphone jack output on or off. */ | 56 | /* Turn headphone jack output on or off. */ |
57 | imx31_regmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22)); | 57 | bitmod32(&GPIO3_DR, enable ? (1 << 22) : 0, (1 << 22)); |
58 | } | 58 | } |
59 | 59 | ||
60 | void wmcodec_write(int reg, int data) | 60 | void wmcodec_write(int reg, int data) |
diff --git a/firmware/target/arm/imx31/iomuxc-imx31.c b/firmware/target/arm/imx31/iomuxc-imx31.c index 876b8b2a9c..412693e221 100644 --- a/firmware/target/arm/imx31/iomuxc-imx31.c +++ b/firmware/target/arm/imx31/iomuxc-imx31.c | |||
@@ -32,8 +32,8 @@ void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin, | |||
32 | unsigned long index = pin / 4; | 32 | unsigned long index = pin / 4; |
33 | unsigned int shift = 8*(pin % 4); | 33 | unsigned int shift = 8*(pin % 4); |
34 | 34 | ||
35 | imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index, | 35 | bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index, |
36 | mux << shift, IOMUXC_MUX_MASK << shift); | 36 | mux << shift, IOMUXC_MUX_MASK << shift); |
37 | } | 37 | } |
38 | 38 | ||
39 | 39 | ||
@@ -45,6 +45,6 @@ void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin, | |||
45 | unsigned long index = padoffs / 3; | 45 | unsigned long index = padoffs / 3; |
46 | unsigned int shift = 10*(padoffs % 3); | 46 | unsigned int shift = 10*(padoffs % 3); |
47 | 47 | ||
48 | imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index, | 48 | bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index, |
49 | config << shift, IOMUXC_PAD_MASK << shift); | 49 | config << shift, IOMUXC_PAD_MASK << shift); |
50 | } | 50 | } |
diff --git a/firmware/target/arm/imx31/mc13783-imx31.c b/firmware/target/arm/imx31/mc13783-imx31.c index 6e982af3d3..b236dcd2ab 100644 --- a/firmware/target/arm/imx31/mc13783-imx31.c +++ b/firmware/target/arm/imx31/mc13783-imx31.c | |||
@@ -106,7 +106,7 @@ static void mc13783_interrupt_thread(void) | |||
106 | * acknowledged. Reenable interrupt and if anything was still | 106 | * acknowledged. Reenable interrupt and if anything was still |
107 | * pending or became pending again, another signal will be | 107 | * pending or became pending again, another signal will be |
108 | * generated. */ | 108 | * generated. */ |
109 | imx31_regset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); | 109 | bitset32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); |
110 | 110 | ||
111 | event = mc13783_events; | 111 | event = mc13783_events; |
112 | event_last = event + MC13783_NUM_EVENTS; | 112 | event_last = event + MC13783_NUM_EVENTS; |
@@ -138,7 +138,7 @@ static void mc13783_interrupt_thread(void) | |||
138 | void mc13783_event(void) | 138 | void mc13783_event(void) |
139 | { | 139 | { |
140 | /* Mask the interrupt (unmasked when PMIC thread services it). */ | 140 | /* Mask the interrupt (unmasked when PMIC thread services it). */ |
141 | imx31_regclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); | 141 | bitclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE); |
142 | MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE); | 142 | MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE); |
143 | wakeup_signal(&mc13783_svc_wake); | 143 | wakeup_signal(&mc13783_svc_wake); |
144 | } | 144 | } |
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c index 4928108f67..381e589c08 100644 --- a/firmware/target/arm/imx31/sdma-imx31.c +++ b/firmware/target/arm/imx31/sdma-imx31.c | |||
@@ -414,12 +414,12 @@ static void set_channel_ownership(unsigned int channel, unsigned int config) | |||
414 | 414 | ||
415 | /* DSP side */ | 415 | /* DSP side */ |
416 | #if 0 /* Not using this */ | 416 | #if 0 /* Not using this */ |
417 | imx31_regmod32(&SDMA_DSPOVR, (config & CH_OWNSHP_DSP) ? 0 : bit, bit); | 417 | bitmod32(&SDMA_DSPOVR, (config & CH_OWNSHP_DSP) ? 0 : bit, bit); |
418 | #endif | 418 | #endif |
419 | /* Event */ | 419 | /* Event */ |
420 | imx31_regmod32(&SDMA_EVTOVR, (config & CH_OWNSHP_EVT) ? 0 : bit, bit); | 420 | bitmod32(&SDMA_EVTOVR, (config & CH_OWNSHP_EVT) ? 0 : bit, bit); |
421 | /* MCU side */ | 421 | /* MCU side */ |
422 | imx31_regmod32(&SDMA_HOSTOVR, (config & CH_OWNSHP_MCU) ? 0 : bit, bit); | 422 | bitmod32(&SDMA_HOSTOVR, (config & CH_OWNSHP_MCU) ? 0 : bit, bit); |
423 | } | 423 | } |
424 | 424 | ||
425 | static bool setup_channel(struct channel_control_block *ccb_p) | 425 | static bool setup_channel(struct channel_control_block *ccb_p) |
@@ -485,12 +485,12 @@ static bool setup_channel(struct channel_control_block *ccb_p) | |||
485 | if (channel_cfg & CH_OWNSHP_EVT) | 485 | if (channel_cfg & CH_OWNSHP_EVT) |
486 | { | 486 | { |
487 | /* Set event ID to channel activation bitmapping */ | 487 | /* Set event ID to channel activation bitmapping */ |
488 | imx31_regset32(&SDMA_CHNENBL(cd_p->event_id1), 1ul << channel); | 488 | bitset32(&SDMA_CHNENBL(cd_p->event_id1), 1ul << channel); |
489 | 489 | ||
490 | if (cd_p->per_type == SDMA_PER_ATA) | 490 | if (cd_p->per_type == SDMA_PER_ATA) |
491 | { | 491 | { |
492 | /* ATA has two */ | 492 | /* ATA has two */ |
493 | imx31_regset32(&SDMA_CHNENBL(cd_p->event_id2), 1ul << channel); | 493 | bitset32(&SDMA_CHNENBL(cd_p->event_id2), 1ul << channel); |
494 | } | 494 | } |
495 | } | 495 | } |
496 | 496 | ||
@@ -676,7 +676,7 @@ void sdma_channel_stop(unsigned int channel) | |||
676 | 676 | ||
677 | /* Unlock callback if it was set */ | 677 | /* Unlock callback if it was set */ |
678 | if (intmsk & chmsk) | 678 | if (intmsk & chmsk) |
679 | imx31_regset32(&sdma_enabled_ints, chmsk); | 679 | bitset32(&sdma_enabled_ints, chmsk); |
680 | 680 | ||
681 | logf("SDMA ch closed: %d", channel); | 681 | logf("SDMA ch closed: %d", channel); |
682 | } | 682 | } |
@@ -721,7 +721,7 @@ bool sdma_channel_init(unsigned int channel, | |||
721 | 721 | ||
722 | /* Enable interrupt if a callback is specified. */ | 722 | /* Enable interrupt if a callback is specified. */ |
723 | if (cd_p->callback != NULL) | 723 | if (cd_p->callback != NULL) |
724 | imx31_regset32(&sdma_enabled_ints, 1ul << channel); | 724 | bitset32(&sdma_enabled_ints, 1ul << channel); |
725 | 725 | ||
726 | /* Minimum schedulable = 1 */ | 726 | /* Minimum schedulable = 1 */ |
727 | sdma_channel_set_priority(channel, 1); | 727 | sdma_channel_set_priority(channel, 1); |
@@ -741,7 +741,7 @@ void sdma_channel_close(unsigned int channel) | |||
741 | ccb_p = &ccb_array[channel]; | 741 | ccb_p = &ccb_array[channel]; |
742 | 742 | ||
743 | /* Block callbacks (if not initialized, it won't be set). */ | 743 | /* Block callbacks (if not initialized, it won't be set). */ |
744 | imx31_regclr32(&sdma_enabled_ints, 1ul << channel); | 744 | bitclr32(&sdma_enabled_ints, 1ul << channel); |
745 | 745 | ||
746 | if (ccb_p->status.opened_init == 0) | 746 | if (ccb_p->status.opened_init == 0) |
747 | return; | 747 | return; |