diff options
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/config.h | 5 | ||||
-rw-r--r-- | firmware/export/imx31l.h | 10 | ||||
-rw-r--r-- | firmware/target/arm/imx31/app.lds | 42 | ||||
-rw-r--r-- | firmware/target/arm/imx31/ata-imx31.c | 8 | ||||
-rw-r--r-- | firmware/target/arm/imx31/boot.lds | 44 | ||||
-rw-r--r-- | firmware/target/arm/imx31/crt0.S | 43 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | 14 | ||||
-rw-r--r-- | firmware/target/arm/imx31/sdma-imx31.c | 4 |
8 files changed, 108 insertions, 62 deletions
diff --git a/firmware/export/config.h b/firmware/export/config.h index c3dd4fde93..070bd959b7 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h | |||
@@ -826,6 +826,11 @@ Lyre prototype 1 */ | |||
826 | 826 | ||
827 | #endif /* CPU_PP */ | 827 | #endif /* CPU_PP */ |
828 | 828 | ||
829 | #if CONFIG_CPU == IMX31L | ||
830 | #define NOCACHEBSS_ATTR __attribute__((section(".ncbss"),nocommon)) | ||
831 | #define NOCACHEDATA_ATTR __attribute__((section(".ncdata"),nocommon)) | ||
832 | #endif | ||
833 | |||
829 | #ifndef CONFIG_CORELOCK | 834 | #ifndef CONFIG_CORELOCK |
830 | #define CONFIG_CORELOCK CORELOCK_NONE | 835 | #define CONFIG_CORELOCK CORELOCK_NONE |
831 | #endif | 836 | #endif |
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 66ae0acc4d..ea92d059cc 100644 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -35,14 +35,18 @@ | |||
35 | #define FRAME_SIZE (240*320*2) | 35 | #define FRAME_SIZE (240*320*2) |
36 | /* Rockbox framebuffer address, not retail OS */ | 36 | /* Rockbox framebuffer address, not retail OS */ |
37 | #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE) | 37 | #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE) |
38 | #define FRAME ((void *)(FRAME_PHYS_ADDR-CSD0_BASE_ADDR)) | 38 | #define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR)) |
39 | |||
40 | #define CACHEALIGN_SIZE 32 | ||
41 | #define NOCACHE_BASE CSD0_BASE_ADDR | ||
39 | 42 | ||
40 | #define DEVBSS_ATTR __attribute__((section(".devbss"),nocommon)) | ||
41 | /* USBOTG */ | 43 | /* USBOTG */ |
42 | #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) | 44 | #define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048))) |
43 | #define USB_NUM_ENDPOINTS 8 | 45 | #define USB_NUM_ENDPOINTS 8 |
44 | #define USB_DEVBSS_ATTR DEVBSS_ATTR | 46 | #define USB_DEVBSS_ATTR NOCACHEBSS_ATTR |
45 | #define USB_BASE OTG_BASE_ADDR | 47 | #define USB_BASE OTG_BASE_ADDR |
48 | #define QHARRAY_SIZE ((64*USB_NUM_ENDPOINTS*2 + 2047) & (0xffffffff - 2047)) | ||
49 | #define QHARRAY_PHYS_ADDR ((FRAME_PHYS_ADDR - QHARRAY_SIZE) & (0xffffffff - 2047)) | ||
46 | 50 | ||
47 | /* | 51 | /* |
48 | * AIPS 1 | 52 | * AIPS 1 |
diff --git a/firmware/target/arm/imx31/app.lds b/firmware/target/arm/imx31/app.lds index 4ee7ac45d4..7043a55526 100644 --- a/firmware/target/arm/imx31/app.lds +++ b/firmware/target/arm/imx31/app.lds | |||
@@ -17,7 +17,8 @@ STARTUP(target/arm/imx31/crt0.o) | |||
17 | 17 | ||
18 | #include "imx31l.h" | 18 | #include "imx31l.h" |
19 | /* Subtract 1MB for the FRAME/TTB section */ | 19 | /* Subtract 1MB for the FRAME/TTB section */ |
20 | #define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE | 20 | #define DRAMSIZE ((MEMORYSIZE * 0x100000) - STUBOFFSET - CODECSIZE - \ |
21 | PLUGINSIZE - QHARRAY_SIZE - FRAME_SIZE - TTB_SIZE) | ||
21 | 22 | ||
22 | #define DRAMORIG (0x0 + STUBOFFSET) | 23 | #define DRAMORIG (0x0 + STUBOFFSET) |
23 | /* #define IRAMORIG 0x1FFFC000 */ | 24 | /* #define IRAMORIG 0x1FFFC000 */ |
@@ -34,8 +35,7 @@ STARTUP(target/arm/imx31/crt0.o) | |||
34 | MEMORY | 35 | MEMORY |
35 | { | 36 | { |
36 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | 37 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE |
37 | DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE * 0x100000 - 0x100000), \ | 38 | QHARRAY : ORIGIN = QHARRAY_PHYS_ADDR, LENGTH = QHARRAY_SIZE |
38 | LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE | ||
39 | } | 39 | } |
40 | 40 | ||
41 | SECTIONS | 41 | SECTIONS |
@@ -78,6 +78,17 @@ SECTIONS | |||
78 | _dataend = .; | 78 | _dataend = .; |
79 | } > DRAM | 79 | } > DRAM |
80 | 80 | ||
81 | #if 0 /* Unneeded at the moment */ | ||
82 | /* .ncdata section is placed at uncached physical alias address and is | ||
83 | * loaded at the proper cached virtual address - no copying is | ||
84 | * performed in the init code */ | ||
85 | .ncdata . + NOCACHE_BASE : | ||
86 | { | ||
87 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
88 | *(.ncdata*) | ||
89 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
90 | } AT> DRAM | ||
91 | #endif | ||
81 | /DISCARD/ : | 92 | /DISCARD/ : |
82 | { | 93 | { |
83 | *(.eh_frame) | 94 | *(.eh_frame) |
@@ -109,12 +120,22 @@ SECTIONS | |||
109 | *(.ibss) | 120 | *(.ibss) |
110 | *(COMMON) | 121 | *(COMMON) |
111 | . = ALIGN(0x4); | 122 | . = ALIGN(0x4); |
112 | _end = .; | 123 | } > DRAM |
124 | |||
125 | .ncbss . + NOCACHE_BASE (NOLOAD) : | ||
126 | { | ||
127 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
128 | *(.ncbss*) | ||
129 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
130 | } AT> DRAM | ||
131 | |||
132 | .endaddr . - NOCACHE_BASE (NOLOAD) : | ||
133 | { | ||
134 | _end = .; | ||
113 | } > DRAM | 135 | } > DRAM |
114 | 136 | ||
115 | .audiobuf (NOLOAD) : | 137 | .audiobuf (NOLOAD) : |
116 | { | 138 | { |
117 | . = ALIGN(0x4); | ||
118 | _audiobuffer = .; | 139 | _audiobuffer = .; |
119 | audiobuffer = .; | 140 | audiobuffer = .; |
120 | } > DRAM | 141 | } > DRAM |
@@ -144,12 +165,11 @@ SECTIONS | |||
144 | _sdmacodeend = .; | 165 | _sdmacodeend = .; |
145 | } | 166 | } |
146 | 167 | ||
147 | .devbss (NOLOAD) : | 168 | .qharray (NOLOAD) : |
148 | { | 169 | { |
149 | _devbssdata = .; | 170 | _qharray = .; |
150 | *(.qharray) | 171 | *(.qharray) |
151 | *(.devbss*) | 172 | _qharrayend = .; |
152 | _devbssend = .; | 173 | } > QHARRAY |
153 | } > DEVBSS | ||
154 | } | 174 | } |
155 | 175 | ||
diff --git a/firmware/target/arm/imx31/ata-imx31.c b/firmware/target/arm/imx31/ata-imx31.c index 5ce7ad0a03..4c6bebd168 100644 --- a/firmware/target/arm/imx31/ata-imx31.c +++ b/firmware/target/arm/imx31/ata-imx31.c | |||
@@ -249,17 +249,17 @@ static struct wakeup ata_dma_wakeup; | |||
249 | 249 | ||
250 | /** SDMA **/ | 250 | /** SDMA **/ |
251 | /* Array of buffer descriptors for large transfers and alignnment */ | 251 | /* Array of buffer descriptors for large transfers and alignnment */ |
252 | static struct buffer_descriptor ata_bda[ATA_BD_COUNT] DEVBSS_ATTR; | 252 | static struct buffer_descriptor ata_bda[ATA_BD_COUNT] NOCACHEBSS_ATTR; |
253 | /* ATA channel descriptors */ | 253 | /* ATA channel descriptors */ |
254 | static struct channel_descriptor ata_cd_rd DEVBSS_ATTR; /* read channel */ | 254 | static struct channel_descriptor ata_cd_rd NOCACHEBSS_ATTR; /* read channel */ |
255 | static struct channel_descriptor ata_cd_wr DEVBSS_ATTR; /* write channel */ | 255 | static struct channel_descriptor ata_cd_wr NOCACHEBSS_ATTR; /* write channel */ |
256 | /* DMA channel to be started for transfer */ | 256 | /* DMA channel to be started for transfer */ |
257 | static unsigned int current_channel = 0; | 257 | static unsigned int current_channel = 0; |
258 | 258 | ||
259 | /** Buffers **/ | 259 | /** Buffers **/ |
260 | /* Scatter buffer for first and last 32 bytes of a non cache-aligned transfer | 260 | /* Scatter buffer for first and last 32 bytes of a non cache-aligned transfer |
261 | * to cached RAM. */ | 261 | * to cached RAM. */ |
262 | static uint32_t scatter_buffer[32/4*2] DEVBSS_ATTR; | 262 | static uint32_t scatter_buffer[32/4*2] NOCACHEBSS_ATTR; |
263 | /* Address of ends in destination buffer for unaligned reads - copied after | 263 | /* Address of ends in destination buffer for unaligned reads - copied after |
264 | * DMA completes. */ | 264 | * DMA completes. */ |
265 | static void *sb_dst[2] = { NULL, NULL }; | 265 | static void *sb_dst[2] = { NULL, NULL }; |
diff --git a/firmware/target/arm/imx31/boot.lds b/firmware/target/arm/imx31/boot.lds index e08b4bfb7a..6030044c85 100644 --- a/firmware/target/arm/imx31/boot.lds +++ b/firmware/target/arm/imx31/boot.lds | |||
@@ -19,8 +19,7 @@ STARTUP(target/arm/imx31/crt0.o) | |||
19 | MEMORY | 19 | MEMORY |
20 | { | 20 | { |
21 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | 21 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE |
22 | DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE*0x100000 - 0x100000), \ | 22 | QHARRAY : ORIGIN = QHARRAY_PHYS_ADDR, LENGTH = QHARRAY_SIZE |
23 | LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE | ||
24 | } | 23 | } |
25 | 24 | ||
26 | SECTIONS | 25 | SECTIONS |
@@ -59,6 +58,18 @@ SECTIONS | |||
59 | . = ALIGN(0x4); | 58 | . = ALIGN(0x4); |
60 | _dataend = . ; | 59 | _dataend = . ; |
61 | } > DRAM | 60 | } > DRAM |
61 | |||
62 | #if 0 /* Unneeded at the moment */ | ||
63 | /* .ncdata section is placed at uncached physical alias address and is | ||
64 | * loaded at the proper cached virtual address - no copying is | ||
65 | * performed in the init code */ | ||
66 | .ncdata . + NOCACHE_BASE : | ||
67 | { | ||
68 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
69 | *(.ncdata*) | ||
70 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
71 | } AT> DRAM | ||
72 | #endif | ||
62 | 73 | ||
63 | .vectors 0x0 : | 74 | .vectors 0x0 : |
64 | { | 75 | { |
@@ -79,20 +90,33 @@ SECTIONS | |||
79 | stackend = .; | 90 | stackend = .; |
80 | } > IRAM | 91 | } > IRAM |
81 | 92 | ||
93 | /* .bss and .ncbss are treated as a single section to use one init loop to | ||
94 | * zero it - note "_edata" and "_end" */ | ||
82 | .bss (NOLOAD) : | 95 | .bss (NOLOAD) : |
83 | { | 96 | { |
84 | _edata = .; | 97 | _edata = .; |
85 | *(.bss*); | 98 | *(.bss*); |
86 | *(.ibss); | 99 | *(.ibss); |
87 | *(COMMON) | 100 | *(COMMON) |
88 | _end = .; | 101 | . = ALIGN(0x4); |
102 | } > DRAM | ||
103 | |||
104 | .ncbss . + NOCACHE_BASE (NOLOAD) : | ||
105 | { | ||
106 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
107 | *(.ncbss*) | ||
108 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
109 | } AT> DRAM | ||
110 | |||
111 | .endaddr . - NOCACHE_BASE (NOLOAD) : | ||
112 | { | ||
113 | _end = .; | ||
89 | } > DRAM | 114 | } > DRAM |
90 | 115 | ||
91 | .devbss (NOLOAD) : | 116 | .qharray (NOLOAD) : |
92 | { | 117 | { |
93 | _devbssdata = .; | 118 | _qharray = .; |
94 | *(.qharray) | 119 | *(.qharray) |
95 | *(.devbss*) | 120 | _qharrayend = .; |
96 | _devbssend = .; | 121 | } > QHARRAY |
97 | } > DEVBSS | ||
98 | } | 122 | } |
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S index 3a0a0041d4..979306e264 100644 --- a/firmware/target/arm/imx31/crt0.S +++ b/firmware/target/arm/imx31/crt0.S | |||
@@ -134,7 +134,8 @@ remap_start: | |||
134 | 134 | ||
135 | /* Set page tables */ | 135 | /* Set page tables */ |
136 | 136 | ||
137 | /* Map each memory loc to itself, no cache */ | 137 | /* Map each memory loc to itself |
138 | * not cached, not buffered */ | ||
138 | /* Physical address = 0x0 */ | 139 | /* Physical address = 0x0 */ |
139 | mov r1, #(1 << 10) /* superuser - r/w, user - no access */ | 140 | mov r1, #(1 << 10) /* superuser - r/w, user - no access */ |
140 | orr r1, r1, #((0 << 5) | /* domain 0th */ \ | 141 | orr r1, r1, #((0 << 5) | /* domain 0th */ \ |
@@ -148,27 +149,28 @@ remap_start: | |||
148 | cmp r2, r3 | 149 | cmp r2, r3 |
149 | blo 1b | 150 | blo 1b |
150 | 151 | ||
151 | bic r1, r1, #0x0ff00000 /* Back up */ | 152 | /* Bits 31:20 of r1 will be 0 due to wraparound in previous loop */ |
152 | 153 | ||
153 | /* Map 0x80000000 -> 0x0, cached */ | 154 | /* Map PA:0x80000000-0x83ffffff to VA:0x00000000-0x03f00000 |
154 | mov r2, r5 /* TTB pointer */ | 155 | * cached, buffered */ |
155 | add r3, r5, #64*4 /* End position */ | 156 | mov r2, r5 /* TTB pointer */ |
156 | orr r1, r1, #0x80000000 /* Physical address */ | 157 | add r3, r5, #64*4 /* End position */ |
157 | orr r1, r1, #((1 << 3) | /* cache flag */ \ | 158 | orr r1, r1, #(0x80000000 | /* Physical address */ \ |
158 | (1 << 2)) /* buffer flag */ | 159 | (1 << 3) | /* cache flag */ \ |
160 | (1 << 2)) /* buffer flag */ | ||
159 | 1: | 161 | 1: |
160 | str r1, [r2], #4 | 162 | str r1, [r2], #4 |
161 | add r1, r1, #(1 << 20) | 163 | add r1, r1, #(1 << 20) |
162 | cmp r2, r3 | 164 | cmp r2, r3 |
163 | blo 1b | 165 | blo 1b |
164 | 166 | ||
165 | /* Map device section 0x83f00000 to 0x03f00000 - buffered, not cached */ | 167 | /* Map TTB, FRAME and QHARRAY section PA:0x83f00000-0x83ffffff to |
166 | bic r1, r1, #0x0ff00000 | 168 | * VA:0x04000000-0x040fffff |
167 | orr r1, r1, #0x03f00000 | 169 | * not cache, buffered */ |
168 | bic r1, r1, #(1 << 3) | 170 | sub r1, r1, #0x00100000 |
169 | add r2, r5, #63*4 | 171 | bic r1, r1, #(1 << 3) /* clear cache flag */ |
170 | str r1, [r2] | 172 | str r1, [r5, #64*4] |
171 | 173 | ||
172 | /* Enable MMU */ | 174 | /* Enable MMU */ |
173 | mov r0, #0 | 175 | mov r0, #0 |
174 | mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */ | 176 | mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */ |
@@ -249,7 +251,7 @@ remap_end: | |||
249 | bl clean_dcache_range | 251 | bl clean_dcache_range |
250 | #endif /* BOOTLOADER */ | 252 | #endif /* BOOTLOADER */ |
251 | 253 | ||
252 | /* Initialise bss section to zero */ | 254 | /* Initialise bss and ncbss sections to zero */ |
253 | ldr r2, =_edata | 255 | ldr r2, =_edata |
254 | ldr r3, =_end | 256 | ldr r3, =_end |
255 | mov r4, #0 | 257 | mov r4, #0 |
@@ -257,15 +259,6 @@ remap_end: | |||
257 | cmp r3, r2 | 259 | cmp r3, r2 |
258 | strhi r4, [r2], #4 | 260 | strhi r4, [r2], #4 |
259 | bhi 1b | 261 | bhi 1b |
260 | |||
261 | /* Initialise the device bss section to zero */ | ||
262 | ldr r2, =_devbssdata | ||
263 | ldr r3, =_devbssend | ||
264 | mov r4, #0 | ||
265 | 1: | ||
266 | cmp r3, r2 | ||
267 | strhi r4, [r2], #4 | ||
268 | bhi 1b | ||
269 | 262 | ||
270 | /* Set up some stack and munge it with 0xdeadbeef */ | 263 | /* Set up some stack and munge it with 0xdeadbeef */ |
271 | ldr sp, =stackend | 264 | ldr sp, =stackend |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c index 6cec3ecdd3..c0651caf51 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c | |||
@@ -32,8 +32,8 @@ | |||
32 | #define DMA_PLAY_CH_PRIORITY 6 | 32 | #define DMA_PLAY_CH_PRIORITY 6 |
33 | #define DMA_REC_CH_PRIORITY 6 | 33 | #define DMA_REC_CH_PRIORITY 6 |
34 | 34 | ||
35 | static struct buffer_descriptor dma_play_bd DEVBSS_ATTR; | 35 | static struct buffer_descriptor dma_play_bd NOCACHEBSS_ATTR; |
36 | static struct channel_descriptor dma_play_cd DEVBSS_ATTR; | 36 | static struct channel_descriptor dma_play_cd NOCACHEBSS_ATTR; |
37 | 37 | ||
38 | struct dma_data | 38 | struct dma_data |
39 | { | 39 | { |
@@ -315,7 +315,7 @@ void pcm_play_dma_pause(bool pause) | |||
315 | /* Return the number of bytes waiting - full L-R sample pairs only */ | 315 | /* Return the number of bytes waiting - full L-R sample pairs only */ |
316 | size_t pcm_get_bytes_waiting(void) | 316 | size_t pcm_get_bytes_waiting(void) |
317 | { | 317 | { |
318 | static unsigned long dsa DEVBSS_ATTR; | 318 | static unsigned long dsa NOCACHEBSS_ATTR; |
319 | long offs, size; | 319 | long offs, size; |
320 | int oldstatus; | 320 | int oldstatus; |
321 | 321 | ||
@@ -339,7 +339,7 @@ size_t pcm_get_bytes_waiting(void) | |||
339 | /* Return a pointer to the samples and the number of them in *count */ | 339 | /* Return a pointer to the samples and the number of them in *count */ |
340 | const void * pcm_play_dma_get_peak_buffer(int *count) | 340 | const void * pcm_play_dma_get_peak_buffer(int *count) |
341 | { | 341 | { |
342 | static unsigned long dsa DEVBSS_ATTR; | 342 | static unsigned long dsa NOCACHEBSS_ATTR; |
343 | unsigned long addr; | 343 | unsigned long addr; |
344 | long offs, size; | 344 | long offs, size; |
345 | int oldstatus; | 345 | int oldstatus; |
@@ -370,8 +370,8 @@ void * pcm_dma_addr(void *addr) | |||
370 | } | 370 | } |
371 | 371 | ||
372 | #ifdef HAVE_RECORDING | 372 | #ifdef HAVE_RECORDING |
373 | static struct buffer_descriptor dma_rec_bd DEVBSS_ATTR; | 373 | static struct buffer_descriptor dma_rec_bd NOCACHEBSS_ATTR; |
374 | static struct channel_descriptor dma_rec_cd DEVBSS_ATTR; | 374 | static struct channel_descriptor dma_rec_cd NOCACHEBSS_ATTR; |
375 | 375 | ||
376 | static struct dma_data dma_rec_data = | 376 | static struct dma_data dma_rec_data = |
377 | { | 377 | { |
@@ -526,7 +526,7 @@ void pcm_rec_dma_init(void) | |||
526 | 526 | ||
527 | const void * pcm_rec_dma_get_peak_buffer(int *count) | 527 | const void * pcm_rec_dma_get_peak_buffer(int *count) |
528 | { | 528 | { |
529 | static unsigned long pda DEVBSS_ATTR; | 529 | static unsigned long pda NOCACHEBSS_ATTR; |
530 | unsigned long buf, addr, end, bufend; | 530 | unsigned long buf, addr, end, bufend; |
531 | int oldstatus; | 531 | int oldstatus; |
532 | 532 | ||
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c index 40a43f8121..a877d5824b 100644 --- a/firmware/target/arm/imx31/sdma-imx31.c +++ b/firmware/target/arm/imx31/sdma-imx31.c | |||
@@ -40,9 +40,9 @@ static struct sdma_script_start_addrs script_info; | |||
40 | /* Mask of channels with callback enabled */ | 40 | /* Mask of channels with callback enabled */ |
41 | static unsigned long sdma_enabled_ints = 0; | 41 | static unsigned long sdma_enabled_ints = 0; |
42 | /* One channel control block per channel in physically mapped device RAM */ | 42 | /* One channel control block per channel in physically mapped device RAM */ |
43 | static struct channel_control_block ccb_array[CH_NUM] DEVBSS_ATTR; | 43 | static struct channel_control_block ccb_array[CH_NUM] NOCACHEBSS_ATTR; |
44 | /* Channel 0 (command channel) data */ | 44 | /* Channel 0 (command channel) data */ |
45 | static struct buffer_descriptor_extd c0_buffer_desc DEVBSS_ATTR; | 45 | static struct buffer_descriptor_extd c0_buffer_desc NOCACHEBSS_ATTR; |
46 | 46 | ||
47 | /* All SDMA channel interrupts are handled here. | 47 | /* All SDMA channel interrupts are handled here. |
48 | * Dispatches lower channel numbers first (prioritized by SDMA API callers | 48 | * Dispatches lower channel numbers first (prioritized by SDMA API callers |