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Diffstat (limited to 'firmware/target/arm/imx31/crt0.S')
-rw-r--r--firmware/target/arm/imx31/crt0.S43
1 files changed, 18 insertions, 25 deletions
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S
index 3a0a0041d4..979306e264 100644
--- a/firmware/target/arm/imx31/crt0.S
+++ b/firmware/target/arm/imx31/crt0.S
@@ -134,7 +134,8 @@ remap_start:
134 134
135 /* Set page tables */ 135 /* Set page tables */
136 136
137 /* Map each memory loc to itself, no cache */ 137 /* Map each memory loc to itself
138 * not cached, not buffered */
138 /* Physical address = 0x0 */ 139 /* Physical address = 0x0 */
139 mov r1, #(1 << 10) /* superuser - r/w, user - no access */ 140 mov r1, #(1 << 10) /* superuser - r/w, user - no access */
140 orr r1, r1, #((0 << 5) | /* domain 0th */ \ 141 orr r1, r1, #((0 << 5) | /* domain 0th */ \
@@ -148,27 +149,28 @@ remap_start:
148 cmp r2, r3 149 cmp r2, r3
149 blo 1b 150 blo 1b
150 151
151 bic r1, r1, #0x0ff00000 /* Back up */ 152 /* Bits 31:20 of r1 will be 0 due to wraparound in previous loop */
152 153
153 /* Map 0x80000000 -> 0x0, cached */ 154 /* Map PA:0x80000000-0x83ffffff to VA:0x00000000-0x03f00000
154 mov r2, r5 /* TTB pointer */ 155 * cached, buffered */
155 add r3, r5, #64*4 /* End position */ 156 mov r2, r5 /* TTB pointer */
156 orr r1, r1, #0x80000000 /* Physical address */ 157 add r3, r5, #64*4 /* End position */
157 orr r1, r1, #((1 << 3) | /* cache flag */ \ 158 orr r1, r1, #(0x80000000 | /* Physical address */ \
158 (1 << 2)) /* buffer flag */ 159 (1 << 3) | /* cache flag */ \
160 (1 << 2)) /* buffer flag */
1591: 1611:
160 str r1, [r2], #4 162 str r1, [r2], #4
161 add r1, r1, #(1 << 20) 163 add r1, r1, #(1 << 20)
162 cmp r2, r3 164 cmp r2, r3
163 blo 1b 165 blo 1b
164 166
165 /* Map device section 0x83f00000 to 0x03f00000 - buffered, not cached */ 167 /* Map TTB, FRAME and QHARRAY section PA:0x83f00000-0x83ffffff to
166 bic r1, r1, #0x0ff00000 168 * VA:0x04000000-0x040fffff
167 orr r1, r1, #0x03f00000 169 * not cache, buffered */
168 bic r1, r1, #(1 << 3) 170 sub r1, r1, #0x00100000
169 add r2, r5, #63*4 171 bic r1, r1, #(1 << 3) /* clear cache flag */
170 str r1, [r2] 172 str r1, [r5, #64*4]
171 173
172 /* Enable MMU */ 174 /* Enable MMU */
173 mov r0, #0 175 mov r0, #0
174 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */ 176 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */
@@ -249,7 +251,7 @@ remap_end:
249 bl clean_dcache_range 251 bl clean_dcache_range
250#endif /* BOOTLOADER */ 252#endif /* BOOTLOADER */
251 253
252 /* Initialise bss section to zero */ 254 /* Initialise bss and ncbss sections to zero */
253 ldr r2, =_edata 255 ldr r2, =_edata
254 ldr r3, =_end 256 ldr r3, =_end
255 mov r4, #0 257 mov r4, #0
@@ -257,15 +259,6 @@ remap_end:
257 cmp r3, r2 259 cmp r3, r2
258 strhi r4, [r2], #4 260 strhi r4, [r2], #4
259 bhi 1b 261 bhi 1b
260
261 /* Initialise the device bss section to zero */
262 ldr r2, =_devbssdata
263 ldr r3, =_devbssend
264 mov r4, #0
2651:
266 cmp r3, r2
267 strhi r4, [r2], #4
268 bhi 1b
269 262
270 /* Set up some stack and munge it with 0xdeadbeef */ 263 /* Set up some stack and munge it with 0xdeadbeef */
271 ldr sp, =stackend 264 ldr sp, =stackend