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Diffstat (limited to 'firmware/target/arm/imx31/app.lds')
-rw-r--r--firmware/target/arm/imx31/app.lds42
1 files changed, 31 insertions, 11 deletions
diff --git a/firmware/target/arm/imx31/app.lds b/firmware/target/arm/imx31/app.lds
index 4ee7ac45d4..7043a55526 100644
--- a/firmware/target/arm/imx31/app.lds
+++ b/firmware/target/arm/imx31/app.lds
@@ -17,7 +17,8 @@ STARTUP(target/arm/imx31/crt0.o)
17 17
18#include "imx31l.h" 18#include "imx31l.h"
19/* Subtract 1MB for the FRAME/TTB section */ 19/* Subtract 1MB for the FRAME/TTB section */
20#define DRAMSIZE (MEMORYSIZE * 0x100000 - 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE 20#define DRAMSIZE ((MEMORYSIZE * 0x100000) - STUBOFFSET - CODECSIZE - \
21 PLUGINSIZE - QHARRAY_SIZE - FRAME_SIZE - TTB_SIZE)
21 22
22#define DRAMORIG (0x0 + STUBOFFSET) 23#define DRAMORIG (0x0 + STUBOFFSET)
23/* #define IRAMORIG 0x1FFFC000 */ 24/* #define IRAMORIG 0x1FFFC000 */
@@ -34,8 +35,7 @@ STARTUP(target/arm/imx31/crt0.o)
34MEMORY 35MEMORY
35{ 36{
36 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE 37 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
37 DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE * 0x100000 - 0x100000), \ 38 QHARRAY : ORIGIN = QHARRAY_PHYS_ADDR, LENGTH = QHARRAY_SIZE
38 LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE
39} 39}
40 40
41SECTIONS 41SECTIONS
@@ -78,6 +78,17 @@ SECTIONS
78 _dataend = .; 78 _dataend = .;
79 } > DRAM 79 } > DRAM
80 80
81#if 0 /* Unneeded at the moment */
82 /* .ncdata section is placed at uncached physical alias address and is
83 * loaded at the proper cached virtual address - no copying is
84 * performed in the init code */
85 .ncdata . + NOCACHE_BASE :
86 {
87 . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
88 *(.ncdata*)
89 . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
90 } AT> DRAM
91#endif
81 /DISCARD/ : 92 /DISCARD/ :
82 { 93 {
83 *(.eh_frame) 94 *(.eh_frame)
@@ -109,12 +120,22 @@ SECTIONS
109 *(.ibss) 120 *(.ibss)
110 *(COMMON) 121 *(COMMON)
111 . = ALIGN(0x4); 122 . = ALIGN(0x4);
112 _end = .; 123 } > DRAM
124
125 .ncbss . + NOCACHE_BASE (NOLOAD) :
126 {
127 . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
128 *(.ncbss*)
129 . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
130 } AT> DRAM
131
132 .endaddr . - NOCACHE_BASE (NOLOAD) :
133 {
134 _end = .;
113 } > DRAM 135 } > DRAM
114 136
115 .audiobuf (NOLOAD) : 137 .audiobuf (NOLOAD) :
116 { 138 {
117 . = ALIGN(0x4);
118 _audiobuffer = .; 139 _audiobuffer = .;
119 audiobuffer = .; 140 audiobuffer = .;
120 } > DRAM 141 } > DRAM
@@ -144,12 +165,11 @@ SECTIONS
144 _sdmacodeend = .; 165 _sdmacodeend = .;
145 } 166 }
146 167
147 .devbss (NOLOAD) : 168 .qharray (NOLOAD) :
148 { 169 {
149 _devbssdata = .; 170 _qharray = .;
150 *(.qharray) 171 *(.qharray)
151 *(.devbss*) 172 _qharrayend = .;
152 _devbssend = .; 173 } > QHARRAY
153 } > DEVBSS
154} 174}
155 175