diff options
Diffstat (limited to 'firmware/target/arm/imx31/boot.lds')
-rw-r--r-- | firmware/target/arm/imx31/boot.lds | 44 |
1 files changed, 34 insertions, 10 deletions
diff --git a/firmware/target/arm/imx31/boot.lds b/firmware/target/arm/imx31/boot.lds index e08b4bfb7a..6030044c85 100644 --- a/firmware/target/arm/imx31/boot.lds +++ b/firmware/target/arm/imx31/boot.lds | |||
@@ -19,8 +19,7 @@ STARTUP(target/arm/imx31/crt0.o) | |||
19 | MEMORY | 19 | MEMORY |
20 | { | 20 | { |
21 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | 21 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE |
22 | DEVBSS : ORIGIN = CSD0_BASE_ADDR + (MEMORYSIZE*0x100000 - 0x100000), \ | 22 | QHARRAY : ORIGIN = QHARRAY_PHYS_ADDR, LENGTH = QHARRAY_SIZE |
23 | LENGTH = 0x100000 - FRAME_SIZE - TTB_SIZE | ||
24 | } | 23 | } |
25 | 24 | ||
26 | SECTIONS | 25 | SECTIONS |
@@ -59,6 +58,18 @@ SECTIONS | |||
59 | . = ALIGN(0x4); | 58 | . = ALIGN(0x4); |
60 | _dataend = . ; | 59 | _dataend = . ; |
61 | } > DRAM | 60 | } > DRAM |
61 | |||
62 | #if 0 /* Unneeded at the moment */ | ||
63 | /* .ncdata section is placed at uncached physical alias address and is | ||
64 | * loaded at the proper cached virtual address - no copying is | ||
65 | * performed in the init code */ | ||
66 | .ncdata . + NOCACHE_BASE : | ||
67 | { | ||
68 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
69 | *(.ncdata*) | ||
70 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
71 | } AT> DRAM | ||
72 | #endif | ||
62 | 73 | ||
63 | .vectors 0x0 : | 74 | .vectors 0x0 : |
64 | { | 75 | { |
@@ -79,20 +90,33 @@ SECTIONS | |||
79 | stackend = .; | 90 | stackend = .; |
80 | } > IRAM | 91 | } > IRAM |
81 | 92 | ||
93 | /* .bss and .ncbss are treated as a single section to use one init loop to | ||
94 | * zero it - note "_edata" and "_end" */ | ||
82 | .bss (NOLOAD) : | 95 | .bss (NOLOAD) : |
83 | { | 96 | { |
84 | _edata = .; | 97 | _edata = .; |
85 | *(.bss*); | 98 | *(.bss*); |
86 | *(.ibss); | 99 | *(.ibss); |
87 | *(COMMON) | 100 | *(COMMON) |
88 | _end = .; | 101 | . = ALIGN(0x4); |
102 | } > DRAM | ||
103 | |||
104 | .ncbss . + NOCACHE_BASE (NOLOAD) : | ||
105 | { | ||
106 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
107 | *(.ncbss*) | ||
108 | . = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */ | ||
109 | } AT> DRAM | ||
110 | |||
111 | .endaddr . - NOCACHE_BASE (NOLOAD) : | ||
112 | { | ||
113 | _end = .; | ||
89 | } > DRAM | 114 | } > DRAM |
90 | 115 | ||
91 | .devbss (NOLOAD) : | 116 | .qharray (NOLOAD) : |
92 | { | 117 | { |
93 | _devbssdata = .; | 118 | _qharray = .; |
94 | *(.qharray) | 119 | *(.qharray) |
95 | *(.devbss*) | 120 | _qharrayend = .; |
96 | _devbssend = .; | 121 | } > QHARRAY |
97 | } > DEVBSS | ||
98 | } | 122 | } |