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-rw-r--r--bootloader/SOURCES2
-rwxr-xr-xbootloader/mrobe500.c135
-rw-r--r--firmware/SOURCES18
-rw-r--r--firmware/app.lds20
-rw-r--r--firmware/boot.lds125
-rw-r--r--firmware/export/config-mrobe500.h129
-rw-r--r--firmware/export/config.h7
-rw-r--r--firmware/export/cpu.h3
-rw-r--r--firmware/export/dm320.h704
-rw-r--r--firmware/export/timer.h2
-rw-r--r--firmware/sound.c2
-rw-r--r--firmware/target/arm/crt0.S187
-rw-r--r--firmware/target/arm/memswap128-arm.S88
-rw-r--r--firmware/target/arm/olympus/mrobe-500/adc-mr500.c46
-rw-r--r--firmware/target/arm/olympus/mrobe-500/adc-target.h38
-rw-r--r--firmware/target/arm/olympus/mrobe-500/ata-mr500.c130
-rw-r--r--firmware/target/arm/olympus/mrobe-500/ata-target.h71
-rw-r--r--firmware/target/arm/olympus/mrobe-500/backlight-mr500.c50
-rw-r--r--firmware/target/arm/olympus/mrobe-500/backlight-target.h31
-rw-r--r--firmware/target/arm/olympus/mrobe-500/button-mr500.c56
-rw-r--r--firmware/target/arm/olympus/mrobe-500/button-target.h99
-rw-r--r--firmware/target/arm/olympus/mrobe-500/kernel-mr500.c48
-rw-r--r--firmware/target/arm/olympus/mrobe-500/lcd-mr500.c206
-rw-r--r--firmware/target/arm/olympus/mrobe-500/lcd-target.h21
-rw-r--r--firmware/target/arm/olympus/mrobe-500/power-mr500.c93
-rw-r--r--firmware/target/arm/olympus/mrobe-500/system-mr500.c181
-rw-r--r--firmware/target/arm/olympus/mrobe-500/timer-mr500.c108
-rw-r--r--firmware/target/arm/olympus/mrobe-500/timer-target.h39
-rw-r--r--firmware/target/arm/olympus/mrobe-500/usb-mr500.c55
-rw-r--r--firmware/target/arm/system-arm.h9
-rw-r--r--firmware/target/arm/system-target.h2
-rw-r--r--firmware/thread.c7
-rw-r--r--firmware/timer.c4
-rwxr-xr-xtools/configure28
34 files changed, 2651 insertions, 93 deletions
diff --git a/bootloader/SOURCES b/bootloader/SOURCES
index 2de38930ea..2b499c1944 100644
--- a/bootloader/SOURCES
+++ b/bootloader/SOURCES
@@ -17,6 +17,8 @@ tpj1022.c
17iaudio_x5.c 17iaudio_x5.c
18#elif defined(IRIVER_H300_SERIES) 18#elif defined(IRIVER_H300_SERIES)
19iriver_h300.c 19iriver_h300.c
20#elif defined(MROBE_500)
21mrobe500.c
20#else 22#else
21main.c 23main.c
22#endif 24#endif
diff --git a/bootloader/mrobe500.c b/bootloader/mrobe500.c
new file mode 100755
index 0000000000..02726dde5a
--- /dev/null
+++ b/bootloader/mrobe500.c
@@ -0,0 +1,135 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20 #include "inttypes.h"
21#include "string.h"
22#include "cpu.h"
23#include "system.h"
24#include "lcd.h"
25#include "kernel.h"
26#include "thread.h"
27#include "ata.h"
28#include "fat.h"
29#include "disk.h"
30#include "font.h"
31#include "adc.h"
32#include "backlight.h"
33#include "backlight-target.h"
34#include "button.h"
35#include "panic.h"
36#include "power.h"
37#include "file.h"
38#include "common.h"
39#include "rbunicode.h"
40#include "usb.h"
41
42void main(void)
43{
44 unsigned char* loadbuffer;
45 int buffer_size;
46 int rc;
47 int(*kernel_entry)(void);
48
49 power_init();
50 system_init();
51 kernel_init();
52 adc_init();
53 button_init();
54 backlight_init();
55
56 lcd_init();
57 font_init();
58
59 lcd_setfont(FONT_SYSFIXED);
60
61 /* Show debug messages if button is pressed */
62// if(button_read_device())
63 verbose = true;
64
65 printf("Rockbox boot loader");
66 printf("Version %s", APPSVERSION);
67
68 usb_init();
69
70 #if 0
71 /* Enter USB mode without USB thread */
72 if(usb_detect())
73 {
74 const char msg[] = "Bootloader USB mode";
75 reset_screen();
76 lcd_putsxy( (LCD_WIDTH - (SYSFONT_WIDTH * strlen(msg))) / 2,
77 (LCD_HEIGHT - SYSFONT_HEIGHT) / 2, msg);
78 lcd_update();
79
80 ide_power_enable(true);
81 ata_enable(false);
82 sleep(HZ/20);
83 usb_enable(true);
84
85 while (usb_detect())
86 {
87 ata_spin(); /* Prevent the drive from spinning down */
88 sleep(HZ);
89 }
90
91 usb_enable(false);
92
93 reset_screen();
94 lcd_update();
95 }
96 #endif
97
98 printf("ATA");
99 while(true)
100 {
101 }
102#if 0
103 rc = ata_init();
104 if(rc)
105 {
106 reset_screen();
107 error(EATA, rc);
108 }
109
110 printf("disk");
111 disk_init();
112
113 printf("mount");
114 rc = disk_mount_all();
115 if (rc<=0)
116 {
117 error(EDISK,rc);
118 }
119
120 printf("Loading firmware");
121
122 loadbuffer = (unsigned char*) 0x00900000;
123 buffer_size = (unsigned char*)0x00100000 - loadbuffer;
124
125 rc = load_firmware(loadbuffer, BOOTFILE, buffer_size);
126 if(rc < 0)
127 error(EBOOTFILE, rc);
128
129 if (rc == EOK)
130 {
131 kernel_entry = (void*) loadbuffer;
132 rc = kernel_entry();
133 }
134#endif
135}
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 31b887c262..0f5da2fe6c 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -588,6 +588,24 @@ target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
588#endif /* SIMULATOR */ 588#endif /* SIMULATOR */
589#endif /* GIGABEAT_F */ 589#endif /* GIGABEAT_F */
590 590
591#ifdef MROBE_500
592#ifndef SIMULATOR
593target/arm/olympus/mrobe-500/adc-mr500.c
594target/arm/olympus/mrobe-500/ata-mr500.c
595target/arm/olympus/mrobe-500/backlight-mr500.c
596target/arm/olympus/mrobe-500/button-mr500.c
597target/arm/olympus/mrobe-500/kernel-mr500.c
598target/arm/olympus/mrobe-500/lcd-mr500.c
599target/arm/olympus/mrobe-500/power-mr500.c
600target/arm/olympus/mrobe-500/system-mr500.c
601target/arm/olympus/mrobe-500/timer-mr500.c
602target/arm/olympus/mrobe-500/usb-mr500.c
603#ifndef BOOTLOADER
604
605#endif
606#endif /* SIMULATOR */
607#endif /* MROBE_500 */
608
591#ifdef ELIO_TPJ1022 609#ifdef ELIO_TPJ1022
592#ifndef SIMULATOR 610#ifndef SIMULATOR
593target/arm/ata-as-arm.S 611target/arm/ata-as-arm.S
diff --git a/firmware/app.lds b/firmware/app.lds
index 8b0bed31d2..998ac40791 100644
--- a/firmware/app.lds
+++ b/firmware/app.lds
@@ -28,9 +28,13 @@ INPUT(target/sh/crt0.o)
28#define STUBOFFSET 0 28#define STUBOFFSET 0
29#endif 29#endif
30 30
31#if CONFIG_CPU!=S3C2440 31#if CONFIG_CPU==S3C2440
32#include "s3c2440.h"
33#define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE
34#else
32#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE 35#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
33#endif 36#endif
37
34#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300) 38#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300)
35#define DRAMORIG 0x31000000 + STUBOFFSET 39#define DRAMORIG 0x31000000 + STUBOFFSET
36#define IRAMORIG 0x10000000 40#define IRAMORIG 0x10000000
@@ -48,12 +52,14 @@ INPUT(target/sh/crt0.o)
48#define IRAMORIG 0x400000 52#define IRAMORIG 0x400000
49#define IRAMSIZE 0x7000 53#define IRAMSIZE 0x7000
50#elif CONFIG_CPU==S3C2440 54#elif CONFIG_CPU==S3C2440
51#include "s3c2440.h" 55#define DRAMORIG 0x00000100 + STUBOFFSET
52#define DRAMORIG (0x100 + STUBOFFSET)
53#define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - STUBOFFSET - LCD_BUFFER_SIZE - TTB_SIZE - PLUGINSIZE - CODECSIZE
54#define IRAMORIG DRAMORIG 56#define IRAMORIG DRAMORIG
55#define IRAMSIZE 4K 57#define IRAMSIZE 0x1000
56#define IRAM DRAM 58#define IRAM DRAM
59#elif CONFIG_CPU==DM320
60#define DRAMORIG 0x00900000 + STUBOFFSET
61#define IRAMORIG 0x00000000
62#define IRAMSIZE 0x4000
57#else 63#else
58#define DRAMORIG 0x09000000 + STUBOFFSET 64#define DRAMORIG 0x09000000 + STUBOFFSET
59#define IRAMORIG 0x0f000000 65#define IRAMORIG 0x0f000000
@@ -79,7 +85,7 @@ MEMORY
79 85
80SECTIONS 86SECTIONS
81{ 87{
82#ifndef CPU_ARM 88#if !defined(CPU_ARM)
83 .vectors : 89 .vectors :
84 { 90 {
85 loadaddress = .; 91 loadaddress = .;
@@ -136,7 +142,7 @@ SECTIONS
136 *(.eh_frame) 142 *(.eh_frame)
137 } 143 }
138 144
139#ifdef CPU_ARM 145#if defined(CPU_ARM)
140 .vectors 0x0 : 146 .vectors 0x0 :
141 { 147 {
142 _vectorsstart = .; 148 _vectorsstart = .;
diff --git a/firmware/boot.lds b/firmware/boot.lds
index 7f7bb9b12f..0e2ccc1b90 100644
--- a/firmware/boot.lds
+++ b/firmware/boot.lds
@@ -57,6 +57,12 @@ INPUT(target/sh/crt0.o)
57#define IRAMSIZE 4K 57#define IRAMSIZE 4K
58#define FLASHORIG 0x0000000 58#define FLASHORIG 0x0000000
59#define FLASHSIZE 1M 59#define FLASHSIZE 1M
60#elif CONFIG_CPU == DM320
61#define DRAMORIG 0x00900000
62#define IRAMORIG 0x00000000
63#define IRAMSIZE 16K
64#define FLASHORIG 0x00100000
65#define FLASHSIZE 8M
60#elif CONFIG_CPU == PP5002 66#elif CONFIG_CPU == PP5002
61#define DRAMORIG 0x28000000 67#define DRAMORIG 0x28000000
62#define IRAMORIG 0x40000000 68#define IRAMORIG 0x40000000
@@ -121,33 +127,94 @@ SECTIONS
121} 127}
122#elif (CONFIG_CPU==S3C2440) 128#elif (CONFIG_CPU==S3C2440)
123{ 129{
124 . = DRAMORIG + 0x1000000; 130 . = DRAMORIG + 0x1000000;
125 .text : { 131
126 *(.init.text) 132 .text : {
127 *(.text*) 133 *(.init.text)
128 } 134 *(.text*)
129 .data : { 135 }
130 *(.icode) 136
131 *(.irodata) 137 .data : {
132 *(.idata) 138 *(.icode)
133 *(.data*) 139 *(.irodata)
134 _dataend = . ; 140 *(.idata)
135 } 141 *(.data*)
136 .stack : 142 . = ALIGN(0x4);
137 { 143 _dataend = . ;
138 *(.stack) 144 }
139 _stackbegin = .; 145
140 stackbegin = .; 146 .stack :
141 . += 0x2000; 147 {
142 _stackend = .; 148 *(.stack)
143 stackend = .; 149 _stackbegin = .;
144 } 150 stackbegin = .;
145 .bss : { 151 . += 0x2000;
146 _edata = .; 152 _stackend = .;
147 *(.bss*); 153 stackend = .;
148 *(.ibss); 154 }
149 _end = .; 155 .bss : {
150 } 156 _edata = .;
157 *(.bss*);
158 *(.ibss);
159 _end = .;
160 }
161}
162#elif (CONFIG_CPU==DM320)
163{
164 . = DRAMORIG + 0x1000000;
165
166 .vectors 0x0 :
167 {
168 _vectorsstart = .;
169 *(.vectors);
170 _vectorsend = .;
171 } AT> DRAM
172 _vectorscopy = LOADADDR(.vectors);
173
174 .text : {
175 *(.init.text)
176 *(.text*)
177 *(.glue_7)
178 *(.glue_7t)
179 . = ALIGN(0x4);
180 } > DRAM
181
182 .rodata :
183 {
184 *(.rodata) /* problems without this, dunno why */
185 *(.rodata*)
186 *(.rodata.str1.1)
187 *(.rodata.str1.4)
188 . = ALIGN(0x4);
189
190 /* Pseudo-allocate the copies of the data sections */
191 _datacopy = .;
192 } > DRAM
193
194 .data : {
195 *(.icode)
196 *(.irodata)
197 *(.idata)
198 *(.data*)
199 . = ALIGN(0x4);
200 _dataend = . ;
201 } >DRAM
202
203 .stack :
204 {
205 *(.stack)
206 _stackbegin = .;
207 stackbegin = .;
208 . += 0x2000;
209 _stackend = .;
210 stackend = .;
211 } >DRAM
212 .bss : {
213 _edata = .;
214 *(.bss*);
215 *(.ibss);
216 _end = .;
217 }>DRAM
151} 218}
152#else 219#else
153{ 220{
@@ -172,10 +239,10 @@ SECTIONS
172 *(.idata) 239 *(.idata)
173 *(.data*) 240 *(.data*)
174 . = ALIGN(0x4); 241 . = ALIGN(0x4);
175 _dataend = .; 242 _dataend = .;
176 . = ALIGN(0x10); /* Maintain proper alignment for .text section */ 243 . = ALIGN(0x10); /* Maintain proper alignment for .text section */
177 } > IRAM 244 } > IRAM
178 245
179 /* TRICK ALERT! Newer versions of the linker don't allow output sections 246 /* TRICK ALERT! Newer versions of the linker don't allow output sections
180 to overlap even if one of them is empty, so advance the location pointer 247 to overlap even if one of them is empty, so advance the location pointer
181 "by hand" */ 248 "by hand" */
diff --git a/firmware/export/config-mrobe500.h b/firmware/export/config-mrobe500.h
new file mode 100644
index 0000000000..3e74db68b4
--- /dev/null
+++ b/firmware/export/config-mrobe500.h
@@ -0,0 +1,129 @@
1/*
2 * This config file is for toshiba Gigabeat F
3 */
4#define TARGET_TREE /* this target is using the target tree system */
5
6#define CONFIG_SDRAM_START 0x00900000
7
8#define OLYMPUS_MROBE_500 1
9
10/* For Rolo and boot loader */
11#define MODEL_NUMBER 19
12
13/* define this if you have a bitmap LCD display */
14#define HAVE_LCD_BITMAP
15
16/* define this if you have a colour LCD */
17#define HAVE_LCD_COLOR
18
19/* define this if you have access to the quickscreen */
20#define HAVE_QUICKSCREEN
21
22/* define this if you have access to the pitchscreen */
23#define HAVE_PITCHSCREEN
24
25/* define this if you would like tagcache to build on this target */
26#define HAVE_TAGCACHE
27
28/* define this if the target has volume keys which can be used in the lists */
29#define HAVE_VOLUME_IN_LIST
30
31/* LCD dimensions */
32#define LCD_WIDTH 480
33#define LCD_HEIGHT 640
34#define LCD_DEPTH 16 /* 65k colours */
35#define LCD_PIXELFORMAT RGB565 /* rgb565 */
36
37/* Define this if your LCD can be enabled/disabled */
38//#define HAVE_LCD_ENABLE
39
40#define CONFIG_KEYPAD MROBE500_PAD
41
42/* Define this if you do software codec */
43#define CONFIG_CODEC SWCODEC
44
45/* define this if you have a real-time clock */
46//#define CONFIG_RTC RTC_S3C2440
47
48/* Define this for LCD backlight available */
49#define HAVE_BACKLIGHT
50
51#define HAVE_BACKLIGHT_BRIGHTNESS
52
53/* Main LCD backlight brightness range and defaults */
54#define MIN_BRIGHTNESS_SETTING 0 /* 0.5 mA */
55#define MAX_DIM_BRIGHTNESS_SETTING 15 /* highest 'dimness' */
56#define MAX_BRIGHTNESS_SETTING 63 /* 32 mA */
57#define DEFAULT_BRIGHTNESS_SETTING 39 /* 20 mA */
58#define DEFAULT_DIMNESS_SETTING 9 /* 5 mA */
59
60/* Define this if you have a software controlled poweroff */
61#define HAVE_SW_POWEROFF
62
63/* The number of bytes reserved for loadable codecs */
64#define CODEC_SIZE 0x80000
65
66/* The number of bytes reserved for loadable plugins */
67#define PLUGIN_BUFFER_SIZE 0x80000
68
69/* Define this if you have the WM8975 audio codec */
70//#define HAVE_WM8751
71
72/* Define this if you want to use the adaptive bass capibility of the 8751 */
73/* #define USE_ADAPTIVE_BASS */
74
75#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \
76 SAMPR_CAP_11)
77
78#define BATTERY_CAPACITY_DEFAULT 1100 /* default battery capacity */
79#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */
80#define BATTERY_CAPACITY_MAX 2500 /* max. capacity selectable */
81#define BATTERY_CAPACITY_INC 100 /* capacity increment */
82#define BATTERY_TYPES_COUNT 1 /* only one type */
83
84/* Hardware controlled charging with monitoring */
85#define CONFIG_CHARGING CHARGING_MONITOR
86
87#ifndef SIMULATOR
88
89/* Define this if you have a Motorola SCF5249 */
90#define CONFIG_CPU DM320
91
92/* Define this if you want to use coldfire's i2c interface */
93//#define CONFIG_I2C I2C_S3C2440
94
95/* define this if the hardware can be powered off while charging */
96#define HAVE_POWEROFF_WHILE_CHARGING
97
98/* The size of the flash ROM */
99#define FLASH_SIZE 0x400000
100
101/* Define this to the CPU frequency */
102#define CPU_FREQ 16934400
103
104/* Define this if you have ATA power-off control */
105#define HAVE_ATA_POWER_OFF
106
107/* Virtual LED (icon) */
108#define CONFIG_LED LED_VIRTUAL
109
110#define CONFIG_LCD LCD_MROBE500
111
112/* define this if the backlight can be set to a brightness */
113#define HAVE_BACKLIGHT_SET_FADING
114#define __BACKLIGHT_INIT
115
116/* Offset ( in the firmware file's header ) to the file CRC */
117#define FIRMWARE_OFFSET_FILE_CRC 0
118
119/* Offset ( in the firmware file's header ) to the real data */
120#define FIRMWARE_OFFSET_FILE_DATA 8
121
122/* Define this if you have adjustable CPU frequency */
123/* #define HAVE_ADJUSTABLE_CPU_FREQ */
124
125#define BOOTFILE_EXT "mrobe500"
126#define BOOTFILE "rockbox." BOOTFILE_EXT
127#define BOOTDIR "/.rockbox"
128
129#endif
diff --git a/firmware/export/config.h b/firmware/export/config.h
index a18bf14a97..4a4185fdc3 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -48,6 +48,7 @@
48#define PNX0101 101 48#define PNX0101 101
49#define S3C2440 2440 49#define S3C2440 2440
50#define TMS320DSC25 25 50#define TMS320DSC25 25
51#define DM320 320
51 52
52/* CONFIG_KEYPAD */ 53/* CONFIG_KEYPAD */
53#define PLAYER_PAD 1 54#define PLAYER_PAD 1
@@ -66,6 +67,7 @@
66#define SANSA_C200_PAD 14 67#define SANSA_C200_PAD 14
67#define ELIO_TPJ1022_PAD 15 68#define ELIO_TPJ1022_PAD 15
68#define ARCHOS_AV300_PAD 16 69#define ARCHOS_AV300_PAD 16
70#define MROBE500_PAD 17
69 71
70/* CONFIG_REMOTE_KEYPAD */ 72/* CONFIG_REMOTE_KEYPAD */
71#define H100_REMOTE 1 73#define H100_REMOTE 1
@@ -97,6 +99,7 @@
97#define LCD_TPJ1022 15 /* as used by Tatung Elio TPJ-1022 */ 99#define LCD_TPJ1022 15 /* as used by Tatung Elio TPJ-1022 */
98#define LCD_DSC25 16 /* as used by Archos AV300 */ 100#define LCD_DSC25 16 /* as used by Archos AV300 */
99#define LCD_C200 17 /* as used by Sandisk Sansa c200 */ 101#define LCD_C200 17 /* as used by Sandisk Sansa c200 */
102#define LCD_MROBE500 18 /* as used by Olympus M:Robe 500i */
100 103
101/* LCD_PIXELFORMAT */ 104/* LCD_PIXELFORMAT */
102#define HORIZONTAL_PACKING 1 105#define HORIZONTAL_PACKING 1
@@ -197,6 +200,8 @@
197#include "config-c200.h" 200#include "config-c200.h"
198#elif defined(ELIO_TPJ1022) 201#elif defined(ELIO_TPJ1022)
199#include "config-tpj1022.h" 202#include "config-tpj1022.h"
203#elif defined(MROBE_500)
204#include "config-mrobe500.h"
200#else 205#else
201/* no known platform */ 206/* no known platform */
202#endif 207#endif
@@ -294,7 +299,7 @@
294 299
295/* define for all cpus from ARM family */ 300/* define for all cpus from ARM family */
296#if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \ 301#if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \
297 || (CONFIG_CPU == TMS320DSC25) 302 || (CONFIG_CPU == TMS320DSC25) || (CONFIG_CPU == DM320)
298#define CPU_ARM 303#define CPU_ARM
299#endif 304#endif
300 305
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index eb1c57b646..ff9fbeec3a 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -42,3 +42,6 @@
42#if CONFIG_CPU == S3C2440 42#if CONFIG_CPU == S3C2440
43#include "s3c2440.h" 43#include "s3c2440.h"
44#endif 44#endif
45#if CONFIG_CPU == DM320
46#include "dm320.h"
47#endif
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h
new file mode 100644
index 0000000000..5e164cff57
--- /dev/null
+++ b/firmware/export/dm320.h
@@ -0,0 +1,704 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20/** All register offset definitions for the TI DM320
21 * Taken from: http://svn.neurostechnology.com/filedetails.php?repname=neuros-bsp&path=%2Ftrunk%2Fkernels%2Flinux-2.6.15%2Finclude%2Fasm-arm%2Farch-ntosd-dm320%2Fio_registers.h&rev=0&sc=0
22 */
23
24#ifndef __DM320_H__
25#define __DM320_H__
26
27#define FRAME ((short *) (0x4470000))
28
29#define PHY_IO_BASE 0x00030000
30
31/* Timer 0-3 */
32#define IO_TIMER0_TMMD 0x0000
33#define IO_TIMER0_TMRSV0 0x0002
34#define IO_TIMER0_TMPRSCL 0x0004
35#define IO_TIMER0_TMDIV 0x0006
36#define IO_TIMER0_TMTRG 0x0008
37#define IO_TIMER0_TMCNT 0x000A
38
39#define IO_TIMER1_TMMD 0x0080
40#define IO_TIMER1_TMRSV0 0x0082
41#define IO_TIMER1_TMPRSCL 0x0084
42#define IO_TIMER1_TMDIV 0x0086
43#define IO_TIMER1_TMTRG 0x0088
44#define IO_TIMER1_TMCNT 0x008A
45
46#define IO_TIMER2_TMMD 0x0100
47#define IO_TIMER2_TMVDCLR 0x0102
48#define IO_TIMER2_TMPRSCL 0x0104
49#define IO_TIMER2_TMDIV 0x0106
50#define IO_TIMER2_TMTRG 0x0108
51#define IO_TIMER2_TMCNT 0x010A
52
53#define IO_TIMER3_TMMD 0x0180
54#define IO_TIMER3_TMVDCLR 0x0182
55#define IO_TIMER3_TMPRSCL 0x0184
56#define IO_TIMER3_TMDIV 0x0186
57#define IO_TIMER3_TMTRG 0x0188
58#define IO_TIMER3_TMCNT 0x018A
59
60/* Serial 0/1 */
61#define IO_SERIAL0_TX_DATA 0x0200
62#define IO_SERIAL0_RX_DATA 0x0202
63#define IO_SERIAL0_TX_ENABLE 0x0204
64#define IO_SERIAL0_MODE 0x0206
65#define IO_SERIAL0_DMA_TRIGGER 0x0208
66#define IO_SERIAL0_DMA_MODE 0x020A
67#define IO_SERIAL0_DMA_SDRAM_LOW 0x020C
68#define IO_SERIAL0_DMA_SDRAM_HI 0x020E
69#define IO_SERIAL0_DMA_STATUS 0x0210
70
71#define IO_SERIAL1_TX_DATA 0x0280
72#define IO_SERIAL1_RX_DATA 0x0282
73#define IO_SERIAL1_TX_ENABLE 0x0284
74#define IO_SERIAL1_MODE 0x0286
75
76/* UART 0/1 */
77#define IO_UART0_DTRR 0x0300
78#define IO_UART0_BRSR 0x0302
79#define IO_UART0_MSR 0x0304
80#define IO_UART0_RFCR 0x0306
81#define IO_UART0_TFCR 0x0308
82#define IO_UART0_LCR 0x030A
83#define IO_UART0_SR 0x030C
84
85#define IO_UART1_DTRR 0x0380
86#define IO_UART1_BRSR 0x0382
87#define IO_UART1_MSR 0x0384
88#define IO_UART1_RFCR 0x0386
89#define IO_UART1_TFCR 0x0388
90#define IO_UART1_LCR 0x038A
91#define IO_UART1_SR 0x038C
92
93/* Watchdog Timer */
94#define IO_WATCHDOG_MODE 0x0400
95#define IO_WATCHDOG_RESET 0x0402
96#define IO_WATCHDOG_PRESCALAR 0x0404
97#define IO_WATCHDOG_DIVISOR 0x0406
98#define IO_WATCHDOG_EXT_RESET 0x0408
99
100/* MMC/SD Controller */
101#define IO_MMC_CONTROL 0x0480
102#define IO_MMC_MEM_CLK_CONTROL 0x0482
103#define IO_MMC_STATUS0 0x0484
104#define IO_MMC_STATUS1 0x0486
105#define IO_MMC_INT_ENABLE 0x0488
106#define IO_MMC_RESPONSE_TIMEOUT 0x048A
107#define IO_MMC_READ_TIMEOUT 0x048C
108#define IO_MMC_BLOCK_LENGTH 0x048E
109#define IO_MMC_NR_BLOCKS 0x0490
110#define IO_MMC_NR_BLOCKS_COUNT 0x0492
111#define IO_MMC_RX_DATA 0x0494
112#define IO_MMC_TX_DATA 0x0496
113#define IO_MMC_COMMAND 0x0498
114#define IO_MMC_ARG_LOW 0x049A
115#define IO_MMC_ARG_HI 0x049C
116#define IO_MMC_RESPONSE0 0x049E
117#define IO_MMC_RESPONSE1 0x04A0
118#define IO_MMC_RESPONSE2 0x04A2
119#define IO_MMC_RESPONSE3 0x04A4
120#define IO_MMC_RESPONSE4 0x04A6
121#define IO_MMC_RESPONSE5 0x04A8
122#define IO_MMC_RESPONSE6 0x04AA
123#define IO_MMC_RESPONSE7 0x04AC
124#define IO_MMC_SPI_DATA 0x04AE
125#define IO_MMC_SPI_ERR 0x04B0
126#define IO_MMC_COMMAND_INDEX 0x04B2
127#define IO_MMC_CLK_START_PHASE 0x04B4
128#define IO_MMC_RESPONSE_TOUT_CNT 0x04B6
129#define IO_MMC_READ_TOUT_CNT 0x04B8
130#define IO_MMC_BLOCK_LENGTH_CNT 0x04BA
131
132#define IO_MMC_SD_DMA_TRIGGER 0x04BC
133#define IO_MMC_SD_DMA_MODE 0x04BE
134#define IO_MMC_SD_DMA_ADDR_LOW 0x04C0
135#define IO_MMC_SD_DMA_ADDR_HI 0x04C2
136#define IO_MMC_SD_DMA_STATUS0 0x04C4
137#define IO_MMC_SD_DMA_STATUS1 0x04C6
138#define IO_MMC_SD_DMA_TIMEOUT 0x04C8
139
140#define IO_SDIO_CONTROL 0x04CA
141#define IO_SDIO_STATUS0 0x04CC
142#define IO_SDIO_INT_ENABLE 0x04CE
143#define IO_SDIO_INT_STATUS 0x04D0
144
145/* Interrupt Controller */
146#define IO_INTC_FIQ0 0x0500
147#define IO_INTC_FIQ1 0x0502
148#define IO_INTC_FIQ2 0x0504
149#define IO_INTC_IRQ0 0x0508
150#define IO_INTC_IRQ1 0x050A
151#define IO_INTC_IRQ2 0x050C
152#define IO_INTC_FIQENTRY0 0x0510
153#define IO_INTC_FIQENTRY1 0x0512
154#define IO_INTC_FIQ_LOCK_ADDR0 0x0514
155#define IO_INTC_FIQ_LOCK_ADDR1 0x0516
156#define IO_INTC_IRQENTRY0 0x0518
157#define IO_INTC_IRQENTRY1 0x051A
158#define IO_INTC_IRQ_LOCK_ADDR0 0x051C
159#define IO_INTC_IRQ_LOCK_ADDR1 0x051E
160#define IO_INTC_FISEL0 0x0520
161#define IO_INTC_FISEL1 0x0522
162#define IO_INTC_FISEL2 0x0524
163#define IO_INTC_EINT0 0x0528
164#define IO_INTC_EINT1 0x052A
165#define IO_INTC_EINT2 0x052C
166#define IO_INTC_RAW 0x0530
167#define IO_INTC_ENTRY_TBA0 0x0538
168#define IO_INTC_ENTRY_TBA1 0x053A
169#define IO_INTC_PRIORITY0 0x0540
170#define IO_INTC_PRIORITY1 0x0542
171#define IO_INTC_PRIORITY2 0x0544
172#define IO_INTC_PRIORITY3 0x0546
173#define IO_INTC_PRIORITY4 0x0548
174#define IO_INTC_PRIORITY5 0x054A
175#define IO_INTC_PRIORITY6 0x054C
176#define IO_INTC_PRIORITY7 0x054E
177#define IO_INTC_PRIORITY8 0x0550
178#define IO_INTC_PRIORITY9 0x0552
179#define IO_INTC_PRIORITY10 0x0554
180#define IO_INTC_PRIORITY11 0x0556
181#define IO_INTC_PRIORITY12 0x0558
182#define IO_INTC_PRIORITY13 0x055A
183#define IO_INTC_PRIORITY14 0x055C
184#define IO_INTC_PRIORITY15 0x055E
185#define IO_INTC_PRIORITY16 0x0560
186#define IO_INTC_PRIORITY17 0x0562
187#define IO_INTC_PRIORITY18 0x0564
188#define IO_INTC_PRIORITY19 0x0566
189#define IO_INTC_PRIORITY20 0x0568
190#define IO_INTC_PRIORITY21 0x056A
191#define IO_INTC_PRIORITY22 0x056C
192
193/* GIO Controller */
194#define IO_GIO_DIR0 0x0580
195#define IO_GIO_DIR1 0x0582
196#define IO_GIO_DIR2 0x0584
197#define IO_GIO_INV0 0x0586
198#define IO_GIO_INV1 0x0588
199#define IO_GIO_INV2 0x058A
200#define IO_GIO_BITSET0 0x058C
201#define IO_GIO_BITSET1 0x058E
202#define IO_GIO_BITSET2 0x0590
203#define IO_GIO_BITCLR0 0x0592
204#define IO_GIO_BITCLR1 0x0594
205#define IO_GIO_BITCLR2 0x0596
206#define IO_GIO_IRQPORT 0x0598
207#define IO_GIO_IRQEDGE 0x059A
208#define IO_GIO_CHAT0 0x059C
209#define IO_GIO_CHAT1 0x059E
210#define IO_GIO_CHAT2 0x05A0
211#define IO_GIO_NCHAT 0x05A2
212#define IO_GIO_FSEL0 0x05A4
213#define IO_GIO_FSEL1 0x05A6
214#define IO_GIO_FSEL2 0x05A8
215#define IO_GIO_FSEL3 0x05AA
216#define IO_GIO_FSEL4 0x05AC
217#define IO_GIO_CARD_SET 0x05AE
218#define IO_GIO_CARD_ST 0x05B0
219
220/* DSP Controller */
221#define IO_DSPC_HPIB_CONTROL 0x0600
222#define IO_DSPC_HPIB_STATUS 0x0602
223
224/* OSD Controller */
225#define IO_OSD_MODE 0x0680
226#define IO_OSD_VIDWINMD 0x0682
227#define IO_OSD_OSDWINMD0 0x0684
228#define IO_OSD_OSDWINMD1 0x0686
229#define IO_OSD_ATRMD 0x0688
230#define IO_OSD_RECTCUR 0x0688
231#define IO_OSD_RESERVED 0x068A
232#define IO_OSD_VIDWIN0OFST 0x068C
233#define IO_OSD_VIDWIN1OFST 0x068E
234#define IO_OSD_OSDWIN0OFST 0x0690
235#define IO_OSD_OSDWIN1OFST 0x0692
236#define IO_OSD_VIDWINADH 0x0694
237#define IO_OSD_VIDWIN0ADL 0x0696
238#define IO_OSD_VIDWIN1ADL 0x0698
239#define IO_OSD_OSDWINADH 0x069A
240#define IO_OSD_OSDWIN0ADL 0x069C
241#define IO_OSD_OSDWIN1ADL 0x069E
242#define IO_OSD_BASEPX 0x06A0
243#define IO_OSD_BASEPY 0x06A2
244#define IO_OSD_VIDWIN0XP 0x06A4
245#define IO_OSD_VIDWIN0YP 0x06A6
246#define IO_OSD_VIDWIN0XL 0x06A8
247#define IO_OSD_VIDWIN0YL 0x06AA
248#define IO_OSD_VIDWIN1XP 0x06AC
249#define IO_OSD_VIDWIN1YP 0x06AE
250#define IO_OSD_VIDWIN1XL 0x06B0
251#define IO_OSD_VIDWIN1YL 0x06B2
252
253#define IO_OSD_OSDWIN0XP 0x06B4
254#define IO_OSD_OSDWIN0YP 0x06B6
255#define IO_OSD_OSDWIN0XL 0x06B8
256#define IO_OSD_OSDWIN0YL 0x06BA
257#define IO_OSD_OSDWIN1XP 0x06BC
258#define IO_OSD_OSDWIN1YP 0x06BE
259#define IO_OSD_OSDWIN1XL 0x06C0
260#define IO_OSD_OSDWIN1YL 0x06C2
261#define IO_OSD_CURXP 0x06C4
262#define IO_OSD_CURYP 0x06C6
263#define IO_OSD_CURXL 0x06C8
264#define IO_OSD_CURYL 0x06CA
265
266#define IO_OSD_W0BMP01 0x06D0
267#define IO_OSD_W0BMP23 0x06D2
268#define IO_OSD_W0BMP45 0x06D4
269#define IO_OSD_W0BMP67 0x06D6
270#define IO_OSD_W0BMP89 0x06D8
271#define IO_OSD_W0BMPAB 0x06DA
272#define IO_OSD_W0BMPCD 0x06DC
273#define IO_OSD_W0BMPEF 0x06DE
274
275#define IO_OSD_W1BMP01 0x06E0
276#define IO_OSD_W1BMP23 0x06E2
277#define IO_OSD_W1BMP45 0x06E4
278#define IO_OSD_W1BMP67 0x06E6
279#define IO_OSD_W1BMP89 0x06E8
280#define IO_OSD_W1BMPAB 0x06EA
281#define IO_OSD_W1BMPCD 0x06EC
282#define IO_OSD_W1BMPEF 0x06EE
283
284#define IO_OSD_MISCCTL 0x06F4
285#define IO_OSD_CLUTRAMYCB 0x06F6
286#define IO_OSD_CLUTRAMCR 0x06F8
287
288#define IO_OSD_PPWIN0ADH 0x06FC
289#define IO_OSD_PPWIN0ADL 0x06FE
290
291
292/* CCD Controller */
293#define IO_CCD_SYNCEN 0x0700
294#define IO_CCD_MODESET 0x0702
295#define IO_CCD_HDWIDTH 0x0704
296#define IO_CCD_VDWIDTH 0x0706
297#define IO_CCD_PPLN 0x0708
298#define IO_CCD_LPFR 0x070A
299#define IO_CCD_SPH 0x070C
300#define IO_CCD_NPH 0x070E
301#define IO_CCD_SLV0 0x0710
302#define IO_CCD_SLV1 0x0712
303#define IO_CCD_NLV 0x0714
304#define IO_CCD_CULH 0x0716
305#define IO_CCD_CULV 0x0718
306#define IO_CCD_HSIZE 0x071A
307#define IO_CCD_SDOFST 0x071C
308#define IO_CCD_STADRH 0x071E
309#define IO_CCD_STADRL 0x0720
310#define IO_CCD_CLAMP 0x0722
311#define IO_CCD_DCSUB 0x0724
312#define IO_CCD_COLPTN 0x0726
313#define IO_CCD_BLKCMP0 0x0728
314#define IO_CCD_BLKCMP1 0x072A
315#define IO_CCD_MEDFILT 0x072C
316#define IO_CCD_RYEGAN 0x072E /* this is kept on the odd chance that some code is using the misspelled reg */
317#define IO_CCD_RYEGAIN 0x072E
318#define IO_CCD_GRCYGAIN 0x0730
319#define IO_CCD_GBGGAIN 0x0732
320#define IO_CCD_BMGGAIN 0x0734
321#define IO_CCD_OFFSET 0x0736
322#define IO_CCD_OUTCLP 0x0738
323#define IO_CCD_VDINT0 0x073A
324#define IO_CCD_VDINT1 0x073C
325#define IO_CCD_RSV0 0x073E
326#define IO_CCD_GAMMAWD 0x0740
327#define IO_CCD_REC656IF 0x0742
328#define IO_CCD_CCDFG 0x0744
329#define IO_CCD_FMTCFG 0x0746
330#define IO_CCD_FMTSPH 0x0748
331#define IO_CCD_FMTLNH 0x074A
332#define IO_CCD_FMTSLV 0x074C
333#define IO_CCD_FMTSNV 0x074E
334#define IO_CCD_FMTOFST 0x0750
335#define IO_CCD_FMTRLEN 0x0752
336#define IO_CCD_FMTHCNT 0x0754
337#define IO_CCD_FMTPTNA 0x0756
338#define IO_CCD_FMTPTNB 0x0758
339
340/* NTSC/PAL Encoder */
341#define IO_VID_ENC_VMOD 0x0800
342#define IO_VID_ENC_VDCTL 0x0802
343#define IO_VID_ENC_VDPRO 0x0804
344#define IO_VID_ENC_SYNCCTL 0x0806
345#define IO_VID_ENC_HSPLS 0x0808
346#define IO_VID_ENC_VSPLS 0x080A
347#define IO_VID_ENC_HINT 0x080C
348#define IO_VID_ENC_HSTART 0x080E
349#define IO_VID_ENC_HVALID 0x0810
350#define IO_VID_ENC_VINT 0x0812
351#define IO_VID_ENC_VSTART 0x0814
352#define IO_VID_ENC_VVALID 0x0816
353#define IO_VID_ENC_HSDLY 0x0818
354#define IO_VID_ENC_VSDLY 0x081A
355#define IO_VID_ENC_YCCTL 0x081C
356#define IO_VID_ENC_RGBCTL 0x081E
357#define IO_VID_ENC_RGBCLP 0x0820
358#define IO_VID_ENC_LNECTL 0x0822
359#define IO_VID_ENC_CULLLNE 0x0824
360#define IO_VID_ENC_LCDOUT 0x0826
361#define IO_VID_ENC_BRTS 0x0828
362#define IO_VID_ENC_BRTW 0x082A
363#define IO_VID_ENC_ACCTL 0x082C
364#define IO_VID_ENC_PWMP 0x082E
365#define IO_VID_ENC_PWMW 0x0830
366#define IO_VID_ENC_DCLKCTL 0x0832
367#define IO_VID_ENC_DCLKPTN0 0x0834
368#define IO_VID_ENC_DCLKPTN1 0x0836
369#define IO_VID_ENC_DCLKPTN2 0x0838
370#define IO_VID_ENC_DCLKPTN3 0x083A
371#define IO_VID_ENC_DCLKPTN0A 0x083C
372#define IO_VID_ENC_DCLKPTN1A 0x083E
373#define IO_VID_ENC_DCLKPTN2A 0x0840
374#define IO_VID_ENC_DCLKPTN3A 0x0842
375#define IO_VID_ENC_DCLKHS 0x0844
376#define IO_VID_ENC_DCLKHSA 0x0846
377#define IO_VID_ENC_DCLKHR 0x0848
378#define IO_VID_ENC_DCLKVS 0x084A
379#define IO_VID_ENC_DCLKVR 0x084C
380#define IO_VID_ENC_CAPCTL 0x084E
381#define IO_VID_ENC_CAPDO 0x0850
382#define IO_VID_ENC_CAPDE 0x0852
383#define IO_VID_ENC_ATR0 0x0854
384
385/* Clock Controller */
386#define IO_CLK_PLLA 0x0880
387#define IO_CLK_PLLB 0x0882
388#define IO_CLK_SEL0 0x0884
389#define IO_CLK_SEL1 0x0886
390#define IO_CLK_SEL2 0x0888
391#define IO_CLK_DIV0 0x088A
392#define IO_CLK_DIV1 0x088C
393#define IO_CLK_DIV2 0x088E
394#define IO_CLK_DIV3 0x0890
395#define IO_CLK_DIV4 0x0892
396#define IO_CLK_BYP 0x0894
397#define IO_CLK_INV 0x0896
398#define IO_CLK_MOD0 0x0898
399#define IO_CLK_MOD1 0x089A
400#define IO_CLK_MOD2 0x089C
401#define IO_CLK_LPCTL0 0x089E
402#define IO_CLK_LPCTL1 0x08A0
403#define IO_CLK_OSEL 0x08A2
404#define IO_CLK_00DIV 0x08A4
405#define IO_CLK_O1DIV 0x08A6
406#define IO_CLK_02DIV 0x08A8
407#define IO_CLK_PWM0C 0x08AA
408#define IO_CLK_PWM0H 0x08AC
409#define IO_CLK_PWM1C 0x08AE
410#define IO_CLK_PWM1H 0x08B0
411
412/* Bus Controller */
413#define IO_BUSC_ECR 0x0900
414#define IO_BUSC_EBYTER 0x0902
415#define IO_BUSC_EBITR 0x0904
416#define IO_BUSC_REVR 0x0906
417
418/* SDRAM Controller */
419#define IO_SDRAM_SDBUFD0L 0x0980
420#define IO_SDRAM_SDBUFD0H 0x0982
421#define IO_SDRAM_SDBUFD1L 0x0984
422#define IO_SDRAM_SDBUFD1H 0x0986
423#define IO_SDRAM_SDBUFD2L 0x0988
424#define IO_SDRAM_SDBUFD2H 0x098A
425#define IO_SDRAM_SDBUFD3L 0x098C
426#define IO_SDRAM_SDBUFD3H 0x098E
427#define IO_SDRAM_SDBUFD4L 0x0990
428#define IO_SDRAM_SDBUFD4H 0x0992
429#define IO_SDRAM_SDBUFD5L 0x0994
430#define IO_SDRAM_SDBUFD5H 0x0996
431#define IO_SDRAM_SDBUFD6L 0x0998
432#define IO_SDRAM_SDBUFD6H 0x099A
433#define IO_SDRAM_SDBUFD7L 0x099C
434#define IO_SDRAM_SDBUFD7H 0x099E
435#define IO_SDRAM_SDBUFAD1 0x09A0
436#define IO_SDRAM_SDBUFAD2 0x09A2
437#define IO_SDRAM_SDBUFCTL 0x09A4
438#define IO_SDRAM_SDMODE 0x09A6
439#define IO_SDRAM_REFCTL 0x09A8
440#define IO_SDRAM_SDPRTY1 0x09AA
441#define IO_SDRAM_SDPRTY2 0x09AC
442#define IO_SDRAM_SDPRTY3 0x09AE
443#define IO_SDRAM_SDPRTY4 0x09B0
444#define IO_SDRAM_SDPRTY5 0x09B2
445#define IO_SDRAM_SDPRTY6 0x09B4
446#define IO_SDRAM_SDPRTY7 0x09B6
447#define IO_SDRAM_SDPRTY8 0x09B8
448#define IO_SDRAM_SDPRTY9 0x09BA
449#define IO_SDRAM_SDPRTY10 0x09BC
450#define IO_SDRAM_SDPRTY11 0x09BE
451#define IO_SDRAM_SDPRTY12 0x09C0
452#define IO_SDRAM_RSV 0x09C2
453#define IO_SDRAM_SDPRTYON 0x09C4
454#define IO_SDRAM_SDDMASEL 0x09C6
455
456/* EMIF Controller */
457#define IO_EMIF_CS0CTRL1 0x0A00
458#define IO_EMIF_CS0CTRL2 0x0A02
459#define IO_EMIF_CS0CTRL3 0x0A04
460#define IO_EMIF_CS1CTRL1A 0x0A06
461#define IO_EMIF_CS1CTRL1B 0x0A08
462#define IO_EMIF_CS1CTRL2 0x0A0A
463#define IO_EMIF_CS2CTRL1 0x0A0C
464#define IO_EMIF_CS2CTRL2 0x0A0E
465#define IO_EMIF_CS3CTRL1 0x0A10
466#define IO_EMIF_CS3CTRL2 0x0A12
467#define IO_EMIF_CS4CTRL1 0x0A14
468#define IO_EMIF_CS4CTRL2 0x0A16
469#define IO_EMIF_BUSCTRL 0x0A18
470#define IO_EMIF_BUSRLS 0x0A1A
471#define IO_EMIF_CFCTRL1 0x0A1C
472#define IO_EMIF_CFCTRL2 0x0A1E
473#define IO_EMIF_SMCTRL 0x0A20
474#define IO_EMIF_BUSINTEN 0x0A22
475#define IO_EMIF_BUSSTS 0x0A24
476#define IO_EMIF_BUSWAITMD 0x0A26
477#define IO_EMIF_ECC1CP 0x0A28
478#define IO_EMIF_ECC1LP 0x0A2A
479#define IO_EMIF_ECC2CP 0x0A2C
480#define IO_EMIF_ECC2LP 0x0A2E
481#define IO_EMIF_ECC3CP 0x0A30
482#define IO_EMIF_ECC3LP 0x0A32
483#define IO_EMIF_ECC4CP 0x0A34
484#define IO_EMIF_ECC4LP 0x0A36
485#define IO_EMIF_ECC5CP 0x0A38
486#define IO_EMIF_ECC5LP 0x0A3A
487#define IO_EMIF_ECC6CP 0x0A3C
488#define IO_EMIF_ECC6LP 0x0A3E
489#define IO_EMIF_ECC7CP 0x0A40
490#define IO_EMIF_ECC7LP 0x0A42
491#define IO_EMIF_ECC8CP 0x0A44
492#define IO_EMIF_ECC8LP 0x0A46
493#define IO_EMIF_ECCCLR 0x0A48
494#define IO_EMIF_PAGESZ 0x0A4A
495#define IO_EMIF_PRIORCTL 0x0A4C
496#define IO_EMIF_MGDSPDEST 0x0A4E
497#define IO_EMIF_MGDSPADDH 0x0A50
498#define IO_EMIF_MGDSPADDL 0x0A52
499#define IO_EMIF_AHBADDH 0x0A54
500#define IO_EMIF_AHBADDL 0x0A56
501#define IO_EMIF_MTCADDH 0x0A58
502#define IO_EMIF_MTCADDL 0x0A5A
503#define IO_EMIF_DMASIZE 0x0A5C
504#define IO_EMIF_DMAMTCSEL 0x0A5E
505#define IO_EMIF_DMACTL 0x0A60
506
507/* Preivew Engine */
508#define IO_PREV_ENG_PVEN 0x0A80
509#define IO_PREV_ENG_PVSET1 0x0A82
510#define IO_PREV_ENG_RADRH 0x0A84
511#define IO_PREV_ENG_RADRL 0x0A86
512#define IO_PREV_ENG_WADRH 0x0A88
513#define IO_PREV_ENG_WADRL 0x0A8A
514#define IO_PREV_ENG_HSTART 0x0A8C
515#define IO_PREV_ENG_HSIZE 0x0A8E
516#define IO_PREV_ENG_VSTART 0x0A90
517#define IO_PREV_ENG_VSIZE 0x0A92
518#define IO_PREV_ENG_PVSET2 0x0A94
519#define IO_PREV_ENG_NFILT 0x0A96
520#define IO_PREV_ENG_DGAIN 0x0A98
521#define IO_PREV_ENG_WBGAIN0 0x0A9A
522#define IO_PREV_ENG_WBGAIN1 0x0A9C
523#define IO_PREV_ENG_SMTH 0x0A9E
524#define IO_PREV_ENG_HRSZ 0x0AA0
525#define IO_PREV_ENG_VRSZ 0x0AA2
526#define IO_PREV_ENG_BLOFST0 0x0AA4
527#define IO_PREV_ENG_BLOFST1 0x0AA6
528#define IO_PREV_ENG_MTXGAIN0 0x0AA8
529#define IO_PREV_ENG_MTXGAIN1 0x0AAA
530#define IO_PREV_ENG_MTXGAIN2 0x0AAC
531#define IO_PREV_ENG_MTXGAIN3 0x0AAE
532#define IO_PREV_ENG_MTXGAIN4 0x0AB0
533#define IO_PREV_ENG_MTXGAIN5 0x0AB2
534#define IO_PREV_ENG_MTXGAIN6 0x0AB4
535#define IO_PREV_ENG_MTXGAIN7 0x0AB6
536#define IO_PREV_ENG_MTXGAIN8 0x0AB8
537#define IO_PREV_ENG_MTXOFST0 0x0ABA
538#define IO_PREV_ENG_MTXOFST1 0x0ABC
539#define IO_PREV_ENG_MTXOFST2 0x0ABE
540#define IO_PREV_ENG_GAMTBYP 0x0AC0
541#define IO_PREV_ENG_CSC0 0x0AC2
542#define IO_PREV_ENG_CSC1 0x0AC4
543#define IO_PREV_ENG_CSC2 0x0AC6
544#define IO_PREV_ENG_CSC3 0x0AC8
545#define IO_PREV_ENG_CSC4 0x0ACA
546#define IO_PREV_ENG_YOFST 0x0ACC
547#define IO_PREV_ENG_COFST 0x0ACE
548#define IO_PREV_ENG_CNTBRT 0x0AD0
549#define IO_PREV_ENG_CSUP0 0x0AD2
550#define IO_PREV_ENG_CSUP1 0x0AD4
551#define IO_PREV_ENG_SETUPY 0x0AD4
552#define IO_PREV_ENG_SETUPC 0x0AD8
553#define IO_PREV_ENG_TABLE_ADDR 0x0ADA
554#define IO_PREV_ENG_TABLE_DATA 0x0ADC
555#define IO_PREV_ENG_HG_CTL 0x0ADE
556#define IO_PREV_ENG_HG_R0_HSTART 0x0AE0
557#define IO_PREV_ENG_HG_R0_HSIZE 0x0AE2
558#define IO_PREV_ENG_HG_R0_VSTART 0x0AE4
559#define IO_PREV_ENG_HR_R0_VSIZE 0x0AE6
560#define IO_PREV_ENG_HG_R1_HSTART 0x0AE8
561#define IO_PREV_ENG_HG_R1_HSIZE 0x0AEA
562#define IO_PREV_ENG_HG_R1_VSTART 0x0AEC
563#define IO_PREV_ENG_HG_R1_VSIZE 0x0AEE
564#define IO_PREV_ENG_HG_R2_HSTART 0x0AF0
565#define IO_PREV_ENG_HG_R2_HSIZE 0x0AF2
566#define IO_PREV_ENG_HG_R2_VSTART 0x0AF4
567#define IO_PREV_ENG_HG_R2_VSIZE 0x0AF6
568#define IO_PREV_ENG_HG_R3_HSTART 0x0AF8
569#define IO_PREV_ENG_HG_R3_HSIZE 0x0AFA
570#define IO_PREV_ENG_HG_R3_VSTART 0x0AFC
571#define IO_PREV_ENG_HG_R3_VSIZE 0x0AFE
572#define IO_PREV_ENG_HG_ADDR 0x0B00
573#define IO_PREV_ENG_HG_DATA 0x0B02
574
575/* H3A Hardware */
576#define IO_H3A_H3ACTRL 0x0B80
577#define IO_H3A_AFCTRL 0x0B82
578#define IO_H3A_AFPAX1 0x0B84
579#define IO_H3A_AFPAX2 0x0B86
580#define IO_H3A_AFPAX3 0x0B88
581#define IO_H3A_AFPAX4 0x0B8A
582#define IO_H3A_AFIRSH 0x0B8C
583#define IO_H3A_AFPAX5 0x0B8E
584#define IO_H3A_AFSDRA1 0x0B90
585#define IO_H3A_AFSDRA2 0x0B92
586#define IO_H3A_AFSDRFLG 0x0B94
587#define IO_H3A_AFCOEFF10 0x0B96
588#define IO_H3A_AFCOEFF11 0x0B98
589#define IO_H3A_AFCOEFF12 0x0B9A
590#define IO_H3A_AFCOEFF13 0x0B9C
591#define IO_H3A_AFCOEFF14 0x0B9E
592#define IO_H3A_AFCOEFF15 0x0BA0
593#define IO_H3A_AFCOEFF16 0x0BA2
594#define IO_H3A_AFCOEFF17 0x0BA4
595#define IO_H3A_AFCOEFF18 0x0BA6
596#define IO_H3A_AFCOEFF19 0x0BA8
597#define IO_H3A_AFCOEFF110 0x0BAA
598#define IO_H3A_AFCOEFF20 0x0BAC
599#define IO_H3A_AFCOEFF21 0x0BAE
600#define IO_H3A_AFCOEFF22 0x0BB0
601#define IO_H3A_AFCOEFF23 0x0BB2
602#define IO_H3A_AFCOEFF24 0x0BB4
603#define IO_H3A_AFCOEFF25 0x0BB6
604#define IO_H3A_AFCOEFF26 0x0BB8
605#define IO_H3A_AFCOEFF27 0x0BBA
606#define IO_H3A_AFCOEFF28 0x0BBC
607#define IO_H3A_AFCOEFF29 0x0BBE
608#define IO_H3A_AFCOEFF210 0x0BC0
609#define IO_H3A_AEWCTRL 0x0BC2
610#define IO_H3A_AEWWIN1 0x0BC4
611#define IO_H3A_AEWWIN2 0x0BC6
612#define IO_H3A_AEWWIN3 0x0BC8
613#define IO_H3A_AEWWIN4 0x0BCA
614#define IO_H3A_AEWWIN5 0x0BCC
615#define IO_H3A_AEWSDRA1 0x0BCE
616#define IO_H3A_AEWSDRA2 0x0BD0
617#define IO_H3A_AEWSDRFLG 0x0BD2
618
619/* Reserved 0x0C00 - 0x0CCFF */
620
621/* Memory Stick Controller : */
622#define IO_MEM_STICK_MODE 0x0C80
623#define IO_MEM_STICK_CMD 0x0C82
624#define IO_MEM_STICK_DATA 0x0C84
625#define IO_MEM_STICK_STATUS 0x0C86
626#define IO_MEM_STICK_SYS 0x0C88
627#define IO_MEM_STICK_ENDIAN 0x0C8A
628#define IO_MEM_STICK_INT_STATUS 0x0C8C
629#define IO_MEM_STICK_DMA_TRG 0x0C8E
630#define IO_MEM_STICK_DMA_MODE 0x0C90
631#define IO_MEM_STICK_SDRAM_ADDL 0x0C92
632#define IO_MEM_STICK_SDRAM_ADDH 0x0C94
633#define IO_MEM_STICK_DMA_STATUS 0x0C96
634
635/* ATM : WBB Need to find these Register values */
636#define IO_ATM_ 0x0D00
637
638/* I2C */
639#define IO_I2C_TXDATA 0x0D80
640#define IO_I2C_RXDATA 0x0D82
641#define IO_I2C_SCS 0x0D84
642
643/* Taken from linux/include/asm-arm/arch-itdm320/irqs.h
644 *
645 * Copyright (C) 1999 ARM Limited
646 * Copyright (C) 2004 Ingenient Technologies
647 */
648
649/*
650 * Interrupt numbers
651 */
652#define IRQ_TIMER0 0
653#define IRQ_TIMER1 1
654#define IRQ_TIMER2 2
655#define IRQ_TIMER3 3
656#define IRQ_CCD_VD0 4
657#define IRQ_CCD_VD1 5
658#define IRQ_CCD_WEN 6
659#define IRQ_VENC 7
660#define IRQ_SERIAL0 8
661#define IRQ_SERIAL1 9
662#define IRQ_EXT_HOST 10
663#define IRQ_DSPHINT 11
664#define IRQ_UART0 12
665#define IRQ_UART1 13
666#define IRQ_USB_DMA 14
667#define IRQ_USB_CORE 15
668#define IRQ_VLYNQ 16
669#define IRQ_MTC0 17
670#define IRQ_MTC1 18
671#define IRQ_SD_MMC 19
672#define IRQ_SDIO_MS 20
673#define IRQ_GIO0 21
674#define IRQ_GIO1 22
675#define IRQ_GIO2 23
676#define IRQ_GIO3 24
677#define IRQ_GIO4 25
678#define IRQ_GIO5 26
679#define IRQ_GIO6 27
680#define IRQ_GIO7 28
681#define IRQ_GIO8 29
682#define IRQ_GIO9 30
683#define IRQ_GIO10 31
684#define IRQ_GIO11 32
685#define IRQ_GIO12 33
686#define IRQ_GIO13 34
687#define IRQ_GIO14 35
688#define IRQ_GIO15 36
689#define IRQ_PREVIEW0 37
690#define IRQ_PREVIEW1 38
691#define IRQ_WATCHDOG 39
692#define IRQ_I2C 40
693#define IRQ_CLKC 41
694
695/* Embedded Debugging Interrupts */
696#define IRQ_ICE 42
697#define IRQ_ARMCOM_RX 43
698#define IRQ_ARMCOM_TX 44
699
700#define IRQ_RESERVED 45
701
702#define NR_IRQS 46
703
704#endif
diff --git a/firmware/export/timer.h b/firmware/export/timer.h
index 920419d1f9..f4df8d51d4 100644
--- a/firmware/export/timer.h
+++ b/firmware/export/timer.h
@@ -31,7 +31,7 @@
31 #define TIMER_FREQ (CPU_FREQ/2) 31 #define TIMER_FREQ (CPU_FREQ/2)
32#elif CONFIG_CPU == PNX0101 32#elif CONFIG_CPU == PNX0101
33 #define TIMER_FREQ 3000000 33 #define TIMER_FREQ 3000000
34#elif CONFIG_CPU == S3C2440 34#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320
35 #include "timer-target.h" 35 #include "timer-target.h"
36#elif defined(SIMULATOR) 36#elif defined(SIMULATOR)
37 #define TIMER_FREQ 1000000 37 #define TIMER_FREQ 1000000
diff --git a/firmware/sound.c b/firmware/sound.c
index dd70b42230..8b68a5569b 100644
--- a/firmware/sound.c
+++ b/firmware/sound.c
@@ -465,7 +465,7 @@ void sound_set_volume(int value)
465 || defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \ 465 || defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \
466 || defined(HAVE_AS3514) 466 || defined(HAVE_AS3514)
467 current_volume = value * 10; /* tenth of dB */ 467 current_volume = value * 10; /* tenth of dB */
468 set_prescaled_volume(); 468 set_prescaled_volume();
469#elif CONFIG_CPU == PNX0101 469#elif CONFIG_CPU == PNX0101
470 int tmp = (60 - value * 4) & 0xff; 470 int tmp = (60 - value * 4) & 0xff;
471 CODECVOL = tmp | (tmp << 8); 471 CODECVOL = tmp | (tmp << 8);
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S
index e7a0a38f36..56876ca9b1 100644
--- a/firmware/target/arm/crt0.S
+++ b/firmware/target/arm/crt0.S
@@ -33,9 +33,8 @@ start:
33 33
34 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ 34 msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
35 35
36#ifndef BOOTLOADER 36#if !defined(BOOTLOADER) || (CONFIG_CPU == DM320)
37 37#if !defined(DEBUG)
38#ifndef DEBUG
39 /* Copy exception handler code to address 0 */ 38 /* Copy exception handler code to address 0 */
40 ldr r2, =_vectorsstart 39 ldr r2, =_vectorsstart
41 ldr r3, =_vectorsend 40 ldr r3, =_vectorsend
@@ -52,8 +51,11 @@ start:
52 ldr r0, =fiq_handler 51 ldr r0, =fiq_handler
53 str r0, [r1, #28] 52 str r0, [r1, #28]
54#endif 53#endif
55 54#endif
56#ifndef STUB 55
56#if !defined(BOOTLOADER)
57
58#if !defined(STUB)
57 /* Zero out IBSS */ 59 /* Zero out IBSS */
58 ldr r2, =_iedata 60 ldr r2, =_iedata
59 ldr r3, =_iend 61 ldr r3, =_iend
@@ -98,6 +100,159 @@ start:
98/* Code for ARM bootloader targets other than iPod go here */ 100/* Code for ARM bootloader targets other than iPod go here */
99 101
100#if CONFIG_CPU == S3C2440 102#if CONFIG_CPU == S3C2440
103 /* Proper initialization pulled from 0x5070 */
104
105 /* BWSCON
106 * Reserved 0
107 * Bank 0:
108 * Bus width 10 (16 bit)
109 * Bank 1:
110 * Buswidth 00 (8 bit)
111 * Disable wait 0
112 * Not using UB/LB 0
113 * Bank 2:
114 * Buswidth 10 (32 bit)
115 * Disable wait 0
116 * Not using UB/LB 0
117 * Bank 3:
118 * Buswidth 10 (32 bit)
119 * Disable wait 0
120 * Use UB/LB 1
121 * Bank 4:
122 * Buswidth 10 (32 bit)
123 * Disable wait 0
124 * Use UB/LB 1
125 * Bank 5:
126 * Buswidth 00 (8 bit)
127 * Disable wait 0
128 * Not using UB/LB 0
129 * Bank 6:
130 * Buswidth 10 (32 bit)
131 * Disable wait 0
132 * Not using UB/LB 0
133 * Bank 7:
134 * Buswidth 00 (8 bit)
135 * Disable wait 0
136 * Not using UB/LB 0
137 */
138 ldr r2,=0x01055102
139 mov r1, #0x48000000
140 str r2, [r1]
141
142 /* BANKCON0
143 * Pagemode: normal (1 data) 00
144 * Pagemode access cycle: 2 clocks 00
145 * Address hold: 2 clocks 10
146 * Chip selection hold time: 1 clock 10
147 * Access cycle: 8 clocks 101
148 * Chip select setup time: 1 clock 01
149 * Address setup time: 0 clock 00
150 */
151 ldr r2,=0x00000D60
152 str r2, [r1, #4]
153
154
155 /* BANKCON1
156 * Pagemode: normal (1 data) 00
157 * Pagemode access cycle: 2 clocks 00
158 * Address hold: 0 clocks 00
159 * Chip selection hold time: 0 clock 00
160 * Access cycle: 1 clocks 000
161 * Chip select setup time: 0 clocks 00
162 * Address setup time: 0 clocks 00
163 */
164 ldr r2,=0x00000000
165 str r2, [r1, #8]
166
167 /* BANKCON2
168 * Pagemode: normal (1 data) 00
169 * Pagemode access cycle: 2 clocks 00
170 * Address hold: 2 clocks 10
171 * Chip selection hold time: 2 clocks 10
172 * Access cycle: 14 clocks 111
173 * Chip select setup time: 4 clocks 11
174 * Address setup time: 0 clocks 00
175 */
176 ldr r2,=0x00001FA0
177 str r2, [r1, #0xC]
178
179 /* BANKCON3 */
180 ldr r2,=0x00001D80
181 str r2, [r1, #0x10]
182 /* BANKCON4 */
183 str r2, [r1, #0x14]
184
185 /* BANKCON5 */
186 ldr r2,=0x00000000
187 str r2, [r1, #0x18]
188
189 /* BANKCON6/7
190 * SCAN: 9 bit 01
191 * Trcd: 3 clocks 01
192 * Tcah: 0 clock 00
193 * Tcoh: 0 clock 00
194 * Tacc: 1 clock 000
195 * Tcos: 0 clock 00
196 * Tacs: 0 clock 00
197 * MT: Sync DRAM 11
198 */
199 ldr r2,=0x00018005
200 str r2, [r1, #0x1C]
201 /* BANKCON7 */
202 str r2, [r1, #0x20]
203
204 /* REFRESH */
205 ldr r2,=0x00980501
206 str r2, [r1, #0x24]
207
208 /* BANKSIZE
209 * BK76MAP: 32M/32M 000
210 * Reserved: 0 0 (was 1)
211 * SCLK_EN: always 1 (was 0)
212 * SCKE_EN: disable 0
213 * Reserved: 0 0
214 * BURST_EN: enabled 1
215 */
216 ldr r2,=0x00000090
217 str r2, [r1, #0x28]
218
219 /* MRSRB6 */
220 ldr r2,=0x00000030
221 str r2, [r1, #0x2C]
222 /* MRSRB7 */
223 str r2, [r1, #0x30]
224
225#if 0
226 /* This next part I am not sure of the purpose */
227
228 /* GPACON */
229 mov r2,#0x01FFFCFF
230 str r2,=0x56000000
231
232 /* GPADAT */
233 mov r2,#0x01FFFEFF
234 str r2,=0x56000004
235
236 /* MRSRB6 */
237 mov r2,#0x00000000
238 str r2,=0x4800002C
239
240 /* GPADAT */
241 ldr r2,=0x01FFFFFF
242 mov r1, #0x56000000
243 str r2, [r1, #4]
244
245 /* MRSRB6 */
246 mov r2,#0x00000030
247 str r2,=0x4800002C
248
249 /* GPACON */
250 mov r2,#0x01FFFFFF
251 str r2,=0x56000000
252
253 /* End of the unknown */
254#endif
255
101 /* get the high part of our execute address */ 256 /* get the high part of our execute address */
102 ldr r2, =0xffffff00 257 ldr r2, =0xffffff00
103 and r4, pc, r2 258 and r4, pc, r2
@@ -118,6 +273,28 @@ start:
118 273
119start_loc: 274start_loc:
120 bl main 275 bl main
276
277#else
278 /* get the high part of our execute address */
279 ldr r2, =0xffffff00
280 and r4, pc, r2
281
282 /* Copy bootloader to safe area - 0x01900000 */
283 mov r5, #0x00900000
284 add r5, r5, #0x01000000
285 ldr r6, = _dataend
286 sub r0, r6, r5 /* length of loader */
287 add r0, r4, r0 /* r0 points to start of loader */
2881:
289 cmp r5, r6
290 ldrcc r2, [r4], #4
291 strcc r2, [r5], #4
292 bcc 1b
293
294 ldr pc, =start_loc /* jump to the relocated start_loc: */
295
296start_loc:
297 bl main
121#endif 298#endif
122 299
123#else /* BOOTLOADER */ 300#else /* BOOTLOADER */
diff --git a/firmware/target/arm/memswap128-arm.S b/firmware/target/arm/memswap128-arm.S
index f5276ef353..f672def1ec 100644
--- a/firmware/target/arm/memswap128-arm.S
+++ b/firmware/target/arm/memswap128-arm.S
@@ -1,44 +1,44 @@
1/*************************************************************************** 1/***************************************************************************
2 * __________ __ ___. 2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___ 3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / 4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < 5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ 6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/ 7 * \/ \/ \/ \/ \/
8 * $Id$ 8 * $Id$
9 * 9 *
10 * Copyright (C) 2007 by Michael Sevakis 10 * Copyright (C) 2007 by Michael Sevakis
11 * 11 *
12 * All files in this archive are subject to the GNU General Public License. 12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement. 13 * See the file COPYING in the source tree root for full license agreement.
14 * 14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY 15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied. 16 * KIND, either express or implied.
17 * 17 *
18 ****************************************************************************/ 18 ****************************************************************************/
19 19
20/**************************************************************************** 20/****************************************************************************
21 * void memswap128(void *buf1, void *buf2, size_t len) 21 * void memswap128(void *buf1, void *buf2, size_t len)
22 */ 22 */
23 .section .icode, "ax", %progbits 23 .section .icode, "ax", %progbits
24 .align 2 24 .align 2
25 .global memswap128 25 .global memswap128
26 .type memswap128, %function 26 .type memswap128, %function
27memswap128: 27memswap128:
28 @ r0 = buf1 28 @ r0 = buf1
29 @ r1 = buf2 29 @ r1 = buf2
30 @ r2 = len 30 @ r2 = len
31 movs r2, r2, lsr #4 @ bytes => lines, len == 0? 31 movs r2, r2, lsr #4 @ bytes => lines, len == 0?
32 moveq pc, lr @ not at least a line? leave 32 moveq pc, lr @ not at least a line? leave
33 stmdb sp!, { r4-r10, lr } @ save registers and return address 33 stmdb sp!, { r4-r10, lr } @ save registers and return address
34.loop: @ 34.loop: @
35 ldmia r0, { r3-r6 } @ read four longwords from buf1 35 ldmia r0, { r3-r6 } @ read four longwords from buf1
36 ldmia r1, { r7-r10 } @ read four longwords from buf2 36 ldmia r1, { r7-r10 } @ read four longwords from buf2
37 stmia r0!, { r7-r10 } @ write buf2 data to buf1, buf1 += 16 37 stmia r0!, { r7-r10 } @ write buf2 data to buf1, buf1 += 16
38 stmia r1!, { r3-r6 } @ write buf1 data to buf2, buf2 += 16 38 stmia r1!, { r3-r6 } @ write buf1 data to buf2, buf2 += 16
39 subs r2, r2, #1 @ len -= 1, len > 0 ? 39 subs r2, r2, #1 @ len -= 1, len > 0 ?
40 bhi .loop @ yes? keep exchanging 40 bhi .loop @ yes? keep exchanging
41 ldmia sp!, { r4-r10, pc } @ restore registers and return 41 ldmia sp!, { r4-r10, pc } @ restore registers and return
42.end: 42.end:
43 .size memswap128, .end-memswap128 43 .size memswap128, .end-memswap128
44 44
diff --git a/firmware/target/arm/olympus/mrobe-500/adc-mr500.c b/firmware/target/arm/olympus/mrobe-500/adc-mr500.c
new file mode 100644
index 0000000000..4fb2aa3677
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/adc-mr500.c
@@ -0,0 +1,46 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "cpu.h"
21#include "adc-target.h"
22#include "kernel.h"
23
24/* prototypes */
25static void adc_tick(void);
26
27void adc_init(void)
28{
29 /* attach the adc reading to the tick */
30 tick_add_task(adc_tick);
31}
32
33/* Called to get the recent ADC reading */
34inline unsigned short adc_read(int channel)
35{
36 return (short)channel;
37}
38
39/* add this to the tick so that the ADC converts are done in the background */
40static void adc_tick(void)
41{
42}
43
44
45
46
diff --git a/firmware/target/arm/olympus/mrobe-500/adc-target.h b/firmware/target/arm/olympus/mrobe-500/adc-target.h
new file mode 100644
index 0000000000..fbf38ee13d
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/adc-target.h
@@ -0,0 +1,38 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef _ADC_TARGET_H_
21#define _ADC_TARGET_H_
22
23/* only two channels used by the Gigabeat */
24#define NUM_ADC_CHANNELS 2
25
26#define ADC_BATTERY 0
27#define ADC_HPREMOTE 1
28#define ADC_UNKNOWN_3 2
29#define ADC_UNKNOWN_4 3
30#define ADC_UNKNOWN_5 4
31#define ADC_UNKNOWN_6 5
32#define ADC_UNKNOWN_7 6
33#define ADC_UNKNOWN_8 7
34
35#define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */
36#define ADC_READ_ERROR 0xFFFF
37
38#endif
diff --git a/firmware/target/arm/olympus/mrobe-500/ata-mr500.c b/firmware/target/arm/olympus/mrobe-500/ata-mr500.c
new file mode 100644
index 0000000000..b4028d5ead
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/ata-mr500.c
@@ -0,0 +1,130 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22#include "kernel.h"
23#include "thread.h"
24#include "system.h"
25#include "power.h"
26#include "panic.h"
27#include "pcf50606.h"
28#include "ata-target.h"
29#include "backlight-target.h"
30
31/* ARESET on C7C68300 and RESET on ATA interface (Active Low) */
32#define ATA_RESET_ENABLE return
33#define ATA_RESET_DISABLE return
34
35/* ATA_EN on C7C68300 */
36#define USB_ATA_ENABLE return
37#define USB_ATA_DISABLE return
38
39void ata_reset(void)
40{
41 ATA_RESET_ENABLE;
42 sleep(1); /* > 25us */
43 ATA_RESET_DISABLE;
44 sleep(1); /* > 2ms */
45}
46
47/* This function is called before enabling the USB bus */
48void ata_enable(bool on)
49{
50 if(on)
51 USB_ATA_DISABLE;
52 else
53 USB_ATA_ENABLE;
54}
55
56bool ata_is_coldstart(void)
57{
58 return false;
59}
60
61void ata_device_init(void)
62{
63 /* ATA reset */
64 ATA_RESET_DISABLE; /* Set the pin to disable an active low reset */
65}
66
67#if !defined(BOOTLOADER)
68void copy_read_sectors(unsigned char* buf, int wordcount)
69{
70 __buttonlight_trigger();
71
72 /* Unaligned transfer - slow copy */
73 if ( (unsigned long)buf & 1)
74 { /* not 16-bit aligned, copy byte by byte */
75 unsigned short tmp = 0;
76 unsigned char* bufend = buf + wordcount*2;
77 do
78 {
79 tmp = ATA_DATA;
80 *buf++ = tmp & 0xff; /* I assume big endian */
81 *buf++ = tmp >> 8; /* and don't use the SWAB16 macro */
82 } while (buf < bufend); /* tail loop is faster */
83 return;
84 }
85 /* This should never happen, but worth watching for */
86 if(wordcount > (1 << 18))
87 panicf("atd-meg-fx.c: copy_read_sectors: too many sectors per read!");
88
89//#define GIGABEAT_DEBUG_ATA
90#ifdef GIGABEAT_DEBUG_ATA
91 static int line = 0;
92 static char str[256];
93 snprintf(str, sizeof(str), "ODD DMA to %08x, %d", buf, wordcount);
94 lcd_puts(10, line, str);
95 line = (line+1) % 32;
96 lcd_update();
97#endif
98 /* Reset the channel */
99 DMASKTRIG0 |= 4;
100 /* Wait for DMA controller to be ready */
101 while(DMASKTRIG0 & 0x2)
102 ;
103 while(DSTAT0 & (1 << 20))
104 ;
105 /* Source is ATA_DATA, on AHB Bus, Fixed */
106 DISRC0 = (int) 0x18000000;
107 DISRCC0 = 0x1;
108 /* Dest mapped to physical address, on AHB bus, increment */
109 DIDST0 = (int) buf;
110 if(DIDST0 < 0x30000000)
111 DIDST0 += 0x30000000;
112 DIDSTC0 = 0;
113
114 /* DACK/DREQ Sync to AHB, Whole service, No reload, 16-bit transfers */
115 DCON0 = ((1 << 30) | (1<<27) | (1<<22) | (1<<20)) | wordcount;
116
117 /* Activate the channel */
118 DMASKTRIG0 = 0x2;
119
120 invalidate_dcache_range((void *)buf, wordcount*2);
121
122 /* Start DMA */
123 DMASKTRIG0 |= 0x1;
124
125 /* Wait for transfer to complete */
126 while((DSTAT0 & 0x000fffff))
127 priority_yield();
128 /* Dump cache for the buffer */
129}
130#endif
diff --git a/firmware/target/arm/olympus/mrobe-500/ata-target.h b/firmware/target/arm/olympus/mrobe-500/ata-target.h
new file mode 100644
index 0000000000..87d8a9b535
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/ata-target.h
@@ -0,0 +1,71 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef ATA_TARGET_H
21#define ATA_TARGET_H
22
23/* Plain C read & write loops */
24#define PREFER_C_READING
25#define PREFER_C_WRITING
26#if !defined(BOOTLOADER)
27//#define ATA_OPTIMIZED_READING
28//void copy_read_sectors(unsigned char* buf, int wordcount);
29#endif
30
31#define ATA_IOBASE 0x50000000
32#define ATA_DATA (*((volatile unsigned short*)(ATA_IOBASE+0xa0)))
33#define ATA_ERROR (*((volatile unsigned char*)(ATA_IOBASE + 0xa2)))
34#define ATA_NSECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0x24)))
35#define ATA_SECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0x26)))
36#define ATA_LCYL (*((volatile unsigned char*)(ATA_IOBASE + 0x28)))
37#define ATA_HCYL (*((volatile unsigned char*)(ATA_IOBASE + 0x2A)))
38#define ATA_SELECT (*((volatile unsigned char*)(ATA_IOBASE + 0x2C)))
39#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0x2E)))
40#define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE + 0x9C)))
41
42#define STATUS_BSY 0x80
43#define STATUS_RDY 0x40
44#define STATUS_DF 0x20
45#define STATUS_DRQ 0x08
46#define STATUS_ERR 0x01
47#define ERROR_ABRT 0x04
48
49#define WRITE_PATTERN1 0xa5
50#define WRITE_PATTERN2 0x5a
51#define WRITE_PATTERN3 0xaa
52#define WRITE_PATTERN4 0x55
53
54#define READ_PATTERN1 0xa5
55#define READ_PATTERN2 0x5a
56#define READ_PATTERN3 0xaa
57#define READ_PATTERN4 0x55
58
59#define READ_PATTERN1_MASK 0xff
60#define READ_PATTERN2_MASK 0xff
61#define READ_PATTERN3_MASK 0xff
62#define READ_PATTERN4_MASK 0xff
63
64#define SET_REG(reg,val) reg = (val)
65#define SET_16BITREG(reg,val) reg = (val)
66
67void ata_reset(void);
68void ata_device_init(void);
69bool ata_is_coldstart(void);
70
71#endif
diff --git a/firmware/target/arm/olympus/mrobe-500/backlight-mr500.c b/firmware/target/arm/olympus/mrobe-500/backlight-mr500.c
new file mode 100644
index 0000000000..6a335d357c
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/backlight-mr500.c
@@ -0,0 +1,50 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22#include "system.h"
23#include "backlight-target.h"
24#include "backlight.h"
25#include "lcd.h"
26#include "power.h"
27
28void __backlight_on(void)
29{
30}
31
32void __backlight_off(void)
33{
34}
35
36/* Assumes that the backlight has been initialized */
37void __backlight_set_brightness(int brightness)
38{
39 (void) brightness;
40}
41
42void __backlight_dim(bool dim_now)
43{
44 (void) dim_now;
45}
46
47bool __backlight_init(void)
48{
49 return true;
50}
diff --git a/firmware/target/arm/olympus/mrobe-500/backlight-target.h b/firmware/target/arm/olympus/mrobe-500/backlight-target.h
new file mode 100644
index 0000000000..d28cfbbdf1
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/backlight-target.h
@@ -0,0 +1,31 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef BACKLIGHT_TARGET_H
21#define BACKLIGHT_TARGET_H
22
23bool __backlight_init(void);
24void __backlight_on(void);
25void __backlight_off(void);
26void __backlight_set_brightness(int brightness);
27
28/* true: backlight fades off - false: backlight fades on */
29void __backlight_dim(bool dim);
30
31#endif
diff --git a/firmware/target/arm/olympus/mrobe-500/button-mr500.c b/firmware/target/arm/olympus/mrobe-500/button-mr500.c
new file mode 100644
index 0000000000..9cafab5c14
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/button-mr500.c
@@ -0,0 +1,56 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22#include "system.h"
23#include "button.h"
24#include "kernel.h"
25#include "backlight.h"
26#include "adc.h"
27#include "system.h"
28#include "backlight-target.h"
29
30static int const remote_buttons[] =
31{
32 BUTTON_NONE, /* Headphones connected - remote disconnected */
33 BUTTON_RC_PLAY,
34 BUTTON_RC_DSP,
35 BUTTON_RC_REW,
36 BUTTON_RC_FF,
37 BUTTON_RC_VOL_UP,
38 BUTTON_RC_VOL_DOWN,
39 BUTTON_NONE, /* Remote control attached - no buttons pressed */
40 BUTTON_NONE, /* Nothing in the headphone socket */
41};
42
43void button_init_device(void)
44{
45 /* Power, Remote Play & Hold switch */
46}
47
48inline bool button_hold(void)
49{
50 return false;
51}
52
53int button_read_device(void)
54{
55 return 0;
56}
diff --git a/firmware/target/arm/olympus/mrobe-500/button-target.h b/firmware/target/arm/olympus/mrobe-500/button-target.h
new file mode 100644
index 0000000000..6637c5bf2b
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/button-target.h
@@ -0,0 +1,99 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#ifndef _BUTTON_TARGET_H_
21#define _BUTTON_TARGET_H_
22
23#include <stdbool.h>
24#include "config.h"
25
26#define HAS_BUTTON_HOLD
27
28bool button_hold(void);
29void button_init_device(void);
30int button_read_device(void);
31
32/* Toshiba Gigabeat specific button codes */
33
34#define BUTTON_POWER 0x00000001
35#define BUTTON_MENU 0x00000002
36
37#define BUTTON_LEFT 0x00000004
38#define BUTTON_RIGHT 0x00000008
39#define BUTTON_UP 0x00000010
40#define BUTTON_DOWN 0x00000020
41
42#define BUTTON_VOL_UP 0x00000040
43#define BUTTON_VOL_DOWN 0x00000080
44
45#define BUTTON_SELECT 0x00000100
46#define BUTTON_A 0x00000200
47
48/* Remote control buttons */
49
50#define BUTTON_RC_VOL_UP 0x00000400
51#define BUTTON_RC_VOL_DOWN 0x00000800
52#define BUTTON_RC_FF 0x00001000
53#define BUTTON_RC_REW 0x00002000
54
55#define BUTTON_RC_PLAY 0x00004000
56#define BUTTON_RC_DSP 0x00008000
57
58/* Toshiba Gigabeat specific remote button ADC values */
59/* The remote control uses ADC 1 to emulate button pushes
60 Reading (approx) Button HP plugged in? Remote plugged in?
61 0 N/A Yes No
62 125 Play/Pause Cant tell Yes
63 241 Speaker+ Cant tell Yes
64 369 Rewind Cant tell Yes
65 492 Fast Fwd Cant tell Yes
66 616 Vol + Cant tell Yes
67 742 Vol - Cant tell Yes
68 864 None Cant tell Yes
69 1023 N/A No No
70*/
71
72/*
73 Notes:
74
75 Buttons on the remote are translated into equivalent button presses just
76 as if you were pressing them on the Gigabeat itself.
77
78 We cannot tell if the hold is asserted on the remote. The Hold function on
79 the remote is to block the output of the buttons changing.
80
81 Only one button can be sensed at a time. If another is pressed, the button
82 with the lowest reading is dominant. So, if Rewind and Vol + are pressed
83 at the same time, Rewind value is the one that is read.
84*/
85
86
87
88
89#define BUTTON_MAIN (BUTTON_POWER|BUTTON_MENU|BUTTON_LEFT|BUTTON_RIGHT\
90 |BUTTON_UP|BUTTON_DOWN|BUTTON_VOL_UP|BUTTON_VOL_DOWN\
91 |BUTTON_SELECT|BUTTON_A)
92
93#define BUTTON_REMOTE (BUTTON_RC_VOL_UP|BUTTON_RC_VOL_DOWN|BUTTON_RC_FF\
94 |BUTTON_RC_REW|BUTTON_RC_PLAY|BUTTON_RC_DSP)
95
96#define POWEROFF_BUTTON BUTTON_POWER
97#define POWEROFF_COUNT 10
98
99#endif /* _BUTTON_TARGET_H_ */
diff --git a/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c
new file mode 100644
index 0000000000..27bb0475e4
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c
@@ -0,0 +1,48 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "system.h"
22#include "kernel.h"
23#include "timer.h"
24#include "thread.h"
25
26extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
27
28void tick_start(unsigned int interval_in_ms)
29{
30 (void)interval_in_ms;
31}
32
33void TIMER4(void)
34{
35 int i;
36
37 /* Run through the list of tick tasks */
38 for(i = 0; i < MAX_NUM_TICK_TASKS; i++)
39 {
40 if(tick_funcs[i])
41 {
42 tick_funcs[i]();
43 }
44 }
45
46 current_tick++;
47
48}
diff --git a/firmware/target/arm/olympus/mrobe-500/lcd-mr500.c b/firmware/target/arm/olympus/mrobe-500/lcd-mr500.c
new file mode 100644
index 0000000000..5e41b829e1
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/lcd-mr500.c
@@ -0,0 +1,206 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * Some of this is based on the Cowon A2 Firmware release:
13 * http://www.cowonglobal.com/download/gnu/cowon_pmp_a2_src_1.59_GPL.tar.gz
14 *
15 * All files in this archive are subject to the GNU General Public License.
16 * See the file COPYING in the source tree root for full license agreement.
17 *
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
20 *
21 ****************************************************************************/
22
23#include "config.h"
24#include "cpu.h"
25#include "string.h"
26#include "lcd.h"
27#include "kernel.h"
28#include "memory.h"
29#include "system-target.h"
30
31static volatile bool lcd_on = true;
32volatile bool lcd_poweroff = false;
33/*
34** These are imported from lcd-16bit.c
35*/
36extern unsigned fg_pattern;
37extern unsigned bg_pattern;
38
39bool lcd_enabled(void)
40{
41 return lcd_on;
42}
43
44/* LCD init - based on code from ingenient-bsp/bootloader/board/dm320/splash.c
45 * and code by Catalin Patulea from the M:Robe 500i linux port
46 */
47void lcd_init_device(void)
48{
49 unsigned int addr;
50
51 /* Clear the Frame */
52 memset16(FRAME, 0x0000, LCD_WIDTH*LCD_HEIGHT);
53
54 outw(0x00ff, IO_OSD_MODE);
55 outw(0x0002, IO_OSD_VIDWINMD);
56 outw(0x2001, IO_OSD_OSDWINMD0);
57 outw(0x0002, IO_OSD_OSDWINMD1);
58 outw(0x0000, IO_OSD_ATRMD);
59 outw(0x0000, IO_OSD_RECTCUR);
60
61 outw((480*2) / 32, IO_OSD_OSDWIN0OFST);
62 addr = ((int)FRAME-CONFIG_SDRAM_START) / 32;
63 outw(addr >> 16, IO_OSD_OSDWINADH);
64 outw(addr & 0xFFFF, IO_OSD_OSDWIN0ADL);
65
66 outw(80, IO_OSD_BASEPX);
67 outw(2, IO_OSD_BASEPY);
68
69 outw(0, IO_OSD_OSDWIN0XP);
70 outw(0, IO_OSD_OSDWIN0YP);
71 outw(480, IO_OSD_OSDWIN0XL);
72 outw(640, IO_OSD_OSDWIN0YL);
73}
74
75/* Update a fraction of the display. */
76void lcd_update_rect(int x, int y, int width, int height)
77{
78 fb_data *dst, *src;
79
80 if (!lcd_on)
81 return;
82
83 if (x + width > LCD_WIDTH)
84 width = LCD_WIDTH - x; /* Clip right */
85 if (x < 0)
86 width += x, x = 0; /* Clip left */
87 if (width <= 0)
88 return; /* nothing left to do */
89
90 if (y + height > LCD_HEIGHT)
91 height = LCD_HEIGHT - y; /* Clip bottom */
92 if (y < 0)
93 height += y, y = 0; /* Clip top */
94 if (height <= 0)
95 return; /* nothing left to do */
96
97 dst = (fb_data *)FRAME + LCD_WIDTH*y + x;
98 src = &lcd_framebuffer[y][x];
99
100 /* Copy part of the Rockbox framebuffer to the second framebuffer */
101 if (width < LCD_WIDTH)
102 {
103 int y;
104 /* Not full width - do line-by-line */
105 for(y=0;y<height;y++)
106 {
107 memcpy(dst, src, width*sizeof(fb_data));
108 dst+=LCD_WIDTH;
109 src+=LCD_WIDTH;
110 }
111 }
112 else
113 {
114 /* Full width - copy as one line */
115 memcpy(dst, src, LCD_WIDTH*height*sizeof(fb_data));
116 }
117}
118
119void lcd_enable(bool state)
120{
121 (void)state;
122}
123
124/* Update the display.
125 This must be called after all other LCD functions that change the display. */
126void lcd_update(void)
127{
128 if (!lcd_on)
129 return;
130
131 memcpy((fb_data *)FRAME, &lcd_framebuffer[0][0],
132 LCD_WIDTH*LCD_HEIGHT*sizeof(fb_data));
133}
134
135/* Line write helper function for lcd_yuv_blit. Write two lines of yuv420. */
136extern void lcd_write_yuv420_lines(fb_data *dst,
137 unsigned char chroma_buf[LCD_HEIGHT/2*3],
138 unsigned char const * const src[3],
139 int width,
140 int stride);
141/* Performance function to blit a YUV bitmap directly to the LCD */
142/* For the Gigabeat - show it rotated */
143/* So the LCD_WIDTH is now the height */
144void lcd_yuv_blit(unsigned char * const src[3],
145 int src_x, int src_y, int stride,
146 int x, int y, int width, int height)
147{
148 /* Caches for chroma data so it only need be recaculated every other
149 line */
150 unsigned char chroma_buf[LCD_HEIGHT/2*3]; /* 480 bytes */
151 unsigned char const * yuv_src[3];
152 off_t z;
153
154 if (!lcd_on)
155 return;
156
157 /* Sorry, but width and height must be >= 2 or else */
158 width &= ~1;
159 height >>= 1;
160
161 fb_data *dst = (fb_data*)FRAME + x * LCD_WIDTH + (LCD_WIDTH - y) - 1;
162
163 z = stride*src_y;
164 yuv_src[0] = src[0] + z + src_x;
165 yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1);
166 yuv_src[2] = src[2] + (yuv_src[1] - src[1]);
167
168 do
169 {
170 lcd_write_yuv420_lines(dst, chroma_buf, yuv_src, width,
171 stride);
172 yuv_src[0] += stride << 1; /* Skip down two luma lines */
173 yuv_src[1] += stride >> 1; /* Skip down one chroma line */
174 yuv_src[2] += stride >> 1;
175 dst -= 2;
176 }
177 while (--height > 0);
178}
179
180void lcd_set_contrast(int val) {
181 (void) val;
182 // TODO:
183}
184
185void lcd_set_invert_display(bool yesno) {
186 (void) yesno;
187 // TODO:
188}
189
190void lcd_blit(const fb_data* data, int bx, int y, int bwidth,
191 int height, int stride)
192{
193 (void) data;
194 (void) bx;
195 (void) y;
196 (void) bwidth;
197 (void) height;
198 (void) stride;
199 //TODO:
200}
201
202void lcd_set_flip(bool yesno) {
203 (void) yesno;
204 // TODO:
205}
206
diff --git a/firmware/target/arm/olympus/mrobe-500/lcd-target.h b/firmware/target/arm/olympus/mrobe-500/lcd-target.h
new file mode 100644
index 0000000000..bac1bef237
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/lcd-target.h
@@ -0,0 +1,21 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20extern void lcd_enable(bool state);
21
diff --git a/firmware/target/arm/olympus/mrobe-500/power-mr500.c b/firmware/target/arm/olympus/mrobe-500/power-mr500.c
new file mode 100644
index 0000000000..28fe6a297a
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/power-mr500.c
@@ -0,0 +1,93 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22#include <stdbool.h>
23#include "kernel.h"
24#include "system.h"
25#include "power.h"
26#include "pcf50606.h"
27#include "backlight.h"
28#include "backlight-target.h"
29
30#ifndef SIMULATOR
31
32void power_init(void)
33{
34 /* Initialize IDE power pin */
35 ide_power_enable(true);
36 /* Charger detect */
37}
38
39bool charger_inserted(void)
40{
41 return false;
42}
43
44/* Returns true if the unit is charging the batteries. */
45bool charging_state(void) {
46 return false;
47}
48
49void ide_power_enable(bool on)
50{
51 if (on)
52 return;
53 else
54 return;
55}
56
57bool ide_powered(void)
58{
59 return true;
60}
61
62void power_off(void)
63{
64 /* turn off backlight and wait for 1 second */
65 __backlight_off();
66 sleep(HZ);
67 /* set SLEEP bit to on in CLKCON to turn off */
68// CLKCON |=(1<<3);
69}
70
71#else /* SIMULATOR */
72
73bool charger_inserted(void)
74{
75 return false;
76}
77
78void charger_enable(bool on)
79{
80 (void)on;
81}
82
83void power_off(void)
84{
85}
86
87void ide_power_enable(bool on)
88{
89 (void)on;
90}
91
92#endif /* SIMULATOR */
93
diff --git a/firmware/target/arm/olympus/mrobe-500/system-mr500.c b/firmware/target/arm/olympus/mrobe-500/system-mr500.c
new file mode 100644
index 0000000000..c93c9f6260
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/system-mr500.c
@@ -0,0 +1,181 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "kernel.h"
21#include "system.h"
22#include "panic.h"
23
24#define default_interrupt(name) \
25 extern __attribute__((weak,alias("UIRQ"))) void name (void)
26
27default_interrupt(TIMER0);
28default_interrupt(TIMER1);
29default_interrupt(TIMER2);
30default_interrupt(TIMER3);
31default_interrupt(CCD_VD0);
32default_interrupt(CCD_VD1);
33default_interrupt(CCD_WEN);
34default_interrupt(VENC);
35default_interrupt(SERIAL0);
36default_interrupt(SERIAL1);
37default_interrupt(EXT_HOST);
38default_interrupt(DSPHINT);
39default_interrupt(UART0);
40default_interrupt(UART1);
41default_interrupt(USB_DMA);
42default_interrupt(USB_CORE);
43default_interrupt(VLYNQ);
44default_interrupt(MTC0);
45default_interrupt(MTC1);
46default_interrupt(SD_MMC);
47default_interrupt(SDIO_MS);
48default_interrupt(GIO0);
49default_interrupt(GIO1);
50default_interrupt(GIO2);
51default_interrupt(GIO3);
52default_interrupt(GIO4);
53default_interrupt(GIO5);
54default_interrupt(GIO6);
55default_interrupt(GIO7);
56default_interrupt(GIO8);
57default_interrupt(GIO9);
58default_interrupt(GIO10);
59default_interrupt(GIO11);
60default_interrupt(GIO12);
61default_interrupt(GIO13);
62default_interrupt(GIO14);
63default_interrupt(GIO15);
64default_interrupt(PREVIEW0);
65default_interrupt(PREVIEW1);
66default_interrupt(WATCHDOG);
67default_interrupt(I2C);
68default_interrupt(CLKC);
69default_interrupt(ICE);
70default_interrupt(ARMCOM_RX);
71default_interrupt(ARMCOM_TX);
72default_interrupt(RESERVED);
73
74static void (* const irqvector[])(void) =
75{
76 TIMER0,TIMER1,TIMER2,TIMER3,CCD_VD0,CCD_VD1,
77 CCD_WEN,VENC,SERIAL0,SERIAL1,EXT_HOST,DSPHINT,
78 UART0,UART1,USB_DMA,USB_CORE,VLYNQ,MTC0,MTC1,
79 SD_MMC,SDIO_MS,GIO0,GIO1,GIO2,GIO3,GIO4,GIO5,
80 GIO6,GIO7,GIO8,GIO9,GIO10,GIO11,GIO12,GIO13,
81 GIO14,GIO15,PREVIEW0,PREVIEW1,WATCHDOG,I2C,CLKC,
82 ICE,ARMCOM_RX,ARMCOM_TX,RESERVED
83};
84
85static const char * const irqname[] =
86{
87 "TIMER0","TIMER1","TIMER2","TIMER3","CCD_VD0","CCD_VD1",
88 "CCD_WEN","VENC","SERIAL0","SERIAL1","EXT_HOST","DSPHINT",
89 "UART0","UART1","USB_DMA","USB_CORE","VLYNQ","MTC0","MTC1",
90 "SD_MMC","SDIO_MS","GIO0","GIO1","GIO2","GIO3","GIO4","GIO5",
91 "GIO6","GIO7","GIO8","GIO9","GIO10","GIO11","GIO12","GIO13",
92 "GIO14","GIO15","PREVIEW0","PREVIEW1","WATCHDOG","I2C","CLKC",
93 "ICE","ARMCOM_RX","ARMCOM_TX","RESERVED"
94};
95
96static void UIRQ(void)
97{
98 unsigned int offset = inw(IO_INTC_IRQENTRY0);
99 panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
100}
101
102void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
103void irq_handler(void)
104{
105 /*
106 * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
107 */
108
109 asm volatile (
110 "sub lr, lr, #4 \r\n"
111 "stmfd sp!, {r0-r3, ip, lr} \r\n"
112 "mov r0, #0x00030000 \r\n"
113 "ldr r0, [r0, #0x518] \r\n"
114 "ldr r1, =irqvector \r\n"
115 "ldr r1, [r1, r0, lsl #2] \r\n"
116 "mov lr, pc \r\n"
117 "bx r1 \r\n"
118 "ldmfd sp!, {r0-r3, ip, pc}^ \r\n"
119 );
120}
121
122void system_reboot(void)
123{
124
125}
126
127void system_init(void)
128{
129 /* taken from linux/arch/arm/mach-itdm320-20/irq.c */
130
131 /* Clearing all FIQs and IRQs. */
132 outw(0xFFFF, IO_INTC_IRQ0);
133 outw(0xFFFF, IO_INTC_IRQ1);
134 outw(0xFFFF, IO_INTC_IRQ2);
135
136 outw(0xFFFF, IO_INTC_FIQ0);
137 outw(0xFFFF, IO_INTC_FIQ1);
138 outw(0xFFFF, IO_INTC_FIQ2);
139
140 /* Masking all Interrupts. */
141 outw(0, IO_INTC_EINT0);
142 outw(0, IO_INTC_EINT1);
143 outw(0, IO_INTC_EINT2);
144
145 /* Setting INTC to all IRQs. */
146 outw(0, IO_INTC_FISEL0);
147 outw(0, IO_INTC_FISEL1);
148 outw(0, IO_INTC_FISEL2);
149}
150
151int system_memory_guard(int newmode)
152{
153 (void)newmode;
154 return 0;
155}
156
157#ifdef HAVE_ADJUSTABLE_CPU_FREQ
158
159void set_cpu_frequency(long frequency)
160{
161 if (frequency == CPUFREQ_MAX)
162 {
163 asm volatile("mov r0, #0\n"
164 "mrc p15, 0, r0, c1, c0, 0\n"
165 "orr r0, r0, #3<<30\n" /* set to Asynchronous mode*/
166 "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
167
168 FREQ = CPUFREQ_MAX;
169 }
170 else
171 {
172 asm volatile("mov r0, #0\n"
173 "mrc p15, 0, r0, c1, c0, 0\n"
174 "bic r0, r0, #3<<30\n" /* set to FastBus mode*/
175 "mcr p15, 0, r0, c1, c0, 0" : : : "r0");
176
177 FREQ = CPUFREQ_NORMAL;
178 }
179}
180
181#endif
diff --git a/firmware/target/arm/olympus/mrobe-500/timer-mr500.c b/firmware/target/arm/olympus/mrobe-500/timer-mr500.c
new file mode 100644
index 0000000000..cd3cec5663
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/timer-mr500.c
@@ -0,0 +1,108 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id: $
9*
10* Copyright (C) 2007 by Karl Kurbjun
11*
12* All files in this archive are subject to the GNU General Public License.
13* See the file COPYING in the source tree root for full license agreement.
14*
15* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16* KIND, either express or implied.
17*
18****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22#include "system.h"
23#include "timer.h"
24#include "logf.h"
25
26/* GPB0/TOUT0 should already have been configured as output so that pin
27 should not be a functional pin and TIMER0 output unseen there */
28void TIMER0(void)
29{
30 if (pfn_timer != NULL)
31 pfn_timer();
32}
33
34static void stop_timer(void)
35{
36}
37
38bool __timer_set(long cycles, bool start)
39{
40 /* taken from linux/arch/arm/mach-itdm320-20/time.c and timer-meg-fx.c */
41
42 /* Turn off all timers */
43/* outw(CONFIG_TIMER0_TMMD_STOP, IO_TIMER0_TMMD);
44 outw(CONFIG_TIMER1_TMMD_STOP, IO_TIMER1_TMMD);
45 outw(CONFIG_TIMER2_TMMD_STOP, IO_TIMER2_TMMD);
46 outw(CONFIG_TIMER3_TMMD_STOP, IO_TIMER3_TMMD);
47 */
48 /* Turn Timer0 to Free Run mode */
49// outw(CONFIG_TIMER0_TMMD_FREE_RUN, IO_TIMER0_TMMD);
50
51 bool retval = false;
52
53 /* Find the minimum factor that puts the counter in range 1-65535 */
54 unsigned int prescaler = (cycles + 65534) / 65535;
55
56 /* Test this by writing 1's to registers to see how many bits we have */
57 /* Maximum divider setting is x / 1024 / 65536 = x / 67108864 */
58 {
59 int oldlevel;
60 unsigned int divider;
61
62 if (start && pfn_unregister != NULL)
63 {
64 pfn_unregister();
65 pfn_unregister = NULL;
66 }
67
68 oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL);
69
70 /* Max prescale is 1023+1 */
71 for (divider = 0; prescaler > 1024; prescaler >>= 1, divider++);
72
73 /* Setup the Prescalar */
74 outw(prescaler, IO_TIMER0_TMPRSCL);
75
76 /* Setup the Divisor */
77 outw(divider, IO_TIMER0_TMDIV);
78
79 set_irq_level(oldlevel);
80
81 retval = true;
82 }
83
84 return retval;
85}
86
87bool __timer_register(void)
88{
89 bool retval = true;
90
91 int oldstatus = set_interrupt_status(IRQ_FIQ_DISABLED, IRQ_FIQ_STATUS);
92
93 stop_timer();
94
95 /* Turn Timer0 to Free Run mode */
96 outw(0x0002, IO_TIMER0_TMMD);
97
98 set_interrupt_status(oldstatus, IRQ_FIQ_STATUS);
99
100 return retval;
101}
102
103void __timer_unregister(void)
104{
105 int oldstatus = set_interrupt_status(IRQ_FIQ_DISABLED, IRQ_FIQ_STATUS);
106 stop_timer();
107 set_interrupt_status(oldstatus, IRQ_FIQ_STATUS);
108}
diff --git a/firmware/target/arm/olympus/mrobe-500/timer-target.h b/firmware/target/arm/olympus/mrobe-500/timer-target.h
new file mode 100644
index 0000000000..320b35d5d3
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/timer-target.h
@@ -0,0 +1,39 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id: $
9*
10* Copyright (C) 2007 by Karl Kurbjun
11*
12* All files in this archive are subject to the GNU General Public License.
13* See the file COPYING in the source tree root for full license agreement.
14*
15* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16* KIND, either express or implied.
17*
18****************************************************************************/
19#ifndef TIMER_TARGET_H
20#define TIMER_TARGET_H
21
22/* timer is based on PCLK and minimum division is 2 */
23#define TIMER_FREQ (49156800/2)
24
25bool __timer_set(long cycles, bool set);
26bool __timer_register(void);
27void __timer_unregister(void);
28
29#define __TIMER_SET(cycles, set) \
30 __timer_set(cycles, set)
31
32#define __TIMER_REGISTER(reg_prio, unregister_callback, cycles, \
33 int_prio, timer_callback) \
34 __timer_register()
35
36#define __TIMER_UNREGISTER(...) \
37 __timer_unregister()
38
39#endif /* TIMER_TARGET_H */
diff --git a/firmware/target/arm/olympus/mrobe-500/usb-mr500.c b/firmware/target/arm/olympus/mrobe-500/usb-mr500.c
new file mode 100644
index 0000000000..e8d0e39c2e
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/usb-mr500.c
@@ -0,0 +1,55 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id: $
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22#include "system.h"
23#include "kernel.h"
24#include "ata.h"
25
26#define USB_RST_ASSERT
27#define USB_RST_DEASSERT
28
29#define USB_VPLUS_PWR_ASSERT
30#define USB_VPLUS_PWR_DEASSERT
31
32#define USB_UNIT_IS_PRESENT false
33
34/* The usb detect is one pin to the cpu active low */
35inline bool usb_detect(void)
36{
37 return USB_UNIT_IS_PRESENT;
38}
39
40void usb_init_device(void)
41{
42// ata_enable(true);
43}
44
45void usb_enable(bool on)
46{
47 if (on)
48 {
49 USB_VPLUS_PWR_ASSERT;
50 }
51 else
52 {
53 USB_VPLUS_PWR_DEASSERT;
54 }
55}
diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h
index 1a9cccc711..aeb90df399 100644
--- a/firmware/target/arm/system-arm.h
+++ b/firmware/target/arm/system-arm.h
@@ -22,6 +22,15 @@
22#define nop \ 22#define nop \
23 asm volatile ("nop") 23 asm volatile ("nop")
24 24
25//#define outw(v,a) *(volatile unsigned short *)(a+PHY_IO_BASE) = (v)
26#ifndef outw
27#define outw(v,p) (*((unsigned short*)(p + PHY_IO_BASE)) = v)
28#endif
29
30#ifndef inw
31#define inw(p) (*((unsigned short*)(p + PHY_IO_BASE)))
32#endif
33
25/* This gets too complicated otherwise with all the ARM variation and would 34/* This gets too complicated otherwise with all the ARM variation and would
26 have conflicts with another system-target.h elsewhere so include a 35 have conflicts with another system-target.h elsewhere so include a
27 subheader from here. */ 36 subheader from here. */
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 522e73123a..5cfd02840c 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -22,6 +22,7 @@
22 22
23#include "system-arm.h" 23#include "system-arm.h"
24 24
25#if (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
25/* TODO: This header is actually portalplayer specific, and should be 26/* TODO: This header is actually portalplayer specific, and should be
26 * moved into an appropriate subdir (or even split in 2). */ 27 * moved into an appropriate subdir (or even split in 2). */
27 28
@@ -90,5 +91,6 @@ static inline void flush_icache(void)
90} 91}
91 92
92#endif /* CONFIG_CPU */ 93#endif /* CONFIG_CPU */
94#endif
93 95
94#endif /* SYSTEM_TARGET_H */ 96#endif /* SYSTEM_TARGET_H */
diff --git a/firmware/thread.c b/firmware/thread.c
index a4981af256..86b90f4f0d 100644
--- a/firmware/thread.c
+++ b/firmware/thread.c
@@ -105,7 +105,7 @@ static void remove_from_list(struct thread_entry **list,
105 struct thread_entry *thread) ICODE_ATTR; 105 struct thread_entry *thread) ICODE_ATTR;
106*/ 106*/
107 107
108void switch_thread(bool save_context, struct thread_entry **blocked_list) 108void switch_thread(bool save_context, struct thread_entry **blocked_list)
109 ICODE_ATTR; 109 ICODE_ATTR;
110 110
111static inline void store_context(void* addr) __attribute__ ((always_inline)); 111static inline void store_context(void* addr) __attribute__ ((always_inline));
@@ -196,6 +196,11 @@ static inline void core_sleep(void)
196 for(i=0; i<10; i++); /* wait for IDLE */ 196 for(i=0; i<10; i++); /* wait for IDLE */
197 CLKCON &= ~(1 << 2); /* reset IDLE bit when wake up */ 197 CLKCON &= ~(1 << 2); /* reset IDLE bit when wake up */
198} 198}
199#else
200static inline void core_sleep(void)
201{
202
203}
199#endif 204#endif
200 205
201#elif defined(CPU_COLDFIRE) 206#elif defined(CPU_COLDFIRE)
diff --git a/firmware/timer.c b/firmware/timer.c
index 1ac16b697a..b86d4493a3 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -208,7 +208,7 @@ static bool timer_set(long cycles, bool start)
208 cycles_new = cycles; 208 cycles_new = cycles;
209 209
210 return true; 210 return true;
211#elif CONFIG_CPU == S3C2440 211#else
212 return __TIMER_SET(cycles, start); 212 return __TIMER_SET(cycles, start);
213#endif /* CONFIG_CPU */ 213#endif /* CONFIG_CPU */
214} 214}
@@ -268,7 +268,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
268 irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); 268 irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
269 irq_enable_int(IRQ_TIMER1); 269 irq_enable_int(IRQ_TIMER1);
270 return true; 270 return true;
271#elif CONFIG_CPU == S3C2440 271#else
272 return __TIMER_REGISTER(reg_prio, unregister_callback, cycles, 272 return __TIMER_REGISTER(reg_prio, unregister_callback, cycles,
273 int_prio, timer_callback); 273 int_prio, timer_callback);
274#endif 274#endif
diff --git a/tools/configure b/tools/configure
index 61c2618a98..a928e3060c 100755
--- a/tools/configure
+++ b/tools/configure
@@ -618,8 +618,8 @@ cat <<EOF
618 31) M5/M5L 51) Sansa e200R 618 31) M5/M5L 51) Sansa e200R
619 52) Sansa c200 619 52) Sansa c200
620 620
621 ==Tatung== 621 ==Tatung== ==Olympus==
622 60) Elio TPJ-1022 622 60) Elio TPJ-1022 70) M:Robe 500
623EOF 623EOF
624 624
625 buildfor=`input`; 625 buildfor=`input`;
@@ -1257,6 +1257,30 @@ EOF
1257 t_model="gigabeat-fx" 1257 t_model="gigabeat-fx"
1258 ;; 1258 ;;
1259 1259
1260 70|mrobe500)
1261 target_id=20
1262 archos="mrobe500"
1263 target="-DMROBE_500"
1264 memory=64 # always
1265 arm9tdmicc
1266 tool="$rootdir/tools/scramble -add=giga"
1267 bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
1268 bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
1269 output="rockbox.mrobe500"
1270 appextra="recorder:gui"
1271 archosrom=""
1272 flash=""
1273 plugins="no"
1274 swcodec="yes"
1275 toolset=$gigabeatbitmaptools
1276 boottool="cp "
1277 bootoutput="rockbox.mrboot"
1278 # architecture, manufacturer and model for the target-tree build
1279 t_cpu="arm"
1280 t_manufacturer="olympus"
1281 t_model="mrobe-500"
1282 ;;
1283
1260 50|e200) 1284 50|e200)
1261 target_id=23 1285 target_id=23
1262 archos="e200" 1286 archos="e200"
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 14:07:54 +0000