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| author | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2010-06-30 02:02:46 +0000 |
| commit | e286b0bbc04a34c181978efce19c6d0814e228c0 (patch) | |
| tree | 841288761e20dc9a7a25e5ba83306adf52547d65 /firmware/target/arm/s3c2440/adc-s3c2440.c | |
| parent | f4a00174b50c209f2a23b7a73fe7cb544ef59d02 (diff) | |
| download | rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.tar.gz rockbox-e286b0bbc04a34c181978efce19c6d0814e228c0.zip | |
Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s3c2440/adc-s3c2440.c')
| -rw-r--r-- | firmware/target/arm/s3c2440/adc-s3c2440.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/s3c2440/adc-s3c2440.c b/firmware/target/arm/s3c2440/adc-s3c2440.c index f42a3d2b6a..2e0cf8a512 100644 --- a/firmware/target/arm/s3c2440/adc-s3c2440.c +++ b/firmware/target/arm/s3c2440/adc-s3c2440.c | |||
| @@ -39,7 +39,7 @@ void adc_init(void) | |||
| 39 | int i; | 39 | int i; |
| 40 | 40 | ||
| 41 | /* Turn on the ADC PCLK */ | 41 | /* Turn on the ADC PCLK */ |
| 42 | s3c_regset32(&CLKCON, 1<<15); | 42 | bitset32(&CLKCON, 1<<15); |
| 43 | 43 | ||
| 44 | /* Set channel 0, normal mode, disable "start by read" */ | 44 | /* Set channel 0, normal mode, disable "start by read" */ |
| 45 | ADCCON &= ~(0x3F); | 45 | ADCCON &= ~(0x3F); |