Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657

10 files changed, 35 insertions, 63 deletions

diff --git a/firmware/target/arm/s3c2440/adc-s3c2440.c b/firmware/target/arm/s3c2440/adc-s3c2440.c
index f42a3d2b6a..2e0cf8a512 100644
--- a/firmware/target/arm/s3c2440/adc-s3c2440.c
+++ b/firmware/target/arm/s3c2440/adc-s3c2440.c
@@ -39,7 +39,7 @@ void adc_init(void)
     int i;
 
     /* Turn on the ADC PCLK */
-    s3c_regset32(&CLKCON, 1<<15);
+    bitset32(&CLKCON, 1<<15);
 
     /* Set channel 0, normal mode, disable "start by read" */
     ADCCON &= ~(0x3F);
diff --git a/firmware/target/arm/s3c2440/dma-s3c2440.c b/firmware/target/arm/s3c2440/dma-s3c2440.c
index b83897cb22..c8df4fcc75 100644
--- a/firmware/target/arm/s3c2440/dma-s3c2440.c
+++ b/firmware/target/arm/s3c2440/dma-s3c2440.c
@@ -76,8 +76,8 @@ void dma_init(void)
     INTPND = DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK;
     
     /* Enable interrupt in controller */
-    s3c_regclr32(&INTMOD, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK);
-    s3c_regclr32(&INTMSK, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK);
+    bitclr32(&INTMOD, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK);
+    bitclr32(&INTMSK, DMA0_MASK | DMA1_MASK | DMA2_MASK | DMA3_MASK);
 }
 
 void dma_retain(void)
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
index e9f55479c7..c1c9017fbb 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
@@ -50,14 +50,14 @@ void fiq_handler(void) __attribute__((interrupt ("FIQ")));
 void pcm_play_lock(void)
 {
     if (++dma_play_lock.locked == 1)
-        s3c_regset32(&INTMSK, DMA2_MASK);
+        bitset32(&INTMSK, DMA2_MASK);
 }
 
 /* Unmask the DMA interrupt if enabled */
 void pcm_play_unlock(void)
 {
     if (--dma_play_lock.locked == 0)
-        s3c_regclr32(&INTMSK, dma_play_lock.state);
+        bitclr32(&INTMSK, dma_play_lock.state);
 }
 
 void pcm_play_dma_init(void)
@@ -65,7 +65,7 @@ void pcm_play_dma_init(void)
     /* There seem to be problems when changing the IIS interface configuration
      * when a clock is not present.
      */
-    s3c_regset32(&CLKCON, 1<<17);
+    bitset32(&CLKCON, 1<<17);
     /* slave, transmit mode, 16 bit samples - MCLK 384fs - use 16.9344Mhz -
        BCLK 32fs */
     IISMOD = (1<<9) | (1<<8) | (2<<6) | (1<<3) | (1<<2) | (1<<0);
@@ -73,7 +73,7 @@ void pcm_play_dma_init(void)
     /* RX,TX off,on */
     IISCON |= (1<<3) | (1<<2);
 
-    s3c_regclr32(&CLKCON, 1<<17);
+    bitclr32(&CLKCON, 1<<17);
 
     audiohw_init();
 
@@ -86,11 +86,11 @@ void pcm_play_dma_init(void)
     /* Do not service DMA requests, yet */
 
     /* clear any pending int and mask it */
-    s3c_regset32(&INTMSK, DMA2_MASK);
+    bitset32(&INTMSK, DMA2_MASK);
     SRCPND = DMA2_MASK;
 
     /* connect to FIQ */
-    s3c_regset32(&INTMOD, DMA2_MASK);
+    bitset32(&INTMOD, DMA2_MASK);
 }
 
 void pcm_postinit(void)
@@ -132,7 +132,7 @@ static void play_start_pcm(void)
 static void play_stop_pcm(void)
 {
     /* Mask DMA interrupt */
-    s3c_regset32(&INTMSK, DMA2_MASK);
+    bitset32(&INTMSK, DMA2_MASK);
 
     /* De-Activate the DMA channel */
     DMASKTRIG2 = 0x4;
@@ -160,7 +160,7 @@ static void play_stop_pcm(void)
 void pcm_play_dma_start(const void *addr, size_t size)
 {
     /* Enable the IIS clock */
-    s3c_regset32(&CLKCON, 1<<17);
+    bitset32(&CLKCON, 1<<17);
 
     /* stop any DMA in progress - idle IIS */
     play_stop_pcm();
@@ -191,7 +191,7 @@ void pcm_play_dma_stop(void)
     play_stop_pcm();
 
     /* Disconnect the IIS clock */
-    s3c_regclr32(&CLKCON, 1<<17);
+    bitclr32(&CLKCON, 1<<17);
 }
 
 void pcm_play_dma_pause(bool pause)
diff --git a/firmware/target/arm/s3c2440/i2c-s3c2440.c b/firmware/target/arm/s3c2440/i2c-s3c2440.c
index 4669186a4c..155eb2f956 100644
--- a/firmware/target/arm/s3c2440/i2c-s3c2440.c
+++ b/firmware/target/arm/s3c2440/i2c-s3c2440.c
@@ -43,7 +43,7 @@ void i2c_write(int addr, const unsigned char *buf, int count)
     mutex_lock(&i2c_mtx);
 
     /* Turn on I2C clock */
-    s3c_regset32(&CLKCON, 1 << 16);
+    bitset32(&CLKCON, 1 << 16);
 
     /* Set mode to master transmitter and enable lines */
     IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB;
@@ -76,7 +76,7 @@ void i2c_write(int addr, const unsigned char *buf, int count)
     IICSTAT = 0;
 
     /* Turn off I2C clock */
-    s3c_regclr32(&CLKCON, 1 << 16);
+    bitclr32(&CLKCON, 1 << 16);
 
     mutex_unlock(&i2c_mtx);
 }
@@ -92,11 +92,11 @@ void i2c_init(void)
     INTPND = IIC_MASK;
 
     /* Enable i2c interrupt in controller */
-    s3c_regclr32(&INTMOD, IIC_MASK);
-    s3c_regclr32(&INTMSK, IIC_MASK);
+    bitclr32(&INTMOD, IIC_MASK);
+    bitclr32(&INTMSK, IIC_MASK);
 
     /* Turn on I2C clock */
-    s3c_regset32(&CLKCON, 1 << 16);
+    bitset32(&CLKCON, 1 << 16);
 
     /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */
     GPECON = (GPECON & ~((3 << 30) | (3 << 28))) |
@@ -110,7 +110,7 @@ void i2c_init(void)
     IICLC = (0 << 0);
 
     /* Turn off I2C clock */
-    s3c_regclr32(&CLKCON, 1 << 16);
+    bitclr32(&CLKCON, 1 << 16);
 }
 
 void IIC(void)
diff --git a/firmware/target/arm/s3c2440/kernel-s3c2440.c b/firmware/target/arm/s3c2440/kernel-s3c2440.c
index 6cabc8dc81..892758e147 100644
--- a/firmware/target/arm/s3c2440/kernel-s3c2440.c
+++ b/firmware/target/arm/s3c2440/kernel-s3c2440.c
@@ -62,7 +62,7 @@ void tick_start(unsigned int interval_in_ms)
 #ifdef BOOTLOADER
 void tick_stop(void)
 {
-    s3c_regset32(&INTMSK, TIMER4_MASK);
+    bitset32(&INTMSK, TIMER4_MASK);
     TCON &= ~(1 << 20);
     SRCPND = TIMER4_MASK;
     INTPND = TIMER4_MASK;
diff --git a/firmware/target/arm/s3c2440/lcd-s3c2440.c b/firmware/target/arm/s3c2440/lcd-s3c2440.c
index b9f7d3ef3d..77be29f556 100644
--- a/firmware/target/arm/s3c2440/lcd-s3c2440.c
+++ b/firmware/target/arm/s3c2440/lcd-s3c2440.c
@@ -101,7 +101,7 @@ static void LCD_CTRL_clock(bool onoff)
         GPDCON  |= 0xAAA0AAA0;
         GPDUP   |= 0xFCFC;
 
-        s3c_regset32(&CLKCON, 0x20);  /* enable LCD clock */
+        bitset32(&CLKCON, 0x20);  /* enable LCD clock */
         LCDCON1 |= LCD_ENVID;
     }
     else
@@ -113,7 +113,7 @@ static void LCD_CTRL_clock(bool onoff)
         GPDUP   &= ~0xFCFC;
 
         LCDCON1 &= ~LCD_ENVID;        /* Must disable first or bus may freeze */
-        s3c_regclr32(&CLKCON, 0x20);  /* disable LCD clock */
+        bitclr32(&CLKCON, 0x20);  /* disable LCD clock */
     }
 }
 
@@ -165,7 +165,7 @@ static void LCD_SPI_SS(bool select)
 
 static void LCD_SPI_start(void)
 {
-    s3c_regset32(&CLKCON, 0x40000);   /* enable SPI clock */
+    bitset32(&CLKCON, 0x40000);   /* enable SPI clock */
     LCD_SPI_SS(false);
     SPCON0=0x3E;
     SPPRE0=24;
@@ -179,7 +179,7 @@ static void LCD_SPI_stop(void)
     LCD_SPI_SS(false);
 
     SPCON0 &= ~0x10;
-    s3c_regclr32(&CLKCON, 0x40000);    /* disable SPI clock */
+    bitclr32(&CLKCON, 0x40000);    /* disable SPI clock */
 }
 
 static void LCD_SPI_init(void)
@@ -253,7 +253,7 @@ void lcd_init_device(void)
     GPBUP   |= 0x181;
 #endif
 
-    s3c_regset32(&CLKCON, 0x20);  /* enable LCD clock */
+    bitset32(&CLKCON, 0x20);  /* enable LCD clock */
 
     LCD_CTRL_setup();
 #ifdef GIGABEAT_F
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
index 30db29c42c..8a6b62f31f 100644
--- a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
+++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
@@ -62,14 +62,14 @@ void fiq_handler(void) __attribute__((interrupt ("FIQ")));
 void pcm_play_lock(void)
 {
     if (++dma_play_lock.locked == 1)
-        s3c_regset32(&INTMSK, DMA2_MASK);
+        bitset32(&INTMSK, DMA2_MASK);
 }
 
 /* Unmask the DMA interrupt if enabled */
 void pcm_play_unlock(void)
 {
     if (--dma_play_lock.locked == 0)
-        s3c_regclr32(&INTMSK, dma_play_lock.state);
+        bitclr32(&INTMSK, dma_play_lock.state);
 }
 
 void pcm_play_dma_init(void)
@@ -77,7 +77,7 @@ void pcm_play_dma_init(void)
     /* There seem to be problems when changing the IIS interface configuration
      * when a clock is not present.
      */
-    s3c_regset32(&CLKCON, 1<<17);
+    bitset32(&CLKCON, 1<<17);
     
 #ifdef HAVE_UDA1341
     /* master, transmit mode, 16 bit samples, BCLK 32fs, PCLK */
@@ -95,7 +95,7 @@ void pcm_play_dma_init(void)
     IISCON |= (1<<3) | (1<<2);
 #endif
 
-    s3c_regclr32(&CLKCON, 1<<17);
+    bitclr32(&CLKCON, 1<<17);
 
     audiohw_init();
 
@@ -112,11 +112,11 @@ void pcm_play_dma_init(void)
     /* Do not service DMA requests, yet */
 
     /* clear any pending int and mask it */
-    s3c_regset32(&INTMSK, DMA2_MASK);
+    bitset32(&INTMSK, DMA2_MASK);
     SRCPND = DMA2_MASK;
 
     /* connect to FIQ */
-    s3c_regset32(&INTMOD, DMA2_MASK);
+    bitset32(&INTMOD, DMA2_MASK);
 }
 
 void pcm_postinit(void)
@@ -172,7 +172,7 @@ static void play_start_pcm(void)
 static void play_stop_pcm(void)
 {
     /* Mask DMA interrupt */
-    s3c_regset32(&INTMSK, DMA2_MASK);
+    bitset32(&INTMSK, DMA2_MASK);
 
     /* De-Activate the DMA channel */
     DMASKTRIG2 = 0x4;
@@ -200,7 +200,7 @@ static void play_stop_pcm(void)
 void pcm_play_dma_start(const void *addr, size_t size)
 {
     /* Enable the IIS clock */
-    s3c_regset32(&CLKCON, 1<<17);
+    bitset32(&CLKCON, 1<<17);
 
     /* stop any DMA in progress - idle IIS */
     play_stop_pcm();
@@ -231,7 +231,7 @@ void pcm_play_dma_stop(void)
     play_stop_pcm();
 
     /* Disconnect the IIS clock */
-    s3c_regclr32(&CLKCON, 1<<17);
+    bitclr32(&CLKCON, 1<<17);
 }
 
 void pcm_play_dma_pause(bool pause)
diff --git a/firmware/target/arm/s3c2440/sd-s3c2440.c b/firmware/target/arm/s3c2440/sd-s3c2440.c
index f4c8a4f599..d42405db65 100644
--- a/firmware/target/arm/s3c2440/sd-s3c2440.c
+++ b/firmware/target/arm/s3c2440/sd-s3c2440.c
@@ -299,8 +299,8 @@ static void init_sdi_controller(const int card_no)
 
 #if 1
     /* Enable interrupt in controller */
-    s3c_regclr32(&INTMOD, SDI_MASK);
-    s3c_regclr32(&INTMSK, SDI_MASK);
+    bitclr32(&INTMOD, SDI_MASK);
+    bitclr32(&INTMSK, SDI_MASK);
     
     SDIIMSK |= S3C2410_SDIIMSK_DATAFINISH 
                | S3C2410_SDIIMSK_DATATIMEOUT
diff --git a/firmware/target/arm/s3c2440/system-s3c2440.c b/firmware/target/arm/s3c2440/system-s3c2440.c
index cb273ad4df..577b46966c 100644
--- a/firmware/target/arm/s3c2440/system-s3c2440.c
+++ b/firmware/target/arm/s3c2440/system-s3c2440.c
@@ -136,24 +136,6 @@ void memory_init(void)
     enable_mmu();
 }
 
-void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
-                  unsigned long mask)
-{
-    int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
-    *reg = (*reg & ~mask) | (bits & mask);
-    restore_interrupt(oldstatus);
-}
-
-void s3c_regset32(volatile unsigned long *reg, unsigned long bits)
-{
-    s3c_regmod32(reg, bits, bits);
-}
-
-void s3c_regclr32(volatile unsigned long *reg, unsigned long bits)
-{
-    s3c_regmod32(reg, 0, bits);
-}
-
 #ifdef BOOTLOADER
 void system_prepare_fw_start(void)
 {
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h
index ad32f89552..c48a62cf47 100644
--- a/firmware/target/arm/s3c2440/system-target.h
+++ b/firmware/target/arm/s3c2440/system-target.h
@@ -69,14 +69,4 @@
 void system_prepare_fw_start(void);
 void tick_stop(void);
 
-/* Functions to set and clear register bits atomically */
-
-/* Set and clear register bits */
-void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
-                  unsigned long mask);
-/* Set register bits */
-void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
-/* Clear register bits */
-void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
-
 #endif /* SYSTEM_TARGET_H */