diff options
Diffstat (limited to 'firmware/target/arm/imx31/dvfs_dptc-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/dvfs_dptc-imx31.c | 54 |
1 files changed, 26 insertions, 28 deletions
diff --git a/firmware/target/arm/imx31/dvfs_dptc-imx31.c b/firmware/target/arm/imx31/dvfs_dptc-imx31.c index 6bacc20c10..aa8d0f52fb 100644 --- a/firmware/target/arm/imx31/dvfs_dptc-imx31.c +++ b/firmware/target/arm/imx31/dvfs_dptc-imx31.c | |||
@@ -275,7 +275,7 @@ static void INIT_ATTR dvfs_init(void) | |||
275 | 275 | ||
276 | #ifndef DVFS_NO_PWRRDY | 276 | #ifndef DVFS_NO_PWRRDY |
277 | /* Configure PWRRDY signal pin. */ | 277 | /* Configure PWRRDY signal pin. */ |
278 | imx31_regclr32(&GPIO1_GDIR, (1 << 5)); | 278 | bitclr32(&GPIO1_GDIR, (1 << 5)); |
279 | iomuxc_set_pin_mux(IOMUXC_GPIO1_5, | 279 | iomuxc_set_pin_mux(IOMUXC_GPIO1_5, |
280 | IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL); | 280 | IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL); |
281 | #endif | 281 | #endif |
@@ -289,27 +289,26 @@ static void INIT_ATTR dvfs_init(void) | |||
289 | } | 289 | } |
290 | 290 | ||
291 | /* Set up LTR0. */ | 291 | /* Set up LTR0. */ |
292 | imx31_regmod32(&CCM_LTR0, | 292 | bitmod32(&CCM_LTR0, |
293 | DVFS_UPTHR << CCM_LTR0_UPTHR_POS | | 293 | DVFS_UPTHR << CCM_LTR0_UPTHR_POS | |
294 | DVFS_DNTHR << CCM_LTR0_DNTHR_POS | | 294 | DVFS_DNTHR << CCM_LTR0_DNTHR_POS | |
295 | DVFS_DIV3CK << CCM_LTR0_DIV3CK_POS, | 295 | DVFS_DIV3CK << CCM_LTR0_DIV3CK_POS, |
296 | CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK); | 296 | CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK); |
297 | 297 | ||
298 | /* Set up LTR1. */ | 298 | /* Set up LTR1. */ |
299 | imx31_regmod32(&CCM_LTR1, | 299 | bitmod32(&CCM_LTR1, |
300 | DVFS_DNCNT << CCM_LTR1_DNCNT_POS | | 300 | DVFS_DNCNT << CCM_LTR1_DNCNT_POS | |
301 | DVFS_UPCNT << CCM_LTR1_UPCNT_POS | | 301 | DVFS_UPCNT << CCM_LTR1_UPCNT_POS | |
302 | DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS | | 302 | DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS | |
303 | CCM_LTR1_LTBRSR, | 303 | CCM_LTR1_LTBRSR, |
304 | CCM_LTR1_DNCNT | CCM_LTR1_UPCNT | | 304 | CCM_LTR1_DNCNT | CCM_LTR1_UPCNT | |
305 | CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR); | 305 | CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR); |
306 | 306 | ||
307 | /* Set up LTR2-- EMA configuration. */ | 307 | /* Set up LTR2-- EMA configuration. */ |
308 | imx31_regmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS, | 308 | bitmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS, CCM_LTR2_EMAC); |
309 | CCM_LTR2_EMAC); | ||
310 | 309 | ||
311 | /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */ | 310 | /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */ |
312 | imx31_regset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI); | 311 | bitset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI); |
313 | 312 | ||
314 | /* Initialize current core PLL and dividers for default level. Assumes | 313 | /* Initialize current core PLL and dividers for default level. Assumes |
315 | * clocking scheme has been set up appropriately in other init code. */ | 314 | * clocking scheme has been set up appropriately in other init code. */ |
@@ -517,8 +516,8 @@ static __attribute__((interrupt("IRQ"))) void CCM_CLK_HANDLER(void) | |||
517 | static void INIT_ATTR dptc_init(void) | 516 | static void INIT_ATTR dptc_init(void) |
518 | { | 517 | { |
519 | /* Force DPTC off if running for some reason. */ | 518 | /* Force DPTC off if running for some reason. */ |
520 | imx31_regmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM, | 519 | bitmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM, |
521 | CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN); | 520 | CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN); |
522 | 521 | ||
523 | /* Shadow the regulator registers */ | 522 | /* Shadow the regulator registers */ |
524 | mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2); | 523 | mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2); |
@@ -528,14 +527,14 @@ static void INIT_ATTR dptc_init(void) | |||
528 | 527 | ||
529 | /* Interrupt goes to MCU, specified reference circuits enabled when | 528 | /* Interrupt goes to MCU, specified reference circuits enabled when |
530 | * DPTC is active. */ | 529 | * DPTC is active. */ |
531 | imx31_regset32(&CCM_PMCR0, CCM_PMCR0_PTVIS); | 530 | bitset32(&CCM_PMCR0, CCM_PMCR0_PTVIS); |
532 | 531 | ||
533 | imx31_regmod32(&CCM_PMCR0, DPTC_DRCE_MASK, | 532 | bitmod32(&CCM_PMCR0, DPTC_DRCE_MASK, |
534 | CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 | | 533 | CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 | |
535 | CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3); | 534 | CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3); |
536 | 535 | ||
537 | /* DPTC counting range = 256 system clocks */ | 536 | /* DPTC counting range = 256 system clocks */ |
538 | imx31_regclr32(&CCM_PMCR0, CCM_PMCR0_DCR); | 537 | bitclr32(&CCM_PMCR0, CCM_PMCR0_DCR); |
539 | 538 | ||
540 | logf("DPTC: Initialized"); | 539 | logf("DPTC: Initialized"); |
541 | } | 540 | } |
@@ -629,7 +628,7 @@ void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value) | |||
629 | shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */ | 628 | shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */ |
630 | } | 629 | } |
631 | 630 | ||
632 | imx31_regmod32(reg_p, value << shift, 0x7 << shift); | 631 | bitmod32(reg_p, value << shift, 0x7 << shift); |
633 | } | 632 | } |
634 | 633 | ||
635 | 634 | ||
@@ -643,7 +642,7 @@ void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge) | |||
643 | else if ((unsigned)index < 16) | 642 | else if ((unsigned)index < 16) |
644 | bit = 1ul << (index + 29); | 643 | bit = 1ul << (index + 29); |
645 | 644 | ||
646 | imx31_regmod32(&CCM_LTR0, edge ? bit : 0, bit); | 645 | bitmod32(&CCM_LTR0, edge ? bit : 0, bit); |
647 | } | 646 | } |
648 | 647 | ||
649 | 648 | ||
@@ -652,7 +651,7 @@ void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert) | |||
652 | if ((unsigned)dvgp <= 3) | 651 | if ((unsigned)dvgp <= 3) |
653 | { | 652 | { |
654 | unsigned long bit = 1ul << dvgp; | 653 | unsigned long bit = 1ul << dvgp; |
655 | imx31_regmod32(&CCM_PMCR1, assert ? bit : 0, bit); | 654 | bitmod32(&CCM_PMCR1, assert ? bit : 0, bit); |
656 | } | 655 | } |
657 | } | 656 | } |
658 | 657 | ||
@@ -660,8 +659,7 @@ void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert) | |||
660 | /* Turn the wait-for-interrupt monitoring on or off */ | 659 | /* Turn the wait-for-interrupt monitoring on or off */ |
661 | void dvfs_wfi_monitor(bool on) | 660 | void dvfs_wfi_monitor(bool on) |
662 | { | 661 | { |
663 | imx31_regmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM, | 662 | bitmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM, CCM_PMCR0_WFIM); |
664 | CCM_PMCR0_WFIM); | ||
665 | } | 663 | } |
666 | 664 | ||
667 | 665 | ||