Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 3 insertions, 3 deletions

diff --git a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c
index 4540be671a..9d7d30547b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c
@@ -85,17 +85,17 @@ void ide_power_enable(bool on)
     if (!on)
     {
         /* Bus must be isolated before power off */
-        imx31_regset32(&GPIO2_DR, (1 << 16));
+        bitset32(&GPIO2_DR, (1 << 16));
     }
 
     /* HD power switch */
-    imx31_regmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5));
+    bitmod32(&GPIO3_DR, on ? (1 << 5) : 0, (1 << 5));
 
     if (on)
     {
         /* Bus switch may be turned on after powerup */
         sleep(HZ/10);
-        imx31_regclr32(&GPIO2_DR, (1 << 16));
+        bitclr32(&GPIO2_DR, (1 << 16));
     }
 }