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author | Michael Sevakis <jethead71@rockbox.org> | 2009-03-22 01:50:48 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2009-03-22 01:50:48 +0000 |
commit | b7f7655dc2ae979fee8b01ed894224e5c2f7c719 (patch) | |
tree | 6540a83276514c2ea27b9c633ac9872588e126be /firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |
parent | 6a76ebbab10594f425edbd26e1fa35b0e37a61e5 (diff) | |
download | rockbox-b7f7655dc2ae979fee8b01ed894224e5c2f7c719.tar.gz rockbox-b7f7655dc2ae979fee8b01ed894224e5c2f7c719.zip |
imx31/mc13783: Do some housekeeping with register macros, function names and other defines. No functional changes (except to alter a couple int priorities).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20442 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c index 7646402435..d846f4d1d0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |||
@@ -50,22 +50,18 @@ void fmradio_i2c_init(void) | |||
50 | * disabled */ | 50 | * disabled */ |
51 | imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1, | 51 | imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1, |
52 | /* RI_DTE1 (I2C2_SCLK) */ | 52 | /* RI_DTE1 (I2C2_SCLK) */ |
53 | SW_PAD_CTL_IO2w(SW_PAD_CTL_PUE_PKE_DISABLE | | 53 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | |
54 | SW_PAD_CTL_PUS_UP_100K | | 54 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO2_POS) | |
55 | SW_PAD_CTL_HYS | | ||
56 | SW_PAD_CTL_ODE) | | ||
57 | /* DCD_DTE1 (I2C2_SDA) */ | 55 | /* DCD_DTE1 (I2C2_SDA) */ |
58 | SW_PAD_CTL_IO1w(SW_PAD_CTL_PUE_PKE_DISABLE | | 56 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | |
59 | SW_PAD_CTL_PUS_UP_100K | | 57 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO1_POS), |
60 | SW_PAD_CTL_HYS | | ||
61 | SW_PAD_CTL_ODE), | ||
62 | SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1); | 58 | SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1); |
63 | /* set outputs to I2C2 */ | 59 | /* set outputs to I2C2 */ |
64 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 60 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, |
65 | /* RI_DTE1 => I2C2_SCLK */ | 61 | /* RI_DTE1 => I2C2_SCLK */ |
66 | SW_MUX_CTL_SIG4w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) | | 62 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG4_POS) | |
67 | /* DCD_DTE1 => I2C2_SDA */ | 63 | /* DCD_DTE1 => I2C2_SDA */ |
68 | SW_MUX_CTL_SIG3w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2), | 64 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG3_POS), |
69 | SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3); | 65 | SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3); |
70 | } | 66 | } |
71 | 67 | ||
@@ -79,7 +75,8 @@ void fmradio_i2c_enable(bool enable) | |||
79 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ | 75 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ |
80 | /* I2C2_SDA => MCU2_15 */ | 76 | /* I2C2_SDA => MCU2_15 */ |
81 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 77 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, |
82 | SW_MUX_CTL_SIG3w(SW_MUX_OUT_GPIO_DR | SW_MUX_IN_GPIO_PSR_ISR), | 78 | (SW_MUX_OUT_GPIO_DR | |
79 | SW_MUX_IN_GPIO_PSR_ISR) << SW_MUX_CTL_SIG3_POS, | ||
83 | SW_MUX_CTL_SIG3); | 80 | SW_MUX_CTL_SIG3); |
84 | /* enable CLK32KMCU clock */ | 81 | /* enable CLK32KMCU clock */ |
85 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 82 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |