diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2009-03-22 01:50:48 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2009-03-22 01:50:48 +0000 |
commit | b7f7655dc2ae979fee8b01ed894224e5c2f7c719 (patch) | |
tree | 6540a83276514c2ea27b9c633ac9872588e126be | |
parent | 6a76ebbab10594f425edbd26e1fa35b0e37a61e5 (diff) | |
download | rockbox-b7f7655dc2ae979fee8b01ed894224e5c2f7c719.tar.gz rockbox-b7f7655dc2ae979fee8b01ed894224e5c2f7c719.zip |
imx31/mc13783: Do some housekeeping with register macros, function names and other defines. No functional changes (except to alter a couple int priorities).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20442 a1c6a512-1295-4272-9138-f99709370657
23 files changed, 465 insertions, 596 deletions
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index ea2187e0c2..2c1e93e528 100755 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -247,10 +247,10 @@ | |||
247 | #define SW_MUX_CTL_SIG3 (0x7f << 16) | 247 | #define SW_MUX_CTL_SIG3 (0x7f << 16) |
248 | #define SW_MUX_CTL_SIG4 (0x7f << 24) | 248 | #define SW_MUX_CTL_SIG4 (0x7f << 24) |
249 | /* Shift above flags into one of the four fields in each register */ | 249 | /* Shift above flags into one of the four fields in each register */ |
250 | #define SW_MUX_CTL_SIG1w(x) (((x) << 0) & SW_MUX_CTL_SIG1) | 250 | #define SW_MUX_CTL_SIG1_POS (0) |
251 | #define SW_MUX_CTL_SIG2w(x) (((x) << 8) & SW_MUX_CTL_SIG2) | 251 | #define SW_MUX_CTL_SIG2_POS (8) |
252 | #define SW_MUX_CTL_SIG3w(x) (((x) << 16) & SW_MUX_CTL_SIG3) | 252 | #define SW_MUX_CTL_SIG3_POS (16) |
253 | #define SW_MUX_CTL_SIG4w(x) (((x) << 24) & SW_MUX_CTL_SIG4) | 253 | #define SW_MUX_CTL_SIG4_POS (24) |
254 | 254 | ||
255 | /* SW_PAD_CTL */ | 255 | /* SW_PAD_CTL */ |
256 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) | 256 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) |
@@ -395,9 +395,9 @@ | |||
395 | #define SW_PAD_CTL_IO3 (0x3ff << 20) | 395 | #define SW_PAD_CTL_IO3 (0x3ff << 20) |
396 | 396 | ||
397 | /* Shift above flags into one of the three fields in each register */ | 397 | /* Shift above flags into one of the three fields in each register */ |
398 | #define SW_PAD_CTL_IO1w(x) (((x) << 0) & SW_PAD_CTL_IO1) | 398 | #define SW_PAD_CTL_IO1_POS (0) |
399 | #define SW_PAD_CTL_IO2w(x) (((x) << 10) & SW_PAD_CTL_IO2) | 399 | #define SW_PAD_CTL_IO2_POS (10) |
400 | #define SW_PAD_CTL_IO3w(x) (((x) << 20) & SW_PAD_CTL_IO3) | 400 | #define SW_PAD_CTL_IO3_POS (20) |
401 | 401 | ||
402 | /* RNGA */ | 402 | /* RNGA */ |
403 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) | 403 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) |
@@ -530,7 +530,8 @@ | |||
530 | #define EPITCR_DBGEN (1 << 18) | 530 | #define EPITCR_DBGEN (1 << 18) |
531 | #define EPITCR_IOVW (1 << 17) | 531 | #define EPITCR_IOVW (1 << 17) |
532 | #define EPITCR_SWR (1 << 16) | 532 | #define EPITCR_SWR (1 << 16) |
533 | #define EPITCR_PRESCALER(n) ((n) << 4) /* Divide by n+1 */ | 533 | #define EPITCR_PRESCALER (0xfff << 4) /* Divide by n+1 */ |
534 | #define EPITCR_PRESCALER_POS (4) | ||
534 | #define EPITCR_RLD (1 << 3) | 535 | #define EPITCR_RLD (1 << 3) |
535 | #define EPITCR_OCIEN (1 << 2) | 536 | #define EPITCR_OCIEN (1 << 2) |
536 | #define EPITCR_ENMOD (1 << 1) | 537 | #define EPITCR_ENMOD (1 << 1) |
@@ -933,10 +934,10 @@ | |||
933 | #define AUDMUX_CNMCR_CLKPOL (1 << 16) | 934 | #define AUDMUX_CNMCR_CLKPOL (1 << 16) |
934 | 935 | ||
935 | #define AUDMUX_CNMCR_CNTHI (0xff << 8) | 936 | #define AUDMUX_CNMCR_CNTHI (0xff << 8) |
936 | #define AUDMUX_CNMCR_CNTHIw(x) (((x) << 8) & AUDMUX_CNMCR_CNTHI) | 937 | #define AUDMUX_CNMCR_CNTHI_POS (8) |
937 | 938 | ||
938 | #define AUDMUX_CNMCR_CNTLOW (0xff << 0) | 939 | #define AUDMUX_CNMCR_CNTLOW (0xff << 0) |
939 | #define AUDMUX_CNMCR_CNTLOWw(x) (((x) << 0) & AUDMUX_CNMCR_CNTLOW) | 940 | #define AUDMUX_CNMCR_CNTLOW_POS (0) |
940 | 941 | ||
941 | /* SSI */ | 942 | /* SSI */ |
942 | #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00)) | 943 | #define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00)) |
@@ -1080,57 +1081,39 @@ | |||
1080 | #define SSI_STRCCR_WL24 (0xb << 13) | 1081 | #define SSI_STRCCR_WL24 (0xb << 13) |
1081 | 1082 | ||
1082 | #define SSI_STRCCR_DC (0x1f << 8) | 1083 | #define SSI_STRCCR_DC (0x1f << 8) |
1083 | #define SSI_STRCCR_DCw(x) (((x) << 8) & SSI_STRCCR_DC) | 1084 | #define SSI_STRCCR_DC_POS (8) |
1084 | #define SSI_STRCCR_DCr(x) (((x) & SSI_SRCCR_DC) >> 8) | ||
1085 | 1085 | ||
1086 | #define SSI_STRCCR_PM (0xf << 0) | 1086 | #define SSI_STRCCR_PM (0xf << 0) |
1087 | #define SSI_STRCCR_PMw(x) (((x) << 0) & SSI_STRCCR_PM) | 1087 | #define SSI_STRCCR_PM_POS (0) |
1088 | #define SSI_STRCCR_PMr(x) (((x) & SSI_SRCCR_PM) >> 0) | ||
1089 | 1088 | ||
1090 | /* SSI SFCSR */ | 1089 | /* SSI SFCSR */ |
1091 | #define SSI_SFCSR_RFCNT1 (0xf << 28) | 1090 | #define SSI_SFCSR_RFCNT1 (0xf << 28) |
1092 | #define SSI_SFCSR_RFCNT1w(x) (((x) << 28) & SSI_SFCSR_RFCNT1) | 1091 | #define SSI_SFCSR_RFCNT1_POS (28) |
1093 | #define SSI_SFCSR_RFCNT1r(x) (((x) & SSI_SFCSR_RFCNT1) >> 28) | ||
1094 | 1092 | ||
1095 | #define SSI_SFCSR_TFCNT1 (0xf << 24) | 1093 | #define SSI_SFCSR_TFCNT1 (0xf << 24) |
1096 | #define SSI_SFCSR_TFCNT1w(x) (((x) << 24) & SSI_SFCSR_TFCNT1) | 1094 | #define SSI_SFCSR_TFCNN1_POS (24) |
1097 | #define SSI_SFCSR_TFCNT1r(x) (((x) & SSI_SFCSR_TFCNT1) >> 24) | ||
1098 | 1095 | ||
1099 | #define SSI_SFCSR_RFWM1 (0xf << 20) | 1096 | #define SSI_SFCSR_RFWM1 (0xf << 20) |
1100 | #define SSI_SFCSR_RFWM1w(x) (((x) << 20) & SSI_SFCSR_RFWM1) | 1097 | #define SSI_SFCSR_RFWM1_POS (20) |
1101 | #define SSI_SFCSR_RFWM1r(x) (((x) & SSI_SFCSR_RFWM1) >> 20) | ||
1102 | #define SSI_SFCSR_RFWM1_1 (0x1 << 20) | ||
1103 | #define SSI_SFCSR_RFWM1_2 (0x2 << 20) | ||
1104 | #define SSI_SFCSR_RFWM1_3 (0x3 << 20) | ||
1105 | #define SSI_SFCSR_RFWM1_4 (0x4 << 20) | ||
1106 | #define SSI_SFCSR_RFWM1_5 (0x5 << 20) | ||
1107 | #define SSI_SFCSR_RFWM1_6 (0x6 << 20) | ||
1108 | #define SSI_SFCSR_RFWM1_7 (0x7 << 20) | ||
1109 | 1098 | ||
1110 | #define SSI_SFCSR_TFWM1 (0xf << 16) | 1099 | #define SSI_SFCSR_TFWM1 (0xf << 16) |
1111 | #define SSI_SFCSR_TFWM1w(x) (((x) << 16) & SSI_SFCSR_TFWM1) | 1100 | #define SSI_SFCSR_TFWM1_POS (16) |
1112 | #define SSI_SFCSR_TFWM1r(x) (((x) & SSI_SFCSR_TFWM1) >> 16) | ||
1113 | 1101 | ||
1114 | #define SSI_SFCSR_RFCNT0 (0xf << 12) | 1102 | #define SSI_SFCSR_RFCNT0 (0xf << 12) |
1115 | #define SSI_SFCSR_RFCNT0w(x) (((x) << 12) & SSI_SFCSR_RFCNT0) | 1103 | #define SSI_SFCSR_RFCNT0_POS (12) |
1116 | #define SSI_SFCSR_RFCNT0r(x) (((x) & SSI_SFCSR_RFCNT0) >> 12) | ||
1117 | 1104 | ||
1118 | #define SSI_SFCSR_TFCNT0 (0xf << 8) | 1105 | #define SSI_SFCSR_TFCNT0 (0xf << 8) |
1119 | #define SSI_SFCSR_TFCNT0w(x) (((x) << 8) & SSI_SFCSR_TFCNT0) | 1106 | #define SSI_SFCSR_TFCNT0_POS (8) |
1120 | #define SSI_SFCSR_TFCNT0r(x) (((x) & SSI_SFCSR_TFCNT0) >> 8) | ||
1121 | 1107 | ||
1122 | #define SSI_SFCSR_RFWM0 (0xf << 4) | 1108 | #define SSI_SFCSR_RFWM0 (0xf << 4) |
1123 | #define SSI_SFCSR_RFWM0w(x) (((x) << 4) & SSI_SFCSR_RFWM0) | 1109 | #define SSI_SFCSR_RFWM0_POS (4) |
1124 | #define SSI_SFCSR_RFWM0r(x) (((x) & SSI_SFCSR_RFWM0) >> 4) | ||
1125 | 1110 | ||
1126 | #define SSI_SFCSR_TFWM0 (0xf << 0) | 1111 | #define SSI_SFCSR_TFWM0 (0xf << 0) |
1127 | #define SSI_SFCSR_TFWM0w(x) (((x) << 0) & SSI_SFCSR_TFWM0) | 1112 | #define SSI_SFCSR_TFWM0_POS (0) |
1128 | #define SSI_SFCSR_TFWM0r(x) (((x) & SSI_SFCSR_TFWM0) >> 0) | ||
1129 | 1113 | ||
1130 | /* SACNT */ | 1114 | /* SACNT */ |
1131 | #define SSI_SACNT_FRDIV (0x3f << 5) | 1115 | #define SSI_SACNT_FRDIV (0x3f << 5) |
1132 | #define SSI_SACNT_FRDIVw(x) (((x) << 5) & SSI_SACNT_FRDIV) | 1116 | #define SSI_SACNT_FRDIV_POS (5) |
1133 | #define SSI_SACNT_FRDIVr(x) (((x) & SSI_SACNT_FRDIV) >> 5) | ||
1134 | 1117 | ||
1135 | #define SSI_SACNT_WR (0x1 << 4) | 1118 | #define SSI_SACNT_WR (0x1 << 4) |
1136 | #define SSI_SACNT_RD (0x1 << 3) | 1119 | #define SSI_SACNT_RD (0x1 << 3) |
@@ -1156,8 +1139,7 @@ | |||
1156 | #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04)) | 1139 | #define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04)) |
1157 | 1140 | ||
1158 | #define WDOG_WCR_WT (0xff << 8) | 1141 | #define WDOG_WCR_WT (0xff << 8) |
1159 | #define WDOG_WCR_WTw(x) (((x) << 8) & WDOG_WCR_WT) | 1142 | #define WDOG_WCR_WT_POS (8) |
1160 | #define WDOG_WCR_WTr(x) (((x) & WDOG_WCR_WT) >> 8) | ||
1161 | 1143 | ||
1162 | #define WDOG_WCR_WOE (0x1 << 6) | 1144 | #define WDOG_WCR_WOE (0x1 << 6) |
1163 | #define WDOG_WCR_WDA (0x1 << 5) | 1145 | #define WDOG_WCR_WDA (0x1 << 5) |
@@ -1245,45 +1227,45 @@ | |||
1245 | /* | 1227 | /* |
1246 | * IRQ Controller Register Definitions. | 1228 | * IRQ Controller Register Definitions. |
1247 | */ | 1229 | */ |
1248 | #define AVIC_BASE_ADDR 0x68000000 | 1230 | #define AVIC_BASE_ADDR 0x68000000 |
1249 | #define INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00)) | 1231 | #define AVIC_INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00)) |
1250 | #define NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04)) | 1232 | #define AVIC_NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04)) |
1251 | #define INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08)) | 1233 | #define AVIC_INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08)) |
1252 | #define INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C)) | 1234 | #define AVIC_INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C)) |
1253 | #define INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10)) | 1235 | #define AVIC_INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10)) |
1254 | #define INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14)) | 1236 | #define AVIC_INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14)) |
1255 | #define INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18)) | 1237 | #define AVIC_INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18)) |
1256 | #define INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C)) | 1238 | #define AVIC_INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C)) |
1257 | #define NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n]) | 1239 | #define AVIC_NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n]) |
1258 | #define NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20)) | 1240 | #define AVIC_NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20)) |
1259 | #define NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24)) | 1241 | #define AVIC_NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24)) |
1260 | #define NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28)) | 1242 | #define AVIC_NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28)) |
1261 | #define NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C)) | 1243 | #define AVIC_NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C)) |
1262 | #define NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30)) | 1244 | #define AVIC_NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30)) |
1263 | #define NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34)) | 1245 | #define AVIC_NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34)) |
1264 | #define NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38)) | 1246 | #define AVIC_NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38)) |
1265 | #define NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C)) | 1247 | #define AVIC_NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C)) |
1266 | #define NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40)) | 1248 | #define AVIC_NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40)) |
1267 | #define FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44)) | 1249 | #define AVIC_FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44)) |
1268 | #define INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48)) | 1250 | #define AVIC_INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48)) |
1269 | #define INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C)) | 1251 | #define AVIC_INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C)) |
1270 | #define INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50)) | 1252 | #define AVIC_INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50)) |
1271 | #define INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54)) | 1253 | #define AVIC_INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54)) |
1272 | #define NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58)) | 1254 | #define AVIC_NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58)) |
1273 | #define NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C)) | 1255 | #define AVIC_NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C)) |
1274 | #define FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60)) | 1256 | #define AVIC_FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60)) |
1275 | #define FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64)) | 1257 | #define AVIC_FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64)) |
1276 | #define VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100) | 1258 | #define AVIC_VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100) |
1277 | #define VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n]) | 1259 | #define AVIC_VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n]) |
1278 | 1260 | ||
1279 | /* The vectors go all the way up to 63. 4 bytes for each */ | 1261 | /* The vectors go all the way up to 63. 4 bytes for each */ |
1280 | #define INTCNTL_ABFLAG (1 << 25) | 1262 | #define AVIC_INTCNTL_ABFLAG (1 << 25) |
1281 | #define INTCNTL_ABFEN (1 << 24) | 1263 | #define AVIC_INTCNTL_ABFEN (1 << 24) |
1282 | #define INTCNTL_NIDIS (1 << 22) | 1264 | #define AVIC_INTCNTL_NIDIS (1 << 22) |
1283 | #define INTCNTL_FIDIS (1 << 21) | 1265 | #define AVIC_INTCNTL_FIDIS (1 << 21) |
1284 | #define INTCNTL_NIAD (1 << 20) | 1266 | #define AVIC_INTCNTL_NIAD (1 << 20) |
1285 | #define INTCNTL_FIAD (1 << 19) | 1267 | #define AVIC_INTCNTL_FIAD (1 << 19) |
1286 | #define INTCNTL_NM (1 << 18) | 1268 | #define AVIC_INTCNTL_NM (1 << 18) |
1287 | 1269 | ||
1288 | /* L210 */ | 1270 | /* L210 */ |
1289 | #define L2CC_BASE_ADDR 0x30000000 | 1271 | #define L2CC_BASE_ADDR 0x30000000 |
@@ -1299,224 +1281,167 @@ | |||
1299 | #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG)) | 1281 | #define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG)) |
1300 | 1282 | ||
1301 | /* CCM */ | 1283 | /* CCM */ |
1302 | #define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00)) | 1284 | #define CCM_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00)) |
1303 | #define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04)) | 1285 | #define CCM_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04)) |
1304 | #define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08)) | 1286 | #define CCM_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08)) |
1305 | #define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C)) | 1287 | #define CCM_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C)) |
1306 | #define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10)) | 1288 | #define CCM_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10)) |
1307 | #define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14)) | 1289 | #define CCM_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14)) |
1308 | #define CLKCTL_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18)) | 1290 | #define CCM_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18)) |
1309 | #define CLKCTL_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C)) | 1291 | #define CCM_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C)) |
1310 | #define CLKCTL_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20)) | 1292 | #define CCM_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20)) |
1311 | #define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24)) | 1293 | #define CCM_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24)) |
1312 | #define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28)) | 1294 | #define CCM_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28)) |
1313 | #define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C)) | 1295 | #define CCM_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C)) |
1314 | #define CLKCTL_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30)) | 1296 | #define CCM_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30)) |
1315 | #define CLKCTL_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34)) | 1297 | #define CCM_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34)) |
1316 | #define CLKCTL_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38)) | 1298 | #define CCM_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38)) |
1317 | #define CLKCTL_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C)) | 1299 | #define CCM_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C)) |
1318 | #define CLKCTL_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40)) | 1300 | #define CCM_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40)) |
1319 | #define CLKCTL_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44)) | 1301 | #define CCM_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44)) |
1320 | #define CLKCTL_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48)) | 1302 | #define CCM_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48)) |
1321 | #define CLKCTL_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C)) | 1303 | #define CCM_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C)) |
1322 | #define CLKCTL_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50)) | 1304 | #define CCM_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50)) |
1323 | #define CLKCTL_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54)) | 1305 | #define CCM_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54)) |
1324 | #define CLKCTL_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58)) | 1306 | #define CCM_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58)) |
1325 | #define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C)) | 1307 | #define CCM_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C)) |
1326 | #define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) | 1308 | #define CCM_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60)) |
1327 | #define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) | 1309 | #define CCM_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64)) |
1328 | 1310 | ||
1329 | /* CCMR */ | 1311 | /* CCMR */ |
1330 | #define CCMR_L2PG (0x1 << 29) | 1312 | #define CCM_CCMR_L2PG (0x1 << 29) |
1331 | #define CCMR_VSTBY (0x1 << 28) | 1313 | #define CCM_CCMR_VSTBY (0x1 << 28) |
1332 | #define CCMR_WBEN (0x1 << 27) | 1314 | #define CCM_CCMR_WBEN (0x1 << 27) |
1333 | #define CCMR_FPMF (0x1 << 26) | 1315 | #define CCM_CCMR_FPMF (0x1 << 26) |
1334 | #define CCMR_CSCS (0x1 << 25) | 1316 | #define CCM_CCMR_CSCS (0x1 << 25) |
1335 | #define CCMR_PERCS (0x1 << 24) | 1317 | #define CCM_CCMR_PERCS (0x1 << 24) |
1336 | 1318 | ||
1337 | #define CCMR_SSI2S (0x3 << 21) | 1319 | #define CCM_CCMR_SSI2S (0x3 << 21) |
1338 | #define CCMR_SSI2S_MCU_CLK (0x0 << 21) | 1320 | #define CCM_CCMR_SSI2S_MCU_CLK (0x0 << 21) |
1339 | #define CCMR_SSI2S_USB_CLK (0x1 << 21) | 1321 | #define CCM_CCMR_SSI2S_USB_CLK (0x1 << 21) |
1340 | #define CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */ | 1322 | #define CCM_CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */ |
1341 | 1323 | ||
1342 | #define CCMR_SSI1S (0x3 << 18) | 1324 | #define CCM_CCMR_SSI1S (0x3 << 18) |
1343 | #define CCMR_SSI1S_MCU_CLK (0x0 << 18) | 1325 | #define CCM_CCMR_SSI1S_MCU_CLK (0x0 << 18) |
1344 | #define CCMR_SSI1S_USB_CLK (0x1 << 18) | 1326 | #define CCM_CCMR_SSI1S_USB_CLK (0x1 << 18) |
1345 | #define CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */ | 1327 | #define CCM_CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */ |
1346 | 1328 | ||
1347 | #define CCMR_RAMW (0x3 << 16) | 1329 | #define CCM_CCMR_RAMW (0x3 << 16) |
1348 | #define CCMR_RAMW_0ARM_0ALTMS (0x0 << 16) | 1330 | #define CCM_CCMR_RAMW_0ARM_0ALTMS (0x0 << 16) |
1349 | #define CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */ | 1331 | #define CCM_CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */ |
1350 | #define CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */ | 1332 | #define CCM_CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */ |
1351 | #define CCMR_RAMW_1ARM_1ALTMS (0x3 << 16) | 1333 | #define CCM_CCMR_RAMW_1ARM_1ALTMS (0x3 << 16) |
1352 | 1334 | ||
1353 | #define CCMR_LPM (0x3 << 14) | 1335 | #define CCM_CCMR_LPM (0x3 << 14) |
1354 | #define CCMR_LPM_WAIT_MODE (0x0 << 14) | 1336 | #define CCM_CCMR_LPM_WAIT_MODE (0x0 << 14) |
1355 | #define CCMR_LPM_DOZE_MODE (0x1 << 14) | 1337 | #define CCM_CCMR_LPM_DOZE_MODE (0x1 << 14) |
1356 | #define CCMR_LPM_SRM (0x2 << 14) /* State retention mode */ | 1338 | #define CCM_CCMR_LPM_SRM (0x2 << 14) /* State retention mode */ |
1357 | #define CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */ | 1339 | #define CCM_CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */ |
1358 | 1340 | ||
1359 | #define CCMR_FIRS (0x3 << 11) | 1341 | #define CCM_CCMR_FIRS (0x3 << 11) |
1360 | #define CCMR_FIRS_MCU_CLK (0x0 << 11) | 1342 | #define CCM_CCMR_FIRS_MCU_CLK (0x0 << 11) |
1361 | #define CCMR_FIRS_USB_CLK (0x1 << 11) | 1343 | #define CCM_CCMR_FIRS_USB_CLK (0x1 << 11) |
1362 | #define CCMR_FIRS_SERIAL_CLK (0x2 << 11) | 1344 | #define CCM_CCMR_FIRS_SERIAL_CLK (0x2 << 11) |
1363 | 1345 | ||
1364 | #define CCMR_WAMO (0x1 << 10) | 1346 | #define CCM_CCMR_WAMO (0x1 << 10) |
1365 | #define CCMR_UPE (0x1 << 9) | 1347 | #define CCM_CCMR_UPE (0x1 << 9) |
1366 | #define CCMR_SPE (0x1 << 8) | 1348 | #define CCM_CCMR_SPE (0x1 << 8) |
1367 | #define CCMR_MDS (0x1 << 7) | 1349 | #define CCM_CCMR_MDS (0x1 << 7) |
1368 | 1350 | ||
1369 | #define CCMR_ROMW (0x3 << 5) | 1351 | #define CCM_CCMR_ROMW (0x3 << 5) |
1370 | #define CCMR_ROMW_0ARM_0ALTMS (0x0 << 5) | 1352 | #define CCM_CCMR_ROMW_0ARM_0ALTMS (0x0 << 5) |
1371 | #define CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */ | 1353 | #define CCM_CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */ |
1372 | #define CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */ | 1354 | #define CCM_CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */ |
1373 | #define CCMR_ROMW_1ARM_1ALTMS (0x3 << 5) | 1355 | #define CCM_CCMR_ROMW_1ARM_1ALTMS (0x3 << 5) |
1374 | 1356 | ||
1375 | #define CCMR_SBYCS (0x1 << 4) | 1357 | #define CCM_CCMR_SBYCS (0x1 << 4) |
1376 | #define CCMR_MPE (0x1 << 3) | 1358 | #define CCM_CCMR_MPE (0x1 << 3) |
1377 | 1359 | ||
1378 | #define CCMR_PRCS (0x3 << 1) | 1360 | #define CCM_CCMR_PRCS (0x3 << 1) |
1379 | #define CCMR_PRCS_FPM (0x1 << 1) | 1361 | #define CCM_CCMR_PRCS_FPM (0x1 << 1) |
1380 | #define CCMR_PRCS_CKIH (0x2 << 1) | 1362 | #define CCM_CCMR_PRCS_CKIH (0x2 << 1) |
1381 | 1363 | ||
1382 | #define CCMR_FPME (0x1 << 0) | 1364 | #define CCM_CCMR_FPME (0x1 << 0) |
1383 | 1365 | ||
1384 | /* PDR0 */ | 1366 | /* PDR0 */ |
1385 | #define PDR0_CSI_PODF (0x1ff << 23) | 1367 | #define CCM_PDR0_CSI_PODF (0x1ff << 23) |
1386 | #define PDR0_CSI_PODFw(x) (((x) << 23) & PDR0_CSI_PODF) | 1368 | #define CCM_PDR0_CSI_PODF_POS (23) |
1387 | #define PDR0_CSI_PODFr(x) (((x) & PDR0_CSI_PODF) >> 23) | ||
1388 | 1369 | ||
1389 | #define PDR0_PER_PODF (0x1f << 16) | 1370 | #define CCM_PDR0_PER_PODF (0x1f << 16) |
1390 | #define PDR0_PER_PODFw(x) (((x) << 16) & PDR0_PER_PODF) | 1371 | #define CCM_PDR0_PER_PODF_POS (16) |
1391 | #define PDR0_PER_PODFr(x) (((x) & PDR0_PER_PODF) >> 16) | ||
1392 | 1372 | ||
1393 | #define PDR0_HSP_PODF (0x7 << 11) | 1373 | #define CCM_PDR0_HSP_PODF (0x7 << 11) |
1394 | #define PDR0_HSP_PODFw(x) (((x) << 11) & PDR0_HSP_PODF) | 1374 | #define CCM_PDR0_HSP_PODF_POS (11) |
1395 | #define PDR0_HSP_PODFr(x) (((x) & PDR0_HSP_PODF) >> 11) | ||
1396 | 1375 | ||
1397 | #define PDR0_NFC_PODF (0x7 << 8) | 1376 | #define CCM_PDR0_NFC_PODF (0x7 << 8) |
1398 | #define PDR0_NFC_PODFw(x) (((x) << 8) & PDR0_NFC_PODF) | 1377 | #define CCM_PDR0_NFC_PODF_POS (8) |
1399 | #define PDR0_NFC_PODFr(x) (((x) & PDR0_NFC_PODF) >> 8) | ||
1400 | 1378 | ||
1401 | #define PDR0_IPG_PODF (0x3 << 6) | 1379 | #define CCM_PDR0_IPG_PODF (0x3 << 6) |
1402 | #define PDR0_IPG_PODFw(x) (((x) << 6) & PDR0_IPG_PODF) | 1380 | #define CCM_PDR0_IPG_PODF_POS (6) |
1403 | #define PDR0_IPG_PODFr(x) (((x) & PDR0_IPG_PODF) >> 6) | ||
1404 | 1381 | ||
1405 | #define PDR0_MAX_PODF (0x7 << 3) | 1382 | #define CCM_PDR0_MAX_PODF (0x7 << 3) |
1406 | #define PDR0_MAX_PODFw(x) (((x) << 3) & PDR0_MAX_PODF) | 1383 | #define CCM_PDR0_MAX_PODF_POS (3) |
1407 | #define PDR0_MAX_PODFr(x) (((x) & PDR0_MAX_PODF) >> 3) | ||
1408 | 1384 | ||
1409 | #define PDR0_MCU_PODF (0x7 << 0) | 1385 | #define CCM_PDR0_MCU_PODF (0x7 << 0) |
1410 | #define PDR0_MCU_PODFw(x) (((x) << 0) & PDR0_MCU_PODF) | 1386 | #define CCM_PDR0_MCU_PODF_POS (0) |
1411 | #define PDR0_MCU_PODFr(x) (((x) & PDR0_MCU_PODF) >> 0) | ||
1412 | 1387 | ||
1413 | /* PDR1 */ | 1388 | /* PDR1 */ |
1414 | #define PDR1_USB_PRDF (0x3 << 30) | 1389 | #define CCM_PDR1_USB_PRDF (0x3 << 30) |
1415 | #define PDR1_USB_PRDFw(x) (((x) << 30) & PDR1_USB_PRDF) | 1390 | #define CCM_PDR1_USB_PRDF_POS (30) |
1416 | #define PDR1_USB_PRDFr(x) (((x) & PDR1_USB_PRDF) >> 30) | 1391 | |
1417 | 1392 | #define CCM_PDR1_USB_PODF (0x7 << 27) | |
1418 | #define PDR1_USB_PODF (0x7 << 27) | 1393 | #define CCM_PDR1_USB_PODF_POS (27) |
1419 | #define PDR1_USB_PODFw(x) (((x) << 27) & PDR1_USB_PODF) | 1394 | |
1420 | #define PDR1_USB_PODFr(x) (((x) & PDR1_USB_PODF) >> 27) | 1395 | #define CCM_PDR1_FIRI_PRE_PODF (0x7 << 24) |
1421 | 1396 | #define CCM_PDR1_FIRI_PRE_PODF_POS (24) | |
1422 | #define PDR1_FIRI_PRE_PODF (0x7 << 24) | 1397 | |
1423 | #define PDR1_FIRI_PRE_PODFw(x) (((x) << 24) & PDR1_FIRI_PRE_PODF) | 1398 | #define CCM_PDR1_FIRI_PODF (0x3f << 18) |
1424 | #define PDR1_FIRI_PRE_PODFr(x) (((x) & PDR1_FIRI_PRE_PODF) >> 24) | 1399 | #define CCM_PDR1_FIRI_PODF_POS (18) |
1425 | 1400 | ||
1426 | #define PDR1_FIRI_PODF (0x3f << 18) | 1401 | #define CCM_PDR1_SSI2_PRE_PODF (0x7 << 15) |
1427 | #define PDR1_FIRI_PODFw(x) (((x) << 18) & PDR1_FIRI_PODF) | 1402 | #define CCM_PDR1_SSI2_PRE_PODF_POS (15) |
1428 | #define PDR1_FIRI_PODFr(x) (((x) & PDR1_FIRI_PODF) >> 18) | 1403 | |
1429 | 1404 | #define CCM_PDR1_SSI2_PODF (0x3f << 9) | |
1430 | #define PDR1_SSI2_PRE_PODF (0x7 << 15) | 1405 | #define CCM_PDR1_SSI2_PODF_POS (9) |
1431 | #define PDR1_SSI2_PRE_PODFw(x) (((x) << 15) & PDR1_SSI2_PRE_PODF) | 1406 | |
1432 | #define PDR1_SSI2_PRE_PODFr(x) (((x) & PDR1_SSI2_PRE_PODF) >> 15) | 1407 | #define CCM_PDR1_SSI1_PRE_PODF (0x7 << 6) |
1433 | 1408 | #define CCM_PDR1_SSI1_PRE_PODF_POS (6) | |
1434 | #define PDR1_SSI2_PODF (0x3f << 9) | 1409 | |
1435 | #define PDR1_SSI2_PODFw(x) (((x) << 9) & PDR1_SSI2_PODF) | 1410 | #define CCM_PDR1_SSI1_PODF (0x3f << 0) |
1436 | #define PDR1_SSI2_PODFr(x) (((x) & PDR1_SSI2_PODF) >> 9) | 1411 | #define CCM_PDR1_SSI1_PODF_POS (0) |
1437 | 1412 | ||
1438 | #define PDR1_SSI1_PRE_PODF (0x7 << 6) | 1413 | #define CCM_WIMR0_GPIO3 (1 << 0) |
1439 | #define PDR1_SSI1_PRE_PODFw(x) (((x) << 6) & PDR1_SSI1_PRE_PODF) | 1414 | #define CCM_WIMR0_GPIO2 (1 << 1) |
1440 | #define PDR1_SSI1_PRE_PODFr(x) (((x) & PDR1_SSI1_PRE_PODF) >> 6) | 1415 | #define CCM_WIMR0_GPIO1 (1 << 2) |
1441 | 1416 | #define CCM_WIMR0_PCMCIA (1 << 3) | |
1442 | #define PDR1_SSI1_PODF (0x3f << 0) | 1417 | #define CCM_WIMR0_WDT (1 << 4) |
1443 | #define PDR1_SSI1_PODFw(x) (((x) << 0) & PDR1_SSI1_PODF) | 1418 | #define CCM_WIMR0_USB_OTG (1 << 5) |
1444 | #define PDR1_SSI1_PODFr(x) (((x) & PDR1_SSI1_PODF) >> 0) | 1419 | #define CCM_WIMR0_IPI_INT_UH2 (1 << 6) |
1445 | 1420 | #define CCM_WIMR0_IPI_INT_UH1 (1 << 7) | |
1446 | #define CGR0_SD_MMC1(cg) ((cg) << 0*2) | 1421 | #define CCM_WIMR0_IPI_INT_UART5_ANDED (1 << 8) |
1447 | #define CGR0_SD_MMC2(cg) ((cg) << 1*2) | 1422 | #define CCM_WIMR0_IPI_INT_UART4_ANDED (1 << 9) |
1448 | #define CGR0_GPT(cg) ((cg) << 2*2) | 1423 | #define CCM_WIMR0_IPI_INT_UART3_ANDED (1 << 10) |
1449 | #define CGR0_EPIT1(cg) ((cg) << 3*2) | 1424 | #define CCM_WIMR0_IPI_INT_UART2_ANDED (1 << 11) |
1450 | #define CGR0_EPIT2(cg) ((cg) << 4*2) | 1425 | #define CCM_WIMR0_IPI_INT_UART1_ANDED (1 << 12) |
1451 | #define CGR0_IIM(cg) ((cg) << 5*2) | 1426 | #define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ (1 << 13) |
1452 | #define CGR0_ATA(cg) ((cg) << 6*2) | 1427 | #define CCM_WIMR0_IPI_INT_SDHC2 (1 << 14) |
1453 | #define CGR0_SDMA(cg) ((cg) << 7*2) | 1428 | #define CCM_WIMR0_IPI_INT_SDHC1 (1 << 15) |
1454 | #define CGR0_CSPI3(cg) ((cg) << 8*2) | 1429 | #define CCM_WIMR0_IPI_INT_RTC (1 << 16) |
1455 | #define CGR0_RNG(cg) ((cg) << 9*2) | 1430 | #define CCM_WIMR0_IPI_INT_PWM (1 << 17) |
1456 | #define CGR0_UART1(cg) ((cg) << 10*2) | 1431 | #define CCM_WIMR0_IPI_INT_KPP (1 << 18) |
1457 | #define CGR0_UART2(cg) ((cg) << 11*2) | 1432 | #define CCM_WIMR0_IPI_INT_IIM (1 << 19) |
1458 | #define CGR0_SSI1(cg) ((cg) << 12*2) | 1433 | #define CCM_WIMR0_IPI_INT_GPT (1 << 20) |
1459 | #define CGR0_I2C1(cg) ((cg) << 13*2) | 1434 | #define CCM_WIMR0_IPI_INT_FIR (1 << 21) |
1460 | #define CGR0_I2C2(cg) ((cg) << 14*2) | 1435 | #define CCM_WIMR0_IPI_INT_EPIT2 (1 << 22) |
1461 | #define CGR0_I2C3(cg) ((cg) << 15*2) | 1436 | #define CCM_WIMR0_IPI_INT_EPIT1 (1 << 23) |
1462 | 1437 | #define CCM_WIMR0_IPI_INT_CSPI2 (1 << 24) | |
1463 | #define CGR1_HANTRO(cg) ((cg) << 0*2) | 1438 | #define CCM_WIMR0_IPI_INT_CSPI1 (1 << 25) |
1464 | #define CGR1_MEMSTICK1(cg) ((cg) << 1*2) | 1439 | #define CCM_WIMR0_IPI_INT_POWER_FAIL (1 << 26) |
1465 | #define CGR1_MEMSTICK2(cg) ((cg) << 2*2) | 1440 | #define CCM_WIMR0_IPI_INT_CSPI3 (1 << 27) |
1466 | #define CGR1_CSI(cg) ((cg) << 3*2) | 1441 | #define CCM_WIMR0_RESERVED28 (1 << 28) |
1467 | #define CGR1_RTC(cg) ((cg) << 4*2) | 1442 | #define CCM_WIMR0_RESERVED29 (1 << 29) |
1468 | #define CGR1_WDOG(cg) ((cg) << 5*2) | 1443 | #define CCM_WIMR0_RESERVED30 (1 << 30) |
1469 | #define CGR1_PWM(cg) ((cg) << 6*2) | 1444 | #define CCM_WIMR0_RESERVED31 (1 << 31) |
1470 | #define CGR1_SIM(cg) ((cg) << 7*2) | ||
1471 | #define CGR1_ECT(cg) ((cg) << 8*2) | ||
1472 | #define CGR1_USBOTG(cg) ((cg) << 9*2) | ||
1473 | #define CGR1_KPP(cg) ((cg) << 10*2) | ||
1474 | #define CGR1_IPU(cg) ((cg) << 11*2) | ||
1475 | #define CGR1_UART3(cg) ((cg) << 12*2) | ||
1476 | #define CGR1_UART4(cg) ((cg) << 13*2) | ||
1477 | #define CGR1_UART5(cg) ((cg) << 14*2) | ||
1478 | #define CGR1_1_WIRE(cg) ((cg) << 15*2) | ||
1479 | |||
1480 | #define CGR2_SSI2(cg) ((cg) << 0*2) | ||
1481 | #define CGR2_CSPI1(cg) ((cg) << 1*2) | ||
1482 | #define CGR2_CSPI2(cg) ((cg) << 2*2) | ||
1483 | #define CGR2_GACC(cg) ((cg) << 3*2) | ||
1484 | #define CGR2_EMI(cg) ((cg) << 4*2) | ||
1485 | #define CGR2_RTIC(cg) ((cg) << 5*2) | ||
1486 | #define CGR2_FIR(cg) ((cg) << 6*2) | ||
1487 | |||
1488 | #define WIM_GPIO3 (1 << 0) | ||
1489 | #define WIM_GPIO2 (1 << 1) | ||
1490 | #define WIM_GPIO1 (1 << 2) | ||
1491 | #define WIM_PCMCIA (1 << 3) | ||
1492 | #define WIM_WDT (1 << 4) | ||
1493 | #define WIM_USB_OTG (1 << 5) | ||
1494 | #define WIM_IPI_INT_UH2 (1 << 6) | ||
1495 | #define WIM_IPI_INT_UH1 (1 << 7) | ||
1496 | #define WIM_IPI_INT_UART5_ANDED (1 << 8) | ||
1497 | #define WIM_IPI_INT_UART4_ANDED (1 << 9) | ||
1498 | #define WIM_IPI_INT_UART3_ANDED (1 << 10) | ||
1499 | #define WIM_IPI_INT_UART2_ANDED (1 << 11) | ||
1500 | #define WIM_IPI_INT_UART1_ANDED (1 << 12) | ||
1501 | #define WIM_IPI_INT_SIM_DATA_IRQ (1 << 13) | ||
1502 | #define WIM_IPI_INT_SDHC2 (1 << 14) | ||
1503 | #define WIM_IPI_INT_SDHC1 (1 << 15) | ||
1504 | #define WIM_IPI_INT_RTC (1 << 16) | ||
1505 | #define WIM_IPI_INT_PWM (1 << 17) | ||
1506 | #define WIM_IPI_INT_KPP (1 << 18) | ||
1507 | #define WIM_IPI_INT_IIM (1 << 19) | ||
1508 | #define WIM_IPI_INT_GPT (1 << 20) | ||
1509 | #define WIM_IPI_INT_FIR (1 << 21) | ||
1510 | #define WIM_IPI_INT_EPIT2 (1 << 22) | ||
1511 | #define WIM_IPI_INT_EPIT1 (1 << 23) | ||
1512 | #define WIM_IPI_INT_CSPI2 (1 << 24) | ||
1513 | #define WIM_IPI_INT_CSPI1 (1 << 25) | ||
1514 | #define WIM_IPI_INT_POWER_FAIL (1 << 26) | ||
1515 | #define WIM_IPI_INT_CSPI3 (1 << 27) | ||
1516 | #define WIM_RESERVED28 (1 << 28) | ||
1517 | #define WIM_RESERVED29 (1 << 29) | ||
1518 | #define WIM_RESERVED30 (1 << 30) | ||
1519 | #define WIM_RESERVED31 (1 << 31) | ||
1520 | 1445 | ||
1521 | /* WEIM - CS0 */ | 1446 | /* WEIM - CS0 */ |
1522 | #define CSCRU 0x00 | 1447 | #define CSCRU 0x00 |
diff --git a/firmware/export/mc13783.h b/firmware/export/mc13783.h index d8b719be03..09fb1f1fc4 100644 --- a/firmware/export/mc13783.h +++ b/firmware/export/mc13783.h | |||
@@ -246,29 +246,25 @@ enum mc13783_regs_enum | |||
246 | 246 | ||
247 | /* IDENTIFICATION (7) */ | 247 | /* IDENTIFICATION (7) */ |
248 | #define MC13783_REVISION (0x1f << 0) | 248 | #define MC13783_REVISION (0x1f << 0) |
249 | #define MC13783_REVISIONr(x) (((x) & MC13783_REVISION) >> 0) | 249 | #define MC13783_REVISION_POS (0) |
250 | #define MC13783_ICID (0x7 << 6) | 250 | #define MC13783_ICID (0x7 << 6) |
251 | #define MC13783_ICIDr(x) (((x) & MC13783_ICID) >> 6) | 251 | #define MC13783_ICID_POS (6) |
252 | #define MC13783_FIN (0x3 << 9) | 252 | #define MC13783_FIN (0x3 << 9) |
253 | #define MC13783_FINr(x) (((x) & MC13783_FIN) >> 9)) | 253 | #define MC13783_FIN_POS (9) |
254 | #define MC13783_FAB (0x3 << 12) | 254 | #define MC13783_FAB (0x3 << 12) |
255 | #define MC13783_FABr(x) (((x) & MC13783_FAB) >> 12)) | 255 | #define MC13783_FAB_POS (12) |
256 | 256 | ||
257 | /* SEMAPHORE (8) */ | 257 | /* SEMAPHORE (8) */ |
258 | #define MC13783_SEMCTRLA (0x1 << 0) | 258 | #define MC13783_SEMCTRLA (0x1 << 0) |
259 | #define MC13783_SEMCTRLB (0x1 << 2) | 259 | #define MC13783_SEMCTRLB (0x1 << 2) |
260 | #define MC13783_SEMWRTA (0xf << 4) | 260 | #define MC13783_SEMWRTA (0xf << 4) |
261 | #define MC13783_SEMWRTAw(x) (((x) << 4) & MC13783_SEMWRTA) | 261 | #define MC13783_SEMWRTA_POS (4) |
262 | #define MC13783_SEMWRTAr(x) (((x) & MC13783_SEMWRTA) >> 4) | ||
263 | #define MC13783_SEMWRTB (0x3f << 8) | 262 | #define MC13783_SEMWRTB (0x3f << 8) |
264 | #define MC13783_SEMWRTBw(x) (((x) << 8) & MC13783_SEMWRTB) | 263 | #define MC13783_SEMWRTB_POS (8) |
265 | #define MC13783_SEMWRTBr(x) (((x) & MC13783_SEMWRTB) >> 8) | ||
266 | #define MC13783_SEMRDA (0xf << 14) | 264 | #define MC13783_SEMRDA (0xf << 14) |
267 | #define MC13783_SEMRDAw(x) (((x) << 14) & MC13783_SEMRDA) | 265 | #define MC13783_SEMRDA_POS (14) |
268 | #define MC13783_SEMRDAr(x) (((x) & MC13783_SEMRDA) >> 14) | ||
269 | #define MC13783_SEMRDB (0x3f << 18) | 266 | #define MC13783_SEMRDB (0x3f << 18) |
270 | #define MC13783_SEMRDBw(x) (((x) << 18) & MC13783_SEMRDB) | 267 | #define MC13783_SEMRDB_POS (18) |
271 | #define MC13783_SEMRDBr(x) (((x) & MC13783_SEMRDB) >> 18) | ||
272 | 268 | ||
273 | /* ARBITRATION_PERIPHERAL_AUDIO (9) */ | 269 | /* ARBITRATION_PERIPHERAL_AUDIO (9) */ |
274 | #define MC13783_AUDIOTXSEL (0x3 << 0) | 270 | #define MC13783_AUDIOTXSEL (0x3 << 0) |
@@ -418,20 +414,16 @@ enum mc13783_regs_enum | |||
418 | #define MC13783_COINCHEN (0x1 << 23) | 414 | #define MC13783_COINCHEN (0x1 << 23) |
419 | 415 | ||
420 | /* POWER_CONTROL1 (14) */ | 416 | /* POWER_CONTROL1 (14) */ |
421 | #define MC13783_PCT (0xff << 0) | ||
422 | /* Up to 8 seconds */ | 417 | /* Up to 8 seconds */ |
423 | #define MC13783_PCTw(x) (((x) << 0) & MC13783_PCT) | 418 | #define MC13783_PCT (0xff << 0) |
424 | #define MC13783_PCTr(x) (((x) & MC13783_PCT) >> 0) | 419 | #define MC13783_PCT_POS (0) |
425 | #define MC13783_PCCOUNT (0xf << 8) | 420 | #define MC13783_PCCOUNT (0xf << 8) |
426 | #define MC13783_PCCOUNTw(x) (((x) << 8) & MC13783_PCCOUNT) | 421 | #define MC13783_PCCOUNT_POS (8) |
427 | #define MC13783_PCCOUNTr(x) (((x) & MC13783_PCCOUNT) >> 8) | ||
428 | #define MC13783_PCMAXCNT (0xf << 12) | 422 | #define MC13783_PCMAXCNT (0xf << 12) |
429 | #define MC13783_PCMAXCNTw(x) (((x) << 12) & MC13783_PCMAXCNT) | 423 | #define MC13783_PCMAXCNT_POS (12) |
430 | #define MC13783_PCMAXCNTr(x) (((x) & MC13783_PCMAXCNT) >> 12) | ||
431 | #define MC13783_MEMTMR (0xf << 16) | ||
432 | /* Up to 8 minutes with MEMALLON=0, <> 0 + MEMALLON=1: infinite */ | 424 | /* Up to 8 minutes with MEMALLON=0, <> 0 + MEMALLON=1: infinite */ |
433 | #define MC13783_MEMTMRw(x) (((x) << 16) & MC13783_MEMTMR) | 425 | #define MC13783_MEMTMR (0xf << 16) |
434 | #define MC13783_MEMTMRr(x) (((x) & MC13783_MEMTMR) >> 16) | 426 | #define MC13783_MEMTMR_POS (16) |
435 | #define MC13783_MEMALLON (0x1 << 20) | 427 | #define MC13783_MEMALLON (0x1 << 20) |
436 | 428 | ||
437 | /* POWER_CONTROL2 (15) */ | 429 | /* POWER_CONTROL2 (15) */ |
@@ -501,47 +493,35 @@ enum mc13783_regs_enum | |||
501 | 493 | ||
502 | /* SWITCHERS0 (24) */ | 494 | /* SWITCHERS0 (24) */ |
503 | #define MC13783_SW1A (0x3f << 0) | 495 | #define MC13783_SW1A (0x3f << 0) |
504 | #define MC13783_SW1Aw(x) (((x) << 0) & MC13783_SW1A) | 496 | #define MC13783_SW1A_POS (0) |
505 | #define MC13783_SW1Ar(x) (((x) & MC13783_SW1A) >> 0) | ||
506 | #define MC13783_SW1ADVS (0x3f << 6) | 497 | #define MC13783_SW1ADVS (0x3f << 6) |
507 | #define MC13783_SW1ADVSw(x) (((x) << 6) & MC13783_SW1ADVS) | 498 | #define MC13783_SW1ADVS_POS (6) |
508 | #define MC13783_SW1ADVSr(x) (((x) & MC13783_SW1ADVS) >> 6) | ||
509 | #define MC13783_SW1ASTBY (0x3f << 12) | 499 | #define MC13783_SW1ASTBY (0x3f << 12) |
510 | #define MC13783_SW1ASTBYw(x) (((x) << 12) & MC13783_SW1ASTBY) | 500 | #define MC13783_SW1ASTBY_POS (12) |
511 | #define MC13783_SW1ASTBYr(x) (((x) & MC13783_SW1ASTBY) >> 12) | ||
512 | 501 | ||
513 | /* SWITCHERS1 (25) */ | 502 | /* SWITCHERS1 (25) */ |
514 | #define MC13783_SW1B (0x3f << 0) | 503 | #define MC13783_SW1B (0x3f << 0) |
515 | #define MC13783_SW1Bw(x) (((x) << 0) & MC13783_SW1B) | 504 | #define MC13783_SW1B_POS (0) |
516 | #define MC13783_SW1Br(x) (((x) & MC13783_SW1B) >> 0) | ||
517 | #define MC13783_SW1BDVS (0x3f << 6) | 505 | #define MC13783_SW1BDVS (0x3f << 6) |
518 | #define MC13783_SW1BDVSw(x) (((x) << 6) & MC13783_SW1BDVS) | 506 | #define MC13783_SW1BDVS_POS (6) |
519 | #define MC13783_SW1BDVSr(x) (((x) & MC13783_SW1BDVS) >> 6) | ||
520 | #define MC13783_SW1BSTBY (0x3f << 12) | 507 | #define MC13783_SW1BSTBY (0x3f << 12) |
521 | #define MC13783_SW1BSTBYw(x) (((x) << 12) & MC13783_SW1BSTBY) | 508 | #define MC13783_SW1BSTBY_POS (12) |
522 | #define MC13783_SW1BSTBYr(x) (((x) & MC13783_SW1BSTBY) >> 12) | ||
523 | 509 | ||
524 | /* SWITCHERS2 (26) */ | 510 | /* SWITCHERS2 (26) */ |
525 | #define MC13783_SW2A (0x3f << 0) | 511 | #define MC13783_SW2A (0x3f << 0) |
526 | #define MC13783_SW2Aw(x) (((x) << 0) & MC13783_SW1A) | 512 | #define MC13783_SW2A_POS (0) |
527 | #define MC13783_SW2Ar(x) (((x) & MC13783_SW1A) >> 0) | ||
528 | #define MC13783_SW2ADVS (0x3f << 6) | 513 | #define MC13783_SW2ADVS (0x3f << 6) |
529 | #define MC13783_SW2ADVSw(x) (((x) << 6) & MC13783_SW2ADVS) | 514 | #define MC13783_SW2ADVS_POS (6) |
530 | #define MC13783_SW2ADVSr(x) (((x) & MC13783_SW2ADVS) >> 6) | ||
531 | #define MC13783_SW2ASTBY (0x3f << 12) | 515 | #define MC13783_SW2ASTBY (0x3f << 12) |
532 | #define MC13783_SW2ASTBYw(x) (((x) << 12) & MC13783_SW2ASTBY) | 516 | #define MC13783_SW2ASTBY_POS (12) |
533 | #define MC13783_SW2ASTBYr(x) (((x) & MC13783_SW2ASTBY) >> 12) | ||
534 | 517 | ||
535 | /* SWITCHERS3 (27) */ | 518 | /* SWITCHERS3 (27) */ |
536 | #define MC13783_SW2B (0x3f << 0) | 519 | #define MC13783_SW2B (0x3f << 0) |
537 | #define MC13783_SW2Bw(x) (((x) << 0) & MC13783_SW2B) | 520 | #define MC13783_SW2B_POS (0) |
538 | #define MC13783_SW2Br(x) (((x) & MC13783_SW2B) >> 0) | ||
539 | #define MC13783_SW2BDVS (0x3f << 6) | 521 | #define MC13783_SW2BDVS (0x3f << 6) |
540 | #define MC13783_SW2BDVSw(x) (((x) << 6) & MC13783_SW2BDVS) | 522 | #define MC13783_SW2BDVS_POS (6) |
541 | #define MC13783_SW2BDVSr(x) (((x) & MC13783_SW2BDVS) >> 6) | ||
542 | #define MC13783_SW2BSTBY (0x3f << 12) | 523 | #define MC13783_SW2BSTBY (0x3f << 12) |
543 | #define MC13783_SW2BSTBYw(x) (((x) << 12) & MC13783_SW2BSTBY) | 524 | #define MC13783_SW2BSTBY_POS (12) |
544 | #define MC13783_SW2BSTBYr(x) (((x) & MC13783_SW2BSTBY) >> 12) | ||
545 | 525 | ||
546 | /* SWITCHERS4 (28) */ | 526 | /* SWITCHERS4 (28) */ |
547 | #define MC13783_SW1AMODE (0x3 << 0) | 527 | #define MC13783_SW1AMODE (0x3 << 0) |
@@ -804,30 +784,26 @@ enum mc13783_regs_enum | |||
804 | 784 | ||
805 | /* AUDIO_RX1 (37) */ | 785 | /* AUDIO_RX1 (37) */ |
806 | #define MC13783_PGARXEN (0x1 << 0) | 786 | #define MC13783_PGARXEN (0x1 << 0) |
807 | #define MC13783_PGARX (0xf << 1) | ||
808 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ | 787 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ |
809 | #define MC13783_PGARXw(x) (((x) << 1) & MC13783_PGARX) | 788 | #define MC13783_PGARX (0xf << 1) |
810 | #define MC13783_PGARXr(x) (((x) & MC13783_PGARX) >> 1) | 789 | #define MC13783_PGARX_POS (1) |
811 | #define MC13783_PGASTEN (0x1 << 5) | 790 | #define MC13783_PGASTEN (0x1 << 5) |
812 | #define MC13783_PGAST (0xf << 6) | ||
813 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ | 791 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ |
814 | #define MC13783_PGASTw(x) (((x) << 6) & MC13783_PGAST) | 792 | #define MC13783_PGAST (0xf << 6) |
815 | #define MC13783_PGASTr(x) (((x) & MC13783_PGAST) >> 6) | 793 | #define MC13783_PGAST_POS (6) |
816 | #define MC13783_ARXINEN (0x1 << 10) | 794 | #define MC13783_ARXINEN (0x1 << 10) |
817 | #define MC13783_ARXIN (0x1 << 11) | 795 | #define MC13783_ARXIN (0x1 << 11) |
818 | #define MC13783_PGARXIN (0xf << 12) | ||
819 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ | 796 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ |
820 | #define MC13783_PGARXINw(x) (((x) << 12) & MC13783_PGARXIN) | 797 | #define MC13783_PGARXIN (0xf << 12) |
821 | #define MC13783_PGARXINr(x) (((x) & MC13783_PGARXIN) >> 12) | 798 | #define MC13783_PGARXIN_POS (12) |
822 | #define MC13783_MONO (0x3 << 16) | 799 | #define MC13783_MONO (0x3 << 16) |
823 | #define MC13783_MONO_LR_INDEPENDENT (0x0 << 16) | 800 | #define MC13783_MONO_LR_INDEPENDENT (0x0 << 16) |
824 | #define MC13783_MONO_ST_OPPOSITE (0x1 << 16) | 801 | #define MC13783_MONO_ST_OPPOSITE (0x1 << 16) |
825 | #define MC13783_MONO_ST_TO_MONO (0x2 << 16) | 802 | #define MC13783_MONO_ST_TO_MONO (0x2 << 16) |
826 | #define MC13783_MONO_MONO_OPPOSITE (0x3 << 16) | 803 | #define MC13783_MONO_MONO_OPPOSITE (0x3 << 16) |
827 | #define MC13783_BAL (0x7 << 18) | ||
828 | /* 000=-21dB...3dB steps...111=0dB: left or right */ | 804 | /* 000=-21dB...3dB steps...111=0dB: left or right */ |
829 | #define MC13783_BALw(x) (((x) << 18) & MC13783_BAL) | 805 | #define MC13783_BAL (0x7 << 18) |
830 | #define MC13783_BALr(x) (((x) & MC13783_BAL) >> 18) | 806 | #define MC13783_BAL_POS (18) |
831 | #define MC13783_BALLR (0x1 << 21) | 807 | #define MC13783_BALLR (0x1 << 21) |
832 | 808 | ||
833 | /* AUDIO_TX (38) */ | 809 | /* AUDIO_TX (38) */ |
@@ -844,14 +820,12 @@ enum mc13783_regs_enum | |||
844 | #define MC13783_ATXINEN (0x1 << 11) | 820 | #define MC13783_ATXINEN (0x1 << 11) |
845 | #define MC13783_ATXOUTEN (0x1 << 12) | 821 | #define MC13783_ATXOUTEN (0x1 << 12) |
846 | #define MC13783_RXINREC (0x1 << 13) | 822 | #define MC13783_RXINREC (0x1 << 13) |
823 | /* 00000=-8dB...01000=0dB...11111=+23dB */ | ||
847 | #define MC13783_PGATXR (0x1f << 14) | 824 | #define MC13783_PGATXR (0x1f << 14) |
825 | #define MC13783_PGATXR_POS (14) | ||
848 | /* 00000=-8dB...01000=0dB...11111=+23dB */ | 826 | /* 00000=-8dB...01000=0dB...11111=+23dB */ |
849 | #define MC13783_PGATXRw(x) (((x) << 14) & MC13783_PGATXR) | ||
850 | #define MC13783_PGATXRr(x) (((x) & MC13783_PGATXR) >> 14) | ||
851 | #define MC13783_PGATXL (0x1f << 19) | 827 | #define MC13783_PGATXL (0x1f << 19) |
852 | /* 00000=-8dB...01000=0dB...11111=+23dB */ | 828 | #define MC13783_PGATXL_POS (19) |
853 | #define MC13783_PGATXLw(x) (((x) << 19) & MC13783_PGATXL) | ||
854 | #define MC13783_PGATXLr(x) (((x) & MC13783_PGATXL) >> 19) | ||
855 | 829 | ||
856 | /* SSI_NETWORK (39) */ | 830 | /* SSI_NETWORK (39) */ |
857 | #define MC13783_CDCTXRXSLOT (0x3 << 2) | 831 | #define MC13783_CDCTXRXSLOT (0x3 << 2) |
@@ -869,10 +843,9 @@ enum mc13783_regs_enum | |||
869 | #define MC13783_CDCRXSECSLOT_TS1 (0x1 << 6) | 843 | #define MC13783_CDCRXSECSLOT_TS1 (0x1 << 6) |
870 | #define MC13783_CDCRXSECSLOT_TS2 (0x2 << 6) | 844 | #define MC13783_CDCRXSECSLOT_TS2 (0x2 << 6) |
871 | #define MC13783_CDCRXSECSLOT_TS3 (0x3 << 6) | 845 | #define MC13783_CDCRXSECSLOT_TS3 (0x3 << 6) |
872 | #define MC13783_CDCRXSECGAIN (0x3 << 8) | ||
873 | /* -inf, -0dB, -6dB, -12dB */ | 846 | /* -inf, -0dB, -6dB, -12dB */ |
874 | #define MC13783_CDCRXSECGAINw(x) (((x) << 8) & MC13783_CDCRXSECGAIN) | 847 | #define MC13783_CDCRXSECGAIN (0x3 << 8) |
875 | #define MC13783_CDCRXSECGAINr(x) (((x) & MC13783_CDCRXSECGAIN) >> 8) | 848 | #define MC13783_CDCRXSECGAIN_POS (8) |
876 | #define MC13783_CDCSUMGAIN (0x1 << 10) | 849 | #define MC13783_CDCSUMGAIN (0x1 << 10) |
877 | #define MC13783_CDCFSDLY (0x1 << 11) | 850 | #define MC13783_CDCFSDLY (0x1 << 11) |
878 | #define MC13783_STDCSLOTS (0x3 << 12) | 851 | #define MC13783_STDCSLOTS (0x3 << 12) |
@@ -890,10 +863,9 @@ enum mc13783_regs_enum | |||
890 | #define MC13783_STDCRXSECSLOT_TS2_TS3 (0x1 << 16) | 863 | #define MC13783_STDCRXSECSLOT_TS2_TS3 (0x1 << 16) |
891 | #define MC13783_STDCRXSECSLOT_TS4_TS5 (0x2 << 16) | 864 | #define MC13783_STDCRXSECSLOT_TS4_TS5 (0x2 << 16) |
892 | #define MC13783_STDCRXSECSLOT_TS6_TS7 (0x3 << 16) | 865 | #define MC13783_STDCRXSECSLOT_TS6_TS7 (0x3 << 16) |
893 | #define MC13783_STDCRXSECGAIN (0x3 << 18) | ||
894 | /* -inf, -0dB, -6dB, -12dB */ | 866 | /* -inf, -0dB, -6dB, -12dB */ |
895 | #define MC13783_STDCRXSECGAINw(x) (((x) << 8) & MC13783_STDCRXSECGAIN) | 867 | #define MC13783_STDCRXSECGAIN (0x3 << 18) |
896 | #define MC13783_STDCRXSECGAINr(x) (((x) & MC13783_STDCRXSECGAIN) >> 8) | 868 | #define MC13783_STDCRXSECGAIN_POS (18) |
897 | #define MC13783_STDSUMGAIN (0x1 << 20) | 869 | #define MC13783_STDSUMGAIN (0x1 << 20) |
898 | 870 | ||
899 | /* AUDIO_CODEC (40) */ | 871 | /* AUDIO_CODEC (40) */ |
@@ -988,14 +960,11 @@ enum mc13783_regs_enum | |||
988 | #define MC13783_ADSEL (0x1 << 3) | 960 | #define MC13783_ADSEL (0x1 << 3) |
989 | #define MC13783_TRIGMASK (0x1 << 4) | 961 | #define MC13783_TRIGMASK (0x1 << 4) |
990 | #define MC13783_ADA1 (0x7 << 5) | 962 | #define MC13783_ADA1 (0x7 << 5) |
991 | #define MC13783_ADA1w(x) (((x) << 5) & MC13783_ADA1) | 963 | #define MC13783_ADA1_POS (5) |
992 | #define MC13783_ADA1r(x) (((x) & MC13783_ADA1) >> 5) | ||
993 | #define MC13783_ADA2 (0x7 << 8) | 964 | #define MC13783_ADA2 (0x7 << 8) |
994 | #define MC13783_ADA2w(x) (((x) << 8) & MC13783_ADA2) | 965 | #define MC13783_ADA2_POS (8) |
995 | #define MC13783_ADA2r(x) (((x) & MC13783_ADA2) >> 8) | ||
996 | #define MC13783_ATO (0xff << 11) | 966 | #define MC13783_ATO (0xff << 11) |
997 | #define MC13783_ATOw(x) (((x) << 11) & MC13783_ATO) | 967 | #define MC13783_ATO_POS (11) |
998 | #define MC13783_ATOr(x) (((x) & MC13783_ATO) >> 11) | ||
999 | #define MC13783_ATOX (0x1 << 19) | 968 | #define MC13783_ATOX (0x1 << 19) |
1000 | #define MC13783_ASC (0x1 << 20) | 969 | #define MC13783_ASC (0x1 << 20) |
1001 | #define MC13783_ADTRIGIGN (0x1 << 21) | 970 | #define MC13783_ADTRIGIGN (0x1 << 21) |
@@ -1004,26 +973,24 @@ enum mc13783_regs_enum | |||
1004 | 973 | ||
1005 | /* ADC2 (45) */ | 974 | /* ADC2 (45) */ |
1006 | #define MC13783_ADD1 (0x3ff << 2) | 975 | #define MC13783_ADD1 (0x3ff << 2) |
1007 | #define MC13783_ADD1r(x) (((x) & MC13783_ADD1) >> 2) | 976 | #define MC13783_ADD1_POS (2) |
1008 | #define MC13783_ADD2 (0x3ff << 14) | 977 | #define MC13783_ADD2 (0x3ff << 14) |
1009 | #define MC13783_ADD2r(x) (((x) & MC13783_ADD2) >> 14) | 978 | #define MC13783_ADD2_POS (14) |
1010 | 979 | ||
1011 | /* ADC3 (46) */ | 980 | /* ADC3 (46) */ |
1012 | #define MC13783_WHIGH (0x3f << 0) | 981 | #define MC13783_WHIGH (0x3f << 0) |
1013 | #define MC13783_WHIGHw(x) (((x) << 0) & MC13783_WHIGH) | 982 | #define MC13783_WHIGH_POS (0) |
1014 | #define MC13783_WHIGHr(x) (((x) & MC13783_WHIGH) >> 0) | ||
1015 | #define MC13783_ICID (0x7 << 6) | 983 | #define MC13783_ICID (0x7 << 6) |
1016 | #define MC13783_ICIDr(x) (((x) & MC13783_ICID) >> 6) | 984 | #define MC13783_ICID_POS (6) |
1017 | #define MC13783_WLOW (0x3f << 9) | 985 | #define MC13783_WLOW (0x3f << 9) |
1018 | #define MC13783_WLOWw(x) (((x) << 9) & MC13783_WLOW) | 986 | #define MC13783_WLOW_POS (9) |
1019 | #define MC13783_WLOWr(x) (((x) & MC13783_WLOW) >> 9) | ||
1020 | #define MC13783_ADCBIS2_ACCESS (0x1 << 23) | 987 | #define MC13783_ADCBIS2_ACCESS (0x1 << 23) |
1021 | 988 | ||
1022 | /* ADC4 (47) */ | 989 | /* ADC4 (47) */ |
1023 | #define MC13783_ADCBIS1 (0x3ff << 2) | 990 | #define MC13783_ADCBIS1 (0x3ff << 2) |
1024 | #define MC13783_ADCBIS1r(x) (((x) & MC13783_ADCBIS1) >> 2) | 991 | #define MC13783_ADCBIS1_POS (2) |
1025 | #define MC13783_ADCBIS2 (0x3ff << 14) | 992 | #define MC13783_ADCBIS2 (0x3ff << 14) |
1026 | #define MC13783_ADCBIS2r(x) (((x) & MC13783_ADCBIS2) >> 14) | 993 | #define MC13783_ADCBIS2_POS (14) |
1027 | 994 | ||
1028 | /* CHARGER (48) */ | 995 | /* CHARGER (48) */ |
1029 | #define MC13783_VCHRG (0x7 << 0) | 996 | #define MC13783_VCHRG (0x7 << 0) |
@@ -1036,8 +1003,7 @@ enum mc13783_regs_enum | |||
1036 | #define MC13783_VCHRG_3_800V (0x6 << 0) | 1003 | #define MC13783_VCHRG_3_800V (0x6 << 0) |
1037 | #define MC13783_VCHRG_4_500V (0x7 << 0) | 1004 | #define MC13783_VCHRG_4_500V (0x7 << 0) |
1038 | #define MC13783_ICHRG (0xf << 3) /* Min Nom Max */ | 1005 | #define MC13783_ICHRG (0xf << 3) /* Min Nom Max */ |
1039 | #define MC13783_ICHRGw(x) (((x) << 3) & MC13783_ICHRG) | 1006 | #define MC13783_ICHRG_POS (3) |
1040 | #define MC13783_ICHRGr(x) (((x) & MC13783_ICHRG) >> 3) | ||
1041 | #define MC13783_ICHRG_0MA (0x0 << 3) /* 0 0 0 */ | 1007 | #define MC13783_ICHRG_0MA (0x0 << 3) /* 0 0 0 */ |
1042 | #define MC13783_ICHRG_70MA (0x1 << 3) /* 55 70 85 */ | 1008 | #define MC13783_ICHRG_70MA (0x1 << 3) /* 55 70 85 */ |
1043 | #define MC13783_ICHRG_177MA (0x2 << 3) /* 161 177 195 */ | 1009 | #define MC13783_ICHRG_177MA (0x2 << 3) /* 161 177 195 */ |
@@ -1055,8 +1021,7 @@ enum mc13783_regs_enum | |||
1055 | #define MC13783_ICHRG_1596MA (0xe << 3) /* 1450 1596 1755 */ | 1021 | #define MC13783_ICHRG_1596MA (0xe << 3) /* 1450 1596 1755 */ |
1056 | #define MC13783_ICHRG_FULLY_ON (0xf << 3) /* Disallow HW FET turn on */ | 1022 | #define MC13783_ICHRG_FULLY_ON (0xf << 3) /* Disallow HW FET turn on */ |
1057 | #define MC13783_ICHRGTR (0x7 << 7) /* Min Nom Max */ | 1023 | #define MC13783_ICHRGTR (0x7 << 7) /* Min Nom Max */ |
1058 | #define MC13783_ICHRGTRw(x) (((x) << 7) & MC13783_ICHRGTR) | 1024 | #define MC13783_ICHRGTR_POS (7) |
1059 | #define MC13783_ICHRGTRr(x) (((x) & MC13783_ICHRGTR) >> 7) | ||
1060 | #define MC13783_ICHRGTR_0MA (0x0 << 7) /* 0 0 0 */ | 1025 | #define MC13783_ICHRGTR_0MA (0x0 << 7) /* 0 0 0 */ |
1061 | #define MC13783_ICHRGTR_9MA (0x1 << 7) /* 6 9 12 */ | 1026 | #define MC13783_ICHRGTR_9MA (0x1 << 7) /* 6 9 12 */ |
1062 | #define MC13783_ICHRGTR_20MA (0x2 << 7) /* 14 20 26 */ | 1027 | #define MC13783_ICHRGTR_20MA (0x2 << 7) /* 14 20 26 */ |
@@ -1148,8 +1113,7 @@ enum mc13783_regs_enum | |||
1148 | #define MC13783_ABREF_600MV (0x2 << 14) | 1113 | #define MC13783_ABREF_600MV (0x2 << 14) |
1149 | #define MC13783_ABREF_800MV (0x3 << 14) | 1114 | #define MC13783_ABREF_800MV (0x3 << 14) |
1150 | #define MC13783_FLPATTRN (0xf << 17) | 1115 | #define MC13783_FLPATTRN (0xf << 17) |
1151 | #define MC13783_FLPATTRNw(x) (((x) << 17) & MC13783_FLPATTRN) | 1116 | #define MC13783_FLPATTRN_POS (17) |
1152 | #define MC13783_FLPATTRNr(x) (((x) & MC13783_FLPATTRN) >> 17) | ||
1153 | #define MC13783_FLBANK1 (0x1 << 21) | 1117 | #define MC13783_FLBANK1 (0x1 << 21) |
1154 | #define MC13783_FLBANK2 (0x1 << 22) | 1118 | #define MC13783_FLBANK2 (0x1 << 22) |
1155 | #define MC13783_FLBANK3 (0x1 << 23) | 1119 | #define MC13783_FLBANK3 (0x1 << 23) |
@@ -1178,98 +1142,70 @@ enum mc13783_regs_enum | |||
1178 | 1142 | ||
1179 | /* LED_CONTROL2 (53) */ | 1143 | /* LED_CONTROL2 (53) */ |
1180 | #define MC13783_LEDMD (0x7 << 0) | 1144 | #define MC13783_LEDMD (0x7 << 0) |
1181 | #define MC13783_LEDMDw(x) (((x) << 0) & MC13783_LEDMD) | 1145 | #define MC13783_LEDMD_POS (0) |
1182 | #define MC13783_LEDMDr(x) (((x) & MC13783_LEDMD) >> 0) | ||
1183 | #define MC13783_LEDAD (0x7 << 3) | 1146 | #define MC13783_LEDAD (0x7 << 3) |
1184 | #define MC13783_LEDADw(x) (((x) << 3) & MC13783_LEDAD) | 1147 | #define MC13783_LEDAD_POS (3) |
1185 | #define MC13783_LEDADr(x) (((x) & MC13783_LEDAD) >> 3) | ||
1186 | #define MC13783_LEDKP (0x7 << 6) | 1148 | #define MC13783_LEDKP (0x7 << 6) |
1187 | #define MC13783_LEDKPw(x) (((x) << 6) & MC13783_LEDKP) | 1149 | #define MC13783_LEDKP_POS (6) |
1188 | #define MC13783_LEDKPr(x) (((x) & MC13783_LEDKP) >> 6) | ||
1189 | #define MC13783_LEDMDDC (0xf << 9) | 1150 | #define MC13783_LEDMDDC (0xf << 9) |
1190 | #define MC13783_LEDMDDCw(x) (((x) << 9) & MC13783_LEDMDDC) | 1151 | #define MC13783_LEDMDDC_POS (9) |
1191 | #define MC13783_LEDMDDCr(x) (((x) & MC13783_LEDMDDC) >> 9) | ||
1192 | #define MC13783_LEDADDC (0xf << 13) | 1152 | #define MC13783_LEDADDC (0xf << 13) |
1193 | #define MC13783_LEDADDCw(x) (((x) << 13) & MC13783_LEDADDC) | 1153 | #define MC13783_LEDADDC_POS (13) |
1194 | #define MC13783_LEDADDCr(x) (((x) & MC13783_LEDADDC) >> 13) | ||
1195 | #define MC13783_LEDKPDC (0xf << 17) | 1154 | #define MC13783_LEDKPDC (0xf << 17) |
1196 | #define MC13783_LEDKPDCw(x) (((x) << 17) & MC13783_LEDKPDC) | 1155 | #define MC13783_LEDKPDC_POS (17) |
1197 | #define MC13783_LEDKPDCr(x) (((x) & MC13783_LEDKPDC) >> 17) | ||
1198 | #define MC13783_BLPERIOD (0x1 << 21) | 1156 | #define MC13783_BLPERIOD (0x1 << 21) |
1199 | #define MC13783_BLPERIODw(x) (((x) << 21) & MC13783_BLPERIOD) | 1157 | #define MC13783_BLPERIOD_POS (21) |
1200 | #define MC13783_BLPERIODr(x) (((x) & MC13783_BLPERIOD) >> 21) | ||
1201 | #define MC13783_SLEWLIMBL (0x1 << 23) | 1158 | #define MC13783_SLEWLIMBL (0x1 << 23) |
1202 | 1159 | ||
1203 | /* LED_CONTROL3 (54) */ | 1160 | /* LED_CONTROL3 (54) */ |
1204 | #define MC13783_LEDR1 (0x3 << 0) | 1161 | #define MC13783_LEDR1 (0x3 << 0) |
1205 | #define MC13783_LEDR1w(x) (((x) << 0) & MC13783_LEDR1) | 1162 | #define MC13783_LEDR1_POS (0) |
1206 | #define MC13783_LEDR1r(x) (((x) & MC13783_LEDR1) >> 0) | ||
1207 | #define MC13783_LEDG1 (0x3 << 2) | 1163 | #define MC13783_LEDG1 (0x3 << 2) |
1208 | #define MC13783_LEDG1w(x) (((x) << 2) & MC13783_LEDG1) | 1164 | #define MC13783_LEDG1_POS (2) |
1209 | #define MC13783_LEDG1r(x) (((x) & MC13783_LEDG1) >> 2) | ||
1210 | #define MC13783_LEDB1 (0x3 << 4) | 1165 | #define MC13783_LEDB1 (0x3 << 4) |
1211 | #define MC13783_LEDB1w(x) (((x) << 4) & MC13783_LEDB1) | 1166 | #define MC13783_LEDB1_POS (4) |
1212 | #define MC13783_LEDB1r(x) (((x) & MC13783_LEDB1) >> 4) | ||
1213 | #define MC13783_LEDR1DC (0x1f << 6) | 1167 | #define MC13783_LEDR1DC (0x1f << 6) |
1214 | #define MC13783_LEDR1DCw(x) (((x) << 6) & MC13783_LEDR1DC) | 1168 | #define MC13783_LEDR1DC_POS (6) |
1215 | #define MC13783_LEDR1DCr(x) (((x) & MC13783_LEDR1DC) >> 6) | ||
1216 | #define MC13783_LEDG1DC (0x1f << 11) | 1169 | #define MC13783_LEDG1DC (0x1f << 11) |
1217 | #define MC13783_LEDG1DCw(x) (((x) << 11) & MC13783_LEDG1DC) | 1170 | #define MC13783_LEDG1DC_POS (11) |
1218 | #define MC13783_LEDG1DCr(x) (((x) & MC13783_LEDG1DC) >> 11) | ||
1219 | #define MC13783_LEDB1DC (0x1f << 16) | 1171 | #define MC13783_LEDB1DC (0x1f << 16) |
1220 | #define MC13783_LEDB1DCw(x) (((x) << 16) & MC13783_LEDB1DC) | 1172 | #define MC13783_LEDB1DC_POS (16) |
1221 | #define MC13783_LEDB1DCr(x) (((x) & MC13783_LEDB1DC) >> 16) | ||
1222 | #define MC13783_TC1PERIOD (0x3 << 21) | 1173 | #define MC13783_TC1PERIOD (0x3 << 21) |
1223 | #define MC13783_TC1PERIODw(x) (((x) << 21) & MC13783_TC1PERIOD) | 1174 | #define MC13783_TC1PERIOD_POS (21) |
1224 | #define MC13783_TC1PERIODr(x) (((x) & MC13783_TC1PERIOD) >> 21) | ||
1225 | #define MC13783_TC1TRIODE (0x1 << 23) | 1175 | #define MC13783_TC1TRIODE (0x1 << 23) |
1226 | 1176 | ||
1227 | /* LED_CONTROL4 (55) */ | 1177 | /* LED_CONTROL4 (55) */ |
1228 | #define MC13783_LEDR2 (0x3 << 0) | 1178 | #define MC13783_LEDR2 (0x3 << 0) |
1229 | #define MC13783_LEDR2w(x) (((x) << 0) & MC13783_LEDR2) | 1179 | #define MC13783_LEDR2_POS (0) |
1230 | #define MC13783_LEDR2r(x) (((x) & MC13783_LEDR2) >> 0) | ||
1231 | #define MC13783_LEDG2 (0x3 << 2) | 1180 | #define MC13783_LEDG2 (0x3 << 2) |
1232 | #define MC13783_LEDG2w(x) (((x) << 2) & MC13783_LEDG2) | 1181 | #define MC13783_LEDG2_POS (2) |
1233 | #define MC13783_LEDG2r(x) (((x) & MC13783_LEDG2) >> 2) | ||
1234 | #define MC13783_LEDB2 (0x3 << 4) | 1182 | #define MC13783_LEDB2 (0x3 << 4) |
1235 | #define MC13783_LEDB2w(x) (((x) << 4) & MC13783_LEDB2) | 1183 | #define MC13783_LEDB2_POS (4) |
1236 | #define MC13783_LEDB2r(x) (((x) & MC13783_LEDB2) >> 4) | ||
1237 | #define MC13783_LEDR2DC (0x1f << 6) | 1184 | #define MC13783_LEDR2DC (0x1f << 6) |
1238 | #define MC13783_LEDR2DCw(x) (((x) << 6) & MC13783_LEDR2DC) | 1185 | #define MC13783_LEDR2DC_POS (6) |
1239 | #define MC13783_LEDR2DCr(x) (((x) & MC13783_LEDR2DC) >> 6) | ||
1240 | #define MC13783_LEDG2DC (0x1f << 11) | 1186 | #define MC13783_LEDG2DC (0x1f << 11) |
1241 | #define MC13783_LEDG2DCw(x) (((x) << 11) & MC13783_LEDG2DC) | 1187 | #define MC13783_LEDG2DC_POS (11) |
1242 | #define MC13783_LEDG2DCr(x) (((x) & MC13783_LEDG2DC) >> 11) | ||
1243 | #define MC13783_LEDB2DC (0x1f << 16) | 1188 | #define MC13783_LEDB2DC (0x1f << 16) |
1244 | #define MC13783_LEDB2DCw(x) (((x) << 16) & MC13783_LEDB2DC) | 1189 | #define MC13783_LEDB2DC_POS (16) |
1245 | #define MC13783_LEDB2DCr(x) (((x) & MC13783_LEDB2DC) >> 16) | ||
1246 | #define MC13783_TC2PERIOD (0x3 << 21) | 1190 | #define MC13783_TC2PERIOD (0x3 << 21) |
1247 | #define MC13783_TC2PERIODw(x) (((x) << 21) & MC13783_TC2PERIOD) | 1191 | #define MC13783_TC2PERIOD_POS (21) |
1248 | #define MC13783_TC2PERIODr(x) (((x) & MC13783_TC2PERIOD) >> 21) | ||
1249 | #define MC13783_TC2TRIODE (0x1 << 23) | 1192 | #define MC13783_TC2TRIODE (0x1 << 23) |
1250 | 1193 | ||
1251 | /* LED_CONTROL5 (56) */ | 1194 | /* LED_CONTROL5 (56) */ |
1252 | #define MC13783_LEDR3 (0x3 << 0) | 1195 | #define MC13783_LEDR3 (0x3 << 0) |
1253 | #define MC13783_LEDR3w(x) (((x) << 0) & MC13783_LEDR3) | 1196 | #define MC13783_LEDR3_POS (0) |
1254 | #define MC13783_LEDR3r(x) (((x) & MC13783_LEDR3) >> 0) | ||
1255 | #define MC13783_LEDG3 (0x3 << 2) | 1197 | #define MC13783_LEDG3 (0x3 << 2) |
1256 | #define MC13783_LEDG3w(x) (((x) << 2) & MC13783_LEDG3) | 1198 | #define MC13783_LEDG3_POS (2) |
1257 | #define MC13783_LEDG3r(x) (((x) & MC13783_LEDG3) >> 2) | ||
1258 | #define MC13783_LEDB3 (0x3 << 4) | 1199 | #define MC13783_LEDB3 (0x3 << 4) |
1259 | #define MC13783_LEDB3w(x) (((x) << 4) & MC13783_LEDB3) | 1200 | #define MC13783_LEDB3_POS (4) |
1260 | #define MC13783_LEDB3r(x) (((x) & MC13783_LEDB3) >> 4) | ||
1261 | #define MC13783_LEDR3DC (0x1f << 6) | 1201 | #define MC13783_LEDR3DC (0x1f << 6) |
1262 | #define MC13783_LEDR3DCw(x) (((x) << 6) & MC13783_LEDR3DC) | 1202 | #define MC13783_LEDR3DC_POS (6) |
1263 | #define MC13783_LEDR3DCr(x) (((x) & MC13783_LEDR3DC) >> 6) | ||
1264 | #define MC13783_LEDG3DC (0x1f << 11) | 1203 | #define MC13783_LEDG3DC (0x1f << 11) |
1265 | #define MC13783_LEDG3DCw(x) (((x) << 11) & MC13783_LEDG3DC) | 1204 | #define MC13783_LEDG3DC_POS (11) |
1266 | #define MC13783_LEDG3DCr(x) (((x) & MC13783_LEDG3DC) >> 11) | ||
1267 | #define MC13783_LEDB3DC (0x1f << 16) | 1205 | #define MC13783_LEDB3DC (0x1f << 16) |
1268 | #define MC13783_LEDB3DCw(x) (((x) << 16) & MC13783_LEDB3DC) | 1206 | #define MC13783_LEDB3DC_POS (16) |
1269 | #define MC13783_LEDB3DCr(x) (((x) & MC13783_LEDB3DC) >> 16) | ||
1270 | #define MC13783_TC3PERIOD (0x3 << 21) | 1207 | #define MC13783_TC3PERIOD (0x3 << 21) |
1271 | #define MC13783_TC3PERIODw(x) (((x) << 21) & MC13783_TC3PERIOD) | 1208 | #define MC13783_TC3PERIOD_POS (21) |
1272 | #define MC13783_TC3PERIODr(x) (((x) & MC13783_TC3PERIOD) >> 21) | ||
1273 | #define MC13783_TC3TRIODE (0x1 << 23) | 1209 | #define MC13783_TC3TRIODE (0x1 << 23) |
1274 | 1210 | ||
1275 | /* For event enum values which are target-defined */ | 1211 | /* For event enum values which are target-defined */ |
diff --git a/firmware/target/arm/imx31/debug-imx31.c b/firmware/target/arm/imx31/debug-imx31.c index ad436ea231..abf180cfd2 100644 --- a/firmware/target/arm/imx31/debug-imx31.c +++ b/firmware/target/arm/imx31/debug-imx31.c | |||
@@ -50,15 +50,15 @@ bool __dbg_hw_info(void) | |||
50 | iim_system_rev()); | 50 | iim_system_rev()); |
51 | lcd_puts(0, line++, buf); line++; | 51 | lcd_puts(0, line++, buf); line++; |
52 | 52 | ||
53 | mpctl = CLKCTL_MPCTL; | 53 | mpctl = CCM_MPCTL; |
54 | spctl = CLKCTL_SPCTL; | 54 | spctl = CCM_SPCTL; |
55 | upctl = CLKCTL_UPCTL; | 55 | upctl = CCM_UPCTL; |
56 | 56 | ||
57 | pllref = imx31_clkctl_get_pll_ref_clk(); | 57 | pllref = ccm_get_pll_ref_clk(); |
58 | 58 | ||
59 | mcu_pllfreq = imx31_clkctl_get_pll(PLL_MCU); | 59 | mcu_pllfreq = ccm_get_pll(PLL_MCU); |
60 | ser_pllfreq = imx31_clkctl_get_pll(PLL_SERIAL); | 60 | ser_pllfreq = ccm_get_pll(PLL_SERIAL); |
61 | usb_pllfreq = imx31_clkctl_get_pll(PLL_USB); | 61 | usb_pllfreq = ccm_get_pll(PLL_USB); |
62 | 62 | ||
63 | snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref); | 63 | snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref); |
64 | lcd_puts(0, line++, buf); line++; | 64 | lcd_puts(0, line++, buf); line++; |
@@ -70,7 +70,7 @@ bool __dbg_hw_info(void) | |||
70 | snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq); | 70 | snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq); |
71 | lcd_puts(0, line++, buf); line++; | 71 | lcd_puts(0, line++, buf); line++; |
72 | 72 | ||
73 | regval = CLKCTL_PDR0; | 73 | regval = CCM_PDR0; |
74 | snprintf(buf, sizeof (buf), " PDR0: %08lX", regval); | 74 | snprintf(buf, sizeof (buf), " PDR0: %08lX", regval); |
75 | lcd_puts(0, line++, buf); | 75 | lcd_puts(0, line++, buf); |
76 | 76 | ||
@@ -111,7 +111,7 @@ bool __dbg_hw_info(void) | |||
111 | snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq); | 111 | snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq); |
112 | lcd_puts(0, line++, buf); line++; | 112 | lcd_puts(0, line++, buf); line++; |
113 | 113 | ||
114 | regval = CLKCTL_PDR1; | 114 | regval = CCM_PDR1; |
115 | snprintf(buf, sizeof (buf), " PDR1: %08lX", regval); | 115 | snprintf(buf, sizeof (buf), " PDR1: %08lX", regval); |
116 | lcd_puts(0, line++, buf); | 116 | lcd_puts(0, line++, buf); |
117 | 117 | ||
@@ -120,7 +120,7 @@ bool __dbg_hw_info(void) | |||
120 | snprintf(buf, sizeof (buf), " usb_clk: %u", freq); | 120 | snprintf(buf, sizeof (buf), " usb_clk: %u", freq); |
121 | lcd_puts(0, line++, buf); | 121 | lcd_puts(0, line++, buf); |
122 | 122 | ||
123 | freq = usb_pllfreq / (((CLKCTL_PDR0 >> 16) & 0x1f) + 1); | 123 | freq = usb_pllfreq / (((CCM_PDR0 >> 16) & 0x1f) + 1); |
124 | snprintf(buf, sizeof (buf), " ipg_per_baud: %u", freq); | 124 | snprintf(buf, sizeof (buf), " ipg_per_baud: %u", freq); |
125 | lcd_puts(0, line++, buf); | 125 | lcd_puts(0, line++, buf); |
126 | 126 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c index 3c66c42adc..52293228f8 100644 --- a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c | |||
@@ -57,8 +57,8 @@ unsigned short adc_read(int channel) | |||
57 | { | 57 | { |
58 | /* Keep enable, start conversion, increment from channel 0, | 58 | /* Keep enable, start conversion, increment from channel 0, |
59 | * increment from channel 4 */ | 59 | * increment from channel 4 */ |
60 | uint32_t adc1 = MC13783_ADEN | MC13783_ASC | MC13783_ADA1w(0) | | 60 | uint32_t adc1 = MC13783_ADEN | MC13783_ASC | |
61 | MC13783_ADA2w(4); | 61 | (0 << MC13783_ADA1_POS) | (4 << MC13783_ADA2_POS); |
62 | 62 | ||
63 | if (input_select == 1) | 63 | if (input_select == 1) |
64 | adc1 |= MC13783_ADSEL; /* 2nd set of inputs */ | 64 | adc1 |= MC13783_ADSEL; /* 2nd set of inputs */ |
@@ -81,7 +81,9 @@ unsigned short adc_read(int channel) | |||
81 | mutex_unlock(&adc_mtx); | 81 | mutex_unlock(&adc_mtx); |
82 | 82 | ||
83 | /* Channels 0-3/8-11 in ADD1, 4-7/12-15 in ADD2 */ | 83 | /* Channels 0-3/8-11 in ADD1, 4-7/12-15 in ADD2 */ |
84 | return (channel & 4) ? MC13783_ADD2r(data) : MC13783_ADD1r(data); | 84 | return (channel & 4) ? |
85 | ((data & MC13783_ADD2) >> MC13783_ADD2_POS) : | ||
86 | ((data & MC13783_ADD1) >> MC13783_ADD1_POS); | ||
85 | } | 87 | } |
86 | 88 | ||
87 | bool adc_enable_channel(int channel, bool enable) | 89 | bool adc_enable_channel(int channel, bool enable) |
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c index c32dead30a..c941037317 100644 --- a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c | |||
@@ -275,7 +275,7 @@ static unsigned long ata_dma_selected = ATA_DMA_PIO; | |||
275 | static unsigned int get_T(void) | 275 | static unsigned int get_T(void) |
276 | { | 276 | { |
277 | /* T = ATA clock period in nanoseconds */ | 277 | /* T = ATA clock period in nanoseconds */ |
278 | return 1000 * 1000 * 1000 / imx31_clkctl_get_ata_clk(); | 278 | return 1000 * 1000 * 1000 / ccm_get_ata_clk(); |
279 | } | 279 | } |
280 | 280 | ||
281 | static void ata_wait_for_idle(void) | 281 | static void ata_wait_for_idle(void) |
@@ -325,7 +325,7 @@ void ata_reset(void) | |||
325 | void ata_enable(bool on) | 325 | void ata_enable(bool on) |
326 | { | 326 | { |
327 | /* Unconditionally clock module before writing regs */ | 327 | /* Unconditionally clock module before writing regs */ |
328 | imx31_clkctl_module_clock_gating(CG_ATA, CGM_ON_ALL); | 328 | ccm_module_clock_gating(CG_ATA, CGM_ON_RUN_WAIT); |
329 | ata_wait_for_idle(); | 329 | ata_wait_for_idle(); |
330 | 330 | ||
331 | if (on) | 331 | if (on) |
@@ -339,7 +339,7 @@ void ata_enable(bool on) | |||
339 | sleep(HZ/100); | 339 | sleep(HZ/100); |
340 | 340 | ||
341 | /* Disable off - unclock ATA module */ | 341 | /* Disable off - unclock ATA module */ |
342 | imx31_clkctl_module_clock_gating(CG_ATA, CGM_OFF); | 342 | ccm_module_clock_gating(CG_ATA, CGM_OFF); |
343 | } | 343 | } |
344 | } | 344 | } |
345 | 345 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c index a135889e6e..4ba7da4be0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c | |||
@@ -59,7 +59,7 @@ void UIE_VECTOR(void) | |||
59 | ); | 59 | ); |
60 | 60 | ||
61 | offset = mode == 0x11 ? | 61 | offset = mode == 0x11 ? |
62 | (int32_t)FIVECSR : ((int32_t)NIVECSR >> 16); | 62 | (int32_t)AVIC_FIVECSR : ((int32_t)AVIC_NIVECSR >> 16); |
63 | 63 | ||
64 | panicf("Unhandled %s %d: %s", | 64 | panicf("Unhandled %s %d: %s", |
65 | mode == 0x11 ? "FIQ" : "IRQ", offset, | 65 | mode == 0x11 ? "FIQ" : "IRQ", offset, |
@@ -69,7 +69,7 @@ void UIE_VECTOR(void) | |||
69 | /* We use the AVIC */ | 69 | /* We use the AVIC */ |
70 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | 70 | void __attribute__((interrupt("IRQ"))) irq_handler(void) |
71 | { | 71 | { |
72 | const int offset = (int32_t)NIVECSR >> 16; | 72 | const int offset = (int32_t)AVIC_NIVECSR >> 16; |
73 | 73 | ||
74 | if (offset == -1) | 74 | if (offset == -1) |
75 | { | 75 | { |
@@ -105,20 +105,20 @@ void avic_init(void) | |||
105 | int i; | 105 | int i; |
106 | 106 | ||
107 | /* Disable all interrupts and set to unhandled */ | 107 | /* Disable all interrupts and set to unhandled */ |
108 | avic_disable_int(ALL); | 108 | avic_disable_int(INT_ALL); |
109 | 109 | ||
110 | /* Reset AVIC control */ | 110 | /* Reset AVIC control */ |
111 | avic->intcntl = 0; | 111 | avic->intcntl = 0; |
112 | 112 | ||
113 | /* Init all interrupts to type IRQ */ | 113 | /* Init all interrupts to type IRQ */ |
114 | avic_set_int_type(ALL, IRQ); | 114 | avic_set_int_type(INT_ALL, INT_TYPE_IRQ); |
115 | 115 | ||
116 | /* Set all normal to lowest priority */ | 116 | /* Set all normal to lowest priority */ |
117 | for (i = 0; i < 8; i++) | 117 | for (i = 0; i < 8; i++) |
118 | avic->nipriority[i] = 0; | 118 | avic->nipriority[i] = 0; |
119 | 119 | ||
120 | /* Set NM bit to enable VIC */ | 120 | /* Set NM bit to enable VIC */ |
121 | avic->intcntl |= INTCNTL_NM; | 121 | avic->intcntl |= AVIC_INTCNTL_NM; |
122 | 122 | ||
123 | /* Enable VE bit in CP15 Control reg to enable VIC */ | 123 | /* Enable VE bit in CP15 Control reg to enable VIC */ |
124 | asm volatile ( | 124 | asm volatile ( |
@@ -147,7 +147,7 @@ void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, | |||
147 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 147 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; |
148 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 148 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
149 | 149 | ||
150 | if (ints != ALL) /* No mass-enable allowed */ | 150 | if (ints != INT_ALL) /* No mass-enable allowed */ |
151 | { | 151 | { |
152 | avic_set_int_type(ints, intstype); | 152 | avic_set_int_type(ints, intstype); |
153 | avic->vector[ints] = (long)handler; | 153 | avic->vector[ints] = (long)handler; |
@@ -163,7 +163,7 @@ void avic_disable_int(enum IMX31_INT_LIST ints) | |||
163 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 163 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; |
164 | uint32_t i; | 164 | uint32_t i; |
165 | 165 | ||
166 | if (ints == ALL) | 166 | if (ints == INT_ALL) |
167 | { | 167 | { |
168 | for (i = 0; i < 64; i++) | 168 | for (i = 0; i < 64; i++) |
169 | { | 169 | { |
@@ -185,7 +185,7 @@ static void set_int_type(int i, enum INT_TYPE intstype) | |||
185 | volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)]; | 185 | volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)]; |
186 | uint32_t val = 1L << (i & 0x1f); | 186 | uint32_t val = 1L << (i & 0x1f); |
187 | 187 | ||
188 | if (intstype == IRQ) | 188 | if (intstype == INT_TYPE_IRQ) |
189 | val = *reg & ~val; | 189 | val = *reg & ~val; |
190 | else | 190 | else |
191 | val = *reg | val; | 191 | val = *reg | val; |
@@ -197,7 +197,7 @@ void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype) | |||
197 | { | 197 | { |
198 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 198 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
199 | 199 | ||
200 | if (ints == ALL) | 200 | if (ints == INT_ALL) |
201 | { | 201 | { |
202 | int i; | 202 | int i; |
203 | for (i = 0; i < 64; i++) | 203 | for (i = 0; i < 64; i++) |
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h index 3580c8c083..a049713600 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h | |||
@@ -172,32 +172,34 @@ struct avic_map | |||
172 | }; | 172 | }; |
173 | }; | 173 | }; |
174 | 174 | ||
175 | #define INT_PRIO_DEFAULT 7 | ||
176 | |||
175 | enum INT_TYPE | 177 | enum INT_TYPE |
176 | { | 178 | { |
177 | IRQ = 0, | 179 | INT_TYPE_IRQ = 0, |
178 | FIQ | 180 | INT_TYPE_FIQ |
179 | }; | 181 | }; |
180 | 182 | ||
181 | enum IMX31_INT_LIST | 183 | enum IMX31_INT_LIST |
182 | { | 184 | { |
183 | __IMX31_INT_FIRST = -1, | 185 | __IMX31_INT_FIRST = -1, |
184 | RESERVED0, RESERVED1, RESERVED2, I2C3, | 186 | INT_RESERVED0, INT_RESERVED1, INT_RESERVED2, INT_I2C3, |
185 | I2C2, MPEG4_ENCODER, RTIC, FIR, | 187 | INT_I2C2, INT_MPEG4_ENCODER, INT_RTIC, INT_FIR, |
186 | MMC_SDHC2, MMC_SDHC1, I2C1, SSI2, | 188 | INT_MMC_SDHC2, INT_MMC_SDHC1, INT_I2C1, INT_SSI2, |
187 | SSI1, CSPI2, CSPI1, ATA, | 189 | INT_SSI1, INT_CSPI2, INT_CSPI1, INT_ATA, |
188 | MBX, CSPI3, UART3, IIM, | 190 | INT_MBX, INT_CSPI3, INT_UART3, INT_IIM, |
189 | SIM1, SIM2, RNGA, EVTMON, | 191 | INT_SIM1, INT_SIM2, INT_RNGA, INT_EVTMON, |
190 | KPP, RTC, PWN, EPIT2, | 192 | INT_KPP, INT_RTC, INT_PWN, INT_EPIT2, |
191 | EPIT1, GPT, PWR_FAIL, CCM_DVFS, | 193 | INT_EPIT1, INT_GPT, INT_PWR_FAIL, INT_CCM_DVFS, |
192 | UART2, NANDFC, SDMA, USB_HOST1, | 194 | INT_UART2, INT_NANDFC, INT_SDMA, INT_USB_HOST1, |
193 | USB_HOST2, USB_OTG, RESERVED3, MSHC1, | 195 | INT_USB_HOST2, INT_USB_OTG, INT_RESERVED3, INT_MSHC1, |
194 | MSHC2, IPU_ERR, IPU, RESERVED4, | 196 | INT_MSHC2, INT_IPU_ERR, INT_IPU, INT_RESERVED4, |
195 | RESERVED5, UART1, UART4, UART5, | 197 | INT_RESERVED5, INT_UART1, INT_UART4, INT_UART5, |
196 | ETC_IRQ, SCC_SCM, SCC_SMN, GPIO2, | 198 | INT_ETC_IRQ, INT_SCC_SCM, INT_SCC_SMN, INT_GPIO2, |
197 | GPIO1, CCM_CLK, PCMCIA, WDOG, | 199 | INT_GPIO1, INT_CCM_CLK, INT_PCMCIA, INT_WDOG, |
198 | GPIO3, RESERVED6, EXT_PWMG, EXT_TEMP, | 200 | INT_GPIO3, INT_RESERVED6, INT_EXT_PWMG, INT_EXT_TEMP, |
199 | EXT_SENS1, EXT_SENS2, EXT_WDOG, EXT_TV, | 201 | INT_EXT_SENS1, INT_EXT_SENS2, INT_EXT_WDOG, INT_EXT_TV, |
200 | ALL | 202 | INT_ALL |
201 | }; | 203 | }; |
202 | 204 | ||
203 | void avic_init(void); | 205 | void avic_init(void); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c index 8f75b72f58..8457d06a77 100644 --- a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c | |||
@@ -176,7 +176,8 @@ void _backlight_off(void) | |||
176 | sleep(HZ/100); | 176 | sleep(HZ/100); |
177 | 177 | ||
178 | /* Write final PWM setting */ | 178 | /* Write final PWM setting */ |
179 | mc13783_write_masked(MC13783_LED_CONTROL2, MC13783_LEDMDDCw(0), | 179 | mc13783_write_masked(MC13783_LED_CONTROL2, |
180 | 0 << MC13783_LEDMDDC_POS, | ||
180 | MC13783_LEDMDDC); | 181 | MC13783_LEDMDDC); |
181 | 182 | ||
182 | #ifdef HAVE_LCD_SLEEP | 183 | #ifdef HAVE_LCD_SLEEP |
@@ -198,10 +199,10 @@ void _backlight_set_brightness(int brightness) | |||
198 | 199 | ||
199 | md = led_md_pwm_table[brightness].md; | 200 | md = led_md_pwm_table[brightness].md; |
200 | backlight_pwm_bits = backlight_on_status ? | 201 | backlight_pwm_bits = backlight_on_status ? |
201 | MC13783_LEDMDDCw(led_md_pwm_table[brightness].pwm) : 0; | 202 | (led_md_pwm_table[brightness].pwm << MC13783_LEDMDDC_POS) : 0; |
202 | 203 | ||
203 | mc13783_write_masked(MC13783_LED_CONTROL2, | 204 | mc13783_write_masked(MC13783_LED_CONTROL2, |
204 | MC13783_LEDMDw(md) | backlight_pwm_bits, | 205 | (md << MC13783_LEDMD_POS) | backlight_pwm_bits, |
205 | MC13783_LEDMD | MC13783_LEDMDDC); | 206 | MC13783_LEDMD | MC13783_LEDMDDC); |
206 | 207 | ||
207 | mutex_unlock(&backlight_mutex); | 208 | mutex_unlock(&backlight_mutex); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c index d2a46f2c9f..505ba397d9 100644 --- a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c | |||
@@ -197,7 +197,7 @@ void button_init_device(void) | |||
197 | #endif | 197 | #endif |
198 | 198 | ||
199 | /* Enable keypad clock */ | 199 | /* Enable keypad clock */ |
200 | imx31_clkctl_module_clock_gating(CG_KPP, CGM_ON_ALL); | 200 | ccm_module_clock_gating(CG_KPP, CGM_ON_RUN_WAIT); |
201 | 201 | ||
202 | /* 1. Enable number of rows in keypad (KPCR[4:0]) | 202 | /* 1. Enable number of rows in keypad (KPCR[4:0]) |
203 | * | 203 | * |
@@ -219,8 +219,7 @@ void button_init_device(void) | |||
219 | * 6. Set the KDIE control bit bit. */ | 219 | * 6. Set the KDIE control bit bit. */ |
220 | KPP_KPSR = KPP_KPSR_KDIE | KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKD; | 220 | KPP_KPSR = KPP_KPSR_KDIE | KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKD; |
221 | 221 | ||
222 | /* KPP IRQ at priority 3 */ | 222 | avic_enable_int(INT_KPP, INT_TYPE_IRQ, INT_PRIO_DEFAULT, KPP_HANDLER); |
223 | avic_enable_int(KPP, IRQ, 3, KPP_HANDLER); | ||
224 | 223 | ||
225 | button_power_event(); | 224 | button_power_event(); |
226 | mc13783_enable_event(MC13783_ONOFD1_EVENT); | 225 | mc13783_enable_event(MC13783_ONOFD1_EVENT); |
@@ -235,7 +234,7 @@ void button_close_device(void) | |||
235 | { | 234 | { |
236 | int oldlevel = disable_irq_save(); | 235 | int oldlevel = disable_irq_save(); |
237 | 236 | ||
238 | avic_disable_int(KPP); | 237 | avic_disable_int(INT_KPP); |
239 | KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE); | 238 | KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE); |
240 | int_btn = BUTTON_NONE; | 239 | int_btn = BUTTON_NONE; |
241 | 240 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c index df592deecb..761cf8f701 100644 --- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c | |||
@@ -24,47 +24,41 @@ | |||
24 | #include "cpu.h" | 24 | #include "cpu.h" |
25 | #include "clkctl-imx31.h" | 25 | #include "clkctl-imx31.h" |
26 | 26 | ||
27 | unsigned int imx31_get_src_pll(void) | 27 | unsigned int ccm_get_src_pll(void) |
28 | { | 28 | { |
29 | return (CLKCTL_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU; | 29 | return (CCM_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU; |
30 | } | 30 | } |
31 | 31 | ||
32 | void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg, | 32 | void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode) |
33 | enum IMX31_CG_MODES mode) | ||
34 | { | 33 | { |
35 | volatile unsigned long *reg; | 34 | volatile unsigned long *reg; |
36 | unsigned long mask; | 35 | unsigned long mask; |
37 | int shift; | 36 | int shift; |
38 | int oldlevel; | ||
39 | 37 | ||
40 | if (cg >= CG_NUM_CLOCKS) | 38 | if (cg >= CG_NUM_CLOCKS) |
41 | return; | 39 | return; |
42 | 40 | ||
43 | reg = &CLKCTL_CGR0 + cg / 16; /* Select CGR0, CGR1, CGR2 */ | 41 | reg = &CCM_CGR0 + cg / 16; /* Select CGR0, CGR1, CGR2 */ |
44 | shift = 2*(cg % 16); /* Get field shift */ | 42 | shift = 2*(cg % 16); /* Get field shift */ |
45 | mask = CG_MASK << shift; /* Select field */ | 43 | mask = CG_MASK << shift; /* Select field */ |
46 | 44 | ||
47 | oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS); | 45 | imx31_regmod32(reg, mode << shift, mask); |
48 | |||
49 | *reg = (*reg & ~mask) | ((mode << shift) & mask); | ||
50 | |||
51 | restore_interrupt(oldlevel); | ||
52 | } | 46 | } |
53 | 47 | ||
54 | /* Get the PLL reference clock frequency in HZ */ | 48 | /* Get the PLL reference clock frequency in HZ */ |
55 | unsigned int imx31_clkctl_get_pll_ref_clk(void) | 49 | unsigned int ccm_get_pll_ref_clk(void) |
56 | { | 50 | { |
57 | if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1)) | 51 | if ((CCM_CCMR & (3 << 1)) == (1 << 1)) |
58 | return CONFIG_CLK32_FREQ * 1024; | 52 | return CONFIG_CLK32_FREQ * 1024; |
59 | else | 53 | else |
60 | return CONFIG_HCLK_FREQ; | 54 | return CONFIG_HCLK_FREQ; |
61 | } | 55 | } |
62 | 56 | ||
63 | /* Return PLL frequency in HZ */ | 57 | /* Return PLL frequency in HZ */ |
64 | unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll) | 58 | unsigned int ccm_get_pll(enum IMX31_PLLS pll) |
65 | { | 59 | { |
66 | uint32_t infreq = imx31_clkctl_get_pll_ref_clk(); | 60 | uint32_t infreq = ccm_get_pll_ref_clk(); |
67 | uint32_t reg = (&CLKCTL_MPCTL)[pll]; | 61 | uint32_t reg = (&CCM_MPCTL)[pll]; |
68 | uint32_t mfn = reg & 0x3ff; | 62 | uint32_t mfn = reg & 0x3ff; |
69 | uint32_t pd = ((reg >> 26) & 0xf) + 1; | 63 | uint32_t pd = ((reg >> 26) & 0xf) + 1; |
70 | uint64_t mfd = ((reg >> 16) & 0x3ff) + 1; | 64 | uint64_t mfd = ((reg >> 16) & 0x3ff) + 1; |
@@ -75,27 +69,27 @@ unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll) | |||
75 | return 2*infreq*(mfi * mfd + mfn) / (mfd * pd); | 69 | return 2*infreq*(mfi * mfd + mfn) / (mfd * pd); |
76 | } | 70 | } |
77 | 71 | ||
78 | unsigned int imx31_clkctl_get_ipg_clk(void) | 72 | unsigned int ccm_get_ipg_clk(void) |
79 | { | 73 | { |
80 | unsigned int pllnum = imx31_get_src_pll(); | 74 | unsigned int pllnum = ccm_get_src_pll(); |
81 | unsigned int pll = imx31_clkctl_get_pll(pllnum); | 75 | unsigned int pll = ccm_get_pll(pllnum); |
82 | uint32_t reg = CLKCTL_PDR0; | 76 | uint32_t reg = CCM_PDR0; |
83 | unsigned int max_pdf = ((reg >> 3) & 0x7) + 1; | 77 | unsigned int max_pdf = ((reg >> 3) & 0x7) + 1; |
84 | unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1; | 78 | unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1; |
85 | 79 | ||
86 | return pll / (max_pdf * ipg_pdf); | 80 | return pll / (max_pdf * ipg_pdf); |
87 | } | 81 | } |
88 | 82 | ||
89 | unsigned int imx31_clkctl_get_ahb_clk(void) | 83 | unsigned int ccm_get_ahb_clk(void) |
90 | { | 84 | { |
91 | unsigned int pllnum = imx31_get_src_pll(); | 85 | unsigned int pllnum = ccm_get_src_pll(); |
92 | unsigned int pll = imx31_clkctl_get_pll(pllnum); | 86 | unsigned int pll = ccm_get_pll(pllnum); |
93 | unsigned int max_pdf = ((CLKCTL_PDR0 >> 3) & 0x7) + 1; | 87 | unsigned int max_pdf = ((CCM_PDR0 >> 3) & 0x7) + 1; |
94 | 88 | ||
95 | return pll / max_pdf; | 89 | return pll / max_pdf; |
96 | } | 90 | } |
97 | 91 | ||
98 | unsigned int imx31_clkctl_get_ata_clk(void) | 92 | unsigned int ccm_get_ata_clk(void) |
99 | { | 93 | { |
100 | return imx31_clkctl_get_ipg_clk(); | 94 | return ccm_get_ipg_clk(); |
101 | } | 95 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h index bd8f89a15b..e1057a9618 100644 --- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h +++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h | |||
@@ -20,8 +20,8 @@ | |||
20 | * KIND, either express or implied. | 20 | * KIND, either express or implied. |
21 | * | 21 | * |
22 | ****************************************************************************/ | 22 | ****************************************************************************/ |
23 | #ifndef _CLKCTL_IMX31_H_ | 23 | #ifndef _CCM_IMX31_H_ |
24 | #define _CLKCTL_IMX31_H_ | 24 | #define _CCM_IMX31_H_ |
25 | 25 | ||
26 | enum IMX31_CG_LIST | 26 | enum IMX31_CG_LIST |
27 | { | 27 | { |
@@ -82,8 +82,8 @@ enum IMX31_CG_MODES | |||
82 | 82 | ||
83 | /* Enable or disable module clocks independently - module must _not_ be | 83 | /* Enable or disable module clocks independently - module must _not_ be |
84 | * active! */ | 84 | * active! */ |
85 | void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg, | 85 | void ccm_module_clock_gating(enum IMX31_CG_LIST cg, |
86 | enum IMX31_CG_MODES mode); | 86 | enum IMX31_CG_MODES mode); |
87 | 87 | ||
88 | enum IMX31_PLLS | 88 | enum IMX31_PLLS |
89 | { | 89 | { |
@@ -97,18 +97,18 @@ enum IMX31_PLLS | |||
97 | #define CONFIG_HCLK_FREQ 27000000 | 97 | #define CONFIG_HCLK_FREQ 27000000 |
98 | 98 | ||
99 | /* Get the PLL reference clock frequency in HZ */ | 99 | /* Get the PLL reference clock frequency in HZ */ |
100 | unsigned int imx31_clkctl_get_pll_ref_clk(void); | 100 | unsigned int ccm_get_pll_ref_clk(void); |
101 | 101 | ||
102 | /* Return PLL frequency in HZ */ | 102 | /* Return PLL frequency in HZ */ |
103 | unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll); | 103 | unsigned int ccm_get_pll(enum IMX31_PLLS pll); |
104 | 104 | ||
105 | /* Return ipg_clk in HZ */ | 105 | /* Return ipg_clk in HZ */ |
106 | unsigned int imx31_clkctl_get_ipg_clk(void); | 106 | unsigned int ccm_get_ipg_clk(void); |
107 | 107 | ||
108 | /* Return ahb_clk in HZ */ | 108 | /* Return ahb_clk in HZ */ |
109 | unsigned int imx31_clkctl_get_ahb_clk(void); | 109 | unsigned int ccm_get_ahb_clk(void); |
110 | 110 | ||
111 | /* Return the ATA frequency in HZ */ | 111 | /* Return the ATA frequency in HZ */ |
112 | unsigned int imx31_clkctl_get_ata_clk(void); | 112 | unsigned int ccm_get_ata_clk(void); |
113 | 113 | ||
114 | #endif /* _CLKCTL_IMX31_H_ */ | 114 | #endif /* _CCM_IMX31_H_ */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c index 7646402435..d846f4d1d0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |||
@@ -50,22 +50,18 @@ void fmradio_i2c_init(void) | |||
50 | * disabled */ | 50 | * disabled */ |
51 | imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1, | 51 | imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1, |
52 | /* RI_DTE1 (I2C2_SCLK) */ | 52 | /* RI_DTE1 (I2C2_SCLK) */ |
53 | SW_PAD_CTL_IO2w(SW_PAD_CTL_PUE_PKE_DISABLE | | 53 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | |
54 | SW_PAD_CTL_PUS_UP_100K | | 54 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO2_POS) | |
55 | SW_PAD_CTL_HYS | | ||
56 | SW_PAD_CTL_ODE) | | ||
57 | /* DCD_DTE1 (I2C2_SDA) */ | 55 | /* DCD_DTE1 (I2C2_SDA) */ |
58 | SW_PAD_CTL_IO1w(SW_PAD_CTL_PUE_PKE_DISABLE | | 56 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | |
59 | SW_PAD_CTL_PUS_UP_100K | | 57 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO1_POS), |
60 | SW_PAD_CTL_HYS | | ||
61 | SW_PAD_CTL_ODE), | ||
62 | SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1); | 58 | SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1); |
63 | /* set outputs to I2C2 */ | 59 | /* set outputs to I2C2 */ |
64 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 60 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, |
65 | /* RI_DTE1 => I2C2_SCLK */ | 61 | /* RI_DTE1 => I2C2_SCLK */ |
66 | SW_MUX_CTL_SIG4w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) | | 62 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG4_POS) | |
67 | /* DCD_DTE1 => I2C2_SDA */ | 63 | /* DCD_DTE1 => I2C2_SDA */ |
68 | SW_MUX_CTL_SIG3w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2), | 64 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG3_POS), |
69 | SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3); | 65 | SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3); |
70 | } | 66 | } |
71 | 67 | ||
@@ -79,7 +75,8 @@ void fmradio_i2c_enable(bool enable) | |||
79 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ | 75 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ |
80 | /* I2C2_SDA => MCU2_15 */ | 76 | /* I2C2_SDA => MCU2_15 */ |
81 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 77 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, |
82 | SW_MUX_CTL_SIG3w(SW_MUX_OUT_GPIO_DR | SW_MUX_IN_GPIO_PSR_ISR), | 78 | (SW_MUX_OUT_GPIO_DR | |
79 | SW_MUX_IN_GPIO_PSR_ISR) << SW_MUX_CTL_SIG3_POS, | ||
83 | SW_MUX_CTL_SIG3); | 80 | SW_MUX_CTL_SIG3); |
84 | /* enable CLK32KMCU clock */ | 81 | /* enable CLK32KMCU clock */ |
85 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 82 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c index 446932b308..3d0ff977da 100644 --- a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c | |||
@@ -22,6 +22,7 @@ | |||
22 | ****************************************************************************/ | 22 | ****************************************************************************/ |
23 | #include "config.h" | 23 | #include "config.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "avic-imx31.h" | ||
25 | #include "gpio-imx31.h" | 26 | #include "gpio-imx31.h" |
26 | 27 | ||
27 | /* Gigabeat S definitions for static GPIO event registration */ | 28 | /* Gigabeat S definitions for static GPIO event registration */ |
@@ -44,7 +45,7 @@ static const struct gpio_event gpio1_events[] = | |||
44 | /* Describes the events attached to GPIO1 port */ | 45 | /* Describes the events attached to GPIO1 port */ |
45 | const struct gpio_event_list gpio1_event_list = | 46 | const struct gpio_event_list gpio1_event_list = |
46 | { | 47 | { |
47 | .ints_priority = 7, | 48 | .ints_priority = INT_PRIO_DEFAULT, |
48 | .count = ARRAYLEN(gpio1_events), | 49 | .count = ARRAYLEN(gpio1_events), |
49 | .events = gpio1_events, | 50 | .events = gpio1_events, |
50 | }; | 51 | }; |
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c index 090182bed4..944f70eae3 100644 --- a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c | |||
@@ -55,21 +55,21 @@ static struct gpio_module_descriptor | |||
55 | #if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS) | 55 | #if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS) |
56 | { | 56 | { |
57 | .base = (struct gpio_map *)GPIO1_BASE_ADDR, | 57 | .base = (struct gpio_map *)GPIO1_BASE_ADDR, |
58 | .ints = GPIO1, | 58 | .ints = INT_GPIO1, |
59 | .handler = GPIO1_HANDLER, | 59 | .handler = GPIO1_HANDLER, |
60 | }, | 60 | }, |
61 | #endif | 61 | #endif |
62 | #if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS) | 62 | #if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS) |
63 | { | 63 | { |
64 | .base = (struct gpio_map *)GPIO2_BASE_ADDR, | 64 | .base = (struct gpio_map *)GPIO2_BASE_ADDR, |
65 | .ints = GPIO2, | 65 | .ints = INT_GPIO2, |
66 | .handler = GPIO2_HANDLER, | 66 | .handler = GPIO2_HANDLER, |
67 | }, | 67 | }, |
68 | #endif | 68 | #endif |
69 | #if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS) | 69 | #if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS) |
70 | { | 70 | { |
71 | .base = (struct gpio_map *)GPIO3_BASE_ADDR, | 71 | .base = (struct gpio_map *)GPIO3_BASE_ADDR, |
72 | .ints = GPIO3, | 72 | .ints = INT_GPIO3, |
73 | .handler = GPIO3_HANDLER, | 73 | .handler = GPIO3_HANDLER, |
74 | }, | 74 | }, |
75 | #endif | 75 | #endif |
@@ -168,7 +168,7 @@ bool gpio_enable_event(enum gpio_event_ids id) | |||
168 | if (imr == 0) | 168 | if (imr == 0) |
169 | { | 169 | { |
170 | /* First enabled interrupt for this GPIO */ | 170 | /* First enabled interrupt for this GPIO */ |
171 | avic_enable_int(desc->ints, IRQ, desc->list->ints_priority, | 171 | avic_enable_int(desc->ints, INT_TYPE_IRQ, desc->list->ints_priority, |
172 | desc->handler); | 172 | desc->handler); |
173 | } | 173 | } |
174 | 174 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c index bf69afedb7..05d761c9ce 100644 --- a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c | |||
@@ -57,7 +57,7 @@ static struct i2c_module_descriptor | |||
57 | { | 57 | { |
58 | .base = (struct i2c_map *)I2C1_BASE_ADDR, | 58 | .base = (struct i2c_map *)I2C1_BASE_ADDR, |
59 | .cg = CG_I2C1, | 59 | .cg = CG_I2C1, |
60 | .ints = I2C1, | 60 | .ints = INT_I2C1, |
61 | .handler = I2C1_HANDLER, | 61 | .handler = I2C1_HANDLER, |
62 | }, | 62 | }, |
63 | #endif | 63 | #endif |
@@ -65,7 +65,7 @@ static struct i2c_module_descriptor | |||
65 | { | 65 | { |
66 | .base = (struct i2c_map *)I2C2_BASE_ADDR, | 66 | .base = (struct i2c_map *)I2C2_BASE_ADDR, |
67 | .cg = CG_I2C2, | 67 | .cg = CG_I2C2, |
68 | .ints = I2C2, | 68 | .ints = INT_I2C2, |
69 | .handler = I2C2_HANDLER, | 69 | .handler = I2C2_HANDLER, |
70 | }, | 70 | }, |
71 | #endif | 71 | #endif |
@@ -73,7 +73,7 @@ static struct i2c_module_descriptor | |||
73 | { | 73 | { |
74 | .base = (struct i2c_map *)I2C3_BASE_ADDR, | 74 | .base = (struct i2c_map *)I2C3_BASE_ADDR, |
75 | .cg = CG_I2C3, | 75 | .cg = CG_I2C3, |
76 | .ints = I2C3, | 76 | .ints = INT_I2C3, |
77 | .handler = I2C3_HANDLER, | 77 | .handler = I2C3_HANDLER, |
78 | }, | 78 | }, |
79 | #endif | 79 | #endif |
@@ -286,11 +286,11 @@ void i2c_init(void) | |||
286 | for (i = 0; i < I2C_NUM_I2C; i++) | 286 | for (i = 0; i < I2C_NUM_I2C; i++) |
287 | { | 287 | { |
288 | struct i2c_module_descriptor *const desc = &i2c_descs[i]; | 288 | struct i2c_module_descriptor *const desc = &i2c_descs[i]; |
289 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); | 289 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); |
290 | mutex_init(&desc->m); | 290 | mutex_init(&desc->m); |
291 | wakeup_init(&desc->w); | 291 | wakeup_init(&desc->w); |
292 | desc->base->i2cr = 0; | 292 | desc->base->i2cr = 0; |
293 | imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF); | 293 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
294 | } | 294 | } |
295 | } | 295 | } |
296 | 296 | ||
@@ -305,8 +305,9 @@ void i2c_enable_node(struct i2c_node *node, bool enable) | |||
305 | if (++desc->enable == 1) | 305 | if (++desc->enable == 1) |
306 | { | 306 | { |
307 | /* First enable */ | 307 | /* First enable */ |
308 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); | 308 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); |
309 | avic_enable_int(desc->ints, IRQ, 7, desc->handler); | 309 | avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
310 | desc->handler); | ||
310 | } | 311 | } |
311 | } | 312 | } |
312 | else | 313 | else |
@@ -317,7 +318,7 @@ void i2c_enable_node(struct i2c_node *node, bool enable) | |||
317 | while (desc->base->i2sr & I2C_I2SR_IBB); /* Wait for STOP */ | 318 | while (desc->base->i2sr & I2C_I2SR_IBB); /* Wait for STOP */ |
318 | desc->base->i2cr &= ~I2C_I2CR_IEN; | 319 | desc->base->i2cr &= ~I2C_I2CR_IEN; |
319 | avic_disable_int(desc->ints); | 320 | avic_disable_int(desc->ints); |
320 | imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF); | 321 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
321 | } | 322 | } |
322 | } | 323 | } |
323 | 324 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c index a2f3d779eb..01e9b8b721 100644 --- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c | |||
@@ -38,11 +38,11 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void) | |||
38 | 38 | ||
39 | void tick_start(unsigned int interval_in_ms) | 39 | void tick_start(unsigned int interval_in_ms) |
40 | { | 40 | { |
41 | imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_ON_ALL); /* EPIT1 module | 41 | ccm_module_clock_gating(CG_EPIT1, CGM_ON_RUN_WAIT); /* EPIT1 module |
42 | clock ON - before writing | 42 | clock ON - before writing |
43 | regs! */ | 43 | regs! */ |
44 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */ | 44 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */ |
45 | CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT1; /* Clear wakeup mask */ | 45 | CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT1; /* Clear wakeup mask */ |
46 | 46 | ||
47 | /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1) | 47 | /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1) |
48 | * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz, | 48 | * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz, |
@@ -53,13 +53,14 @@ void tick_start(unsigned int interval_in_ms) | |||
53 | * Compare interrupt enabled, | 53 | * Compare interrupt enabled, |
54 | * Count from load value */ | 54 | * Count from load value */ |
55 | EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | | 55 | EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | |
56 | EPITCR_PRESCALER(2640-1) | EPITCR_RLD | EPITCR_OCIEN | | 56 | (2640-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_OCIEN | |
57 | EPITCR_ENMOD; | 57 | EPITCR_ENMOD; |
58 | 58 | ||
59 | EPITLR1 = interval_in_ms*25; /* Count down from interval */ | 59 | EPITLR1 = interval_in_ms*25; /* Count down from interval */ |
60 | EPITCMPR1 = 0; /* Event when counter reaches 0 */ | 60 | EPITCMPR1 = 0; /* Event when counter reaches 0 */ |
61 | EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */ | 61 | EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */ |
62 | avic_enable_int(EPIT1, IRQ, 7, EPIT1_HANDLER); | 62 | avic_enable_int(INT_EPIT1, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
63 | EPIT1_HANDLER); | ||
63 | EPITCR1 |= EPITCR_EN; /* Enable the counter */ | 64 | EPITCR1 |= EPITCR_EN; /* Enable the counter */ |
64 | } | 65 | } |
65 | 66 | ||
@@ -73,9 +74,9 @@ void kernel_device_init(void) | |||
73 | #ifdef BOOTLOADER | 74 | #ifdef BOOTLOADER |
74 | void tick_stop(void) | 75 | void tick_stop(void) |
75 | { | 76 | { |
76 | avic_disable_int(EPIT1); /* Disable insterrupt */ | 77 | avic_disable_int(INT_EPIT1); /* Disable insterrupt */ |
77 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */ | 78 | EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */ |
78 | EPITSR1 = EPITSR_OCIF; /* Clear pending */ | 79 | EPITSR1 = EPITSR_OCIF; /* Clear pending */ |
79 | imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */ | 80 | ccm_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */ |
80 | } | 81 | } |
81 | #endif | 82 | #endif |
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c index deaa2a0dcd..00f196a512 100644 --- a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c | |||
@@ -130,8 +130,8 @@ void pcm_play_dma_init(void) | |||
130 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); | 130 | sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd); |
131 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); | 131 | sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY); |
132 | 132 | ||
133 | imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL); | 133 | ccm_module_clock_gating(CG_SSI1, CGM_ON_RUN_WAIT); |
134 | imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL); | 134 | ccm_module_clock_gating(CG_SSI2, CGM_ON_RUN_WAIT); |
135 | 135 | ||
136 | /* Reset & disable SSIs */ | 136 | /* Reset & disable SSIs */ |
137 | SSI_SCR1 &= ~SSI_SCR_SSIEN; | 137 | SSI_SCR1 &= ~SSI_SCR_SSIEN; |
@@ -178,12 +178,12 @@ void pcm_play_dma_init(void) | |||
178 | SSI_STCR_TEFS | SSI_STCR_TFEN0; | 178 | SSI_STCR_TEFS | SSI_STCR_TFEN0; |
179 | 179 | ||
180 | /* 16 bits per word, 2 words per frame */ | 180 | /* 16 bits per word, 2 words per frame */ |
181 | SSI_STCCR2 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | | 181 | SSI_STCCR2 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) | |
182 | SSI_STRCCR_PMw(4-1); | 182 | ((4-1) << SSI_STRCCR_PM_POS); |
183 | 183 | ||
184 | /* Transmit low watermark */ | 184 | /* Transmit low watermark */ |
185 | SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_TFWM0) | | 185 | SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_TFWM0) | |
186 | SSI_SFCSR_TFWM0w(8-SDMA_SSI_TXFIFO_WML); | 186 | ((8-SDMA_SSI_TXFIFO_WML) << SSI_SFCSR_TFWM0_POS); |
187 | SSI_STMSK2 = 0; | 187 | SSI_STMSK2 = 0; |
188 | 188 | ||
189 | /* SSI1 - provides MCLK to codec. Receives data from codec. */ | 189 | /* SSI1 - provides MCLK to codec. Receives data from codec. */ |
@@ -201,7 +201,7 @@ void pcm_play_dma_init(void) | |||
201 | * The hardware seems to force a divide by 4 even if all bits are | 201 | * The hardware seems to force a divide by 4 even if all bits are |
202 | * zero but comply by setting DIV2 and the others to zero. | 202 | * zero but comply by setting DIV2 and the others to zero. |
203 | */ | 203 | */ |
204 | SSI_STCCR1 = SSI_STRCCR_DIV2 | SSI_STRCCR_PMw(1-1); | 204 | SSI_STCCR1 = SSI_STRCCR_DIV2 | ((1-1) << SSI_STRCCR_PM_POS); |
205 | 205 | ||
206 | /* SSI1 - receive - asynchronous clocks */ | 206 | /* SSI1 - receive - asynchronous clocks */ |
207 | SSI_SCR1 = SSI_SCR_I2S_MODE_SLAVE; | 207 | SSI_SCR1 = SSI_SCR_I2S_MODE_SLAVE; |
@@ -210,12 +210,12 @@ void pcm_play_dma_init(void) | |||
210 | SSI_SRCR_REFS; | 210 | SSI_SRCR_REFS; |
211 | 211 | ||
212 | /* 16 bits per word, 2 words per frame */ | 212 | /* 16 bits per word, 2 words per frame */ |
213 | SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) | | 213 | SSI_SRCCR1 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) | |
214 | SSI_STRCCR_PMw(4-1); | 214 | ((4-1) << SSI_STRCCR_PM_POS); |
215 | 215 | ||
216 | /* Receive high watermark */ | 216 | /* Receive high watermark */ |
217 | SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_RFWM0) | | 217 | SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_RFWM0) | |
218 | SSI_SFCSR_RFWM0w(SDMA_SSI_RXFIFO_WML); | 218 | (SDMA_SSI_RXFIFO_WML << SSI_SFCSR_RFWM0_POS); |
219 | SSI_SRMSK1 = 0; | 219 | SSI_SRMSK1 = 0; |
220 | 220 | ||
221 | /* Enable SSI1 (codec clock) */ | 221 | /* Enable SSI1 (codec clock) */ |
@@ -252,7 +252,7 @@ static void play_start_pcm(void) | |||
252 | static void play_stop_pcm(void) | 252 | static void play_stop_pcm(void) |
253 | { | 253 | { |
254 | /* Wait for FIFO to empty */ | 254 | /* Wait for FIFO to empty */ |
255 | while (SSI_SFCSR_TFCNT0r(SSI_SFCSR2) > 0); | 255 | while (SSI_SFCSR_TFCNT0 & SSI_SFCSR2); |
256 | 256 | ||
257 | /* Disable transmission */ | 257 | /* Disable transmission */ |
258 | SSI_STCR2 &= ~SSI_STCR_TFEN0; | 258 | SSI_STCR2 &= ~SSI_STCR_TFEN0; |
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c index 98604d1eef..f905057372 100644 --- a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c | |||
@@ -58,7 +58,7 @@ static struct spi_module_descriptor | |||
58 | { | 58 | { |
59 | .base = (struct cspi_map *)CSPI1_BASE_ADDR, | 59 | .base = (struct cspi_map *)CSPI1_BASE_ADDR, |
60 | .cg = CG_CSPI1, | 60 | .cg = CG_CSPI1, |
61 | .ints = CSPI1, | 61 | .ints = INT_CSPI1, |
62 | .handler = CSPI1_HANDLER, | 62 | .handler = CSPI1_HANDLER, |
63 | }, | 63 | }, |
64 | #endif | 64 | #endif |
@@ -66,7 +66,7 @@ static struct spi_module_descriptor | |||
66 | { | 66 | { |
67 | .base = (struct cspi_map *)CSPI2_BASE_ADDR, | 67 | .base = (struct cspi_map *)CSPI2_BASE_ADDR, |
68 | .cg = CG_CSPI2, | 68 | .cg = CG_CSPI2, |
69 | .ints = CSPI2, | 69 | .ints = INT_CSPI2, |
70 | .handler = CSPI2_HANDLER, | 70 | .handler = CSPI2_HANDLER, |
71 | }, | 71 | }, |
72 | #endif | 72 | #endif |
@@ -74,7 +74,7 @@ static struct spi_module_descriptor | |||
74 | { | 74 | { |
75 | .base = (struct cspi_map *)CSPI3_BASE_ADDR, | 75 | .base = (struct cspi_map *)CSPI3_BASE_ADDR, |
76 | .cg = CG_CSPI3, | 76 | .cg = CG_CSPI3, |
77 | .ints = CSPI3, | 77 | .ints = INT_CSPI3, |
78 | .handler = CSPI3_HANDLER, | 78 | .handler = CSPI3_HANDLER, |
79 | }, | 79 | }, |
80 | #endif | 80 | #endif |
@@ -267,12 +267,13 @@ void spi_enable_module(struct spi_node *node) | |||
267 | struct cspi_map * const base = desc->base; | 267 | struct cspi_map * const base = desc->base; |
268 | 268 | ||
269 | /* Enable clock-gating register */ | 269 | /* Enable clock-gating register */ |
270 | imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL); | 270 | ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT); |
271 | /* Reset */ | 271 | /* Reset */ |
272 | spi_reset(base); | 272 | spi_reset(base); |
273 | desc->last = NULL; | 273 | desc->last = NULL; |
274 | /* Enable interrupt at controller level */ | 274 | /* Enable interrupt at controller level */ |
275 | avic_enable_int(desc->ints, IRQ, 6, desc->handler); | 275 | avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
276 | desc->handler); | ||
276 | } | 277 | } |
277 | 278 | ||
278 | mutex_unlock(&desc->m); | 279 | mutex_unlock(&desc->m); |
@@ -297,7 +298,7 @@ void spi_disable_module(struct spi_node *node) | |||
297 | base->conreg &= ~CSPI_CONREG_EN; | 298 | base->conreg &= ~CSPI_CONREG_EN; |
298 | 299 | ||
299 | /* Disable interface clock */ | 300 | /* Disable interface clock */ |
300 | imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF); | 301 | ccm_module_clock_gating(desc->cg, CGM_OFF); |
301 | } | 302 | } |
302 | 303 | ||
303 | mutex_unlock(&desc->m); | 304 | mutex_unlock(&desc->m); |
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c index b3f0fd66c9..c710c5b93c 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c | |||
@@ -49,7 +49,7 @@ unsigned int iim_prod_rev(void) | |||
49 | static void iim_init(void) | 49 | static void iim_init(void) |
50 | { | 50 | { |
51 | /* Initialize the IC revision info (required by SDMA) */ | 51 | /* Initialize the IC revision info (required by SDMA) */ |
52 | imx31_clkctl_module_clock_gating(CG_IIM, CGM_ON_ALL); | 52 | ccm_module_clock_gating(CG_IIM, CGM_ON_RUN_WAIT); |
53 | product_rev = IIM_PREV; | 53 | product_rev = IIM_PREV; |
54 | system_rev = IIM_SREV; | 54 | system_rev = IIM_SREV; |
55 | } | 55 | } |
@@ -59,13 +59,13 @@ static void iim_init(void) | |||
59 | /* Initialize the watchdog timer */ | 59 | /* Initialize the watchdog timer */ |
60 | void watchdog_init(unsigned int half_seconds) | 60 | void watchdog_init(unsigned int half_seconds) |
61 | { | 61 | { |
62 | uint16_t wcr = WDOG_WCR_WTw(half_seconds) | /* Timeout */ | 62 | uint16_t wcr = ((half_seconds << WDOG_WCR_WT_POS) & WDOG_WCR_WT) | |
63 | WDOG_WCR_WOE | /* WDOG output enabled */ | 63 | WDOG_WCR_WOE | /* WDOG output enabled */ |
64 | WDOG_WCR_WDA | /* WDOG assertion - no effect */ | 64 | WDOG_WCR_WDA | /* WDOG assertion - no effect */ |
65 | WDOG_WCR_SRS | /* System reset - no effect */ | 65 | WDOG_WCR_SRS | /* System reset - no effect */ |
66 | WDOG_WCR_WRE; /* Generate a WDOG signal */ | 66 | WDOG_WCR_WRE; /* Generate a WDOG signal */ |
67 | 67 | ||
68 | imx31_clkctl_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT); | 68 | ccm_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT); |
69 | 69 | ||
70 | WDOG_WCR = wcr; | 70 | WDOG_WCR = wcr; |
71 | WDOG_WSR = 0x5555; | 71 | WDOG_WSR = 0x5555; |
@@ -86,8 +86,8 @@ void watchdog_service(void) | |||
86 | /* Start the general-purpose timer (1MHz) */ | 86 | /* Start the general-purpose timer (1MHz) */ |
87 | void gpt_start(void) | 87 | void gpt_start(void) |
88 | { | 88 | { |
89 | imx31_clkctl_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT); | 89 | ccm_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT); |
90 | unsigned int ipg_mhz = imx31_clkctl_get_ipg_clk() / 1000000; | 90 | unsigned int ipg_mhz = ccm_get_ipg_clk() / 1000000; |
91 | 91 | ||
92 | GPTCR &= ~GPTCR_EN; /* Disable counter */ | 92 | GPTCR &= ~GPTCR_EN; /* Disable counter */ |
93 | GPTCR |= GPTCR_SWR; /* Reset module */ | 93 | GPTCR |= GPTCR_SWR; /* Reset module */ |
@@ -123,7 +123,7 @@ void system_reboot(void) | |||
123 | void system_exception_wait(void) | 123 | void system_exception_wait(void) |
124 | { | 124 | { |
125 | /* Called in many contexts so button reading may be a chore */ | 125 | /* Called in many contexts so button reading may be a chore */ |
126 | avic_disable_int(ALL); | 126 | avic_disable_int(INT_ALL); |
127 | core_idle(); | 127 | core_idle(); |
128 | while (1); | 128 | while (1); |
129 | } | 129 | } |
@@ -174,8 +174,8 @@ void system_init(void) | |||
174 | 174 | ||
175 | unsigned int i; | 175 | unsigned int i; |
176 | 176 | ||
177 | /* MCR WFI enables wait mode */ | 177 | /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */ |
178 | CLKCTL_CCMR &= ~(3 << 14); | 178 | imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM); |
179 | 179 | ||
180 | iim_init(); | 180 | iim_init(); |
181 | 181 | ||
@@ -189,7 +189,7 @@ void system_init(void) | |||
189 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); | 189 | imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN); |
190 | 190 | ||
191 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) | 191 | for (i = 0; i < ARRAYLEN(disable_clocks); i++) |
192 | imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF); | 192 | ccm_module_clock_gating(disable_clocks[i], CGM_OFF); |
193 | 193 | ||
194 | avic_init(); | 194 | avic_init(); |
195 | gpt_start(); | 195 | gpt_start(); |
@@ -242,7 +242,7 @@ void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p, | |||
242 | void system_prepare_fw_start(void) | 242 | void system_prepare_fw_start(void) |
243 | { | 243 | { |
244 | disable_interrupt(IRQ_FIQ_STATUS); | 244 | disable_interrupt(IRQ_FIQ_STATUS); |
245 | avic_disable_int(ALL); | 245 | avic_disable_int(INT_ALL); |
246 | mc13783_close(); | 246 | mc13783_close(); |
247 | tick_stop(); | 247 | tick_stop(); |
248 | } | 248 | } |
diff --git a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c index 531baf3cc5..c4734a543b 100644 --- a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c | |||
@@ -35,11 +35,11 @@ static void __attribute__((interrupt("IRQ"))) EPIT2_HANDLER(void) | |||
35 | static void stop_timer(bool clock_off) | 35 | static void stop_timer(bool clock_off) |
36 | { | 36 | { |
37 | /* Ensure clock gating on (before touching any module registers) */ | 37 | /* Ensure clock gating on (before touching any module registers) */ |
38 | imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_ON_ALL); | 38 | ccm_module_clock_gating(CG_EPIT2, CGM_ON_RUN_WAIT); |
39 | /* Disable insterrupt */ | 39 | /* Disable insterrupt */ |
40 | avic_disable_int(EPIT2); | 40 | avic_disable_int(INT_EPIT2); |
41 | /* Clear wakeup mask */ | 41 | /* Clear wakeup mask */ |
42 | CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT2; | 42 | CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT2; |
43 | /* Disable counter */ | 43 | /* Disable counter */ |
44 | EPITCR2 &= ~(EPITCR_OCIEN | EPITCR_EN); | 44 | EPITCR2 &= ~(EPITCR_OCIEN | EPITCR_EN); |
45 | /* Clear pending */ | 45 | /* Clear pending */ |
@@ -48,7 +48,7 @@ static void stop_timer(bool clock_off) | |||
48 | if (clock_off) | 48 | if (clock_off) |
49 | { | 49 | { |
50 | /* Final stop, not reset; don't clock module any longer */ | 50 | /* Final stop, not reset; don't clock module any longer */ |
51 | imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_OFF); | 51 | ccm_module_clock_gating(CG_EPIT2, CGM_OFF); |
52 | } | 52 | } |
53 | } | 53 | } |
54 | 54 | ||
@@ -77,7 +77,7 @@ bool _timer_set(long cycles, bool start) | |||
77 | * Reload from modulus register, | 77 | * Reload from modulus register, |
78 | * Count from load value */ | 78 | * Count from load value */ |
79 | EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | | 79 | EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW | |
80 | EPITCR_PRESCALER(1-1) | EPITCR_RLD | EPITCR_ENMOD; | 80 | (1-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_ENMOD; |
81 | EPITLR2 = cycles; | 81 | EPITLR2 = cycles; |
82 | /* Event when counter reaches 0 */ | 82 | /* Event when counter reaches 0 */ |
83 | EPITCMPR2 = 0; | 83 | EPITCMPR2 = 0; |
@@ -95,7 +95,8 @@ bool _timer_register(void) | |||
95 | 95 | ||
96 | /* Enable interrupt */ | 96 | /* Enable interrupt */ |
97 | EPITCR2 |= EPITCR_OCIEN; | 97 | EPITCR2 |= EPITCR_OCIEN; |
98 | avic_enable_int(EPIT2, IRQ, 8, EPIT2_HANDLER); | 98 | avic_enable_int(INT_EPIT2, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
99 | EPIT2_HANDLER); | ||
99 | /* Start timer */ | 100 | /* Start timer */ |
100 | EPITCR2 |= EPITCR_EN; | 101 | EPITCR2 |= EPITCR_EN; |
101 | 102 | ||
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c index 8682cff7c7..2011d0c633 100644 --- a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c | |||
@@ -89,7 +89,7 @@ void usb_enable(bool on) | |||
89 | { | 89 | { |
90 | /* Module clock should be on since since this could be called with | 90 | /* Module clock should be on since since this could be called with |
91 | * OFF initially and writing module registers would hardlock otherwise. */ | 91 | * OFF initially and writing module registers would hardlock otherwise. */ |
92 | imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_ON_ALL); | 92 | ccm_module_clock_gating(CG_USBOTG, CGM_ON_RUN_WAIT); |
93 | enable_transceiver(true); | 93 | enable_transceiver(true); |
94 | 94 | ||
95 | if (on) | 95 | if (on) |
@@ -100,7 +100,7 @@ void usb_enable(bool on) | |||
100 | { | 100 | { |
101 | usb_core_exit(); | 101 | usb_core_exit(); |
102 | enable_transceiver(false); | 102 | enable_transceiver(false); |
103 | imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_OFF); | 103 | ccm_module_clock_gating(CG_USBOTG, CGM_OFF); |
104 | } | 104 | } |
105 | } | 105 | } |
106 | 106 | ||
@@ -117,9 +117,14 @@ static void __attribute__((interrupt("IRQ"))) USB_OTG_HANDLER(void) | |||
117 | void usb_drv_int_enable(bool enable) | 117 | void usb_drv_int_enable(bool enable) |
118 | { | 118 | { |
119 | if (enable) | 119 | if (enable) |
120 | avic_enable_int(USB_OTG, IRQ, 7, USB_OTG_HANDLER); | 120 | { |
121 | else | 121 | avic_enable_int(INT_USB_OTG, INT_TYPE_IRQ, INT_PRIO_DEFAULT, |
122 | avic_disable_int(USB_OTG); | 122 | USB_OTG_HANDLER); |
123 | } | ||
124 | else | ||
125 | { | ||
126 | avic_disable_int(INT_USB_OTG); | ||
127 | } | ||
123 | } | 128 | } |
124 | 129 | ||
125 | /* Called during the bus reset interrupt when in detect mode */ | 130 | /* Called during the bus reset interrupt when in detect mode */ |
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c index 542f6eb633..cf9331144a 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c | |||
@@ -52,11 +52,13 @@ void audiohw_init(void) | |||
52 | * WM Codec post divider (MCLKDIV=1.5): | 52 | * WM Codec post divider (MCLKDIV=1.5): |
53 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK | 53 | * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK |
54 | */ | 54 | */ |
55 | imx31_regmod32(&CLKCTL_PDR1, | 55 | imx31_regmod32(&CCM_PDR1, |
56 | PDR1_SSI1_PODFw(5-1) | PDR1_SSI2_PODFw(64-1) | | 56 | (1-1) << CCM_PDR1_SSI1_PRE_PODF_POS | |
57 | PDR1_SSI1_PRE_PODFw(1-1) | PDR1_SSI2_PRE_PODFw(8-1), | 57 | (5-1) << CCM_PDR1_SSI1_PODF_POS | |
58 | PDR1_SSI1_PODF | PDR1_SSI2_PODF | | 58 | (8-1) << CCM_PDR1_SSI2_PRE_PODF_POS, |
59 | PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF); | 59 | (64-1) << CCM_PDR1_SSI2_PODF_POS | |
60 | CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF | | ||
61 | CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF); | ||
60 | 62 | ||
61 | i2c_enable_node(&wm8978_i2c_node, true); | 63 | i2c_enable_node(&wm8978_i2c_node, true); |
62 | 64 | ||
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c index 4c5674afb9..97af419077 100644 --- a/firmware/target/arm/imx31/sdma-imx31.c +++ b/firmware/target/arm/imx31/sdma-imx31.c | |||
@@ -502,10 +502,11 @@ static bool setup_channel(struct channel_control_block *ccb_p) | |||
502 | /** Public routines **/ | 502 | /** Public routines **/ |
503 | void sdma_init(void) | 503 | void sdma_init(void) |
504 | { | 504 | { |
505 | imx31_clkctl_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT); | ||
506 | int i; | 505 | int i; |
507 | unsigned long acr; | 506 | unsigned long acr; |
508 | 507 | ||
508 | ccm_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT); | ||
509 | |||
509 | /* Reset the controller */ | 510 | /* Reset the controller */ |
510 | SDMA_RESET |= SDMA_RESET_RESET; | 511 | SDMA_RESET |= SDMA_RESET_RESET; |
511 | while (SDMA_RESET & SDMA_RESET_RESET); | 512 | while (SDMA_RESET & SDMA_RESET_RESET); |
@@ -532,11 +533,11 @@ void sdma_init(void) | |||
532 | /* 32-word channel contexts, use default bootscript address */ | 533 | /* 32-word channel contexts, use default bootscript address */ |
533 | SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050; | 534 | SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050; |
534 | 535 | ||
535 | avic_enable_int(SDMA, IRQ, 8, SDMA_HANDLER); | 536 | avic_enable_int(INT_SDMA, INT_TYPE_IRQ, INT_PRIO_DEFAULT+1, SDMA_HANDLER); |
536 | 537 | ||
537 | /* SDMA core must run at the proper frequency based upon the AHB/IPG ratio */ | 538 | /* SDMA core must run at the proper frequency based upon the AHB/IPG |
538 | acr = (imx31_clkctl_get_ahb_clk() / imx31_clkctl_get_ipg_clk()) < 2 ? | 539 | * ratio */ |
539 | SDMA_CONFIG_ACR : 0; | 540 | acr = (ccm_get_ahb_clk() / ccm_get_ipg_clk()) < 2 ? SDMA_CONFIG_ACR : 0; |
540 | 541 | ||
541 | /* No dsp, no debug | 542 | /* No dsp, no debug |
542 | * Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0 | 543 | * Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0 |