23 files changed, 465 insertions, 596 deletions

diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index ea2187e0c2..2c1e93e528 100755
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -247,10 +247,10 @@
 #define SW_MUX_CTL_SIG3         (0x7f << 16)
 #define SW_MUX_CTL_SIG4         (0x7f << 24)
 /* Shift above flags into one of the four fields in each register */
-#define SW_MUX_CTL_SIG1w(x)     (((x) <<  0) & SW_MUX_CTL_SIG1)
-#define SW_MUX_CTL_SIG2w(x)     (((x) <<  8) & SW_MUX_CTL_SIG2)
-#define SW_MUX_CTL_SIG3w(x)     (((x) << 16) & SW_MUX_CTL_SIG3)
-#define SW_MUX_CTL_SIG4w(x)     (((x) << 24) & SW_MUX_CTL_SIG4)
+#define SW_MUX_CTL_SIG1_POS     (0)
+#define SW_MUX_CTL_SIG2_POS     (8)
+#define SW_MUX_CTL_SIG3_POS     (16)
+#define SW_MUX_CTL_SIG4_POS     (24)
 
 /* SW_PAD_CTL */
 #define SW_PAD_CTL_TTM_PAD__X__X                            IOMUXC_(0x154)
@@ -395,9 +395,9 @@
 #define SW_PAD_CTL_IO3                  (0x3ff << 20)
 
 /* Shift above flags into one of the three fields in each register */
-#define SW_PAD_CTL_IO1w(x)              (((x) <<  0) & SW_PAD_CTL_IO1)
-#define SW_PAD_CTL_IO2w(x)              (((x) << 10) & SW_PAD_CTL_IO2)
-#define SW_PAD_CTL_IO3w(x)              (((x) << 20) & SW_PAD_CTL_IO3)
+#define SW_PAD_CTL_IO1_POS              (0)
+#define SW_PAD_CTL_IO2_POS              (10)
+#define SW_PAD_CTL_IO3_POS              (20)
 
 /* RNGA */
 #define RNGA_CONTROL            (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
@@ -530,7 +530,8 @@
 #define EPITCR_DBGEN                    (1 << 18)
 #define EPITCR_IOVW                     (1 << 17)
 #define EPITCR_SWR                      (1 << 16)
-#define EPITCR_PRESCALER(n)             ((n) << 4) /* Divide by n+1 */
+#define EPITCR_PRESCALER                (0xfff << 4) /* Divide by n+1 */
+#define EPITCR_PRESCALER_POS            (4)
 #define EPITCR_RLD                      (1 << 3)
 #define EPITCR_OCIEN                    (1 << 2)
 #define EPITCR_ENMOD                    (1 << 1)
@@ -933,10 +934,10 @@
 #define AUDMUX_CNMCR_CLKPOL         (1 << 16)
 
 #define AUDMUX_CNMCR_CNTHI          (0xff << 8)
-#define AUDMUX_CNMCR_CNTHIw(x)      (((x) << 8) & AUDMUX_CNMCR_CNTHI)
+#define AUDMUX_CNMCR_CNTHI_POS      (8)
 
 #define AUDMUX_CNMCR_CNTLOW         (0xff << 0)
-#define AUDMUX_CNMCR_CNTLOWw(x)     (((x) << 0) & AUDMUX_CNMCR_CNTLOW)
+#define AUDMUX_CNMCR_CNTLOW_POS     (0)
 
 /* SSI */
 #define SSI_STX0_1              (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
@@ -1080,57 +1081,39 @@
 #define SSI_STRCCR_WL24         (0xb << 13)
 
 #define SSI_STRCCR_DC           (0x1f << 8)
-#define SSI_STRCCR_DCw(x)       (((x) << 8) & SSI_STRCCR_DC)
-#define SSI_STRCCR_DCr(x)       (((x) & SSI_SRCCR_DC) >> 8)
+#define SSI_STRCCR_DC_POS       (8)
 
 #define SSI_STRCCR_PM           (0xf << 0)
-#define SSI_STRCCR_PMw(x)       (((x) << 0) & SSI_STRCCR_PM)
-#define SSI_STRCCR_PMr(x)       (((x) & SSI_SRCCR_PM) >> 0)
+#define SSI_STRCCR_PM_POS       (0)
 
 /* SSI SFCSR */
 #define SSI_SFCSR_RFCNT1        (0xf << 28)
-#define SSI_SFCSR_RFCNT1w(x)    (((x) << 28) & SSI_SFCSR_RFCNT1)
-#define SSI_SFCSR_RFCNT1r(x)    (((x) & SSI_SFCSR_RFCNT1) >> 28)
+#define SSI_SFCSR_RFCNT1_POS    (28)
 
 #define SSI_SFCSR_TFCNT1        (0xf << 24)
-#define SSI_SFCSR_TFCNT1w(x)    (((x) << 24) & SSI_SFCSR_TFCNT1)
-#define SSI_SFCSR_TFCNT1r(x)    (((x) & SSI_SFCSR_TFCNT1) >> 24)
+#define SSI_SFCSR_TFCNN1_POS    (24)
 
 #define SSI_SFCSR_RFWM1         (0xf << 20)
-#define SSI_SFCSR_RFWM1w(x)     (((x) << 20) & SSI_SFCSR_RFWM1)
-#define SSI_SFCSR_RFWM1r(x)     (((x) & SSI_SFCSR_RFWM1) >> 20)
-#define SSI_SFCSR_RFWM1_1       (0x1 << 20)
-#define SSI_SFCSR_RFWM1_2       (0x2 << 20)
-#define SSI_SFCSR_RFWM1_3       (0x3 << 20)
-#define SSI_SFCSR_RFWM1_4       (0x4 << 20)
-#define SSI_SFCSR_RFWM1_5       (0x5 << 20)
-#define SSI_SFCSR_RFWM1_6       (0x6 << 20)
-#define SSI_SFCSR_RFWM1_7       (0x7 << 20)
+#define SSI_SFCSR_RFWM1_POS     (20)
 
 #define SSI_SFCSR_TFWM1         (0xf << 16)
-#define SSI_SFCSR_TFWM1w(x)     (((x) << 16) & SSI_SFCSR_TFWM1)
-#define SSI_SFCSR_TFWM1r(x)     (((x) & SSI_SFCSR_TFWM1) >> 16)
+#define SSI_SFCSR_TFWM1_POS     (16)
 
 #define SSI_SFCSR_RFCNT0        (0xf << 12)
-#define SSI_SFCSR_RFCNT0w(x)    (((x) << 12) & SSI_SFCSR_RFCNT0)
-#define SSI_SFCSR_RFCNT0r(x)    (((x) & SSI_SFCSR_RFCNT0) >> 12)
+#define SSI_SFCSR_RFCNT0_POS    (12)
 
 #define SSI_SFCSR_TFCNT0        (0xf << 8)
-#define SSI_SFCSR_TFCNT0w(x)    (((x) << 8) & SSI_SFCSR_TFCNT0)
-#define SSI_SFCSR_TFCNT0r(x)    (((x) & SSI_SFCSR_TFCNT0) >> 8)
+#define SSI_SFCSR_TFCNT0_POS    (8)
 
 #define SSI_SFCSR_RFWM0         (0xf << 4)
-#define SSI_SFCSR_RFWM0w(x)     (((x) << 4) & SSI_SFCSR_RFWM0)
-#define SSI_SFCSR_RFWM0r(x)     (((x) & SSI_SFCSR_RFWM0) >> 4)
+#define SSI_SFCSR_RFWM0_POS     (4)
 
 #define SSI_SFCSR_TFWM0         (0xf << 0)
-#define SSI_SFCSR_TFWM0w(x)     (((x) << 0) & SSI_SFCSR_TFWM0)
-#define SSI_SFCSR_TFWM0r(x)     (((x) & SSI_SFCSR_TFWM0) >> 0)
+#define SSI_SFCSR_TFWM0_POS     (0)
 
 /* SACNT */
 #define SSI_SACNT_FRDIV         (0x3f << 5)
-#define SSI_SACNT_FRDIVw(x)     (((x) << 5) & SSI_SACNT_FRDIV)
-#define SSI_SACNT_FRDIVr(x)     (((x) & SSI_SACNT_FRDIV) >> 5)
+#define SSI_SACNT_FRDIV_POS     (5)
 
 #define SSI_SACNT_WR            (0x1 << 4)
 #define SSI_SACNT_RD            (0x1 << 3)
@@ -1156,8 +1139,7 @@
 #define WDOG_WRSR               (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04))
 
 #define WDOG_WCR_WT             (0xff << 8)
-#define WDOG_WCR_WTw(x)         (((x) << 8) & WDOG_WCR_WT)
-#define WDOG_WCR_WTr(x)         (((x) & WDOG_WCR_WT) >> 8)
+#define WDOG_WCR_WT_POS         (8)
 
 #define WDOG_WCR_WOE            (0x1 << 6)
 #define WDOG_WCR_WDA            (0x1 << 5)
@@ -1245,45 +1227,45 @@
 /*
  * IRQ Controller Register Definitions.
  */
-#define AVIC_BASE_ADDR         0x68000000
-#define INTCNTL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
-#define NIMASK                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
-#define INTENNUM               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
-#define INTDISNUM              (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
-#define INTENABLEH             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
-#define INTENABLEL             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
-#define INTTYPEH               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
-#define INTTYPEL               (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
-#define NIPRIORITY(n)          (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
-#define NIPRIORITY7            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
-#define NIPRIORITY6            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
-#define NIPRIORITY5            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
-#define NIPRIORITY4            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
-#define NIPRIORITY3            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
-#define NIPRIORITY2            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
-#define NIPRIORITY1            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
-#define NIPRIORITY0            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
-#define NIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
-#define FIVECSR                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
-#define INTSRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
-#define INTSRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
-#define INTFRCH                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
-#define INTFRCL                (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
-#define NIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
-#define NIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
-#define FIPNDH                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
-#define FIPNDL                 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
-#define VECTOR_BASE_ADDR       (AVIC_BASE_ADDR+0x100)
-#define VECTOR(n)              (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
+#define AVIC_BASE_ADDR          0x68000000
+#define AVIC_INTCNTL            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
+#define AVIC_NIMASK             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
+#define AVIC_INTENNUM           (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
+#define AVIC_INTDISNUM          (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
+#define AVIC_INTENABLEH         (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
+#define AVIC_INTENABLEL         (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
+#define AVIC_INTTYPEH           (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
+#define AVIC_INTTYPEL           (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
+#define AVIC_NIPRIORITY(n)      (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
+#define AVIC_NIPRIORITY7        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
+#define AVIC_NIPRIORITY6        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
+#define AVIC_NIPRIORITY5        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
+#define AVIC_NIPRIORITY4        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
+#define AVIC_NIPRIORITY3        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
+#define AVIC_NIPRIORITY2        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
+#define AVIC_NIPRIORITY1        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
+#define AVIC_NIPRIORITY0        (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
+#define AVIC_NIVECSR            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
+#define AVIC_FIVECSR            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
+#define AVIC_INTSRCH            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
+#define AVIC_INTSRCL            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
+#define AVIC_INTFRCH            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
+#define AVIC_INTFRCL            (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
+#define AVIC_NIPNDH             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
+#define AVIC_NIPNDL             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
+#define AVIC_FIPNDH             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
+#define AVIC_FIPNDL             (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
+#define AVIC_VECTOR_BASE_ADDR   (AVIC_BASE_ADDR+0x100)
+#define AVIC_VECTOR(n)          (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
 
 /* The vectors go all the way up to 63. 4 bytes for each */
-#define INTCNTL_ABFLAG         (1 << 25)
-#define INTCNTL_ABFEN          (1 << 24)
-#define INTCNTL_NIDIS          (1 << 22)
-#define INTCNTL_FIDIS          (1 << 21)
-#define INTCNTL_NIAD           (1 << 20)
-#define INTCNTL_FIAD           (1 << 19)
-#define INTCNTL_NM             (1 << 18)
+#define AVIC_INTCNTL_ABFLAG     (1 << 25)
+#define AVIC_INTCNTL_ABFEN      (1 << 24)
+#define AVIC_INTCNTL_NIDIS      (1 << 22)
+#define AVIC_INTCNTL_FIDIS      (1 << 21)
+#define AVIC_INTCNTL_NIAD       (1 << 20)
+#define AVIC_INTCNTL_FIAD       (1 << 19)
+#define AVIC_INTCNTL_NM         (1 << 18)
 
 /* L210 */
 #define L2CC_BASE_ADDR                  0x30000000
@@ -1299,224 +1281,167 @@
 #define L2CC_CACHE_SYNC                 (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
 
 /* CCM */
-#define CLKCTL_CCMR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
-#define CLKCTL_PDR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
-#define CLKCTL_PDR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
-#define CLKCTL_RCSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
-#define CLKCTL_MPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
-#define CLKCTL_UPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
-#define CLKCTL_SPCTL                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
-#define CLKCTL_COSR                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
-#define CLKCTL_CGR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
-#define CLKCTL_CGR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
-#define CLKCTL_CGR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
-#define CLKCTL_WIMR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
-#define CLKCTL_LDC                      (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
-#define CLKCTL_DCVR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
-#define CLKCTL_DCVR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
-#define CLKCTL_DCVR2                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
-#define CLKCTL_DCVR3                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
-#define CLKCTL_LTR0                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
-#define CLKCTL_LTR1                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
-#define CLKCTL_LTR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
-#define CLKCTL_LTR3                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
-#define CLKCTL_LTBR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
-#define CLKCTL_LTBR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
-#define CLKCTL_PMCR0                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
-#define CLKCTL_PMCR1                    (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
-#define CLKCTL_PDR2                     (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
+#define CCM_CCMR                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
+#define CCM_PDR0                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
+#define CCM_PDR1                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
+#define CCM_RCSR                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
+#define CCM_MPCTL                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
+#define CCM_UPCTL                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
+#define CCM_SPCTL                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
+#define CCM_COSR                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
+#define CCM_CGR0                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
+#define CCM_CGR1                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
+#define CCM_CGR2                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
+#define CCM_WIMR0                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
+#define CCM_LDC                         (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
+#define CCM_DCVR0                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
+#define CCM_DCVR1                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
+#define CCM_DCVR2                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
+#define CCM_DCVR3                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
+#define CCM_LTR0                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
+#define CCM_LTR1                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
+#define CCM_LTR2                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
+#define CCM_LTR3                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
+#define CCM_LTBR0                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
+#define CCM_LTBR1                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
+#define CCM_PMCR0                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
+#define CCM_PMCR1                       (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
+#define CCM_PDR2                        (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
 
 /* CCMR */
-#define CCMR_L2PG                       (0x1 << 29)
-#define CCMR_VSTBY                      (0x1 << 28)
-#define CCMR_WBEN                       (0x1 << 27)
-#define CCMR_FPMF                       (0x1 << 26)
-#define CCMR_CSCS                       (0x1 << 25)
-#define CCMR_PERCS                      (0x1 << 24)
-
-#define CCMR_SSI2S                      (0x3 << 21)
-#define CCMR_SSI2S_MCU_CLK              (0x0 << 21)
-#define CCMR_SSI2S_USB_CLK              (0x1 << 21)
-#define CCMR_SSI2S_SERIAL_CLK           (0x2 << 21) /* default */
-
-#define CCMR_SSI1S                      (0x3 << 18)
-#define CCMR_SSI1S_MCU_CLK              (0x0 << 18)
-#define CCMR_SSI1S_USB_CLK              (0x1 << 18)
-#define CCMR_SSI1S_SERIAL_CLK           (0x2 << 18) /* default */
-
-#define CCMR_RAMW                       (0x3 << 16)
-#define CCMR_RAMW_0ARM_0ALTMS           (0x0 << 16)
-#define CCMR_RAMW_0ARM_1ALTMS           (0x1 << 16) /* Not recommended */
-#define CCMR_RAMW_1ARM_0ALTMS           (0x2 << 16) /* Not recommended */
-#define CCMR_RAMW_1ARM_1ALTMS           (0x3 << 16)
-
-#define CCMR_LPM                        (0x3 << 14)
-#define CCMR_LPM_WAIT_MODE              (0x0 << 14)
-#define CCMR_LPM_DOZE_MODE              (0x1 << 14)
-#define CCMR_LPM_SRM                    (0x2 << 14) /* State retention mode */
-#define CCMR_LPM_DSM                    (0x3 << 14) /* Deep sleep mode */
-
-#define CCMR_FIRS                       (0x3 << 11)
-#define CCMR_FIRS_MCU_CLK               (0x0 << 11)
-#define CCMR_FIRS_USB_CLK               (0x1 << 11)
-#define CCMR_FIRS_SERIAL_CLK            (0x2 << 11)
-
-#define CCMR_WAMO                       (0x1 << 10)
-#define CCMR_UPE                        (0x1 << 9)
-#define CCMR_SPE                        (0x1 << 8)
-#define CCMR_MDS                        (0x1 << 7)
-
-#define CCMR_ROMW                       (0x3 << 5)
-#define CCMR_ROMW_0ARM_0ALTMS           (0x0 << 5)
-#define CCMR_ROMW_0ARM_1ALTMS           (0x1 << 5) /* Not recommended */
-#define CCMR_ROMW_1ARM_0ALTMS           (0x2 << 5) /* Not recommended */
-#define CCMR_ROMW_1ARM_1ALTMS           (0x3 << 5)
-
-#define CCMR_SBYCS                      (0x1 << 4)
-#define CCMR_MPE                        (0x1 << 3)
-
-#define CCMR_PRCS                       (0x3 << 1)
-#define CCMR_PRCS_FPM                   (0x1 << 1)
-#define CCMR_PRCS_CKIH                  (0x2 << 1)
-
-#define CCMR_FPME                       (0x1 << 0)
+#define CCM_CCMR_L2PG                   (0x1 << 29)
+#define CCM_CCMR_VSTBY                  (0x1 << 28)
+#define CCM_CCMR_WBEN                   (0x1 << 27)
+#define CCM_CCMR_FPMF                   (0x1 << 26)
+#define CCM_CCMR_CSCS                   (0x1 << 25)
+#define CCM_CCMR_PERCS                  (0x1 << 24)
+
+#define CCM_CCMR_SSI2S                  (0x3 << 21)
+#define CCM_CCMR_SSI2S_MCU_CLK          (0x0 << 21)
+#define CCM_CCMR_SSI2S_USB_CLK          (0x1 << 21)
+#define CCM_CCMR_SSI2S_SERIAL_CLK       (0x2 << 21) /* default */
+
+#define CCM_CCMR_SSI1S                  (0x3 << 18)
+#define CCM_CCMR_SSI1S_MCU_CLK          (0x0 << 18)
+#define CCM_CCMR_SSI1S_USB_CLK          (0x1 << 18)
+#define CCM_CCMR_SSI1S_SERIAL_CLK       (0x2 << 18) /* default */
+
+#define CCM_CCMR_RAMW                   (0x3 << 16)
+#define CCM_CCMR_RAMW_0ARM_0ALTMS       (0x0 << 16)
+#define CCM_CCMR_RAMW_0ARM_1ALTMS       (0x1 << 16) /* Not recommended */
+#define CCM_CCMR_RAMW_1ARM_0ALTMS       (0x2 << 16) /* Not recommended */
+#define CCM_CCMR_RAMW_1ARM_1ALTMS       (0x3 << 16)
+
+#define CCM_CCMR_LPM                    (0x3 << 14)
+#define CCM_CCMR_LPM_WAIT_MODE          (0x0 << 14)
+#define CCM_CCMR_LPM_DOZE_MODE          (0x1 << 14)
+#define CCM_CCMR_LPM_SRM                (0x2 << 14) /* State retention mode */
+#define CCM_CCMR_LPM_DSM                (0x3 << 14) /* Deep sleep mode */
+
+#define CCM_CCMR_FIRS                   (0x3 << 11)
+#define CCM_CCMR_FIRS_MCU_CLK           (0x0 << 11)
+#define CCM_CCMR_FIRS_USB_CLK           (0x1 << 11)
+#define CCM_CCMR_FIRS_SERIAL_CLK        (0x2 << 11)
+
+#define CCM_CCMR_WAMO                   (0x1 << 10)
+#define CCM_CCMR_UPE                    (0x1 << 9)
+#define CCM_CCMR_SPE                    (0x1 << 8)
+#define CCM_CCMR_MDS                    (0x1 << 7)
+
+#define CCM_CCMR_ROMW                   (0x3 << 5)
+#define CCM_CCMR_ROMW_0ARM_0ALTMS       (0x0 << 5)
+#define CCM_CCMR_ROMW_0ARM_1ALTMS       (0x1 << 5) /* Not recommended */
+#define CCM_CCMR_ROMW_1ARM_0ALTMS       (0x2 << 5) /* Not recommended */
+#define CCM_CCMR_ROMW_1ARM_1ALTMS       (0x3 << 5)
+
+#define CCM_CCMR_SBYCS                  (0x1 << 4)
+#define CCM_CCMR_MPE                    (0x1 << 3)
+
+#define CCM_CCMR_PRCS                   (0x3 << 1)
+#define CCM_CCMR_PRCS_FPM               (0x1 << 1)
+#define CCM_CCMR_PRCS_CKIH              (0x2 << 1)
+
+#define CCM_CCMR_FPME                   (0x1 << 0)
 
 /* PDR0 */
-#define PDR0_CSI_PODF                   (0x1ff << 23)
-#define PDR0_CSI_PODFw(x)               (((x) << 23) & PDR0_CSI_PODF)
-#define PDR0_CSI_PODFr(x)               (((x) & PDR0_CSI_PODF) >> 23)
+#define CCM_PDR0_CSI_PODF               (0x1ff << 23)
+#define CCM_PDR0_CSI_PODF_POS           (23)
 
-#define PDR0_PER_PODF                   (0x1f << 16)
-#define PDR0_PER_PODFw(x)               (((x) << 16) & PDR0_PER_PODF)
-#define PDR0_PER_PODFr(x)               (((x) & PDR0_PER_PODF) >> 16)
+#define CCM_PDR0_PER_PODF               (0x1f << 16)
+#define CCM_PDR0_PER_PODF_POS           (16)
 
-#define PDR0_HSP_PODF                   (0x7 << 11)
-#define PDR0_HSP_PODFw(x)               (((x) << 11) & PDR0_HSP_PODF)
-#define PDR0_HSP_PODFr(x)               (((x) & PDR0_HSP_PODF) >> 11)
+#define CCM_PDR0_HSP_PODF               (0x7 << 11)
+#define CCM_PDR0_HSP_PODF_POS           (11)
 
-#define PDR0_NFC_PODF                   (0x7 << 8)
-#define PDR0_NFC_PODFw(x)               (((x) << 8) & PDR0_NFC_PODF)
-#define PDR0_NFC_PODFr(x)               (((x) & PDR0_NFC_PODF) >> 8)
+#define CCM_PDR0_NFC_PODF               (0x7 << 8)
+#define CCM_PDR0_NFC_PODF_POS           (8)
 
-#define PDR0_IPG_PODF                   (0x3 << 6)
-#define PDR0_IPG_PODFw(x)               (((x) << 6) & PDR0_IPG_PODF)
-#define PDR0_IPG_PODFr(x)               (((x) & PDR0_IPG_PODF) >> 6)
+#define CCM_PDR0_IPG_PODF               (0x3 << 6)
+#define CCM_PDR0_IPG_PODF_POS           (6)
 
-#define PDR0_MAX_PODF                   (0x7 << 3)
-#define PDR0_MAX_PODFw(x)               (((x) << 3) & PDR0_MAX_PODF)
-#define PDR0_MAX_PODFr(x)               (((x) & PDR0_MAX_PODF) >> 3)
+#define CCM_PDR0_MAX_PODF               (0x7 << 3)
+#define CCM_PDR0_MAX_PODF_POS           (3)
 
-#define PDR0_MCU_PODF                   (0x7 << 0)
-#define PDR0_MCU_PODFw(x)               (((x) << 0) & PDR0_MCU_PODF)
-#define PDR0_MCU_PODFr(x)               (((x) & PDR0_MCU_PODF) >> 0)
+#define CCM_PDR0_MCU_PODF               (0x7 << 0)
+#define CCM_PDR0_MCU_PODF_POS           (0)
 
 /* PDR1 */
-#define PDR1_USB_PRDF                   (0x3 << 30)
-#define PDR1_USB_PRDFw(x)               (((x) << 30) & PDR1_USB_PRDF)
-#define PDR1_USB_PRDFr(x)               (((x) & PDR1_USB_PRDF) >> 30)
-
-#define PDR1_USB_PODF                   (0x7 << 27)
-#define PDR1_USB_PODFw(x)               (((x) << 27) & PDR1_USB_PODF)
-#define PDR1_USB_PODFr(x)               (((x) & PDR1_USB_PODF) >> 27)
-
-#define PDR1_FIRI_PRE_PODF              (0x7 << 24)
-#define PDR1_FIRI_PRE_PODFw(x)          (((x) << 24) & PDR1_FIRI_PRE_PODF)
-#define PDR1_FIRI_PRE_PODFr(x)          (((x) & PDR1_FIRI_PRE_PODF) >> 24)
-
-#define PDR1_FIRI_PODF                  (0x3f << 18)
-#define PDR1_FIRI_PODFw(x)              (((x) << 18) & PDR1_FIRI_PODF)
-#define PDR1_FIRI_PODFr(x)              (((x) & PDR1_FIRI_PODF) >> 18)
-
-#define PDR1_SSI2_PRE_PODF              (0x7 << 15)
-#define PDR1_SSI2_PRE_PODFw(x)          (((x) << 15) & PDR1_SSI2_PRE_PODF)
-#define PDR1_SSI2_PRE_PODFr(x)          (((x) & PDR1_SSI2_PRE_PODF) >> 15)
-
-#define PDR1_SSI2_PODF                  (0x3f << 9)
-#define PDR1_SSI2_PODFw(x)              (((x) << 9) & PDR1_SSI2_PODF)
-#define PDR1_SSI2_PODFr(x)              (((x) & PDR1_SSI2_PODF) >> 9)
-
-#define PDR1_SSI1_PRE_PODF              (0x7 << 6)
-#define PDR1_SSI1_PRE_PODFw(x)          (((x) << 6) & PDR1_SSI1_PRE_PODF)
-#define PDR1_SSI1_PRE_PODFr(x)          (((x) & PDR1_SSI1_PRE_PODF) >> 6)
-
-#define PDR1_SSI1_PODF                  (0x3f << 0)
-#define PDR1_SSI1_PODFw(x)              (((x) << 0) & PDR1_SSI1_PODF)
-#define PDR1_SSI1_PODFr(x)              (((x) & PDR1_SSI1_PODF) >> 0)
-
-#define CGR0_SD_MMC1(cg)                ((cg) << 0*2)
-#define CGR0_SD_MMC2(cg)                ((cg) << 1*2)
-#define CGR0_GPT(cg)                    ((cg) << 2*2)
-#define CGR0_EPIT1(cg)                  ((cg) << 3*2)
-#define CGR0_EPIT2(cg)                  ((cg) << 4*2)
-#define CGR0_IIM(cg)                    ((cg) << 5*2)
-#define CGR0_ATA(cg)                    ((cg) << 6*2)
-#define CGR0_SDMA(cg)                   ((cg) << 7*2)
-#define CGR0_CSPI3(cg)                  ((cg) << 8*2)
-#define CGR0_RNG(cg)                    ((cg) << 9*2)
-#define CGR0_UART1(cg)                  ((cg) << 10*2)
-#define CGR0_UART2(cg)                  ((cg) << 11*2)
-#define CGR0_SSI1(cg)                   ((cg) << 12*2)
-#define CGR0_I2C1(cg)                   ((cg) << 13*2)
-#define CGR0_I2C2(cg)                   ((cg) << 14*2)
-#define CGR0_I2C3(cg)                   ((cg) << 15*2)
-
-#define CGR1_HANTRO(cg)                 ((cg) << 0*2)
-#define CGR1_MEMSTICK1(cg)              ((cg) << 1*2)
-#define CGR1_MEMSTICK2(cg)              ((cg) << 2*2)
-#define CGR1_CSI(cg)                    ((cg) << 3*2)
-#define CGR1_RTC(cg)                    ((cg) << 4*2)
-#define CGR1_WDOG(cg)                   ((cg) << 5*2)
-#define CGR1_PWM(cg)                    ((cg) << 6*2)
-#define CGR1_SIM(cg)                    ((cg) << 7*2)
-#define CGR1_ECT(cg)                    ((cg) << 8*2)
-#define CGR1_USBOTG(cg)                 ((cg) << 9*2)
-#define CGR1_KPP(cg)                    ((cg) << 10*2)
-#define CGR1_IPU(cg)                    ((cg) << 11*2)
-#define CGR1_UART3(cg)                  ((cg) << 12*2)
-#define CGR1_UART4(cg)                  ((cg) << 13*2)
-#define CGR1_UART5(cg)                  ((cg) << 14*2)
-#define CGR1_1_WIRE(cg)                 ((cg) << 15*2)
-
-#define CGR2_SSI2(cg)                   ((cg) << 0*2)
-#define CGR2_CSPI1(cg)                  ((cg) << 1*2)
-#define CGR2_CSPI2(cg)                  ((cg) << 2*2)
-#define CGR2_GACC(cg)                   ((cg) << 3*2)
-#define CGR2_EMI(cg)                    ((cg) << 4*2)
-#define CGR2_RTIC(cg)                   ((cg) << 5*2)
-#define CGR2_FIR(cg)                    ((cg) << 6*2)
-
-#define WIM_GPIO3                       (1 << 0)
-#define WIM_GPIO2                       (1 << 1)
-#define WIM_GPIO1                       (1 << 2)
-#define WIM_PCMCIA                      (1 << 3)
-#define WIM_WDT                         (1 << 4)
-#define WIM_USB_OTG                     (1 << 5)
-#define WIM_IPI_INT_UH2                 (1 << 6)
-#define WIM_IPI_INT_UH1                 (1 << 7)
-#define WIM_IPI_INT_UART5_ANDED         (1 << 8)
-#define WIM_IPI_INT_UART4_ANDED         (1 << 9)
-#define WIM_IPI_INT_UART3_ANDED         (1 << 10)
-#define WIM_IPI_INT_UART2_ANDED         (1 << 11)
-#define WIM_IPI_INT_UART1_ANDED         (1 << 12)
-#define WIM_IPI_INT_SIM_DATA_IRQ        (1 << 13)
-#define WIM_IPI_INT_SDHC2               (1 << 14)
-#define WIM_IPI_INT_SDHC1               (1 << 15)
-#define WIM_IPI_INT_RTC                 (1 << 16)
-#define WIM_IPI_INT_PWM                 (1 << 17)
-#define WIM_IPI_INT_KPP                 (1 << 18)
-#define WIM_IPI_INT_IIM                 (1 << 19)
-#define WIM_IPI_INT_GPT                 (1 << 20)
-#define WIM_IPI_INT_FIR                 (1 << 21)
-#define WIM_IPI_INT_EPIT2               (1 << 22)
-#define WIM_IPI_INT_EPIT1               (1 << 23)
-#define WIM_IPI_INT_CSPI2               (1 << 24)
-#define WIM_IPI_INT_CSPI1               (1 << 25)
-#define WIM_IPI_INT_POWER_FAIL          (1 << 26)
-#define WIM_IPI_INT_CSPI3               (1 << 27)
-#define WIM_RESERVED28                  (1 << 28)
-#define WIM_RESERVED29                  (1 << 29)
-#define WIM_RESERVED30                  (1 << 30)
-#define WIM_RESERVED31                  (1 << 31)
+#define CCM_PDR1_USB_PRDF               (0x3 << 30)
+#define CCM_PDR1_USB_PRDF_POS           (30)
+
+#define CCM_PDR1_USB_PODF               (0x7 << 27)
+#define CCM_PDR1_USB_PODF_POS           (27)
+
+#define CCM_PDR1_FIRI_PRE_PODF          (0x7 << 24)
+#define CCM_PDR1_FIRI_PRE_PODF_POS      (24)
+
+#define CCM_PDR1_FIRI_PODF              (0x3f << 18)
+#define CCM_PDR1_FIRI_PODF_POS          (18)
+
+#define CCM_PDR1_SSI2_PRE_PODF          (0x7 << 15)
+#define CCM_PDR1_SSI2_PRE_PODF_POS      (15)
+
+#define CCM_PDR1_SSI2_PODF              (0x3f << 9)
+#define CCM_PDR1_SSI2_PODF_POS          (9)
+
+#define CCM_PDR1_SSI1_PRE_PODF          (0x7 << 6)
+#define CCM_PDR1_SSI1_PRE_PODF_POS      (6)
+
+#define CCM_PDR1_SSI1_PODF              (0x3f << 0)
+#define CCM_PDR1_SSI1_PODF_POS          (0)
+
+#define CCM_WIMR0_GPIO3                 (1 << 0)
+#define CCM_WIMR0_GPIO2                 (1 << 1)
+#define CCM_WIMR0_GPIO1                 (1 << 2)
+#define CCM_WIMR0_PCMCIA                (1 << 3)
+#define CCM_WIMR0_WDT                   (1 << 4)
+#define CCM_WIMR0_USB_OTG               (1 << 5)
+#define CCM_WIMR0_IPI_INT_UH2           (1 << 6)
+#define CCM_WIMR0_IPI_INT_UH1           (1 << 7)
+#define CCM_WIMR0_IPI_INT_UART5_ANDED   (1 << 8)
+#define CCM_WIMR0_IPI_INT_UART4_ANDED   (1 << 9)
+#define CCM_WIMR0_IPI_INT_UART3_ANDED   (1 << 10)
+#define CCM_WIMR0_IPI_INT_UART2_ANDED   (1 << 11)
+#define CCM_WIMR0_IPI_INT_UART1_ANDED   (1 << 12)
+#define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ  (1 << 13)
+#define CCM_WIMR0_IPI_INT_SDHC2         (1 << 14)
+#define CCM_WIMR0_IPI_INT_SDHC1         (1 << 15)
+#define CCM_WIMR0_IPI_INT_RTC           (1 << 16)
+#define CCM_WIMR0_IPI_INT_PWM           (1 << 17)
+#define CCM_WIMR0_IPI_INT_KPP           (1 << 18)
+#define CCM_WIMR0_IPI_INT_IIM           (1 << 19)
+#define CCM_WIMR0_IPI_INT_GPT           (1 << 20)
+#define CCM_WIMR0_IPI_INT_FIR           (1 << 21)
+#define CCM_WIMR0_IPI_INT_EPIT2         (1 << 22)
+#define CCM_WIMR0_IPI_INT_EPIT1         (1 << 23)
+#define CCM_WIMR0_IPI_INT_CSPI2         (1 << 24)
+#define CCM_WIMR0_IPI_INT_CSPI1         (1 << 25)
+#define CCM_WIMR0_IPI_INT_POWER_FAIL    (1 << 26)
+#define CCM_WIMR0_IPI_INT_CSPI3         (1 << 27)
+#define CCM_WIMR0_RESERVED28            (1 << 28)
+#define CCM_WIMR0_RESERVED29            (1 << 29)
+#define CCM_WIMR0_RESERVED30            (1 << 30)
+#define CCM_WIMR0_RESERVED31            (1 << 31)
 
 /* WEIM - CS0 */
 #define CSCRU                           0x00
diff --git a/firmware/export/mc13783.h b/firmware/export/mc13783.h
index d8b719be03..09fb1f1fc4 100644
--- a/firmware/export/mc13783.h
+++ b/firmware/export/mc13783.h
@@ -246,29 +246,25 @@ enum mc13783_regs_enum
 
 /* IDENTIFICATION (7) */
 #define MC13783_REVISION                (0x1f << 0)
-    #define MC13783_REVISIONr(x)        (((x) & MC13783_REVISION) >> 0) 
+#define MC13783_REVISION_POS            (0)
 #define MC13783_ICID                    (0x7 << 6)
-    #define MC13783_ICIDr(x)            (((x) & MC13783_ICID) >> 6)
+#define MC13783_ICID_POS                (6)
 #define MC13783_FIN                     (0x3 << 9)
-    #define MC13783_FINr(x)             (((x) & MC13783_FIN) >> 9))
+#define MC13783_FIN_POS                 (9)
 #define MC13783_FAB                     (0x3 << 12)
-    #define MC13783_FABr(x)             (((x) & MC13783_FAB) >> 12))
+#define MC13783_FAB_POS                 (12)
 
 /* SEMAPHORE (8) */
 #define MC13783_SEMCTRLA                (0x1 << 0)
 #define MC13783_SEMCTRLB                (0x1 << 2)
 #define MC13783_SEMWRTA                 (0xf << 4)
-    #define MC13783_SEMWRTAw(x)         (((x) << 4) & MC13783_SEMWRTA)
-    #define MC13783_SEMWRTAr(x)         (((x) & MC13783_SEMWRTA) >> 4)
+#define MC13783_SEMWRTA_POS             (4)
 #define MC13783_SEMWRTB                 (0x3f << 8)
-    #define MC13783_SEMWRTBw(x)         (((x) << 8) & MC13783_SEMWRTB)
-    #define MC13783_SEMWRTBr(x)         (((x) & MC13783_SEMWRTB) >> 8)
+#define MC13783_SEMWRTB_POS             (8)
 #define MC13783_SEMRDA                  (0xf << 14)
-    #define MC13783_SEMRDAw(x)          (((x) << 14) & MC13783_SEMRDA)
-    #define MC13783_SEMRDAr(x)          (((x) & MC13783_SEMRDA) >> 14)
+#define MC13783_SEMRDA_POS              (14)
 #define MC13783_SEMRDB                  (0x3f << 18)
-    #define MC13783_SEMRDBw(x)          (((x) << 18) & MC13783_SEMRDB)
-    #define MC13783_SEMRDBr(x)          (((x) & MC13783_SEMRDB) >> 18)
+#define MC13783_SEMRDB_POS              (18)
 
 /* ARBITRATION_PERIPHERAL_AUDIO (9) */
 #define MC13783_AUDIOTXSEL              (0x3 << 0)
@@ -418,20 +414,16 @@ enum mc13783_regs_enum
 #define MC13783_COINCHEN                (0x1 << 23)
 
 /* POWER_CONTROL1 (14) */
-#define MC13783_PCT                     (0xff << 0)
     /* Up to 8 seconds */
-    #define MC13783_PCTw(x)             (((x) << 0) & MC13783_PCT)
-    #define MC13783_PCTr(x)             (((x) & MC13783_PCT) >> 0)
+#define MC13783_PCT                     (0xff << 0)
+#define MC13783_PCT_POS                 (0)
 #define MC13783_PCCOUNT                 (0xf << 8)
-    #define MC13783_PCCOUNTw(x)         (((x) << 8) & MC13783_PCCOUNT)
-    #define MC13783_PCCOUNTr(x)         (((x) & MC13783_PCCOUNT) >> 8)
+#define MC13783_PCCOUNT_POS             (8)
 #define MC13783_PCMAXCNT                (0xf << 12)
-    #define MC13783_PCMAXCNTw(x)        (((x) << 12) & MC13783_PCMAXCNT)
-    #define MC13783_PCMAXCNTr(x)        (((x) & MC13783_PCMAXCNT) >> 12)
-#define MC13783_MEMTMR                  (0xf << 16)
+#define MC13783_PCMAXCNT_POS            (12)
     /* Up to 8 minutes with MEMALLON=0, <> 0 + MEMALLON=1: infinite */
-    #define MC13783_MEMTMRw(x)          (((x) << 16) & MC13783_MEMTMR)
-    #define MC13783_MEMTMRr(x)          (((x) & MC13783_MEMTMR) >> 16)
+#define MC13783_MEMTMR                  (0xf << 16)
+#define MC13783_MEMTMR_POS              (16)
 #define MC13783_MEMALLON                (0x1 << 20)
 
 /* POWER_CONTROL2 (15) */
@@ -501,47 +493,35 @@ enum mc13783_regs_enum
 
 /* SWITCHERS0 (24) */
 #define MC13783_SW1A                    (0x3f << 0)
-    #define MC13783_SW1Aw(x)            (((x) << 0) & MC13783_SW1A)
-    #define MC13783_SW1Ar(x)            (((x) & MC13783_SW1A) >> 0)
+#define MC13783_SW1A_POS                (0)
 #define MC13783_SW1ADVS                 (0x3f << 6)
-    #define MC13783_SW1ADVSw(x)         (((x) << 6) & MC13783_SW1ADVS)
-    #define MC13783_SW1ADVSr(x)         (((x) & MC13783_SW1ADVS) >> 6)
+#define MC13783_SW1ADVS_POS             (6)
 #define MC13783_SW1ASTBY                (0x3f << 12)
-    #define MC13783_SW1ASTBYw(x)        (((x) << 12) & MC13783_SW1ASTBY)
-    #define MC13783_SW1ASTBYr(x)        (((x) & MC13783_SW1ASTBY) >> 12)
+#define MC13783_SW1ASTBY_POS            (12)
 
 /* SWITCHERS1 (25) */
 #define MC13783_SW1B                    (0x3f << 0)
-    #define MC13783_SW1Bw(x)            (((x) << 0) & MC13783_SW1B)
-    #define MC13783_SW1Br(x)            (((x) & MC13783_SW1B) >> 0)
+#define MC13783_SW1B_POS                (0)
 #define MC13783_SW1BDVS                 (0x3f << 6)
-    #define MC13783_SW1BDVSw(x)         (((x) << 6) & MC13783_SW1BDVS)
-    #define MC13783_SW1BDVSr(x)         (((x) & MC13783_SW1BDVS) >> 6)
+#define MC13783_SW1BDVS_POS             (6)
 #define MC13783_SW1BSTBY                (0x3f << 12)
-    #define MC13783_SW1BSTBYw(x)        (((x) << 12) & MC13783_SW1BSTBY)
-    #define MC13783_SW1BSTBYr(x)        (((x) & MC13783_SW1BSTBY) >> 12)
+#define MC13783_SW1BSTBY_POS            (12)
 
 /* SWITCHERS2 (26) */
 #define MC13783_SW2A                    (0x3f << 0)
-    #define MC13783_SW2Aw(x)            (((x) << 0) & MC13783_SW1A)
-    #define MC13783_SW2Ar(x)            (((x) & MC13783_SW1A) >> 0)
+#define MC13783_SW2A_POS                (0)
 #define MC13783_SW2ADVS                 (0x3f << 6)
-    #define MC13783_SW2ADVSw(x)         (((x) << 6) & MC13783_SW2ADVS)
-    #define MC13783_SW2ADVSr(x)         (((x) & MC13783_SW2ADVS) >> 6)
+#define MC13783_SW2ADVS_POS             (6)
 #define MC13783_SW2ASTBY                (0x3f << 12)
-    #define MC13783_SW2ASTBYw(x)        (((x) << 12) & MC13783_SW2ASTBY)
-    #define MC13783_SW2ASTBYr(x)        (((x) & MC13783_SW2ASTBY) >> 12)
+#define MC13783_SW2ASTBY_POS            (12)
 
 /* SWITCHERS3 (27) */
 #define MC13783_SW2B                    (0x3f << 0)
-    #define MC13783_SW2Bw(x)            (((x) << 0) & MC13783_SW2B)
-    #define MC13783_SW2Br(x)            (((x) & MC13783_SW2B) >> 0)
+#define MC13783_SW2B_POS                (0)
 #define MC13783_SW2BDVS                 (0x3f << 6)
-    #define MC13783_SW2BDVSw(x)         (((x) << 6) & MC13783_SW2BDVS)
-    #define MC13783_SW2BDVSr(x)         (((x) & MC13783_SW2BDVS) >> 6)
+#define MC13783_SW2BDVS_POS             (6)
 #define MC13783_SW2BSTBY                (0x3f << 12)
-    #define MC13783_SW2BSTBYw(x)        (((x) << 12) & MC13783_SW2BSTBY)
-    #define MC13783_SW2BSTBYr(x)        (((x) & MC13783_SW2BSTBY) >> 12)
+#define MC13783_SW2BSTBY_POS            (12)
 
 /* SWITCHERS4 (28) */
 #define MC13783_SW1AMODE                (0x3 << 0)
@@ -804,30 +784,26 @@ enum mc13783_regs_enum
 
 /* AUDIO_RX1 (37) */
 #define MC13783_PGARXEN                 (0x1 << 0)
-#define MC13783_PGARX                   (0xf << 1)
     /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
-    #define MC13783_PGARXw(x)           (((x) << 1) & MC13783_PGARX)
-    #define MC13783_PGARXr(x)           (((x) & MC13783_PGARX) >> 1)
+#define MC13783_PGARX                   (0xf << 1)
+#define MC13783_PGARX_POS               (1)
 #define MC13783_PGASTEN                 (0x1 << 5)
-#define MC13783_PGAST                   (0xf << 6)
     /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
-    #define MC13783_PGASTw(x)           (((x) << 6) & MC13783_PGAST)
-    #define MC13783_PGASTr(x)           (((x) & MC13783_PGAST) >> 6)
+#define MC13783_PGAST                   (0xf << 6)
+#define MC13783_PGAST_POS               (6)
 #define MC13783_ARXINEN                 (0x1 << 10)
 #define MC13783_ARXIN                   (0x1 << 11)
-#define MC13783_PGARXIN                 (0xf << 12)
     /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
-    #define MC13783_PGARXINw(x)         (((x) << 12) & MC13783_PGARXIN)
-    #define MC13783_PGARXINr(x)         (((x) & MC13783_PGARXIN) >> 12)
+#define MC13783_PGARXIN                 (0xf << 12)
+#define MC13783_PGARXIN_POS             (12)
 #define MC13783_MONO                    (0x3 << 16)
     #define MC13783_MONO_LR_INDEPENDENT (0x0 << 16)
     #define MC13783_MONO_ST_OPPOSITE    (0x1 << 16)
     #define MC13783_MONO_ST_TO_MONO     (0x2 << 16)
     #define MC13783_MONO_MONO_OPPOSITE  (0x3 << 16)
-#define MC13783_BAL                     (0x7 << 18)
     /* 000=-21dB...3dB steps...111=0dB: left or right */
-    #define MC13783_BALw(x)             (((x) << 18) & MC13783_BAL)
-    #define MC13783_BALr(x)             (((x) & MC13783_BAL) >> 18)
+#define MC13783_BAL                     (0x7 << 18)
+#define MC13783_BAL_POS                 (18)
 #define MC13783_BALLR                   (0x1 << 21)
 
 /* AUDIO_TX (38) */
@@ -844,14 +820,12 @@ enum mc13783_regs_enum
 #define MC13783_ATXINEN                 (0x1 << 11)
 #define MC13783_ATXOUTEN                (0x1 << 12)
 #define MC13783_RXINREC                 (0x1 << 13)
+    /* 00000=-8dB...01000=0dB...11111=+23dB */
 #define MC13783_PGATXR                  (0x1f << 14)
+#define MC13783_PGATXR_POS              (14)
     /* 00000=-8dB...01000=0dB...11111=+23dB */
-    #define MC13783_PGATXRw(x)          (((x) << 14) & MC13783_PGATXR)
-    #define MC13783_PGATXRr(x)          (((x) & MC13783_PGATXR) >> 14)
 #define MC13783_PGATXL                  (0x1f << 19)
-    /* 00000=-8dB...01000=0dB...11111=+23dB */
-    #define MC13783_PGATXLw(x)          (((x) << 19) & MC13783_PGATXL)
-    #define MC13783_PGATXLr(x)          (((x) & MC13783_PGATXL) >> 19)
+#define MC13783_PGATXL_POS              (19)
 
 /* SSI_NETWORK (39) */
 #define MC13783_CDCTXRXSLOT             (0x3 << 2)
@@ -869,10 +843,9 @@ enum mc13783_regs_enum
     #define MC13783_CDCRXSECSLOT_TS1    (0x1 << 6)
     #define MC13783_CDCRXSECSLOT_TS2    (0x2 << 6)
     #define MC13783_CDCRXSECSLOT_TS3    (0x3 << 6)
-#define MC13783_CDCRXSECGAIN            (0x3 << 8)
     /* -inf, -0dB, -6dB, -12dB */
-    #define MC13783_CDCRXSECGAINw(x)    (((x) << 8) & MC13783_CDCRXSECGAIN)
-    #define MC13783_CDCRXSECGAINr(x)    (((x) & MC13783_CDCRXSECGAIN) >> 8)
+#define MC13783_CDCRXSECGAIN            (0x3 << 8)
+#define MC13783_CDCRXSECGAIN_POS        (8)
 #define MC13783_CDCSUMGAIN              (0x1 << 10)
 #define MC13783_CDCFSDLY                (0x1 << 11)
 #define MC13783_STDCSLOTS               (0x3 << 12)
@@ -890,10 +863,9 @@ enum mc13783_regs_enum
     #define MC13783_STDCRXSECSLOT_TS2_TS3 (0x1 << 16)
     #define MC13783_STDCRXSECSLOT_TS4_TS5 (0x2 << 16)
     #define MC13783_STDCRXSECSLOT_TS6_TS7 (0x3 << 16)
-#define MC13783_STDCRXSECGAIN           (0x3 << 18)
     /* -inf, -0dB, -6dB, -12dB */
-    #define MC13783_STDCRXSECGAINw(x)   (((x) << 8) & MC13783_STDCRXSECGAIN)
-    #define MC13783_STDCRXSECGAINr(x)   (((x) & MC13783_STDCRXSECGAIN) >> 8)
+#define MC13783_STDCRXSECGAIN           (0x3 << 18)
+#define MC13783_STDCRXSECGAIN_POS       (18)
 #define MC13783_STDSUMGAIN              (0x1 << 20)
 
 /* AUDIO_CODEC (40) */
@@ -988,14 +960,11 @@ enum mc13783_regs_enum
 #define MC13783_ADSEL                   (0x1 << 3)
 #define MC13783_TRIGMASK                (0x1 << 4)
 #define MC13783_ADA1                    (0x7 << 5)
-    #define MC13783_ADA1w(x)            (((x) << 5) & MC13783_ADA1)
-    #define MC13783_ADA1r(x)            (((x) & MC13783_ADA1) >> 5)
+#define MC13783_ADA1_POS                (5)
 #define MC13783_ADA2                    (0x7 << 8)
-    #define MC13783_ADA2w(x)            (((x) << 8) & MC13783_ADA2)
-    #define MC13783_ADA2r(x)            (((x) & MC13783_ADA2) >> 8)
+#define MC13783_ADA2_POS                (8)
 #define MC13783_ATO                     (0xff << 11)
-    #define MC13783_ATOw(x)             (((x) << 11) & MC13783_ATO)
-    #define MC13783_ATOr(x)             (((x) & MC13783_ATO) >> 11)
+#define MC13783_ATO_POS                 (11)
 #define MC13783_ATOX                    (0x1 << 19)
 #define MC13783_ASC                     (0x1 << 20)
 #define MC13783_ADTRIGIGN               (0x1 << 21)
@@ -1004,26 +973,24 @@ enum mc13783_regs_enum
 
 /* ADC2 (45) */
 #define MC13783_ADD1                    (0x3ff << 2)
-    #define MC13783_ADD1r(x)            (((x) & MC13783_ADD1) >> 2)
+#define MC13783_ADD1_POS                (2)
 #define MC13783_ADD2                    (0x3ff << 14)
-    #define MC13783_ADD2r(x)            (((x) & MC13783_ADD2) >> 14)
+#define MC13783_ADD2_POS                (14)
 
 /* ADC3 (46) */
 #define MC13783_WHIGH                   (0x3f << 0)
-    #define MC13783_WHIGHw(x)           (((x) << 0) & MC13783_WHIGH)
-    #define MC13783_WHIGHr(x)           (((x) & MC13783_WHIGH) >> 0)
+#define MC13783_WHIGH_POS               (0)
 #define MC13783_ICID                    (0x7 << 6)
-    #define MC13783_ICIDr(x)            (((x) & MC13783_ICID) >> 6)
+#define MC13783_ICID_POS                (6)
 #define MC13783_WLOW                    (0x3f << 9)
-    #define MC13783_WLOWw(x)            (((x) << 9) & MC13783_WLOW)
-    #define MC13783_WLOWr(x)            (((x) & MC13783_WLOW) >> 9)
+#define MC13783_WLOW_POS                (9)
 #define MC13783_ADCBIS2_ACCESS          (0x1 << 23)
 
 /* ADC4 (47) */
 #define MC13783_ADCBIS1                 (0x3ff << 2)
-    #define MC13783_ADCBIS1r(x)         (((x) & MC13783_ADCBIS1) >> 2)
+#define MC13783_ADCBIS1_POS             (2)
 #define MC13783_ADCBIS2                 (0x3ff << 14)
-    #define MC13783_ADCBIS2r(x)         (((x) & MC13783_ADCBIS2) >> 14)
+#define MC13783_ADCBIS2_POS             (14)
 
 /* CHARGER (48) */
 #define MC13783_VCHRG                   (0x7 << 0)
@@ -1036,8 +1003,7 @@ enum mc13783_regs_enum
     #define MC13783_VCHRG_3_800V        (0x6 << 0)
     #define MC13783_VCHRG_4_500V        (0x7 << 0)
 #define MC13783_ICHRG                   (0xf << 3) /*  Min  Nom  Max */
-    #define MC13783_ICHRGw(x)           (((x) << 3) & MC13783_ICHRG)
-    #define MC13783_ICHRGr(x)           (((x) & MC13783_ICHRG) >> 3)
+    #define MC13783_ICHRG_POS           (3)
     #define MC13783_ICHRG_0MA           (0x0 << 3) /*    0    0    0 */
     #define MC13783_ICHRG_70MA          (0x1 << 3) /*   55   70   85 */
     #define MC13783_ICHRG_177MA         (0x2 << 3) /*  161  177  195 */
@@ -1055,8 +1021,7 @@ enum mc13783_regs_enum
     #define MC13783_ICHRG_1596MA        (0xe << 3) /* 1450 1596 1755 */
     #define MC13783_ICHRG_FULLY_ON      (0xf << 3) /* Disallow HW FET turn on */ 
 #define MC13783_ICHRGTR                 (0x7 << 7) /*  Min  Nom  Max */
-    #define MC13783_ICHRGTRw(x)         (((x) << 7) & MC13783_ICHRGTR)
-    #define MC13783_ICHRGTRr(x)         (((x) & MC13783_ICHRGTR) >> 7)
+    #define MC13783_ICHRGTR_POS         (7)
     #define MC13783_ICHRGTR_0MA         (0x0 << 7) /*    0    0    0 */
     #define MC13783_ICHRGTR_9MA         (0x1 << 7) /*    6    9   12 */
     #define MC13783_ICHRGTR_20MA        (0x2 << 7) /*   14   20   26 */
@@ -1148,8 +1113,7 @@ enum mc13783_regs_enum
     #define MC13783_ABREF_600MV         (0x2 << 14)
     #define MC13783_ABREF_800MV         (0x3 << 14)
 #define MC13783_FLPATTRN                (0xf << 17)
-    #define MC13783_FLPATTRNw(x)        (((x) << 17) & MC13783_FLPATTRN)
-    #define MC13783_FLPATTRNr(x)        (((x) & MC13783_FLPATTRN) >> 17)
+    #define MC13783_FLPATTRN_POS        (17)
 #define MC13783_FLBANK1                 (0x1 << 21)
 #define MC13783_FLBANK2                 (0x1 << 22)
 #define MC13783_FLBANK3                 (0x1 << 23)
@@ -1178,98 +1142,70 @@ enum mc13783_regs_enum
 
 /* LED_CONTROL2 (53) */
 #define MC13783_LEDMD                   (0x7 << 0)
-    #define MC13783_LEDMDw(x)           (((x) << 0) & MC13783_LEDMD)
-    #define MC13783_LEDMDr(x)           (((x) & MC13783_LEDMD) >> 0)
+#define MC13783_LEDMD_POS               (0)
 #define MC13783_LEDAD                   (0x7 << 3)
-    #define MC13783_LEDADw(x)           (((x) << 3) & MC13783_LEDAD)
-    #define MC13783_LEDADr(x)           (((x) & MC13783_LEDAD) >> 3)
+#define MC13783_LEDAD_POS               (3)
 #define MC13783_LEDKP                   (0x7 << 6)
-    #define MC13783_LEDKPw(x)           (((x) << 6) & MC13783_LEDKP)
-    #define MC13783_LEDKPr(x)           (((x) & MC13783_LEDKP) >> 6)
+#define MC13783_LEDKP_POS               (6)
 #define MC13783_LEDMDDC                 (0xf << 9)
-    #define MC13783_LEDMDDCw(x)         (((x) << 9) & MC13783_LEDMDDC)
-    #define MC13783_LEDMDDCr(x)         (((x) & MC13783_LEDMDDC) >> 9)
+#define MC13783_LEDMDDC_POS             (9)
 #define MC13783_LEDADDC                 (0xf << 13)
-    #define MC13783_LEDADDCw(x)         (((x) << 13) & MC13783_LEDADDC)
-    #define MC13783_LEDADDCr(x)         (((x) & MC13783_LEDADDC) >> 13)
+#define MC13783_LEDADDC_POS             (13)
 #define MC13783_LEDKPDC                 (0xf << 17)
-    #define MC13783_LEDKPDCw(x)         (((x) << 17) & MC13783_LEDKPDC)
-    #define MC13783_LEDKPDCr(x)         (((x) & MC13783_LEDKPDC) >> 17)
+#define MC13783_LEDKPDC_POS             (17)
 #define MC13783_BLPERIOD                (0x1 << 21)
-    #define MC13783_BLPERIODw(x)        (((x) << 21) & MC13783_BLPERIOD)
-    #define MC13783_BLPERIODr(x)        (((x) & MC13783_BLPERIOD) >> 21)
+#define MC13783_BLPERIOD_POS            (21)
 #define MC13783_SLEWLIMBL               (0x1 << 23)
 
 /* LED_CONTROL3 (54) */
 #define MC13783_LEDR1                   (0x3 << 0)
-    #define MC13783_LEDR1w(x)           (((x) << 0) & MC13783_LEDR1)
-    #define MC13783_LEDR1r(x)           (((x) & MC13783_LEDR1) >> 0)
+#define MC13783_LEDR1_POS               (0)
 #define MC13783_LEDG1                   (0x3 << 2)
-    #define MC13783_LEDG1w(x)           (((x) << 2) & MC13783_LEDG1)
-    #define MC13783_LEDG1r(x)           (((x) & MC13783_LEDG1) >> 2)
+#define MC13783_LEDG1_POS               (2)
 #define MC13783_LEDB1                   (0x3 << 4)
-    #define MC13783_LEDB1w(x)           (((x) << 4) & MC13783_LEDB1)
-    #define MC13783_LEDB1r(x)           (((x) & MC13783_LEDB1) >> 4)
+#define MC13783_LEDB1_POS               (4)
 #define MC13783_LEDR1DC                 (0x1f << 6)
-    #define MC13783_LEDR1DCw(x)         (((x) << 6) & MC13783_LEDR1DC)
-    #define MC13783_LEDR1DCr(x)         (((x) & MC13783_LEDR1DC) >> 6)
+#define MC13783_LEDR1DC_POS             (6)
 #define MC13783_LEDG1DC                 (0x1f << 11)
-    #define MC13783_LEDG1DCw(x)         (((x) << 11) & MC13783_LEDG1DC)
-    #define MC13783_LEDG1DCr(x)         (((x) & MC13783_LEDG1DC) >> 11)
+#define MC13783_LEDG1DC_POS             (11)
 #define MC13783_LEDB1DC                 (0x1f << 16)
-    #define MC13783_LEDB1DCw(x)         (((x) << 16) & MC13783_LEDB1DC)
-    #define MC13783_LEDB1DCr(x)         (((x) & MC13783_LEDB1DC) >> 16)
+#define MC13783_LEDB1DC_POS             (16)
 #define MC13783_TC1PERIOD               (0x3 << 21)
-    #define MC13783_TC1PERIODw(x)       (((x) << 21) & MC13783_TC1PERIOD)
-    #define MC13783_TC1PERIODr(x)       (((x) & MC13783_TC1PERIOD) >> 21)
+#define MC13783_TC1PERIOD_POS           (21)
 #define MC13783_TC1TRIODE               (0x1 << 23)
 
 /* LED_CONTROL4 (55) */
 #define MC13783_LEDR2                   (0x3 << 0)
-    #define MC13783_LEDR2w(x)           (((x) << 0) & MC13783_LEDR2)
-    #define MC13783_LEDR2r(x)           (((x) & MC13783_LEDR2) >> 0)
+#define MC13783_LEDR2_POS               (0)
 #define MC13783_LEDG2                   (0x3 << 2)
-    #define MC13783_LEDG2w(x)           (((x) << 2) & MC13783_LEDG2)
-    #define MC13783_LEDG2r(x)           (((x) & MC13783_LEDG2) >> 2)
+#define MC13783_LEDG2_POS               (2)
 #define MC13783_LEDB2                   (0x3 << 4)
-    #define MC13783_LEDB2w(x)           (((x) << 4) & MC13783_LEDB2)
-    #define MC13783_LEDB2r(x)           (((x) & MC13783_LEDB2) >> 4)
+#define MC13783_LEDB2_POS               (4)
 #define MC13783_LEDR2DC                 (0x1f << 6)
-    #define MC13783_LEDR2DCw(x)         (((x) << 6) & MC13783_LEDR2DC)
-    #define MC13783_LEDR2DCr(x)         (((x) & MC13783_LEDR2DC) >> 6)
+#define MC13783_LEDR2DC_POS             (6)
 #define MC13783_LEDG2DC                 (0x1f << 11)
-    #define MC13783_LEDG2DCw(x)         (((x) << 11) & MC13783_LEDG2DC)
-    #define MC13783_LEDG2DCr(x)         (((x) & MC13783_LEDG2DC) >> 11)
+#define MC13783_LEDG2DC_POS             (11)
 #define MC13783_LEDB2DC                 (0x1f << 16)
-    #define MC13783_LEDB2DCw(x)         (((x) << 16) & MC13783_LEDB2DC)
-    #define MC13783_LEDB2DCr(x)         (((x) & MC13783_LEDB2DC) >> 16)
+#define MC13783_LEDB2DC_POS             (16)
 #define MC13783_TC2PERIOD               (0x3 << 21)
-    #define MC13783_TC2PERIODw(x)       (((x) << 21) & MC13783_TC2PERIOD)
-    #define MC13783_TC2PERIODr(x)       (((x) & MC13783_TC2PERIOD) >> 21)
+#define MC13783_TC2PERIOD_POS           (21)
 #define MC13783_TC2TRIODE               (0x1 << 23)
 
 /* LED_CONTROL5 (56) */
 #define MC13783_LEDR3                   (0x3 << 0)
-    #define MC13783_LEDR3w(x)           (((x) << 0) & MC13783_LEDR3)
-    #define MC13783_LEDR3r(x)           (((x) & MC13783_LEDR3) >> 0)
+#define MC13783_LEDR3_POS               (0)
 #define MC13783_LEDG3                   (0x3 << 2)
-    #define MC13783_LEDG3w(x)           (((x) << 2) & MC13783_LEDG3)
-    #define MC13783_LEDG3r(x)           (((x) & MC13783_LEDG3) >> 2)
+#define MC13783_LEDG3_POS               (2)
 #define MC13783_LEDB3                   (0x3 << 4)
-    #define MC13783_LEDB3w(x)           (((x) << 4) & MC13783_LEDB3)
-    #define MC13783_LEDB3r(x)           (((x) & MC13783_LEDB3) >> 4)
+#define MC13783_LEDB3_POS               (4)
 #define MC13783_LEDR3DC                 (0x1f << 6)
-    #define MC13783_LEDR3DCw(x)         (((x) << 6) & MC13783_LEDR3DC)
-    #define MC13783_LEDR3DCr(x)         (((x) & MC13783_LEDR3DC) >> 6)
+#define MC13783_LEDR3DC_POS             (6)
 #define MC13783_LEDG3DC                 (0x1f << 11)
-    #define MC13783_LEDG3DCw(x)         (((x) << 11) & MC13783_LEDG3DC)
-    #define MC13783_LEDG3DCr(x)         (((x) & MC13783_LEDG3DC) >> 11)
+#define MC13783_LEDG3DC_POS             (11)
 #define MC13783_LEDB3DC                 (0x1f << 16)
-    #define MC13783_LEDB3DCw(x)         (((x) << 16) & MC13783_LEDB3DC)
-    #define MC13783_LEDB3DCr(x)         (((x) & MC13783_LEDB3DC) >> 16)
+#define MC13783_LEDB3DC_POS             (16)
 #define MC13783_TC3PERIOD               (0x3 << 21)
-    #define MC13783_TC3PERIODw(x)       (((x) << 21) & MC13783_TC3PERIOD)
-    #define MC13783_TC3PERIODr(x)       (((x) & MC13783_TC3PERIOD) >> 21)
+#define MC13783_TC3PERIOD_POS           (21)
 #define MC13783_TC3TRIODE               (0x1 << 23)
 
 /* For event enum values which are target-defined */
diff --git a/firmware/target/arm/imx31/debug-imx31.c b/firmware/target/arm/imx31/debug-imx31.c
index ad436ea231..abf180cfd2 100644
--- a/firmware/target/arm/imx31/debug-imx31.c
+++ b/firmware/target/arm/imx31/debug-imx31.c
@@ -50,15 +50,15 @@ bool __dbg_hw_info(void)
                  iim_system_rev());
         lcd_puts(0, line++, buf); line++;
 
-        mpctl = CLKCTL_MPCTL;
-        spctl = CLKCTL_SPCTL;
-        upctl = CLKCTL_UPCTL;
+        mpctl = CCM_MPCTL;
+        spctl = CCM_SPCTL;
+        upctl = CCM_UPCTL;
 
-        pllref = imx31_clkctl_get_pll_ref_clk();
+        pllref = ccm_get_pll_ref_clk();
 
-        mcu_pllfreq = imx31_clkctl_get_pll(PLL_MCU);
-        ser_pllfreq = imx31_clkctl_get_pll(PLL_SERIAL);
-        usb_pllfreq = imx31_clkctl_get_pll(PLL_USB);
+        mcu_pllfreq = ccm_get_pll(PLL_MCU);
+        ser_pllfreq = ccm_get_pll(PLL_SERIAL);
+        usb_pllfreq = ccm_get_pll(PLL_USB);
 
         snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref);
         lcd_puts(0, line++, buf); line++;
@@ -70,7 +70,7 @@ bool __dbg_hw_info(void)
         snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq);
         lcd_puts(0, line++, buf); line++;
 
-        regval = CLKCTL_PDR0;
+        regval = CCM_PDR0;
         snprintf(buf, sizeof (buf), "  PDR0: %08lX", regval);
         lcd_puts(0, line++, buf);
 
@@ -111,7 +111,7 @@ bool __dbg_hw_info(void)
         snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq);
         lcd_puts(0, line++, buf); line++;
 
-        regval = CLKCTL_PDR1;
+        regval = CCM_PDR1;
         snprintf(buf, sizeof (buf), "  PDR1: %08lX", regval);
         lcd_puts(0, line++, buf);
 
@@ -120,7 +120,7 @@ bool __dbg_hw_info(void)
         snprintf(buf, sizeof (buf), "   usb_clk:       %u", freq);
         lcd_puts(0, line++, buf);
 
-        freq = usb_pllfreq / (((CLKCTL_PDR0 >> 16) & 0x1f) + 1);
+        freq = usb_pllfreq / (((CCM_PDR0 >> 16) & 0x1f) + 1);
         snprintf(buf, sizeof (buf), "   ipg_per_baud:  %u", freq);
         lcd_puts(0, line++, buf);
           
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
index 3c66c42adc..52293228f8 100644
--- a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
@@ -57,8 +57,8 @@ unsigned short adc_read(int channel)
     {
         /* Keep enable, start conversion, increment from channel 0,
          * increment from channel 4 */
-        uint32_t adc1 = MC13783_ADEN | MC13783_ASC | MC13783_ADA1w(0) |
-                        MC13783_ADA2w(4);
+        uint32_t adc1 = MC13783_ADEN | MC13783_ASC |
+                        (0 << MC13783_ADA1_POS) | (4 << MC13783_ADA2_POS);
 
         if (input_select == 1)
             adc1 |= MC13783_ADSEL; /* 2nd set of inputs */
@@ -81,7 +81,9 @@ unsigned short adc_read(int channel)
     mutex_unlock(&adc_mtx);
 
     /* Channels 0-3/8-11 in ADD1, 4-7/12-15 in ADD2 */
-    return (channel & 4) ? MC13783_ADD2r(data) : MC13783_ADD1r(data);
+    return (channel & 4) ?
+        ((data & MC13783_ADD2) >> MC13783_ADD2_POS) :
+        ((data & MC13783_ADD1) >> MC13783_ADD1_POS);
 }
 
 bool adc_enable_channel(int channel, bool enable)
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
index c32dead30a..c941037317 100644
--- a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
@@ -275,7 +275,7 @@ static unsigned long ata_dma_selected = ATA_DMA_PIO;
 static unsigned int get_T(void)
 {
     /* T = ATA clock period in nanoseconds */
-    return 1000 * 1000 * 1000 / imx31_clkctl_get_ata_clk();
+    return 1000 * 1000 * 1000 / ccm_get_ata_clk();
 }
 
 static void ata_wait_for_idle(void)
@@ -325,7 +325,7 @@ void ata_reset(void)
 void ata_enable(bool on)
 {
     /* Unconditionally clock module before writing regs */
-    imx31_clkctl_module_clock_gating(CG_ATA, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_ATA, CGM_ON_RUN_WAIT);
     ata_wait_for_idle();
 
     if (on)
@@ -339,7 +339,7 @@ void ata_enable(bool on)
         sleep(HZ/100);
 
         /* Disable off - unclock ATA module */
-        imx31_clkctl_module_clock_gating(CG_ATA, CGM_OFF);
+        ccm_module_clock_gating(CG_ATA, CGM_OFF);
     }
 }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
index a135889e6e..4ba7da4be0 100644
--- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
@@ -59,7 +59,7 @@ void UIE_VECTOR(void)
     );
 
     offset = mode == 0x11 ?
-        (int32_t)FIVECSR : ((int32_t)NIVECSR >> 16);
+        (int32_t)AVIC_FIVECSR : ((int32_t)AVIC_NIVECSR >> 16);
 
     panicf("Unhandled %s %d: %s",
            mode == 0x11 ? "FIQ" : "IRQ", offset,
@@ -69,7 +69,7 @@ void UIE_VECTOR(void)
 /* We use the AVIC */
 void __attribute__((interrupt("IRQ"))) irq_handler(void)
 {
-    const int offset = (int32_t)NIVECSR >> 16;
+    const int offset = (int32_t)AVIC_NIVECSR >> 16;
 
     if (offset == -1)
     {
@@ -105,20 +105,20 @@ void avic_init(void)
     int i;
 
     /* Disable all interrupts and set to unhandled */
-    avic_disable_int(ALL);
+    avic_disable_int(INT_ALL);
 
     /* Reset AVIC control */
     avic->intcntl = 0;
 
     /* Init all interrupts to type IRQ */
-    avic_set_int_type(ALL, IRQ);
+    avic_set_int_type(INT_ALL, INT_TYPE_IRQ);
 
     /* Set all normal to lowest priority */
     for (i = 0; i < 8; i++)
         avic->nipriority[i] = 0;
 
     /* Set NM bit to enable VIC */
-    avic->intcntl |= INTCNTL_NM;
+    avic->intcntl |= AVIC_INTCNTL_NM;
 
     /* Enable VE bit in CP15 Control reg to enable VIC */
     asm volatile (
@@ -147,7 +147,7 @@ void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
     struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 
-    if (ints != ALL) /* No mass-enable allowed */
+    if (ints != INT_ALL) /* No mass-enable allowed */
     {
         avic_set_int_type(ints, intstype);
         avic->vector[ints] = (long)handler;
@@ -163,7 +163,7 @@ void avic_disable_int(enum IMX31_INT_LIST ints)
     struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
     uint32_t i;
 
-    if (ints == ALL)
+    if (ints == INT_ALL)
     {
         for (i = 0; i < 64; i++)
         {
@@ -185,7 +185,7 @@ static void set_int_type(int i, enum INT_TYPE intstype)
     volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)];
     uint32_t val = 1L << (i & 0x1f);
 
-    if (intstype == IRQ)
+    if (intstype == INT_TYPE_IRQ)
         val = *reg & ~val;
     else
         val = *reg | val;
@@ -197,7 +197,7 @@ void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype)
 {
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 
-    if (ints == ALL)
+    if (ints == INT_ALL)
     {
         int i;
         for (i = 0; i < 64; i++)
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
index 3580c8c083..a049713600 100644
--- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
+++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
@@ -172,32 +172,34 @@ struct avic_map
     };
 };
 
+#define INT_PRIO_DEFAULT    7
+
 enum INT_TYPE
 {
-    IRQ = 0,
-    FIQ
+    INT_TYPE_IRQ = 0,
+    INT_TYPE_FIQ
 };
 
 enum IMX31_INT_LIST
 {
     __IMX31_INT_FIRST = -1,
-   RESERVED0, RESERVED1,     RESERVED2, I2C3,
-   I2C2,      MPEG4_ENCODER, RTIC,      FIR,
-   MMC_SDHC2, MMC_SDHC1,     I2C1,      SSI2,
-   SSI1,      CSPI2,         CSPI1,     ATA,
-   MBX,       CSPI3,         UART3,     IIM,
-   SIM1,      SIM2,          RNGA,      EVTMON,
-   KPP,       RTC,           PWN,       EPIT2,
-   EPIT1,     GPT,           PWR_FAIL,  CCM_DVFS,
-   UART2,     NANDFC,        SDMA,      USB_HOST1,
-   USB_HOST2, USB_OTG,       RESERVED3, MSHC1,
-   MSHC2,     IPU_ERR,       IPU,       RESERVED4,
-   RESERVED5, UART1,         UART4,     UART5,
-   ETC_IRQ,   SCC_SCM,       SCC_SMN,   GPIO2,
-   GPIO1,     CCM_CLK,       PCMCIA,    WDOG,
-   GPIO3,     RESERVED6,     EXT_PWMG,  EXT_TEMP,
-   EXT_SENS1, EXT_SENS2,     EXT_WDOG,  EXT_TV,
-   ALL
+   INT_RESERVED0, INT_RESERVED1,     INT_RESERVED2, INT_I2C3,
+   INT_I2C2,      INT_MPEG4_ENCODER, INT_RTIC,      INT_FIR,
+   INT_MMC_SDHC2, INT_MMC_SDHC1,     INT_I2C1,      INT_SSI2,
+   INT_SSI1,      INT_CSPI2,         INT_CSPI1,     INT_ATA,
+   INT_MBX,       INT_CSPI3,         INT_UART3,     INT_IIM,
+   INT_SIM1,      INT_SIM2,          INT_RNGA,      INT_EVTMON,
+   INT_KPP,       INT_RTC,           INT_PWN,       INT_EPIT2,
+   INT_EPIT1,     INT_GPT,           INT_PWR_FAIL,  INT_CCM_DVFS,
+   INT_UART2,     INT_NANDFC,        INT_SDMA,      INT_USB_HOST1,
+   INT_USB_HOST2, INT_USB_OTG,       INT_RESERVED3, INT_MSHC1,
+   INT_MSHC2,     INT_IPU_ERR,       INT_IPU,       INT_RESERVED4,
+   INT_RESERVED5, INT_UART1,         INT_UART4,     INT_UART5,
+   INT_ETC_IRQ,   INT_SCC_SCM,       INT_SCC_SMN,   INT_GPIO2,
+   INT_GPIO1,     INT_CCM_CLK,       INT_PCMCIA,    INT_WDOG,
+   INT_GPIO3,     INT_RESERVED6,     INT_EXT_PWMG,  INT_EXT_TEMP,
+   INT_EXT_SENS1, INT_EXT_SENS2,     INT_EXT_WDOG,  INT_EXT_TV,
+   INT_ALL
 };
 
 void avic_init(void);
diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
index 8f75b72f58..8457d06a77 100644
--- a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
@@ -176,7 +176,8 @@ void _backlight_off(void)
     sleep(HZ/100);
 
     /* Write final PWM setting */
-    mc13783_write_masked(MC13783_LED_CONTROL2, MC13783_LEDMDDCw(0),
+    mc13783_write_masked(MC13783_LED_CONTROL2,
+                         0 << MC13783_LEDMDDC_POS,
                          MC13783_LEDMDDC);
 
 #ifdef HAVE_LCD_SLEEP
@@ -198,10 +199,10 @@ void _backlight_set_brightness(int brightness)
 
     md = led_md_pwm_table[brightness].md;
     backlight_pwm_bits = backlight_on_status ?
-        MC13783_LEDMDDCw(led_md_pwm_table[brightness].pwm) : 0;
+        (led_md_pwm_table[brightness].pwm << MC13783_LEDMDDC_POS) : 0;
 
     mc13783_write_masked(MC13783_LED_CONTROL2,
-                         MC13783_LEDMDw(md) | backlight_pwm_bits,
+                         (md << MC13783_LEDMD_POS) | backlight_pwm_bits,
                          MC13783_LEDMD | MC13783_LEDMDDC);
 
     mutex_unlock(&backlight_mutex);
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
index d2a46f2c9f..505ba397d9 100644
--- a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
@@ -197,7 +197,7 @@ void button_init_device(void)
 #endif
 
     /* Enable keypad clock */
-    imx31_clkctl_module_clock_gating(CG_KPP, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_KPP, CGM_ON_RUN_WAIT);
 
     /* 1. Enable number of rows in keypad (KPCR[4:0])
      *
@@ -219,8 +219,7 @@ void button_init_device(void)
      * 6. Set the KDIE control bit bit. */
     KPP_KPSR = KPP_KPSR_KDIE | KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKD;
 
-    /* KPP IRQ at priority 3 */
-    avic_enable_int(KPP, IRQ, 3, KPP_HANDLER);
+    avic_enable_int(INT_KPP, INT_TYPE_IRQ, INT_PRIO_DEFAULT, KPP_HANDLER);
 
     button_power_event();
     mc13783_enable_event(MC13783_ONOFD1_EVENT);
@@ -235,7 +234,7 @@ void button_close_device(void)
 {
     int oldlevel = disable_irq_save();
 
-    avic_disable_int(KPP);
+    avic_disable_int(INT_KPP);
     KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE);
     int_btn = BUTTON_NONE;
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
index df592deecb..761cf8f701 100644
--- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
@@ -24,47 +24,41 @@
 #include "cpu.h"
 #include "clkctl-imx31.h"
 
-unsigned int imx31_get_src_pll(void)
+unsigned int ccm_get_src_pll(void)
 {
-    return (CLKCTL_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU;
+    return (CCM_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU;
 }
 
-void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
-                                      enum IMX31_CG_MODES mode)
+void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode)
 {
     volatile unsigned long *reg;
     unsigned long mask;
     int shift;
-    int oldlevel;
 
     if (cg >= CG_NUM_CLOCKS)
         return;
 
-    reg = &CLKCTL_CGR0 + cg / 16;   /* Select CGR0, CGR1, CGR2 */
-    shift = 2*(cg % 16);            /* Get field shift */
-    mask = CG_MASK << shift;        /* Select field */
+    reg = &CCM_CGR0 + cg / 16;  /* Select CGR0, CGR1, CGR2 */
+    shift = 2*(cg % 16);        /* Get field shift */
+    mask = CG_MASK << shift;    /* Select field */
 
-    oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
-
-    *reg = (*reg & ~mask) | ((mode << shift) & mask);
-
-    restore_interrupt(oldlevel);
+    imx31_regmod32(reg, mode << shift, mask);
 }
 
 /* Get the PLL reference clock frequency in HZ */
-unsigned int imx31_clkctl_get_pll_ref_clk(void)
+unsigned int ccm_get_pll_ref_clk(void)
 {
-    if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1))
+    if ((CCM_CCMR & (3 << 1)) == (1 << 1))
         return CONFIG_CLK32_FREQ * 1024;
     else
         return CONFIG_HCLK_FREQ;
 }
 
 /* Return PLL frequency in HZ */
-unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll)
+unsigned int ccm_get_pll(enum IMX31_PLLS pll)
 {
-    uint32_t infreq = imx31_clkctl_get_pll_ref_clk();
-    uint32_t reg = (&CLKCTL_MPCTL)[pll];
+    uint32_t infreq = ccm_get_pll_ref_clk();
+    uint32_t reg = (&CCM_MPCTL)[pll];
     uint32_t mfn = reg & 0x3ff;
     uint32_t pd  = ((reg >> 26) & 0xf) + 1;
     uint64_t mfd = ((reg >> 16) & 0x3ff) + 1;
@@ -75,27 +69,27 @@ unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll)
     return 2*infreq*(mfi * mfd + mfn) / (mfd * pd);
 }
 
-unsigned int imx31_clkctl_get_ipg_clk(void)
+unsigned int ccm_get_ipg_clk(void)
 {
-    unsigned int pllnum = imx31_get_src_pll();
-    unsigned int pll = imx31_clkctl_get_pll(pllnum);
-    uint32_t reg = CLKCTL_PDR0;
+    unsigned int pllnum = ccm_get_src_pll();
+    unsigned int pll = ccm_get_pll(pllnum);
+    uint32_t reg = CCM_PDR0;
     unsigned int max_pdf = ((reg >> 3) & 0x7) + 1;
     unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1;
 
     return pll / (max_pdf * ipg_pdf);
 }
 
-unsigned int imx31_clkctl_get_ahb_clk(void)
+unsigned int ccm_get_ahb_clk(void)
 {
-    unsigned int pllnum = imx31_get_src_pll();
-    unsigned int pll = imx31_clkctl_get_pll(pllnum);
-    unsigned int max_pdf = ((CLKCTL_PDR0 >> 3) & 0x7) + 1;
+    unsigned int pllnum = ccm_get_src_pll();
+    unsigned int pll = ccm_get_pll(pllnum);
+    unsigned int max_pdf = ((CCM_PDR0 >> 3) & 0x7) + 1;
 
     return pll / max_pdf;
 }
 
-unsigned int imx31_clkctl_get_ata_clk(void)
+unsigned int ccm_get_ata_clk(void)
 {
-    return imx31_clkctl_get_ipg_clk();
+    return ccm_get_ipg_clk();
 }
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
index bd8f89a15b..e1057a9618 100644
--- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
+++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
@@ -20,8 +20,8 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef _CLKCTL_IMX31_H_
-#define _CLKCTL_IMX31_H_
+#ifndef _CCM_IMX31_H_
+#define _CCM_IMX31_H_
 
 enum IMX31_CG_LIST
 {
@@ -82,8 +82,8 @@ enum IMX31_CG_MODES
 
 /* Enable or disable module clocks independently - module must _not_ be
  * active! */
-void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
-                                      enum IMX31_CG_MODES mode);
+void ccm_module_clock_gating(enum IMX31_CG_LIST cg,
+                             enum IMX31_CG_MODES mode);
 
 enum IMX31_PLLS
 {
@@ -97,18 +97,18 @@ enum IMX31_PLLS
 #define CONFIG_HCLK_FREQ    27000000
 
 /* Get the PLL reference clock frequency in HZ */
-unsigned int imx31_clkctl_get_pll_ref_clk(void);
+unsigned int ccm_get_pll_ref_clk(void);
 
 /* Return PLL frequency in HZ */
-unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll);
+unsigned int ccm_get_pll(enum IMX31_PLLS pll);
 
 /* Return ipg_clk in HZ */
-unsigned int imx31_clkctl_get_ipg_clk(void);
+unsigned int ccm_get_ipg_clk(void);
 
 /* Return ahb_clk in HZ */
-unsigned int imx31_clkctl_get_ahb_clk(void);
+unsigned int ccm_get_ahb_clk(void);
 
 /* Return the ATA frequency in HZ */
-unsigned int imx31_clkctl_get_ata_clk(void);
+unsigned int ccm_get_ata_clk(void);
 
-#endif /* _CLKCTL_IMX31_H_ */
+#endif /* _CCM_IMX31_H_ */
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
index 7646402435..d846f4d1d0 100644
--- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
@@ -50,22 +50,18 @@ void fmradio_i2c_init(void)
      * disabled */
     imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1,
         /* RI_DTE1 (I2C2_SCLK) */
-        SW_PAD_CTL_IO2w(SW_PAD_CTL_PUE_PKE_DISABLE |
-                        SW_PAD_CTL_PUS_UP_100K |
-                        SW_PAD_CTL_HYS |
-                        SW_PAD_CTL_ODE) |
+        ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K |
+          SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO2_POS) |
         /* DCD_DTE1 (I2C2_SDA) */
-        SW_PAD_CTL_IO1w(SW_PAD_CTL_PUE_PKE_DISABLE |
-                        SW_PAD_CTL_PUS_UP_100K |
-                        SW_PAD_CTL_HYS |
-                        SW_PAD_CTL_ODE),
+        ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K |
+          SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO1_POS),
         SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1);
     /* set outputs to I2C2 */
     imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,
        /* RI_DTE1 => I2C2_SCLK */
-       SW_MUX_CTL_SIG4w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) |
+       ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG4_POS) |
        /* DCD_DTE1 => I2C2_SDA */
-       SW_MUX_CTL_SIG3w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2),
+       ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG3_POS),
        SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3);
 }
 
@@ -79,7 +75,8 @@ void fmradio_i2c_enable(bool enable)
         imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */
         /* I2C2_SDA => MCU2_15 */ 
         imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,
-            SW_MUX_CTL_SIG3w(SW_MUX_OUT_GPIO_DR | SW_MUX_IN_GPIO_PSR_ISR),
+            (SW_MUX_OUT_GPIO_DR |
+             SW_MUX_IN_GPIO_PSR_ISR) << SW_MUX_CTL_SIG3_POS,
             SW_MUX_CTL_SIG3);
         /* enable CLK32KMCU clock */
         mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN);
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c
index 446932b308..3d0ff977da 100644
--- a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c
@@ -22,6 +22,7 @@
  ****************************************************************************/
 #include "config.h"
 #include "system.h"
+#include "avic-imx31.h"
 #include "gpio-imx31.h"
 
 /* Gigabeat S definitions for static GPIO event registration */
@@ -44,7 +45,7 @@ static const struct gpio_event gpio1_events[] =
 /* Describes the events attached to GPIO1 port */
 const struct gpio_event_list gpio1_event_list =
 {
-    .ints_priority = 7,
+    .ints_priority = INT_PRIO_DEFAULT,
     .count         = ARRAYLEN(gpio1_events),
     .events        = gpio1_events,
 };
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c
index 090182bed4..944f70eae3 100644
--- a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c
@@ -55,21 +55,21 @@ static struct gpio_module_descriptor
 #if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS)
     {
         .base    = (struct gpio_map *)GPIO1_BASE_ADDR,
-        .ints    = GPIO1,
+        .ints    = INT_GPIO1,
         .handler = GPIO1_HANDLER,
     },
 #endif
 #if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS)
     {
         .base    = (struct gpio_map *)GPIO2_BASE_ADDR,
-        .ints    = GPIO2,
+        .ints    = INT_GPIO2,
         .handler = GPIO2_HANDLER,
     },
 #endif
 #if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS)
     {
         .base    = (struct gpio_map *)GPIO3_BASE_ADDR,
-        .ints    = GPIO3,
+        .ints    = INT_GPIO3,
         .handler = GPIO3_HANDLER,
     },
 #endif
@@ -168,7 +168,7 @@ bool gpio_enable_event(enum gpio_event_ids id)
     if (imr == 0)
     {
         /* First enabled interrupt for this GPIO */
-        avic_enable_int(desc->ints, IRQ, desc->list->ints_priority,
+        avic_enable_int(desc->ints, INT_TYPE_IRQ, desc->list->ints_priority,
                         desc->handler);
     }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
index bf69afedb7..05d761c9ce 100644
--- a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
@@ -57,7 +57,7 @@ static struct i2c_module_descriptor
     {
         .base    = (struct i2c_map *)I2C1_BASE_ADDR,
         .cg      = CG_I2C1,
-        .ints    = I2C1,
+        .ints    = INT_I2C1,
         .handler = I2C1_HANDLER,
     },
 #endif
@@ -65,7 +65,7 @@ static struct i2c_module_descriptor
     {
         .base    = (struct i2c_map *)I2C2_BASE_ADDR,
         .cg      = CG_I2C2,
-        .ints    = I2C2,
+        .ints    = INT_I2C2,
         .handler = I2C2_HANDLER,
     },
 #endif
@@ -73,7 +73,7 @@ static struct i2c_module_descriptor
     {
         .base    = (struct i2c_map *)I2C3_BASE_ADDR,
         .cg      = CG_I2C3,
-        .ints    = I2C3,
+        .ints    = INT_I2C3,
         .handler = I2C3_HANDLER,
     },
 #endif
@@ -286,11 +286,11 @@ void i2c_init(void)
     for (i = 0; i < I2C_NUM_I2C; i++)
     {
         struct i2c_module_descriptor *const desc = &i2c_descs[i];
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL);
+        ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT);
         mutex_init(&desc->m);
         wakeup_init(&desc->w);
         desc->base->i2cr = 0;
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF);
+        ccm_module_clock_gating(desc->cg, CGM_OFF);
     }
 }
 
@@ -305,8 +305,9 @@ void i2c_enable_node(struct i2c_node *node, bool enable)
         if (++desc->enable == 1)
         {
             /* First enable */
-            imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL);
-            avic_enable_int(desc->ints, IRQ, 7, desc->handler);
+            ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT);
+            avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                            desc->handler);
         }
     }
     else
@@ -317,7 +318,7 @@ void i2c_enable_node(struct i2c_node *node, bool enable)
             while (desc->base->i2sr & I2C_I2SR_IBB); /* Wait for STOP */
             desc->base->i2cr &= ~I2C_I2CR_IEN;
             avic_disable_int(desc->ints);
-            imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF);
+            ccm_module_clock_gating(desc->cg, CGM_OFF);
         }
     }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
index a2f3d779eb..01e9b8b721 100644
--- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -38,11 +38,11 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
 
 void tick_start(unsigned int interval_in_ms)
 {
-    imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_ON_ALL); /* EPIT1 module
+    ccm_module_clock_gating(CG_EPIT1, CGM_ON_RUN_WAIT); /* EPIT1 module
                                                clock ON - before writing
                                                regs! */
     EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */
-    CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT1;     /* Clear wakeup mask */
+    CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT1;  /* Clear wakeup mask */
 
     /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1)
      * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz,
@@ -53,13 +53,14 @@ void tick_start(unsigned int interval_in_ms)
      * Compare interrupt enabled,
      * Count from load value */
     EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
-              EPITCR_PRESCALER(2640-1) | EPITCR_RLD | EPITCR_OCIEN |
+              (2640-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_OCIEN |
               EPITCR_ENMOD;
  
     EPITLR1 = interval_in_ms*25; /* Count down from interval */
     EPITCMPR1 = 0;               /* Event when counter reaches 0 */
     EPITSR1 = EPITSR_OCIF;       /* Clear any pending interrupt */
-    avic_enable_int(EPIT1, IRQ, 7, EPIT1_HANDLER);
+    avic_enable_int(INT_EPIT1, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                    EPIT1_HANDLER);
     EPITCR1 |= EPITCR_EN;        /* Enable the counter */
 }
 
@@ -73,9 +74,9 @@ void kernel_device_init(void)
 #ifdef BOOTLOADER
 void tick_stop(void)
 {
-    avic_disable_int(EPIT1);                /* Disable insterrupt */
+    avic_disable_int(INT_EPIT1);            /* Disable insterrupt */
     EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */
     EPITSR1 = EPITSR_OCIF;                  /* Clear pending */
-    imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */
+    ccm_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */
 }
 #endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
index deaa2a0dcd..00f196a512 100644
--- a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
@@ -130,8 +130,8 @@ void pcm_play_dma_init(void)
     sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd);
     sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY);
 
-    imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL);
-    imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_SSI1, CGM_ON_RUN_WAIT);
+    ccm_module_clock_gating(CG_SSI2, CGM_ON_RUN_WAIT);
 
     /* Reset & disable SSIs */
     SSI_SCR1 &= ~SSI_SCR_SSIEN;
@@ -178,12 +178,12 @@ void pcm_play_dma_init(void)
                 SSI_STCR_TEFS | SSI_STCR_TFEN0;
 
     /* 16 bits per word, 2 words per frame */
-    SSI_STCCR2 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
-                 SSI_STRCCR_PMw(4-1);
+    SSI_STCCR2 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) |
+                 ((4-1) << SSI_STRCCR_PM_POS);
 
     /* Transmit low watermark */
     SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_TFWM0) |
-                 SSI_SFCSR_TFWM0w(8-SDMA_SSI_TXFIFO_WML);
+                 ((8-SDMA_SSI_TXFIFO_WML) << SSI_SFCSR_TFWM0_POS);
     SSI_STMSK2 = 0;
 
     /* SSI1 - provides MCLK to codec. Receives data from codec. */
@@ -201,7 +201,7 @@ void pcm_play_dma_init(void)
      * The hardware seems to force a divide by 4 even if all bits are
      * zero but comply by setting DIV2 and the others to zero.
      */
-    SSI_STCCR1 = SSI_STRCCR_DIV2 | SSI_STRCCR_PMw(1-1);
+    SSI_STCCR1 = SSI_STRCCR_DIV2 | ((1-1) << SSI_STRCCR_PM_POS);
 
     /* SSI1 - receive - asynchronous clocks */
     SSI_SCR1 = SSI_SCR_I2S_MODE_SLAVE;
@@ -210,12 +210,12 @@ void pcm_play_dma_init(void)
                 SSI_SRCR_REFS;
 
     /* 16 bits per word, 2 words per frame */
-    SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
-                 SSI_STRCCR_PMw(4-1);
+    SSI_SRCCR1 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) |
+                 ((4-1) << SSI_STRCCR_PM_POS);
 
     /* Receive high watermark */
     SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_RFWM0) |
-                 SSI_SFCSR_RFWM0w(SDMA_SSI_RXFIFO_WML);
+                 (SDMA_SSI_RXFIFO_WML << SSI_SFCSR_RFWM0_POS);
     SSI_SRMSK1 = 0;
 
     /* Enable SSI1 (codec clock) */
@@ -252,7 +252,7 @@ static void play_start_pcm(void)
 static void play_stop_pcm(void)
 {
     /* Wait for FIFO to empty */
-    while (SSI_SFCSR_TFCNT0r(SSI_SFCSR2) > 0);
+    while (SSI_SFCSR_TFCNT0 & SSI_SFCSR2);
 
     /* Disable transmission */
     SSI_STCR2 &= ~SSI_STCR_TFEN0;
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
index 98604d1eef..f905057372 100644
--- a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
@@ -58,7 +58,7 @@ static struct spi_module_descriptor
     {
         .base    = (struct cspi_map *)CSPI1_BASE_ADDR,
         .cg      = CG_CSPI1,
-        .ints    = CSPI1,
+        .ints    = INT_CSPI1,
         .handler = CSPI1_HANDLER,
     },
 #endif
@@ -66,7 +66,7 @@ static struct spi_module_descriptor
     {
         .base    = (struct cspi_map *)CSPI2_BASE_ADDR,
         .cg      = CG_CSPI2,
-        .ints    = CSPI2,
+        .ints    = INT_CSPI2,
         .handler = CSPI2_HANDLER,
     },
 #endif
@@ -74,7 +74,7 @@ static struct spi_module_descriptor
     {
         .base    = (struct cspi_map *)CSPI3_BASE_ADDR,
         .cg      = CG_CSPI3,
-        .ints    = CSPI3,
+        .ints    = INT_CSPI3,
         .handler = CSPI3_HANDLER,
     },
 #endif
@@ -267,12 +267,13 @@ void spi_enable_module(struct spi_node *node)
         struct cspi_map * const base = desc->base;
 
         /* Enable clock-gating register */
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL);
+        ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT);
         /* Reset */
         spi_reset(base);
         desc->last = NULL;
         /* Enable interrupt at controller level */
-        avic_enable_int(desc->ints, IRQ, 6, desc->handler);
+        avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                        desc->handler);
     }
 
     mutex_unlock(&desc->m);
@@ -297,7 +298,7 @@ void spi_disable_module(struct spi_node *node)
         base->conreg &= ~CSPI_CONREG_EN;
 
         /* Disable interface clock */
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF);
+        ccm_module_clock_gating(desc->cg, CGM_OFF);
     }
 
     mutex_unlock(&desc->m);
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
index b3f0fd66c9..c710c5b93c 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
@@ -49,7 +49,7 @@ unsigned int iim_prod_rev(void)
 static void iim_init(void)
 {
     /* Initialize the IC revision info (required by SDMA) */
-    imx31_clkctl_module_clock_gating(CG_IIM, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_IIM, CGM_ON_RUN_WAIT);
     product_rev = IIM_PREV;
     system_rev = IIM_SREV;
 }
@@ -59,13 +59,13 @@ static void iim_init(void)
 /* Initialize the watchdog timer */
 void watchdog_init(unsigned int half_seconds)
 {
-    uint16_t wcr = WDOG_WCR_WTw(half_seconds) | /* Timeout */
+    uint16_t wcr = ((half_seconds << WDOG_WCR_WT_POS) & WDOG_WCR_WT) |
                    WDOG_WCR_WOE |       /* WDOG output enabled */
                    WDOG_WCR_WDA |       /* WDOG assertion - no effect */
                    WDOG_WCR_SRS |       /* System reset - no effect */
                    WDOG_WCR_WRE;        /* Generate a WDOG signal */
 
-    imx31_clkctl_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT);
+    ccm_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT);
 
     WDOG_WCR = wcr;
     WDOG_WSR = 0x5555;
@@ -86,8 +86,8 @@ void watchdog_service(void)
 /* Start the general-purpose timer (1MHz) */
 void gpt_start(void)
 {
-    imx31_clkctl_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
-    unsigned int ipg_mhz = imx31_clkctl_get_ipg_clk() / 1000000;
+    ccm_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
+    unsigned int ipg_mhz = ccm_get_ipg_clk() / 1000000;
 
     GPTCR &= ~GPTCR_EN; /* Disable counter */
     GPTCR |= GPTCR_SWR; /* Reset module */
@@ -123,7 +123,7 @@ void system_reboot(void)
 void system_exception_wait(void)
 {
     /* Called in many contexts so button reading may be a chore */
-    avic_disable_int(ALL);
+    avic_disable_int(INT_ALL);
     core_idle();
     while (1);
 }
@@ -174,8 +174,8 @@ void system_init(void)
 
     unsigned int i;
 
-    /* MCR WFI enables wait mode */
-    CLKCTL_CCMR &= ~(3 << 14);
+    /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */
+    imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM);
 
     iim_init();
 
@@ -189,7 +189,7 @@ void system_init(void)
     imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN);
 
     for (i = 0; i < ARRAYLEN(disable_clocks); i++)
-        imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF);
+        ccm_module_clock_gating(disable_clocks[i], CGM_OFF);
 
     avic_init();
     gpt_start();
@@ -242,7 +242,7 @@ void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p,
 void system_prepare_fw_start(void)
 {
     disable_interrupt(IRQ_FIQ_STATUS);
-    avic_disable_int(ALL);
+    avic_disable_int(INT_ALL);
     mc13783_close();
     tick_stop();
 }
diff --git a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
index 531baf3cc5..c4734a543b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
@@ -35,11 +35,11 @@ static void __attribute__((interrupt("IRQ"))) EPIT2_HANDLER(void)
 static void stop_timer(bool clock_off)
 {
     /* Ensure clock gating on (before touching any module registers) */
-    imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_EPIT2, CGM_ON_RUN_WAIT);
     /* Disable insterrupt */
-    avic_disable_int(EPIT2);
+    avic_disable_int(INT_EPIT2);
     /* Clear wakeup mask */
-    CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT2;
+    CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT2;
     /* Disable counter */
     EPITCR2 &= ~(EPITCR_OCIEN | EPITCR_EN);
     /* Clear pending */
@@ -48,7 +48,7 @@ static void stop_timer(bool clock_off)
     if (clock_off)
     {
         /* Final stop, not reset; don't clock module any longer */
-        imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_OFF);
+        ccm_module_clock_gating(CG_EPIT2, CGM_OFF);
     }
 }
 
@@ -77,7 +77,7 @@ bool _timer_set(long cycles, bool start)
      * Reload from modulus register,
      * Count from load value */
     EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
-              EPITCR_PRESCALER(1-1) | EPITCR_RLD | EPITCR_ENMOD;
+              (1-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_ENMOD;
     EPITLR2 = cycles;
     /* Event when counter reaches 0 */
     EPITCMPR2 = 0;
@@ -95,7 +95,8 @@ bool _timer_register(void)
 
     /* Enable interrupt */
     EPITCR2 |= EPITCR_OCIEN;
-    avic_enable_int(EPIT2, IRQ, 8, EPIT2_HANDLER);
+    avic_enable_int(INT_EPIT2, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                    EPIT2_HANDLER);
     /* Start timer */
     EPITCR2 |= EPITCR_EN;
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
index 8682cff7c7..2011d0c633 100644
--- a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
@@ -89,7 +89,7 @@ void usb_enable(bool on)
 {
     /* Module clock should be on since since this could be called with
      * OFF initially and writing module registers would hardlock otherwise. */
-    imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_USBOTG, CGM_ON_RUN_WAIT);
     enable_transceiver(true);
 
     if (on)
@@ -100,7 +100,7 @@ void usb_enable(bool on)
     {
         usb_core_exit();
         enable_transceiver(false);
-        imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_OFF);
+        ccm_module_clock_gating(CG_USBOTG, CGM_OFF);
     }
 }
 
@@ -117,9 +117,14 @@ static void __attribute__((interrupt("IRQ"))) USB_OTG_HANDLER(void)
 void usb_drv_int_enable(bool enable)
 {
     if (enable)
-        avic_enable_int(USB_OTG, IRQ, 7, USB_OTG_HANDLER);
-    else    
-        avic_disable_int(USB_OTG);
+    {
+        avic_enable_int(INT_USB_OTG, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                        USB_OTG_HANDLER);
+    }
+    else
+    {
+        avic_disable_int(INT_USB_OTG);
+    }
 }
 
 /* Called during the bus reset interrupt when in detect mode */
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
index 542f6eb633..cf9331144a 100644
--- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
@@ -52,11 +52,13 @@ void audiohw_init(void)
      * WM Codec post divider (MCLKDIV=1.5):
      * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK
      */
-    imx31_regmod32(&CLKCTL_PDR1,
-                   PDR1_SSI1_PODFw(5-1) | PDR1_SSI2_PODFw(64-1) |
-                   PDR1_SSI1_PRE_PODFw(1-1) | PDR1_SSI2_PRE_PODFw(8-1),
-                   PDR1_SSI1_PODF | PDR1_SSI2_PODF |
-                   PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF);
+    imx31_regmod32(&CCM_PDR1,
+                   (1-1) << CCM_PDR1_SSI1_PRE_PODF_POS |
+                   (5-1) << CCM_PDR1_SSI1_PODF_POS |
+                   (8-1) << CCM_PDR1_SSI2_PRE_PODF_POS,
+                   (64-1) << CCM_PDR1_SSI2_PODF_POS |
+                   CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF |
+                   CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF);
 
     i2c_enable_node(&wm8978_i2c_node, true);
 
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c
index 4c5674afb9..97af419077 100644
--- a/firmware/target/arm/imx31/sdma-imx31.c
+++ b/firmware/target/arm/imx31/sdma-imx31.c
@@ -502,10 +502,11 @@ static bool setup_channel(struct channel_control_block *ccb_p)
 /** Public routines **/
 void sdma_init(void)
 {
-    imx31_clkctl_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT);
     int i;
     unsigned long acr;
 
+    ccm_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT);
+
     /* Reset the controller */
     SDMA_RESET |= SDMA_RESET_RESET;
     while (SDMA_RESET & SDMA_RESET_RESET);
@@ -532,11 +533,11 @@ void sdma_init(void)
     /* 32-word channel contexts, use default bootscript address */
     SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050;
 
-    avic_enable_int(SDMA, IRQ, 8, SDMA_HANDLER);
+    avic_enable_int(INT_SDMA, INT_TYPE_IRQ, INT_PRIO_DEFAULT+1, SDMA_HANDLER);
 
-    /* SDMA core must run at the proper frequency based upon the AHB/IPG ratio */
-    acr = (imx31_clkctl_get_ahb_clk() / imx31_clkctl_get_ipg_clk()) < 2 ?
-          SDMA_CONFIG_ACR : 0;
+    /* SDMA core must run at the proper frequency based upon the AHB/IPG
+     * ratio */
+    acr = (ccm_get_ahb_clk() / ccm_get_ipg_clk()) < 2 ? SDMA_CONFIG_ACR : 0;
 
     /* No dsp, no debug
      * Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0