imx31/mc13783: Do some housekeeping with register macros, function names and other defines. No functional changes (except to alter a couple int priorities).

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20442 a1c6a512-1295-4272-9138-f99709370657

21 files changed, 174 insertions, 166 deletions

diff --git a/firmware/target/arm/imx31/debug-imx31.c b/firmware/target/arm/imx31/debug-imx31.c
index ad436ea231..abf180cfd2 100644
--- a/firmware/target/arm/imx31/debug-imx31.c
+++ b/firmware/target/arm/imx31/debug-imx31.c
@@ -50,15 +50,15 @@ bool __dbg_hw_info(void)
                  iim_system_rev());
         lcd_puts(0, line++, buf); line++;
 
-        mpctl = CLKCTL_MPCTL;
-        spctl = CLKCTL_SPCTL;
-        upctl = CLKCTL_UPCTL;
+        mpctl = CCM_MPCTL;
+        spctl = CCM_SPCTL;
+        upctl = CCM_UPCTL;
 
-        pllref = imx31_clkctl_get_pll_ref_clk();
+        pllref = ccm_get_pll_ref_clk();
 
-        mcu_pllfreq = imx31_clkctl_get_pll(PLL_MCU);
-        ser_pllfreq = imx31_clkctl_get_pll(PLL_SERIAL);
-        usb_pllfreq = imx31_clkctl_get_pll(PLL_USB);
+        mcu_pllfreq = ccm_get_pll(PLL_MCU);
+        ser_pllfreq = ccm_get_pll(PLL_SERIAL);
+        usb_pllfreq = ccm_get_pll(PLL_USB);
 
         snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref);
         lcd_puts(0, line++, buf); line++;
@@ -70,7 +70,7 @@ bool __dbg_hw_info(void)
         snprintf(buf, sizeof (buf), " mpl_dpdgck_clk: %u", mcu_pllfreq);
         lcd_puts(0, line++, buf); line++;
 
-        regval = CLKCTL_PDR0;
+        regval = CCM_PDR0;
         snprintf(buf, sizeof (buf), "  PDR0: %08lX", regval);
         lcd_puts(0, line++, buf);
 
@@ -111,7 +111,7 @@ bool __dbg_hw_info(void)
         snprintf(buf, sizeof (buf), " upl_dpdgck_clk: %u", usb_pllfreq);
         lcd_puts(0, line++, buf); line++;
 
-        regval = CLKCTL_PDR1;
+        regval = CCM_PDR1;
         snprintf(buf, sizeof (buf), "  PDR1: %08lX", regval);
         lcd_puts(0, line++, buf);
 
@@ -120,7 +120,7 @@ bool __dbg_hw_info(void)
         snprintf(buf, sizeof (buf), "   usb_clk:       %u", freq);
         lcd_puts(0, line++, buf);
 
-        freq = usb_pllfreq / (((CLKCTL_PDR0 >> 16) & 0x1f) + 1);
+        freq = usb_pllfreq / (((CCM_PDR0 >> 16) & 0x1f) + 1);
         snprintf(buf, sizeof (buf), "   ipg_per_baud:  %u", freq);
         lcd_puts(0, line++, buf);
           
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
index 3c66c42adc..52293228f8 100644
--- a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
@@ -57,8 +57,8 @@ unsigned short adc_read(int channel)
     {
         /* Keep enable, start conversion, increment from channel 0,
          * increment from channel 4 */
-        uint32_t adc1 = MC13783_ADEN | MC13783_ASC | MC13783_ADA1w(0) |
-                        MC13783_ADA2w(4);
+        uint32_t adc1 = MC13783_ADEN | MC13783_ASC |
+                        (0 << MC13783_ADA1_POS) | (4 << MC13783_ADA2_POS);
 
         if (input_select == 1)
             adc1 |= MC13783_ADSEL; /* 2nd set of inputs */
@@ -81,7 +81,9 @@ unsigned short adc_read(int channel)
     mutex_unlock(&adc_mtx);
 
     /* Channels 0-3/8-11 in ADD1, 4-7/12-15 in ADD2 */
-    return (channel & 4) ? MC13783_ADD2r(data) : MC13783_ADD1r(data);
+    return (channel & 4) ?
+        ((data & MC13783_ADD2) >> MC13783_ADD2_POS) :
+        ((data & MC13783_ADD1) >> MC13783_ADD1_POS);
 }
 
 bool adc_enable_channel(int channel, bool enable)
diff --git a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
index c32dead30a..c941037317 100644
--- a/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
@@ -275,7 +275,7 @@ static unsigned long ata_dma_selected = ATA_DMA_PIO;
 static unsigned int get_T(void)
 {
     /* T = ATA clock period in nanoseconds */
-    return 1000 * 1000 * 1000 / imx31_clkctl_get_ata_clk();
+    return 1000 * 1000 * 1000 / ccm_get_ata_clk();
 }
 
 static void ata_wait_for_idle(void)
@@ -325,7 +325,7 @@ void ata_reset(void)
 void ata_enable(bool on)
 {
     /* Unconditionally clock module before writing regs */
-    imx31_clkctl_module_clock_gating(CG_ATA, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_ATA, CGM_ON_RUN_WAIT);
     ata_wait_for_idle();
 
     if (on)
@@ -339,7 +339,7 @@ void ata_enable(bool on)
         sleep(HZ/100);
 
         /* Disable off - unclock ATA module */
-        imx31_clkctl_module_clock_gating(CG_ATA, CGM_OFF);
+        ccm_module_clock_gating(CG_ATA, CGM_OFF);
     }
 }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
index a135889e6e..4ba7da4be0 100644
--- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c
@@ -59,7 +59,7 @@ void UIE_VECTOR(void)
     );
 
     offset = mode == 0x11 ?
-        (int32_t)FIVECSR : ((int32_t)NIVECSR >> 16);
+        (int32_t)AVIC_FIVECSR : ((int32_t)AVIC_NIVECSR >> 16);
 
     panicf("Unhandled %s %d: %s",
            mode == 0x11 ? "FIQ" : "IRQ", offset,
@@ -69,7 +69,7 @@ void UIE_VECTOR(void)
 /* We use the AVIC */
 void __attribute__((interrupt("IRQ"))) irq_handler(void)
 {
-    const int offset = (int32_t)NIVECSR >> 16;
+    const int offset = (int32_t)AVIC_NIVECSR >> 16;
 
     if (offset == -1)
     {
@@ -105,20 +105,20 @@ void avic_init(void)
     int i;
 
     /* Disable all interrupts and set to unhandled */
-    avic_disable_int(ALL);
+    avic_disable_int(INT_ALL);
 
     /* Reset AVIC control */
     avic->intcntl = 0;
 
     /* Init all interrupts to type IRQ */
-    avic_set_int_type(ALL, IRQ);
+    avic_set_int_type(INT_ALL, INT_TYPE_IRQ);
 
     /* Set all normal to lowest priority */
     for (i = 0; i < 8; i++)
         avic->nipriority[i] = 0;
 
     /* Set NM bit to enable VIC */
-    avic->intcntl |= INTCNTL_NM;
+    avic->intcntl |= AVIC_INTCNTL_NM;
 
     /* Enable VE bit in CP15 Control reg to enable VIC */
     asm volatile (
@@ -147,7 +147,7 @@ void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
     struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 
-    if (ints != ALL) /* No mass-enable allowed */
+    if (ints != INT_ALL) /* No mass-enable allowed */
     {
         avic_set_int_type(ints, intstype);
         avic->vector[ints] = (long)handler;
@@ -163,7 +163,7 @@ void avic_disable_int(enum IMX31_INT_LIST ints)
     struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
     uint32_t i;
 
-    if (ints == ALL)
+    if (ints == INT_ALL)
     {
         for (i = 0; i < 64; i++)
         {
@@ -185,7 +185,7 @@ static void set_int_type(int i, enum INT_TYPE intstype)
     volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)];
     uint32_t val = 1L << (i & 0x1f);
 
-    if (intstype == IRQ)
+    if (intstype == INT_TYPE_IRQ)
         val = *reg & ~val;
     else
         val = *reg | val;
@@ -197,7 +197,7 @@ void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype)
 {
     int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 
-    if (ints == ALL)
+    if (ints == INT_ALL)
     {
         int i;
         for (i = 0; i < 64; i++)
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
index 3580c8c083..a049713600 100644
--- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
+++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h
@@ -172,32 +172,34 @@ struct avic_map
     };
 };
 
+#define INT_PRIO_DEFAULT    7
+
 enum INT_TYPE
 {
-    IRQ = 0,
-    FIQ
+    INT_TYPE_IRQ = 0,
+    INT_TYPE_FIQ
 };
 
 enum IMX31_INT_LIST
 {
     __IMX31_INT_FIRST = -1,
-   RESERVED0, RESERVED1,     RESERVED2, I2C3,
-   I2C2,      MPEG4_ENCODER, RTIC,      FIR,
-   MMC_SDHC2, MMC_SDHC1,     I2C1,      SSI2,
-   SSI1,      CSPI2,         CSPI1,     ATA,
-   MBX,       CSPI3,         UART3,     IIM,
-   SIM1,      SIM2,          RNGA,      EVTMON,
-   KPP,       RTC,           PWN,       EPIT2,
-   EPIT1,     GPT,           PWR_FAIL,  CCM_DVFS,
-   UART2,     NANDFC,        SDMA,      USB_HOST1,
-   USB_HOST2, USB_OTG,       RESERVED3, MSHC1,
-   MSHC2,     IPU_ERR,       IPU,       RESERVED4,
-   RESERVED5, UART1,         UART4,     UART5,
-   ETC_IRQ,   SCC_SCM,       SCC_SMN,   GPIO2,
-   GPIO1,     CCM_CLK,       PCMCIA,    WDOG,
-   GPIO3,     RESERVED6,     EXT_PWMG,  EXT_TEMP,
-   EXT_SENS1, EXT_SENS2,     EXT_WDOG,  EXT_TV,
-   ALL
+   INT_RESERVED0, INT_RESERVED1,     INT_RESERVED2, INT_I2C3,
+   INT_I2C2,      INT_MPEG4_ENCODER, INT_RTIC,      INT_FIR,
+   INT_MMC_SDHC2, INT_MMC_SDHC1,     INT_I2C1,      INT_SSI2,
+   INT_SSI1,      INT_CSPI2,         INT_CSPI1,     INT_ATA,
+   INT_MBX,       INT_CSPI3,         INT_UART3,     INT_IIM,
+   INT_SIM1,      INT_SIM2,          INT_RNGA,      INT_EVTMON,
+   INT_KPP,       INT_RTC,           INT_PWN,       INT_EPIT2,
+   INT_EPIT1,     INT_GPT,           INT_PWR_FAIL,  INT_CCM_DVFS,
+   INT_UART2,     INT_NANDFC,        INT_SDMA,      INT_USB_HOST1,
+   INT_USB_HOST2, INT_USB_OTG,       INT_RESERVED3, INT_MSHC1,
+   INT_MSHC2,     INT_IPU_ERR,       INT_IPU,       INT_RESERVED4,
+   INT_RESERVED5, INT_UART1,         INT_UART4,     INT_UART5,
+   INT_ETC_IRQ,   INT_SCC_SCM,       INT_SCC_SMN,   INT_GPIO2,
+   INT_GPIO1,     INT_CCM_CLK,       INT_PCMCIA,    INT_WDOG,
+   INT_GPIO3,     INT_RESERVED6,     INT_EXT_PWMG,  INT_EXT_TEMP,
+   INT_EXT_SENS1, INT_EXT_SENS2,     INT_EXT_WDOG,  INT_EXT_TV,
+   INT_ALL
 };
 
 void avic_init(void);
diff --git a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
index 8f75b72f58..8457d06a77 100644
--- a/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/backlight-imx31.c
@@ -176,7 +176,8 @@ void _backlight_off(void)
     sleep(HZ/100);
 
     /* Write final PWM setting */
-    mc13783_write_masked(MC13783_LED_CONTROL2, MC13783_LEDMDDCw(0),
+    mc13783_write_masked(MC13783_LED_CONTROL2,
+                         0 << MC13783_LEDMDDC_POS,
                          MC13783_LEDMDDC);
 
 #ifdef HAVE_LCD_SLEEP
@@ -198,10 +199,10 @@ void _backlight_set_brightness(int brightness)
 
     md = led_md_pwm_table[brightness].md;
     backlight_pwm_bits = backlight_on_status ?
-        MC13783_LEDMDDCw(led_md_pwm_table[brightness].pwm) : 0;
+        (led_md_pwm_table[brightness].pwm << MC13783_LEDMDDC_POS) : 0;
 
     mc13783_write_masked(MC13783_LED_CONTROL2,
-                         MC13783_LEDMDw(md) | backlight_pwm_bits,
+                         (md << MC13783_LEDMD_POS) | backlight_pwm_bits,
                          MC13783_LEDMD | MC13783_LEDMDDC);
 
     mutex_unlock(&backlight_mutex);
diff --git a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
index d2a46f2c9f..505ba397d9 100644
--- a/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/button-imx31.c
@@ -197,7 +197,7 @@ void button_init_device(void)
 #endif
 
     /* Enable keypad clock */
-    imx31_clkctl_module_clock_gating(CG_KPP, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_KPP, CGM_ON_RUN_WAIT);
 
     /* 1. Enable number of rows in keypad (KPCR[4:0])
      *
@@ -219,8 +219,7 @@ void button_init_device(void)
      * 6. Set the KDIE control bit bit. */
     KPP_KPSR = KPP_KPSR_KDIE | KPP_KPSR_KRSS | KPP_KPSR_KDSC | KPP_KPSR_KPKD;
 
-    /* KPP IRQ at priority 3 */
-    avic_enable_int(KPP, IRQ, 3, KPP_HANDLER);
+    avic_enable_int(INT_KPP, INT_TYPE_IRQ, INT_PRIO_DEFAULT, KPP_HANDLER);
 
     button_power_event();
     mc13783_enable_event(MC13783_ONOFD1_EVENT);
@@ -235,7 +234,7 @@ void button_close_device(void)
 {
     int oldlevel = disable_irq_save();
 
-    avic_disable_int(KPP);
+    avic_disable_int(INT_KPP);
     KPP_KPSR &= ~(KPP_KPSR_KRIE | KPP_KPSR_KDIE);
     int_btn = BUTTON_NONE;
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
index df592deecb..761cf8f701 100644
--- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.c
@@ -24,47 +24,41 @@
 #include "cpu.h"
 #include "clkctl-imx31.h"
 
-unsigned int imx31_get_src_pll(void)
+unsigned int ccm_get_src_pll(void)
 {
-    return (CLKCTL_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU;
+    return (CCM_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU;
 }
 
-void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
-                                      enum IMX31_CG_MODES mode)
+void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode)
 {
     volatile unsigned long *reg;
     unsigned long mask;
     int shift;
-    int oldlevel;
 
     if (cg >= CG_NUM_CLOCKS)
         return;
 
-    reg = &CLKCTL_CGR0 + cg / 16;   /* Select CGR0, CGR1, CGR2 */
-    shift = 2*(cg % 16);            /* Get field shift */
-    mask = CG_MASK << shift;        /* Select field */
+    reg = &CCM_CGR0 + cg / 16;  /* Select CGR0, CGR1, CGR2 */
+    shift = 2*(cg % 16);        /* Get field shift */
+    mask = CG_MASK << shift;    /* Select field */
 
-    oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
-
-    *reg = (*reg & ~mask) | ((mode << shift) & mask);
-
-    restore_interrupt(oldlevel);
+    imx31_regmod32(reg, mode << shift, mask);
 }
 
 /* Get the PLL reference clock frequency in HZ */
-unsigned int imx31_clkctl_get_pll_ref_clk(void)
+unsigned int ccm_get_pll_ref_clk(void)
 {
-    if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1))
+    if ((CCM_CCMR & (3 << 1)) == (1 << 1))
         return CONFIG_CLK32_FREQ * 1024;
     else
         return CONFIG_HCLK_FREQ;
 }
 
 /* Return PLL frequency in HZ */
-unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll)
+unsigned int ccm_get_pll(enum IMX31_PLLS pll)
 {
-    uint32_t infreq = imx31_clkctl_get_pll_ref_clk();
-    uint32_t reg = (&CLKCTL_MPCTL)[pll];
+    uint32_t infreq = ccm_get_pll_ref_clk();
+    uint32_t reg = (&CCM_MPCTL)[pll];
     uint32_t mfn = reg & 0x3ff;
     uint32_t pd  = ((reg >> 26) & 0xf) + 1;
     uint64_t mfd = ((reg >> 16) & 0x3ff) + 1;
@@ -75,27 +69,27 @@ unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll)
     return 2*infreq*(mfi * mfd + mfn) / (mfd * pd);
 }
 
-unsigned int imx31_clkctl_get_ipg_clk(void)
+unsigned int ccm_get_ipg_clk(void)
 {
-    unsigned int pllnum = imx31_get_src_pll();
-    unsigned int pll = imx31_clkctl_get_pll(pllnum);
-    uint32_t reg = CLKCTL_PDR0;
+    unsigned int pllnum = ccm_get_src_pll();
+    unsigned int pll = ccm_get_pll(pllnum);
+    uint32_t reg = CCM_PDR0;
     unsigned int max_pdf = ((reg >> 3) & 0x7) + 1;
     unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1;
 
     return pll / (max_pdf * ipg_pdf);
 }
 
-unsigned int imx31_clkctl_get_ahb_clk(void)
+unsigned int ccm_get_ahb_clk(void)
 {
-    unsigned int pllnum = imx31_get_src_pll();
-    unsigned int pll = imx31_clkctl_get_pll(pllnum);
-    unsigned int max_pdf = ((CLKCTL_PDR0 >> 3) & 0x7) + 1;
+    unsigned int pllnum = ccm_get_src_pll();
+    unsigned int pll = ccm_get_pll(pllnum);
+    unsigned int max_pdf = ((CCM_PDR0 >> 3) & 0x7) + 1;
 
     return pll / max_pdf;
 }
 
-unsigned int imx31_clkctl_get_ata_clk(void)
+unsigned int ccm_get_ata_clk(void)
 {
-    return imx31_clkctl_get_ipg_clk();
+    return ccm_get_ipg_clk();
 }
diff --git a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
index bd8f89a15b..e1057a9618 100644
--- a/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
+++ b/firmware/target/arm/imx31/gigabeat-s/clkctl-imx31.h
@@ -20,8 +20,8 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
-#ifndef _CLKCTL_IMX31_H_
-#define _CLKCTL_IMX31_H_
+#ifndef _CCM_IMX31_H_
+#define _CCM_IMX31_H_
 
 enum IMX31_CG_LIST
 {
@@ -82,8 +82,8 @@ enum IMX31_CG_MODES
 
 /* Enable or disable module clocks independently - module must _not_ be
  * active! */
-void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
-                                      enum IMX31_CG_MODES mode);
+void ccm_module_clock_gating(enum IMX31_CG_LIST cg,
+                             enum IMX31_CG_MODES mode);
 
 enum IMX31_PLLS
 {
@@ -97,18 +97,18 @@ enum IMX31_PLLS
 #define CONFIG_HCLK_FREQ    27000000
 
 /* Get the PLL reference clock frequency in HZ */
-unsigned int imx31_clkctl_get_pll_ref_clk(void);
+unsigned int ccm_get_pll_ref_clk(void);
 
 /* Return PLL frequency in HZ */
-unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll);
+unsigned int ccm_get_pll(enum IMX31_PLLS pll);
 
 /* Return ipg_clk in HZ */
-unsigned int imx31_clkctl_get_ipg_clk(void);
+unsigned int ccm_get_ipg_clk(void);
 
 /* Return ahb_clk in HZ */
-unsigned int imx31_clkctl_get_ahb_clk(void);
+unsigned int ccm_get_ahb_clk(void);
 
 /* Return the ATA frequency in HZ */
-unsigned int imx31_clkctl_get_ata_clk(void);
+unsigned int ccm_get_ata_clk(void);
 
-#endif /* _CLKCTL_IMX31_H_ */
+#endif /* _CCM_IMX31_H_ */
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
index 7646402435..d846f4d1d0 100644
--- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
@@ -50,22 +50,18 @@ void fmradio_i2c_init(void)
      * disabled */
     imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1,
         /* RI_DTE1 (I2C2_SCLK) */
-        SW_PAD_CTL_IO2w(SW_PAD_CTL_PUE_PKE_DISABLE |
-                        SW_PAD_CTL_PUS_UP_100K |
-                        SW_PAD_CTL_HYS |
-                        SW_PAD_CTL_ODE) |
+        ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K |
+          SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO2_POS) |
         /* DCD_DTE1 (I2C2_SDA) */
-        SW_PAD_CTL_IO1w(SW_PAD_CTL_PUE_PKE_DISABLE |
-                        SW_PAD_CTL_PUS_UP_100K |
-                        SW_PAD_CTL_HYS |
-                        SW_PAD_CTL_ODE),
+        ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K |
+          SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO1_POS),
         SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1);
     /* set outputs to I2C2 */
     imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,
        /* RI_DTE1 => I2C2_SCLK */
-       SW_MUX_CTL_SIG4w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) |
+       ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG4_POS) |
        /* DCD_DTE1 => I2C2_SDA */
-       SW_MUX_CTL_SIG3w(SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2),
+       ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG3_POS),
        SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3);
 }
 
@@ -79,7 +75,8 @@ void fmradio_i2c_enable(bool enable)
         imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */
         /* I2C2_SDA => MCU2_15 */ 
         imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2,
-            SW_MUX_CTL_SIG3w(SW_MUX_OUT_GPIO_DR | SW_MUX_IN_GPIO_PSR_ISR),
+            (SW_MUX_OUT_GPIO_DR |
+             SW_MUX_IN_GPIO_PSR_ISR) << SW_MUX_CTL_SIG3_POS,
             SW_MUX_CTL_SIG3);
         /* enable CLK32KMCU clock */
         mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN);
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c
index 446932b308..3d0ff977da 100644
--- a/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/gpio-gigabeat-s.c
@@ -22,6 +22,7 @@
  ****************************************************************************/
 #include "config.h"
 #include "system.h"
+#include "avic-imx31.h"
 #include "gpio-imx31.h"
 
 /* Gigabeat S definitions for static GPIO event registration */
@@ -44,7 +45,7 @@ static const struct gpio_event gpio1_events[] =
 /* Describes the events attached to GPIO1 port */
 const struct gpio_event_list gpio1_event_list =
 {
-    .ints_priority = 7,
+    .ints_priority = INT_PRIO_DEFAULT,
     .count         = ARRAYLEN(gpio1_events),
     .events        = gpio1_events,
 };
diff --git a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c
index 090182bed4..944f70eae3 100644
--- a/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/gpio-imx31.c
@@ -55,21 +55,21 @@ static struct gpio_module_descriptor
 #if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS)
     {
         .base    = (struct gpio_map *)GPIO1_BASE_ADDR,
-        .ints    = GPIO1,
+        .ints    = INT_GPIO1,
         .handler = GPIO1_HANDLER,
     },
 #endif
 #if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS)
     {
         .base    = (struct gpio_map *)GPIO2_BASE_ADDR,
-        .ints    = GPIO2,
+        .ints    = INT_GPIO2,
         .handler = GPIO2_HANDLER,
     },
 #endif
 #if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS)
     {
         .base    = (struct gpio_map *)GPIO3_BASE_ADDR,
-        .ints    = GPIO3,
+        .ints    = INT_GPIO3,
         .handler = GPIO3_HANDLER,
     },
 #endif
@@ -168,7 +168,7 @@ bool gpio_enable_event(enum gpio_event_ids id)
     if (imr == 0)
     {
         /* First enabled interrupt for this GPIO */
-        avic_enable_int(desc->ints, IRQ, desc->list->ints_priority,
+        avic_enable_int(desc->ints, INT_TYPE_IRQ, desc->list->ints_priority,
                         desc->handler);
     }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
index bf69afedb7..05d761c9ce 100644
--- a/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/i2c-imx31.c
@@ -57,7 +57,7 @@ static struct i2c_module_descriptor
     {
         .base    = (struct i2c_map *)I2C1_BASE_ADDR,
         .cg      = CG_I2C1,
-        .ints    = I2C1,
+        .ints    = INT_I2C1,
         .handler = I2C1_HANDLER,
     },
 #endif
@@ -65,7 +65,7 @@ static struct i2c_module_descriptor
     {
         .base    = (struct i2c_map *)I2C2_BASE_ADDR,
         .cg      = CG_I2C2,
-        .ints    = I2C2,
+        .ints    = INT_I2C2,
         .handler = I2C2_HANDLER,
     },
 #endif
@@ -73,7 +73,7 @@ static struct i2c_module_descriptor
     {
         .base    = (struct i2c_map *)I2C3_BASE_ADDR,
         .cg      = CG_I2C3,
-        .ints    = I2C3,
+        .ints    = INT_I2C3,
         .handler = I2C3_HANDLER,
     },
 #endif
@@ -286,11 +286,11 @@ void i2c_init(void)
     for (i = 0; i < I2C_NUM_I2C; i++)
     {
         struct i2c_module_descriptor *const desc = &i2c_descs[i];
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL);
+        ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT);
         mutex_init(&desc->m);
         wakeup_init(&desc->w);
         desc->base->i2cr = 0;
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF);
+        ccm_module_clock_gating(desc->cg, CGM_OFF);
     }
 }
 
@@ -305,8 +305,9 @@ void i2c_enable_node(struct i2c_node *node, bool enable)
         if (++desc->enable == 1)
         {
             /* First enable */
-            imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL);
-            avic_enable_int(desc->ints, IRQ, 7, desc->handler);
+            ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT);
+            avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                            desc->handler);
         }
     }
     else
@@ -317,7 +318,7 @@ void i2c_enable_node(struct i2c_node *node, bool enable)
             while (desc->base->i2sr & I2C_I2SR_IBB); /* Wait for STOP */
             desc->base->i2cr &= ~I2C_I2CR_IEN;
             avic_disable_int(desc->ints);
-            imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF);
+            ccm_module_clock_gating(desc->cg, CGM_OFF);
         }
     }
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
index a2f3d779eb..01e9b8b721 100644
--- a/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
@@ -38,11 +38,11 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
 
 void tick_start(unsigned int interval_in_ms)
 {
-    imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_ON_ALL); /* EPIT1 module
+    ccm_module_clock_gating(CG_EPIT1, CGM_ON_RUN_WAIT); /* EPIT1 module
                                                clock ON - before writing
                                                regs! */
     EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */
-    CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT1;     /* Clear wakeup mask */
+    CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT1;  /* Clear wakeup mask */
 
     /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1)
      * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz,
@@ -53,13 +53,14 @@ void tick_start(unsigned int interval_in_ms)
      * Compare interrupt enabled,
      * Count from load value */
     EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
-              EPITCR_PRESCALER(2640-1) | EPITCR_RLD | EPITCR_OCIEN |
+              (2640-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_OCIEN |
               EPITCR_ENMOD;
  
     EPITLR1 = interval_in_ms*25; /* Count down from interval */
     EPITCMPR1 = 0;               /* Event when counter reaches 0 */
     EPITSR1 = EPITSR_OCIF;       /* Clear any pending interrupt */
-    avic_enable_int(EPIT1, IRQ, 7, EPIT1_HANDLER);
+    avic_enable_int(INT_EPIT1, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                    EPIT1_HANDLER);
     EPITCR1 |= EPITCR_EN;        /* Enable the counter */
 }
 
@@ -73,9 +74,9 @@ void kernel_device_init(void)
 #ifdef BOOTLOADER
 void tick_stop(void)
 {
-    avic_disable_int(EPIT1);                /* Disable insterrupt */
+    avic_disable_int(INT_EPIT1);            /* Disable insterrupt */
     EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */
     EPITSR1 = EPITSR_OCIF;                  /* Clear pending */
-    imx31_clkctl_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */
+    ccm_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */
 }
 #endif
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
index deaa2a0dcd..00f196a512 100644
--- a/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-imx31.c
@@ -130,8 +130,8 @@ void pcm_play_dma_init(void)
     sdma_channel_init(DMA_PLAY_CH_NUM, &dma_play_cd, &dma_play_bd);
     sdma_channel_set_priority(DMA_PLAY_CH_NUM, DMA_PLAY_CH_PRIORITY);
 
-    imx31_clkctl_module_clock_gating(CG_SSI1, CGM_ON_ALL);
-    imx31_clkctl_module_clock_gating(CG_SSI2, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_SSI1, CGM_ON_RUN_WAIT);
+    ccm_module_clock_gating(CG_SSI2, CGM_ON_RUN_WAIT);
 
     /* Reset & disable SSIs */
     SSI_SCR1 &= ~SSI_SCR_SSIEN;
@@ -178,12 +178,12 @@ void pcm_play_dma_init(void)
                 SSI_STCR_TEFS | SSI_STCR_TFEN0;
 
     /* 16 bits per word, 2 words per frame */
-    SSI_STCCR2 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
-                 SSI_STRCCR_PMw(4-1);
+    SSI_STCCR2 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) |
+                 ((4-1) << SSI_STRCCR_PM_POS);
 
     /* Transmit low watermark */
     SSI_SFCSR2 = (SSI_SFCSR2 & ~SSI_SFCSR_TFWM0) |
-                 SSI_SFCSR_TFWM0w(8-SDMA_SSI_TXFIFO_WML);
+                 ((8-SDMA_SSI_TXFIFO_WML) << SSI_SFCSR_TFWM0_POS);
     SSI_STMSK2 = 0;
 
     /* SSI1 - provides MCLK to codec. Receives data from codec. */
@@ -201,7 +201,7 @@ void pcm_play_dma_init(void)
      * The hardware seems to force a divide by 4 even if all bits are
      * zero but comply by setting DIV2 and the others to zero.
      */
-    SSI_STCCR1 = SSI_STRCCR_DIV2 | SSI_STRCCR_PMw(1-1);
+    SSI_STCCR1 = SSI_STRCCR_DIV2 | ((1-1) << SSI_STRCCR_PM_POS);
 
     /* SSI1 - receive - asynchronous clocks */
     SSI_SCR1 = SSI_SCR_I2S_MODE_SLAVE;
@@ -210,12 +210,12 @@ void pcm_play_dma_init(void)
                 SSI_SRCR_REFS;
 
     /* 16 bits per word, 2 words per frame */
-    SSI_SRCCR1 = SSI_STRCCR_WL16 | SSI_STRCCR_DCw(2-1) |
-                 SSI_STRCCR_PMw(4-1);
+    SSI_SRCCR1 = SSI_STRCCR_WL16 | ((2-1) << SSI_STRCCR_DC_POS) |
+                 ((4-1) << SSI_STRCCR_PM_POS);
 
     /* Receive high watermark */
     SSI_SFCSR1 = (SSI_SFCSR1 & ~SSI_SFCSR_RFWM0) |
-                 SSI_SFCSR_RFWM0w(SDMA_SSI_RXFIFO_WML);
+                 (SDMA_SSI_RXFIFO_WML << SSI_SFCSR_RFWM0_POS);
     SSI_SRMSK1 = 0;
 
     /* Enable SSI1 (codec clock) */
@@ -252,7 +252,7 @@ static void play_start_pcm(void)
 static void play_stop_pcm(void)
 {
     /* Wait for FIFO to empty */
-    while (SSI_SFCSR_TFCNT0r(SSI_SFCSR2) > 0);
+    while (SSI_SFCSR_TFCNT0 & SSI_SFCSR2);
 
     /* Disable transmission */
     SSI_STCR2 &= ~SSI_STCR_TFEN0;
diff --git a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
index 98604d1eef..f905057372 100644
--- a/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/spi-imx31.c
@@ -58,7 +58,7 @@ static struct spi_module_descriptor
     {
         .base    = (struct cspi_map *)CSPI1_BASE_ADDR,
         .cg      = CG_CSPI1,
-        .ints    = CSPI1,
+        .ints    = INT_CSPI1,
         .handler = CSPI1_HANDLER,
     },
 #endif
@@ -66,7 +66,7 @@ static struct spi_module_descriptor
     {
         .base    = (struct cspi_map *)CSPI2_BASE_ADDR,
         .cg      = CG_CSPI2,
-        .ints    = CSPI2,
+        .ints    = INT_CSPI2,
         .handler = CSPI2_HANDLER,
     },
 #endif
@@ -74,7 +74,7 @@ static struct spi_module_descriptor
     {
         .base    = (struct cspi_map *)CSPI3_BASE_ADDR,
         .cg      = CG_CSPI3,
-        .ints    = CSPI3,
+        .ints    = INT_CSPI3,
         .handler = CSPI3_HANDLER,
     },
 #endif
@@ -267,12 +267,13 @@ void spi_enable_module(struct spi_node *node)
         struct cspi_map * const base = desc->base;
 
         /* Enable clock-gating register */
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL);
+        ccm_module_clock_gating(desc->cg, CGM_ON_RUN_WAIT);
         /* Reset */
         spi_reset(base);
         desc->last = NULL;
         /* Enable interrupt at controller level */
-        avic_enable_int(desc->ints, IRQ, 6, desc->handler);
+        avic_enable_int(desc->ints, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                        desc->handler);
     }
 
     mutex_unlock(&desc->m);
@@ -297,7 +298,7 @@ void spi_disable_module(struct spi_node *node)
         base->conreg &= ~CSPI_CONREG_EN;
 
         /* Disable interface clock */
-        imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF);
+        ccm_module_clock_gating(desc->cg, CGM_OFF);
     }
 
     mutex_unlock(&desc->m);
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
index b3f0fd66c9..c710c5b93c 100644
--- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c
@@ -49,7 +49,7 @@ unsigned int iim_prod_rev(void)
 static void iim_init(void)
 {
     /* Initialize the IC revision info (required by SDMA) */
-    imx31_clkctl_module_clock_gating(CG_IIM, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_IIM, CGM_ON_RUN_WAIT);
     product_rev = IIM_PREV;
     system_rev = IIM_SREV;
 }
@@ -59,13 +59,13 @@ static void iim_init(void)
 /* Initialize the watchdog timer */
 void watchdog_init(unsigned int half_seconds)
 {
-    uint16_t wcr = WDOG_WCR_WTw(half_seconds) | /* Timeout */
+    uint16_t wcr = ((half_seconds << WDOG_WCR_WT_POS) & WDOG_WCR_WT) |
                    WDOG_WCR_WOE |       /* WDOG output enabled */
                    WDOG_WCR_WDA |       /* WDOG assertion - no effect */
                    WDOG_WCR_SRS |       /* System reset - no effect */
                    WDOG_WCR_WRE;        /* Generate a WDOG signal */
 
-    imx31_clkctl_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT);
+    ccm_module_clock_gating(CG_WDOG, CGM_ON_RUN_WAIT);
 
     WDOG_WCR = wcr;
     WDOG_WSR = 0x5555;
@@ -86,8 +86,8 @@ void watchdog_service(void)
 /* Start the general-purpose timer (1MHz) */
 void gpt_start(void)
 {
-    imx31_clkctl_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
-    unsigned int ipg_mhz = imx31_clkctl_get_ipg_clk() / 1000000;
+    ccm_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
+    unsigned int ipg_mhz = ccm_get_ipg_clk() / 1000000;
 
     GPTCR &= ~GPTCR_EN; /* Disable counter */
     GPTCR |= GPTCR_SWR; /* Reset module */
@@ -123,7 +123,7 @@ void system_reboot(void)
 void system_exception_wait(void)
 {
     /* Called in many contexts so button reading may be a chore */
-    avic_disable_int(ALL);
+    avic_disable_int(INT_ALL);
     core_idle();
     while (1);
 }
@@ -174,8 +174,8 @@ void system_init(void)
 
     unsigned int i;
 
-    /* MCR WFI enables wait mode */
-    CLKCTL_CCMR &= ~(3 << 14);
+    /* MCR WFI enables wait mode (CCM_CCMR_LPM_WAIT_MODE = 0) */
+    imx31_regclr32(&CCM_CCMR, CCM_CCMR_LPM);
 
     iim_init();
 
@@ -189,7 +189,7 @@ void system_init(void)
     imx31_regclr32(&UCR1_5, EUARTUCR1_UARTEN);
 
     for (i = 0; i < ARRAYLEN(disable_clocks); i++)
-        imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF);
+        ccm_module_clock_gating(disable_clocks[i], CGM_OFF);
 
     avic_init();
     gpt_start();
@@ -242,7 +242,7 @@ void __attribute__((naked)) imx31_regclr32(volatile uint32_t *reg_p,
 void system_prepare_fw_start(void)
 {
     disable_interrupt(IRQ_FIQ_STATUS);
-    avic_disable_int(ALL);
+    avic_disable_int(INT_ALL);
     mc13783_close();
     tick_stop();
 }
diff --git a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
index 531baf3cc5..c4734a543b 100644
--- a/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/timer-imx31.c
@@ -35,11 +35,11 @@ static void __attribute__((interrupt("IRQ"))) EPIT2_HANDLER(void)
 static void stop_timer(bool clock_off)
 {
     /* Ensure clock gating on (before touching any module registers) */
-    imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_EPIT2, CGM_ON_RUN_WAIT);
     /* Disable insterrupt */
-    avic_disable_int(EPIT2);
+    avic_disable_int(INT_EPIT2);
     /* Clear wakeup mask */
-    CLKCTL_WIMR0 &= ~WIM_IPI_INT_EPIT2;
+    CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT2;
     /* Disable counter */
     EPITCR2 &= ~(EPITCR_OCIEN | EPITCR_EN);
     /* Clear pending */
@@ -48,7 +48,7 @@ static void stop_timer(bool clock_off)
     if (clock_off)
     {
         /* Final stop, not reset; don't clock module any longer */
-        imx31_clkctl_module_clock_gating(CG_EPIT2, CGM_OFF);
+        ccm_module_clock_gating(CG_EPIT2, CGM_OFF);
     }
 }
 
@@ -77,7 +77,7 @@ bool _timer_set(long cycles, bool start)
      * Reload from modulus register,
      * Count from load value */
     EPITCR2 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
-              EPITCR_PRESCALER(1-1) | EPITCR_RLD | EPITCR_ENMOD;
+              (1-1) << EPITCR_PRESCALER_POS | EPITCR_RLD | EPITCR_ENMOD;
     EPITLR2 = cycles;
     /* Event when counter reaches 0 */
     EPITCMPR2 = 0;
@@ -95,7 +95,8 @@ bool _timer_register(void)
 
     /* Enable interrupt */
     EPITCR2 |= EPITCR_OCIEN;
-    avic_enable_int(EPIT2, IRQ, 8, EPIT2_HANDLER);
+    avic_enable_int(INT_EPIT2, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                    EPIT2_HANDLER);
     /* Start timer */
     EPITCR2 |= EPITCR_EN;
 
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
index 8682cff7c7..2011d0c633 100644
--- a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
@@ -89,7 +89,7 @@ void usb_enable(bool on)
 {
     /* Module clock should be on since since this could be called with
      * OFF initially and writing module registers would hardlock otherwise. */
-    imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_ON_ALL);
+    ccm_module_clock_gating(CG_USBOTG, CGM_ON_RUN_WAIT);
     enable_transceiver(true);
 
     if (on)
@@ -100,7 +100,7 @@ void usb_enable(bool on)
     {
         usb_core_exit();
         enable_transceiver(false);
-        imx31_clkctl_module_clock_gating(CG_USBOTG, CGM_OFF);
+        ccm_module_clock_gating(CG_USBOTG, CGM_OFF);
     }
 }
 
@@ -117,9 +117,14 @@ static void __attribute__((interrupt("IRQ"))) USB_OTG_HANDLER(void)
 void usb_drv_int_enable(bool enable)
 {
     if (enable)
-        avic_enable_int(USB_OTG, IRQ, 7, USB_OTG_HANDLER);
-    else    
-        avic_disable_int(USB_OTG);
+    {
+        avic_enable_int(INT_USB_OTG, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
+                        USB_OTG_HANDLER);
+    }
+    else
+    {
+        avic_disable_int(INT_USB_OTG);
+    }
 }
 
 /* Called during the bus reset interrupt when in detect mode */
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
index 542f6eb633..cf9331144a 100644
--- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-imx31.c
@@ -52,11 +52,13 @@ void audiohw_init(void)
      * WM Codec post divider (MCLKDIV=1.5):
      * INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK
      */
-    imx31_regmod32(&CLKCTL_PDR1,
-                   PDR1_SSI1_PODFw(5-1) | PDR1_SSI2_PODFw(64-1) |
-                   PDR1_SSI1_PRE_PODFw(1-1) | PDR1_SSI2_PRE_PODFw(8-1),
-                   PDR1_SSI1_PODF | PDR1_SSI2_PODF |
-                   PDR1_SSI1_PRE_PODF | PDR1_SSI2_PRE_PODF);
+    imx31_regmod32(&CCM_PDR1,
+                   (1-1) << CCM_PDR1_SSI1_PRE_PODF_POS |
+                   (5-1) << CCM_PDR1_SSI1_PODF_POS |
+                   (8-1) << CCM_PDR1_SSI2_PRE_PODF_POS,
+                   (64-1) << CCM_PDR1_SSI2_PODF_POS |
+                   CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF |
+                   CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF);
 
     i2c_enable_node(&wm8978_i2c_node, true);
 
diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c
index 4c5674afb9..97af419077 100644
--- a/firmware/target/arm/imx31/sdma-imx31.c
+++ b/firmware/target/arm/imx31/sdma-imx31.c
@@ -502,10 +502,11 @@ static bool setup_channel(struct channel_control_block *ccb_p)
 /** Public routines **/
 void sdma_init(void)
 {
-    imx31_clkctl_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT);
     int i;
     unsigned long acr;
 
+    ccm_module_clock_gating(CG_SDMA, CGM_ON_RUN_WAIT);
+
     /* Reset the controller */
     SDMA_RESET |= SDMA_RESET_RESET;
     while (SDMA_RESET & SDMA_RESET_RESET);
@@ -532,11 +533,11 @@ void sdma_init(void)
     /* 32-word channel contexts, use default bootscript address */
     SDMA_CHN0ADDR = SDMA_CHN0ADDR_SMSZ | 0x0050;
 
-    avic_enable_int(SDMA, IRQ, 8, SDMA_HANDLER);
+    avic_enable_int(INT_SDMA, INT_TYPE_IRQ, INT_PRIO_DEFAULT+1, SDMA_HANDLER);
 
-    /* SDMA core must run at the proper frequency based upon the AHB/IPG ratio */
-    acr = (imx31_clkctl_get_ahb_clk() / imx31_clkctl_get_ipg_clk()) < 2 ?
-          SDMA_CONFIG_ACR : 0;
+    /* SDMA core must run at the proper frequency based upon the AHB/IPG
+     * ratio */
+    acr = (ccm_get_ahb_clk() / ccm_get_ipg_clk()) < 2 ? SDMA_CONFIG_ACR : 0;
 
     /* No dsp, no debug
      * Static context switching - TLSbo86520L SW Workaround for SDMA Chnl0