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author | Michael Sevakis <jethead71@rockbox.org> | 2009-03-22 01:50:48 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2009-03-22 01:50:48 +0000 |
commit | b7f7655dc2ae979fee8b01ed894224e5c2f7c719 (patch) | |
tree | 6540a83276514c2ea27b9c633ac9872588e126be /firmware/target/arm/imx31/gigabeat-s/avic-imx31.c | |
parent | 6a76ebbab10594f425edbd26e1fa35b0e37a61e5 (diff) | |
download | rockbox-b7f7655dc2ae979fee8b01ed894224e5c2f7c719.tar.gz rockbox-b7f7655dc2ae979fee8b01ed894224e5c2f7c719.zip |
imx31/mc13783: Do some housekeeping with register macros, function names and other defines. No functional changes (except to alter a couple int priorities).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20442 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/avic-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/avic-imx31.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c index a135889e6e..4ba7da4be0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.c | |||
@@ -59,7 +59,7 @@ void UIE_VECTOR(void) | |||
59 | ); | 59 | ); |
60 | 60 | ||
61 | offset = mode == 0x11 ? | 61 | offset = mode == 0x11 ? |
62 | (int32_t)FIVECSR : ((int32_t)NIVECSR >> 16); | 62 | (int32_t)AVIC_FIVECSR : ((int32_t)AVIC_NIVECSR >> 16); |
63 | 63 | ||
64 | panicf("Unhandled %s %d: %s", | 64 | panicf("Unhandled %s %d: %s", |
65 | mode == 0x11 ? "FIQ" : "IRQ", offset, | 65 | mode == 0x11 ? "FIQ" : "IRQ", offset, |
@@ -69,7 +69,7 @@ void UIE_VECTOR(void) | |||
69 | /* We use the AVIC */ | 69 | /* We use the AVIC */ |
70 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | 70 | void __attribute__((interrupt("IRQ"))) irq_handler(void) |
71 | { | 71 | { |
72 | const int offset = (int32_t)NIVECSR >> 16; | 72 | const int offset = (int32_t)AVIC_NIVECSR >> 16; |
73 | 73 | ||
74 | if (offset == -1) | 74 | if (offset == -1) |
75 | { | 75 | { |
@@ -105,20 +105,20 @@ void avic_init(void) | |||
105 | int i; | 105 | int i; |
106 | 106 | ||
107 | /* Disable all interrupts and set to unhandled */ | 107 | /* Disable all interrupts and set to unhandled */ |
108 | avic_disable_int(ALL); | 108 | avic_disable_int(INT_ALL); |
109 | 109 | ||
110 | /* Reset AVIC control */ | 110 | /* Reset AVIC control */ |
111 | avic->intcntl = 0; | 111 | avic->intcntl = 0; |
112 | 112 | ||
113 | /* Init all interrupts to type IRQ */ | 113 | /* Init all interrupts to type IRQ */ |
114 | avic_set_int_type(ALL, IRQ); | 114 | avic_set_int_type(INT_ALL, INT_TYPE_IRQ); |
115 | 115 | ||
116 | /* Set all normal to lowest priority */ | 116 | /* Set all normal to lowest priority */ |
117 | for (i = 0; i < 8; i++) | 117 | for (i = 0; i < 8; i++) |
118 | avic->nipriority[i] = 0; | 118 | avic->nipriority[i] = 0; |
119 | 119 | ||
120 | /* Set NM bit to enable VIC */ | 120 | /* Set NM bit to enable VIC */ |
121 | avic->intcntl |= INTCNTL_NM; | 121 | avic->intcntl |= AVIC_INTCNTL_NM; |
122 | 122 | ||
123 | /* Enable VE bit in CP15 Control reg to enable VIC */ | 123 | /* Enable VE bit in CP15 Control reg to enable VIC */ |
124 | asm volatile ( | 124 | asm volatile ( |
@@ -147,7 +147,7 @@ void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, | |||
147 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 147 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; |
148 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 148 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
149 | 149 | ||
150 | if (ints != ALL) /* No mass-enable allowed */ | 150 | if (ints != INT_ALL) /* No mass-enable allowed */ |
151 | { | 151 | { |
152 | avic_set_int_type(ints, intstype); | 152 | avic_set_int_type(ints, intstype); |
153 | avic->vector[ints] = (long)handler; | 153 | avic->vector[ints] = (long)handler; |
@@ -163,7 +163,7 @@ void avic_disable_int(enum IMX31_INT_LIST ints) | |||
163 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; | 163 | struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR; |
164 | uint32_t i; | 164 | uint32_t i; |
165 | 165 | ||
166 | if (ints == ALL) | 166 | if (ints == INT_ALL) |
167 | { | 167 | { |
168 | for (i = 0; i < 64; i++) | 168 | for (i = 0; i < 64; i++) |
169 | { | 169 | { |
@@ -185,7 +185,7 @@ static void set_int_type(int i, enum INT_TYPE intstype) | |||
185 | volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)]; | 185 | volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)]; |
186 | uint32_t val = 1L << (i & 0x1f); | 186 | uint32_t val = 1L << (i & 0x1f); |
187 | 187 | ||
188 | if (intstype == IRQ) | 188 | if (intstype == INT_TYPE_IRQ) |
189 | val = *reg & ~val; | 189 | val = *reg & ~val; |
190 | else | 190 | else |
191 | val = *reg | val; | 191 | val = *reg | val; |
@@ -197,7 +197,7 @@ void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype) | |||
197 | { | 197 | { |
198 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | 198 | int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); |
199 | 199 | ||
200 | if (ints == ALL) | 200 | if (ints == INT_ALL) |
201 | { | 201 | { |
202 | int i; | 202 | int i; |
203 | for (i = 0; i < 64; i++) | 203 | for (i = 0; i < 64; i++) |