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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h | 312 |
1 files changed, 312 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h new file mode 100644 index 0000000000..ed2bf3270e --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-rtc.h | |||
@@ -0,0 +1,312 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__RTC__H__ | ||
24 | #define __HEADERGEN__STMP3700__RTC__H__ | ||
25 | |||
26 | #define REGS_RTC_BASE (0x8005c000) | ||
27 | |||
28 | #define REGS_RTC_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_RTC_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_RTC_CTRL (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x0)) | ||
36 | #define HW_RTC_CTRL_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x4)) | ||
37 | #define HW_RTC_CTRL_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0x8)) | ||
38 | #define HW_RTC_CTRL_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x0 + 0xc)) | ||
39 | #define BP_RTC_CTRL_SFTRST 31 | ||
40 | #define BM_RTC_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_RTC_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_RTC_CTRL_CLKGATE 30 | ||
43 | #define BM_RTC_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_RTC_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_RTC_CTRL_SUPPRESS_COPY2ANALOG 6 | ||
46 | #define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x40 | ||
47 | #define BF_RTC_CTRL_SUPPRESS_COPY2ANALOG(v) (((v) << 6) & 0x40) | ||
48 | #define BP_RTC_CTRL_FORCE_UPDATE 5 | ||
49 | #define BM_RTC_CTRL_FORCE_UPDATE 0x20 | ||
50 | #define BF_RTC_CTRL_FORCE_UPDATE(v) (((v) << 5) & 0x20) | ||
51 | #define BP_RTC_CTRL_WATCHDOGEN 4 | ||
52 | #define BM_RTC_CTRL_WATCHDOGEN 0x10 | ||
53 | #define BF_RTC_CTRL_WATCHDOGEN(v) (((v) << 4) & 0x10) | ||
54 | #define BP_RTC_CTRL_ONEMSEC_IRQ 3 | ||
55 | #define BM_RTC_CTRL_ONEMSEC_IRQ 0x8 | ||
56 | #define BF_RTC_CTRL_ONEMSEC_IRQ(v) (((v) << 3) & 0x8) | ||
57 | #define BP_RTC_CTRL_ALARM_IRQ 2 | ||
58 | #define BM_RTC_CTRL_ALARM_IRQ 0x4 | ||
59 | #define BF_RTC_CTRL_ALARM_IRQ(v) (((v) << 2) & 0x4) | ||
60 | #define BP_RTC_CTRL_ONEMSEC_IRQ_EN 1 | ||
61 | #define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x2 | ||
62 | #define BF_RTC_CTRL_ONEMSEC_IRQ_EN(v) (((v) << 1) & 0x2) | ||
63 | #define BP_RTC_CTRL_ALARM_IRQ_EN 0 | ||
64 | #define BM_RTC_CTRL_ALARM_IRQ_EN 0x1 | ||
65 | #define BF_RTC_CTRL_ALARM_IRQ_EN(v) (((v) << 0) & 0x1) | ||
66 | |||
67 | /** | ||
68 | * Register: HW_RTC_STAT | ||
69 | * Address: 0x10 | ||
70 | * SCT: no | ||
71 | */ | ||
72 | #define HW_RTC_STAT (*(volatile unsigned long *)(REGS_RTC_BASE + 0x10)) | ||
73 | #define BP_RTC_STAT_RTC_PRESENT 31 | ||
74 | #define BM_RTC_STAT_RTC_PRESENT 0x80000000 | ||
75 | #define BF_RTC_STAT_RTC_PRESENT(v) (((v) << 31) & 0x80000000) | ||
76 | #define BP_RTC_STAT_ALARM_PRESENT 30 | ||
77 | #define BM_RTC_STAT_ALARM_PRESENT 0x40000000 | ||
78 | #define BF_RTC_STAT_ALARM_PRESENT(v) (((v) << 30) & 0x40000000) | ||
79 | #define BP_RTC_STAT_WATCHDOG_PRESENT 29 | ||
80 | #define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 | ||
81 | #define BF_RTC_STAT_WATCHDOG_PRESENT(v) (((v) << 29) & 0x20000000) | ||
82 | #define BP_RTC_STAT_XTAL32000_PRESENT 28 | ||
83 | #define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 | ||
84 | #define BF_RTC_STAT_XTAL32000_PRESENT(v) (((v) << 28) & 0x10000000) | ||
85 | #define BP_RTC_STAT_XTAL32768_PRESENT 27 | ||
86 | #define BM_RTC_STAT_XTAL32768_PRESENT 0x8000000 | ||
87 | #define BF_RTC_STAT_XTAL32768_PRESENT(v) (((v) << 27) & 0x8000000) | ||
88 | #define BP_RTC_STAT_STALE_REGS 16 | ||
89 | #define BM_RTC_STAT_STALE_REGS 0xff0000 | ||
90 | #define BF_RTC_STAT_STALE_REGS(v) (((v) << 16) & 0xff0000) | ||
91 | #define BP_RTC_STAT_NEW_REGS 8 | ||
92 | #define BM_RTC_STAT_NEW_REGS 0xff00 | ||
93 | #define BF_RTC_STAT_NEW_REGS(v) (((v) << 8) & 0xff00) | ||
94 | |||
95 | /** | ||
96 | * Register: HW_RTC_MILLISECONDS | ||
97 | * Address: 0x20 | ||
98 | * SCT: yes | ||
99 | */ | ||
100 | #define HW_RTC_MILLISECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x0)) | ||
101 | #define HW_RTC_MILLISECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x4)) | ||
102 | #define HW_RTC_MILLISECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0x8)) | ||
103 | #define HW_RTC_MILLISECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x20 + 0xc)) | ||
104 | #define BP_RTC_MILLISECONDS_COUNT 0 | ||
105 | #define BM_RTC_MILLISECONDS_COUNT 0xffffffff | ||
106 | #define BF_RTC_MILLISECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
107 | |||
108 | /** | ||
109 | * Register: HW_RTC_SECONDS | ||
110 | * Address: 0x30 | ||
111 | * SCT: yes | ||
112 | */ | ||
113 | #define HW_RTC_SECONDS (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x0)) | ||
114 | #define HW_RTC_SECONDS_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x4)) | ||
115 | #define HW_RTC_SECONDS_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0x8)) | ||
116 | #define HW_RTC_SECONDS_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x30 + 0xc)) | ||
117 | #define BP_RTC_SECONDS_COUNT 0 | ||
118 | #define BM_RTC_SECONDS_COUNT 0xffffffff | ||
119 | #define BF_RTC_SECONDS_COUNT(v) (((v) << 0) & 0xffffffff) | ||
120 | |||
121 | /** | ||
122 | * Register: HW_RTC_ALARM | ||
123 | * Address: 0x40 | ||
124 | * SCT: yes | ||
125 | */ | ||
126 | #define HW_RTC_ALARM (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x0)) | ||
127 | #define HW_RTC_ALARM_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x4)) | ||
128 | #define HW_RTC_ALARM_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0x8)) | ||
129 | #define HW_RTC_ALARM_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x40 + 0xc)) | ||
130 | #define BP_RTC_ALARM_VALUE 0 | ||
131 | #define BM_RTC_ALARM_VALUE 0xffffffff | ||
132 | #define BF_RTC_ALARM_VALUE(v) (((v) << 0) & 0xffffffff) | ||
133 | |||
134 | /** | ||
135 | * Register: HW_RTC_WATCHDOG | ||
136 | * Address: 0x50 | ||
137 | * SCT: yes | ||
138 | */ | ||
139 | #define HW_RTC_WATCHDOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x0)) | ||
140 | #define HW_RTC_WATCHDOG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x4)) | ||
141 | #define HW_RTC_WATCHDOG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0x8)) | ||
142 | #define HW_RTC_WATCHDOG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x50 + 0xc)) | ||
143 | #define BP_RTC_WATCHDOG_COUNT 0 | ||
144 | #define BM_RTC_WATCHDOG_COUNT 0xffffffff | ||
145 | #define BF_RTC_WATCHDOG_COUNT(v) (((v) << 0) & 0xffffffff) | ||
146 | |||
147 | /** | ||
148 | * Register: HW_RTC_PERSISTENT0 | ||
149 | * Address: 0x60 | ||
150 | * SCT: yes | ||
151 | */ | ||
152 | #define HW_RTC_PERSISTENT0 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x0)) | ||
153 | #define HW_RTC_PERSISTENT0_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x4)) | ||
154 | #define HW_RTC_PERSISTENT0_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0x8)) | ||
155 | #define HW_RTC_PERSISTENT0_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x60 + 0xc)) | ||
156 | #define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 | ||
157 | #define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xfffc0000 | ||
158 | #define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) (((v) << 18) & 0xfffc0000) | ||
159 | #define BP_RTC_PERSISTENT0_AUTO_RESTART 17 | ||
160 | #define BM_RTC_PERSISTENT0_AUTO_RESTART 0x20000 | ||
161 | #define BF_RTC_PERSISTENT0_AUTO_RESTART(v) (((v) << 17) & 0x20000) | ||
162 | #define BP_RTC_PERSISTENT0_DISABLE_PSWITCH 16 | ||
163 | #define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x10000 | ||
164 | #define BF_RTC_PERSISTENT0_DISABLE_PSWITCH(v) (((v) << 16) & 0x10000) | ||
165 | #define BP_RTC_PERSISTENT0_LOWERBIAS 14 | ||
166 | #define BM_RTC_PERSISTENT0_LOWERBIAS 0xc000 | ||
167 | #define BF_RTC_PERSISTENT0_LOWERBIAS(v) (((v) << 14) & 0xc000) | ||
168 | #define BP_RTC_PERSISTENT0_DISABLE_XTALOK 13 | ||
169 | #define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x2000 | ||
170 | #define BF_RTC_PERSISTENT0_DISABLE_XTALOK(v) (((v) << 13) & 0x2000) | ||
171 | #define BP_RTC_PERSISTENT0_MSEC_RES 8 | ||
172 | #define BM_RTC_PERSISTENT0_MSEC_RES 0x1f00 | ||
173 | #define BF_RTC_PERSISTENT0_MSEC_RES(v) (((v) << 8) & 0x1f00) | ||
174 | #define BP_RTC_PERSISTENT0_ALARM_WAKE 7 | ||
175 | #define BM_RTC_PERSISTENT0_ALARM_WAKE 0x80 | ||
176 | #define BF_RTC_PERSISTENT0_ALARM_WAKE(v) (((v) << 7) & 0x80) | ||
177 | #define BP_RTC_PERSISTENT0_XTAL32_FREQ 6 | ||
178 | #define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x40 | ||
179 | #define BF_RTC_PERSISTENT0_XTAL32_FREQ(v) (((v) << 6) & 0x40) | ||
180 | #define BP_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 5 | ||
181 | #define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x20 | ||
182 | #define BF_RTC_PERSISTENT0_XTAL32KHZ_PWRUP(v) (((v) << 5) & 0x20) | ||
183 | #define BP_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 4 | ||
184 | #define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x10 | ||
185 | #define BF_RTC_PERSISTENT0_XTAL24MHZ_PWRUP(v) (((v) << 4) & 0x10) | ||
186 | #define BP_RTC_PERSISTENT0_LCK_SECS 3 | ||
187 | #define BM_RTC_PERSISTENT0_LCK_SECS 0x8 | ||
188 | #define BF_RTC_PERSISTENT0_LCK_SECS(v) (((v) << 3) & 0x8) | ||
189 | #define BP_RTC_PERSISTENT0_ALARM_EN 2 | ||
190 | #define BM_RTC_PERSISTENT0_ALARM_EN 0x4 | ||
191 | #define BF_RTC_PERSISTENT0_ALARM_EN(v) (((v) << 2) & 0x4) | ||
192 | #define BP_RTC_PERSISTENT0_ALARM_WAKE_EN 1 | ||
193 | #define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x2 | ||
194 | #define BF_RTC_PERSISTENT0_ALARM_WAKE_EN(v) (((v) << 1) & 0x2) | ||
195 | #define BP_RTC_PERSISTENT0_CLOCKSOURCE 0 | ||
196 | #define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x1 | ||
197 | #define BF_RTC_PERSISTENT0_CLOCKSOURCE(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_RTC_PERSISTENT1 | ||
201 | * Address: 0x70 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_RTC_PERSISTENT1 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x0)) | ||
205 | #define HW_RTC_PERSISTENT1_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x4)) | ||
206 | #define HW_RTC_PERSISTENT1_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0x8)) | ||
207 | #define HW_RTC_PERSISTENT1_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x70 + 0xc)) | ||
208 | #define BP_RTC_PERSISTENT1_GENERAL 0 | ||
209 | #define BM_RTC_PERSISTENT1_GENERAL 0xffffffff | ||
210 | #define BV_RTC_PERSISTENT1_GENERAL__SPARE3 0x4000 | ||
211 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_BOOT 0x2000 | ||
212 | #define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 | ||
213 | #define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x800 | ||
214 | #define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x400 | ||
215 | #define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x200 | ||
216 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x100 | ||
217 | #define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x80 | ||
218 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_HI 0x40 | ||
219 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_CS_LO 0x20 | ||
220 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_3 0x10 | ||
221 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_2 0x8 | ||
222 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_1 0x4 | ||
223 | #define BV_RTC_PERSISTENT1_GENERAL__SDRAM_NDX_0 0x2 | ||
224 | #define BV_RTC_PERSISTENT1_GENERAL__ETM_ENABLE 0x1 | ||
225 | #define BF_RTC_PERSISTENT1_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
226 | #define BF_RTC_PERSISTENT1_GENERAL_V(v) ((BV_RTC_PERSISTENT1_GENERAL__##v << 0) & 0xffffffff) | ||
227 | |||
228 | /** | ||
229 | * Register: HW_RTC_PERSISTENT2 | ||
230 | * Address: 0x80 | ||
231 | * SCT: yes | ||
232 | */ | ||
233 | #define HW_RTC_PERSISTENT2 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x0)) | ||
234 | #define HW_RTC_PERSISTENT2_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x4)) | ||
235 | #define HW_RTC_PERSISTENT2_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0x8)) | ||
236 | #define HW_RTC_PERSISTENT2_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x80 + 0xc)) | ||
237 | #define BP_RTC_PERSISTENT2_GENERAL 0 | ||
238 | #define BM_RTC_PERSISTENT2_GENERAL 0xffffffff | ||
239 | #define BF_RTC_PERSISTENT2_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
240 | |||
241 | /** | ||
242 | * Register: HW_RTC_PERSISTENT3 | ||
243 | * Address: 0x90 | ||
244 | * SCT: yes | ||
245 | */ | ||
246 | #define HW_RTC_PERSISTENT3 (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x0)) | ||
247 | #define HW_RTC_PERSISTENT3_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x4)) | ||
248 | #define HW_RTC_PERSISTENT3_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0x8)) | ||
249 | #define HW_RTC_PERSISTENT3_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0x90 + 0xc)) | ||
250 | #define BP_RTC_PERSISTENT3_GENERAL 0 | ||
251 | #define BM_RTC_PERSISTENT3_GENERAL 0xffffffff | ||
252 | #define BF_RTC_PERSISTENT3_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
253 | |||
254 | /** | ||
255 | * Register: HW_RTC_PERSISTENT4 | ||
256 | * Address: 0xa0 | ||
257 | * SCT: yes | ||
258 | */ | ||
259 | #define HW_RTC_PERSISTENT4 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x0)) | ||
260 | #define HW_RTC_PERSISTENT4_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x4)) | ||
261 | #define HW_RTC_PERSISTENT4_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0x8)) | ||
262 | #define HW_RTC_PERSISTENT4_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xa0 + 0xc)) | ||
263 | #define BP_RTC_PERSISTENT4_GENERAL 0 | ||
264 | #define BM_RTC_PERSISTENT4_GENERAL 0xffffffff | ||
265 | #define BF_RTC_PERSISTENT4_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
266 | |||
267 | /** | ||
268 | * Register: HW_RTC_PERSISTENT5 | ||
269 | * Address: 0xb0 | ||
270 | * SCT: yes | ||
271 | */ | ||
272 | #define HW_RTC_PERSISTENT5 (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x0)) | ||
273 | #define HW_RTC_PERSISTENT5_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x4)) | ||
274 | #define HW_RTC_PERSISTENT5_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0x8)) | ||
275 | #define HW_RTC_PERSISTENT5_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xb0 + 0xc)) | ||
276 | #define BP_RTC_PERSISTENT5_GENERAL 0 | ||
277 | #define BM_RTC_PERSISTENT5_GENERAL 0xffffffff | ||
278 | #define BF_RTC_PERSISTENT5_GENERAL(v) (((v) << 0) & 0xffffffff) | ||
279 | |||
280 | /** | ||
281 | * Register: HW_RTC_DEBUG | ||
282 | * Address: 0xc0 | ||
283 | * SCT: yes | ||
284 | */ | ||
285 | #define HW_RTC_DEBUG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x0)) | ||
286 | #define HW_RTC_DEBUG_SET (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x4)) | ||
287 | #define HW_RTC_DEBUG_CLR (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0x8)) | ||
288 | #define HW_RTC_DEBUG_TOG (*(volatile unsigned long *)(REGS_RTC_BASE + 0xc0 + 0xc)) | ||
289 | #define BP_RTC_DEBUG_WATCHDOG_RESET_MASK 1 | ||
290 | #define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x2 | ||
291 | #define BF_RTC_DEBUG_WATCHDOG_RESET_MASK(v) (((v) << 1) & 0x2) | ||
292 | #define BP_RTC_DEBUG_WATCHDOG_RESET 0 | ||
293 | #define BM_RTC_DEBUG_WATCHDOG_RESET 0x1 | ||
294 | #define BF_RTC_DEBUG_WATCHDOG_RESET(v) (((v) << 0) & 0x1) | ||
295 | |||
296 | /** | ||
297 | * Register: HW_RTC_VERSION | ||
298 | * Address: 0xd0 | ||
299 | * SCT: no | ||
300 | */ | ||
301 | #define HW_RTC_VERSION (*(volatile unsigned long *)(REGS_RTC_BASE + 0xd0)) | ||
302 | #define BP_RTC_VERSION_MAJOR 24 | ||
303 | #define BM_RTC_VERSION_MAJOR 0xff000000 | ||
304 | #define BF_RTC_VERSION_MAJOR(v) (((v) << 24) & 0xff000000) | ||
305 | #define BP_RTC_VERSION_MINOR 16 | ||
306 | #define BM_RTC_VERSION_MINOR 0xff0000 | ||
307 | #define BF_RTC_VERSION_MINOR(v) (((v) << 16) & 0xff0000) | ||
308 | #define BP_RTC_VERSION_STEP 0 | ||
309 | #define BM_RTC_VERSION_STEP 0xffff | ||
310 | #define BF_RTC_VERSION_STEP(v) (((v) << 0) & 0xffff) | ||
311 | |||
312 | #endif /* __HEADERGEN__STMP3700__RTC__H__ */ | ||