imx233: generate register headers for stmp3600, stmp3700 and imx233

Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934

1 files changed, 451 insertions, 0 deletions

diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h
new file mode 100644
index 0000000000..c528c81fee
--- /dev/null
+++ b/firmware/target/arm/imx233/regs/stmp3700/regs-lcdif.h
@@ -0,0 +1,451 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * This file was automatically generated by headergen, DO NOT EDIT it.
+ * headergen version: 2.1.7
+ * XML versions: stmp3700:3.2.0
+ *
+ * Copyright (C) 2013 by Amaury Pouly
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __HEADERGEN__STMP3700__LCDIF__H__
+#define __HEADERGEN__STMP3700__LCDIF__H__
+
+#define REGS_LCDIF_BASE (0x80030000)
+
+#define REGS_LCDIF_VERSION "3.2.0"
+
+/**
+ * Register: HW_LCDIF_CTRL
+ * Address: 0
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL                                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x0))
+#define HW_LCDIF_CTRL_SET                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x4))
+#define HW_LCDIF_CTRL_CLR                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0x8))
+#define HW_LCDIF_CTRL_TOG                                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x0 + 0xc))
+#define BP_LCDIF_CTRL_SFTRST                                31
+#define BM_LCDIF_CTRL_SFTRST                                0x80000000
+#define BF_LCDIF_CTRL_SFTRST(v)                             (((v) << 31) & 0x80000000)
+#define BP_LCDIF_CTRL_CLKGATE                               30
+#define BM_LCDIF_CTRL_CLKGATE                               0x40000000
+#define BF_LCDIF_CTRL_CLKGATE(v)                            (((v) << 30) & 0x40000000)
+#define BP_LCDIF_CTRL_READ_WRITEB                           29
+#define BM_LCDIF_CTRL_READ_WRITEB                           0x20000000
+#define BF_LCDIF_CTRL_READ_WRITEB(v)                        (((v) << 29) & 0x20000000)
+#define BP_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   28
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE                   0x10000000
+#define BF_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(v)                (((v) << 28) & 0x10000000)
+#define BP_LCDIF_CTRL_DATA_SHIFT_DIR                        27
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR                        0x8000000
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT     0x0
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT    0x1
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR(v)                     (((v) << 27) & 0x8000000)
+#define BF_LCDIF_CTRL_DATA_SHIFT_DIR_V(v)                   ((BV_LCDIF_CTRL_DATA_SHIFT_DIR__##v << 27) & 0x8000000)
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS                        25
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS                        0x6000000
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v)                     (((v) << 25) & 0x6000000)
+#define BP_LCDIF_CTRL_DVI_MODE                              24
+#define BM_LCDIF_CTRL_DVI_MODE                              0x1000000
+#define BF_LCDIF_CTRL_DVI_MODE(v)                           (((v) << 24) & 0x1000000)
+#define BP_LCDIF_CTRL_BYPASS_COUNT                          23
+#define BM_LCDIF_CTRL_BYPASS_COUNT                          0x800000
+#define BF_LCDIF_CTRL_BYPASS_COUNT(v)                       (((v) << 23) & 0x800000)
+#define BP_LCDIF_CTRL_DATA_SWIZZLE                          21
+#define BM_LCDIF_CTRL_DATA_SWIZZLE                          0x600000
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__NO_SWAP                 0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__LITTLE_ENDIAN           0x0
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__BIG_ENDIAN_SWAP         0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__SWAP_ALL_BYTES          0x1
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_SWAP                0x2
+#define BV_LCDIF_CTRL_DATA_SWIZZLE__HWD_BYTE_SWAP           0x3
+#define BF_LCDIF_CTRL_DATA_SWIZZLE(v)                       (((v) << 21) & 0x600000)
+#define BF_LCDIF_CTRL_DATA_SWIZZLE_V(v)                     ((BV_LCDIF_CTRL_DATA_SWIZZLE__##v << 21) & 0x600000)
+#define BP_LCDIF_CTRL_VSYNC_MODE                            20
+#define BM_LCDIF_CTRL_VSYNC_MODE                            0x100000
+#define BF_LCDIF_CTRL_VSYNC_MODE(v)                         (((v) << 20) & 0x100000)
+#define BP_LCDIF_CTRL_DOTCLK_MODE                           19
+#define BM_LCDIF_CTRL_DOTCLK_MODE                           0x80000
+#define BF_LCDIF_CTRL_DOTCLK_MODE(v)                        (((v) << 19) & 0x80000)
+#define BP_LCDIF_CTRL_DATA_SELECT                           18
+#define BM_LCDIF_CTRL_DATA_SELECT                           0x40000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE                 0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE                0x1
+#define BF_LCDIF_CTRL_DATA_SELECT(v)                        (((v) << 18) & 0x40000)
+#define BF_LCDIF_CTRL_DATA_SELECT_V(v)                      ((BV_LCDIF_CTRL_DATA_SELECT__##v << 18) & 0x40000)
+#define BP_LCDIF_CTRL_WORD_LENGTH                           17
+#define BM_LCDIF_CTRL_WORD_LENGTH                           0x20000
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT                   0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT                    0x1
+#define BF_LCDIF_CTRL_WORD_LENGTH(v)                        (((v) << 17) & 0x20000)
+#define BF_LCDIF_CTRL_WORD_LENGTH_V(v)                      ((BV_LCDIF_CTRL_WORD_LENGTH__##v << 17) & 0x20000)
+#define BP_LCDIF_CTRL_RUN                                   16
+#define BM_LCDIF_CTRL_RUN                                   0x10000
+#define BF_LCDIF_CTRL_RUN(v)                                (((v) << 16) & 0x10000)
+#define BP_LCDIF_CTRL_COUNT                                 0
+#define BM_LCDIF_CTRL_COUNT                                 0xffff
+#define BF_LCDIF_CTRL_COUNT(v)                              (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_CTRL1
+ * Address: 0x10
+ * SCT: yes
+*/
+#define HW_LCDIF_CTRL1                                  (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x0))
+#define HW_LCDIF_CTRL1_SET                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x4))
+#define HW_LCDIF_CTRL1_CLR                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0x8))
+#define HW_LCDIF_CTRL1_TOG                              (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x10 + 0xc))
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT              16
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT              0xf0000
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v)           (((v) << 16) & 0xf0000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ_EN                  15
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN                  0x8000
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_EN(v)               (((v) << 15) & 0x8000)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                 14
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN                 0x4000
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_EN(v)              (((v) << 14) & 0x4000)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN            13
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN            0x2000
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(v)         (((v) << 13) & 0x2000)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                12
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN                0x1000
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(v)             (((v) << 12) & 0x1000)
+#define BP_LCDIF_CTRL1_OVERFLOW_IRQ                     11
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ                     0x800
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST         0x0
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST            0x1
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ(v)                  (((v) << 11) & 0x800)
+#define BF_LCDIF_CTRL1_OVERFLOW_IRQ_V(v)                ((BV_LCDIF_CTRL1_OVERFLOW_IRQ__##v << 11) & 0x800)
+#define BP_LCDIF_CTRL1_UNDERFLOW_IRQ                    10
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ                    0x400
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST        0x0
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST           0x1
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ(v)                 (((v) << 10) & 0x400)
+#define BF_LCDIF_CTRL1_UNDERFLOW_IRQ_V(v)               ((BV_LCDIF_CTRL1_UNDERFLOW_IRQ__##v << 10) & 0x400)
+#define BP_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ               9
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ               0x200
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST   0x0
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST      0x1
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(v)            (((v) << 9) & 0x200)
+#define BF_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_V(v)          ((BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__##v << 9) & 0x200)
+#define BP_LCDIF_CTRL1_VSYNC_EDGE_IRQ                   8
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ                   0x100
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST       0x0
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST          0x1
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ(v)                (((v) << 8) & 0x100)
+#define BF_LCDIF_CTRL1_VSYNC_EDGE_IRQ_V(v)              ((BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__##v << 8) & 0x100)
+#define BP_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS    5
+#define BM_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS    0xe0
+#define BF_LCDIF_CTRL1_READ_MODE_NUM_PACKED_SUBWORDS(v) (((v) << 5) & 0xe0)
+#define BP_LCDIF_CTRL1_FIRST_READ_DUMMY                 4
+#define BM_LCDIF_CTRL1_FIRST_READ_DUMMY                 0x10
+#define BF_LCDIF_CTRL1_FIRST_READ_DUMMY(v)              (((v) << 4) & 0x10)
+#define BP_LCDIF_CTRL1_LCD_CS_CTRL                      3
+#define BM_LCDIF_CTRL1_LCD_CS_CTRL                      0x8
+#define BF_LCDIF_CTRL1_LCD_CS_CTRL(v)                   (((v) << 3) & 0x8)
+#define BP_LCDIF_CTRL1_BUSY_ENABLE                      2
+#define BM_LCDIF_CTRL1_BUSY_ENABLE                      0x4
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED       0x0
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED        0x1
+#define BF_LCDIF_CTRL1_BUSY_ENABLE(v)                   (((v) << 2) & 0x4)
+#define BF_LCDIF_CTRL1_BUSY_ENABLE_V(v)                 ((BV_LCDIF_CTRL1_BUSY_ENABLE__##v << 2) & 0x4)
+#define BP_LCDIF_CTRL1_MODE86                           1
+#define BM_LCDIF_CTRL1_MODE86                           0x2
+#define BV_LCDIF_CTRL1_MODE86__8080_MODE                0x0
+#define BV_LCDIF_CTRL1_MODE86__6800_MODE                0x1
+#define BF_LCDIF_CTRL1_MODE86(v)                        (((v) << 1) & 0x2)
+#define BF_LCDIF_CTRL1_MODE86_V(v)                      ((BV_LCDIF_CTRL1_MODE86__##v << 1) & 0x2)
+#define BP_LCDIF_CTRL1_RESET                            0
+#define BM_LCDIF_CTRL1_RESET                            0x1
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW              0x0
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH             0x1
+#define BF_LCDIF_CTRL1_RESET(v)                         (((v) << 0) & 0x1)
+#define BF_LCDIF_CTRL1_RESET_V(v)                       ((BV_LCDIF_CTRL1_RESET__##v << 0) & 0x1)
+
+/**
+ * Register: HW_LCDIF_TIMING
+ * Address: 0x20
+ * SCT: no
+*/
+#define HW_LCDIF_TIMING                 (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x20))
+#define BP_LCDIF_TIMING_CMD_HOLD        24
+#define BM_LCDIF_TIMING_CMD_HOLD        0xff000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v)     (((v) << 24) & 0xff000000)
+#define BP_LCDIF_TIMING_CMD_SETUP       16
+#define BM_LCDIF_TIMING_CMD_SETUP       0xff0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v)    (((v) << 16) & 0xff0000)
+#define BP_LCDIF_TIMING_DATA_HOLD       8
+#define BM_LCDIF_TIMING_DATA_HOLD       0xff00
+#define BF_LCDIF_TIMING_DATA_HOLD(v)    (((v) << 8) & 0xff00)
+#define BP_LCDIF_TIMING_DATA_SETUP      0
+#define BM_LCDIF_TIMING_DATA_SETUP      0xff
+#define BF_LCDIF_TIMING_DATA_SETUP(v)   (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL0
+ * Address: 0x30
+ * SCT: yes
+*/
+#define HW_LCDIF_VDCTRL0                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x0))
+#define HW_LCDIF_VDCTRL0_SET                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x4))
+#define HW_LCDIF_VDCTRL0_CLR                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0x8))
+#define HW_LCDIF_VDCTRL0_TOG                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x30 + 0xc))
+#define BP_LCDIF_VDCTRL0_VSYNC_OEB                  29
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB                  0x20000000
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT    0x0
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT     0x1
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB(v)               (((v) << 29) & 0x20000000)
+#define BF_LCDIF_VDCTRL0_VSYNC_OEB_V(v)             ((BV_LCDIF_VDCTRL0_VSYNC_OEB__##v << 29) & 0x20000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_PRESENT             28
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT             0x10000000
+#define BF_LCDIF_VDCTRL0_ENABLE_PRESENT(v)          (((v) << 28) & 0x10000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_POL                  27
+#define BM_LCDIF_VDCTRL0_VSYNC_POL                  0x8000000
+#define BF_LCDIF_VDCTRL0_VSYNC_POL(v)               (((v) << 27) & 0x8000000)
+#define BP_LCDIF_VDCTRL0_HSYNC_POL                  26
+#define BM_LCDIF_VDCTRL0_HSYNC_POL                  0x4000000
+#define BF_LCDIF_VDCTRL0_HSYNC_POL(v)               (((v) << 26) & 0x4000000)
+#define BP_LCDIF_VDCTRL0_DOTCLK_POL                 25
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL                 0x2000000
+#define BF_LCDIF_VDCTRL0_DOTCLK_POL(v)              (((v) << 25) & 0x2000000)
+#define BP_LCDIF_VDCTRL0_ENABLE_POL                 24
+#define BM_LCDIF_VDCTRL0_ENABLE_POL                 0x1000000
+#define BF_LCDIF_VDCTRL0_ENABLE_POL(v)              (((v) << 24) & 0x1000000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          21
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT          0x200000
+#define BF_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(v)       (((v) << 21) & 0x200000)
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     20
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT     0x100000
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(v)  (((v) << 20) & 0x100000)
+#define BP_LCDIF_VDCTRL0_INTERLACE                  19
+#define BM_LCDIF_VDCTRL0_INTERLACE                  0x80000
+#define BF_LCDIF_VDCTRL0_INTERLACE(v)               (((v) << 19) & 0x80000)
+#define BP_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT    0
+#define BM_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT    0x3ff
+#define BF_LCDIF_VDCTRL0_DOTCLK_V_VALID_DATA_CNT(v) (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL1
+ * Address: 0x40
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL1                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x40))
+#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      20
+#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH      0xfff00000
+#define BF_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH(v)   (((v) << 20) & 0xfff00000)
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD           0
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD           0xfffff
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v)        (((v) << 0) & 0xfffff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL2
+ * Address: 0x50
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL2                            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x50))
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          23
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH          0xff800000
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v)       (((v) << 23) & 0xff800000)
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD               11
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD               0x7ff800
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v)            (((v) << 11) & 0x7ff800)
+#define BP_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT    0
+#define BM_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT    0x7ff
+#define BF_LCDIF_VDCTRL2_DOTCLK_H_VALID_DATA_CNT(v) (((v) << 0) & 0x7ff)
+
+/**
+ * Register: HW_LCDIF_VDCTRL3
+ * Address: 0x60
+ * SCT: no
+*/
+#define HW_LCDIF_VDCTRL3                        (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x60))
+#define BP_LCDIF_VDCTRL3_SYNC_SIGNALS_ON        24
+#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON        0x1000000
+#define BF_LCDIF_VDCTRL3_SYNC_SIGNALS_ON(v)     (((v) << 24) & 0x1000000)
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    12
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT    0xfff000
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) (((v) << 12) & 0xfff000)
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT      0x1ff
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v)   (((v) << 0) & 0x1ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL0
+ * Address: 0x70
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL0                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x70))
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT      20
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT      0x7ff00000
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v)   (((v) << 20) & 0x7ff00000)
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT    10
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT    0xffc00
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT       0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT       0x3ff
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v)    (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL1
+ * Address: 0x80
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL1                   (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x80))
+#define BP_LCDIF_DVICTRL1_F1_START_LINE     20
+#define BM_LCDIF_DVICTRL1_F1_START_LINE     0x3ff00000
+#define BF_LCDIF_DVICTRL1_F1_START_LINE(v)  (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL1_F1_END_LINE       10
+#define BM_LCDIF_DVICTRL1_F1_END_LINE       0xffc00
+#define BF_LCDIF_DVICTRL1_F1_END_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL1_F2_START_LINE     0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE     0x3ff
+#define BF_LCDIF_DVICTRL1_F2_START_LINE(v)  (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL2
+ * Address: 0x90
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL2                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0x90))
+#define BP_LCDIF_DVICTRL2_F2_END_LINE               20
+#define BM_LCDIF_DVICTRL2_F2_END_LINE               0x3ff00000
+#define BF_LCDIF_DVICTRL2_F2_END_LINE(v)            (((v) << 20) & 0x3ff00000)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE       10
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE       0xffc00
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v)    (((v) << 10) & 0xffc00)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DVICTRL3
+ * Address: 0xa0
+ * SCT: no
+*/
+#define HW_LCDIF_DVICTRL3                           (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xa0))
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE       16
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE       0x3ff0000
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v)    (((v) << 16) & 0x3ff0000)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE         0x3ff
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v)      (((v) << 0) & 0x3ff)
+
+/**
+ * Register: HW_LCDIF_DATA
+ * Address: 0xb0
+ * SCT: no
+*/
+#define HW_LCDIF_DATA               (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xb0))
+#define BP_LCDIF_DATA_DATA_THREE    24
+#define BM_LCDIF_DATA_DATA_THREE    0xff000000
+#define BF_LCDIF_DATA_DATA_THREE(v) (((v) << 24) & 0xff000000)
+#define BP_LCDIF_DATA_DATA_TWO      16
+#define BM_LCDIF_DATA_DATA_TWO      0xff0000
+#define BF_LCDIF_DATA_DATA_TWO(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_DATA_DATA_ONE      8
+#define BM_LCDIF_DATA_DATA_ONE      0xff00
+#define BF_LCDIF_DATA_DATA_ONE(v)   (((v) << 8) & 0xff00)
+#define BP_LCDIF_DATA_DATA_ZERO     0
+#define BM_LCDIF_DATA_DATA_ZERO     0xff
+#define BF_LCDIF_DATA_DATA_ZERO(v)  (((v) << 0) & 0xff)
+
+/**
+ * Register: HW_LCDIF_STAT
+ * Address: 0xc0
+ * SCT: no
+*/
+#define HW_LCDIF_STAT                       (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xc0))
+#define BP_LCDIF_STAT_PRESENT               31
+#define BM_LCDIF_STAT_PRESENT               0x80000000
+#define BF_LCDIF_STAT_PRESENT(v)            (((v) << 31) & 0x80000000)
+#define BP_LCDIF_STAT_DMA_REQ               30
+#define BM_LCDIF_STAT_DMA_REQ               0x40000000
+#define BF_LCDIF_STAT_DMA_REQ(v)            (((v) << 30) & 0x40000000)
+#define BP_LCDIF_STAT_RXFIFO_FULL           29
+#define BM_LCDIF_STAT_RXFIFO_FULL           0x20000000
+#define BF_LCDIF_STAT_RXFIFO_FULL(v)        (((v) << 29) & 0x20000000)
+#define BP_LCDIF_STAT_RXFIFO_EMPTY          28
+#define BM_LCDIF_STAT_RXFIFO_EMPTY          0x10000000
+#define BF_LCDIF_STAT_RXFIFO_EMPTY(v)       (((v) << 28) & 0x10000000)
+#define BP_LCDIF_STAT_TXFIFO_FULL           27
+#define BM_LCDIF_STAT_TXFIFO_FULL           0x8000000
+#define BF_LCDIF_STAT_TXFIFO_FULL(v)        (((v) << 27) & 0x8000000)
+#define BP_LCDIF_STAT_TXFIFO_EMPTY          26
+#define BM_LCDIF_STAT_TXFIFO_EMPTY          0x4000000
+#define BF_LCDIF_STAT_TXFIFO_EMPTY(v)       (((v) << 26) & 0x4000000)
+#define BP_LCDIF_STAT_BUSY                  25
+#define BM_LCDIF_STAT_BUSY                  0x2000000
+#define BF_LCDIF_STAT_BUSY(v)               (((v) << 25) & 0x2000000)
+#define BP_LCDIF_STAT_DVI_CURRENT_FIELD     24
+#define BM_LCDIF_STAT_DVI_CURRENT_FIELD     0x1000000
+#define BF_LCDIF_STAT_DVI_CURRENT_FIELD(v)  (((v) << 24) & 0x1000000)
+
+/**
+ * Register: HW_LCDIF_VERSION
+ * Address: 0xd0
+ * SCT: no
+*/
+#define HW_LCDIF_VERSION            (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xd0))
+#define BP_LCDIF_VERSION_MAJOR      24
+#define BM_LCDIF_VERSION_MAJOR      0xff000000
+#define BF_LCDIF_VERSION_MAJOR(v)   (((v) << 24) & 0xff000000)
+#define BP_LCDIF_VERSION_MINOR      16
+#define BM_LCDIF_VERSION_MINOR      0xff0000
+#define BF_LCDIF_VERSION_MINOR(v)   (((v) << 16) & 0xff0000)
+#define BP_LCDIF_VERSION_STEP       0
+#define BM_LCDIF_VERSION_STEP       0xffff
+#define BF_LCDIF_VERSION_STEP(v)    (((v) << 0) & 0xffff)
+
+/**
+ * Register: HW_LCDIF_DEBUG0
+ * Address: 0xe0
+ * SCT: no
+*/
+#define HW_LCDIF_DEBUG0                             (*(volatile unsigned long *)(REGS_LCDIF_BASE + 0xe0))
+#define BP_LCDIF_DEBUG0_STREAMING_END_DETECTED      31
+#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED      0x80000000
+#define BF_LCDIF_DEBUG0_STREAMING_END_DETECTED(v)   (((v) << 31) & 0x80000000)
+#define BP_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     30
+#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT     0x40000000
+#define BF_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT(v)  (((v) << 30) & 0x40000000)
+#define BP_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         29
+#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG         0x20000000
+#define BF_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG(v)      (((v) << 29) & 0x20000000)
+#define BP_LCDIF_DEBUG0_DMACMDKICK                  28
+#define BM_LCDIF_DEBUG0_DMACMDKICK                  0x10000000
+#define BF_LCDIF_DEBUG0_DMACMDKICK(v)               (((v) << 28) & 0x10000000)
+#define BP_LCDIF_DEBUG0_ENABLE                      27
+#define BM_LCDIF_DEBUG0_ENABLE                      0x8000000
+#define BF_LCDIF_DEBUG0_ENABLE(v)                   (((v) << 27) & 0x8000000)
+#define BP_LCDIF_DEBUG0_HSYNC                       26
+#define BM_LCDIF_DEBUG0_HSYNC                       0x4000000
+#define BF_LCDIF_DEBUG0_HSYNC(v)                    (((v) << 26) & 0x4000000)
+#define BP_LCDIF_DEBUG0_VSYNC                       25
+#define BM_LCDIF_DEBUG0_VSYNC                       0x2000000
+#define BF_LCDIF_DEBUG0_VSYNC(v)                    (((v) << 25) & 0x2000000)
+#define BP_LCDIF_DEBUG0_CUR_FRAME_TX                24
+#define BM_LCDIF_DEBUG0_CUR_FRAME_TX                0x1000000
+#define BF_LCDIF_DEBUG0_CUR_FRAME_TX(v)             (((v) << 24) & 0x1000000)
+#define BP_LCDIF_DEBUG0_EMPTY_WORD                  23
+#define BM_LCDIF_DEBUG0_EMPTY_WORD                  0x800000
+#define BF_LCDIF_DEBUG0_EMPTY_WORD(v)               (((v) << 23) & 0x800000)
+#define BP_LCDIF_DEBUG0_CUR_STATE                   16
+#define BM_LCDIF_DEBUG0_CUR_STATE                   0x7f0000
+#define BF_LCDIF_DEBUG0_CUR_STATE(v)                (((v) << 16) & 0x7f0000)
+#define BP_LCDIF_DEBUG0_DATA_COUNT                  0
+#define BM_LCDIF_DEBUG0_DATA_COUNT                  0xffff
+#define BF_LCDIF_DEBUG0_DATA_COUNT(v)               (((v) << 0) & 0xffff)
+
+#endif /* __HEADERGEN__STMP3700__LCDIF__H__ */