diff options
author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-13 19:03:33 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-15 22:27:34 +0200 |
commit | 017667c2dc9843eb5082e991f421c773636dcf36 (patch) | |
tree | 60432008dd3bc012ac60cbfa771305f6d894dd84 /firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h | |
parent | 97b9ade63945fd8b8261fb0cf1dd0aa225c1a319 (diff) | |
download | rockbox-017667c2dc9843eb5082e991f421c773636dcf36.tar.gz rockbox-017667c2dc9843eb5082e991f421c773636dcf36.zip |
imx233: generate register headers for stmp3600, stmp3700 and imx233
Change-Id: Ia87086f4f4f4ecbb844ffd869407b14ea2509934
Diffstat (limited to 'firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h')
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h | 355 |
1 files changed, 355 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h new file mode 100644 index 0000000000..a872606da4 --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3700/regs-gpiomon.h | |||
@@ -0,0 +1,355 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3700:3.2.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3700__GPIOMON__H__ | ||
24 | #define __HEADERGEN__STMP3700__GPIOMON__H__ | ||
25 | |||
26 | #define REGS_GPIOMON_BASE (0x8003c300) | ||
27 | |||
28 | #define REGS_GPIOMON_VERSION "3.2.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_GPIOMON_BANK0_DATAIN | ||
32 | * Address: 0 | ||
33 | * SCT: no | ||
34 | */ | ||
35 | #define HW_GPIOMON_BANK0_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x0)) | ||
36 | #define BP_GPIOMON_BANK0_DATAIN_DATA 0 | ||
37 | #define BM_GPIOMON_BANK0_DATAIN_DATA 0xffffffff | ||
38 | #define BF_GPIOMON_BANK0_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
39 | |||
40 | /** | ||
41 | * Register: HW_GPIOMON_BANK1_DATAIN | ||
42 | * Address: 0x10 | ||
43 | * SCT: no | ||
44 | */ | ||
45 | #define HW_GPIOMON_BANK1_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x10)) | ||
46 | #define BP_GPIOMON_BANK1_DATAIN_DATA 0 | ||
47 | #define BM_GPIOMON_BANK1_DATAIN_DATA 0xffffffff | ||
48 | #define BF_GPIOMON_BANK1_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
49 | |||
50 | /** | ||
51 | * Register: HW_GPIOMON_BANK2_DATAIN | ||
52 | * Address: 0x20 | ||
53 | * SCT: no | ||
54 | */ | ||
55 | #define HW_GPIOMON_BANK2_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x20)) | ||
56 | #define BP_GPIOMON_BANK2_DATAIN_DATA 0 | ||
57 | #define BM_GPIOMON_BANK2_DATAIN_DATA 0xffffffff | ||
58 | #define BF_GPIOMON_BANK2_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
59 | |||
60 | /** | ||
61 | * Register: HW_GPIOMON_BANK3_DATAIN | ||
62 | * Address: 0x30 | ||
63 | * SCT: no | ||
64 | */ | ||
65 | #define HW_GPIOMON_BANK3_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x30)) | ||
66 | #define BP_GPIOMON_BANK3_DATAIN_DATA 0 | ||
67 | #define BM_GPIOMON_BANK3_DATAIN_DATA 0xffffffff | ||
68 | #define BF_GPIOMON_BANK3_DATAIN_DATA(v) (((v) << 0) & 0xffffffff) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_GPIOMON_BANK0_DATAOUT | ||
72 | * Address: 0x40 | ||
73 | * SCT: yes | ||
74 | */ | ||
75 | #define HW_GPIOMON_BANK0_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x0)) | ||
76 | #define HW_GPIOMON_BANK0_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x4)) | ||
77 | #define HW_GPIOMON_BANK0_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x8)) | ||
78 | #define HW_GPIOMON_BANK0_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0xc)) | ||
79 | #define BP_GPIOMON_BANK0_DATAOUT_DATA 0 | ||
80 | #define BM_GPIOMON_BANK0_DATAOUT_DATA 0xffffffff | ||
81 | #define BF_GPIOMON_BANK0_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
82 | |||
83 | /** | ||
84 | * Register: HW_GPIOMON_BANK1_DATAOUT | ||
85 | * Address: 0x50 | ||
86 | * SCT: yes | ||
87 | */ | ||
88 | #define HW_GPIOMON_BANK1_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x0)) | ||
89 | #define HW_GPIOMON_BANK1_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x4)) | ||
90 | #define HW_GPIOMON_BANK1_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x8)) | ||
91 | #define HW_GPIOMON_BANK1_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0xc)) | ||
92 | #define BP_GPIOMON_BANK1_DATAOUT_DATA 0 | ||
93 | #define BM_GPIOMON_BANK1_DATAOUT_DATA 0xffffffff | ||
94 | #define BF_GPIOMON_BANK1_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
95 | |||
96 | /** | ||
97 | * Register: HW_GPIOMON_BANK2_DATAOUT | ||
98 | * Address: 0x60 | ||
99 | * SCT: yes | ||
100 | */ | ||
101 | #define HW_GPIOMON_BANK2_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x0)) | ||
102 | #define HW_GPIOMON_BANK2_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x4)) | ||
103 | #define HW_GPIOMON_BANK2_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x8)) | ||
104 | #define HW_GPIOMON_BANK2_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0xc)) | ||
105 | #define BP_GPIOMON_BANK2_DATAOUT_DATA 0 | ||
106 | #define BM_GPIOMON_BANK2_DATAOUT_DATA 0xffffffff | ||
107 | #define BF_GPIOMON_BANK2_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
108 | |||
109 | /** | ||
110 | * Register: HW_GPIOMON_BANK3_DATAOUT | ||
111 | * Address: 0x70 | ||
112 | * SCT: yes | ||
113 | */ | ||
114 | #define HW_GPIOMON_BANK3_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x0)) | ||
115 | #define HW_GPIOMON_BANK3_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x4)) | ||
116 | #define HW_GPIOMON_BANK3_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x8)) | ||
117 | #define HW_GPIOMON_BANK3_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0xc)) | ||
118 | #define BP_GPIOMON_BANK3_DATAOUT_DATA 0 | ||
119 | #define BM_GPIOMON_BANK3_DATAOUT_DATA 0xffffffff | ||
120 | #define BF_GPIOMON_BANK3_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff) | ||
121 | |||
122 | /** | ||
123 | * Register: HW_GPIOMON_BANK0_DATAOEN | ||
124 | * Address: 0x80 | ||
125 | * SCT: yes | ||
126 | */ | ||
127 | #define HW_GPIOMON_BANK0_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x0)) | ||
128 | #define HW_GPIOMON_BANK0_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x4)) | ||
129 | #define HW_GPIOMON_BANK0_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x8)) | ||
130 | #define HW_GPIOMON_BANK0_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0xc)) | ||
131 | #define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0 | ||
132 | #define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
133 | #define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
134 | |||
135 | /** | ||
136 | * Register: HW_GPIOMON_BANK1_DATAOEN | ||
137 | * Address: 0x90 | ||
138 | * SCT: yes | ||
139 | */ | ||
140 | #define HW_GPIOMON_BANK1_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x0)) | ||
141 | #define HW_GPIOMON_BANK1_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x4)) | ||
142 | #define HW_GPIOMON_BANK1_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x8)) | ||
143 | #define HW_GPIOMON_BANK1_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0xc)) | ||
144 | #define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0 | ||
145 | #define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
146 | #define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
147 | |||
148 | /** | ||
149 | * Register: HW_GPIOMON_BANK2_DATAOEN | ||
150 | * Address: 0xa0 | ||
151 | * SCT: yes | ||
152 | */ | ||
153 | #define HW_GPIOMON_BANK2_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x0)) | ||
154 | #define HW_GPIOMON_BANK2_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x4)) | ||
155 | #define HW_GPIOMON_BANK2_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x8)) | ||
156 | #define HW_GPIOMON_BANK2_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0xc)) | ||
157 | #define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0 | ||
158 | #define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
159 | #define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
160 | |||
161 | /** | ||
162 | * Register: HW_GPIOMON_BANK3_DATAOEN | ||
163 | * Address: 0xb0 | ||
164 | * SCT: yes | ||
165 | */ | ||
166 | #define HW_GPIOMON_BANK3_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x0)) | ||
167 | #define HW_GPIOMON_BANK3_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x4)) | ||
168 | #define HW_GPIOMON_BANK3_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x8)) | ||
169 | #define HW_GPIOMON_BANK3_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0xc)) | ||
170 | #define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0 | ||
171 | #define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0xffffffff | ||
172 | #define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff) | ||
173 | |||
174 | /** | ||
175 | * Register: HW_GPIOMON_CTRL | ||
176 | * Address: 0xc0 | ||
177 | * SCT: yes | ||
178 | */ | ||
179 | #define HW_GPIOMON_CTRL (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x0)) | ||
180 | #define HW_GPIOMON_CTRL_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x4)) | ||
181 | #define HW_GPIOMON_CTRL_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x8)) | ||
182 | #define HW_GPIOMON_CTRL_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0xc)) | ||
183 | #define BP_GPIOMON_CTRL_RSRVD 4 | ||
184 | #define BM_GPIOMON_CTRL_RSRVD 0xfffffff0 | ||
185 | #define BF_GPIOMON_CTRL_RSRVD(v) (((v) << 4) & 0xfffffff0) | ||
186 | #define BP_GPIOMON_CTRL_PINMUX_ALT_RESET 3 | ||
187 | #define BM_GPIOMON_CTRL_PINMUX_ALT_RESET 0x8 | ||
188 | #define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v) (((v) << 3) & 0x8) | ||
189 | #define BP_GPIOMON_CTRL_OEN_8MA 2 | ||
190 | #define BM_GPIOMON_CTRL_OEN_8MA 0x4 | ||
191 | #define BF_GPIOMON_CTRL_OEN_8MA(v) (((v) << 2) & 0x4) | ||
192 | #define BP_GPIOMON_CTRL_OEN_4MA 1 | ||
193 | #define BM_GPIOMON_CTRL_OEN_4MA 0x2 | ||
194 | #define BF_GPIOMON_CTRL_OEN_4MA(v) (((v) << 1) & 0x2) | ||
195 | #define BP_GPIOMON_CTRL_OEN_NAND 0 | ||
196 | #define BM_GPIOMON_CTRL_OEN_NAND 0x1 | ||
197 | #define BF_GPIOMON_CTRL_OEN_NAND(v) (((v) << 0) & 0x1) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK0 | ||
201 | * Address: 0xd0 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_GPIOMON_ALT1_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x0)) | ||
205 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x4)) | ||
206 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x8)) | ||
207 | #define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0xc)) | ||
208 | #define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0 | ||
209 | #define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0xffffffff | ||
210 | #define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
211 | |||
212 | /** | ||
213 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK1 | ||
214 | * Address: 0xe0 | ||
215 | * SCT: yes | ||
216 | */ | ||
217 | #define HW_GPIOMON_ALT1_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x0)) | ||
218 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x4)) | ||
219 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x8)) | ||
220 | #define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0xc)) | ||
221 | #define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0 | ||
222 | #define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0xffffffff | ||
223 | #define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
224 | |||
225 | /** | ||
226 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK2 | ||
227 | * Address: 0xf0 | ||
228 | * SCT: yes | ||
229 | */ | ||
230 | #define HW_GPIOMON_ALT1_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x0)) | ||
231 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x4)) | ||
232 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x8)) | ||
233 | #define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0xc)) | ||
234 | #define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0 | ||
235 | #define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0xffffffff | ||
236 | #define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
237 | |||
238 | /** | ||
239 | * Register: HW_GPIOMON_ALT1_PINMUX_BANK3 | ||
240 | * Address: 0x100 | ||
241 | * SCT: yes | ||
242 | */ | ||
243 | #define HW_GPIOMON_ALT1_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x0)) | ||
244 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x4)) | ||
245 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x8)) | ||
246 | #define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0xc)) | ||
247 | #define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0 | ||
248 | #define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0xffffffff | ||
249 | #define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
250 | |||
251 | /** | ||
252 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK0 | ||
253 | * Address: 0x110 | ||
254 | * SCT: yes | ||
255 | */ | ||
256 | #define HW_GPIOMON_ALT2_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x0)) | ||
257 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x4)) | ||
258 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x8)) | ||
259 | #define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0xc)) | ||
260 | #define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0 | ||
261 | #define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0xffffffff | ||
262 | #define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
263 | |||
264 | /** | ||
265 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK1 | ||
266 | * Address: 0x120 | ||
267 | * SCT: yes | ||
268 | */ | ||
269 | #define HW_GPIOMON_ALT2_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x0)) | ||
270 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x4)) | ||
271 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x8)) | ||
272 | #define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0xc)) | ||
273 | #define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0 | ||
274 | #define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0xffffffff | ||
275 | #define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
276 | |||
277 | /** | ||
278 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK2 | ||
279 | * Address: 0x130 | ||
280 | * SCT: yes | ||
281 | */ | ||
282 | #define HW_GPIOMON_ALT2_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x0)) | ||
283 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x4)) | ||
284 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x8)) | ||
285 | #define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0xc)) | ||
286 | #define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0 | ||
287 | #define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0xffffffff | ||
288 | #define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
289 | |||
290 | /** | ||
291 | * Register: HW_GPIOMON_ALT2_PINMUX_BANK3 | ||
292 | * Address: 0x140 | ||
293 | * SCT: yes | ||
294 | */ | ||
295 | #define HW_GPIOMON_ALT2_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x0)) | ||
296 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x4)) | ||
297 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x8)) | ||
298 | #define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0xc)) | ||
299 | #define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0 | ||
300 | #define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0xffffffff | ||
301 | #define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
302 | |||
303 | /** | ||
304 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK0 | ||
305 | * Address: 0x150 | ||
306 | * SCT: yes | ||
307 | */ | ||
308 | #define HW_GPIOMON_ALT3_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x0)) | ||
309 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x4)) | ||
310 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x8)) | ||
311 | #define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0xc)) | ||
312 | #define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0 | ||
313 | #define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0xffffffff | ||
314 | #define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff) | ||
315 | |||
316 | /** | ||
317 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK1 | ||
318 | * Address: 0x160 | ||
319 | * SCT: yes | ||
320 | */ | ||
321 | #define HW_GPIOMON_ALT3_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x0)) | ||
322 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x4)) | ||
323 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x8)) | ||
324 | #define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0xc)) | ||
325 | #define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0 | ||
326 | #define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0xffffffff | ||
327 | #define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff) | ||
328 | |||
329 | /** | ||
330 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK2 | ||
331 | * Address: 0x170 | ||
332 | * SCT: yes | ||
333 | */ | ||
334 | #define HW_GPIOMON_ALT3_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x0)) | ||
335 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x4)) | ||
336 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x8)) | ||
337 | #define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0xc)) | ||
338 | #define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0 | ||
339 | #define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0xffffffff | ||
340 | #define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff) | ||
341 | |||
342 | /** | ||
343 | * Register: HW_GPIOMON_ALT3_PINMUX_BANK3 | ||
344 | * Address: 0x180 | ||
345 | * SCT: yes | ||
346 | */ | ||
347 | #define HW_GPIOMON_ALT3_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x0)) | ||
348 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x4)) | ||
349 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x8)) | ||
350 | #define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0xc)) | ||
351 | #define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0 | ||
352 | #define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0xffffffff | ||
353 | #define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff) | ||
354 | |||
355 | #endif /* __HEADERGEN__STMP3700__GPIOMON__H__ */ | ||